summaryrefslogtreecommitdiffstats
path: root/drivers/spi/spi-dw-core.c
Commit message (Expand)AuthorAgeFilesLines
* spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan2022-07-131-2/+3
* spi: dw: Add deferred DMA-channels setup supportSerge Semin2022-06-271-1/+4
* spi: dw: Propagate firmware nodeAndy Shevchenko2021-12-231-2/+2
* spi: dw: Replace DWC_HSSI capability with IP-core version checkerSerge Semin2021-11-161-4/+4
* spi: dw: Introduce Synopsys IP-core versions interfaceSerge Semin2021-11-161-0/+14
* spi: dw: Convert to using the Bitfield access macrosSerge Semin2021-11-161-12/+19
* spi: dw: Put the driver entities naming in orderSerge Semin2021-11-161-68/+70
* spi: dw: Discard redundant DW SSI Frame Formats enumerationSerge Semin2021-11-161-2/+2
* spi: dw: Add a symbols namespace for the core moduleSerge Semin2021-11-161-7/+7
* spi: dw: Add support for 32-bits max xfer sizeDamien Le Moal2020-12-091-7/+37
* spi: dw: Fix spi registration for controllers overriding CSLars Povlsen2020-11-251-1/+2
* spi: dw: Set transfer handler before unmasking the IRQsSerge Semin2020-11-171-2/+2
* spi: dw: Add poll-based SPI transfers supportSerge Semin2020-10-081-1/+39
* spi: dw: Introduce max mem-ops SPI bus frequency settingSerge Semin2020-10-081-1/+3
* spi: dw: Add memory operations supportSerge Semin2020-10-081-0/+301
* spi: dw: Add generic DW SSI status-check methodSerge Semin2020-10-081-9/+34
* spi: dw: Explicitly de-assert CS on SPI transfer completionSerge Semin2020-10-081-1/+1
* spi: dw: Discard chip enabling on DMA setup errorSerge Semin2020-10-081-3/+1
* spi: dw: Unmask IRQs after enabling the chipSerge Semin2020-10-081-2/+2
* spi: dw: Perform IRQ setup in a dedicated functionSerge Semin2020-10-081-18/+23
* spi: dw: Refactor IRQ-based SPI transfer procedureSerge Semin2020-10-081-9/+24
* spi: dw: Refactor data IO procedureSerge Semin2020-10-081-20/+17
* spi: dw: Add DW SPI controller config structureSerge Semin2020-10-081-12/+17
* spi: dw: Update Rx sample delay in the config functionSerge Semin2020-10-081-7/+6
* spi: dw: Simplify the SPI bus speed config procedureSerge Semin2020-10-081-13/+10
* spi: dw: Update SPI bus speed in a config functionSerge Semin2020-10-081-14/+14
* spi: dw: Detach SPI device specific CR0 config methodSerge Semin2020-10-081-13/+30
* spi: dw: Add DWC SSI capabilitySerge Semin2020-10-081-43/+37
* spi: dw: Use an explicit set_cs assignmentSerge Semin2020-10-081-4/+4
* spi: spi-dw: Remove extraneous lockingSerge Semin2020-09-291-12/+2
* spi: dw: Add KeemBay Master capabilitySerge Semin2020-09-291-0/+4
* spi: dw: Convert CS-override to DW SPI capabilitiesSerge Semin2020-09-291-2/+2
* spi: dw: Discard DW SSI chip type storagesSerge Semin2020-09-291-4/+2
* spi: dw: Disable all IRQs when controller is unusedSerge Semin2020-09-291-5/+5
* spi: dw: Initialize n_bytes before the memory barrierSerge Semin2020-09-291-1/+1
* spi: dw: Add support for RX sample delay registerLars Povlsen2020-09-081-0/+26
* Merge remote-tracking branch 'spi/for-5.8' into spi-nextMark Brown2020-05-301-1/+3
* spi: dw: Use regset32 DebugFS method to create regdump fileSerge Semin2020-05-291-60/+26
* spi: dw: Add core suffix to the DW APB SSI core source fileSerge Semin2020-05-291-0/+577
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 15:40:24 +0000