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path: root/drivers/spi/spi-meson-spicc.c
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* spi: meson-spicc: add spicc loopback modeXianwei Zhao2024-06-121-2/+4
| | | | | | | | | | Add spicc loopback mode for debugging convenience. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240612-spi_lbc-v1-1-d52e8c8011bd@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: set SPI clock flag CLK_SET_RATE_PARENTXianwei Zhao2024-06-101-6/+10
| | | | | | | | | | Add SPI clock flag CLK_SET_RATE_PARENT for using pclk as parent clock. This gives SPI more flexibility in frequency selection. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20240524-spi_pclk_setparent-v1-1-99e0ce70b66f@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Use devm_clk_get_*() helper function toMark Brown2023-09-111-28/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge series from Li Zetao <lizetao1@huawei.com>: Commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks") provides a new helper function for prepared and enabled clocks when a driver keeps a clock prepared (or enabled) during the whole lifetime of the driver. So where drivers get clocks and enable them immediately, it can be combined into a single function devm_clk_get_*(). Moreover, the unprepare and disable function has been registered to devm_clk_state, and before devm_clk_state is released, the clocks will be unprepareed and disable, so it is unnecessary to unprepare and disable clocks explicitly when remove drivers or in the error handling path.
| * spi: meson-spicc: Use helper function devm_clk_get_enabled()Li Zetao2023-09-111-27/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Li Zetao <lizetao1@huawei.com> Link: https://lore.kernel.org/r/20230823133938.1359106-16-lizetao1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: meson-spicc: switch to use modern nameYang Yingliang2023-09-111-45/+45
|/ | | | | | | | | | Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230823033003.3407403-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Explicitly include correct DT includesRob Herring2023-07-141-1/+0
| | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714174955.4064174-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Get rid of old SPI_MASTER_MUST_TX & SPI_MASTER_MUST_RXAndy Shevchenko2023-07-111-1/+1
| | | | | | | | | | Convert the users from SPI_MASTER_MUST_TX and/or SPI_MASTER_MUST_RX to SPI_CONTROLLER_MUST_TX and/or SPI_CONTROLLER_MUST_RX respectively and kill the not used anymore definitions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230710154932.68377-13-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Replace all spi->chip_select and spi->cs_gpiod references with function ↵Amit Kumar Mahapatra via Alsa-devel2023-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | call Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: Convert to platform remove callback returning voidUwe Kleine-König2023-03-061-4/+2
| | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230303172041.2103336-35-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge tag 'spi-v6.2' of ↵Linus Torvalds2022-12-131-1/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A busy enough release, but not for the core which has only seen very small updates. The biggest addition is the readdition of support for detailed configuration of the timings around chip selects. That had been removed for lack of use but there's been applications found for it on Atmel systems. Otherwise the updates are mostly feature additions and cleanups to existing drivers. Summary: - Provide a helper for getting device match data in a way that abstracts away which firmware interface is being used. - Re-add the spi_set_cs_timing() API for detailed configuration of the timing around chip select and support it on Atmel. - Support for MediaTek MT7986, Microchip PCI1xxxx, Nuvoton WPCM450 FIU and Socionext F_OSPI" * tag 'spi-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits) spi: dt-bindings: Convert Synquacer SPI to DT schema spi: spi-gpio: Don't set MOSI as an input if not 3WIRE mode spi: spi-mtk-nor: Add recovery mechanism for dma read timeout spi: spi-fsl-lpspi: add num-cs binding for lpspi spi: spi-fsl-lpspi: support multiple cs for lpspi spi: mtk-snfi: Add snfi support for MT7986 IC spi: spidev: mask SPI_CS_HIGH in SPI_IOC_RD_MODE spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver spi: dt-bindings: nuvoton,wpcm450-fiu: Fix warning in example (missing reg property) spi: dt-bindings: nuvoton,wpcm450-fiu: Fix error in example (bogus include) spi: mediatek: Enable irq when pdata is ready spi: spi-mtk-nor: Unify write buffer on/off spi: intel: Add support for SFDP opcode spi: intel: Take possible chip address into account in intel_spi_read/write_reg() spi: intel: Implement adjust_op_size() spi: intel: Use ->replacement_op in intel_spi_hw_cycle() spi: cadence: Drop obsolete dependency on COMPILE_TEST spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings spi: wpcm-fiu: Add direct map support ...
| * spi: meson-spicc: Use pinctrl to drive CLK line when idleAmjad Ouled-Ameur2022-10-211-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Link: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v4-2-0342d8e10c49@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: meson-spicc: fix do_div build error on non-arm64Neil Armstrong2022-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes : error: passing argument 1 of '__div64_32' from incompatible pointer type By passing an uint64_t as first variable to do_div(). Reported-by: kernel test robot <lkp@intel.com> Fixes: 04694e50020b ("spi: meson-spicc: move wait completion in driver to take bursts delay in account") Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20221027-b4-spicc-burst-delay-fix-v2-0-8cc2bab3417a@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* | spi: meson-spicc: move wait completion in driver to take bursts delay in accountNeil Armstrong2022-10-261-2/+22
|/ | | | | | | | | | | | | Some delay occurs between each bursts, thus the default delay is wrong and a timeout will occur with big enough transfers. The solution is to handle the timeout management in the driver and add some delay for each bursts in the timeout calculation. Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20221026-spicc-burst-delay-v1-0-1be5ffb7051a@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: make symbol 'meson_spicc_pow2_clk_ops' staticWei Yongjun2022-09-221-1/+1
| | | | | | | | | | | | | | The sparse tool complains as follows: drivers/spi/spi-meson-spicc.c:570:22: warning: symbol 'meson_spicc_pow2_clk_ops' was not declared. Should it be static? This symbol is not used outside of spi-meson-spicc.c, so marks it static. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20220922040807.1409540-1-weiyongjun@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: do not rely on busy flag in pow2 clk opsNeil Armstrong2022-09-081-3/+3
| | | | | | | | | | | | | | | | | | | | | Since [1], controller's busy flag isn't set anymore when the __spi_transfer_message_noqueue() is used instead of the __spi_pump_transfer_message() logic for spi_sync transfers. Since the pow2 clock ops were limited to only be available when a transfer is ongoing (between prepare_transfer_hardware and unprepare_transfer_hardware callbacks), the only way to track this down is to check for the controller cur_msg. [1] ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Fixes: 09992025dacd ("spi: meson-spicc: add local pow2 clock ops to preserve rate between messages") Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Reported-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220908121803.919943-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: add local pow2 clock ops to preserve rate between messagesNeil Armstrong2022-08-111-28/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), this resets the SPICC_CONREG register and notably the value set by the Common Clock Framework. This is problematic because: - the register value CCF can be different from the corresponding CCF cached rate - CCF is allowed to change the clock rate whenever the HW state This introduces: - local pow2 clock ops checking the HW state before allowing a clock operation - separation of legacy pow2 clock patch and new enhanced clock path - SPICC_CONREG datarate value is now value kepts across messages It has been checked that: - SPICC_CONREG datarate value is kept across messages - CCF is only allowed to change the SPICC_CONREG datarate value when busy - SPICC_CONREG datarate value is correct for each transfer This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") because we recalculated and wrote the rate for each xfer. Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220811134445.678446-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: add IRQ check in meson_spicc_probeMiaoqian Lin2022-01-261-0/+5
| | | | | | | | | | | | This check misses checking for platform_get_irq()'s call and may passes the negative error codes to devm_request_irq(), which takes unsigned IRQ #, causing it to fail with -EINVAL, overriding an original error code. Stop calling devm_request_irq() with invalid IRQ #s. Fixes: 454fa271bc4e ("spi: Add Meson SPICC driver") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220126110447.24549-1-linmq006@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: fix memory leak in meson_spicc_removeDongliang Mu2021-07-221-0/+2
| | | | | | | | | | | | In meson_spicc_probe, the error handling code needs to clean up master by calling spi_master_put, but the remove function does not have this function call. This will lead to memory leak of spicc->master. Reported-by: Dongliang Mu <mudongliangabcd@gmail.com> Fixes: 454fa271bc4e("spi: Add Meson SPICC driver") Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com> Link: https://lore.kernel.org/r/20210720100116.1438974-1-mudongliangabcd@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: fix memory leak in meson_spicc_probezpershuai2021-06-141-1/+1
| | | | | | | | | | when meson_spicc_clk_init returns failed, it should goto the out_clk label. Signed-off-by: zpershuai <zpershuai@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/1623562156-21995-1-git-send-email-zpershuai@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: fix a wrong goto jump for avoiding memory leak.zpershuai2021-06-141-2/+4
| | | | | | | | | | In meson_spifc_probe function, when enable the device pclk clock is error, it should use clk_disable_unprepare to release the core clock. Signed-off-by: zpershuai <zpershuai@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/1623562172-22056-1-git-send-email-zpershuai@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: spi-meson-spicc: Remove set but never used variable 'data' from ↵Lee Jones2020-07-171-3/+1
| | | | | | | | | | | | | | | | | | | | meson_spicc_reset_fifo() Looks like it hasn't ever been checked. Fixes the following W=1 kernel build warning(s): drivers/spi/spi-meson-spicc.c: In function ‘meson_spicc_reset_fifo’: drivers/spi/spi-meson-spicc.c:365:6: warning: variable ‘data’ set but not used [-Wunused-but-set-variable] 365 | u32 data; | ^~~~ Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: linux-amlogic@lists.infradead.org Link: https://lore.kernel.org/r/20200717135424.2442271-7-lee.jones@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: add support for Amlogic G12ANeil Armstrong2020-03-121-8/+46
| | | | | | | | | | | | Add support for the SPICC controllers on the Amlogic G12A SoCs family. The G12A SPICC controllers inherit from the AXG enhanced registers but takes an external pclk for the baud rate generator and can achieve up to 166MHz SCLK. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-10-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: adapt burst handling for G12A supportNeil Armstrong2020-03-121-79/+50
| | | | | | | | | | | | The G12A SPICC controller variant has a different FIFO size and doesn't handle the RX Half interrupt the same way as GXL & AXG variants. Thus simplify the burst management and take in account a variable FIFO size. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-8-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: setup IO line delayNeil Armstrong2020-03-121-1/+60
| | | | | | | | | Now the controller can support frequencies higher than 30MHz, we need the setup the I/O line delays in regard of the SPI clock frequency. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-7-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: add min sclk for each compatibleNeil Armstrong2020-03-121-1/+4
| | | | | | | | | | | The G12A SPICC controller variant takes the source clock from a specific clock instead of the bus clock. The minimal clock calculus won't work with the G12A support, thus add the minimal supported clock for each variant and pass this to the SPI core. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-6-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: support max 80MHz clockNeil Armstrong2020-03-121-6/+6
| | | | | | | | | | | | The SPICC controller in Meson-AXG is capable of running at 80M clock. The ASIC IP is improved and the clock is actually running higher than previous old SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20200312133131.26430-5-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: add a linear clock divider supportSunny Luo2020-03-121-40/+164
| | | | | | | | | | | | | | | The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20200312133131.26430-4-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: enhance output enable featureSunny Luo2020-03-121-2/+51
| | | | | | | | | | | | The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS signal lines through the idle state (between two transmission operation), which avoid the signals floating in unexpected state. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Link: https://lore.kernel.org/r/20200312133131.26430-3-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: remove unused variablesNeil Armstrong2020-03-121-2/+0
| | | | | | | | Remove unused variables from spicc data struct. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200312133131.26430-2-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: Use GPIO descriptorsLinus Walleij2019-12-161-23/+2
| | | | | | | | | | | | | Instead of grabbing GPIOs using the legacy interface and handling them in the setup callback, just let the core grab and use the GPIOs using descriptors. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20191205083915.27650-1-linus.walleij@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-09-041-3/+1
| | | | | | | | | | | Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20190904135918.25352-16-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-spicc: Fix error handling in meson_spicc_probe()Alexey Khoroshilov2018-05-021-3/+8
| | | | | | | | | | | If devm_spi_register_master() fails in meson_spicc_probe(), spicc->core is left undisabled. The patch fixes that. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: meson-axg: add SPICC driver supportSunny Luo2017-11-281-0/+1
| | | | | | | | | | Add new compatible string to support SPICC controller which found at Amlogic Meson-AXG SoC. This is aiming at adding a couple of enhanced feature patches. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* spi: Add Meson SPICC driverNeil Armstrong2017-05-241-0/+619
The SPICC hardware block on the Amlogic SoCs is Communication oriented and can do Full-Duplex 8- to 32-bit width SPI transfers up to 30MHz. The current driver only supportd the PIO transfer mode since the DMA seems broken on available hardware. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-22 00:35:57 +0000