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| * tools/power/turbostat: Remove PC7/PC9 support on ADL/RPLZhang Rui2023-09-271-6/+23
| | | | | | | | | | | | | | | | | | | | | | Compared with other platforms that share cnl_features, ADL/RPL don't have PC7/PC9. Clone a new platform feature set from cnl_features for ADL/RPL, with PC7/PC9 removed. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Enable MSR_CORE_C1_RES on recent Intel client platformsZhang Rui2023-09-271-0/+1
| | | | | | | | | | | | | | | | All recent Intel client platforms have MSR_CORE_C1_RES. Enable the support on these platforms, including CNL/ICL/LKF/RKL/TGL/ADL/RPL/MTL. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Introduce probe_pm_features()Zhang Rui2023-09-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | Feature probe has nothing to do with CPUID, thus it should not be in process_cpuids(). Introduce probe_pm_features() and move all feature probing functions into it. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate more probing related codeZhang Rui2023-09-271-20/+17
| | | | | | | | | | | | | | | | | | | | Relocate more feature probing code outside of process_cpuids() into the corresponding probing functions. This improves the readability of code and the turbostat output. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Reorder some functionsZhang Rui2023-09-271-107/+107
| | | | | | | | | | | | | | | | | | Reorder some functions to solve code depdency introduced by next patch. No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate thermal probing codeZhang Rui2023-09-271-5/+10
| | | | | | | | | | | | | | | | Introduce probe_thermal(), and move all thermal probing related code into it. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate lpi probing codeZhang Rui2023-09-271-16/+22
| | | | | | | | | | | | | | Introduce probe_lpi(), and move all lpi probing related code into it. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate graphics probing codeZhang Rui2023-09-271-11/+16
| | | | | | | | | | | | | | | | Introduce probe_graphics(), and move all graphics probing related code into it. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Rename rapl probing functionZhang Rui2023-09-271-4/+4
| | | | | | | | | | | | | | | | | | | | Rename rapl_probe() to probe_rapl() to be consistent with other probing function names. Probe rapl after probing uncore frequency. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Rename uncore probing functionZhang Rui2023-09-271-3/+3
| | | | | | | | | | | | | | | | | | | | Rename intel_uncore_frequency_probe() to probe_intel_uncore_frequency() to be consistent with other probing function names. Probe uncore frequency right after probing cstates. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate pstate probing codeZhang Rui2023-09-271-18/+21
| | | | | | | | | | | | | | | | Introduce probe_pstates() and move all pstate probing related code into it. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Relocate cstate probing codeZhang Rui2023-09-271-19/+31
| | | | | | | | | | | | | | | | | | | | | | | | Move all cstate probing related code into probe_cstates(). Note that dump_platform_info() actually dumps both MSR_PLATFORM_INFO and MSR_IA32_POWER_CTL. MSR_PLATFORM_INFO is for pstate and MSR_IA32_POWER_CTL is for cstate. So split dump_platform_info() and dump MSR_IA32_POWER_CTL in probe_cstates(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Improve probe_platform_features() logicZhang Rui2023-09-271-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMD/Hygon platforms that don't have RAPL use 'amd_features' to describe the platform features. Unknown Intel platforms use 'default_features' to describe the platform features. As none of the platform feature is set for 'amd_features' or 'default_features', there is no need to maintain both of them. Remove 'amd_features' structure and improve the logic in probe_platform_features(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Delete intel_model_duplicates()Zhang Rui2023-09-271-59/+0
| | | | | | | | | | | | | | | | | | | | Now CPU model checks have been cleaned up, no code depends on the duplicated CPU model value. Delete intel_model_duplicates(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract cstate prewake bit supportZhang Rui2023-09-271-43/+4
| | | | | | | | | | | | | | | | | | Abstract cstate prewake bit support. Delete is_icx()/is_spr() CPU model checks. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract aperf/mperf multiplier supportZhang Rui2023-09-271-23/+3
| | | | | | | | | | | | | | | | | | Abstract aperf/mperf multiplier support. Delete is_knl() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract extended cstate MSRs supportZhang Rui2023-09-271-25/+4
| | | | | | | | | | | | | | | | | | | | | | Abstract the support for MSR_PKG_WEIGHTED_CORE_C0_RES, MSR_PKG_ANY_CORE_C0_RES, MSR_PKG_ANY_GFXE_C0_RES and MSR_PKG_BOTH_CORE_GFXE_C0_RES. Delete has_skl_msrs() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract MSR_KNL_CORE_C6_RESIDENCY supportZhang Rui2023-09-271-4/+4
| | | | | | | | | | | | | | Abstract the support for MSR_KNL_CORE_C6_RESIDENCY. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract MSR_ATOM_PKG_C6_RESIDENCY supportZhang Rui2023-09-271-19/+4
| | | | | | | | | | | | | | | | | | Abstract the support for MSR_ATOM_PKG_C6_RESIDENCY. Delete is_slm() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract MSR_CC6/MC6_DEMOTION_POLICY_CONFIG supportZhang Rui2023-09-271-23/+6
| | | | | | | | | | | | | | | | | | Abstract the support for MSR_CC6/MC6_DEMOTION_POLICY_CONFIG. Delete has_slv_msrs() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract MSR_MODULE_C6_RES_MS supportZhang Rui2023-09-271-2/+4
| | | | | | | | | | | | | | Abstract MSR_MODULE_C6_RES_MS support. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract MSR_CORE_C1_RES supportZhang Rui2023-09-271-24/+6
| | | | | | | | | | | | | | | | | | Abstract the support for MSR_CORE_C1_RES. Delete is_dnv() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract IRTL supportZhang Rui2023-09-271-46/+26
| | | | | | | | | | | | | | | | | | Abstract the support for MSR_PKGC3/PKGC6/PKGC7/PKGC8/PKGC9/PKGC10_IRTL. Delete has_snb_msrs() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Use fine grained IRTL outputZhang Rui2023-09-271-63/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | It is pointless to dump the IRTL register for a package cstate that is not supported by the platform. Print IRTL only for states that are available in platform->supported_cstates. Delete has_c8910_msrs() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for is_slm()/is_knl()/is_cnl()/is_ehl() ↵Zhang Rui2023-09-271-39/+5
| | | | | | | | | | | | | | | | | | | | | | models Disable CC3 for is_slm()/is_knl()/is_cnl()/is_ehl() models. Delete is_cnl()/is_ehl() CPU model checks. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for has_c8910_msrs() modelsZhang Rui2023-09-271-15/+7
| | | | | | | | | | | | | | Enable PC8/PC9/PC10 for has_c8910_msrs() models. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for is_bdx() modelsZhang Rui2023-09-271-21/+1
| | | | | | | | | | | | | | | | | | Disable CC7/PC7 for is_bdx() models. Delete is_bdx() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for is_skx()/is_icx()/is_spr() modelsZhang Rui2023-09-271-25/+3
| | | | | | | | | | | | | | | | | | Disable CC3/CC7/PC3/PC7 for is_skx()/is_icx()/is_spr() models. Delete is_skx() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for is_dnv() modelsZhang Rui2023-09-271-6/+1
| | | | | | | | | | | | | | Enable CC1 and disable CC3/CC7/PC3/PC7 for is_dnv() models. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for is_jvl() modelsZhang Rui2023-09-271-24/+1
| | | | | | | | | | | | | | | | | | Disable CC3/CC7/PC2/PC3/PC6/PC7 for is_jvl() models. Delete is_jvl() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for has_slv_msrs() modelsZhang Rui2023-09-271-5/+1
| | | | | | | | | | | | | | Disable PC2/PC3/PC7 and enable PC6 for has_slv_msrs() models. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for has_snb_msrs() modelsZhang Rui2023-09-271-25/+21
| | | | | | | | | | | | | | Enable PC7 for has_snb_msrs() models. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for models with .cst_limit setZhang Rui2023-09-271-31/+27
| | | | | | | | | | | | | | | | Enable PC3/PC6 for platforms with .cst_limit set because package cstates are guarded by pkg_cstate_limit. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for has_snb_msrs() modelsZhang Rui2023-09-271-26/+21
| | | | | | | | | | | | | | Enable CC7 and PC2 for has_snb_msrs() models. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Adjust cstate for models with .has_nhm_msrs setZhang Rui2023-09-271-5/+28
| | | | | | | | | | | | | | Enable CC1/CC3/CC6 for platforms with .has_nhm_msrs set. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Add skeleton support for cstate enumerationZhang Rui2023-09-271-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | Add skeleton support for cstate enumeration. Note that the previous logic may override the cstate setting for multiple times for different reasons. The conversion to new cstate enumeration must be done step by step following the previous code order strictly. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract TSC tweak supportZhang Rui2023-09-271-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On some models, the CPU base frequency is different from the TSC frequency, and the aperf/mperf counters are running at CPU base frequency instead of TSC frequency. Abstract support for TSC tweak. Given that tsc_tweak depends on base_hz, move the code to probe_bclk() after base_hz is available. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Remove unused family/model parameters for RAPL functionsZhang Rui2023-09-271-16/+10
| | | | | | | | | | | | | | | | RAPL probing can be done without family/model checking. Remove these parameters in rapl probe functions. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract hardcoded TDP valueZhang Rui2023-09-271-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | Different hardcoded TDP values are used when TDP can not be retrieved from the hardware. Abstract hardcoded TDP value. Delete CPU model checks in get_tdp_intel(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract fixed DRAM Energy unit supportZhang Rui2023-09-271-21/+10
| | | | | | | | | | | | | | | | | | Abstract the support for fixed Dram domain energy unit. Delete rapl_dram_energy_units_probe() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract RAPL divisor supportZhang Rui2023-09-271-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | INTEL_FAM6_ATOM_SILVERMONT model needs a divisor to convert the raw Energy Units value from MSR_RAPL_POWER_UNIT. Abstract the support for RAPL divisor. Delete CPU model check in rapl_probe_intel(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract Per Core RAPL supportZhang Rui2023-09-271-13/+11
| | | | | | | | | | | | | | Abstract the support for Per Core RAPL. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract RAPL MSRs supportZhang Rui2023-09-271-104/+85
| | | | | | | | | | | | | | | | | | Abstract the support for RAPL MSRs. Delete CPU model checks in rapl_probe_intel(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Simplify the logic for RAPL enumerationZhang Rui2023-09-271-77/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The support for each RAPL domains, as well as the support for the perf status of each RAPL domains, can be detected by checking the availabilities of the corresponding RAPL MSRs. Change the code accordingly and remove the hardcoded logic for each model. Note that this also fixes the INTEL_FAM6_ATOM_TREMONT model, which has RAPL_PKG_PERF_STATUS and MSR_DRAM_PERF_STATUS but doesn't have BIC_PKG__ and BIC_RAM__ set. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Redefine RAPL macrosZhang Rui2023-09-271-57/+45
| | | | | | | | | | | | | | Redefine RAPL macros to make the code more readable. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract hardcoded Crystal Clock frequencyZhang Rui2023-09-271-15/+6
| | | | | | | | | | | | | | | | | | | | Abstract the support for hardcoded Crystal Clock frequency, which is used when crystal clock is not available from CPUID.15. Delete CPU model checks in process_cpuid(). Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract Automatic Cstate Conversion supportZhang Rui2023-09-271-15/+4
| | | | | | | | | | | | | | | | | | | | Abstract the support for AUTOMATIC_CSTATE_CONVERSION bit in MSR_PKG_CST_CONFIG_CONTROL. Delete automatic_cstate_conversion_probe() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract Perf Limit Reasons MSRs supportZhang Rui2023-09-271-29/+15
| | | | | | | | | | | | | | | | | | Abstract the support for MSR_CORE/GFX/RING_PERF_LIMIT_REASONS MSRs. Delete perf_limit_reasons_probe() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract TCC Offset bits supportZhang Rui2023-09-271-41/+12
| | | | | | | | | | | | | | | | | | | | Abstract the support for different TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET. Delete check_tcc_offset() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
| * tools/power/turbostat: Abstract Config TDP MSRs supportZhang Rui2023-09-271-34/+20
| | | | | | | | | | | | | | | | | | | | Abstract the support for MSR_CONFIG_TDP_NOMINAL/LEVEL_1/LEVEL_2/CONTROL and MSR_TURBO_ACTIVATION_RATIO. Delete has_config_tdp() CPU model check. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
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