summaryrefslogtreecommitdiffstats
path: root/tools/testing/cxl
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'for-6.8/cxl-cper' into for-6.8/cxlDan Williams2024-01-091-70/+93
|\
| * cxl/events: Create a CXL event unionIra Weiny2024-01-091-13/+18
| * cxl/events: Separate UUID from event structuresIra Weiny2024-01-091-54/+75
| * cxl/events: Create common event UUID definesIra Weiny2024-01-091-6/+3
* | tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devicesDave Jiang2023-12-221-0/+4
* | cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang2023-12-221-0/+1
|/
* cxl: Add cxl_num_decoders_committed() usage to cxl_testDave Jiang2023-12-043-2/+11
* Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams2023-10-311-3/+1
|\
| * cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter2023-10-271-3/+1
* | tools/testing/cxl: Slow down the mock firmware transferVishal Verma2023-10-271-0/+1
* | cxl/region: Fix x1 root-decoder granularity calculationsJim Harris2023-10-271-1/+1
* | tools/testing/cxl: Add 'sanitize notifier' supportDan Williams2023-10-091-1/+67
* | tools/testing/cxl: Make cxl_memdev_state available to other command emulationDan Williams2023-10-091-3/+3
* | cxl/pci: Clarify devm host for memdev relative setupDan Williams2023-10-061-2/+2
|/
* tools/testing/cxl: Remove unused SZ_512G macroXiao Yang2023-07-201-4/+0
* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-254-35/+45
|\
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-252-15/+15
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-1/+3
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-254-21/+29
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-0/+1
|\ \
| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+1
| |/
* | Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams2023-06-254-104/+79
|\ \
| * | Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams2023-06-252-16/+0
| * | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-3/+3
| * | cxl/mbox: Move mailbox related driver state to its own data structureDan Williams2023-06-251-19/+24
| * | tools/testing/cxl: Remove unused @cxlds argumentDan Williams2023-06-251-47/+39
| |/
* | Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams2023-06-251-9/+183
|\ \
| * | tools/testing/cxl: add firmware update emulation to CXL memdevsVishal Verma2023-06-251-0/+160
| * | tools/testing/cxl: Use named effects for the Command Effect LogVishal Verma2023-06-251-9/+23
| * | tools/testing/cxl: Fix command effects for inject/clear poisonVishal Verma2023-06-251-2/+2
| |/
* | cxl/test: Add Secure Erase opcode supportDavidlohr Bueso2023-06-251-0/+27
* | cxl/test: Add Sanitize opcode supportDavidlohr Bueso2023-06-251-0/+25
|/
* cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang2023-05-181-0/+1
* cxl/port: Enable the HDM decoder capability for switch portsDan Williams2023-05-182-0/+16
* tools/testing/cxl: Use DEFINE_STATIC_SRCU()Dan Williams2023-05-131-1/+1
* cxl/test: Add mock test for set_timestampDavidlohr Bueso2023-04-241-0/+24
* tools/testing/cxl: Require CONFIG_DEBUG_FSAlison Schofield2023-04-231-0/+1
* tools/testing/cxl: Add a sysfs attr to test poison inject limitsAlison Schofield2023-04-231-4/+48
* tools/testing/cxl: Use injected poison for get poison listAlison Schofield2023-04-231-19/+43
* tools/testing/cxl: Mock the Clear Poison mailbox commandAlison Schofield2023-04-231-0/+36
* tools/testing/cxl: Mock the Inject Poison mailbox commandAlison Schofield2023-04-231-0/+77
* tools/testing/cxl: Mock support for Get Poison ListAlison Schofield2023-04-231-0/+42
* Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams2023-02-144-12/+37
|\
| * cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang2023-02-143-5/+9
| * cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang2023-02-143-5/+8
| * cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang2023-02-142-2/+20
* | Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-101-10/+137
|\ \
| * | tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams2023-02-101-10/+137
* | | Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams2023-02-072-1/+353
|\ \ \
| * | | cxl/test: Simulate event log overflowIra Weiny2023-01-261-1/+49