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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm crypto engine driver
maintainers:
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
description:
This document defines the binding for the QCE crypto
controller found on Qualcomm parts.
properties:
compatible:
const: qcom,crypto-v5.1
reg:
maxItems: 1
clocks:
items:
- description: iface clocks register interface.
- description: bus clocks data transfer interface.
- description: core clocks rest of the crypto block.
clock-names:
items:
- const: iface
- const: bus
- const: core
iommus:
minItems: 1
maxItems: 8
description:
phandle to apps_smmu node with sid mask.
interconnects:
maxItems: 1
description:
Interconnect path between qce crypto and main memory.
interconnect-names:
const: memory
dmas:
items:
- description: DMA specifiers for rx dma channel.
- description: DMA specifiers for tx dma channel.
dma-names:
items:
- const: rx
- const: tx
required:
- compatible
- reg
- clocks
- clock-names
- dmas
- dma-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
crypto-engine@fd45a000 {
compatible = "qcom,crypto-v5.1";
reg = <0xfd45a000 0x6000>;
clocks = <&gcc GCC_CE2_AHB_CLK>,
<&gcc GCC_CE2_AXI_CLK>,
<&gcc GCC_CE2_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x584 0x0011>,
<&apps_smmu 0x586 0x0011>,
<&apps_smmu 0x594 0x0011>,
<&apps_smmu 0x596 0x0011>;
};
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