summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
blob: a01d15a033176dad72497a84b9e03c90d295a12c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8650 Display DPU

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    const: qcom,sm8650-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display hf axi
      - description: Display MDSS ahb
      - description: Display lut
      - description: Display core
      - description: Display vsync

  clock-names:
    items:
      - const: nrt_bus
      - const: iface
      - const: lut
      - const: core
      - const: vsync

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sm8650-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&gcc_axi_clk>,
                 <&dispcc_ahb_clk>,
                 <&dispcc_mdp_lut_clk>,
                 <&dispcc_mdp_clk>,
                 <&dispcc_vsync_clk>;
        clock-names = "nrt_bus",
                      "iface",
                      "lut",
                      "core",
                      "vsync";

        assigned-clocks = <&dispcc_vsync_clk>;
        assigned-clock-rates = <19200000>;

        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmhpd RPMHPD_MMCX>;

        interrupt-parent = <&mdss>;
        interrupts = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dpu_intf1_out: endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                dpu_intf2_out: endpoint {
                    remote-endpoint = <&dsi1_in>;
                };
            };
        };

        mdp_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-200000000 {
                opp-hz = /bits/ 64 <200000000>;
                required-opps = <&rpmhpd_opp_low_svs>;
            };

            opp-325000000 {
                opp-hz = /bits/ 64 <325000000>;
                required-opps = <&rpmhpd_opp_svs>;
            };

            opp-375000000 {
                opp-hz = /bits/ 64 <375000000>;
                required-opps = <&rpmhpd_opp_svs_l1>;
            };

            opp-514000000 {
                opp-hz = /bits/ 64 <514000000>;
                required-opps = <&rpmhpd_opp_nom>;
            };
        };
    };
...