summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml
blob: c0a06abf851d30af454c01570fa4a1bac230715a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM8650 TLMM block

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm8650-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 105

  gpio-line-names:
    maxItems: 210

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8650-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8650-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm8650-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
                audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
                cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
                cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
                coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete,
                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
                ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1,
                gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0,
                i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
                i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
                i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
                i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c,
                jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
                mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0,
                nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n,
                pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
                qdss_gpio, qlink_big_enable, qlink_big_request,
                qlink_little_enable, qlink_little_request, qlink_wmss,
                qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0,
                qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,
                qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
                qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41,
                sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
                tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
                tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk,
                uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
                uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1,
                vsense_trigger_mirnat ]

    required:
      - pins

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f100000 {
        compatible = "qcom,sm8650-tlmm";
        reg = <0x0f100000 0x300000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 211>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-state {
            rx-pins {
                pins = "gpio60";
                function = "qup1_se7";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio61";
                function = "qup1_se7";
                bias-disable;
            };
        };
    };
...