1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
|
// SPDX-License-Identifier: GPL-2.0
#include <linux/err.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;
void mxc_set_cpu_type(unsigned int type)
{
__mxc_cpu_type = type;
}
void imx_set_soc_revision(unsigned int rev)
{
imx_soc_revision = rev;
}
unsigned int imx_get_soc_revision(void)
{
return imx_soc_revision;
}
void imx_print_silicon_rev(const char *cpu, int srev)
{
if (srev == IMX_CHIP_REVISION_UNKNOWN)
pr_info("CPU identified as %s, unknown revision\n", cpu);
else
pr_info("CPU identified as %s, silicon rev %d.%d\n",
cpu, (srev >> 4) & 0xf, srev & 0xf);
}
void __init imx_set_aips(void __iomem *base)
{
unsigned int reg;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
imx_writel(0x77777777, base + 0x0);
imx_writel(0x77777777, base + 0x4);
/*
* Set all OPACRx to be non-bufferable, to not require
* supervisor privilege level for access, allow for
* write access and untrusted master access.
*/
imx_writel(0x0, base + 0x40);
imx_writel(0x0, base + 0x44);
imx_writel(0x0, base + 0x48);
imx_writel(0x0, base + 0x4C);
reg = imx_readl(base + 0x50) & 0x00FFFFFF;
imx_writel(reg, base + 0x50);
}
void __init imx_aips_allow_unprivileged_access(
const char *compat)
{
void __iomem *aips_base_addr;
struct device_node *np;
for_each_compatible_node(np, NULL, compat) {
aips_base_addr = of_iomap(np, 0);
imx_set_aips(aips_base_addr);
}
}
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
struct device_node *root;
const char *soc_id;
int ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return NULL;
soc_dev_attr->family = "Freescale i.MX";
root = of_find_node_by_path("/");
ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
of_node_put(root);
if (ret)
goto free_soc;
switch (__mxc_cpu_type) {
case MXC_CPU_MX1:
soc_id = "i.MX1";
break;
case MXC_CPU_MX21:
soc_id = "i.MX21";
break;
case MXC_CPU_MX25:
soc_id = "i.MX25";
break;
case MXC_CPU_MX27:
soc_id = "i.MX27";
break;
case MXC_CPU_MX31:
soc_id = "i.MX31";
break;
case MXC_CPU_MX35:
soc_id = "i.MX35";
break;
case MXC_CPU_MX51:
soc_id = "i.MX51";
break;
case MXC_CPU_MX53:
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;
default:
soc_id = "Unknown";
}
soc_dev_attr->soc_id = soc_id;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_soc_revision >> 4) & 0xf,
imx_soc_revision & 0xf);
if (!soc_dev_attr->revision)
goto free_soc;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev))
goto free_rev;
return soc_device_to_device(soc_dev);
free_rev:
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
return NULL;
}
|
