summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/msm/dsi/dsi.xml.h
blob: 21f489a737d7ac60259bc10ed60f55dfe4bc9071 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
#ifndef DSI_XML
#define DSI_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git

The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2018-07-03 19:37:13)

Copyright (C) 2013-2018 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


enum dsi_traffic_mode {
	NON_BURST_SYNCH_PULSE = 0,
	NON_BURST_SYNCH_EVENT = 1,
	BURST_MODE = 2,
};

enum dsi_vid_dst_format {
	VID_DST_FORMAT_RGB565 = 0,
	VID_DST_FORMAT_RGB666 = 1,
	VID_DST_FORMAT_RGB666_LOOSE = 2,
	VID_DST_FORMAT_RGB888 = 3,
};

enum dsi_rgb_swap {
	SWAP_RGB = 0,
	SWAP_RBG = 1,
	SWAP_BGR = 2,
	SWAP_BRG = 3,
	SWAP_GRB = 4,
	SWAP_GBR = 5,
};

enum dsi_cmd_trigger {
	TRIGGER_NONE = 0,
	TRIGGER_SEOF = 1,
	TRIGGER_TE = 2,
	TRIGGER_SW = 4,
	TRIGGER_SW_SEOF = 5,
	TRIGGER_SW_TE = 6,
};

enum dsi_cmd_dst_format {
	CMD_DST_FORMAT_RGB111 = 0,
	CMD_DST_FORMAT_RGB332 = 3,
	CMD_DST_FORMAT_RGB444 = 4,
	CMD_DST_FORMAT_RGB565 = 6,
	CMD_DST_FORMAT_RGB666 = 7,
	CMD_DST_FORMAT_RGB888 = 8,
};

enum dsi_lane_swap {
	LANE_SWAP_0123 = 0,
	LANE_SWAP_3012 = 1,
	LANE_SWAP_2301 = 2,
	LANE_SWAP_1230 = 3,
	LANE_SWAP_0321 = 4,
	LANE_SWAP_1032 = 5,
	LANE_SWAP_2103 = 6,
	LANE_SWAP_3210 = 7,
};

#define DSI_IRQ_CMD_DMA_DONE					0x00000001
#define DSI_IRQ_MASK_CMD_DMA_DONE				0x00000002
#define DSI_IRQ_CMD_MDP_DONE					0x00000100
#define DSI_IRQ_MASK_CMD_MDP_DONE				0x00000200
#define DSI_IRQ_VIDEO_DONE					0x00010000
#define DSI_IRQ_MASK_VIDEO_DONE					0x00020000
#define DSI_IRQ_BTA_DONE					0x00100000
#define DSI_IRQ_MASK_BTA_DONE					0x00200000
#define DSI_IRQ_ERROR						0x01000000
#define DSI_IRQ_MASK_ERROR					0x02000000
#define REG_DSI_6G_HW_VERSION					0x00000000
#define DSI_6G_HW_VERSION_MAJOR__MASK				0xf0000000
#define DSI_6G_HW_VERSION_MAJOR__SHIFT				28
static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
{
	return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
}
#define DSI_6G_HW_VERSION_MINOR__MASK				0x0fff0000
#define DSI_6G_HW_VERSION_MINOR__SHIFT				16
static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
{
	return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
}
#define DSI_6G_HW_VERSION_STEP__MASK				0x0000ffff
#define DSI_6G_HW_VERSION_STEP__SHIFT				0
static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
{
	return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
}

#define REG_DSI_CTRL						0x00000000
#define DSI_CTRL_ENABLE						0x00000001
#define DSI_CTRL_VID_MODE_EN					0x00000002
#define DSI_CTRL_CMD_MODE_EN					0x00000004
#define DSI_CTRL_LANE0						0x00000010
#define DSI_CTRL_LANE1						0x00000020
#define DSI_CTRL_LANE2						0x00000040
#define DSI_CTRL_LANE3						0x00000080
#define DSI_CTRL_CLK_EN						0x00000100
#define DSI_CTRL_ECC_CHECK					0x00100000
#define DSI_CTRL_CRC_CHECK					0x01000000

#define REG_DSI_STATUS0						0x00000004
#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY			0x00000001
#define DSI_STATUS0_CMD_MODE_DMA_BUSY				0x00000002
#define DSI_STATUS0_CMD_MODE_MDP_BUSY				0x00000004
#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY			0x00000008
#define DSI_STATUS0_DSI_BUSY					0x00000010
#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION			0x80000000

#define REG_DSI_FIFO_STATUS					0x00000008
#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW			0x00000080

#define REG_DSI_VID_CFG0					0x0000000c
#define DSI_VID_CFG0_VIRT_CHANNEL__MASK				0x00000003
#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT			0
static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
{
	return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
}
#define DSI_VID_CFG0_DST_FORMAT__MASK				0x00000030
#define DSI_VID_CFG0_DST_FORMAT__SHIFT				4
static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
{
	return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
}
#define DSI_VID_CFG0_TRAFFIC_MODE__MASK				0x00000300
#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT			8
static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
{
	return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
}
#define DSI_VID_CFG0_BLLP_POWER_STOP				0x00001000
#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP			0x00008000
#define DSI_VID_CFG0_HSA_POWER_STOP				0x00010000
#define DSI_VID_CFG0_HBP_POWER_STOP				0x00100000
#define DSI_VID_CFG0_HFP_POWER_STOP				0x01000000
#define DSI_VID_CFG0_PULSE_MODE_HSA_HE				0x10000000

#define REG_DSI_VID_CFG1					0x0000001c
#define DSI_VID_CFG1_R_SEL					0x00000001
#define DSI_VID_CFG1_G_SEL					0x00000010
#define DSI_VID_CFG1_B_SEL					0x00000100
#define DSI_VID_CFG1_RGB_SWAP__MASK				0x00007000
#define DSI_VID_CFG1_RGB_SWAP__SHIFT				12
static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
{
	return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
}

#define REG_DSI_ACTIVE_H					0x00000020
#define DSI_ACTIVE_H_START__MASK				0x00000fff
#define DSI_ACTIVE_H_START__SHIFT				0
static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
{
	return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
}
#define DSI_ACTIVE_H_END__MASK					0x0fff0000
#define DSI_ACTIVE_H_END__SHIFT					16
static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
{
	return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
}

#define REG_DSI_ACTIVE_V					0x00000024
#define DSI_ACTIVE_V_START__MASK				0x00000fff
#define DSI_ACTIVE_V_START__SHIFT				0
static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
{
	return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
}
#define DSI_ACTIVE_V_END__MASK					0x0fff0000
#define DSI_ACTIVE_V_END__SHIFT					16
static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
{
	return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
}

#define REG_DSI_TOTAL						0x00000028
#define DSI_TOTAL_H_TOTAL__MASK					0x00000fff
#define DSI_TOTAL_H_TOTAL__SHIFT				0
static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
{
	return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
}
#define DSI_TOTAL_V_TOTAL__MASK					0x0fff0000
#define DSI_TOTAL_V_TOTAL__SHIFT				16
static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
{
	return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
}

#define REG_DSI_ACTIVE_HSYNC					0x0000002c
#define DSI_ACTIVE_HSYNC_START__MASK				0x00000fff
#define DSI_ACTIVE_HSYNC_START__SHIFT				0
static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
{
	return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
}
#define DSI_ACTIVE_HSYNC_END__MASK				0x0fff0000
#define DSI_ACTIVE_HSYNC_END__SHIFT				16
static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
{
	return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
}

#define REG_DSI_ACTIVE_VSYNC_HPOS				0x00000030
#define DSI_ACTIVE_VSYNC_HPOS_START__MASK			0x00000fff
#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT			0
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
{
	return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
}
#define DSI_ACTIVE_VSYNC_HPOS_END__MASK				0x0fff0000
#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT			16
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
{
	return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
}

#define REG_DSI_ACTIVE_VSYNC_VPOS				0x00000034
#define DSI_ACTIVE_VSYNC_VPOS_START__MASK			0x00000fff
#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT			0
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
{
	return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
}
#define DSI_ACTIVE_VSYNC_VPOS_END__MASK				0x0fff0000
#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT			16
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
{
	return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
}

#define REG_DSI_CMD_DMA_CTRL					0x00000038
#define DSI_CMD_DMA_CTRL_BROADCAST_EN				0x80000000
#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER			0x10000000
#define DSI_CMD_DMA_CTRL_LOW_POWER				0x04000000

#define REG_DSI_CMD_CFG0					0x0000003c
#define DSI_CMD_CFG0_DST_FORMAT__MASK				0x0000000f
#define DSI_CMD_CFG0_DST_FORMAT__SHIFT				0
static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
{
	return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
}
#define DSI_CMD_CFG0_R_SEL					0x00000010
#define DSI_CMD_CFG0_G_SEL					0x00000100
#define DSI_CMD_CFG0_B_SEL					0x00001000
#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK			0x00f00000
#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT			20
static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
{
	return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
}
#define DSI_CMD_CFG0_RGB_SWAP__MASK				0x00070000
#define DSI_CMD_CFG0_RGB_SWAP__SHIFT				16
static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
{
	return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
}

#define REG_DSI_CMD_CFG1					0x00000040
#define DSI_CMD_CFG1_WR_MEM_START__MASK				0x000000ff
#define DSI_CMD_CFG1_WR_MEM_START__SHIFT			0
static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
{
	return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
}
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK			0x0000ff00
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT			8
static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
{
	return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
}
#define DSI_CMD_CFG1_INSERT_DCS_COMMAND				0x00010000

#define REG_DSI_DMA_BASE					0x00000044

#define REG_DSI_DMA_LEN						0x00000048

#define REG_DSI_CMD_MDP_STREAM_CTRL				0x00000054
#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK			0x0000003f
#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT		0
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
{
	return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK		0x00000300
#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT		8
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
	return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK		0xffff0000
#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT		16
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
{
	return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
}

#define REG_DSI_CMD_MDP_STREAM_TOTAL				0x00000058
#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK			0x00000fff
#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT			0
static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
{
	return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
}
#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK			0x0fff0000
#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT			16
static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
{
	return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
}

#define REG_DSI_ACK_ERR_STATUS					0x00000064

static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }

static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }

#define REG_DSI_TRIG_CTRL					0x00000080
#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK				0x00000007
#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT			0
static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
{
	return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
}
#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK				0x00000070
#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT			4
static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
{
	return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
}
#define DSI_TRIG_CTRL_STREAM__MASK				0x00000300
#define DSI_TRIG_CTRL_STREAM__SHIFT				8
static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
{
	return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
}
#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME			0x00001000
#define DSI_TRIG_CTRL_TE					0x80000000

#define REG_DSI_TRIG_DMA					0x0000008c

#define REG_DSI_DLN0_PHY_ERR					0x000000b0
#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC				0x00000001
#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC			0x00000010
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL			0x00000100
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0		0x00001000
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1		0x00010000

#define REG_DSI_TIMEOUT_STATUS					0x000000bc

#define REG_DSI_CLKOUT_TIMING_CTRL				0x000000c0
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK			0x0000003f
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT			0
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
{
	return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
}
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK			0x00003f00
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT		8
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
{
	return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
}

#define REG_DSI_EOT_PACKET_CTRL					0x000000c8
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND			0x00000001
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE			0x00000010

#define REG_DSI_LANE_CTRL					0x000000a8
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST			0x10000000

#define REG_DSI_LANE_SWAP_CTRL					0x000000ac
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK			0x00000007
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT			0
static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
{
	return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
}

#define REG_DSI_ERR_INT_MASK0					0x00000108

#define REG_DSI_INTR_CTRL					0x0000010c

#define REG_DSI_RESET						0x00000114

#define REG_DSI_CLK_CTRL					0x00000118
#define DSI_CLK_CTRL_AHBS_HCLK_ON				0x00000001
#define DSI_CLK_CTRL_AHBM_SCLK_ON				0x00000002
#define DSI_CLK_CTRL_PCLK_ON					0x00000004
#define DSI_CLK_CTRL_DSICLK_ON					0x00000008
#define DSI_CLK_CTRL_BYTECLK_ON					0x00000010
#define DSI_CLK_CTRL_ESCCLK_ON					0x00000020
#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK			0x00000200

#define REG_DSI_CLK_STATUS					0x0000011c
#define DSI_CLK_STATUS_PLL_UNLOCKED				0x00010000

#define REG_DSI_PHY_RESET					0x00000128
#define DSI_PHY_RESET_RESET					0x00000001

#define REG_DSI_T_CLK_PRE_EXTEND				0x0000017c
#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK			0x00000001

#define REG_DSI_RDBK_DATA_CTRL					0x000001d0
#define DSI_RDBK_DATA_CTRL_COUNT__MASK				0x00ff0000
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT				16
static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
{
	return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
}
#define DSI_RDBK_DATA_CTRL_CLR					0x00000001

#define REG_DSI_VERSION						0x000001f0
#define DSI_VERSION_MAJOR__MASK					0xff000000
#define DSI_VERSION_MAJOR__SHIFT				24
static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
{
	return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
}

#define REG_DSI_PHY_PLL_CTRL_0					0x00000200
#define DSI_PHY_PLL_CTRL_0_ENABLE				0x00000001

#define REG_DSI_PHY_PLL_CTRL_1					0x00000204

#define REG_DSI_PHY_PLL_CTRL_2					0x00000208

#define REG_DSI_PHY_PLL_CTRL_3					0x0000020c

#define REG_DSI_PHY_PLL_CTRL_4					0x00000210

#define REG_DSI_PHY_PLL_CTRL_5					0x00000214

#define REG_DSI_PHY_PLL_CTRL_6					0x00000218

#define REG_DSI_PHY_PLL_CTRL_7					0x0000021c

#define REG_DSI_PHY_PLL_CTRL_8					0x00000220

#define REG_DSI_PHY_PLL_CTRL_9					0x00000224

#define REG_DSI_PHY_PLL_CTRL_10					0x00000228

#define REG_DSI_PHY_PLL_CTRL_11					0x0000022c

#define REG_DSI_PHY_PLL_CTRL_12					0x00000230

#define REG_DSI_PHY_PLL_CTRL_13					0x00000234

#define REG_DSI_PHY_PLL_CTRL_14					0x00000238

#define REG_DSI_PHY_PLL_CTRL_15					0x0000023c

#define REG_DSI_PHY_PLL_CTRL_16					0x00000240

#define REG_DSI_PHY_PLL_CTRL_17					0x00000244

#define REG_DSI_PHY_PLL_CTRL_18					0x00000248

#define REG_DSI_PHY_PLL_CTRL_19					0x0000024c

#define REG_DSI_PHY_PLL_CTRL_20					0x00000250

#define REG_DSI_PHY_PLL_STATUS					0x00000280
#define DSI_PHY_PLL_STATUS_PLL_BUSY				0x00000001

#define REG_DSI_8x60_PHY_TPA_CTRL_1				0x00000258

#define REG_DSI_8x60_PHY_TPA_CTRL_2				0x0000025c

#define REG_DSI_8x60_PHY_TIMING_CTRL_0				0x00000260

#define REG_DSI_8x60_PHY_TIMING_CTRL_1				0x00000264

#define REG_DSI_8x60_PHY_TIMING_CTRL_2				0x00000268

#define REG_DSI_8x60_PHY_TIMING_CTRL_3				0x0000026c

#define REG_DSI_8x60_PHY_TIMING_CTRL_4				0x00000270

#define REG_DSI_8x60_PHY_TIMING_CTRL_5				0x00000274

#define REG_DSI_8x60_PHY_TIMING_CTRL_6				0x00000278

#define REG_DSI_8x60_PHY_TIMING_CTRL_7				0x0000027c

#define REG_DSI_8x60_PHY_TIMING_CTRL_8				0x00000280

#define REG_DSI_8x60_PHY_TIMING_CTRL_9				0x00000284

#define REG_DSI_8x60_PHY_TIMING_CTRL_10				0x00000288

#define REG_DSI_8x60_PHY_TIMING_CTRL_11				0x0000028c

#define REG_DSI_8x60_PHY_CTRL_0					0x00000290

#define REG_DSI_8x60_PHY_CTRL_1					0x00000294

#define REG_DSI_8x60_PHY_CTRL_2					0x00000298

#define REG_DSI_8x60_PHY_CTRL_3					0x0000029c

#define REG_DSI_8x60_PHY_STRENGTH_0				0x000002a0

#define REG_DSI_8x60_PHY_STRENGTH_1				0x000002a4

#define REG_DSI_8x60_PHY_STRENGTH_2				0x000002a8

#define REG_DSI_8x60_PHY_STRENGTH_3				0x000002ac

#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0			0x000002cc

#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1			0x000002d0

#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2			0x000002d4

#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3			0x000002d8

#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4			0x000002dc

#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER				0x000000f0

#define REG_DSI_8x60_PHY_CAL_CTRL				0x000000f4

#define REG_DSI_8x60_PHY_CAL_STATUS				0x000000fc
#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY			0x10000000

static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0			0x00000100

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1			0x00000104

#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2			0x00000108

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH		0x0000010c

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0			0x00000114

#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1			0x00000118

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0			0x00000140
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1			0x00000144
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2			0x00000148
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3			0x0000014c

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4			0x00000150
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5			0x00000154
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6			0x00000158
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7			0x0000015c
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8			0x00000160
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9			0x00000164
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK		0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT		4
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10			0x00000168
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK		0x00000007
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT		0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
}

#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11			0x0000016c
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK	0x000000ff
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT	0
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
	return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}

#define REG_DSI_28nm_8960_PHY_CTRL_0				0x00000170

#define REG_DSI_28nm_8960_PHY_CTRL_1				0x00000174

#define REG_DSI_28nm_8960_PHY_CTRL_2				0x00000178

#define REG_DSI_28nm_8960_PHY_CTRL_3				0x0000017c

#define REG_DSI_28nm_8960_PHY_STRENGTH_0			0x00000180

#define REG_DSI_28nm_8960_PHY_STRENGTH_1			0x00000184

#define REG_DSI_28nm_8960_PHY_STRENGTH_2			0x00000188

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0			0x0000018c

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1			0x00000190

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2			0x00000194

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3			0x00000198

#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4			0x0000019c

#define REG_DSI_28nm_8960_PHY_LDO_CTRL				0x000001b0

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0		0x00000000

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1		0x00000004

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2		0x00000008

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3		0x0000000c

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4		0x00000010

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5		0x00000014

#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG	0x00000018

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER		0x00000028

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0			0x0000002c

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1			0x00000030

#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2			0x00000034

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0			0x00000038

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1			0x0000003c

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2			0x00000040

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3			0x00000044

#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4			0x00000048

#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS			0x00000050
#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY		0x00000010

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0			0x00000000
#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE			0x00000001

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1			0x00000004

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2			0x00000008

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3			0x0000000c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4			0x00000010

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5			0x00000014

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6			0x00000018

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7			0x0000001c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8			0x00000020

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9			0x00000024

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10			0x00000028

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11			0x0000002c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12			0x00000030

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13			0x00000034

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14			0x00000038

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15			0x0000003c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16			0x00000040

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17			0x00000044

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18			0x00000048

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19			0x0000004c

#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20			0x00000050

#define REG_DSI_28nm_8960_PHY_PLL_RDY				0x00000080
#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY			0x00000001

static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }

static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }

#define REG_DSI_28nm_PHY_LNCK_CFG_0				0x00000100

#define REG_DSI_28nm_PHY_LNCK_CFG_1				0x00000104

#define REG_DSI_28nm_PHY_LNCK_CFG_2				0x00000108

#define REG_DSI_28nm_PHY_LNCK_CFG_3				0x0000010c

#define REG_DSI_28nm_PHY_LNCK_CFG_4				0x00000110

#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH			0x00000114

#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL				0x00000118

#define REG_DSI_28nm_PHY_LNCK_TEST_STR0				0x0000011c

#define REG_DSI_28nm_PHY_LNCK_TEST_STR1				0x00000120

#define REG_DSI_28nm_PHY_TIMING_CTRL_0				0x00000140
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_1				0x00000144
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_2				0x00000148
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_3				0x0000014c
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8			0x00000001

#define REG_DSI_28nm_PHY_TIMING_CTRL_4				0x00000150
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_5				0x00000154
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_6				0x00000158
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_7				0x0000015c
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_8				0x00000160
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_9				0x00000164
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK			0x00000007
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT			0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT		4
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_10				0x00000168
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK		0x00000007
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
}

#define REG_DSI_28nm_PHY_TIMING_CTRL_11				0x0000016c
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK		0x000000ff
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT		0
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}

#define REG_DSI_28nm_PHY_CTRL_0					0x00000170

#define REG_DSI_28nm_PHY_CTRL_1					0x00000174

#define REG_DSI_28nm_PHY_CTRL_2					0x00000178

#define REG_DSI_28nm_PHY_CTRL_3					0x0000017c

#define REG_DSI_28nm_PHY_CTRL_4					0x00000180

#define REG_DSI_28nm_PHY_STRENGTH_0				0x00000184

#define REG_DSI_28nm_PHY_STRENGTH_1				0x00000188

#define REG_DSI_28nm_PHY_BIST_CTRL_0				0x000001b4

#define REG_DSI_28nm_PHY_BIST_CTRL_1				0x000001b8

#define REG_DSI_28nm_PHY_BIST_CTRL_2				0x000001bc

#define REG_DSI_28nm_PHY_BIST_CTRL_3				0x000001c0

#define REG_DSI_28nm_PHY_BIST_CTRL_4				0x000001c4

#define REG_DSI_28nm_PHY_BIST_CTRL_5				0x000001c8

#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL				0x000001d4
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL		0x00000001

#define REG_DSI_28nm_PHY_LDO_CNTRL				0x000001dc

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0			0x00000000

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1			0x00000004

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2			0x00000008

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3			0x0000000c

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4			0x00000010

#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5			0x00000014

#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG			0x00000018

#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG				0x00000000
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR			0x00000001

#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG			0x00000004

#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG			0x00000008

#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG				0x0000000c

#define REG_DSI_28nm_PHY_PLL_VREG_CFG				0x00000010
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B		0x00000002

#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG				0x00000014

#define REG_DSI_28nm_PHY_PLL_DMUX_CFG				0x00000018

#define REG_DSI_28nm_PHY_PLL_AMUX_CFG				0x0000001c

#define REG_DSI_28nm_PHY_PLL_GLB_CFG				0x00000020
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B			0x00000001
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B		0x00000002
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B		0x00000004
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE			0x00000008

#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG			0x00000024

#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG			0x00000028

#define REG_DSI_28nm_PHY_PLL_LPFR_CFG				0x0000002c

#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG				0x00000030

#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG				0x00000034

#define REG_DSI_28nm_PHY_PLL_SDM_CFG0				0x00000038
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK			0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT		0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP				0x00000040

#define REG_DSI_28nm_PHY_PLL_SDM_CFG1				0x0000003c
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK		0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT		0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
}
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK		0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT		6
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
}

#define REG_DSI_28nm_PHY_PLL_SDM_CFG2				0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK		0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT		0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
}

#define REG_DSI_28nm_PHY_PLL_SDM_CFG3				0x00000044
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK		0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT		0
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
{
	return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
}

#define REG_DSI_28nm_PHY_PLL_SDM_CFG4				0x00000048

#define REG_DSI_28nm_PHY_PLL_SSC_CFG0				0x0000004c

#define REG_DSI_28nm_PHY_PLL_SSC_CFG1				0x00000050

#define REG_DSI_28nm_PHY_PLL_SSC_CFG2				0x00000054

#define REG_DSI_28nm_PHY_PLL_SSC_CFG3				0x00000058

#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0				0x0000005c

#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1				0x00000060

#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2				0x00000064

#define REG_DSI_28nm_PHY_PLL_TEST_CFG				0x00000068
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET			0x00000001

#define REG_DSI_28nm_PHY_PLL_CAL_CFG0				0x0000006c

#define REG_DSI_28nm_PHY_PLL_CAL_CFG1				0x00000070

#define REG_DSI_28nm_PHY_PLL_CAL_CFG2				0x00000074

#define REG_DSI_28nm_PHY_PLL_CAL_CFG3				0x00000078

#define REG_DSI_28nm_PHY_PLL_CAL_CFG4				0x0000007c

#define REG_DSI_28nm_PHY_PLL_CAL_CFG5				0x00000080

#define REG_DSI_28nm_PHY_PLL_CAL_CFG6				0x00000084

#define REG_DSI_28nm_PHY_PLL_CAL_CFG7				0x00000088

#define REG_DSI_28nm_PHY_PLL_CAL_CFG8				0x0000008c

#define REG_DSI_28nm_PHY_PLL_CAL_CFG9				0x00000090

#define REG_DSI_28nm_PHY_PLL_CAL_CFG10				0x00000094

#define REG_DSI_28nm_PHY_PLL_CAL_CFG11				0x00000098

#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG				0x0000009c

#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL			0x000000a0

#define REG_DSI_28nm_PHY_PLL_CTRL_42				0x000000a4

#define REG_DSI_28nm_PHY_PLL_CTRL_43				0x000000a8

#define REG_DSI_28nm_PHY_PLL_CTRL_44				0x000000ac

#define REG_DSI_28nm_PHY_PLL_CTRL_45				0x000000b0

#define REG_DSI_28nm_PHY_PLL_CTRL_46				0x000000b4

#define REG_DSI_28nm_PHY_PLL_CTRL_47				0x000000b8

#define REG_DSI_28nm_PHY_PLL_CTRL_48				0x000000bc

#define REG_DSI_28nm_PHY_PLL_STATUS				0x000000c0
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY				0x00000001

#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0				0x000000c4

#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1				0x000000c8

#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2				0x000000cc

#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3				0x000000d0

#define REG_DSI_28nm_PHY_PLL_CTRL_54				0x000000d4

static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }

static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }

#define REG_DSI_20nm_PHY_LNCK_CFG_0				0x00000100

#define REG_DSI_20nm_PHY_LNCK_CFG_1				0x00000104

#define REG_DSI_20nm_PHY_LNCK_CFG_2				0x00000108

#define REG_DSI_20nm_PHY_LNCK_CFG_3				0x0000010c

#define REG_DSI_20nm_PHY_LNCK_CFG_4				0x00000110

#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH			0x00000114

#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL				0x00000118

#define REG_DSI_20nm_PHY_LNCK_TEST_STR0				0x0000011c

#define REG_DSI_20nm_PHY_LNCK_TEST_STR1				0x00000120

#define REG_DSI_20nm_PHY_TIMING_CTRL_0				0x00000140
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_1				0x00000144
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_2				0x00000148
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_3				0x0000014c
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8			0x00000001

#define REG_DSI_20nm_PHY_TIMING_CTRL_4				0x00000150
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_5				0x00000154
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_6				0x00000158
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_7				0x0000015c
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_8				0x00000160
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_9				0x00000164
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK			0x00000007
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT			0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT		4
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_10				0x00000168
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK		0x00000007
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
}

#define REG_DSI_20nm_PHY_TIMING_CTRL_11				0x0000016c
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK		0x000000ff
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT		0
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
	return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
}

#define REG_DSI_20nm_PHY_CTRL_0					0x00000170

#define REG_DSI_20nm_PHY_CTRL_1					0x00000174

#define REG_DSI_20nm_PHY_CTRL_2					0x00000178

#define REG_DSI_20nm_PHY_CTRL_3					0x0000017c

#define REG_DSI_20nm_PHY_CTRL_4					0x00000180

#define REG_DSI_20nm_PHY_STRENGTH_0				0x00000184

#define REG_DSI_20nm_PHY_STRENGTH_1				0x00000188

#define REG_DSI_20nm_PHY_BIST_CTRL_0				0x000001b4

#define REG_DSI_20nm_PHY_BIST_CTRL_1				0x000001b8

#define REG_DSI_20nm_PHY_BIST_CTRL_2				0x000001bc

#define REG_DSI_20nm_PHY_BIST_CTRL_3				0x000001c0

#define REG_DSI_20nm_PHY_BIST_CTRL_4				0x000001c4

#define REG_DSI_20nm_PHY_BIST_CTRL_5				0x000001c8

#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL				0x000001d4
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL		0x00000001

#define REG_DSI_20nm_PHY_LDO_CNTRL				0x000001dc

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0			0x00000000

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1			0x00000004

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2			0x00000008

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3			0x0000000c

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4			0x00000010

#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5			0x00000014

#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG			0x00000018

#define REG_DSI_14nm_PHY_CMN_REVISION_ID0			0x00000000

#define REG_DSI_14nm_PHY_CMN_REVISION_ID1			0x00000004

#define REG_DSI_14nm_PHY_CMN_REVISION_ID2			0x00000008

#define REG_DSI_14nm_PHY_CMN_REVISION_ID3			0x0000000c

#define REG_DSI_14nm_PHY_CMN_CLK_CFG0				0x00000010
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK		0x000000f0
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT		4
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
}
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK		0x000000f0
#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT		4
static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
}

#define REG_DSI_14nm_PHY_CMN_CLK_CFG1				0x00000014
#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL			0x00000001

#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL			0x00000018
#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL		0x00000004

#define REG_DSI_14nm_PHY_CMN_CTRL_0				0x0000001c

#define REG_DSI_14nm_PHY_CMN_CTRL_1				0x00000020

#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER				0x00000024

#define REG_DSI_14nm_PHY_CMN_SW_CFG0				0x00000028

#define REG_DSI_14nm_PHY_CMN_SW_CFG1				0x0000002c

#define REG_DSI_14nm_PHY_CMN_SW_CFG2				0x00000030

#define REG_DSI_14nm_PHY_CMN_HW_CFG0				0x00000034

#define REG_DSI_14nm_PHY_CMN_HW_CFG1				0x00000038

#define REG_DSI_14nm_PHY_CMN_HW_CFG2				0x0000003c

#define REG_DSI_14nm_PHY_CMN_HW_CFG3				0x00000040

#define REG_DSI_14nm_PHY_CMN_HW_CFG4				0x00000044

#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL				0x00000048
#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START			0x00000001

#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL				0x0000004c
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK		0x0000003f
#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT		0
static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK			0x000000c0
#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT			6
static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN			0x00000001

static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK		0x00000007
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
}
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK		0x00000070
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT		4
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK		0x00000007
#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK		0x000000ff
#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT		0
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
{
	return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
}

static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }

static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }

#define REG_DSI_14nm_PHY_PLL_IE_TRIM				0x00000000

#define REG_DSI_14nm_PHY_PLL_IP_TRIM				0x00000004

#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM				0x00000010

#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN			0x0000001c

#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET			0x00000028

#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL			0x0000002c

#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2			0x00000030

#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3			0x00000034

#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4			0x00000038

#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5			0x0000003c

#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1			0x00000040

#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2			0x00000044

#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1			0x00000048

#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2			0x0000004c

#define REG_DSI_14nm_PHY_PLL_VREF_CFG1				0x0000005c

#define REG_DSI_14nm_PHY_PLL_KVCO_CODE				0x00000058

#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1			0x0000006c

#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2			0x00000070

#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1				0x00000074

#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2				0x00000078

#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1			0x0000007c

#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2			0x00000080

#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3			0x00000084

#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN			0x00000088

#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE			0x0000008c

#define REG_DSI_14nm_PHY_PLL_DEC_START				0x00000090

#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER			0x00000094

#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1			0x00000098

#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2			0x0000009c

#define REG_DSI_14nm_PHY_PLL_SSC_PER1				0x000000a0

#define REG_DSI_14nm_PHY_PLL_SSC_PER2				0x000000a4

#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1			0x000000a8

#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2			0x000000ac

#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1			0x000000b4

#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2			0x000000b8

#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3			0x000000bc

#define REG_DSI_14nm_PHY_PLL_TXCLK_EN				0x000000c0

#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL				0x000000c4

#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS		0x000000cc

#define REG_DSI_14nm_PHY_PLL_PLL_MISC1				0x000000e8

#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR				0x000000f0

#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET			0x000000f4

#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET			0x000000f8

#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET			0x000000fc

#define REG_DSI_14nm_PHY_PLL_PLL_LPF1				0x00000100

#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV			0x00000104

#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP			0x00000108

#define REG_DSI_10nm_PHY_CMN_REVISION_ID0			0x00000000

#define REG_DSI_10nm_PHY_CMN_REVISION_ID1			0x00000004

#define REG_DSI_10nm_PHY_CMN_REVISION_ID2			0x00000008

#define REG_DSI_10nm_PHY_CMN_REVISION_ID3			0x0000000c

#define REG_DSI_10nm_PHY_CMN_CLK_CFG0				0x00000010

#define REG_DSI_10nm_PHY_CMN_CLK_CFG1				0x00000014

#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL				0x00000018

#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL				0x0000001c

#define REG_DSI_10nm_PHY_CMN_VREG_CTRL				0x00000020

#define REG_DSI_10nm_PHY_CMN_CTRL_0				0x00000024

#define REG_DSI_10nm_PHY_CMN_CTRL_1				0x00000028

#define REG_DSI_10nm_PHY_CMN_CTRL_2				0x0000002c

#define REG_DSI_10nm_PHY_CMN_LANE_CFG0				0x00000030

#define REG_DSI_10nm_PHY_CMN_LANE_CFG1				0x00000034

#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL				0x00000038

#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0				0x00000098

#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1				0x0000009c

#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2				0x000000a0

#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3				0x000000a4

#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4				0x000000a8

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0			0x000000ac

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1			0x000000b0

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2			0x000000b4

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3			0x000000b8

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4			0x000000bc

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5			0x000000c0

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6			0x000000c4

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7			0x000000c8

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8			0x000000cc

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9			0x000000d0

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10			0x000000d4

#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11			0x000000d8

#define REG_DSI_10nm_PHY_CMN_PHY_STATUS				0x000000ec

#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0			0x000000f4

#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1			0x000000f8

static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }

static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }

#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE		0x00000000

#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO		0x00000004

#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE		0x00000010

#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER			0x0000001c

#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER			0x00000020

#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES			0x00000024

#define REG_DSI_10nm_PHY_PLL_CMODE				0x0000002c

#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS		0x00000030

#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE	0x00000054

#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE		0x00000064

#define REG_DSI_10nm_PHY_PLL_PFILT				0x0000007c

#define REG_DSI_10nm_PHY_PLL_IFILT				0x00000080

#define REG_DSI_10nm_PHY_PLL_OUTDIV				0x00000094

#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE			0x000000a4

#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE		0x000000a8

#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO		0x000000b4

#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1		0x000000cc

#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1		0x000000d0

#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1		0x000000d4

#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1		0x000000d8

#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1			0x0000010c

#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1		0x00000110

#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1			0x00000114

#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1			0x00000118

#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1		0x0000011c

#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1		0x00000120

#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL			0x0000013c

#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE			0x00000140

#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1			0x00000144

#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1		0x0000014c

#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1		0x00000154

#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1		0x0000015c

#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1	0x00000164

#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE			0x00000180

#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY			0x00000184

#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS			0x0000018c

#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE			0x000001a0


#endif /* DSI_XML */