summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/rcar-du/rcar_du_plane.h
blob: f9893d7d6dfce966eb49f6ed57fdc50d3656a5a3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * R-Car Display Unit Planes
 *
 * Copyright (C) 2013-2014 Renesas Electronics Corporation
 *
 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
 */

#ifndef __RCAR_DU_PLANE_H__
#define __RCAR_DU_PLANE_H__

#include <drm/drm_plane.h>

struct rcar_du_format_info;
struct rcar_du_group;

/*
 * The RCAR DU has 8 hardware planes, shared between primary and overlay planes.
 * As using overlay planes requires at least one of the CRTCs being enabled, no
 * more than 7 overlay planes can be available. We thus create 1 primary plane
 * per CRTC and 7 overlay planes, for a total of up to 9 KMS planes.
 */
#define RCAR_DU_NUM_KMS_PLANES		9
#define RCAR_DU_NUM_HW_PLANES		8

enum rcar_du_plane_source {
	RCAR_DU_PLANE_MEMORY,
	RCAR_DU_PLANE_VSPD0,
	RCAR_DU_PLANE_VSPD1,
};

struct rcar_du_plane {
	struct drm_plane plane;
	struct rcar_du_group *group;
};

static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane)
{
	return container_of(plane, struct rcar_du_plane, plane);
}

/**
 * struct rcar_du_plane_state - Driver-specific plane state
 * @state: base DRM plane state
 * @format: information about the pixel format used by the plane
 * @hwindex: 0-based hardware plane index, -1 means unused
 * @colorkey: value of the plane colorkey property
 */
struct rcar_du_plane_state {
	struct drm_plane_state state;

	const struct rcar_du_format_info *format;
	int hwindex;
	enum rcar_du_plane_source source;

	unsigned int colorkey;
};

static inline struct rcar_du_plane_state *
to_rcar_plane_state(struct drm_plane_state *state)
{
	return container_of(state, struct rcar_du_plane_state, state);
}

int rcar_du_atomic_check_planes(struct drm_device *dev,
				struct drm_atomic_state *state);

int __rcar_du_plane_atomic_check(struct drm_plane *plane,
				 struct drm_plane_state *state,
				 const struct rcar_du_format_info **format);

int rcar_du_planes_init(struct rcar_du_group *rgrp);

void __rcar_du_plane_setup(struct rcar_du_group *rgrp,
			   const struct rcar_du_plane_state *state);

static inline void rcar_du_plane_setup(struct rcar_du_plane *plane)
{
	struct rcar_du_plane_state *state =
		to_rcar_plane_state(plane->plane.state);

	return __rcar_du_plane_setup(plane->group, state);
}

#endif /* __RCAR_DU_PLANE_H__ */