summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/xe/xe_sriov_types.h
blob: c7b7ad4af5c8f6d48713b7a211ffa725bd0653bf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2023 Intel Corporation
 */

#ifndef _XE_SRIOV_TYPES_H_
#define _XE_SRIOV_TYPES_H_

#include <linux/build_bug.h>
#include <linux/mutex.h>
#include <linux/types.h>

/**
 * VFID - Virtual Function Identifier
 * @n: VF number
 *
 * Helper macro to represent Virtual Function (VF) Identifier.
 * VFID(0) is used as alias to the PFID that represents Physical Function.
 *
 * Note: According to PCI spec, SR-IOV VF's numbers are 1-based (VF1, VF2, ...).
 */
#define VFID(n)		(n)
#define PFID		VFID(0)

/**
 * enum xe_sriov_mode - SR-IOV mode
 * @XE_SRIOV_MODE_NONE: bare-metal mode (non-virtualized)
 * @XE_SRIOV_MODE_PF: SR-IOV Physical Function (PF) mode
 * @XE_SRIOV_MODE_VF: SR-IOV Virtual Function (VF) mode
 */
enum xe_sriov_mode {
	/*
	 * Note: We don't use default enum value 0 to allow catch any too early
	 * attempt of checking the SR-IOV mode prior to the actual mode probe.
	 */
	XE_SRIOV_MODE_NONE = 1,
	XE_SRIOV_MODE_PF,
	XE_SRIOV_MODE_VF,
};
static_assert(XE_SRIOV_MODE_NONE);

/**
 * struct xe_device_pf - Xe PF related data
 *
 * The data in this structure is valid only if driver is running in the
 * @XE_SRIOV_MODE_PF mode.
 */
struct xe_device_pf {
	/** @device_total_vfs: Maximum number of VFs supported by the device. */
	u16 device_total_vfs;

	/** @driver_max_vfs: Maximum number of VFs supported by the driver. */
	u16 driver_max_vfs;

	/** @master_lock: protects all VFs configurations across GTs */
	struct mutex master_lock;
};

#endif