summaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/lpass-wsa-macro.c
blob: 7e21cec3c2fb97a9be518b4316cdeafae2cf0776 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of_clk.h>
#include <linux/clk-provider.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/pm_runtime.h>
#include <linux/of_platform.h>
#include <sound/tlv.h>

#include "lpass-macro-common.h"
#include "lpass-wsa-macro.h"

#define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL	(0x0000)
#define CDC_WSA_MCLK_EN_MASK			BIT(0)
#define CDC_WSA_MCLK_ENABLE			BIT(0)
#define CDC_WSA_MCLK_DISABLE			0
#define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL	(0x0004)
#define CDC_WSA_FS_CNT_EN_MASK			BIT(0)
#define CDC_WSA_FS_CNT_ENABLE			BIT(0)
#define CDC_WSA_FS_CNT_DISABLE			0
#define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL	(0x0008)
#define CDC_WSA_SWR_CLK_EN_MASK			BIT(0)
#define CDC_WSA_SWR_CLK_ENABLE			BIT(0)
#define CDC_WSA_SWR_RST_EN_MASK			BIT(1)
#define CDC_WSA_SWR_RST_ENABLE			BIT(1)
#define CDC_WSA_SWR_RST_DISABLE			0
#define CDC_WSA_TOP_TOP_CFG0			(0x0080)
#define CDC_WSA_TOP_TOP_CFG1			(0x0084)
#define CDC_WSA_TOP_FREQ_MCLK			(0x0088)
#define CDC_WSA_TOP_DEBUG_BUS_SEL		(0x008C)
#define CDC_WSA_TOP_DEBUG_EN0			(0x0090)
#define CDC_WSA_TOP_DEBUG_EN1			(0x0094)
#define CDC_WSA_TOP_DEBUG_DSM_LB		(0x0098)
#define CDC_WSA_TOP_RX_I2S_CTL			(0x009C)
#define CDC_WSA_TOP_TX_I2S_CTL			(0x00A0)
#define CDC_WSA_TOP_I2S_CLK			(0x00A4)
#define CDC_WSA_TOP_I2S_RESET			(0x00A8)
#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0		(0x0100)
#define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK	GENMASK(2, 0)
#define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK	GENMASK(5, 3)
#define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1		(0x0104)
#define CDC_WSA_RX_INTX_2_SEL_MASK		GENMASK(2, 0)
#define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK	GENMASK(5, 3)
#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0		(0x0108)
#define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1		(0x010C)
#define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0		(0x0110)
#define CDC_WSA_RX_MIX_TX1_SEL_MASK		GENMASK(5, 3)
#define CDC_WSA_RX_MIX_TX1_SEL_SHFT		3
#define CDC_WSA_RX_MIX_TX0_SEL_MASK		GENMASK(2, 0)
#define CDC_WSA_RX_INP_MUX_RX_EC_CFG0		(0x0114)
#define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0	(0x0118)
#define CDC_WSA_TX0_SPKR_PROT_PATH_CTL		(0x0244)
#define CDC_WSA_TX_SPKR_PROT_RESET_MASK		BIT(5)
#define CDC_WSA_TX_SPKR_PROT_RESET		BIT(5)
#define CDC_WSA_TX_SPKR_PROT_NO_RESET		0
#define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK	BIT(4)
#define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE		BIT(4)
#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE	0
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK	GENMASK(3, 0)
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K	0
#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0		(0x0248)
#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL		(0x0264)
#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0		(0x0268)
#define CDC_WSA_TX2_SPKR_PROT_PATH_CTL		(0x0284)
#define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0		(0x0288)
#define CDC_WSA_TX3_SPKR_PROT_PATH_CTL		(0x02A4)
#define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0		(0x02A8)
#define CDC_WSA_INTR_CTRL_CFG			(0x0340)
#define CDC_WSA_INTR_CTRL_CLR_COMMIT		(0x0344)
#define CDC_WSA_INTR_CTRL_PIN1_MASK0		(0x0360)
#define CDC_WSA_INTR_CTRL_PIN1_STATUS0		(0x0368)
#define CDC_WSA_INTR_CTRL_PIN1_CLEAR0		(0x0370)
#define CDC_WSA_INTR_CTRL_PIN2_MASK0		(0x0380)
#define CDC_WSA_INTR_CTRL_PIN2_STATUS0		(0x0388)
#define CDC_WSA_INTR_CTRL_PIN2_CLEAR0		(0x0390)
#define CDC_WSA_INTR_CTRL_LEVEL0		(0x03C0)
#define CDC_WSA_INTR_CTRL_BYPASS0		(0x03C8)
#define CDC_WSA_INTR_CTRL_SET0			(0x03D0)
#define CDC_WSA_RX0_RX_PATH_CTL			(0x0400)
#define CDC_WSA_RX_PATH_CLK_EN_MASK		BIT(5)
#define CDC_WSA_RX_PATH_CLK_ENABLE		BIT(5)
#define CDC_WSA_RX_PATH_CLK_DISABLE		0
#define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK	BIT(4)
#define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE		BIT(4)
#define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE	0
#define CDC_WSA_RX0_RX_PATH_CFG0		(0x0404)
#define CDC_WSA_RX_PATH_COMP_EN_MASK		BIT(1)
#define CDC_WSA_RX_PATH_COMP_ENABLE		BIT(1)
#define CDC_WSA_RX_PATH_HD2_EN_MASK		BIT(2)
#define CDC_WSA_RX_PATH_HD2_ENABLE		BIT(2)
#define CDC_WSA_RX_PATH_SPKR_RATE_MASK		BIT(3)
#define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072	BIT(3)
#define CDC_WSA_RX0_RX_PATH_CFG1		(0x0408)
#define CDC_WSA_RX_PATH_SMART_BST_EN_MASK	BIT(0)
#define CDC_WSA_RX_PATH_SMART_BST_ENABLE	BIT(0)
#define CDC_WSA_RX_PATH_SMART_BST_DISABLE	0
#define CDC_WSA_RX0_RX_PATH_CFG2		(0x040C)
#define CDC_WSA_RX0_RX_PATH_CFG3		(0x0410)
#define CDC_WSA_RX_DC_DCOEFF_MASK		GENMASK(1, 0)
#define CDC_WSA_RX0_RX_VOL_CTL			(0x0414)
#define CDC_WSA_RX0_RX_PATH_MIX_CTL		(0x0418)
#define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK		BIT(5)
#define CDC_WSA_RX_PATH_MIX_CLK_ENABLE		BIT(5)
#define CDC_WSA_RX_PATH_MIX_CLK_DISABLE		0
#define CDC_WSA_RX0_RX_PATH_MIX_CFG		(0x041C)
#define CDC_WSA_RX0_RX_VOL_MIX_CTL		(0x0420)
#define CDC_WSA_RX0_RX_PATH_SEC0		(0x0424)
#define CDC_WSA_RX0_RX_PATH_SEC1		(0x0428)
#define CDC_WSA_RX_PGA_HALF_DB_MASK		BIT(0)
#define CDC_WSA_RX_PGA_HALF_DB_ENABLE		BIT(0)
#define CDC_WSA_RX_PGA_HALF_DB_DISABLE		0
#define CDC_WSA_RX0_RX_PATH_SEC2		(0x042C)
#define CDC_WSA_RX0_RX_PATH_SEC3		(0x0430)
#define CDC_WSA_RX_PATH_HD2_SCALE_MASK		GENMASK(1, 0)
#define CDC_WSA_RX_PATH_HD2_ALPHA_MASK		GENMASK(5, 2)
#define CDC_WSA_RX0_RX_PATH_SEC5		(0x0438)
#define CDC_WSA_RX0_RX_PATH_SEC6		(0x043C)
#define CDC_WSA_RX0_RX_PATH_SEC7		(0x0440)
#define CDC_WSA_RX0_RX_PATH_MIX_SEC0		(0x0444)
#define CDC_WSA_RX0_RX_PATH_MIX_SEC1		(0x0448)
#define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL		(0x044C)
#define CDC_WSA_RX_DSMDEM_CLK_EN_MASK		BIT(0)
#define CDC_WSA_RX_DSMDEM_CLK_ENABLE		BIT(0)
#define CDC_WSA_RX1_RX_PATH_CTL			(0x0480)
#define CDC_WSA_RX1_RX_PATH_CFG0		(0x0484)
#define CDC_WSA_RX1_RX_PATH_CFG1		(0x0488)
#define CDC_WSA_RX1_RX_PATH_CFG2		(0x048C)
#define CDC_WSA_RX1_RX_PATH_CFG3		(0x0490)
#define CDC_WSA_RX1_RX_VOL_CTL			(0x0494)
#define CDC_WSA_RX1_RX_PATH_MIX_CTL		(0x0498)
#define CDC_WSA_RX1_RX_PATH_MIX_CFG		(0x049C)
#define CDC_WSA_RX1_RX_VOL_MIX_CTL		(0x04A0)
#define CDC_WSA_RX1_RX_PATH_SEC0		(0x04A4)
#define CDC_WSA_RX1_RX_PATH_SEC1		(0x04A8)
#define CDC_WSA_RX1_RX_PATH_SEC2		(0x04AC)
#define CDC_WSA_RX1_RX_PATH_SEC3		(0x04B0)
#define CDC_WSA_RX1_RX_PATH_SEC5		(0x04B8)
#define CDC_WSA_RX1_RX_PATH_SEC6		(0x04BC)
#define CDC_WSA_RX1_RX_PATH_SEC7		(0x04C0)
#define CDC_WSA_RX1_RX_PATH_MIX_SEC0		(0x04C4)
#define CDC_WSA_RX1_RX_PATH_MIX_SEC1		(0x04C8)
#define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL		(0x04CC)
#define CDC_WSA_BOOST0_BOOST_PATH_CTL		(0x0500)
#define CDC_WSA_BOOST_PATH_CLK_EN_MASK		BIT(4)
#define CDC_WSA_BOOST_PATH_CLK_ENABLE		BIT(4)
#define CDC_WSA_BOOST_PATH_CLK_DISABLE		0
#define CDC_WSA_BOOST0_BOOST_CTL		(0x0504)
#define CDC_WSA_BOOST0_BOOST_CFG1		(0x0508)
#define CDC_WSA_BOOST0_BOOST_CFG2		(0x050C)
#define CDC_WSA_BOOST1_BOOST_PATH_CTL		(0x0540)
#define CDC_WSA_BOOST1_BOOST_CTL		(0x0544)
#define CDC_WSA_BOOST1_BOOST_CFG1		(0x0548)
#define CDC_WSA_BOOST1_BOOST_CFG2		(0x054C)
#define CDC_WSA_COMPANDER0_CTL0			(0x0580)
#define CDC_WSA_COMPANDER_CLK_EN_MASK		BIT(0)
#define CDC_WSA_COMPANDER_CLK_ENABLE		BIT(0)
#define CDC_WSA_COMPANDER_SOFT_RST_MASK		BIT(1)
#define CDC_WSA_COMPANDER_SOFT_RST_ENABLE	BIT(1)
#define CDC_WSA_COMPANDER_HALT_MASK		BIT(2)
#define CDC_WSA_COMPANDER_HALT			BIT(2)
#define CDC_WSA_COMPANDER0_CTL1			(0x0584)
#define CDC_WSA_COMPANDER0_CTL2			(0x0588)
#define CDC_WSA_COMPANDER0_CTL3			(0x058C)
#define CDC_WSA_COMPANDER0_CTL4			(0x0590)
#define CDC_WSA_COMPANDER0_CTL5			(0x0594)
#define CDC_WSA_COMPANDER0_CTL6			(0x0598)
#define CDC_WSA_COMPANDER0_CTL7			(0x059C)
#define CDC_WSA_COMPANDER1_CTL0			(0x05C0)
#define CDC_WSA_COMPANDER1_CTL1			(0x05C4)
#define CDC_WSA_COMPANDER1_CTL2			(0x05C8)
#define CDC_WSA_COMPANDER1_CTL3			(0x05CC)
#define CDC_WSA_COMPANDER1_CTL4			(0x05D0)
#define CDC_WSA_COMPANDER1_CTL5			(0x05D4)
#define CDC_WSA_COMPANDER1_CTL6			(0x05D8)
#define CDC_WSA_COMPANDER1_CTL7			(0x05DC)
#define CDC_WSA_SOFTCLIP0_CRC			(0x0600)
#define CDC_WSA_SOFTCLIP_CLK_EN_MASK		BIT(0)
#define CDC_WSA_SOFTCLIP_CLK_ENABLE		BIT(0)
#define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL		(0x0604)
#define CDC_WSA_SOFTCLIP_EN_MASK		BIT(0)
#define CDC_WSA_SOFTCLIP_ENABLE			BIT(0)
#define CDC_WSA_SOFTCLIP1_CRC			(0x0640)
#define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL		(0x0644)
#define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL	(0x0680)
#define CDC_WSA_EC_HQ_EC_CLK_EN_MASK		BIT(0)
#define CDC_WSA_EC_HQ_EC_CLK_ENABLE		BIT(0)
#define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0		(0x0684)
#define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK	GENMASK(4, 1)
#define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K	BIT(3)
#define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL	(0x06C0)
#define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0		(0x06C4)
#define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL	(0x0700)
#define CDC_WSA_SPLINE_ASRC0_CTL0		(0x0704)
#define CDC_WSA_SPLINE_ASRC0_CTL1		(0x0708)
#define CDC_WSA_SPLINE_ASRC0_FIFO_CTL		(0x070C)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB	(0x0710)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB	(0x0714)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB	(0x0718)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB	(0x071C)
#define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO		(0x0720)
#define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL		(0x0740)
#define CDC_WSA_SPLINE_ASRC1_CTL0		(0x0744)
#define CDC_WSA_SPLINE_ASRC1_CTL1		(0x0748)
#define CDC_WSA_SPLINE_ASRC1_FIFO_CTL		(0x074C)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
#define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO	(0x0760)
#define WSA_MAX_OFFSET				(0x0760)

#define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
#define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
		SNDRV_PCM_FMTBIT_S24_LE |\
		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)

#define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
			SNDRV_PCM_RATE_48000)
#define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
		SNDRV_PCM_FMTBIT_S24_LE |\
		SNDRV_PCM_FMTBIT_S24_3LE)

#define NUM_INTERPOLATORS 2
#define WSA_NUM_CLKS_MAX	5
#define WSA_MACRO_MCLK_FREQ 19200000
#define WSA_MACRO_MUX_INP_MASK2 0x38
#define WSA_MACRO_MUX_CFG_OFFSET 0x8
#define WSA_MACRO_MUX_CFG1_OFFSET 0x4
#define WSA_MACRO_RX_COMP_OFFSET 0x40
#define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40
#define WSA_MACRO_RX_PATH_OFFSET 0x80
#define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
#define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
#define WSA_MACRO_FS_RATE_MASK 0x0F
#define WSA_MACRO_EC_MIX_TX0_MASK 0x03
#define WSA_MACRO_EC_MIX_TX1_MASK 0x18
#define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2

enum {
	WSA_MACRO_GAIN_OFFSET_M1P5_DB,
	WSA_MACRO_GAIN_OFFSET_0_DB,
};
enum {
	WSA_MACRO_RX0 = 0,
	WSA_MACRO_RX1,
	WSA_MACRO_RX_MIX,
	WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX,
	WSA_MACRO_RX_MIX1,
	WSA_MACRO_RX_MAX,
};

enum {
	WSA_MACRO_TX0 = 0,
	WSA_MACRO_TX1,
	WSA_MACRO_TX_MAX,
};

enum {
	WSA_MACRO_EC0_MUX = 0,
	WSA_MACRO_EC1_MUX,
	WSA_MACRO_EC_MUX_MAX,
};

enum {
	WSA_MACRO_COMP1, /* SPK_L */
	WSA_MACRO_COMP2, /* SPK_R */
	WSA_MACRO_COMP_MAX
};

enum {
	WSA_MACRO_SOFTCLIP0, /* RX0 */
	WSA_MACRO_SOFTCLIP1, /* RX1 */
	WSA_MACRO_SOFTCLIP_MAX
};

enum {
	INTn_1_INP_SEL_ZERO = 0,
	INTn_1_INP_SEL_RX0,
	INTn_1_INP_SEL_RX1,
	INTn_1_INP_SEL_RX2,
	INTn_1_INP_SEL_RX3,
	INTn_1_INP_SEL_DEC0,
	INTn_1_INP_SEL_DEC1,
};

enum {
	INTn_2_INP_SEL_ZERO = 0,
	INTn_2_INP_SEL_RX0,
	INTn_2_INP_SEL_RX1,
	INTn_2_INP_SEL_RX2,
	INTn_2_INP_SEL_RX3,
};

struct interp_sample_rate {
	int sample_rate;
	int rate_val;
};

static struct interp_sample_rate int_prim_sample_rate_val[] = {
	{8000, 0x0},	/* 8K */
	{16000, 0x1},	/* 16K */
	{24000, -EINVAL},/* 24K */
	{32000, 0x3},	/* 32K */
	{48000, 0x4},	/* 48K */
	{96000, 0x5},	/* 96K */
	{192000, 0x6},	/* 192K */
	{384000, 0x7},	/* 384K */
	{44100, 0x8}, /* 44.1K */
};

static struct interp_sample_rate int_mix_sample_rate_val[] = {
	{48000, 0x4},	/* 48K */
	{96000, 0x5},	/* 96K */
	{192000, 0x6},	/* 192K */
};

enum {
	WSA_MACRO_AIF_INVALID = 0,
	WSA_MACRO_AIF1_PB,
	WSA_MACRO_AIF_MIX1_PB,
	WSA_MACRO_AIF_VI,
	WSA_MACRO_AIF_ECHO,
	WSA_MACRO_MAX_DAIS,
};

struct wsa_macro {
	struct device *dev;
	int comp_enabled[WSA_MACRO_COMP_MAX];
	int ec_hq[WSA_MACRO_RX1 + 1];
	u16 prim_int_users[WSA_MACRO_RX1 + 1];
	u16 wsa_mclk_users;
	unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
	unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
	int rx_port_value[WSA_MACRO_RX_MAX];
	int ear_spkr_gain;
	int spkr_gain_offset;
	int spkr_mode;
	int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
	int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
	struct regmap *regmap;
	struct clk *mclk;
	struct clk *npl;
	struct clk *macro;
	struct clk *dcodec;
	struct clk *fsgen;
	struct clk_hw hw;
};
#define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)

static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);

static const char *const rx_text[] = {
	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
};

static const char *const rx_mix_text[] = {
	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
};

static const char *const rx_mix_ec_text[] = {
	"ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
};

static const char *const rx_mux_text[] = {
	"ZERO", "AIF1_PB", "AIF_MIX1_PB"
};

static const char *const rx_sidetone_mix_text[] = {
	"ZERO", "SRC0"
};

static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
	"G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
	"G_4_DB", "G_5_DB", "G_6_DB"
};

static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
				wsa_macro_ear_spkr_pa_gain_text);

/* RX INT0 */
static const struct soc_enum rx0_prim_inp0_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
		0, 7, rx_text);

static const struct soc_enum rx0_prim_inp1_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
		3, 7, rx_text);

static const struct soc_enum rx0_prim_inp2_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
		3, 7, rx_text);

static const struct soc_enum rx0_mix_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
		0, 5, rx_mix_text);

static const struct soc_enum rx0_sidetone_mix_enum =
	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);

static const struct snd_kcontrol_new rx0_prim_inp0_mux =
	SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);

static const struct snd_kcontrol_new rx0_prim_inp1_mux =
	SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);

static const struct snd_kcontrol_new rx0_prim_inp2_mux =
	SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);

static const struct snd_kcontrol_new rx0_mix_mux =
	SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);

static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
	SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);

/* RX INT1 */
static const struct soc_enum rx1_prim_inp0_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
		0, 7, rx_text);

static const struct soc_enum rx1_prim_inp1_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
		3, 7, rx_text);

static const struct soc_enum rx1_prim_inp2_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
		3, 7, rx_text);

static const struct soc_enum rx1_mix_chain_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
		0, 5, rx_mix_text);

static const struct snd_kcontrol_new rx1_prim_inp0_mux =
	SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);

static const struct snd_kcontrol_new rx1_prim_inp1_mux =
	SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);

static const struct snd_kcontrol_new rx1_prim_inp2_mux =
	SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);

static const struct snd_kcontrol_new rx1_mix_mux =
	SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum);

static const struct soc_enum rx_mix_ec0_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
		0, 3, rx_mix_ec_text);

static const struct soc_enum rx_mix_ec1_enum =
	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
		3, 3, rx_mix_ec_text);

static const struct snd_kcontrol_new rx_mix_ec0_mux =
	SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);

static const struct snd_kcontrol_new rx_mix_ec1_mux =
	SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);

static const struct reg_default wsa_defaults[] = {
	/* WSA Macro */
	{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
	{ CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
	{ CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
	{ CDC_WSA_TOP_TOP_CFG0, 0x00},
	{ CDC_WSA_TOP_TOP_CFG1, 0x00},
	{ CDC_WSA_TOP_FREQ_MCLK, 0x00},
	{ CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
	{ CDC_WSA_TOP_DEBUG_EN0, 0x00},
	{ CDC_WSA_TOP_DEBUG_EN1, 0x00},
	{ CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
	{ CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
	{ CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
	{ CDC_WSA_TOP_I2S_CLK, 0x02},
	{ CDC_WSA_TOP_I2S_RESET, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
	{ CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
	{ CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
	{ CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
	{ CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
	{ CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
	{ CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
	{ CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
	{ CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
	{ CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
	{ CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
	{ CDC_WSA_INTR_CTRL_CFG, 0x00},
	{ CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
	{ CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
	{ CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
	{ CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
	{ CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
	{ CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
	{ CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
	{ CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
	{ CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
	{ CDC_WSA_INTR_CTRL_SET0, 0x00},
	{ CDC_WSA_RX0_RX_PATH_CTL, 0x04},
	{ CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
	{ CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
	{ CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
	{ CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
	{ CDC_WSA_RX0_RX_VOL_CTL, 0x00},
	{ CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
	{ CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
	{ CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
	{ CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
	{ CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
	{ CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
	{ CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
	{ CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
	{ CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
	{ CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
	{ CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
	{ CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
	{ CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
	{ CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
	{ CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
	{ CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
	{ CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
	{ CDC_WSA_RX1_RX_VOL_CTL, 0x00},
	{ CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
	{ CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
	{ CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
	{ CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
	{ CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
	{ CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
	{ CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
	{ CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
	{ CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
	{ CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
	{ CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
	{ CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
	{ CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
	{ CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
	{ CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
	{ CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
	{ CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
	{ CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
	{ CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
	{ CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
	{ CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
	{ CDC_WSA_COMPANDER0_CTL0, 0x60},
	{ CDC_WSA_COMPANDER0_CTL1, 0xDB},
	{ CDC_WSA_COMPANDER0_CTL2, 0xFF},
	{ CDC_WSA_COMPANDER0_CTL3, 0x35},
	{ CDC_WSA_COMPANDER0_CTL4, 0xFF},
	{ CDC_WSA_COMPANDER0_CTL5, 0x00},
	{ CDC_WSA_COMPANDER0_CTL6, 0x01},
	{ CDC_WSA_COMPANDER0_CTL7, 0x28},
	{ CDC_WSA_COMPANDER1_CTL0, 0x60},
	{ CDC_WSA_COMPANDER1_CTL1, 0xDB},
	{ CDC_WSA_COMPANDER1_CTL2, 0xFF},
	{ CDC_WSA_COMPANDER1_CTL3, 0x35},
	{ CDC_WSA_COMPANDER1_CTL4, 0xFF},
	{ CDC_WSA_COMPANDER1_CTL5, 0x00},
	{ CDC_WSA_COMPANDER1_CTL6, 0x01},
	{ CDC_WSA_COMPANDER1_CTL7, 0x28},
	{ CDC_WSA_SOFTCLIP0_CRC, 0x00},
	{ CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
	{ CDC_WSA_SOFTCLIP1_CRC, 0x00},
	{ CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
	{ CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
	{ CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
	{ CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
	{ CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
	{ CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
	{ CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
};

static bool wsa_is_wronly_register(struct device *dev,
					unsigned int reg)
{
	switch (reg) {
	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
		return true;
	}

	return false;
}

static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
	case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
	case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
	case CDC_WSA_TOP_TOP_CFG0:
	case CDC_WSA_TOP_TOP_CFG1:
	case CDC_WSA_TOP_FREQ_MCLK:
	case CDC_WSA_TOP_DEBUG_BUS_SEL:
	case CDC_WSA_TOP_DEBUG_EN0:
	case CDC_WSA_TOP_DEBUG_EN1:
	case CDC_WSA_TOP_DEBUG_DSM_LB:
	case CDC_WSA_TOP_RX_I2S_CTL:
	case CDC_WSA_TOP_TX_I2S_CTL:
	case CDC_WSA_TOP_I2S_CLK:
	case CDC_WSA_TOP_I2S_RESET:
	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
	case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
	case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
	case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
	case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
	case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
	case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
	case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
	case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
	case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
	case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
	case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
	case CDC_WSA_INTR_CTRL_CFG:
	case CDC_WSA_INTR_CTRL_PIN1_MASK0:
	case CDC_WSA_INTR_CTRL_PIN2_MASK0:
	case CDC_WSA_INTR_CTRL_LEVEL0:
	case CDC_WSA_INTR_CTRL_BYPASS0:
	case CDC_WSA_INTR_CTRL_SET0:
	case CDC_WSA_RX0_RX_PATH_CTL:
	case CDC_WSA_RX0_RX_PATH_CFG0:
	case CDC_WSA_RX0_RX_PATH_CFG1:
	case CDC_WSA_RX0_RX_PATH_CFG2:
	case CDC_WSA_RX0_RX_PATH_CFG3:
	case CDC_WSA_RX0_RX_VOL_CTL:
	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
	case CDC_WSA_RX0_RX_PATH_MIX_CFG:
	case CDC_WSA_RX0_RX_VOL_MIX_CTL:
	case CDC_WSA_RX0_RX_PATH_SEC0:
	case CDC_WSA_RX0_RX_PATH_SEC1:
	case CDC_WSA_RX0_RX_PATH_SEC2:
	case CDC_WSA_RX0_RX_PATH_SEC3:
	case CDC_WSA_RX0_RX_PATH_SEC5:
	case CDC_WSA_RX0_RX_PATH_SEC6:
	case CDC_WSA_RX0_RX_PATH_SEC7:
	case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
	case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
	case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
	case CDC_WSA_RX1_RX_PATH_CTL:
	case CDC_WSA_RX1_RX_PATH_CFG0:
	case CDC_WSA_RX1_RX_PATH_CFG1:
	case CDC_WSA_RX1_RX_PATH_CFG2:
	case CDC_WSA_RX1_RX_PATH_CFG3:
	case CDC_WSA_RX1_RX_VOL_CTL:
	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
	case CDC_WSA_RX1_RX_PATH_MIX_CFG:
	case CDC_WSA_RX1_RX_VOL_MIX_CTL:
	case CDC_WSA_RX1_RX_PATH_SEC0:
	case CDC_WSA_RX1_RX_PATH_SEC1:
	case CDC_WSA_RX1_RX_PATH_SEC2:
	case CDC_WSA_RX1_RX_PATH_SEC3:
	case CDC_WSA_RX1_RX_PATH_SEC5:
	case CDC_WSA_RX1_RX_PATH_SEC6:
	case CDC_WSA_RX1_RX_PATH_SEC7:
	case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
	case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
	case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
	case CDC_WSA_BOOST0_BOOST_PATH_CTL:
	case CDC_WSA_BOOST0_BOOST_CTL:
	case CDC_WSA_BOOST0_BOOST_CFG1:
	case CDC_WSA_BOOST0_BOOST_CFG2:
	case CDC_WSA_BOOST1_BOOST_PATH_CTL:
	case CDC_WSA_BOOST1_BOOST_CTL:
	case CDC_WSA_BOOST1_BOOST_CFG1:
	case CDC_WSA_BOOST1_BOOST_CFG2:
	case CDC_WSA_COMPANDER0_CTL0:
	case CDC_WSA_COMPANDER0_CTL1:
	case CDC_WSA_COMPANDER0_CTL2:
	case CDC_WSA_COMPANDER0_CTL3:
	case CDC_WSA_COMPANDER0_CTL4:
	case CDC_WSA_COMPANDER0_CTL5:
	case CDC_WSA_COMPANDER0_CTL7:
	case CDC_WSA_COMPANDER1_CTL0:
	case CDC_WSA_COMPANDER1_CTL1:
	case CDC_WSA_COMPANDER1_CTL2:
	case CDC_WSA_COMPANDER1_CTL3:
	case CDC_WSA_COMPANDER1_CTL4:
	case CDC_WSA_COMPANDER1_CTL5:
	case CDC_WSA_COMPANDER1_CTL7:
	case CDC_WSA_SOFTCLIP0_CRC:
	case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
	case CDC_WSA_SOFTCLIP1_CRC:
	case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
	case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
	case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
	case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
	case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
	case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
	case CDC_WSA_SPLINE_ASRC0_CTL0:
	case CDC_WSA_SPLINE_ASRC0_CTL1:
	case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
	case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
	case CDC_WSA_SPLINE_ASRC1_CTL0:
	case CDC_WSA_SPLINE_ASRC1_CTL1:
	case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
		return true;
	}

	return false;
}

static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
{
	bool ret;

	ret = wsa_is_rw_register(dev, reg);
	if (!ret)
		return wsa_is_wronly_register(dev, reg);

	return ret;
}

static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
	case CDC_WSA_COMPANDER0_CTL6:
	case CDC_WSA_COMPANDER1_CTL6:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
		return true;
	}

	return wsa_is_rw_register(dev, reg);
}

static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
{
	/* Update volatile list for rx/tx macros */
	switch (reg) {
	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
	case CDC_WSA_COMPANDER0_CTL6:
	case CDC_WSA_COMPANDER1_CTL6:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
		return true;
	}
	return false;
}

static const struct regmap_config wsa_regmap_config = {
	.name = "wsa_macro",
	.reg_bits = 16,
	.val_bits = 32, /* 8 but with 32 bit read/write */
	.reg_stride = 4,
	.cache_type = REGCACHE_FLAT,
	.reg_defaults = wsa_defaults,
	.num_reg_defaults = ARRAY_SIZE(wsa_defaults),
	.max_register = WSA_MAX_OFFSET,
	.writeable_reg = wsa_is_writeable_register,
	.volatile_reg = wsa_is_volatile_register,
	.readable_reg = wsa_is_readable_register,
};

/**
 * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
 * settings based on speaker mode.
 *
 * @component: codec instance
 * @mode: Indicates speaker configuration mode.
 *
 * Returns 0 on success or -EINVAL on error.
 */
int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
{
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	wsa->spkr_mode = mode;

	switch (mode) {
	case WSA_MACRO_SPKR_MODE_1:
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
		break;
	default:
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
		break;
	}
	return 0;
}
EXPORT_SYMBOL(wsa_macro_set_spkr_mode);

static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
						u8 int_prim_fs_rate_reg_val,
						u32 sample_rate)
{
	u8 int_1_mix1_inp;
	u32 j, port;
	u16 int_mux_cfg0, int_mux_cfg1;
	u16 int_fs_reg;
	u8 inp0_sel, inp1_sel, inp2_sel;
	struct snd_soc_component *component = dai->component;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
		int_1_mix1_inp = port;
		if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) {
			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
				__func__, dai->id);
			return -EINVAL;
		}

		int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;

		/*
		 * Loop through all interpolator MUX inputs and find out
		 * to which interpolator input, the cdc_dma rx port
		 * is connected
		 */
		for (j = 0; j < NUM_INTERPOLATORS; j++) {
			int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
			inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 
								CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
			inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 
								CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
			inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
								CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);

			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
				int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
					     WSA_MACRO_RX_PATH_OFFSET * j;
				/* sample_rate is in Hz */
				snd_soc_component_update_bits(component, int_fs_reg,
							      WSA_MACRO_FS_RATE_MASK,
							      int_prim_fs_rate_reg_val);
			}
			int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
		}
	}

	return 0;
}

static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
					       u8 int_mix_fs_rate_reg_val,
					       u32 sample_rate)
{
	u8 int_2_inp;
	u32 j, port;
	u16 int_mux_cfg1, int_fs_reg;
	u8 int_mux_cfg1_val;
	struct snd_soc_component *component = dai->component;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
		int_2_inp = port;
		if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) {
			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
				__func__, dai->id);
			return -EINVAL;
		}

		int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
		for (j = 0; j < NUM_INTERPOLATORS; j++) {
			int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
									CDC_WSA_RX_INTX_2_SEL_MASK);

			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
				int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
					WSA_MACRO_RX_PATH_OFFSET * j;

				snd_soc_component_update_bits(component,
						      int_fs_reg,
						      WSA_MACRO_FS_RATE_MASK,
						      int_mix_fs_rate_reg_val);
			}
			int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
		}
	}
	return 0;
}

static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
					   u32 sample_rate)
{
	int rate_val = 0;
	int i, ret;

	/* set mixing path rate */
	for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
		if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
			rate_val = int_mix_sample_rate_val[i].rate_val;
			break;
		}
	}
	if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
		goto prim_rate;

	ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
	if (ret < 0)
		return ret;
prim_rate:
	/* set primary path sample rate */
	for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
		if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
			rate_val = int_prim_sample_rate_val[i].rate_val;
			break;
		}
	}
	if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
		return -EINVAL;

	ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);

	return ret;
}

static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
			       struct snd_pcm_hw_params *params,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_component *component = dai->component;
	int ret;

	switch (substream->stream) {
	case SNDRV_PCM_STREAM_PLAYBACK:
		ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
		if (ret) {
			dev_err(component->dev,
				"%s: cannot set sample rate: %u\n",
				__func__, params_rate(params));
			return ret;
		}
		break;
	default:
		break;
	}
	return 0;
}

static int wsa_macro_get_channel_map(struct snd_soc_dai *dai,
				     unsigned int *tx_num, unsigned int *tx_slot,
				     unsigned int *rx_num, unsigned int *rx_slot)
{
	struct snd_soc_component *component = dai->component;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	u16 val, mask = 0, cnt = 0, temp;

	switch (dai->id) {
	case WSA_MACRO_AIF_VI:
		*tx_slot = wsa->active_ch_mask[dai->id];
		*tx_num = wsa->active_ch_cnt[dai->id];
		break;
	case WSA_MACRO_AIF1_PB:
	case WSA_MACRO_AIF_MIX1_PB:
		for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
					WSA_MACRO_RX_MAX) {
			mask |= (1 << temp);
			if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
				break;
		}
		if (mask & 0x0C)
			mask = mask >> 0x2;
		*rx_slot = mask;
		*rx_num = cnt;
		break;
	case WSA_MACRO_AIF_ECHO:
		val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
		if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
			mask |= 0x2;
			cnt++;
		}
		if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
			mask |= 0x1;
			cnt++;
		}
		*tx_slot = mask;
		*tx_num = cnt;
		break;
	default:
		dev_err(component->dev, "%s: Invalid AIF\n", __func__);
		break;
	}
	return 0;
}

static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
	.hw_params = wsa_macro_hw_params,
	.get_channel_map = wsa_macro_get_channel_map,
};

static struct snd_soc_dai_driver wsa_macro_dai[] = {
	{
		.name = "wsa_macro_rx1",
		.id = WSA_MACRO_AIF1_PB,
		.playback = {
			.stream_name = "WSA_AIF1 Playback",
			.rates = WSA_MACRO_RX_RATES,
			.formats = WSA_MACRO_RX_FORMATS,
			.rate_max = 384000,
			.rate_min = 8000,
			.channels_min = 1,
			.channels_max = 2,
		},
		.ops = &wsa_macro_dai_ops,
	},
	{
		.name = "wsa_macro_rx_mix",
		.id = WSA_MACRO_AIF_MIX1_PB,
		.playback = {
			.stream_name = "WSA_AIF_MIX1 Playback",
			.rates = WSA_MACRO_RX_MIX_RATES,
			.formats = WSA_MACRO_RX_FORMATS,
			.rate_max = 192000,
			.rate_min = 48000,
			.channels_min = 1,
			.channels_max = 2,
		},
		.ops = &wsa_macro_dai_ops,
	},
	{
		.name = "wsa_macro_vifeedback",
		.id = WSA_MACRO_AIF_VI,
		.capture = {
			.stream_name = "WSA_AIF_VI Capture",
			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
			.formats = WSA_MACRO_RX_FORMATS,
			.rate_max = 48000,
			.rate_min = 8000,
			.channels_min = 1,
			.channels_max = 4,
		},
		.ops = &wsa_macro_dai_ops,
	},
	{
		.name = "wsa_macro_echo",
		.id = WSA_MACRO_AIF_ECHO,
		.capture = {
			.stream_name = "WSA_AIF_ECHO Capture",
			.rates = WSA_MACRO_ECHO_RATES,
			.formats = WSA_MACRO_ECHO_FORMATS,
			.rate_max = 48000,
			.rate_min = 8000,
			.channels_min = 1,
			.channels_max = 2,
		},
		.ops = &wsa_macro_dai_ops,
	},
};

static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
{
	struct regmap *regmap = wsa->regmap;

	if (mclk_enable) {
		if (wsa->wsa_mclk_users == 0) {
			regcache_mark_dirty(regmap);
			regcache_sync(regmap);
			/* 9.6MHz MCLK, set value 0x00 if other frequency */
			regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
			regmap_update_bits(regmap,
					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
					   CDC_WSA_MCLK_EN_MASK,
					   CDC_WSA_MCLK_ENABLE);
			regmap_update_bits(regmap,
					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
					   CDC_WSA_FS_CNT_EN_MASK,
					   CDC_WSA_FS_CNT_ENABLE);
		}
		wsa->wsa_mclk_users++;
	} else {
		if (wsa->wsa_mclk_users <= 0) {
			dev_err(wsa->dev, "clock already disabled\n");
			wsa->wsa_mclk_users = 0;
			return;
		}
		wsa->wsa_mclk_users--;
		if (wsa->wsa_mclk_users == 0) {
			regmap_update_bits(regmap,
					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
					   CDC_WSA_FS_CNT_EN_MASK,
					   CDC_WSA_FS_CNT_DISABLE);
			regmap_update_bits(regmap,
					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
					   CDC_WSA_MCLK_EN_MASK,
					   CDC_WSA_MCLK_DISABLE);
		}
	}
}

static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
				struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
	return 0;
}

static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
					struct snd_kcontrol *kcontrol,
					int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	u32 tx_reg0, tx_reg1;

	if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
		tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
		tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
	} else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
		tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
		tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
	}

	switch (event) {
	case SND_SOC_DAPM_POST_PMU:
			/* Enable V&I sensing */
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_RESET);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_RESET);
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
		break;
	case SND_SOC_DAPM_POST_PMD:
		/* Disable V&I sensing */
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_RESET);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
					      CDC_WSA_TX_SPKR_PROT_RESET);
		snd_soc_component_update_bits(component, tx_reg0,
					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
		snd_soc_component_update_bits(component, tx_reg1,
					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
		break;
	}

	return 0;
}

static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
				     struct snd_kcontrol *kcontrol, int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	u16 path_reg, gain_reg;
	int val;

	switch (w->shift) {
	case WSA_MACRO_RX_MIX0:
		path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
		gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
		break;
	case WSA_MACRO_RX_MIX1:
		path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
		gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
		break;
	default:
		return 0;
	}

	switch (event) {
	case SND_SOC_DAPM_POST_PMU:
		val = snd_soc_component_read(component, gain_reg);
		snd_soc_component_write(component, gain_reg, val);
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component, path_reg,
					      CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
					      CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
		break;
	}

	return 0;
}

static void wsa_macro_hd2_control(struct snd_soc_component *component,
				  u16 reg, int event)
{
	u16 hd2_scale_reg;
	u16 hd2_enable_reg;

	if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
		hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
		hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
	}
	if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
		hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
		hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
	}

	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
		snd_soc_component_update_bits(component, hd2_scale_reg,
					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
					      0x10);
		snd_soc_component_update_bits(component, hd2_scale_reg,
					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
					      0x1);
		snd_soc_component_update_bits(component, hd2_enable_reg,
					      CDC_WSA_RX_PATH_HD2_EN_MASK,
					      CDC_WSA_RX_PATH_HD2_ENABLE);
	}

	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
		snd_soc_component_update_bits(component, hd2_enable_reg,
					      CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
		snd_soc_component_update_bits(component, hd2_scale_reg,
					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
					      0);
		snd_soc_component_update_bits(component, hd2_scale_reg,
					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
					      0);
	}
}

static int wsa_macro_config_compander(struct snd_soc_component *component,
				      int comp, int event)
{
	u16 comp_ctl0_reg, rx_path_cfg0_reg;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	if (!wsa->comp_enabled[comp])
		return 0;

	comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
					(comp * WSA_MACRO_RX_COMP_OFFSET);
	rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
					(comp * WSA_MACRO_RX_PATH_OFFSET);

	if (SND_SOC_DAPM_EVENT_ON(event)) {
		/* Enable Compander Clock */
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_CLK_EN_MASK,
					      CDC_WSA_COMPANDER_CLK_ENABLE);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
					      0);
		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
					      CDC_WSA_RX_PATH_COMP_EN_MASK,
					      CDC_WSA_RX_PATH_COMP_ENABLE);
	}

	if (SND_SOC_DAPM_EVENT_OFF(event)) {
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_HALT_MASK,
					      CDC_WSA_COMPANDER_HALT);
		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
					      CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
					      0);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					      CDC_WSA_COMPANDER_HALT_MASK, 0);
	}

	return 0;
}

static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
					 struct wsa_macro *wsa,
					 int path,
					 bool enable)
{
	u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC +
			(path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
	u8 softclip_mux_mask = (1 << path);
	u8 softclip_mux_value = (1 << path);

	if (enable) {
		if (wsa->softclip_clk_users[path] == 0) {
			snd_soc_component_update_bits(component,
						softclip_clk_reg,
						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
						CDC_WSA_SOFTCLIP_CLK_ENABLE);
			snd_soc_component_update_bits(component,
				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
				softclip_mux_mask, softclip_mux_value);
		}
		wsa->softclip_clk_users[path]++;
	} else {
		wsa->softclip_clk_users[path]--;
		if (wsa->softclip_clk_users[path] == 0) {
			snd_soc_component_update_bits(component,
						softclip_clk_reg,
						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
						0);
			snd_soc_component_update_bits(component,
				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
				softclip_mux_mask, 0x00);
		}
	}
}

static int wsa_macro_config_softclip(struct snd_soc_component *component,
				     int path, int event)
{
	u16 softclip_ctrl_reg;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	int softclip_path = 0;

	if (path == WSA_MACRO_COMP1)
		softclip_path = WSA_MACRO_SOFTCLIP0;
	else if (path == WSA_MACRO_COMP2)
		softclip_path = WSA_MACRO_SOFTCLIP1;

	if (!wsa->is_softclip_on[softclip_path])
		return 0;

	softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
				(softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET);

	if (SND_SOC_DAPM_EVENT_ON(event)) {
		/* Enable Softclip clock and mux */
		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
					      true);
		/* Enable Softclip control */
		snd_soc_component_update_bits(component, softclip_ctrl_reg,
					      CDC_WSA_SOFTCLIP_EN_MASK,
					      CDC_WSA_SOFTCLIP_ENABLE);
	}

	if (SND_SOC_DAPM_EVENT_OFF(event)) {
		snd_soc_component_update_bits(component, softclip_ctrl_reg,
					      CDC_WSA_SOFTCLIP_EN_MASK, 0);
		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
					      false);
	}

	return 0;
}

static bool wsa_macro_adie_lb(struct snd_soc_component *component,
			      int interp_idx)
{
	u16 int_mux_cfg0,  int_mux_cfg1;
	u8 int_n_inp0, int_n_inp1, int_n_inp2;

	int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
	int_mux_cfg1 = int_mux_cfg0 + 4;

	int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
						  CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
		int_n_inp0 == INTn_1_INP_SEL_DEC1)
		return true;

	int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
						  CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
	if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
		int_n_inp1 == INTn_1_INP_SEL_DEC1)
		return true;

	int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
						  CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
	if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
		int_n_inp2 == INTn_1_INP_SEL_DEC1)
		return true;

	return false;
}

static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w,
				      struct snd_kcontrol *kcontrol,
				      int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	u16 reg;

	reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift;
	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		if (wsa_macro_adie_lb(component, w->shift)) {
			snd_soc_component_update_bits(component, reg,
					     CDC_WSA_RX_PATH_CLK_EN_MASK,
					     CDC_WSA_RX_PATH_CLK_ENABLE);
		}
		break;
	default:
		break;
	}
	return 0;
}

static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
{
	u16 prim_int_reg = 0;

	switch (reg) {
	case CDC_WSA_RX0_RX_PATH_CTL:
	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
		prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
		*ind = 0;
		break;
	case CDC_WSA_RX1_RX_PATH_CTL:
	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
		prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
		*ind = 1;
		break;
	}

	return prim_int_reg;
}

static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
					      u16 reg, int event)
{
	u16 prim_int_reg;
	u16 ind = 0;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		wsa->prim_int_users[ind]++;
		if (wsa->prim_int_users[ind] == 1) {
			snd_soc_component_update_bits(component,
						      prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
						      CDC_WSA_RX_DC_DCOEFF_MASK,
						      0x3);
			snd_soc_component_update_bits(component, prim_int_reg,
					CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
					CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
			wsa_macro_hd2_control(component, prim_int_reg, event);
			snd_soc_component_update_bits(component,
				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
				CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
				CDC_WSA_RX_DSMDEM_CLK_ENABLE);
		}
		if ((reg != prim_int_reg) &&
		    ((snd_soc_component_read(
				component, prim_int_reg)) & 0x10))
			snd_soc_component_update_bits(component, reg,
					0x10, 0x10);
		break;
	case SND_SOC_DAPM_POST_PMD:
		wsa->prim_int_users[ind]--;
		if (wsa->prim_int_users[ind] == 0) {
			snd_soc_component_update_bits(component,
				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
				CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
			wsa_macro_hd2_control(component, prim_int_reg, event);
		}
		break;
	}

	return 0;
}

static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
					  struct wsa_macro *wsa,
					  int event, int gain_reg)
{
	int comp_gain_offset, val;

	switch (wsa->spkr_mode) {
	/* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
	case WSA_MACRO_SPKR_MODE_1:
		comp_gain_offset = -12;
		break;
	/* Default case compander gain is 15 dB */
	default:
		comp_gain_offset = -15;
		break;
	}

	switch (event) {
	case SND_SOC_DAPM_POST_PMU:
		/* Apply ear spkr gain only if compander is enabled */
		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
		    (wsa->ear_spkr_gain != 0)) {
			/* For example, val is -8(-12+5-1) for 4dB of gain */
			val = comp_gain_offset + wsa->ear_spkr_gain - 1;
			snd_soc_component_write(component, gain_reg, val);
		}
		break;
	case SND_SOC_DAPM_POST_PMD:
		/*
		 * Reset RX0 volume to 0 dB if compander is enabled and
		 * ear_spkr_gain is non-zero.
		 */
		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
		    (wsa->ear_spkr_gain != 0)) {
			snd_soc_component_write(component, gain_reg, 0x0);
		}
		break;
	}

	return 0;
}

static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
					 struct snd_kcontrol *kcontrol,
					 int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	u16 gain_reg;
	u16 reg;
	int val;
	int offset_val = 0;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	if (w->shift == WSA_MACRO_COMP1) {
		reg = CDC_WSA_RX0_RX_PATH_CTL;
		gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
	} else if (w->shift == WSA_MACRO_COMP2) {
		reg = CDC_WSA_RX1_RX_PATH_CTL;
		gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
	}

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		/* Reset if needed */
		wsa_macro_enable_prim_interpolator(component, reg, event);
		break;
	case SND_SOC_DAPM_POST_PMU:
		wsa_macro_config_compander(component, w->shift, event);
		wsa_macro_config_softclip(component, w->shift, event);
		/* apply gain after int clk is enabled */
		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
			snd_soc_component_update_bits(component,
					CDC_WSA_RX0_RX_PATH_SEC1,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX1_RX_PATH_SEC1,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
			offset_val = -2;
		}
		val = snd_soc_component_read(component, gain_reg);
		val += offset_val;
		snd_soc_component_write(component, gain_reg, val);
		wsa_macro_config_ear_spkr_gain(component, wsa,
						event, gain_reg);
		break;
	case SND_SOC_DAPM_POST_PMD:
		wsa_macro_config_compander(component, w->shift, event);
		wsa_macro_config_softclip(component, w->shift, event);
		wsa_macro_enable_prim_interpolator(component, reg, event);
		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
			snd_soc_component_update_bits(component,
					CDC_WSA_RX0_RX_PATH_SEC1,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX1_RX_PATH_SEC1,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
			snd_soc_component_update_bits(component,
					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
					CDC_WSA_RX_PGA_HALF_DB_MASK,
					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
			offset_val = 2;
			val = snd_soc_component_read(component, gain_reg);
			val += offset_val;
			snd_soc_component_write(component, gain_reg, val);
		}
		wsa_macro_config_ear_spkr_gain(component, wsa,
						event, gain_reg);
		break;
	}

	return 0;
}

static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
				     struct snd_kcontrol *kcontrol,
				     int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	u16 boost_path_ctl, boost_path_cfg1;
	u16 reg, reg_mix;

	if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT0 CHAIN")) {
		boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
		boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
		reg = CDC_WSA_RX0_RX_PATH_CTL;
		reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
	} else if (!snd_soc_dapm_widget_name_cmp(w, "WSA_RX INT1 CHAIN")) {
		boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
		boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
		reg = CDC_WSA_RX1_RX_PATH_CTL;
		reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
	} else {
		dev_warn(component->dev, "Incorrect widget name in the driver\n");
		return -EINVAL;
	}

	switch (event) {
	case SND_SOC_DAPM_PRE_PMU:
		snd_soc_component_update_bits(component, boost_path_cfg1,
					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
					      CDC_WSA_RX_PATH_SMART_BST_ENABLE);
		snd_soc_component_update_bits(component, boost_path_ctl,
					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
					      CDC_WSA_BOOST_PATH_CLK_ENABLE);
		if ((snd_soc_component_read(component, reg_mix)) & 0x10)
			snd_soc_component_update_bits(component, reg_mix,
						0x10, 0x00);
		break;
	case SND_SOC_DAPM_POST_PMU:
		snd_soc_component_update_bits(component, reg, 0x10, 0x00);
		break;
	case SND_SOC_DAPM_POST_PMD:
		snd_soc_component_update_bits(component, boost_path_ctl,
					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
					      CDC_WSA_BOOST_PATH_CLK_DISABLE);
		snd_soc_component_update_bits(component, boost_path_cfg1,
					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
					      CDC_WSA_RX_PATH_SMART_BST_DISABLE);
		break;
	}

	return 0;
}

static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
				 struct snd_kcontrol *kcontrol,
				 int event)
{
	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	u16 val, ec_tx, ec_hq_reg;

	val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);

	switch (w->shift) {
	case WSA_MACRO_EC0_MUX:
		val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
		ec_tx = val - 1;
		break;
	case WSA_MACRO_EC1_MUX:
		val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
		ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
		break;
	default:
		dev_err(component->dev,	"%s: Invalid shift %u\n",
			__func__, w->shift);
		return -EINVAL;
	}

	if (wsa->ec_hq[ec_tx]) {
		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL +	0x40 * ec_tx;
		snd_soc_component_update_bits(component, ec_hq_reg,
					     CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
					     CDC_WSA_EC_HQ_EC_CLK_ENABLE);
		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
		/* default set to 48k */
		snd_soc_component_update_bits(component, ec_hq_reg,
				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
	}

	return 0;
}

static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
			       struct snd_ctl_elem_value *ucontrol)
{

	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];

	return 0;
}

static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
			       struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
	int value = ucontrol->value.integer.value[0];
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	wsa->ec_hq[ec_tx] = value;

	return 0;
}

static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
				   struct snd_ctl_elem_value *ucontrol)
{

	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
	return 0;
}

static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
				   struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
	int value = ucontrol->value.integer.value[0];
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	wsa->comp_enabled[comp] = value;

	return 0;
}

static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
					  struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;

	return 0;
}

static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
					  struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	wsa->ear_spkr_gain =  ucontrol->value.integer.value[0];

	return 0;
}

static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_dapm_widget *widget =
		snd_soc_dapm_kcontrol_widget(kcontrol);
	struct snd_soc_component *component =
				snd_soc_dapm_to_component(widget->dapm);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	ucontrol->value.integer.value[0] =
			wsa->rx_port_value[widget->shift];
	return 0;
}

static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
				struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_dapm_widget *widget =
		snd_soc_dapm_kcontrol_widget(kcontrol);
	struct snd_soc_component *component =
				snd_soc_dapm_to_component(widget->dapm);
	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
	struct snd_soc_dapm_update *update = NULL;
	u32 rx_port_value = ucontrol->value.integer.value[0];
	u32 bit_input;
	u32 aif_rst;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);

	aif_rst = wsa->rx_port_value[widget->shift];
	if (!rx_port_value) {
		if (aif_rst == 0)
			return 0;
		if (aif_rst >= WSA_MACRO_RX_MAX) {
			dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
			return 0;
		}
	}
	wsa->rx_port_value[widget->shift] = rx_port_value;

	bit_input = widget->shift;

	switch (rx_port_value) {
	case 0:
		if (wsa->active_ch_cnt[aif_rst]) {
			clear_bit(bit_input,
				  &wsa->active_ch_mask[aif_rst]);
			wsa->active_ch_cnt[aif_rst]--;
		}
		break;
	case 1:
	case 2:
		set_bit(bit_input,
			&wsa->active_ch_mask[rx_port_value]);
		wsa->active_ch_cnt[rx_port_value]++;
		break;
	default:
		dev_err(component->dev,
			"%s: Invalid AIF_ID for WSA RX MUX %d\n",
			__func__, rx_port_value);
		return -EINVAL;
	}

	snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
					rx_port_value, e, update);
	return 0;
}

static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
					  struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;

	ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];

	return 0;
}

static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
					  struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;

	wsa->is_softclip_on[path] =  ucontrol->value.integer.value[0];

	return 0;
}

static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
	SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
		     wsa_macro_ear_spkr_pa_gain_get,
		     wsa_macro_ear_spkr_pa_gain_put),
	SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
			WSA_MACRO_SOFTCLIP0, 1, 0,
			wsa_macro_soft_clip_enable_get,
			wsa_macro_soft_clip_enable_put),
	SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
			WSA_MACRO_SOFTCLIP1, 1, 0,
			wsa_macro_soft_clip_enable_get,
			wsa_macro_soft_clip_enable_put),

	SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
			  -84, 40, digital_gain),
	SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
			  -84, 40, digital_gain),

	SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
	SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
	SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
		   1, 0),
	SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
		   1, 0),
	SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
		       wsa_macro_get_compander, wsa_macro_set_compander),
	SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
		       wsa_macro_get_compander, wsa_macro_set_compander),
	SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
	SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
};

static const struct soc_enum rx_mux_enum =
	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);

static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
	SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
	SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
	SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
	SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
};

static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
				       struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	u32 spk_tx_id = mixer->shift;
	u32 dai_id = widget->shift;

	if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
		ucontrol->value.integer.value[0] = 1;
	else
		ucontrol->value.integer.value[0] = 0;

	return 0;
}

static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
				       struct snd_ctl_elem_value *ucontrol)
{
	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
	u32 enable = ucontrol->value.integer.value[0];
	u32 spk_tx_id = mixer->shift;

	if (enable) {
		if (spk_tx_id == WSA_MACRO_TX0 &&
			!test_bit(WSA_MACRO_TX0,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
			set_bit(WSA_MACRO_TX0,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
		}
		if (spk_tx_id == WSA_MACRO_TX1 &&
			!test_bit(WSA_MACRO_TX1,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
			set_bit(WSA_MACRO_TX1,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
		}
	} else {
		if (spk_tx_id == WSA_MACRO_TX0 &&
			test_bit(WSA_MACRO_TX0,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
			clear_bit(WSA_MACRO_TX0,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
		}
		if (spk_tx_id == WSA_MACRO_TX1 &&
			test_bit(WSA_MACRO_TX1,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
			clear_bit(WSA_MACRO_TX1,
				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
		}
	}
	snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);

	return 0;
}

static const struct snd_kcontrol_new aif_vi_mixer[] = {
	SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
			wsa_macro_vi_feed_mixer_get,
			wsa_macro_vi_feed_mixer_put),
	SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
			wsa_macro_vi_feed_mixer_get,
			wsa_macro_vi_feed_mixer_put),
};

static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
	SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
			    SND_SOC_NOPM, 0, 0),
	SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
			    SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
			       SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
			       wsa_macro_enable_vi_feedback,
			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
			     SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
			   0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
			   WSA_MACRO_EC0_MUX, 0,
			   &rx_mix_ec0_mux, wsa_macro_enable_echo,
			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
			   WSA_MACRO_EC1_MUX, 0,
			   &rx_mix_ec1_mux, wsa_macro_enable_echo,
			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
			 &rx_mux[WSA_MACRO_RX0]),
	SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
			 &rx_mux[WSA_MACRO_RX1]),
	SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
			 &rx_mux[WSA_MACRO_RX_MIX0]),
	SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
			 &rx_mux[WSA_MACRO_RX_MIX1]),

	SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux),
	SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux),
	SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux),
	SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
			   0, &rx0_mix_mux, wsa_macro_enable_mix_path,
			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
	SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux),
	SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux),
	SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux),
	SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
			   0, &rx1_mix_mux, wsa_macro_enable_mix_path,
			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0,
			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),

	SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
			 4, 0, &rx0_sidetone_mix_mux),

	SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
	SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
	SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),

	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
			     WSA_MACRO_COMP1, 0, NULL, 0,
			     wsa_macro_enable_interpolator,
			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
			     SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
			     WSA_MACRO_COMP2, 0, NULL, 0,
			     wsa_macro_enable_interpolator,
			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
			     SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
			     NULL, 0, wsa_macro_spk_boost_event,
			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
			     SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
			     NULL, 0, wsa_macro_spk_boost_event,
			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
			     SND_SOC_DAPM_POST_PMD),

	SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
	SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
	SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),

	SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
			      wsa_macro_mclk_event,
			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};

static const struct snd_soc_dapm_route wsa_audio_map[] = {
	/* VI Feedback */
	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
	{"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
	{"WSA AIF_VI", NULL, "WSA_MCLK"},

	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
	{"WSA AIF_ECHO", NULL, "WSA_MCLK"},

	{"WSA AIF1 PB", NULL, "WSA_MCLK"},
	{"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},

	{"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
	{"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
	{"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
	{"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},

	{"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
	{"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
	{"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
	{"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},

	{"WSA RX0", NULL, "WSA RX0 MUX"},
	{"WSA RX1", NULL, "WSA RX1 MUX"},
	{"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
	{"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},

	{"WSA RX0", NULL, "WSA_RX0_CLK"},
	{"WSA RX1", NULL, "WSA_RX1_CLK"},
	{"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
	{"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},

	{"WSA_RX0 INP0", "RX0", "WSA RX0"},
	{"WSA_RX0 INP0", "RX1", "WSA RX1"},
	{"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},

	{"WSA_RX0 INP1", "RX0", "WSA RX0"},
	{"WSA_RX0 INP1", "RX1", "WSA RX1"},
	{"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},

	{"WSA_RX0 INP2", "RX0", "WSA RX0"},
	{"WSA_RX0 INP2", "RX1", "WSA RX1"},
	{"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},

	{"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
	{"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
	{"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},

	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
	{"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
	{"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
	{"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
	{"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},

	{"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
	{"WSA_SPK1 OUT", NULL, "WSA_MCLK"},

	{"WSA_RX1 INP0", "RX0", "WSA RX0"},
	{"WSA_RX1 INP0", "RX1", "WSA RX1"},
	{"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},

	{"WSA_RX1 INP1", "RX0", "WSA RX0"},
	{"WSA_RX1 INP1", "RX1", "WSA RX1"},
	{"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},

	{"WSA_RX1 INP2", "RX0", "WSA RX0"},
	{"WSA_RX1 INP2", "RX1", "WSA RX1"},
	{"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
	{"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},

	{"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
	{"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
	{"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
	{"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},

	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
	{"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},

	{"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
	{"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
	{"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
};

static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
{
	struct regmap *regmap = wsa->regmap;

	if (enable) {
		int ret;

		ret = clk_prepare_enable(wsa->mclk);
		if (ret) {
			dev_err(wsa->dev, "failed to enable mclk\n");
			return ret;
		}
		wsa_macro_mclk_enable(wsa, true);

		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
				   CDC_WSA_SWR_CLK_EN_MASK,
				   CDC_WSA_SWR_CLK_ENABLE);

	} else {
		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
				   CDC_WSA_SWR_CLK_EN_MASK, 0);
		wsa_macro_mclk_enable(wsa, false);
		clk_disable_unprepare(wsa->mclk);
	}

	return 0;
}

static int wsa_macro_component_probe(struct snd_soc_component *comp)
{
	struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);

	snd_soc_component_init_regmap(comp, wsa->regmap);

	wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;

	/* set SPKR rate to FS_2P4_3P072 */
	snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);

	snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);

	wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);

	return 0;
}

static int swclk_gate_enable(struct clk_hw *hw)
{
	return wsa_swrm_clock(to_wsa_macro(hw), true);
}

static void swclk_gate_disable(struct clk_hw *hw)
{
	wsa_swrm_clock(to_wsa_macro(hw), false);
}

static int swclk_gate_is_enabled(struct clk_hw *hw)
{
	struct wsa_macro *wsa = to_wsa_macro(hw);
	int ret, val;

	regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
	ret = val & BIT(0);

	return ret;
}

static unsigned long swclk_recalc_rate(struct clk_hw *hw,
				       unsigned long parent_rate)
{
	return parent_rate / 2;
}

static const struct clk_ops swclk_gate_ops = {
	.prepare = swclk_gate_enable,
	.unprepare = swclk_gate_disable,
	.is_enabled = swclk_gate_is_enabled,
	.recalc_rate = swclk_recalc_rate,
};

static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
{
	struct device *dev = wsa->dev;
	const char *parent_clk_name;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	if (wsa->npl)
		parent_clk_name = __clk_get_name(wsa->npl);
	else
		parent_clk_name = __clk_get_name(wsa->mclk);

	init.name = "mclk";
	of_property_read_string(dev_of_node(dev), "clock-output-names",
				&init.name);
	init.ops = &swclk_gate_ops;
	init.flags = 0;
	init.parent_names = &parent_clk_name;
	init.num_parents = 1;
	wsa->hw.init = &init;
	hw = &wsa->hw;
	ret = clk_hw_register(wsa->dev, hw);
	if (ret)
		return ret;

	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}

static const struct snd_soc_component_driver wsa_macro_component_drv = {
	.name = "WSA MACRO",
	.probe = wsa_macro_component_probe,
	.controls = wsa_macro_snd_controls,
	.num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
	.dapm_widgets = wsa_macro_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
	.dapm_routes = wsa_audio_map,
	.num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
};

static int wsa_macro_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct wsa_macro *wsa;
	kernel_ulong_t flags;
	void __iomem *base;
	int ret;

	flags = (kernel_ulong_t)device_get_match_data(dev);

	wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
	if (!wsa)
		return -ENOMEM;

	wsa->macro = devm_clk_get_optional(dev, "macro");
	if (IS_ERR(wsa->macro))
		return dev_err_probe(dev, PTR_ERR(wsa->macro), "unable to get macro clock\n");

	wsa->dcodec = devm_clk_get_optional(dev, "dcodec");
	if (IS_ERR(wsa->dcodec))
		return dev_err_probe(dev, PTR_ERR(wsa->dcodec), "unable to get dcodec clock\n");

	wsa->mclk = devm_clk_get(dev, "mclk");
	if (IS_ERR(wsa->mclk))
		return dev_err_probe(dev, PTR_ERR(wsa->mclk), "unable to get mclk clock\n");

	if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
		wsa->npl = devm_clk_get(dev, "npl");
		if (IS_ERR(wsa->npl))
			return dev_err_probe(dev, PTR_ERR(wsa->npl), "unable to get npl clock\n");
	}

	wsa->fsgen = devm_clk_get(dev, "fsgen");
	if (IS_ERR(wsa->fsgen))
		return dev_err_probe(dev, PTR_ERR(wsa->fsgen), "unable to get fsgen clock\n");

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config);
	if (IS_ERR(wsa->regmap))
		return PTR_ERR(wsa->regmap);

	dev_set_drvdata(dev, wsa);

	wsa->dev = dev;

	/* set MCLK and NPL rates */
	clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ);
	clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ);

	ret = clk_prepare_enable(wsa->macro);
	if (ret)
		goto err;

	ret = clk_prepare_enable(wsa->dcodec);
	if (ret)
		goto err_dcodec;

	ret = clk_prepare_enable(wsa->mclk);
	if (ret)
		goto err_mclk;

	ret = clk_prepare_enable(wsa->npl);
	if (ret)
		goto err_npl;

	ret = clk_prepare_enable(wsa->fsgen);
	if (ret)
		goto err_fsgen;

	/* reset swr ip */
	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
			   CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE);

	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
			   CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE);

	/* Bring out of reset */
	regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
			   CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE);

	ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
					      wsa_macro_dai,
					      ARRAY_SIZE(wsa_macro_dai));
	if (ret)
		goto err_clkout;

	pm_runtime_set_autosuspend_delay(dev, 3000);
	pm_runtime_use_autosuspend(dev);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	ret = wsa_macro_register_mclk_output(wsa);
	if (ret)
		goto err_clkout;

	return 0;

err_clkout:
	clk_disable_unprepare(wsa->fsgen);
err_fsgen:
	clk_disable_unprepare(wsa->npl);
err_npl:
	clk_disable_unprepare(wsa->mclk);
err_mclk:
	clk_disable_unprepare(wsa->dcodec);
err_dcodec:
	clk_disable_unprepare(wsa->macro);
err:
	return ret;

}

static void wsa_macro_remove(struct platform_device *pdev)
{
	struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);

	clk_disable_unprepare(wsa->macro);
	clk_disable_unprepare(wsa->dcodec);
	clk_disable_unprepare(wsa->mclk);
	clk_disable_unprepare(wsa->npl);
	clk_disable_unprepare(wsa->fsgen);
}

static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev)
{
	struct wsa_macro *wsa = dev_get_drvdata(dev);

	regcache_cache_only(wsa->regmap, true);
	regcache_mark_dirty(wsa->regmap);

	clk_disable_unprepare(wsa->fsgen);
	clk_disable_unprepare(wsa->npl);
	clk_disable_unprepare(wsa->mclk);

	return 0;
}

static int __maybe_unused wsa_macro_runtime_resume(struct device *dev)
{
	struct wsa_macro *wsa = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(wsa->mclk);
	if (ret) {
		dev_err(dev, "unable to prepare mclk\n");
		return ret;
	}

	ret = clk_prepare_enable(wsa->npl);
	if (ret) {
		dev_err(dev, "unable to prepare mclkx2\n");
		goto err_npl;
	}

	ret = clk_prepare_enable(wsa->fsgen);
	if (ret) {
		dev_err(dev, "unable to prepare fsgen\n");
		goto err_fsgen;
	}

	regcache_cache_only(wsa->regmap, false);
	regcache_sync(wsa->regmap);

	return 0;
err_fsgen:
	clk_disable_unprepare(wsa->npl);
err_npl:
	clk_disable_unprepare(wsa->mclk);

	return ret;
}

static const struct dev_pm_ops wsa_macro_pm_ops = {
	SET_RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL)
};

static const struct of_device_id wsa_macro_dt_match[] = {
	{
		.compatible = "qcom,sc7280-lpass-wsa-macro",
		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
	}, {
		.compatible = "qcom,sm8250-lpass-wsa-macro",
		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
	}, {
		.compatible = "qcom,sm8450-lpass-wsa-macro",
		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
	}, {
		.compatible = "qcom,sm8550-lpass-wsa-macro",
	}, {
		.compatible = "qcom,sc8280xp-lpass-wsa-macro",
		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
	},
	{}
};
MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);

static struct platform_driver wsa_macro_driver = {
	.driver = {
		.name = "wsa_macro",
		.of_match_table = wsa_macro_dt_match,
		.pm = &wsa_macro_pm_ops,
	},
	.probe = wsa_macro_probe,
	.remove_new = wsa_macro_remove,
};

module_platform_driver(wsa_macro_driver);
MODULE_DESCRIPTION("WSA macro driver");
MODULE_LICENSE("GPL");