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| author | Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | 2011-12-01 22:16:26 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2011-12-08 18:02:25 -0800 |
| commit | f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03 (patch) | |
| tree | e5174f71bffc3b93d4043a2e65756ff9ac85769d | |
| parent | 24ce2705c2dd50e51f325c6e57dec378adc8c135 (diff) | |
| download | linux-f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03.tar.gz linux-f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03.tar.bz2 linux-f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03.zip | |
ARM: OMAP1: Update dpll1 default rate reprogramming method
According to comments in omap1_select_table_rate(), reprogramming dpll1
is tricky, and should always be done from SRAM.
While being at it, move OMAP730 special case handling inside
omap_sram_reprogram_clock().
Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1
reprogramming related issues", which it depends on.
Tested on Amstrad Delta.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap1/clock.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 7 | ||||
| -rw-r--r-- | arch/arm/plat-omap/sram.c | 3 |
3 files changed, 9 insertions, 7 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index ff27dbdba3d6..6d8f7c640237 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -218,12 +218,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) /* * In most cases we should not need to reprogram DPLL. * Reprogramming the DPLL is tricky, it must be done from SRAM. - * (on 730, bit 13 must always be 1) */ - if (cpu_is_omap7xx()) - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); - else - omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); + omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ ck_dpll1_p->rate = ptr->pll_rate; diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index ff2d5248df23..9d1a42a5afd8 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -25,6 +25,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/clkdev_omap.h> +#include <plat/sram.h> /* for omap_sram_reprogram_clock() */ #include <plat/usb.h> /* for OTG_BASE */ #include "clock.h" @@ -944,8 +945,10 @@ void __init omap1_clk_late_init(void) /* Find the highest supported frequency and enable it */ if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { pr_err("System frequencies not set, using default. Check your config.\n"); - omap_writew(0x2290, DPLL_CTL); - omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); + /* + * Reprogramming the DPLL is tricky, it must be done from SRAM. + */ + omap_sram_reprogram_clock(0x2290, 0x0005); ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; } propagate_rate(&ck_dpll1); diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 574351902c83..6b058a621e8d 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -222,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); + /* On 730, bit 13 must always be 1 */ + if (cpu_is_omap7xx()) + ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } |