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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-03-29 11:02:42 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-04-16 13:39:49 +0200
commit0873305e68ac2a4665f1f3d27bb0b98a4312e5bd (patch)
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clk: renesas: r8a7792: Fix LB clock divider
The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car V2H, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
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