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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-30 10:47:49 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:19:24 +0100 |
| commit | 096311157d2a6bb8f06e28e1143e2a5de6a0183b (patch) | |
| tree | dd64bfa951a9d451926c2363bb3a233b1cc450b8 /drivers/clk/renesas | |
| parent | f077cab34df3010df6f4996e648dba5f43fd6b85 (diff) | |
| download | linux-096311157d2a6bb8f06e28e1143e2a5de6a0183b.tar.gz linux-096311157d2a6bb8f06e28e1143e2a5de6a0183b.tar.bz2 linux-096311157d2a6bb8f06e28e1143e2a5de6a0183b.zip | |
clk: renesas: r8a779g0: Fix PCIe clock name
Fix a typo in the name of the module clock for the second PCIe channel.
Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 5974adcef3ed..31b13c997a05 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -193,7 +193,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("msi4", 622, R8A779G0_CLK_MSO), DEF_MOD("msi5", 623, R8A779G0_CLK_MSO), DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC), - DEF_MOD("pscie1", 625, R8A779G0_CLK_S0D2_HSC), + DEF_MOD("pciec1", 625, R8A779G0_CLK_S0D2_HSC), DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4), DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2), DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4), |