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| author | Gabriel Fernandez <gabriel.fernandez@foss.st.com> | 2022-05-16 09:05:51 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-05-20 21:07:48 -0700 |
| commit | 720e34ab3e57e19dba70c384e30494f047999c43 (patch) | |
| tree | 07dc4d80873eb4c7e0c6f21dee73d340c8f6c12b /drivers/clk/stm32/clk-stm32mp13.c | |
| parent | 95f5e0a4c5fc654c9fdfe044e4c692bfead01352 (diff) | |
| download | linux-720e34ab3e57e19dba70c384e30494f047999c43.tar.gz linux-720e34ab3e57e19dba70c384e30494f047999c43.tar.bz2 linux-720e34ab3e57e19dba70c384e30494f047999c43.zip | |
clk: stm32mp13: add stm32 divider clock
Just to introduce management of a stm32 divider clock
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20220516070600.7692-6-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/stm32/clk-stm32mp13.c')
| -rw-r--r-- | drivers/clk/stm32/clk-stm32mp13.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 55326d4d34dd..d93d92b5fe82 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -415,9 +415,16 @@ static struct clk_stm32_gate eth1ck_k = { .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0), }; +static struct clk_stm32_div eth1ptp_k = { + .div_id = DIV_ETH1PTP, + .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops, + CLK_SET_RATE_NO_REPARENT), +}; + static const struct clock_config stm32mp13_clock_cfg[] = { STM32_MUX_CFG(NO_ID, ck_ker_eth1), STM32_GATE_CFG(ETH1CK_K, eth1ck_k), + STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k), }; static u16 stm32mp13_cpt_gate[GATE_NB]; |