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| author | Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 08:42:51 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 20:37:12 -0700 |
| commit | 8f9f717d6c44649353e153cfcd32ad99618956a9 (patch) | |
| tree | 6149cd71ec4995464414f690c56410d54e4f604f /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | d2f429ebb97725e9bec597aad2f0d2c7d203842f (diff) | |
| download | linux-8f9f717d6c44649353e153cfcd32ad99618956a9.tar.gz linux-8f9f717d6c44649353e153cfcd32ad99618956a9.tar.bz2 linux-8f9f717d6c44649353e153cfcd32ad99618956a9.zip | |
drm/i915: Enhance cdclk sanitization
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910154252.30503-8-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index e1a4ac9bd4f0..988d0849ce09 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1598,6 +1598,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) { u32 cdctl, expected; + int cdclk, vco; intel_update_cdclk(dev_priv); intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); @@ -1620,8 +1621,37 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) */ cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; - expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | - skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); + /* Make sure this is a legal cdclk value for the platform */ + cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); + if (cdclk != dev_priv->cdclk.hw.cdclk) + goto sanitize; + + /* Make sure the VCO is correct for the cdclk */ + vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); + if (vco != dev_priv->cdclk.hw.vco) + goto sanitize; + + expected = skl_cdclk_decimal(cdclk); + + /* Figure out what CD2X divider we should be using for this cdclk */ + switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, + dev_priv->cdclk.hw.cdclk)) { + case 2: + expected |= BXT_CDCLK_CD2X_DIV_SEL_1; + break; + case 3: + expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5; + break; + case 4: + expected |= BXT_CDCLK_CD2X_DIV_SEL_2; + break; + case 8: + expected |= BXT_CDCLK_CD2X_DIV_SEL_4; + break; + default: + goto sanitize; + } + /* * Disable SSA Precharge when CD clock frequency < 500 MHz, * enable otherwise. |