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| author | Imre Deak <imre.deak@intel.com> | 2022-04-15 00:06:55 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-04-20 20:42:13 +0300 |
| commit | e20b77c14bc491fbaf7ad1bba4b40de6581cb8e0 (patch) | |
| tree | cecf30b57860df0793de2d8c58a0f79ee8e47c61 /drivers/gpu/drm/i915/display/intel_display_power_map.c | |
| parent | c97bbab02ad7d174b50541864bfa45cf1e4ee14f (diff) | |
| download | linux-e20b77c14bc491fbaf7ad1bba4b40de6581cb8e0.tar.gz linux-e20b77c14bc491fbaf7ad1bba4b40de6581cb8e0.tar.bz2 linux-e20b77c14bc491fbaf7ad1bba4b40de6581cb8e0.zip | |
drm/i915: Remove the ICL specific TBT power domains
The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-16-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power_map.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power_map.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 86d937f8bfe1..d9cf3d3bc02e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -622,10 +622,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, POWER_DOMAIN_AUX_D, \ POWER_DOMAIN_AUX_E, \ POWER_DOMAIN_AUX_F, \ - POWER_DOMAIN_AUX_TBT_C, \ - POWER_DOMAIN_AUX_TBT_D, \ - POWER_DOMAIN_AUX_TBT_E, \ - POWER_DOMAIN_AUX_TBT_F + POWER_DOMAIN_AUX_TBT1, \ + POWER_DOMAIN_AUX_TBT2, \ + POWER_DOMAIN_AUX_TBT3, \ + POWER_DOMAIN_AUX_TBT4 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, ICL_PW_3_POWER_DOMAINS, @@ -668,10 +668,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); static const struct i915_power_well_desc icl_power_wells_pw_1[] = { { |