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| author | Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2021-07-23 10:42:37 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:32:54 -0700 |
| commit | 7711749a604996a41e14b66e3163e045a89fe8e1 (patch) | |
| tree | 1f18746b185f82e886f2398c7edbe7d401241c05 /drivers/gpu/drm/i915/display/intel_snps_phy.h | |
| parent | a6a128116e55970a2df9f39e31e3c8373c0ff558 (diff) | |
| download | linux-7711749a604996a41e14b66e3163e045a89fe8e1.tar.gz linux-7711749a604996a41e14b66e3163e045a89fe8e1.tar.bz2 linux-7711749a604996a41e14b66e3163e045a89fe8e1.zip | |
drm/i915/dg2: Update lane disable power state during PSR
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_snps_phy.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_snps_phy.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index 6aa33ff729ec..6261ff88ef5c 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -12,8 +12,11 @@ struct drm_i915_private; struct intel_encoder; struct intel_crtc_state; struct intel_mpllb_state; +enum phy; void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv); +void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, + enum phy phy, bool enable); int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); |