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path: root/drivers/gpu/drm/i915/display/intel_snps_phy.h
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* drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()Jani Nikula2024-03-211-2/+2
* drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä2023-10-071-1/+2
* drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä2023-10-071-1/+1
* drm/i915/mpllb: move mpllb state check to intel_snps_phy.cJani Nikula2022-06-171-1/+4
* drm/i915: Nuke useless .set_signal_levels() wrappersVille Syrjälä2021-10-041-3/+2
* drm/i915/dg2: use existing mechanisms for SNPS PHY translationsJani Nikula2021-08-131-1/+2
* drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun2021-07-291-0/+3
* drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper2021-07-291-0/+3
* drm/i915/dg2: Add vswing programming for SNPS physMatt Roper2021-07-291-0/+4
* drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper2021-07-291-0/+7
* drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper2021-07-291-0/+18