diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-23 10:42:33 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:06:01 -0700 |
| commit | 865b73ea18bbbb4da4be61186354aaca89d31303 (patch) | |
| tree | bb8e7a19194c446efdd738d5dbe1b364e38f4aef /drivers/gpu/drm/i915/display/intel_snps_phy.h | |
| parent | 29081008047892acb39099c39d39f84c2e7fb028 (diff) | |
| download | linux-865b73ea18bbbb4da4be61186354aaca89d31303.tar.gz linux-865b73ea18bbbb4da4be61186354aaca89d31303.tar.bz2 linux-865b73ea18bbbb4da4be61186354aaca89d31303.zip | |
drm/i915/dg2: Add MPLLB programming for HDMI
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-25-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_snps_phy.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_snps_phy.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index 205ab46f0b67..ca4c2a25182b 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -8,11 +8,18 @@ struct intel_encoder; struct intel_crtc_state; +struct intel_mpllb_state; int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); void intel_mpllb_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_mpllb_disable(struct intel_encoder *encoder); +void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, + struct intel_mpllb_state *pll_state); +int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, + const struct intel_mpllb_state *pll_state); + +int intel_snps_phy_check_hdmi_link_rate(int clock); #endif /* __INTEL_SNPS_PHY_H__ */ |