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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-23 10:42:34 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-29 09:07:05 -0700 |
| commit | a046a0daa3c6855d63fdf108919bb9666ba96c82 (patch) | |
| tree | 9d159cb3b535aa20a5160976807207f82db7b2e3 /drivers/gpu/drm/i915/display/intel_snps_phy.h | |
| parent | 865b73ea18bbbb4da4be61186354aaca89d31303 (diff) | |
| download | linux-a046a0daa3c6855d63fdf108919bb9666ba96c82.tar.gz linux-a046a0daa3c6855d63fdf108919bb9666ba96c82.tar.bz2 linux-a046a0daa3c6855d63fdf108919bb9666ba96c82.zip | |
drm/i915/dg2: Add vswing programming for SNPS phys
Vswing programming for SNPS PHYs is just a single step -- look up the
value that corresponds to the voltage level from a table and program it
into the SNPS_PHY_TX_EQ register.
Bspec: 53920
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-26-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_snps_phy.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_snps_phy.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index ca4c2a25182b..3ce92d424f66 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -6,6 +6,8 @@ #ifndef __INTEL_SNPS_PHY_H__ #define __INTEL_SNPS_PHY_H__ +#include <linux/types.h> + struct intel_encoder; struct intel_crtc_state; struct intel_mpllb_state; @@ -21,5 +23,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state); int intel_snps_phy_check_hdmi_link_rate(int clock); +void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder, + u32 level); #endif /* __INTEL_SNPS_PHY_H__ */ |