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| author | Jani Nikula <jani.nikula@intel.com> | 2022-09-12 14:45:12 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2022-09-13 19:54:46 +0300 |
| commit | 23fbdb07d6a729dd6a1df8e0cdd5772a5935c053 (patch) | |
| tree | 8d1b1719af829c7a5c2f71dcbaa5f77f663004a1 /drivers/gpu/drm/i915/display/skl_watermark.c | |
| parent | 4ff0856db045e1b18074127cc7222c481a99657e (diff) | |
| download | linux-23fbdb07d6a729dd6a1df8e0cdd5772a5935c053.tar.gz linux-23fbdb07d6a729dd6a1df8e0cdd5772a5935c053.tar.bz2 linux-23fbdb07d6a729dd6a1df8e0cdd5772a5935c053.zip | |
drm/i915/ipc: refactor and rename IPC functions
Rename the IPC functions to have skl_watermark_ipc_ prefix, rename
enable to update to reflect what the function actually does, and add
enabled function to abstract direct ->ipc_enabled access for state
query.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/536237d5bc919e8c97a96796f235f5bb264ceff2.1662983005.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/skl_watermark.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/skl_watermark.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index f773efe24e3e..5a6d2122b7a1 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -1843,10 +1843,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, * WaIncreaseLatencyIPCEnabled: kbl,cfl * Display WA #1141: kbl,cfl */ - if ((IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915) || - IS_COMETLAKE(i915)) && - i915->ipc_enabled) + if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) && + skl_watermark_ipc_enabled(i915)) latency += 4; if (skl_needs_memory_bw_wa(i915) && wp->x_tiled) @@ -2014,7 +2012,7 @@ static void skl_compute_transition_wm(struct drm_i915_private *i915, u16 wm0_blocks, trans_offset, blocks; /* Transition WM don't make any sense if ipc is disabled */ - if (!i915->ipc_enabled) + if (!skl_watermark_ipc_enabled(i915)) return; /* @@ -3122,7 +3120,12 @@ void intel_wm_state_verify(struct intel_crtc *crtc, kfree(hw); } -void intel_enable_ipc(struct drm_i915_private *i915) +bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) +{ + return i915->ipc_enabled; +} + +void skl_watermark_ipc_update(struct drm_i915_private *i915) { u32 val; @@ -3131,7 +3134,7 @@ void intel_enable_ipc(struct drm_i915_private *i915) val = intel_uncore_read(&i915->uncore, DISP_ARB_CTL2); - if (i915->ipc_enabled) + if (skl_watermark_ipc_enabled(i915)) val |= DISP_IPC_ENABLE; else val &= ~DISP_IPC_ENABLE; @@ -3139,7 +3142,7 @@ void intel_enable_ipc(struct drm_i915_private *i915) intel_uncore_write(&i915->uncore, DISP_ARB_CTL2, val); } -static bool intel_can_enable_ipc(struct drm_i915_private *i915) +static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915) { /* Display WA #0477 WaDisableIPC: skl */ if (IS_SKYLAKE(i915)) @@ -3154,14 +3157,14 @@ static bool intel_can_enable_ipc(struct drm_i915_private *i915) return true; } -void intel_init_ipc(struct drm_i915_private *i915) +void skl_watermark_ipc_init(struct drm_i915_private *i915) { if (!HAS_IPC(i915)) return; - i915->ipc_enabled = intel_can_enable_ipc(i915); + i915->ipc_enabled = skl_watermark_ipc_can_enable(i915); - intel_enable_ipc(i915); + skl_watermark_ipc_update(i915); } static void |