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| author | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-09-01 23:03:39 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-09-12 15:25:19 -0700 |
| commit | 825477e779121342d12e3c871a5e7487530b5a5d (patch) | |
| tree | 65dae70f6f2377a3c401fd6e6e0de98c8b17e463 /drivers/gpu/drm/i915/display/skl_watermark.c | |
| parent | 85d53200507916955be64b1e2cbca713b8ebe3bc (diff) | |
| download | linux-825477e779121342d12e3c871a5e7487530b5a5d.tar.gz linux-825477e779121342d12e3c871a5e7487530b5a5d.tar.bz2 linux-825477e779121342d12e3c871a5e7487530b5a5d.zip | |
drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
From Meteorlake, Latency Level, SAGV bloack time are read from
LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
and QGV information are also to be read from Mem SS registers.
v2:
- Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR)
- Nit: Rearrange the bit def's from higher to lower(MattR)
- Restore platform definition for ADL-P(MattR)
- Move back intel_qgv_point def to intel_bw.c(Jani)
v3:
- Rebase
Bspec: 64636, 64608
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220902060342.151824-9-radhakrishna.sripada@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/skl_watermark.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/skl_watermark.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index cb297725d5b9..f773efe24e3e 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -72,7 +72,13 @@ intel_has_sagv(struct drm_i915_private *i915) static u32 intel_sagv_block_time(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 12) { + if (DISPLAY_VER(i915) >= 14) { + u32 val; + + val = intel_uncore_read(&i915->uncore, MTL_LATENCY_SAGV); + + return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); + } else if (DISPLAY_VER(i915) >= 12) { u32 val = 0; int ret; |