Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) | Lad Prabhakar | 2020-09-04 | 1 | -1/+1 |
* | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 2018-09-28 | 1 | -4/+1 |
* | clk: renesas: r8a7794: Fix LB clock divider | Geert Uytterhoeven | 2018-04-16 | 1 | -1/+1 |
* | clk: renesas: r8a7794: Add rwdt clock | Fabrizio Castro | 2018-02-20 | 1 | -0/+2 |
* | clk: renesas: r8a7794: Add new CPG/MSSR driver | Geert Uytterhoeven | 2017-05-24 | 1 | -0/+255 |