linux.git - Linux kernel mainline tree

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: renesas: rzg2l: Extend power domain support	Claudiu Beznea	2024-04-25	1	-0/+67
*	clk: renesas: Add minimal boot support for RZ/G3S SoC	Claudiu Beznea	2023-10-10	1	-0/+1
*	clk: renesas: rzg2l: Add divider clock for RZ/G3S	Claudiu Beznea	2023-10-10	1	-0/+11
*	clk: renesas: rzg2l: Refactor SD mux driver	Claudiu Beznea	2023-10-10	1	-5/+11
*	clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header	Claudiu Beznea	2023-10-05	1	-4/+0
*	clk: renesas: rzg2l: Add support for RZ/G3S PLL	Claudiu Beznea	2023-10-05	1	-0/+3
*	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	2023-10-05	1	-1/+1
*	clk: renesas: rzg2l: Use u32 for flag and mux_flags	Claudiu Beznea	2023-09-18	1	-2/+2
*	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	2023-05-23	1	-3/+0
*	clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM	Lad Prabhakar	2022-10-28	1	-0/+4
*	clk: renesas: Add RZ/V2M support using the rzg2l driver	Phil Edworthy	2022-05-06	1	-0/+1
*	clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg	Phil Edworthy	2022-05-05	1	-2/+8
*	clk: renesas: rzg2l: Make use of CLK_MON registers optional	Phil Edworthy	2022-05-05	1	-0/+3
*	clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers	Phil Edworthy	2022-05-05	1	-4/+5
*	clk: renesas: rzg2l: Add read only versions of the clk macros	Phil Edworthy	2022-05-05	1	-0/+9
*	clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro	Phil Edworthy	2022-05-05	1	-7/+9
*	clk: renesas: rzg2l: Add DSI divider clk support	Biju Das	2022-05-05	1	-0/+11
*	clk: renesas: rzg2l: Add PLL5_4 clk mux support	Biju Das	2022-05-05	1	-0/+10
*	clk: renesas: rzg2l: Add FOUTPOSTDIV clk support	Biju Das	2022-05-05	1	-0/+23
*	clk: renesas: Add support for RZ/G2UL SoC	Biju Das	2022-04-13	1	-0/+1
*	clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC	Biju Das	2022-02-10	1	-0/+1
*	clk: renesas: r9a07g044: Add mux and divider for G clock	Biju Das	2021-12-08	1	-0/+4
*	clk: renesas: rzg2l: Add CPG_PL1_DDIV macro	Biju Das	2021-11-19	1	-0/+2
*	clk: renesas: rzg2l: Add missing kerneldoc for resets	Geert Uytterhoeven	2021-11-15	1	-0/+3
*	clk: renesas: r9a07g044: Add SDHI clock and reset entries	Biju Das	2021-10-08	1	-0/+4
*	clk: renesas: rzg2l: Add SDHI clk mux support	Biju Das	2021-10-08	1	-0/+12
*	clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...	Lad Prabhakar	2021-10-08	1	-0/+3
*	clk: renesas: rzg2l: Add support to handle coupled clocks	Biju Das	2021-09-24	1	-1/+10
*	clk: renesas: r9a07g044: Add ethernet clock sources	Biju Das	2021-09-24	1	-0/+3
*	clk: renesas: rzg2l: Add support to handle MUX clocks	Biju Das	2021-09-24	1	-0/+12
*	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	Geert Uytterhoeven	2021-07-19	1	-0/+155