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path: root/drivers/clk/renesas
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* clk: Switch back to struct platform_driver::remove()Uwe Kleine-König2024-09-211-1/+1
*-. Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd2024-09-2114-187/+1526
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| | * clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar2024-09-022-0/+88
| | * clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar2024-09-022-3/+201
| | * clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea2024-09-021-0/+17
| | * clk: renesas: r8a779h0: Add CANFD clockCong Dang2024-08-201-0/+1
| | * clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar2024-08-205-0/+94
| | * clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar2024-08-024-0/+838
| | * clk: renesas: r8a779h0: Add PWM clockCong Dang2024-08-021-0/+1
| | * clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven2024-07-305-28/+20
| | * clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven2024-07-302-24/+0
| | * clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven2024-07-302-10/+0
| | * clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven2024-07-301-5/+5
| | * clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven2024-07-301-7/+7
| | * clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven2024-07-301-6/+6
| | * clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven2024-07-301-4/+9
| | * clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven2024-07-302-0/+44
| | * clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven2024-07-302-10/+26
| | * clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven2024-07-302-7/+18
| | * clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven2024-07-301-16/+55
| | * clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven2024-07-305-21/+27
| | * clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven2024-07-302-5/+11
| | * clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven2024-07-301-15/+17
| | * clk: renesas: rcar-gen4: Removed unused SSMODE_* definitionsGeert Uytterhoeven2024-07-301-4/+0
| | * clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...Lad Prabhakar2024-07-301-28/+17
| | * clk: renesas: rzg2l-cpg: Use devres API to register clocksLad Prabhakar2024-07-301-6/+20
| | * clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven2024-07-301-3/+3
| | * clk: renesas: r8a779g0: cpg_pll_configs should be __initconstGeert Uytterhoeven2024-07-301-1/+1
| | * clk: renesas: r8a779f0: cpg_pll_configs should be __initconstGeert Uytterhoeven2024-07-301-1/+1
| | * clk: renesas: r8a779a0: cpg_pll_configs should be __initconstGeert Uytterhoeven2024-07-301-1/+1
| | * clk: renesas: r9a08g045: Add DMA clocks and resetsClaudiu Beznea2024-07-301-0/+3
| | * clk: renesas: r9a07g043: Add LCDC clock and reset entriesBiju Das2024-07-301-0/+12
| | * clk: renesas: r8a779h0: Add PCIe clockYoshihiro Shimoda2024-07-301-0/+1
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* / clk: Use of_property_present()Rob Herring (Arm)2024-08-021-1/+1
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* clk: renesas: r9a08g045: Add clock, reset and power domain support for I2CClaudiu Beznea2024-06-271-0/+20
* clk: renesas: r8a779h0: Add Audio clocksKuninori Morimoto2024-06-271-0/+2
* clk: renesas: r9a08g045: Add clock, reset and power domain support for the VB...Claudiu Beznea2024-06-271-0/+6
* clk: renesas: Drop "Renesas" from individual driver descriptionsGeert Uytterhoeven2024-06-241-2/+2
* clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven2024-06-241-3/+3
* clk: renesas: r8a779h0: Add VIN clocksNiklas Söderlund2024-06-111-0/+16
* clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlockGeert Uytterhoeven2024-06-071-3/+1
* clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlockGeert Uytterhoeven2024-06-073-5/+1
* clk: renesas: r8a77970: Use common cpg_lockGeert Uytterhoeven2024-06-071-4/+1
* clk: renesas: r8a779h0: Add CSI-2 clocksNiklas Söderlund2024-06-031-0/+2
* clk: renesas: r8a779h0: Add ISPCS clocksNiklas Söderlund2024-06-031-0/+2
* clk: renesas: r9a08g045: Add support for power domainsClaudiu Beznea2024-04-251-0/+41
* clk: renesas: rzg2l: Extend power domain supportClaudiu Beznea2024-04-252-14/+252
* clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INITGeert Uytterhoeven2024-04-253-6/+0
* clk: renesas: r8a7740: Remove unused div4_clk.flags fieldChristophe JAILLET2024-04-251-13/+12
* clk: renesas: r9a07g043: Add clock and reset entry for PLICLad Prabhakar2024-04-231-0/+9
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 14:45:26 +0000