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path: root/drivers/clk/tegra/clk.h
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter2018-12-141-2/+2
* clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver2018-07-251-0/+26
* clk: tegra: Refactor fractional divider calculationPeter De Schrijver2018-07-251-0/+3
* clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo2018-07-251-0/+1
* clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko2018-05-181-1/+1
* clk: tegra: add fence_delay for clock registersPeter De Schrijver2018-03-081-0/+7
* clk: tegra: Add peripheral clock registration helperThierry Reding2017-10-191-0/+3
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-231-6/+0
* clk: tegra: Fix build warnings on Tegra20/Tegra30Thierry Reding2017-03-201-1/+1
* clk: tegra: Add super clock mux/dividerPeter De Schrijver2017-03-201-1/+6
* clk: tegra: Fix constness for peripheral clocksPeter De Schrijver2017-03-201-2/+2
* clk: tegra: Fix type for m fieldPeter De Schrijver2017-03-201-1/+1
* clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker2016-06-301-0/+17
* clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein2016-04-281-0/+6
* clk: tegra: Add fixed factor peripheral clock typeThierry Reding2016-04-281-0/+17
* clk: tegra: Constify peripheral clock registersThierry Reding2016-04-281-2/+2
* clk: tegra: Add support for Tegra210 clocksRhyland Klein2015-12-171-0/+3
* clk: tegra: Add Super Gen5 LogicBill Huang2015-12-171-0/+3
* clk: tegra: pll: Add logic for SSBill Huang2015-12-171-0/+4
* clk: tegra: pll: Add dyn_ramp callbackRhyland Klein2015-12-171-0/+4
* clk: tegra: pll: Add Set_default logicBill Huang2015-12-171-0/+11
* clk: tegra: pll: Adjust vco_min if SDM presentBill Huang2015-12-171-0/+4
* clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein2015-12-171-0/+9
* clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein2015-12-171-0/+24
* clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang2015-11-201-0/+4
* clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein2015-11-201-0/+13
* clk: tegra: pll: Add logic for handling SDM dataRhyland Klein2015-11-201-1/+14
* clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang2015-11-201-1/+3
* clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein2015-11-201-0/+1
* clk: tegra: Constify pdiv-to-hw mappingsThierry Reding2015-11-201-1/+1
* clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein2015-10-201-1/+17
* clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding2015-10-201-3/+15
* clk: tegra: Fix comments for structure definitionsRhyland Klein2015-10-201-37/+37
* clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2015-07-161-0/+3
* clk: tegra: EMC clock driver depends on EMC driverThierry Reding2015-05-131-0/+9
* clk: tegra: Add EMC clock driverMikko Perttunen2015-05-131-0/+3
* clk: tegra: Model oscillator as clockThierry Reding2015-04-101-4/+4
* clk: tegra: Fix typo tabel -> tableThierry Reding2015-04-101-1/+1
* clk: tegra: Implement memory-controller clockThierry Reding2014-11-261-0/+2
* clk: tegra: remove legacy reset APIsStephen Warren2013-12-111-1/+0
* clk: tegra: implement a reset driverStephen Warren2013-12-111-1/+1
* clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-261-0/+1
* clk: tegra: add locking to periph clksPeter De Schrijver2013-11-261-4/+6
* clk: tegra: Add support for PLLSSPeter De Schrijver2013-11-261-0/+5
* clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-261-0/+3
* clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver2013-11-261-0/+7
* clk: tegra: move periph clocks to common filePeter De Schrijver2013-11-261-2/+9
* clk: tegra: move audio clk to common filePeter De Schrijver2013-11-261-0/+4
* clk: tegra: add clkdev registration infraPeter De Schrijver2013-11-261-0/+7
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 11:42:01 +0000