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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
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* drm/i915/hti: abstract hti handlingJani Nikula2022-11-171-9/+2
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak2022-10-261-24/+24
* drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak2022-10-261-0/+1
* drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak2022-10-261-1/+1
* drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak2022-10-261-32/+27
* drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä2022-09-261-22/+0
* drm/i915: Always initialize dpll.lockVille Syrjälä2022-09-261-1/+2
* drm/i915: WARN if PLL ref/unref got messed upVille Syrjälä2022-09-261-1/+6
* drm/i915: Pimp DPLL ref/unref debugsVille Syrjälä2022-09-261-3/+8
* drm/i915: Drop pointless 'budget' variableVille Syrjälä2022-09-261-16/+6
* drm/i915: Set active dpll early for icl+Ville Syrjälä2022-09-081-0/+6
* drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä2022-09-081-1/+23
* drm/i915: Shuffle some PLL code aroundVille Syrjälä2022-09-071-85/+85
* drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()Jani Nikula2022-08-311-2/+4
* drm/i915: move vbt to display.vbtJani Nikula2022-08-311-9/+9
* drm/i915: move and group cdclk under display.cdclkJani Nikula2022-08-311-2/+2
* drm/i915: move dpll under display.dpllJani Nikula2022-08-291-56/+56
* drm/i915: Fix error code in icl_compute_combo_phy_dpll()Dan Carpenter2022-06-281-1/+1
* drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula2022-06-171-0/+88
* drm/i915: Implement w/a 22010492432 for adl-sVille Syrjälä2022-06-161-2/+2
* drm/i915: Clean up DPLL related debugsVille Syrjälä2022-05-311-39/+9
* drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä2022-05-311-66/+215
* drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()Ville Syrjälä2022-04-251-15/+0
* drm/i915: Pass dev_priv to intel_shared_dpll_init()Ville Syrjälä2022-04-251-5/+4
* drm/i915: Make .get_dplls() return intVille Syrjälä2022-04-251-123/+121
* drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()Ville Syrjälä2022-03-101-10/+13
* drm/i915: Replace bxt_clk_div with struct dpllVille Syrjälä2022-03-101-34/+16
* drm/i915: Store the m2 divider as a whole in bxt_clk_divVille Syrjälä2022-03-101-14/+13
* drm/i915: Clean up bxt/glk PLL registersVille Syrjälä2022-03-101-16/+16
* drm/i915: Use designated initializers for bxt_dp_clk_val[]Ville Syrjälä2022-03-041-7/+7
* drm/i915: Remove bxt m2_frac_enVille Syrjälä2022-03-041-10/+8
* drm/i915: Clean up some struct/array initializersVille Syrjälä2022-03-041-9/+9
* drm/i915: Move a bunch of stuff into rodata from the stackVille Syrjälä2022-03-041-12/+12
* drm/i915: Nuke skl_wrpll_context_init()Ville Syrjälä2022-03-041-10/+3
* drm/i915: Use str_on_off()Lucas De Marchi2022-03-021-2/+5
* drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza2022-02-181-13/+31
* drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.cJani Nikula2022-01-191-0/+35
* drm/i915: Move TC PHY registers to their own headerMatt Roper2022-01-111-0/+1
* drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFFJosé Roberto de Souza2021-10-201-3/+3
* drm/i915: Move PCH refclock stuff into its own fileVille Syrjälä2021-10-191-0/+1
* drm/i915/tc: Add/use helpers to retrieve TypeC port propertiesImre Deak2021-09-291-2/+3
* drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä2021-08-251-28/+0
* drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()Ville Syrjälä2021-08-251-10/+3
* Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/...Dave Airlie2021-08-121-494/+131
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| * drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabledImre Deak2021-08-031-1/+33
| * drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.cLucas De Marchi2021-07-301-492/+94
| * drm/i915/dg2: Skip shared DPLL handlingMatt Roper2021-07-221-1/+4
* | Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper2021-07-141-1/+1
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| * drm/i915/jsl_ehl: Use revid->stepping tablesMatt Roper2021-07-141-1/+1
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