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Commit message (
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Author
Age
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Merge tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafa...
Linus Torvalds
2020-12-15
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Merge branch 'opp/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Rafael J. Wysocki
2020-12-14
1
-2
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+1
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media: venus: dev_pm_opp_put_*() accepts NULL argument
Viresh Kumar
2020-12-09
1
-2
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+1
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Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/brooni...
Linus Torvalds
2020-12-15
1
-2
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+3
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Merge series "spi: spi-geni-qcom: Use gpio descriptors for CS" from Stephen B...
Mark Brown
2020-12-10
34
-984
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+2415
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media: netup_unidvb: Don't leak SPI master in probe error path
Lukas Wunner
2020-12-07
1
-2
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+3
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Merge tag 'net-next-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ne...
Linus Torvalds
2020-12-15
1
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+1
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Jakub Kicinski
2020-12-11
7
-32
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+58
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Jakub Kicinski
2020-11-27
34
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+2415
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net: don't include ethtool.h from netdevice.h
Jakub Kicinski
2020-11-23
1
-0
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+1
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Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mc...
Linus Torvalds
2020-12-14
238
-7944
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+23754
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media: ccs: Add support for obtaining C-PHY configuration from firmware
Sakari Ailus
2020-12-07
1
-0
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+4
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media: ccs-pll: Print pixel rates
Sakari Ailus
2020-12-07
1
-0
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+5
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media: ccs: Print written register values
Sakari Ailus
2020-12-07
1
-0
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+4
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media: ccs: Add support for DDR OP SYS and OP PIX clocks
Sakari Ailus
2020-12-07
1
-1
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+8
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media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
2020-12-07
2
-20
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+46
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media: ccs: Dual PLL support
Sakari Ailus
2020-12-07
2
-3
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+51
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media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
2020-12-07
2
-22
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+196
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media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
2020-12-07
1
-27
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+37
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media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
2020-12-07
1
-5
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+7
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media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
2020-12-07
1
-26
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+25
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media: ccs-pll: Rework bounds checks
Sakari Ailus
2020-12-07
2
-57
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+95
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media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
2020-12-07
1
-19
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+66
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media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
2020-12-07
1
-23
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+31
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media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
2020-12-07
3
-29
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+64
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media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
2020-12-07
1
-124
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+131
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media: ccs-pll: Add C-PHY support
Sakari Ailus
2020-12-07
1
-9
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+26
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media: ccs-pll: Add sanity checks
Sakari Ailus
2020-12-07
1
-0
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+9
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media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
2020-12-07
3
-8
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+23
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media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
2020-12-07
3
-6
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+16
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media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
2020-12-07
3
-1
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+7
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media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
2020-12-07
4
-19
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+23
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media: ccs: Add support for lane speed model
Sakari Ailus
2020-12-07
1
-1
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+10
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media: ccs-pll: Add support for lane speed model
Sakari Ailus
2020-12-07
2
-11
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+31
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media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
2020-12-07
1
-2
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+2
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media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
2020-12-07
1
-2
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+1
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media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
2020-12-07
1
-1
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+1
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media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
2020-12-07
1
-2
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+9
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media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
2020-12-07
1
-1
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+1
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media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
2020-12-07
1
-8
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+4
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media: ccs-pll: Use the BIT macro
Sakari Ailus
2020-12-07
1
-2
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+5
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media: ccs-pll: Document the structs in the header as well as the function
Sakari Ailus
2020-12-07
1
-0
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+89
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media: ccs-pll: Move the flags field down, away from 8-bit fields
Sakari Ailus
2020-12-07
1
-1
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+1
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media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
2020-12-07
3
-3
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+4
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media: ccs-pll: Remove parallel bus support
Sakari Ailus
2020-12-07
2
-15
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+4
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media: ccs-pll: End search if there are no better values available
Sakari Ailus
2020-12-07
1
-2
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+8
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media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
2020-12-07
1
-2
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+2
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media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
2020-12-07
3
-188
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+209
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media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
2020-12-07
1
-1
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+1
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media: vivid: fix 'disconnect' error injection
Hans Verkuil
2020-12-07
3
-30
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+66
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