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path: root/drivers/pci/controller/pcie-xilinx-cpm.c
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* PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variantThippeswamy Havalige2025-03-231-1/+2
| | | | | | | | | | | | | Update the CPM5 check to include CPM5_HOST1 variant. Previously, only CPM5 was considered when mapping the "cpm_csr" register. With this change, CPM5_HOST1 is also supported, ensuring proper resource mapping for this variant. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Link: https://lore.kernel.org/r/20250317124136.1317723-1-thippeswamy.havalige@amd.com
* PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controllerThippeswamy Havalige2025-03-111-11/+29
| | | | | | | | | | | | | | | | | | | | | | | | | The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices incorporate the Coherency and PCIe Gen5 Module, specifically the Next-Generation Compact Module (CPM5NC). The integrated CPM5NC block, along with the built-in bridge, can function as a PCIe Root Port and supports the PCIe Gen5 protocol with data transfer rates of up to 32 GT/s, and is capable of supporting up to a x16 lane-width configuration. Bridge errors are managed using a specific interrupt line designed for CPM5N. The INTx interrupt support is not available. Currently in this commit platform specific bridge errors support is not added. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> [kwilczynski: commit log, squashed patch to fix an if-statement condition to ensure that xilinx_cpm_pcie_init_port() does not run on the CPM5NC_HOST variant from https://lore.kernel.org/linux-pci/20250311072402.1049990-1-thippeswamy.havalige@amd.com] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250224155025.782179-4-thippeswamy.havalige@amd.com
* PCI: xilinx-cpm: Fix IRQ domain leak in error path of probeThippeswamy Havalige2025-03-111-4/+6
| | | | | | | | | | | | | | The IRQ domain allocated for the PCIe controller is not freed if resource_list_first_type() returns NULL, leading to a resource leak. This fix ensures properly cleaning up the allocated IRQ domain in the error path. Fixes: 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> [kwilczynski: added missing Fixes: tag, refactored to use one of the goto labels] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Link: https://lore.kernel.org/r/20250224155025.782179-2-thippeswamy.havalige@amd.com
* PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1Thippeswamy Havalige2024-12-181-11/+39
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the Xilinx Versal CPM5 Root Port Controller 1. The key difference between Controller 0 and Controller 1 lies in the platform-specific error interrupt bits, which are located at different register offsets. To handle these differences, updated variant structure to hold the following platform-specific details: - Interrupt status register offset (ir_status) - Interrupt enable register offset (ir_enable) - Miscellaneous interrupt values (ir_misc_value) The driver differentiates between Controller 0 and Controller 1 using the compatible string in the device tree. This ensures that the appropriate register offsets are used for each controller, allowing for correct handling of platform-specific interrupts and initialization. Link: https://lore.kernel.org/r/20240922061318.2653503-3-thippesw@amd.com Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* PCI: xilinx-cpm: Move IRQ definitions to a common headerThippeswamy Havalige2023-10-261-31/+7
| | | | | | | | | | | | | | | | Move the interrupt bit definitions to the pcie-xilinx-common.h file, which then can be shared between pcie-xilinx-cpm and the new xilinx-xdma drivers. While at it, also rename them so these definitions are not CPM-specific. No functional change intended. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20231003173453.938190-2-thippeswamy.havalige@amd.com Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
* PCI: Remove unnecessary <linux/of_irq.h> includesBjorn Helgaas2022-11-101-1/+0
| | | | | | | | | Many host controller drivers #include <linux/of_irq.h> even though they don't need it. Remove the unnecessary #includes. Link: https://lore.kernel.org/r/20221031153954.1163623-6-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <roy.zang@nxp.com>
* PCI: xilinx-cpm: Add support for Versal CPM5 Root PortBharat Kumar Gogada2022-07-221-2/+58
| | | | | | | | | | | | | | | | | | | The Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has a few changes from the existing CPM block: - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Add support for the new CPM5 features. [bhelgaas: compare variant->version with CPM5 explicitly] Link: https://lore.kernel.org/r/20220705105646.16980-3-bharat.kumar.gogada@xilinx.com Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: xilinx-cpm: Rename xilinx_cpm_pcie_port to xilinx_cpm_pcieBjorn Helgaas2022-01-031-22/+22
| | | | | | | | | Rename struct xilinx_cpm_pcie_port to xilinx_cpm_pcie to match the convention of <driver>_pcie. No functional change intended. Link: https://lore.kernel.org/r/20211223011054.1227810-24-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* PCI: Bulk conversion to generic_handle_domain_irq()Marc Zyngier2021-08-021-2/+2
| | | | | | | | | | | | Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Link: https://lore.kernel.org/r/20210802162630.2219813-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
* PCI: xilinx-cpm: Fix reference count leak on error pathPan Bian2021-01-251-0/+1
| | | | | | | | | Also drop the reference count of the node on error path. Link: https://lore.kernel.org/r/20210120143745.699-1-bianpan2016@163.com Fixes: 508f610648b9 ("PCI: xilinx-cpm: Add Versal CPM Root Port driver") Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* PCI: xilinx-cpm: Remove leftover bridge initializationLorenzo Pieralisi2020-09-071-4/+0
| | | | | | | | | | | | | Some fields in the host bridge structure are now initialized by default in the PCI/OF core functions therefore their initialization in the host controller driver is superfluous. Remove it. Link: https://lore.kernel.org/r/20200904142710.8018-1-lorenzo.pieralisi@arm.com Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh@kernel.org>
* Merge branch 'pci/host-probe-refactor'Bjorn Helgaas2020-08-051-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use pci_host_bridge.windows list directly instead of splicing in a temporary list for cadence, mvebu, host-common (Rob Herring) - Use pci_host_probe() instead of open-coding all the pieces for altera, brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene, xilinx, xilinx-nwl (Rob Herring) - Convert to devm_platform_ioremap_resource_byname() instead of open-coding platform_get_resource_byname() and devm_ioremap_resource() for altera, cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng) - Convert to devm_platform_ioremap_resource() instead of open-coding platform_get_resource() and devm_ioremap_resource() for aardvark, brcmstb, exynos, ftpci100, versatile (Dejin Zheng) - Remove redundant error messages from devm_pci_remap_cfg_resource() callers (Dejin Zheng) - Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring) - Default host bridge parent device to the platform device (Rob Herring) - Drop unnecessary zeroing of host bridge fields (Rob Herring) - Use pci_is_root_bus() instead of tracking root bus number separately in aardvark, designware (imx6, keystone, designware-host), mobiveil, xilinx-nwl, xilinx, rockchip, rcar (Rob Herring) - Set host bridge bus number in pci_scan_root_bus_bridge() instead of each driver for aardvark, designware-host, host-common, mediatek, rcar, tegra, v3-semi (Rob Herring) - Use bridge resources instead of parsing DT 'ranges' again for cadence (Rob Herring) - Remove private bus number and range from cadence (Rob Herring) - Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring) - Use struct pci_host_bridge.windows list directly rather than a temporary (Rob Herring) - Reduce OF "missing non-prefetchable window" from error to warning message (Rob Herring) - Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new arch-independent interfaces (Rob Herring) - Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring) - Set bridge map_irq and swizzle_irq to default functions; drivers that don't support legacy IRQs (iproc) need to undo this (Rob Herring) * pci/host-probe-refactor: PCI: Set bridge map_irq and swizzle_irq to default functions PCI: Move DT resource setup into devm_pci_alloc_host_bridge() PCI: rcar-gen2: Convert to use modern host bridge probe functions PCI: of: Reduce missing non-prefetchable memory region to a warning PCI: rcar: Use struct pci_host_bridge.windows list directly PCI: rcar: Use devm_pci_alloc_host_bridge() PCI: cadence: Remove private bus number and range storage PCI: cadence: Use bridge resources for outbound window setup PCI: Move setting pci_host_bridge.busnr out of host drivers PCI: rcar: Use pci_is_root_bus() to check if bus is root bus PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus PCI: designware: Use pci_is_root_bus() to check if bus is root bus PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus PCI: Drop unnecessary zeroing of bridge fields PCI: Set default bridge parent device PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS PCI: controller: Remove duplicate error message PCI: controller: Convert to devm_platform_ioremap_resource() PCI: controller: Convert to devm_platform_ioremap_resource_byname() PCI: xilinx: Use pci_host_probe() to register host PCI: xilinx-nwl: Use pci_host_probe() to register host PCI: rockchip: Use pci_host_probe() to register host PCI: rcar: Use pci_host_probe() to register host PCI: iproc: Use pci_host_probe() to register host PCI: altera: Use pci_host_probe() to register host PCI: xgene: Use pci_host_probe() to register host PCI: versatile: Use pci_host_probe() to register host PCI: v3: Use pci_host_probe() to register host PCI: tegra: Use pci_host_probe() to register host PCI: mobiveil: Use pci_host_probe() to register host PCI: brcmstb: Use pci_host_probe() to register host PCI: host-common: Use struct pci_host_bridge.windows list directly PCI: mvebu: Use struct pci_host_bridge.windows list directly PCI: cadence: Use struct pci_host_bridge.windows list directly # Conflicts: # drivers/pci/controller/cadence/pcie-cadence-host.c
* PCI: xilinx-cpm: Add Versal CPM Root Port driverBharat Kumar Gogada2020-08-051-0/+614
Add support for Versal CPM as Root Port. The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated block for CPM along with the integrated bridge can function as PCIe Root Port. Bridge error and legacy interrupts in Versal CPM are handled using Versal CPM specific interrupt line. [bhelgaas: fold in kerneldoc fix from https://lore.kernel.org/linux-acpi/20200729201224.26799-7-krzk@kernel.org/] Link: https://lore.kernel.org/r/1592312214-9347-3-git-send-email-bharat.kumar.gogada@xilinx.com Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-26 08:06:31 +0000