diff options
Diffstat (limited to 'package/boot')
192 files changed, 19019 insertions, 9172 deletions
diff --git a/package/boot/arm-trusted-firmware-bcm63xx/Makefile b/package/boot/arm-trusted-firmware-bcm63xx/Makefile index bcb5ce9892..385776ff59 100644 --- a/package/boot/arm-trusted-firmware-bcm63xx/Makefile +++ b/package/boot/arm-trusted-firmware-bcm63xx/Makefile @@ -33,6 +33,7 @@ TFA_TARGETS:= \ bcm4908 TFA_MAKE_FLAGS += \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") \ BRCM_CHIP=$(BRCM_CHIP) define Package/trusted-firmware-a/install diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile index d8eef07f5e..0b68d510c5 100644 --- a/package/boot/arm-trusted-firmware-mediatek/Makefile +++ b/package/boot/arm-trusted-firmware-mediatek/Makefile @@ -9,13 +9,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=arm-trusted-firmware-mediatek -PKG_RELEASE:=2 +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git -PKG_SOURCE_DATE:=2024-01-17 -PKG_SOURCE_VERSION:=bacca82a8cac369470df052a9d801a0ceb9b74ca -PKG_MIRROR_HASH:=1138649f64ac3982330925c38c795ca6860289adbd95755991f80afa30ebdea7 +PKG_SOURCE_DATE:=2025-02-12 +PKG_SOURCE_VERSION:=e090770684e775711a624e68e0b28112227a4c38 +PKG_MIRROR_HASH:=1ff9d60f3677aadd9a6716e860985987ba7157bd28ce831112e05c0b3170939a PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org> @@ -52,6 +52,27 @@ define Trusted-Firmware-A/mt7622-nor-2ddr DDR3_FLYBY:=1 endef +define Trusted-Firmware-A/mt7622-ram-1ddr + NAME:=MediaTek MT7622 (RAM, 1x DDR3) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=mt7622 + PLAT:=mt7622 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_mt7622 +endef + +define Trusted-Firmware-A/mt7622-ram-2ddr + NAME:=MediaTek MT7622 (RAM, 2x DDR3) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=mt7622 + PLAT:=mt7622 + DDR3_FLYBY:=1 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_mt7622 +endef + define Trusted-Firmware-A/mt7622-snand-1ddr NAME:=MediaTek MT7622 (SPI-NAND, 1x DDR3) BUILD_SUBTARGET:=mt7622 @@ -331,6 +352,15 @@ define Trusted-Firmware-A/mt7986-spim-nand-ddr3 DDR_TYPE:=ddr3 endef +define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr3 + NAME:=MediaTek MT7986 (SPI-NAND via SPIM using UBI, DDR3) + BOOT_DEVICE:=spim-nand + BUILD_SUBTARGET:=filogic + PLAT:=mt7986 + DDR_TYPE:=ddr3 + USE_UBI:=1 +endef + define Trusted-Firmware-A/mt7988-nor-ddr3 NAME:=MediaTek MT7988 (SPI-NOR, DDR3) BOOT_DEVICE:=nor @@ -483,6 +513,8 @@ endef TFA_TARGETS:= \ mt7622-nor-1ddr \ mt7622-nor-2ddr \ + mt7622-ram-1ddr \ + mt7622-ram-2ddr \ mt7622-snand-1ddr \ mt7622-snand-ubi-1ddr \ mt7622-snand-2ddr \ @@ -508,6 +540,7 @@ TFA_TARGETS:= \ mt7986-sdmmc-ddr3 \ mt7986-snand-ddr3 \ mt7986-spim-nand-ddr3 \ + mt7986-spim-nand-ubi-ddr3 \ mt7986-ram-ddr4 \ mt7986-emmc-ddr4 \ mt7986-nor-ddr4 \ @@ -547,12 +580,15 @@ TFA_MAKE_FLAGS += \ $(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \ $(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \ $(if $(USE_UBI),UBI=1 $(if $(findstring mt7981,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x100000)) \ - all + $(if $(USE_UBI),UBI=1 $(if $(findstring mt7986,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x200000)) \ + $(if $(RAM_BOOT_UART_DL),bl2,all) define Package/trusted-firmware-a-ram/install $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.bin $(BIN_DIR)/$(BUILD_VARIANT)-bl2.bin endef +Package/trusted-firmware-a-mt7622-ram-1ddr/install = $(Package/trusted-firmware-a-ram/install) +Package/trusted-firmware-a-mt7622-ram-2ddr/install = $(Package/trusted-firmware-a-ram/install) Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install) Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install) Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install) diff --git a/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-fix-return-code-when-reading.patch b/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-fix-return-code-when-reading.patch new file mode 100644 index 0000000000..8ac52143a7 --- /dev/null +++ b/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-fix-return-code-when-reading.patch @@ -0,0 +1,31 @@ +From 94802b344195d3574701ca6ab5122f6b7615a6eb Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel@makrotopia.org> +Date: Sun, 11 Aug 2024 23:12:33 +0100 +Subject: [PATCH] mediatek: snfi: fix return code when reading + +Return 0 on succesful read, which may contain correctable bitflips. + +Fixes: #10 +Signed-off-by: Daniel Golle <daniel@makrotopia.org> +--- + plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c ++++ b/plat/mediatek/apsoc_common/bl2/bl2_dev_snfi_init.c +@@ -30,9 +30,14 @@ static int snfi_mtd_read_page(struct nan + int ret; + + ret = mtk_snand_read_page(snf, addr, (void *)buffer, NULL, false); +- if (ret == -EBADMSG || ret > 0) ++ if (ret == -EBADMSG) + ret = 0; + ++ if (ret > 0) { ++ NOTICE("corrected %d bitflips while reading page %u\n", ret, page); ++ ret = 0; ++ } ++ + return ret; + } + diff --git a/package/boot/arm-trusted-firmware-mvebu/Makefile b/package/boot/arm-trusted-firmware-mvebu/Makefile index 047c8db55e..7dd0f11d52 100644 --- a/package/boot/arm-trusted-firmware-mvebu/Makefile +++ b/package/boot/arm-trusted-firmware-mvebu/Makefile @@ -119,6 +119,7 @@ TFA_TARGETS:= \ edpu TFA_MAKE_FLAGS += \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") \ CROSS_CM3=$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \ BL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \ MV_DDR_PATH=$(BUILD_DIR)/$(MV_DDR_NAME) \ diff --git a/package/boot/arm-trusted-firmware-rockchip/Makefile b/package/boot/arm-trusted-firmware-rockchip/Makefile index 6fbcbef0a8..9073afe365 100644 --- a/package/boot/arm-trusted-firmware-rockchip/Makefile +++ b/package/boot/arm-trusted-firmware-rockchip/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de> +# Copyright (C) 2020 Sarah Maedel <openwrt@tbspace.de> # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. @@ -12,7 +12,7 @@ PKG_RELEASE:=1 PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201 -PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de> +PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de> include $(INCLUDE_DIR)/kernel.mk include $(INCLUDE_DIR)/trusted-firmware-a.mk @@ -37,6 +37,9 @@ TFA_TARGETS:= \ rk3328 \ rk3399 +TFA_MAKE_FLAGS+= \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") + ifeq ($(BUILD_VARIANT),rk3399) M0_GCC_NAME:=gcc-arm M0_GCC_RELEASE:=11.2-2022.02 diff --git a/package/boot/arm-trusted-firmware-stm32/Makefile b/package/boot/arm-trusted-firmware-stm32/Makefile new file mode 100644 index 0000000000..403f53acc8 --- /dev/null +++ b/package/boot/arm-trusted-firmware-stm32/Makefile @@ -0,0 +1,63 @@ +# +# Copyright (C) 2024 Bootlin +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_VERSION:=2.12 +PKG_RELEASE:=1 + +PKG_HASH:=b4c047493cac1152203e1ba121ae57267e4899b7bf56eb365e22a933342d31c9 +PKG_MAINTAINER:=Thomas Richard <thomas.richard@bootlin.com> + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/trusted-firmware-a.mk +include $(INCLUDE_DIR)/package.mk + +define Trusted-Firmware-A/Default + BUILD_TARGET:=stm32 + BUILD_DEVICES:=$(1) + DEPENDS:=+u-boot-$(1) +optee-os-$(1) +endef + +define Trusted-Firmware-A/stm32mp1 + BUILD_SUBTARGET:=stm32mp1 + PLAT:=stm32mp1 + MAKE_ARGS += BL32_EXTRA2=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-tee-pageable_v2.bin \ + STM32MP_USB_PROGRAMMER=1 \ + STM32MP1_OPTEE_IN_SYSRAM=1 \ + ARM_ARCH_MAJOR=7 +endef + +define Trusted-Firmware-A/stm32mp135f-dk + $(call Trusted-Firmware-A/stm32mp1) + NAME:=STM32MP135F-DK + DTB_FILE_NAME=stm32mp135f-dk.dtb +endef + +TFA_TARGETS := stm32mp135f-dk + +TFA_MAKE_FLAGS += \ + ARCH=aarch32 AARCH32_SP=optee \ + BL32=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-tee-header_v2.bin \ + BL32_EXTRA1=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-tee-pager_v2.bin \ + BL33=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.bin \ + BL33_CFG=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.dtb \ + DTB_FILE_NAME=$(DTB_FILE_NAME) \ + STM32MP_SDMMC=1 \ + TARGET_BOARD="" \ + $(MAKE_ARGS) \ + all fip + +define Package/trusted-firmware-a/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/tf-a-$(BUILD_VARIANT).stm32 \ + $(STAGING_DIR_IMAGE)/tf-a-$(BUILD_VARIANT).stm32 + $(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/fip.bin \ + $(STAGING_DIR_IMAGE)/fip-$(BUILD_VARIANT).bin +endef + +$(eval $(call BuildPackage/Trusted-Firmware-A)) diff --git a/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch b/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch new file mode 100644 index 0000000000..58b896c65d --- /dev/null +++ b/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch @@ -0,0 +1,66 @@ +From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001 +From: Thomas Richard <thomas.richard@bootlin.com> +Date: Wed, 4 Dec 2024 14:26:52 +0100 +Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration" + +This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c. +--- + fdts/stm32mp135f-dk.dts | 2 ++ + fdts/stm32mp157c-ed1.dts | 2 ++ + fdts/stm32mp15xx-dkx.dtsi | 2 ++ + 3 files changed, 6 insertions(+) + +--- a/fdts/stm32mp135f-dk.dts ++++ b/fdts/stm32mp135f-dk.dts +@@ -190,6 +190,7 @@ + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_CKPER_HSE ++ CLK_RTC_LSE + CLK_SDMMC1_PLL4P + CLK_SDMMC2_PLL4P + CLK_STGEN_HSE +@@ -211,6 +212,7 @@ + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) + DIV(DIV_APB6, 1) ++ DIV(DIV_RTC, 0) + >; + + st,pll_vco { +--- a/fdts/stm32mp157c-ed1.dts ++++ b/fdts/stm32mp157c-ed1.dts +@@ -194,6 +194,7 @@ + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P ++ CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + CLK_CKPER_HSE +@@ -242,6 +243,7 @@ + DIV(DIV_APB3, 1) + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) ++ DIV(DIV_RTC, 23) + DIV(DIV_MCO1, 0) + DIV(DIV_MCO2, 0) + >; +--- a/fdts/stm32mp15xx-dkx.dtsi ++++ b/fdts/stm32mp15xx-dkx.dtsi +@@ -198,6 +198,7 @@ + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P ++ CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + CLK_CKPER_HSE +@@ -246,6 +247,7 @@ + DIV(DIV_APB3, 1) + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) ++ DIV(DIV_RTC, 23) + DIV(DIV_MCO1, 0) + DIV(DIV_MCO2, 0) + >; diff --git a/package/boot/arm-trusted-firmware-sunxi/Makefile b/package/boot/arm-trusted-firmware-sunxi/Makefile index 4b007f8b03..4903c98cde 100644 --- a/package/boot/arm-trusted-firmware-sunxi/Makefile +++ b/package/boot/arm-trusted-firmware-sunxi/Makefile @@ -46,6 +46,9 @@ TFA_TARGETS:= \ sunxi-h6 \ sunxi-h616 +TFA_MAKE_FLAGS+= \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") + define Package/trusted-firmware-a/install $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31_$(BUILD_VARIANT).bin diff --git a/package/boot/arm-trusted-firmware-tools/Makefile b/package/boot/arm-trusted-firmware-tools/Makefile index 209e945a0b..dd0ed66a21 100644 --- a/package/boot/arm-trusted-firmware-tools/Makefile +++ b/package/boot/arm-trusted-firmware-tools/Makefile @@ -8,9 +8,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=arm-trusted-firmware-tools -PKG_VERSION:=2.9 +PKG_VERSION:=2.12 PKG_RELEASE:=1 -PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b +PKG_HASH:=b4c047493cac1152203e1ba121ae57267e4899b7bf56eb365e22a933342d31c9 PKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org> PKG_HOST_ONLY:=1 @@ -33,7 +33,8 @@ define Host/Compile $(MAKE) -C \ $(HOST_BUILD_DIR)/tools/fiptool \ CPPFLAGS="$(HOST_CFLAGS)" \ - LDFLAGS="$(HOST_LDFLAGS)" + LDFLAGS="$(HOST_LDFLAGS)" \ + OPENSSL_DIR="$(STAGING_DIR_HOST)" endef define Host/Install diff --git a/package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch b/package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch index 0b7989163e..8959befaeb 100644 --- a/package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch +++ b/package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch @@ -1,11 +1,11 @@ --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -38,7 +38,7 @@ +@@ -74,7 +74,7 @@ all: --openssl ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile - @echo " HOSTLD $@" -- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} -+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS) - @${ECHO_BLANK_LINE} - @echo "Built $@ successfully" - @${ECHO_BLANK_LINE} + $(s)echo " HOSTLD $@" +- $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS) ++ $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS) $(LDFLAGS) + $(s)echo + $(s)echo "Built $@ successfully" + $(s)echo diff --git a/package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch b/package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch index 6bc8192f44..621047a30e 100644 --- a/package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch +++ b/package/boot/arm-trusted-firmware-tools/patches/002-darwin_compile.patch @@ -1,15 +1,6 @@ --- a/tools/fiptool/fiptool.c +++ b/tools/fiptool/fiptool.c -@@ -3,7 +3,7 @@ - * - * SPDX-License-Identifier: BSD-3-Clause - */ -- -+#define _DARWIN_C_SOURCE - #ifndef _MSC_VER - #include <sys/mount.h> - #endif -@@ -18,6 +18,9 @@ +@@ -19,6 +19,9 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -19,3 +10,13 @@ #include "fiptool.h" #include "tbbr_config.h" +--- a/tools/fiptool/fiptool_platform.h ++++ b/tools/fiptool/fiptool_platform.h +@@ -12,6 +12,7 @@ + #ifndef FIPTOOL_PLATFORM_H + #define FIPTOOL_PLATFORM_H + ++#define _DARWIN_C_SOURCE + #ifndef _MSC_VER + + /* Not Visual Studio, so include Posix Headers. */ diff --git a/package/boot/imx-bootlets/Makefile b/package/boot/imx-bootlets/Makefile index 742c8a3bd0..0ecb0f2dfd 100644 --- a/package/boot/imx-bootlets/Makefile +++ b/package/boot/imx-bootlets/Makefile @@ -7,11 +7,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=imx-bootlets -PKG_VERSION:=10.05.02 +PKG_VERSION:=10.12.01 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=http://trabant.uid0.hu/openwrt/ -PKG_HASH:=09ecd81a64db5166a235932146faf08d0689bfc7ac04ac9fcc3a5bd809fba74a +PKG_HASH:=f7c98cbc41e15184cad61c56115e840e34ac3ebb4a162fadeea905e5038fd65b + +PKG_FLAGS:=nonshared include $(INCLUDE_DIR)/package.mk @@ -35,7 +37,7 @@ define Package/imx-bootlets/install $(INSTALL_BIN) $(PKG_BUILD_DIR)/boot_prep/boot_prep $(STAGING_DIR)/boot_prep $(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prep/output-target/linux_prep $(STAGING_DIR)/linux_prep $(INSTALL_BIN) $(PKG_BUILD_DIR)/power_prep/power_prep $(STAGING_DIR)/power_prep - $(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prebuilt.db $(STAGING_DIR)/linux_prebuilt.db + $(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_ivt.bd $(STAGING_DIR)/linux_ivt.bd endef $(eval $(call BuildPackage,imx-bootlets)) diff --git a/package/boot/imx-bootlets/patches/001-skip_sb_generation.patch b/package/boot/imx-bootlets/patches/001-skip_sb_generation.patch index ad65265850..d1829aa16c 100644 --- a/package/boot/imx-bootlets/patches/001-skip_sb_generation.patch +++ b/package/boot/imx-bootlets/patches/001-skip_sb_generation.patch @@ -1,18 +1,22 @@ --- a/Makefile +++ b/Makefile -@@ -32,10 +32,11 @@ ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IM - sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db - elftosb2 -z -c ./uboot.db -o i$(ARCH)_uboot.sb +@@ -37,13 +37,13 @@ ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IM + elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb + elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb else - @echo "by using the pre-built kernel" -- elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb -- @echo "generating U-Boot boot stream image" -- elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb +- elftosb -z -c ./linux.bd -o i$(ARCH)_linux.sb +- elftosb -z -f imx28 -c ./linux_ivt.bd -o i$(ARCH)_ivt_linux.sb + @echo "... not generating any image for now." -+ #@echo "by using the pre-built kernel" -+ #elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb ++ #elftosb -z -c ./linux.bd -o i$(ARCH)_linux.sb ++ #elftosb -z -f imx28 -c ./linux_ivt.bd -o i$(ARCH)_ivt_linux.sb + +- @echo "generating U-Boot boot stream image" +- elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb +- elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb + #@echo "generating U-Boot boot stream image" -+ #elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb ++ #elftosb -z -c ./uboot.bd -o i$(ARCH)_uboot.sb ++ #elftosb -z -f imx28 -c ./uboot_ivt.bd -o i$(ARCH)_ivt_uboot.sb endif #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" #Please use cfimager to burn xxx_linux.sb. The below way will no diff --git a/package/boot/imx-bootlets/patches/002-set_elftosb_config.patch b/package/boot/imx-bootlets/patches/002-set_elftosb_config.patch index 5cf48fd6fc..afd4150248 100644 --- a/package/boot/imx-bootlets/patches/002-set_elftosb_config.patch +++ b/package/boot/imx-bootlets/patches/002-set_elftosb_config.patch @@ -1,5 +1,5 @@ ---- a/linux_prebuilt.db -+++ b/linux_prebuilt.db +--- a/linux_ivt.bd ++++ b/linux_ivt.bd @@ -4,10 +4,10 @@ options { flags = 0x01; } @@ -7,11 +7,11 @@ - power_prep="./power_prep/power_prep"; - sdram_prep="./boot_prep/boot_prep"; - linux_prep="./linux_prep/output-target/linux_prep"; -- zImage = "./zImage"; +- zImage="./zImage"; + power_prep="./power_prep"; + sdram_prep="./boot_prep"; + linux_prep="./linux_prep"; -+ zImage = "./zImage_dtb"; ++ zImage="./zImage_dtb"; } section (0) { diff --git a/package/boot/imx-bootlets/patches/003-add-olinuxino.patch b/package/boot/imx-bootlets/patches/003-add-olinuxino.patch index 6ed5786344..dd0a5ce478 100644 --- a/package/boot/imx-bootlets/patches/003-add-olinuxino.patch +++ b/package/boot/imx-bootlets/patches/003-add-olinuxino.patch @@ -121,7 +121,7 @@ all: build_prep gen_bootstream -@@ -94,6 +97,8 @@ distclean: clean +@@ -101,6 +104,8 @@ distclean: clean clean: -rm -rf *.sb rm -f sd_mmc_bootstream.raw @@ -130,14 +130,3 @@ $(MAKE) -C linux_prep clean ARCH=$(ARCH) $(MAKE) -C boot_prep clean ARCH=$(ARCH) $(MAKE) -C power_prep clean ARCH=$(ARCH) ---- a/uboot.db -+++ b/uboot.db -@@ -3,7 +3,7 @@ - sources { - power_prep="./power_prep/power_prep"; - sdram_prep="./boot_prep/boot_prep"; -- image="/home/b18647/repos/ltib_latest/rootfs/boot/u-boot"; -+ image="../boot/u-boot"; - } - - section (0) { diff --git a/package/boot/imx-bootlets/patches/004-fix-ARM-8933_1.patch b/package/boot/imx-bootlets/patches/004-fix-ARM-8933_1.patch new file mode 100644 index 0000000000..3b896b2889 --- /dev/null +++ b/package/boot/imx-bootlets/patches/004-fix-ARM-8933_1.patch @@ -0,0 +1,11 @@ +--- a/linux_prep/core/cmdlines.S ++++ b/linux_prep/core/cmdlines.S +@@ -14,7 +14,7 @@ + #define CMDLINES_FILE "output-target/command_lines_stripped.txt" + #endif + +- .section .cmdlines, #alloc ++ .section .cmdlines, "a" + .globl cmdlines_start + cmdlines_start: + .incbin CMDLINES_FILE diff --git a/package/boot/kexec-tools/Makefile b/package/boot/kexec-tools/Makefile index 0ab6affd3f..ffedd350f4 100644 --- a/package/boot/kexec-tools/Makefile +++ b/package/boot/kexec-tools/Makefile @@ -24,7 +24,7 @@ include $(INCLUDE_DIR)/package.mk define Package/kexec-tools/Default SECTION:=utils CATEGORY:=Utilities - URL:=http://kernel.org/pub/linux/kernel/people/horms/kexec-tools/ + URL:=https://github.com/horms/kexec-tools endef define Package/kexec-tools diff --git a/package/boot/kobs-ng/Makefile b/package/boot/kobs-ng/Makefile index 68e6ff170c..261cd92eab 100644 --- a/package/boot/kobs-ng/Makefile +++ b/package/boot/kobs-ng/Makefile @@ -18,6 +18,7 @@ PKG_BUILD_DIR:=$(BUILD_DIR)/imx-kobs-$(PKG_VERSION) PKG_LICENSE:=GPLv2 PKG_LICENSE_FILES:=COPYING +PKG_FLAGS:=nonshared include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/opensbi/Makefile b/package/boot/opensbi/Makefile index b2ef27dd71..c4ab6857c7 100644 --- a/package/boot/opensbi/Makefile +++ b/package/boot/opensbi/Makefile @@ -6,13 +6,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=opensbi -PKG_RELEASE:=1.4 +PKG_RELEASE:=1.6 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/riscv/opensbi -PKG_SOURCE_DATE:=2023-12-24 -PKG_SOURCE_VERSION:=a2b255b88918715173942f2c5e1f97ac9e90c877 -PKG_MIRROR_HASH:=a81d7b3622feba80b2a45fe0d38600be73cfbee64a0426be82a71545c10c54d3 +PKG_SOURCE_DATE:=2024-12-24 +PKG_SOURCE_VERSION:=bd613dd92113f683052acfb23d9dc8ba60029e0a +PKG_MIRROR_HASH:=247bbb751635d9414cf47cce417185fd3323e98c524eafa825dc91b76cc5c054 PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) diff --git a/package/boot/optee-os-stm32/Makefile b/package/boot/optee-os-stm32/Makefile new file mode 100644 index 0000000000..e0be8e433e --- /dev/null +++ b/package/boot/optee-os-stm32/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2024 Bootlin +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_VERSION:=4.4.0 +PKG_RELEASE:=1 + +PKG_HASH:=b13c65ff2abcd21a9200cb0131f34d61bde7c31eb0427fa761d27c3b87c7fec8 +PKG_MAINTAINER:=Thomas Richard <thomas.richard@bootlin.com> + +OPTEE_USE_INTREE_DTC:=1 + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/optee-os.mk +include $(INCLUDE_DIR)/package.mk + +define Optee-os/Default + BUILD_TARGET:=stm32 +endef + +define Optee-os/stm32mp1 + BUILD_SUBTARGET:=stm32mp1 + PLAT:=stm32mp1 +endef + +define Optee-os/stm32mp135f-dk + $(call Optee-os/stm32mp1) + NAME:=STM32MP135F-DK + PLAT_FLAVOR:=135F_DK +endef + +OPTEE_TARGETS := stm32mp135f-dk + +define Package/optee-os/install/default +endef + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(foreach img,$(OPTEE_IMAGE), \ + $(CP) $(PKG_BUILD_DIR)/out/arm-plat-$(PLAT)/core/$(img) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(img); \ + ) +endef + +$(eval $(call BuildPackage/Optee-os)) diff --git a/package/boot/rkbin/Makefile b/package/boot/rkbin/Makefile index 4eacff042c..fef19de7dc 100644 --- a/package/boot/rkbin/Makefile +++ b/package/boot/rkbin/Makefile @@ -25,6 +25,19 @@ define Trusted-Firmware-A/Default BUILD_TARGET:=rockchip endef +define Trusted-Firmware-A/rk3308 + BUILD_SUBTARGET:=armv8 + ATF:=rk33/rk3308_bl31_v2.26.elf + TPL:=rk33/rk3308_ddr_589MHz_uart2_m1_v2.07.bin +endef + +define Trusted-Firmware-A/rk3308-rock-pi-s + NAME:=Radxa ROCK Pi S + BUILD_SUBTARGET:=armv8 + ATF:=rk33/rk3308_bl31_v2.26.elf + TPL:=rk33/rk3308_ddr_589MHz_uart0_m0_v2.07.bin +endef + define Trusted-Firmware-A/rk3566 BUILD_SUBTARGET:=armv8 ATF:=rk35/rk3568_bl31_v1.44.elf @@ -37,9 +50,61 @@ define Trusted-Firmware-A/rk3568 TPL:=rk35/rk3568_ddr_1560MHz_v1.21.bin endef +define Trusted-Firmware-A/rk3568-e25 + NAME:=Radxa E25 board + BUILD_SUBTARGET:=armv8 + ATF:=rk35/rk3568_bl31_v1.44.elf + TPL:=rk35/rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin +endef + +define Trusted-Firmware-A/rk3588 + BUILD_SUBTARGET:=armv8 + ATF:=rk35/rk3588_bl31_v1.45.elf + TPL:=rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin +endef + TFA_TARGETS:= \ + rk3308 \ + rk3308-rock-pi-s \ rk3566 \ - rk3568 + rk3568 \ + rk3568-e25 \ + rk3588 + +TFA_MAKE_FLAGS+= \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") + +ifeq ($(BUILD_VARIANT),rk3308-rock-pi-s) + TPL_FILE:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin + define Download/rk3308-tpl-rock-pi-s + FILE:=$(TPL_FILE) + URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk33/ + HASH:=8a1a42df23cccb86a2dabc14a5c0e9227d64a51b9b83e9968ef5af3b30787f7d + endef + + define Build/Prepare + $(eval $(call Download,rk3308-tpl-rock-pi-s)) + $(call Build/Prepare/Default) + + $(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk33/ + endef +endif + +ifeq ($(BUILD_VARIANT),rk3568-e25) + TPL_FILE:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin + define Download/rk3568-tpl-e25 + FILE:=$(TPL_FILE) + URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk35/ + HASH:=1815f9649dc5661a3ef184b052da39286e51453a66f6ff53cc3e345d65dfabd4 + endef + + define Build/Prepare + $(eval $(call Download,rk3568-tpl-e25)) + $(call Build/Prepare/Default) + + $(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk35/ + endef +endif define Build/Compile endef diff --git a/package/boot/tfa-layerscape/Makefile b/package/boot/tfa-layerscape/Makefile index bf155b926a..1302e35c40 100644 --- a/package/boot/tfa-layerscape/Makefile +++ b/package/boot/tfa-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=tfa-layerscape -PKG_VERSION:=6.6.3.1.0.0 -PKG_RELEASE:=1 +PKG_VERSION:=6.6.23.2.0.0 +PKG_RELEASE:=2 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/atf -PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 -PKG_MIRROR_HASH:=28b731c1c4cc3226ccaef2142c61127f213c03cbd219df556c1d191e95f8470c +PKG_SOURCE_VERSION:=lf-6.6.23-2.0.0 +PKG_MIRROR_HASH:=628a95ba60a593ae0575ee9ede1154445ec3a86a07b18e4947e06e13c2b67859 PKG_BUILD_DEPENDS:=tfa-layerscape/host include $(INCLUDE_DIR)/host-build.mk @@ -25,7 +25,7 @@ HOST_CFLAGS += -Wall -Werror -pedantic -std=c99 define Host/Compile $(MAKE) -C \ $(HOST_BUILD_DIR)/tools/fiptool \ - PLAT_FIPTOOL_HELPER_MK="$(HOST_BUILD_DIR)/tools/nxp/plat_fiptool/plat_fiptool.mk" \ + PLAT_FIPTOOL_HELPER_MK="$(HOST_BUILD_DIR)/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk" \ CFLAGS="$(HOST_CFLAGS)" \ LDFLAGS="$(HOST_LDFLAGS)" \ HOSTCCFLAGS="$(HOST_CFLAGS)" @@ -161,6 +161,7 @@ TFA_TARGETS := \ lx2160a-rdb-sdboot TFA_MAKE_FLAGS += \ + $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") \ fip pbl \ BOOT_MODE=$(BOOT_MODE) \ RCW=$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-rcw.bin \ diff --git a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch index 050b4356ef..db91bd75dd 100644 --- a/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch +++ b/package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -953,10 +953,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ +@@ -128,10 +128,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$ ENCTOOLPATH ?= tools/encrypt_fw ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} @@ -11,7 +11,7 @@ # Variables for use with sptool SPTOOLPATH ?= tools/sptool SPTOOL ?= ${SPTOOLPATH}/sptool.py -@@ -1409,13 +1405,6 @@ endif +@@ -1597,13 +1593,6 @@ endif #(CHECKPATCH) clean: @echo " CLEAN" $(call SHELL_REMOVE_DIR,${BUILD_PLAT}) @@ -21,11 +21,11 @@ -# Clear the MAKEFLAGS as we do not want -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean --endif +-endif #(UNIX_MK) ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean -@@ -1424,13 +1413,6 @@ realclean distclean: +@@ -1612,13 +1601,6 @@ realclean distclean: @echo " REALCLEAN" $(call SHELL_REMOVE_DIR,${BUILD_BASE}) $(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*) @@ -35,29 +35,29 @@ -# Clear the MAKEFLAGS as we do not want -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean --endif +-endif #(UNIX_MK) ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean -@@ -1486,7 +1468,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} +@@ -1674,7 +1656,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL} @${ECHO_BLANK_LINE} - endif + endif #(GENERATE_COT) -${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} $(eval ${CHECK_FIP_CMD}) ${Q}${FIPTOOL} create ${FIP_ARGS} $@ ${Q}${FIPTOOL} info $@ -@@ -1503,7 +1485,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT +@@ -1691,7 +1673,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT @${ECHO_BLANK_LINE} - endif + endif #(GENERATE_COT) -${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL} +${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} $(eval ${CHECK_FWU_FIP_CMD}) ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ ${Q}${FIPTOOL} info $@ -@@ -1511,19 +1493,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP +@@ -1699,19 +1681,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP @echo "Built $@ successfully" @${ECHO_BLANK_LINE} @@ -72,26 +72,26 @@ -# Clear the MAKEFLAGS as we do not want -# to pass the gnumake flags to nmake. - ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) --endif +-endif #(UNIX_MK) - romlib.bin: libraries FORCE ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -67,7 +67,7 @@ all: ${PROJECT} +@@ -81,7 +81,7 @@ all: --openssl ${PROJECT} - ${PROJECT}: --openssl ${OBJECTS} Makefile + ${PROJECT}: ${OBJECTS} Makefile @echo " HOSTLD $@" -- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} -+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS) +- ${Q}${HOSTCC} ${OBJECTS} -o $@ $(LDOPTS) ++ ${Q}${HOSTCC} ${OBJECTS} -o $@ $(LDOPTS) $(LDFLAGS) @${ECHO_BLANK_LINE} @echo "Built $@ successfully" @${ECHO_BLANK_LINE} ---- a/tools/nxp/plat_fiptool/plat_fiptool.mk -+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk -@@ -22,11 +22,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C - $(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o) +--- a/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk ++++ b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk +@@ -21,11 +21,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C + -I./ ifeq (${PLAT_DEF_OID},yes) -HOSTCCFLAGS += -DPLAT_DEF_OID diff --git a/package/boot/uboot-ath79/Makefile b/package/boot/uboot-ath79/Makefile new file mode 100644 index 0000000000..52ca1c6c01 --- /dev/null +++ b/package/boot/uboot-ath79/Makefile @@ -0,0 +1,46 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_VERSION:=2024.10 +PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0 + +UBOOT_USE_INTREE_DTC:=1 + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/host-build.mk + +define U-Boot/Default + BUILD_TARGET:=ath79 + BUILD_SUBTARGET:=generic + UBOOT_IMAGE:=u-boot.bin + UBOOT_CONFIG:=ap121 + HIDDEN:=1 +endef + +define U-Boot/ar9344_nec_aterm + NAME:=NEC Aterm series (AR9344) + BUILD_SUBTARGET:= tiny + BUILD_DEVICES:=nec_wg600hp nec_wr8750n nec_wr9500n + UBOOT_CONFIG:=nec_ar9344_aterm +endef + +define U-Boot/qca9558_nec_aterm + NAME:=NEC Aterm series (QCA9558) + BUILD_SUBTARGET:= generic + BUILD_DEVICES:=nec_wg1400hp nec_wg1800hp nec_wg1800hp2 + UBOOT_CONFIG:=nec_qca9558_aterm +endef + +UBOOT_TARGETS := ar9344_nec_aterm qca9558_nec_aterm + +# don't stage files to bindir, let target/linux/ath79/image/*.mk do that +define Package/u-boot/install +endef + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(INSTALL_DATA) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE) +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-ath79/patches/001-mips-ath79-add-initial-support-for-QCA955x-SoCs.patch b/package/boot/uboot-ath79/patches/001-mips-ath79-add-initial-support-for-QCA955x-SoCs.patch new file mode 100644 index 0000000000..7d6075c9f6 --- /dev/null +++ b/package/boot/uboot-ath79/patches/001-mips-ath79-add-initial-support-for-QCA955x-SoCs.patch @@ -0,0 +1,1020 @@ +From 7c59f0fe98eb20db8dfbf4d3c67d6043a9efe116 Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi <musashino.open@gmail.com> +Date: Sat, 22 Jun 2024 20:45:31 +0900 +Subject: [PATCH 1/2] mips: ath79: add initial support for QCA955x SoCs + +--- + arch/mips/dts/qca955x.dtsi | 70 +++++ + arch/mips/mach-ath79/Kconfig | 9 + + arch/mips/mach-ath79/Makefile | 1 + + .../mach-ath79/include/mach/ar71xx_regs.h | 63 ++++ + arch/mips/mach-ath79/include/mach/ath79.h | 3 + + arch/mips/mach-ath79/qca955x/Makefile | 5 + + arch/mips/mach-ath79/qca955x/clk.c | 286 ++++++++++++++++++ + arch/mips/mach-ath79/qca955x/cpu.c | 7 + + arch/mips/mach-ath79/qca955x/ddr.c | 222 ++++++++++++++ + .../mips/mach-ath79/qca955x/qca955x-ddr-tap.S | 191 ++++++++++++ + 10 files changed, 857 insertions(+) + create mode 100644 arch/mips/dts/qca955x.dtsi + create mode 100644 arch/mips/mach-ath79/qca955x/Makefile + create mode 100644 arch/mips/mach-ath79/qca955x/clk.c + create mode 100644 arch/mips/mach-ath79/qca955x/cpu.c + create mode 100644 arch/mips/mach-ath79/qca955x/ddr.c + create mode 100644 arch/mips/mach-ath79/qca955x/qca955x-ddr-tap.S + +diff --git a/arch/mips/dts/qca955x.dtsi b/arch/mips/dts/qca955x.dtsi +new file mode 100644 +index 0000000000..93bc659743 +--- /dev/null ++++ b/arch/mips/dts/qca955x.dtsi +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++#include "skeleton.dtsi" ++ ++/ { ++ compatible = "qca,qca955x"; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "mips,mips74Kc"; ++ reg = <0>; ++ }; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ xtal: xtal { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-output-names = "xtal"; ++ }; ++ }; ++ ++ ahb { ++ compatible = "simple-bus"; ++ ranges; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ apb { ++ compatible = "simple-bus"; ++ ranges; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ uart0: uart@18020000 { ++ compatible = "ns16550"; ++ reg = <0x18020000 0x20>; ++ reg-shift = <2>; ++ ++ status = "disabled"; ++ }; ++ }; ++ ++ spi0: spi@1f000000 { ++ compatible = "qca,ar7100-spi"; ++ reg = <0x1f000000 0x10>; ++ ++ status = "disabled"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++}; +diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig +index 2fa628568a..21ac4b9f95 100644 +--- a/arch/mips/mach-ath79/Kconfig ++++ b/arch/mips/mach-ath79/Kconfig +@@ -34,6 +34,15 @@ config SOC_QCA953X + help + This supports QCA/Atheros qca953x family SOCs. + ++config SOC_QCA955X ++ bool ++ select MIPS_TUNE_74KC ++ select SUPPORT_BIG_ENDIAN ++ select SUPPORTS_CPU_MIPS32_R1 ++ select SUPPORTS_CPU_MIPS32_R2 ++ help ++ This supports QCA/Atheros qca955x family SOCs. ++ + config SOC_QCA956X + bool + select MIPS_TUNE_74KC +diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile +index fbd40c02be..cd8c1f0334 100644 +--- a/arch/mips/mach-ath79/Makefile ++++ b/arch/mips/mach-ath79/Makefile +@@ -7,4 +7,5 @@ obj-y += dram.o + obj-$(CONFIG_SOC_AR933X) += ar933x/ + obj-$(CONFIG_SOC_AR934X) += ar934x/ + obj-$(CONFIG_SOC_QCA953X) += qca953x/ ++obj-$(CONFIG_SOC_QCA955X) += qca955x/ + obj-$(CONFIG_SOC_QCA956X) += qca956x/ +diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +index 5888f6eb28..1e4860ec9c 100644 +--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h ++++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +@@ -174,11 +174,17 @@ + #define QCA955X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 ++#define QCA955X_RTC_BASE \ ++ (AR71XX_APB_BASE + 0x00107000) ++#define QCA955X_RTC_SIZE 0x1000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 + #define QCA955X_NFC_BASE 0x1b800200 + #define QCA955X_NFC_SIZE 0xb8 ++#define QCA955X_SRIF_BASE \ ++ (AR71XX_APB_BASE + 0x00116000) ++#define QCA955X_SRIF_SIZE 0x1000 + + #define QCA956X_PCI_MEM_BASE1 0x12000000 + #define QCA956X_PCI_MEM_SIZE 0x02000000 +@@ -285,6 +291,17 @@ + #define QCA953X_DDR_REG_CTL_CONF 0x108 + #define QCA953X_DDR_REG_CONFIG3 0x15c + ++#define QCA955X_DDR_REG_TAP_CTRL2 0x24 ++#define QCA955X_DDR_REG_TAP_CTRL3 0x28 ++#define QCA955X_DDR_REG_DDR2_CONFIG 0xb8 ++#define QCA955X_DDR_REG_DDR2_EMR2 0xbc ++#define QCA955X_DDR_REG_DDR2_EMR3 0xc0 ++#define QCA955X_DDR_REG_BURST 0xc4 ++#define QCA955X_DDR_REG_BURST2 0xc8 ++#define QCA955X_DDR_REG_TIMEOUT_MAX 0xcc ++#define QCA955X_DDR_REG_CTL_CONF 0x108 ++#define QCA955X_DDR_REG_CONFIG3 0x15c ++ + #define QCA956X_DDR_REG_TAP_CTRL2 0x24 + #define QCA956X_DDR_REG_TAP_CTRL3 0x28 + #define QCA956X_DDR_REG_DDR2_CONFIG 0xb8 +@@ -500,6 +517,8 @@ + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 + #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 ++#define QCA955X_PLL_DDR_DIT_FRAC_REG 0x40 ++#define QCA955X_PLL_CPU_DIT_FRAC_REG 0x44 + #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + + #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +@@ -508,8 +527,11 @@ + #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f + #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 + #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_CPU_CONFIG_RANGE_SHIFT 17 ++#define QCA955X_PLL_CPU_CONFIG_RANGE_MASK 0x3 + #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 + #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++#define QCA955X_PLL_CPU_CONFIG_PLLPWD BIT(30) + + #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 + #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +@@ -517,8 +539,11 @@ + #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f + #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 + #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA955X_PLL_DDR_CONFIG_RANGE_SHIFT 21 ++#define QCA955X_PLL_DDR_CONFIG_RANGE_MASK 0x3 + #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 + #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++#define QCA955X_PLL_DDR_CONFIG_PLLPWD BIT(30) + + #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) + #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +@@ -533,6 +558,24 @@ + #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA955X_PLL_DDR_DIT_NFRAC_MAX_SHIFT 0 ++#define QCA955X_PLL_DDR_DIT_NFRAC_MAX_MASK 0x3ff ++#define QCA955X_PLL_DDR_DIT_NFRAC_MIN_SHIFT 10 ++#define QCA955X_PLL_DDR_DIT_NFRAC_MIN_MASK 0x3ff ++#define QCA955X_PLL_DDR_DIT_NFRAC_STEP_SHIFT 20 ++#define QCA955X_PLL_DDR_DIT_NFRAC_STEP_MASK 0x7f ++#define QCA955X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 ++#define QCA955X_PLL_DDR_DIT_UPD_CNT_MASK 0xf ++ ++#define QCA955X_PLL_CPU_DIT_NFRAC_MAX_SHIFT 0 ++#define QCA955X_PLL_CPU_DIT_NFRAC_MAX_MASK 0x3f ++#define QCA955X_PLL_CPU_DIT_NFRAC_MIN_SHIFT 6 ++#define QCA955X_PLL_CPU_DIT_NFRAC_MIN_MASK 0x3f ++#define QCA955X_PLL_CPU_DIT_NFRAC_STEP_SHIFT 12 ++#define QCA955X_PLL_CPU_DIT_NFRAC_STEP_MASK 0x3f ++#define QCA955X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 ++#define QCA955X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f ++ + #define QCA956X_PLL_CPU_CONFIG_REG 0x00 + #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 +@@ -1027,6 +1070,7 @@ + #define QCA955X_GPIO_REG_OUT_FUNC3 0x38 + #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c + #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 ++#define QCA955X_GPIO_REG_IN_ENABLE0 0x44 + #define QCA955X_GPIO_REG_FUNC 0x6c + + #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +@@ -1220,6 +1264,25 @@ + #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define QCA955X_SRIF_BB_DPLL1_REG 0x180 ++#define QCA955X_SRIF_BB_DPLL2_REG 0x184 ++#define QCA955X_SRIF_BB_DPLL3_REG 0x188 ++ ++#define QCA955X_SRIF_CPU_DPLL1_REG 0xf00 ++#define QCA955X_SRIF_CPU_DPLL2_REG 0xf04 ++#define QCA955X_SRIF_CPU_DPLL3_REG 0xf08 ++ ++#define QCA955X_SRIF_DDR_DPLL1_REG 0xec0 ++#define QCA955X_SRIF_DDR_DPLL2_REG 0xec4 ++#define QCA955X_SRIF_DDR_DPLL3_REG 0xec8 ++ ++#define QCA955X_SRIF_PCIE_DPLL1_REG 0xc80 ++#define QCA955X_SRIF_PCIE_DPLL2_REG 0xc84 ++#define QCA955X_SRIF_PCIE_DPLL3_REG 0xc88 ++ ++#define QCA955X_SRIF_PMU1_REG 0xcc0 ++#define QCA955X_SRIF_PMU2_REG 0xcc4 ++ + #define QCA956X_SRIF_BB_DPLL1_REG 0x180 + #define QCA956X_SRIF_BB_DPLL2_REG 0x184 + #define QCA956X_SRIF_BB_DPLL3_REG 0x188 +diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h +index 2eda38885e..445cb2711b 100644 +--- a/arch/mips/mach-ath79/include/mach/ath79.h ++++ b/arch/mips/mach-ath79/include/mach/ath79.h +@@ -148,6 +148,9 @@ int ath79_usb_reset(void); + void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); + void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); + ++void qca955x_pll_init(void); ++void qca955x_ddr_init(void); ++ + void qca956x_pll_init(void); + void qca956x_ddr_init(void); + #endif /* __ASM_MACH_ATH79_H */ +diff --git a/arch/mips/mach-ath79/qca955x/Makefile b/arch/mips/mach-ath79/qca955x/Makefile +new file mode 100644 +index 0000000000..a405f9a12d +--- /dev/null ++++ b/arch/mips/mach-ath79/qca955x/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y += cpu.o ++obj-y += clk.o ++obj-y += ddr.o qca955x-ddr-tap.o +diff --git a/arch/mips/mach-ath79/qca955x/clk.c b/arch/mips/mach-ath79/qca955x/clk.c +new file mode 100644 +index 0000000000..20c93de163 +--- /dev/null ++++ b/arch/mips/mach-ath79/qca955x/clk.c +@@ -0,0 +1,286 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ * ++ * based on QCA956x support and QSDK ++ */ ++ ++#include <clock_legacy.h> ++#include <log.h> ++#include <asm/global_data.h> ++#include <asm/io.h> ++#include <asm/addrspace.h> ++#include <asm/types.h> ++#include <linux/bitfield.h> ++#include <linux/bitops.h> ++#include <mach/ar71xx_regs.h> ++#include <mach/ath79.h> ++#include <wait_bit.h> ++ ++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_FMASK \ ++ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK \ ++ << QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT ++#define QCA955X_PLL_CPU_CONFIG_RANGE_FMASK \ ++ QCA955X_PLL_CPU_CONFIG_RANGE_MASK \ ++ << QCA955X_PLL_CPU_CONFIG_RANGE_SHIFT ++#define QCA955X_PLL_CPU_CONFIG_REFDIV_FMASK \ ++ QCA955X_PLL_CPU_CONFIG_REFDIV_MASK \ ++ << QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT ++#define QCA955X_PLL_CPU_CONFIG_NINT_FMASK \ ++ QCA955X_PLL_CPU_CONFIG_NINT_MASK \ ++ << QCA955X_PLL_CPU_CONFIG_NINT_SHIFT ++#define QCA955X_PLL_CPU_CONFIG_NFRAC_FMASK \ ++ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK \ ++ << QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT ++ ++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_FMASK \ ++ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK \ ++ << QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT ++#define QCA955X_PLL_DDR_CONFIG_RANGE_FMASK \ ++ QCA955X_PLL_DDR_CONFIG_RANGE_MASK \ ++ << QCA955X_PLL_DDR_CONFIG_RANGE_SHIFT ++#define QCA955X_PLL_DDR_CONFIG_REFDIV_FMASK \ ++ QCA955X_PLL_DDR_CONFIG_REFDIV_MASK \ ++ << QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT ++#define QCA955X_PLL_DDR_CONFIG_NINT_FMASK \ ++ QCA955X_PLL_DDR_CONFIG_NINT_MASK \ ++ << QCA955X_PLL_DDR_CONFIG_NINT_SHIFT ++#define QCA955X_PLL_DDR_CONFIG_NFRAC_FMASK \ ++ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK \ ++ << QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT ++ ++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_FMASK \ ++ QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK \ ++ << QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT ++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_FMASK \ ++ QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK \ ++ << QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT ++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_FMASK \ ++ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK \ ++ << QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT ++ ++#define QCA955X_PLL_DDR_DIT_UPD_CNT_FMASK \ ++ QCA955X_PLL_DDR_DIT_UPD_CNT_MASK \ ++ << QCA955X_PLL_DDR_DIT_UPD_CNT_SHIFT ++#define QCA955X_PLL_DDR_DIT_NFRAC_STEP_FMASK \ ++ QCA955X_PLL_DDR_DIT_NFRAC_STEP_MASK \ ++ << QCA955X_PLL_DDR_DIT_NFRAC_STEP_SHIFT ++#define QCA955X_PLL_DDR_DIT_NFRAC_MIN_FMASK \ ++ QCA955X_PLL_DDR_DIT_NFRAC_MIN_MASK \ ++ << QCA955X_PLL_DDR_DIT_NFRAC_MIN_SHIFT ++#define QCA955X_PLL_DDR_DIT_NFRAC_MAX_FMASK \ ++ QCA955X_PLL_DDR_DIT_NFRAC_MAX_MASK \ ++ << QCA955X_PLL_DDR_DIT_NFRAC_MAX_SHIFT ++ ++#define QCA955X_PLL_CPU_DIT_UPD_CNT_FMASK \ ++ QCA955X_PLL_CPU_DIT_UPD_CNT_MASK \ ++ << QCA955X_PLL_CPU_DIT_UPD_CNT_SHIFT ++#define QCA955X_PLL_CPU_DIT_NFRAC_STEP_FMASK \ ++ QCA955X_PLL_CPU_DIT_NFRAC_STEP_MASK \ ++ << QCA955X_PLL_CPU_DIT_NFRAC_STEP_SHIFT ++#define QCA955X_PLL_CPU_DIT_NFRAC_MIN_FMASK \ ++ QCA955X_PLL_CPU_DIT_NFRAC_MIN_MASK \ ++ << QCA955X_PLL_CPU_DIT_NFRAC_MIN_SHIFT ++#define QCA955X_PLL_CPU_DIT_NFRAC_MAX_FMASK \ ++ QCA955X_PLL_CPU_DIT_NFRAC_MAX_MASK \ ++ << QCA955X_PLL_CPU_DIT_NFRAC_MAX_SHIFT ++ ++#define PLL_SRIF_DPLL2_KI_MASK GENMASK(29, 26) ++#define PLL_SRIF_DPLL2_KD_MASK GENMASK(25, 19) ++#define PLL_SRIF_DPLL2_PLL_PWD_MASK BIT(16) ++#define PLL_SRIF_DPLL2_DELTA_MASK GENMASK(12, 7) ++ ++#define PLL_SRIF_DPLL2_DEFAULT \ ++ FIELD_PREP(PLL_SRIF_DPLL2_KI_MASK, 0x4) | \ ++ FIELD_PREP(PLL_SRIF_DPLL2_KD_MASK, 0x60) | \ ++ FIELD_PREP(PLL_SRIF_DPLL2_PLL_PWD_MASK, 0x1) | \ ++ FIELD_PREP(PLL_SRIF_DPLL2_DELTA_MASK, 0x1e) ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static u32 qca955x_get_xtal(void) ++{ ++ u32 val; ++ ++ val = ath79_get_bootstrap(); ++ if (val & QCA955X_BOOTSTRAP_REF_CLK_40) ++ return 40000000; ++ else ++ return 25000000; ++} ++ ++int get_serial_clock(void) ++{ ++ return qca955x_get_xtal(); ++} ++ ++void qca955x_pll_init(void) ++{ ++ void __iomem *srif_regs = map_physmem(QCA955X_SRIF_BASE, ++ QCA955X_SRIF_SIZE, MAP_NOCACHE); ++ void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, ++ AR71XX_PLL_SIZE, MAP_NOCACHE); ++ ++ /* 10.33.2 Baseband DPLL2 */ ++ writel(PLL_SRIF_DPLL2_DEFAULT, ++ srif_regs + QCA955X_SRIF_BB_DPLL2_REG); ++ ++ /* 10.33.2 PCIE DPLL2 */ ++ writel(PLL_SRIF_DPLL2_DEFAULT, ++ srif_regs + QCA955X_SRIF_PCIE_DPLL2_REG); ++ ++ /* 10.33.2 DDR DPLL2 */ ++ writel(PLL_SRIF_DPLL2_DEFAULT, ++ srif_regs + QCA955X_SRIF_DDR_DPLL2_REG); ++ ++ /* 10.33.2 CPU DPLL2 */ ++ writel(PLL_SRIF_DPLL2_DEFAULT, ++ srif_regs + QCA955X_SRIF_CPU_DPLL2_REG); ++ ++ /* pll_bypass_set */ ++ setbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS); ++ setbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS); ++ setbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS); ++ ++ /* init_cpu_pll (720_600_240) */ ++ writel(QCA955X_PLL_CPU_CONFIG_PLLPWD | ++ FIELD_PREP(QCA955X_PLL_CPU_CONFIG_OUTDIV_FMASK, 0x0) | ++ FIELD_PREP(QCA955X_PLL_CPU_CONFIG_RANGE_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_CPU_CONFIG_REFDIV_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_CPU_CONFIG_NINT_FMASK, 0x12), ++ pll_regs + QCA955X_PLL_CPU_CONFIG_REG); ++ ++ /* init_ddr_pll (720_600_240) */ ++ writel(QCA955X_PLL_DDR_CONFIG_PLLPWD | ++ FIELD_PREP(QCA955X_PLL_DDR_CONFIG_OUTDIV_FMASK, 0x0) | ++ FIELD_PREP(QCA955X_PLL_DDR_CONFIG_RANGE_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_DDR_CONFIG_REFDIV_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_DDR_CONFIG_NINT_FMASK, 0xf), ++ pll_regs + QCA955X_PLL_DDR_CONFIG_REG); ++ ++ /* init_ahb_pll (720_600_240) */ ++ writel(/* use CPU PLL for AHB (0) */ ++ /* use DDR PLL for DDR (0) */ ++ /* use CPU PLL for CPU (0) */ ++ FIELD_PREP(QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_FMASK, 0x2) | ++ FIELD_PREP(QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_FMASK, 0x0) | ++ FIELD_PREP(QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_FMASK, 0x0) | ++ QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS | ++ QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS | ++ QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS, ++ pll_regs + QCA955X_PLL_CLK_CTRL_REG); ++ ++ /* pll_pwd_unset */ ++ clrbits_be32(pll_regs + QCA955X_PLL_CPU_CONFIG_REG, ++ QCA955X_PLL_CPU_CONFIG_PLLPWD); ++ clrbits_be32(pll_regs + QCA955X_PLL_DDR_CONFIG_REG, ++ QCA955X_PLL_DDR_CONFIG_PLLPWD); ++ ++ /* outdiv_unset */ ++ clrbits_be32(pll_regs + QCA955X_PLL_CPU_CONFIG_REG, ++ QCA955X_PLL_CPU_CONFIG_OUTDIV_FMASK); ++ clrbits_be32(pll_regs + QCA955X_PLL_DDR_CONFIG_REG, ++ QCA955X_PLL_DDR_CONFIG_OUTDIV_FMASK); ++ ++ /* pll_bypass_unset */ ++ clrbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS); ++ clrbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS); ++ clrbits_be32(pll_regs + QCA955X_PLL_CLK_CTRL_REG, ++ QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS); ++ ++ /* ddr_pll_dither_unset */ ++ writel(FIELD_PREP(QCA955X_PLL_DDR_DIT_UPD_CNT_FMASK, 0xf) | ++ FIELD_PREP(QCA955X_PLL_DDR_DIT_NFRAC_STEP_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_DDR_DIT_NFRAC_MIN_FMASK, 0x0) | ++ FIELD_PREP(QCA955X_PLL_DDR_DIT_NFRAC_MAX_FMASK, 0x3ff), ++ pll_regs + QCA955X_PLL_DDR_DIT_FRAC_REG); ++ ++ /* cpu_pll_dither_unset */ ++ writel(FIELD_PREP(QCA955X_PLL_CPU_DIT_UPD_CNT_FMASK, 0xf) | ++ FIELD_PREP(QCA955X_PLL_CPU_DIT_NFRAC_STEP_FMASK, 0x1) | ++ FIELD_PREP(QCA955X_PLL_CPU_DIT_NFRAC_MIN_FMASK, 0x0) | ++ FIELD_PREP(QCA955X_PLL_CPU_DIT_NFRAC_MAX_FMASK, 0x3f), ++ pll_regs + QCA955X_PLL_CPU_DIT_FRAC_REG); ++} ++ ++int get_clocks(void) ++{ ++ void __iomem *regs; ++ u32 pll, cpu_pll, ddr_pll, clk_ctrl; ++ u32 cpu_clk, ddr_clk, ahb_clk; ++ u32 outdiv, refdiv, nint, nfrac, postdiv; ++ u32 xtal = qca955x_get_xtal(); ++ ++ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, ++ MAP_NOCACHE); ++ pll = readl(regs + QCA955X_PLL_CPU_CONFIG_REG); ++ outdiv = FIELD_GET(QCA955X_PLL_CPU_CONFIG_OUTDIV_FMASK, pll); ++ refdiv = FIELD_GET(QCA955X_PLL_CPU_CONFIG_REFDIV_FMASK, pll); ++ nint = FIELD_GET(QCA955X_PLL_CPU_CONFIG_NINT_FMASK, pll); ++ nfrac = FIELD_GET(QCA955X_PLL_CPU_CONFIG_NFRAC_FMASK, pll); ++ ++ cpu_pll = (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); ++ ++ pll = readl(regs + QCA955X_PLL_DDR_CONFIG_REG); ++ outdiv = FIELD_GET(QCA955X_PLL_DDR_CONFIG_OUTDIV_FMASK, pll); ++ refdiv = FIELD_GET(QCA955X_PLL_DDR_CONFIG_REFDIV_FMASK, pll); ++ nint = FIELD_GET(QCA955X_PLL_DDR_CONFIG_NINT_FMASK, pll); ++ nfrac = FIELD_GET(QCA955X_PLL_DDR_CONFIG_NFRAC_FMASK, pll); ++ ++ ddr_pll = (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); ++ ++ clk_ctrl = readl(regs + QCA955X_PLL_CLK_CTRL_REG); ++ ++ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_FMASK, clk_ctrl); ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ cpu_clk = xtal; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ cpu_clk = ddr_pll / (postdiv + 1); ++ else ++ cpu_clk = cpu_pll / (postdiv + 1); ++ ++ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_FMASK, clk_ctrl); ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ddr_clk = xtal; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ddr_clk = cpu_pll / (postdiv + 1); ++ else ++ ddr_clk = ddr_pll / (postdiv + 1); ++ ++ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_FMASK, clk_ctrl); ++ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ahb_clk = xtal; ++ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ahb_clk = ddr_pll; ++ else ++ ahb_clk = cpu_pll; ++ ahb_clk /= (postdiv + 1); ++ ++ gd->cpu_clk = cpu_clk; ++ gd->mem_clk = ddr_clk; ++ gd->bus_clk = ahb_clk; ++ ++ debug("cpu_clk=%u, ddr_clk=%u, bus_clk=%u\n", ++ cpu_clk, ddr_clk, ahb_clk); ++ ++ return 0; ++} ++ ++ulong get_bus_freq(ulong dummy) ++{ ++ if (!gd->bus_clk) ++ get_clocks(); ++ return gd->bus_clk; ++} ++ ++ulong get_ddr_freq(ulong dummy) ++{ ++ if (!gd->mem_clk) ++ get_clocks(); ++ return gd->mem_clk; ++} +diff --git a/arch/mips/mach-ath79/qca955x/cpu.c b/arch/mips/mach-ath79/qca955x/cpu.c +new file mode 100644 +index 0000000000..9405871444 +--- /dev/null ++++ b/arch/mips/mach-ath79/qca955x/cpu.c +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++/* The lowlevel_init() is not needed on QCA955X */ ++void lowlevel_init(void) {} +diff --git a/arch/mips/mach-ath79/qca955x/ddr.c b/arch/mips/mach-ath79/qca955x/ddr.c +new file mode 100644 +index 0000000000..654a410d95 +--- /dev/null ++++ b/arch/mips/mach-ath79/qca955x/ddr.c +@@ -0,0 +1,222 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ * ++ * Based on QCA956x support and QSDK ++ */ ++ ++#include <asm/global_data.h> ++#include <asm/io.h> ++#include <asm/addrspace.h> ++#include <asm/types.h> ++#include <linux/bitfield.h> ++#include <linux/bitops.h> ++#include <linux/delay.h> ++#include <mach/ar71xx_regs.h> ++#include <mach/ath79.h> ++ ++#define DDR_CONFIG_CAS_LATENCY_MSB_MASK BIT(31) ++#define DDR_CONFIG_OPEN_PAGE_MASK BIT(30) ++#define DDR_CONFIG_CAS_LATENCY_MASK GENMASK(29, 27) ++#define DDR_CONFIG_TMRD_MASK GENMASK(26, 23) ++#define DDR_CONFIG_TRFC_MASK GENMASK(22, 17) ++#define DDR_CONFIG_TRRD_MASK GENMASK(16, 13) ++#define DDR_CONFIG_TRP_MASK GENMASK(12, 9) ++#define DDR_CONFIG_TRCD_MASK GENMASK(8, 5) ++#define DDR_CONFIG_TRAS_MASK GENMASK(4, 0) ++ ++#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK BIT(31) ++#define DDR_CONFIG2_SWAP_A26_A27_MASK BIT(30) ++#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK GENMASK(29, 26) ++#define DDR_CONFIG2_TWTR_MASK GENMASK(25, 21) ++#define DDR_CONFIG2_TRTP_MASK GENMASK(20, 17) ++#define DDR_CONFIG2_TRTW_MASK GENMASK(16, 12) ++#define DDR_CONFIG2_TWR_MASK GENMASK(11, 8) ++#define DDR_CONFIG2_CKE_MASK BIT(7) ++#define DDR_CONFIG2_CNTL_OE_EN_MASK BIT(5) ++#define DDR_CONFIG2_BURST_LENGTH_MASK GENMASK(3, 0) ++ ++#define DDR_CTL_CONFIG_SRAM_TSEL_MASK GENMASK(31, 30) ++#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK BIT(20) ++#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK BIT(19) ++#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK BIT(18) ++#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK BIT(17) ++#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK BIT(16) ++#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK BIT(15) ++#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK BIT(14) ++#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK BIT(6) ++#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK BIT(2) ++#define DDR_CTL_CONFIG_HALF_WIDTH_MASK BIT(1) ++ ++#define RST_BOOTSTRAP_DDR_WIDTH_MASK BIT(3) ++ ++#define PMU2_PGM_MASK BIT(21) ++#define PMU2_LDO_TUNE_MASK GENMASK(20, 19) ++ ++/* ++* DDR2 DDR1 ++* 0x40c3 25MHz 0x4186 25Mhz ++* 0x4138 40MHz 0x4270 40Mhz ++*/ ++#define CFG_DDR2_REFRESH_VAL 0x4138 ++ ++#define CFG_DDR2_CONFIG_VAL \ ++ DDR_CONFIG_CAS_LATENCY_MSB_MASK | DDR_CONFIG_OPEN_PAGE_MASK | \ ++ FIELD_PREP(DDR_CONFIG_CAS_LATENCY_MASK, 0x4) | \ ++ FIELD_PREP(DDR_CONFIG_TMRD_MASK, 0xf) | \ ++ FIELD_PREP(DDR_CONFIG_TRFC_MASK, 0x15) | \ ++ FIELD_PREP(DDR_CONFIG_TRRD_MASK, 0x7) | \ ++ FIELD_PREP(DDR_CONFIG_TRP_MASK, 0x9) | \ ++ FIELD_PREP(DDR_CONFIG_TRCD_MASK, 0x9) | \ ++ FIELD_PREP(DDR_CONFIG_TRAS_MASK, 0x1b) ++ ++#define CFG_DDR2_CONFIG2_VAL \ ++ DDR_CONFIG2_HALF_WIDTH_LOW_MASK | /* SWAP_A26_A27 is off */ \ ++ FIELD_PREP(DDR_CONFIG2_GATE_OPEN_LATENCY_MASK, 0xb) | \ ++ FIELD_PREP(DDR_CONFIG2_TWTR_MASK, 0x15) | \ ++ FIELD_PREP(DDR_CONFIG2_TRTP_MASK, 0x9) | \ ++ FIELD_PREP(DDR_CONFIG2_TRTW_MASK, 0xe) | \ ++ FIELD_PREP(DDR_CONFIG2_TWR_MASK, 0x1) | \ ++ DDR_CONFIG2_CKE_MASK | DDR_CONFIG2_CNTL_OE_EN_MASK | \ ++ FIELD_PREP(DDR_CONFIG2_BURST_LENGTH_MASK, 0x8) ++ ++#define CFG_DDR2_CONFIG3_VAL 0x0000000a ++#define CFG_DDR2_EXT_MODE_VAL1 0x782 ++#define CFG_DDR2_EXT_MODE_VAL2 0x402 ++#define CFG_DDR2_MODE_VAL_INIT 0x153 ++#define CFG_DDR2_MODE_VAL 0x53 ++#define CFG_DDR2_TAP_VAL 0x10 ++#define CFG_DDR2_EN_TWL_VAL 0x00001e7d ++#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff ++#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff ++ ++#define CFG_DDR_CTL_CONFIG \ ++ FIELD_PREP(DDR_CTL_CONFIG_SRAM_TSEL_MASK, 0x1) | \ ++ DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK | \ ++ DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK /* for DDR2 */ ++ /* CPU_DDR_SYNC is off (CPU clk != DDR clk) */ ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++void qca955x_ddr_init(void) ++{ ++ u32 cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32; ++ u32 ctl_config = CFG_DDR_CTL_CONFIG; ++ void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, ++ MAP_NOCACHE); ++ void __iomem *srif_regs = map_physmem(QCA955X_SRIF_BASE, QCA955X_SRIF_SIZE, ++ MAP_NOCACHE); ++ ++ /* 16bit */ ++ if (!(ath79_get_bootstrap() & RST_BOOTSTRAP_DDR_WIDTH_MASK)) ++ { ++ ctl_config |= DDR_CTL_CONFIG_HALF_WIDTH_MASK; ++ cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16; ++ } ++ ++ writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); ++ udelay(10); ++ ++ writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); ++ udelay(10); ++ ++ writel(ctl_config, ddr_regs + QCA955X_DDR_REG_CTL_CONF); ++ udelay(10); ++ ++ writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); ++ udelay(100); ++ ++ writel(0x74444444, ddr_regs + QCA955X_DDR_REG_BURST); ++ udelay(100); ++ ++ writel(0x44444444, ddr_regs + QCA955X_DDR_REG_BURST2); ++ udelay(100); ++ ++ writel(0xfffff, ddr_regs + QCA955X_DDR_REG_TIMEOUT_MAX); ++ udelay(100); ++ ++ writel(CFG_DDR2_CONFIG_VAL, ddr_regs + AR71XX_DDR_REG_CONFIG); ++ udelay(100); ++ ++ writel(CFG_DDR2_CONFIG2_VAL, ddr_regs + AR71XX_DDR_REG_CONFIG2); ++ udelay(100); ++ ++ writel(CFG_DDR2_CONFIG3_VAL, ddr_regs + QCA955X_DDR_REG_CONFIG3); ++ udelay(100); ++ ++ writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA955X_DDR_REG_DDR2_CONFIG); ++ udelay(100); ++ ++ writel(CFG_DDR2_CONFIG2_VAL | 0x80, ++ ddr_regs + AR71XX_DDR_REG_CONFIG2); /* CKE Enable */ ++ udelay(100); ++ ++ writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ ++ udelay(10); ++ ++ writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR2 */ ++ udelay(10); ++ ++ writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR3 */ ++ udelay(10); ++ ++ /* EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled */ ++ writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); ++ udelay(100); ++ ++ writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ ++ udelay(10); ++ ++ writel(CFG_DDR2_MODE_VAL_INIT, ddr_regs + AR71XX_DDR_REG_MODE); ++ udelay(1000); ++ ++ writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR Write */ ++ udelay(10); ++ ++ writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */ ++ udelay(10); ++ ++ writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ ++ udelay(10); ++ ++ writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */ ++ udelay(10); ++ ++ /* Issue MRS to remove DLL out-of-reset */ ++ writel(CFG_DDR2_MODE_VAL, ddr_regs + AR71XX_DDR_REG_MODE); ++ udelay(100); ++ ++ writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */ ++ udelay(100); ++ ++ writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR); ++ udelay(100); ++ ++ writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ ++ udelay(100); ++ ++ writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR); ++ udelay(100); ++ ++ writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */ ++ udelay(100); ++ ++ writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH); ++ udelay(100); ++ ++ writel(CFG_DDR2_TAP_VAL, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); ++ writel(CFG_DDR2_TAP_VAL, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); ++ writel(CFG_DDR2_TAP_VAL, ddr_regs + QCA955X_DDR_REG_TAP_CTRL2); ++ writel(CFG_DDR2_TAP_VAL, ddr_regs + QCA955X_DDR_REG_TAP_CTRL3); ++ ++ writel(0x633c8176, srif_regs + QCA955X_SRIF_PMU1_REG); ++ /* Set DDR2 Voltage to 1.8 volts */ ++ writel(PMU2_PGM_MASK | FIELD_PREP(PMU2_LDO_TUNE_MASK, 0x3), ++ srif_regs + QCA955X_SRIF_PMU2_REG); ++} +diff --git a/arch/mips/mach-ath79/qca955x/qca955x-ddr-tap.S b/arch/mips/mach-ath79/qca955x/qca955x-ddr-tap.S +new file mode 100644 +index 0000000000..1c117a5b69 +--- /dev/null ++++ b/arch/mips/mach-ath79/qca955x/qca955x-ddr-tap.S +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ * ++ * Based on QSDK ++ */ ++ ++#include <config.h> ++#include <asm/asm.h> ++#include <asm/regdef.h> ++#include <asm/mipsregs.h> ++#include <asm/addrspace.h> ++#include <mach/ar71xx_regs.h> ++ ++ .set noreorder ++ ++LEAF(ddr_tap_tuning) ++ li a0, 0xbd007f00 ++ sw zero, 0x0(a0) /* Place where the tap values are saved and used for SWEEP */ ++ sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */ ++ sw zero, 0x14(a0) /* Place where the last pass tap value is stored */ ++ li a1, 0xaa55aa55 /* Indicates that the First pass tap value is not found */ ++ sw a1, 0x10(a0) /* Place where the First pass tap value is stored */ ++ nop ++ ++ li a0, CKSEG1ADDR(AR71XX_RESET_BASE) ++ lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */ ++ li a2, 0x08000000 /* Setting the RST_RESET_RTC_RESET */ ++ or a1, a1, a2 ++ sw a1, 0x1c(a0) ++ ++ li a3, 0xffffffff ++ xor a2, a2, a3 ++ and a1, a1, a2 ++ sw a1, 0x1c(a0) /* Taking the RTC out of RESET */ ++ nop ++ ++ li a0, CKSEG1ADDR(QCA955X_RTC_BASE) ++ li a1, 0x1 ++ sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */ ++ ++ li a2, 0x2 ++ ++_poll_for_RTC_ON: ++ lw a1, 0x0044(a0) /* RTC_SYNC_STATUS_ADDRESS */ ++ and a1, a2, a1 ++ bne a1, a2, _poll_for_RTC_ON ++ nop ++ ++_CHANGE_TAPS: ++ li t0, 0xbd007f00 /* Read the current value of the TAP for programming */ ++ lw t1, 0x0(t0) ++ li t2, 0x00000000 ++ or t3, t1, t2 ++ ++ li t0, CKSEG1ADDR(AR71XX_DDR_CTRL_BASE) ++ sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */ ++ sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */ ++ sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */ ++ sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */ ++ ++ li t1, 0x00000010 /* Running the test 8 times */ ++ sw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */ ++ ++ li t1, 0xfa5de83f /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */ ++ sw t1, 0x002c(t0) /* PERF_MASK_ADDR_0_ADDRESS */ ++ ++ li t1, 0x545fc332 ++ sw t1, 0x0070(t0) /* PERF_COMP_AHB_GE0_1_ADDRESS */ ++ ++ li t1, 0xaba03ccd ++ sw t1, 0x0040(t0) /* PERF_COMP_AHB_GE1_0_ADDRESS */ ++ ++ li t1, 0x545fc332 ++ sw t1, 0x0078(t0) /* PERF_COMP_AHB_GE1_1_ADDRESS */ ++ ++ li t1, 0xaba03ccd ++ sw t1, 0x0034(t0) /* PERF_MASK_AHB_GE0_0_ADDRESS */ ++ ++ li t1, 0x545fc332 ++ sw t1, 0x006c(t0) /* PERF_MASK_AHB_GE0_1_ADDRESS */ ++ ++ li t1, 0xaba03ccd ++ sw t1, 0x003c(t0) /* PERF_MASK_AHB_GE1_0_ADDRESS */ ++ ++ li t1, 0x545fc332 ++ sw t1, 0x0074(t0) /* PERF_MASK_AHB_GE1_1_ADDRESS */ ++ ++ li t1, 0xaba03ccd ++ sw t1, 0x0038(t0) /* PERF_COMP_AHB_GE0_0_ADDRESS */ ++ ++ li t1, 0x00000001 ++ sw t1, 0x011c(t0) /* DDR_BIST_ADDRESS */ ++ ++ li t2, 0x1 ++ ++_bist_done_poll: ++ lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */ ++ and t1, t1, t2 ++ bne t1, t2, _bist_done_poll ++ nop ++ ++ lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */ ++ li t4, 0x000001fe ++ and t2, t1, t4 ++ srl t2, t2, 0x1 /* no. of Pass Runs */ ++ ++ li t5, 0x00000000 ++ sw t5, 0x011c(t0) /* DDR_BIST_ADDRESS - Stop the DDR BIST test */ ++ ++ li t5, 0x0001fe00 ++ and t5, t5, t1 ++ bnez t5, _iterate_tap /* This is a redundant compare but nevertheless - Comparing the FAILS */ ++ nop ++ ++ lw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */ ++ li t3, 0x000001fe ++ and t3, t3, t1 ++ srl t3, t3, 0x1 /* No. of runs in the config register. */ ++ bne t3, t2, _iterate_tap ++ nop ++ ++pass_tap: ++ li t0, 0xbd007f00 ++ lw t1, 0x4(t0) ++ addiu t1, t1, 0x1 ++ sw t1, 0x4(t0) ++ ++ li t0, 0xbd007f10 ++ lw t1, 0x0(t0) ++ li t2, 0xaa55aa55 ++ beq t1, t2, _first_pass ++ nop ++ ++ li t0, 0xbd007f00 ++ lw t1, 0x0(t0) ++ li t0, 0xbd007f10 ++ sw t1, 0x4(t0) ++ nop ++ b _iterate_tap ++ nop ++ ++_first_pass: ++ li t0, 0xbd007f00 ++ lw t1, 0x0(t0) ++ li t0, 0xbd007f10 ++ sw t1, 0x0(t0) ++ sw t1, 0x4(t0) ++ nop ++ ++_iterate_tap: ++ li t0, 0xbd007f00 ++ lw t1, 0x0(t0) ++ li t2, 0x3f ++ beq t1, t2, _STOP_TEST ++ nop ++ addiu t1, t1, 0x1 ++ sw t1, 0x0(t0) ++ nop ++ b _CHANGE_TAPS ++ nop ++ ++_STOP_TEST: ++ li t0, 0xbd007f00 ++ lw t1, 0x4(t0) ++ bnez t1, _load_center_tap ++ nop ++ li t3, 0x8 /* Default Tap to be used */ ++ b _load_tap_into_reg ++ nop ++ ++_load_center_tap: ++ li t0, 0xbd007f10 ++ lw t1, 0x0(t0) ++ lw t2, 0x4(t0) ++ add t3, t1, t2 ++ srl t3, t3, 0x1 ++ li t4, 0x3f ++ and t3, t3, t4 ++ ++_load_tap_into_reg: ++ li t0, CKSEG1ADDR(AR71XX_DDR_CTRL_BASE) ++ sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */ ++ sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */ ++ sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */ ++ sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */ ++ ++ nop ++ jr ra ++ nop ++ END(ddr_tap_tuning) +-- +2.43.0 + diff --git a/package/boot/uboot-ath79/patches/400-ath79-add-support-for-NEC-AR9344-Aterm-series.patch b/package/boot/uboot-ath79/patches/400-ath79-add-support-for-NEC-AR9344-Aterm-series.patch new file mode 100644 index 0000000000..5d87d22651 --- /dev/null +++ b/package/boot/uboot-ath79/patches/400-ath79-add-support-for-NEC-AR9344-Aterm-series.patch @@ -0,0 +1,287 @@ +From 80a7688c478a6a372083c29ff0b1826db4dae5b2 Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi <musashino.open@gmail.com> +Date: Wed, 24 Apr 2024 23:54:46 +0900 +Subject: [PATCH] ath79: add support for NEC AR9344 Aterm series + +--- + arch/mips/dts/Makefile | 1 + + arch/mips/dts/nec,ar9344-aterm.dts | 35 +++++++++++++++ + arch/mips/mach-ath79/Kconfig | 5 +++ + board/nec/ar9344_aterm/Kconfig | 30 +++++++++++++ + board/nec/ar9344_aterm/Makefile | 3 ++ + board/nec/ar9344_aterm/ar9344_aterm.c | 59 ++++++++++++++++++++++++++ + configs/nec_ar9344_aterm_defconfig | 61 +++++++++++++++++++++++++++ + include/configs/nec_ar9344_aterm.h | 28 ++++++++++++ + 8 files changed, 222 insertions(+) + create mode 100644 arch/mips/dts/nec,ar9344-aterm.dts + create mode 100644 board/nec/ar9344_aterm/Kconfig + create mode 100644 board/nec/ar9344_aterm/Makefile + create mode 100644 board/nec/ar9344_aterm/ar9344_aterm.c + create mode 100644 configs/nec_ar9344_aterm_defconfig + create mode 100644 include/configs/nec_ar9344_aterm.h + +--- a/arch/mips/dts/Makefile ++++ b/arch/mips/dts/Makefile +@@ -24,6 +24,7 @@ dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY + dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb + dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb + dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb ++dtb-$(CONFIG_BOARD_NEC_AR9344_ATERM) += nec,ar9344-aterm.dtb + dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb + dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb + dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb +--- /dev/null ++++ b/arch/mips/dts/nec,ar9344-aterm.dts +@@ -0,0 +1,35 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++/dts-v1/; ++#include "ar934x.dtsi" ++ ++/ { ++ model = "NEC Aterm series (AR9344)"; ++ compatible = "nec,ar9344-aterm", "qca,ar934x"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:9600n8"; ++ }; ++}; ++ ++&uart0 { ++ clock-frequency = <40000000>; ++ status = "okay"; ++}; ++ ++&xtal { ++ clock-frequency = <40000000>; ++}; ++ ++/* delete unused nodes to reduce dtb size */ ++/delete-node/ &ehci0; ++/delete-node/ &gmac0; ++/delete-node/ &gmac1; ++/delete-node/ &spi0; +--- a/arch/mips/mach-ath79/Kconfig ++++ b/arch/mips/mach-ath79/Kconfig +@@ -67,6 +67,10 @@ config TARGET_AP152 + bool "AP152 Reference Board" + select SOC_QCA956X + ++config BOARD_NEC_AR9344_ATERM ++ bool "NEC Aterm series Boards (AR9344)" ++ select SOC_AR934X ++ + config BOARD_TPLINK_WDR4300 + bool "TP-Link WDR4300 Board" + select SOC_AR934X +@@ -76,6 +80,7 @@ endchoice + source "board/qca/ap121/Kconfig" + source "board/qca/ap143/Kconfig" + source "board/qca/ap152/Kconfig" ++source "board/nec/ar9344_aterm/Kconfig" + source "board/tplink/wdr4300/Kconfig" + + endmenu +--- /dev/null ++++ b/board/nec/ar9344_aterm/Kconfig +@@ -0,0 +1,30 @@ ++if BOARD_NEC_AR9344_ATERM ++ ++config SYS_VENDOR ++ default "nec" ++ ++config SYS_SOC ++ default "ath79" ++ ++config SYS_BOARD ++ default "ar9344_aterm" ++ ++config SYS_CONFIG_NAME ++ default "nec_ar9344_aterm" ++ ++config TEXT_BASE ++ default 0x9f000000 ++ ++config SYS_DCACHE_SIZE ++ default 32768 ++ ++config SYS_DCACHE_LINE_SIZE ++ default 32 ++ ++config SYS_ICACHE_SIZE ++ default 65536 ++ ++config SYS_ICACHE_LINE_SIZE ++ default 32 ++ ++endif +--- /dev/null ++++ b/board/nec/ar9344_aterm/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y = ar9344_aterm.o +--- /dev/null ++++ b/board/nec/ar9344_aterm/ar9344_aterm.c +@@ -0,0 +1,59 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++#include <init.h> ++#include <asm/io.h> ++#include <asm/addrspace.h> ++#include <asm/types.h> ++#include <mach/ath79.h> ++#include <mach/ar71xx_regs.h> ++#include <mach/ddr.h> ++#include <debug_uart.h> ++ ++static void aterm_pinmux_config(void) ++{ ++ void __iomem *regs; ++ ++ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, ++ MAP_NOCACHE); ++ ++ /* Disable JTAG */ ++ writel(0x2, regs + AR934X_GPIO_REG_FUNC); ++ ++ /* Configure default GPIO OE/SET regs */ ++ writel(0x3db1f, regs + AR71XX_GPIO_REG_OE); ++ writel(0x142000, regs + AR71XX_GPIO_REG_SET); ++ ++ /* Configure pin multiplexing */ ++ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0); ++ writel(0x0b0a0900, regs + AR934X_GPIO_REG_OUT_FUNC1); ++ writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2); ++ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3); ++ writel(0x2f2e0000, regs + AR934X_GPIO_REG_OUT_FUNC4); ++ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5); ++} ++ ++#ifdef CONFIG_DEBUG_UART_BOARD_INIT ++void board_debug_uart_init(void) ++{ ++ aterm_pinmux_config(); ++} ++#endif ++ ++#ifdef CONFIG_BOARD_EARLY_INIT_F ++int board_early_init_f(void) ++{ ++#ifndef CONFIG_DEBUG_UART_BOARD_INIT ++ aterm_pinmux_config(); ++#endif ++ ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) ++ ar934x_pll_init(560, 480, 240); ++ ar934x_ddr_init(560, 480, 240); ++#endif ++ ++ return 0; ++} ++#endif +--- /dev/null ++++ b/configs/nec_ar9344_aterm_defconfig +@@ -0,0 +1,61 @@ ++CONFIG_MIPS=y ++CONFIG_SYS_MALLOC_LEN=0x40000 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd007fff ++CONFIG_ENV_SIZE=0x1000 ++CONFIG_DEFAULT_DEVICE_TREE="nec,ar9344-aterm" ++CONFIG_SYS_LOAD_ADDR=0x83000000 ++CONFIG_ARCH_ATH79=y ++CONFIG_BOARD_NEC_AR9344_ATERM=y ++CONFIG_SYS_MIPS_TIMER_FREQ=280000000 ++CONFIG_MIPS_RELOCATION_TABLE_SIZE=0x4000 ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_TIMESTAMP=y ++CONFIG_BOOTDELAY=3 ++# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyS0,115200" ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="bootm 0x9f040000" ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_SYS_MALLOC_BOOTPARAMS=y ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set ++CONFIG_SYS_MAXARGS=32 ++# CONFIG_SYS_XTRACE is not set ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_CONSOLE is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_FDT is not set ++# CONFIG_CMD_RUN is not set ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EXPORTENV is not set ++# CONFIG_CMD_IMPORTENV is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_SAVEENV is not set ++# CONFIG_CMD_ENV_EXISTS is not set ++# CONFIG_CMD_CRC32 is not set ++# CONFIG_CMD_DM is not set ++# CONFIG_CMD_LOADS is not set ++# CONFIG_CMD_ECHO is not set ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SOURCE is not set ++# CONFIG_CMD_SETEXPR is not set ++# CONFIG_CMD_SLEEP is not set ++# CONFIG_ISO_PARTITION is not set ++# CONFIG_OF_TAG_MIGRATE is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_NET is not set ++CONFIG_CLK=y ++# CONFIG_GPIO is not set ++# CONFIG_I2C is not set ++# CONFIG_INPUT is not set ++# CONFIG_POWER is not set ++CONFIG_DM_SERIAL=y ++CONFIG_SYS_NS16550=y ++# CONFIG_GZIP is not set +--- /dev/null ++++ b/include/configs/nec_ar9344_aterm.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++#ifndef __NEC_AR9344_ATERM_H ++#define __NEC_AR9344_ATERM_H ++ ++#define CFG_SYS_SDRAM_BASE 0x80000000 ++ ++#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 ++#define CFG_SYS_INIT_RAM_SIZE 0x8000 ++ ++/* ++ * Serial Port ++ */ ++#define CFG_SYS_NS16550_CLK 40000000 ++ ++/* ++ * Command ++ */ ++/* Miscellaneous configurable options */ ++ ++/* ++ * Diagnostics ++ */ ++ ++#endif /* __NEC_AR9344_ATERM_H */ diff --git a/package/boot/uboot-ath79/patches/401-mips-ath79-add-support-for-NEC-QCA9558-Aterm-series.patch b/package/boot/uboot-ath79/patches/401-mips-ath79-add-support-for-NEC-QCA9558-Aterm-series.patch new file mode 100644 index 0000000000..c06dae28f0 --- /dev/null +++ b/package/boot/uboot-ath79/patches/401-mips-ath79-add-support-for-NEC-QCA9558-Aterm-series.patch @@ -0,0 +1,284 @@ +From 3e01c3042fdc638f6edc57a6e64a111a785589fd Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi <musashino.open@gmail.com> +Date: Sun, 23 Jun 2024 04:09:14 +0900 +Subject: [PATCH 2/2] mips: ath79: add support for NEC QCA9558 Aterm series + +mips: ath79: cleanup defconfig for NEC QCA9558 Aterm series +--- + arch/mips/dts/Makefile | 1 + + arch/mips/dts/nec,qca9558-aterm.dts | 32 +++++++++++++ + arch/mips/mach-ath79/Kconfig | 5 ++ + board/nec/qca9558_aterm/Kconfig | 30 ++++++++++++ + board/nec/qca9558_aterm/Makefile | 3 ++ + board/nec/qca9558_aterm/qca9558_aterm.c | 58 +++++++++++++++++++++++ + configs/nec_qca9558_aterm_defconfig | 61 +++++++++++++++++++++++++ + include/configs/nec_qca9558_aterm.h | 28 ++++++++++++ + 8 files changed, 218 insertions(+) + create mode 100644 arch/mips/dts/nec,qca9558-aterm.dts + create mode 100644 board/nec/qca9558_aterm/Kconfig + create mode 100644 board/nec/qca9558_aterm/Makefile + create mode 100644 board/nec/qca9558_aterm/qca9558_aterm.c + create mode 100644 configs/nec_qca9558_aterm_defconfig + create mode 100644 include/configs/nec_qca9558_aterm.h + +--- a/arch/mips/dts/Makefile ++++ b/arch/mips/dts/Makefile +@@ -25,6 +25,7 @@ dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += + dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb + dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb + dtb-$(CONFIG_BOARD_NEC_AR9344_ATERM) += nec,ar9344-aterm.dtb ++dtb-$(CONFIG_BOARD_NEC_QCA9558_ATERM) += nec,qca9558-aterm.dtb + dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb + dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb + dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb +--- /dev/null ++++ b/arch/mips/dts/nec,qca9558-aterm.dts +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++/dts-v1/; ++#include "qca955x.dtsi" ++ ++/ { ++ model = "NEC Aterm series (QCA9558)"; ++ compatible = "nec,qca9558-aterm", "qca,qca955x"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:9600n8"; ++ }; ++}; ++ ++&uart0 { ++ clock-frequency = <40000000>; ++ status = "okay"; ++}; ++ ++&xtal { ++ clock-frequency = <40000000>; ++}; ++ ++/* delete unused node to reduce dtb size */ ++/delete-node/ &spi0; +--- a/arch/mips/mach-ath79/Kconfig ++++ b/arch/mips/mach-ath79/Kconfig +@@ -71,6 +71,10 @@ config BOARD_NEC_AR9344_ATERM + bool "NEC Aterm series Boards (AR9344)" + select SOC_AR934X + ++config BOARD_NEC_QCA9558_ATERM ++ bool "NEC Aterm series Boards (QCA9558)" ++ select SOC_QCA955X ++ + config BOARD_TPLINK_WDR4300 + bool "TP-Link WDR4300 Board" + select SOC_AR934X +@@ -81,6 +85,7 @@ source "board/qca/ap121/Kconfig" + source "board/qca/ap143/Kconfig" + source "board/qca/ap152/Kconfig" + source "board/nec/ar9344_aterm/Kconfig" ++source "board/nec/qca9558_aterm/Kconfig" + source "board/tplink/wdr4300/Kconfig" + + endmenu +--- /dev/null ++++ b/board/nec/qca9558_aterm/Kconfig +@@ -0,0 +1,30 @@ ++if BOARD_NEC_QCA9558_ATERM ++ ++config SYS_VENDOR ++ default "nec" ++ ++config SYS_SOC ++ default "ath79" ++ ++config SYS_BOARD ++ default "qca9558_aterm" ++ ++config SYS_CONFIG_NAME ++ default "nec_qca9558_aterm" ++ ++config TEXT_BASE ++ default 0x9f000000 ++ ++config SYS_DCACHE_SIZE ++ default 32768 ++ ++config SYS_DCACHE_LINE_SIZE ++ default 32 ++ ++config SYS_ICACHE_SIZE ++ default 65536 ++ ++config SYS_ICACHE_LINE_SIZE ++ default 32 ++ ++endif +--- /dev/null ++++ b/board/nec/qca9558_aterm/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y = qca9558_aterm.o +--- /dev/null ++++ b/board/nec/qca9558_aterm/qca9558_aterm.c +@@ -0,0 +1,58 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++#include <init.h> ++#include <asm/io.h> ++#include <asm/addrspace.h> ++#include <asm/types.h> ++#include <mach/ath79.h> ++#include <mach/ar71xx_regs.h> ++#include <mach/ddr.h> ++#include <debug_uart.h> ++ ++static void aterm_pinmux_config(void) ++{ ++ void __iomem *regs = map_physmem(AR71XX_GPIO_BASE, ++ AR71XX_GPIO_SIZE, MAP_NOCACHE); ++ ++ /* Disable JTAG */ ++ writel(0x2, regs + QCA955X_GPIO_REG_FUNC); ++ ++ /* Configure default GPIO OE/SET regs */ ++ writel(0xa6031f, regs + AR71XX_GPIO_REG_OE); ++ writel(0x402800, regs + AR71XX_GPIO_REG_SET); ++ ++ /* Configure pin multiplexing */ ++ writel(0x00000000, regs + QCA955X_GPIO_REG_OUT_FUNC0); ++ writel(0x0c080900, regs + QCA955X_GPIO_REG_OUT_FUNC1); ++ writel(0x00160000, regs + QCA955X_GPIO_REG_OUT_FUNC2); ++ writel(0x00000000, regs + QCA955X_GPIO_REG_OUT_FUNC3); ++ writel(0x00000000, regs + QCA955X_GPIO_REG_OUT_FUNC4); ++ writel(0x00000000, regs + QCA955X_GPIO_REG_OUT_FUNC5); ++ writel(0x00000908, regs + QCA955X_GPIO_REG_IN_ENABLE0); ++} ++ ++#ifdef CONFIG_DEBUG_UART_BOARD_INIT ++void board_debug_uart_init(void) ++{ ++ aterm_pinmux_config(); ++} ++#endif ++ ++#ifdef CONFIG_BOARD_EARLY_INIT_F ++int board_early_init_f(void) ++{ ++#ifndef CONFIG_DEBUG_UART_BOARD_INIT ++ aterm_pinmux_config(); ++#endif ++ ++#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) ++ qca955x_pll_init(); ++ qca955x_ddr_init(); ++#endif ++ ++ return 0; ++} ++#endif +--- /dev/null ++++ b/configs/nec_qca9558_aterm_defconfig +@@ -0,0 +1,61 @@ ++CONFIG_MIPS=y ++CONFIG_SYS_MALLOC_LEN=0x40000 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xbd007fff ++CONFIG_ENV_SIZE=0x1000 ++CONFIG_DEFAULT_DEVICE_TREE="nec,qca9558-aterm" ++CONFIG_SYS_LOAD_ADDR=0x83000000 ++CONFIG_ARCH_ATH79=y ++CONFIG_BOARD_NEC_QCA9558_ATERM=y ++CONFIG_SYS_MIPS_TIMER_FREQ=280000000 ++CONFIG_MIPS_RELOCATION_TABLE_SIZE=0x4000 ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_TIMESTAMP=y ++CONFIG_BOOTDELAY=3 ++# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyS0,115200" ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="bootm 0x9f040000" ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_SYS_MALLOC_BOOTPARAMS=y ++# CONFIG_CMDLINE_EDITING is not set ++# CONFIG_AUTO_COMPLETE is not set ++# CONFIG_SYS_LONGHELP is not set ++CONFIG_SYS_MAXARGS=32 ++# CONFIG_SYS_XTRACE is not set ++# CONFIG_CMD_BDI is not set ++# CONFIG_CMD_CONSOLE is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_FDT is not set ++# CONFIG_CMD_RUN is not set ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EXPORTENV is not set ++# CONFIG_CMD_IMPORTENV is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_SAVEENV is not set ++# CONFIG_CMD_ENV_EXISTS is not set ++# CONFIG_CMD_CRC32 is not set ++# CONFIG_CMD_DM is not set ++# CONFIG_CMD_LOADS is not set ++# CONFIG_CMD_ECHO is not set ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SOURCE is not set ++# CONFIG_CMD_SETEXPR is not set ++# CONFIG_CMD_SLEEP is not set ++# CONFIG_ISO_PARTITION is not set ++# CONFIG_OF_TAG_MIGRATE is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_NET is not set ++CONFIG_CLK=y ++# CONFIG_GPIO is not set ++# CONFIG_I2C is not set ++# CONFIG_INPUT is not set ++# CONFIG_POWER is not set ++CONFIG_DM_SERIAL=y ++CONFIG_SYS_NS16550=y ++# CONFIG_GZIP is not set +--- /dev/null ++++ b/include/configs/nec_qca9558_aterm.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2024 INAGAKI Hiroshi <musashino.open@gmail.com> ++ */ ++ ++#ifndef __NEC_QCA9558_ATERM_H ++#define __NEC_QCA9558_ATERM_H ++ ++#define CFG_SYS_SDRAM_BASE 0x80000000 ++ ++#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 ++#define CFG_SYS_INIT_RAM_SIZE 0x8000 ++ ++/* ++ * Serial Port ++ */ ++#define CFG_SYS_NS16550_CLK 40000000 ++ ++/* ++ * Command ++ */ ++/* Miscellaneous configurable options */ ++ ++/* ++ * Diagnostics ++ */ ++ ++#endif /* __NEC_QCA9558_ATERM_H */ diff --git a/package/boot/uboot-d1/Makefile b/package/boot/uboot-d1/Makefile index 083a219baf..611922443b 100644 --- a/package/boot/uboot-d1/Makefile +++ b/package/boot/uboot-d1/Makefile @@ -30,7 +30,7 @@ define U-Boot/dongshan_nezha_stu OPENSBI:=generic DEPENDS:=+opensbi_generic UBOOT_DTS:=sun20i-d1-dongshan-nezha-stu.dtb - BUILD_DEVICES:=dongshan_nezha_stu + BUILD_DEVICES:=100ask_dongshan-nezha-stu endef define U-Boot/lichee_rv_dock @@ -38,7 +38,7 @@ define U-Boot/lichee_rv_dock OPENSBI:=generic DEPENDS:=+opensbi_generic UBOOT_DTS:=sun20i-d1-lichee-rv-dock.dtb - BUILD_DEVICES:=lichee_rv_dock + BUILD_DEVICES:=sipeed_lichee-rv-dock endef define U-Boot/mangopi_mq_pro @@ -46,7 +46,7 @@ define U-Boot/mangopi_mq_pro OPENSBI:=generic DEPENDS:=+opensbi_generic UBOOT_DTS:=sun20i-d1-mangopi-mq-pro.dtb - BUILD_DEVICES:=mangopi_mq_pro + BUILD_DEVICES:=widora_mangopi-mq-pro endef define U-Boot/nezha @@ -54,7 +54,7 @@ define U-Boot/nezha OPENSBI:=generic DEPENDS:=+opensbi_generic UBOOT_DTS:=sun20i-d1-nezha.dtb - BUILD_DEVICES:=nezha + BUILD_DEVICES:=allwinner_d1-nezha endef UBOOT_TARGETS := \ @@ -74,7 +74,7 @@ endef define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS) - $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE) + $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-$(UBOOT_IMAGE) mkimage -C none -A riscv -T script -d uEnv-$(UENV).txt \ $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr endef diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 19c3073c74..5b52c3b395 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot -PKG_VERSION:=2024.07 +PKG_VERSION:=2025.01 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 @@ -17,7 +17,7 @@ PKG_SOURCE_URL:= \ https://ftp.denx.de/pub/u-boot \ https://mirror.cyberbits.eu/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=f591da9ab90ef3d6b3d173766d0ddff90c4ed7330680897486117df390d83c8f +PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION) @@ -71,6 +71,9 @@ define Package/uboot-envtools/install $(LN) fw_printenv $(1)/usr/sbin/fw_setenv $(INSTALL_BIN) ./files/fw_printsys $(1)/usr/sbin $(INSTALL_BIN) ./files/fw_setsys $(1)/usr/sbin + $(INSTALL_BIN) ./files/fw_loadenv $(1)/usr/sbin + $(INSTALL_DIR) $(1)/etc/board.d + $(INSTALL_DATA) ./files/fw_defaults $(1)/etc/board.d/05_fw_defaults $(INSTALL_DIR) $(1)/lib $(INSTALL_DATA) ./files/uboot-envtools.sh $(1)/lib $(INSTALL_DIR) $(1)/etc/uci-defaults diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79 index 099aebcfa2..c989e61bd5 100644 --- a/package/boot/uboot-envtools/files/ath79 +++ b/package/boot/uboot-envtools/files/ath79 @@ -20,6 +20,7 @@ alfa-network,n5q|\ alfa-network,pi-wifi4|\ alfa-network,r36a|\ alfa-network,tube-2hq|\ +alfa-network,wifi-camppro-nano-duo|\ araknis,an-300-ap-i-n|\ arduino,yun|\ asus,rt-ac59u|\ @@ -27,6 +28,7 @@ asus,rt-ac59u-v2|\ asus,zenwifi-cd6n|\ asus,zenwifi-cd6r|\ buffalo,bhr-4grv2|\ +buffalo,wzr-450hp2|\ devolo,magic-2-wifi|\ engenius,eap300-v2|\ engenius,eap350-v1|\ @@ -89,6 +91,8 @@ zyxel,nbg6616) aruba,ap-105|\ aruba,ap-115|\ aruba,ap-175|\ +belkin,f9j1108-v2|\ +belkin,f9k1115-v2|\ dongwon,dw02-412h-64m|\ dongwon,dw02-412h-128m|\ glinet,gl-ar300m-lite|\ @@ -118,7 +122,8 @@ domywifi,dw33d) glinet,gl-ar150) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x8000" "0x10000" ;; -huawei,ap5030dn) +huawei,ap5030dn|\ +huawei,ap6010dn) ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x20000" "0x20000" ;; netgear,wndr3700|\ @@ -159,6 +164,7 @@ ruckus,zf7372) ubootenv_add_uci_config "/dev/mtd2" "0x0" "0x40000" "0x10000" ;; sophos,ap15|\ +sophos,ap15c|\ sophos,ap55|\ sophos,ap55c|\ sophos,ap100|\ diff --git a/package/boot/uboot-envtools/files/fw_defaults b/package/boot/uboot-envtools/files/fw_defaults new file mode 100644 index 0000000000..42558aaa88 --- /dev/null +++ b/package/boot/uboot-envtools/files/fw_defaults @@ -0,0 +1,17 @@ +. /lib/functions/uci-defaults.sh + +fw_loadenv + +board_config_update + +[ -f /var/run/uboot-env/owrt_ssid -a -f /var/run/uboot-env/owrt_wifi_key ] && + ucidef_set_wireless all "$(cat /var/run/uboot-env/owrt_ssid)" sae-mixed "$(cat /var/run/uboot-env/owrt_wifi_key)" +[ -f /var/run/uboot-env/owrt_country ] && ucidef_set_country "$(cat /var/run/uboot-env/owrt_country)" +[ -f /var/run/uboot-env/owrt_ssh_auth_key ] && ucidef_set_ssh_authorized_key "$(cat /var/run/uboot-env/owrt_ssh_auth_key)" +[ -f /var/run/uboot-env/owrt_root_password_plain ] && ucidef_set_root_password_plain "$(cat /var/run/uboot-env/owrt_root_password_plain)" +[ -f /var/run/uboot-env/owrt_root_password_hash ] && ucidef_set_root_password_hash "$(cat /var/run/uboot-env/owrt_root_password_hash)" +[ -f /var/run/uboot-env/owrt_timezone ] && ucidef_set_timezone "$(cat /var/run/uboot-env/owrt_timezone)" + +board_config_flush + +exit 0 diff --git a/package/boot/uboot-envtools/files/fw_loadenv b/package/boot/uboot-envtools/files/fw_loadenv new file mode 100644 index 0000000000..9fe302ce89 --- /dev/null +++ b/package/boot/uboot-envtools/files/fw_loadenv @@ -0,0 +1,26 @@ +#!/usr/bin/ucode + +'use strict'; + +const path = '/var/run/uboot-env/'; + +import * as fs from 'fs'; + +if (fs.lsdir(path)) { + warn(`env has already been loaded to ${path}\n`); + exit(0); +} + +let fp = fs.popen('fw_printenv'); +let raw = fp.read('all'); +fp.close(); + +if (!length(raw)) + exit(0); + +fs.mkdir(path); +for (let line in split(raw, '\n')) { + let vals = split(line, '='); + if (vals[0] && vals[1]) + fs.writefile(path + vals[0], vals[1]); +} diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 0e30c489c9..bf107cc135 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -33,6 +33,35 @@ ubootenv_add_ubi_default() { } case "$board" in +abt,asr3000|\ +h3c,magic-nx30-pro|\ +jcg,q30-pro|\ +mercusys,mr90x-v1-ubi|\ +netcore,n60|\ +nokia,ea0326gmp|\ +qihoo,360t7|\ +routerich,ax3000-ubootmod|\ +tplink,tl-xdr4288|\ +tplink,tl-xdr6086|\ +tplink,tl-xdr6088|\ +tplink,tl-xtr8488|\ +xiaomi,mi-router-ax3000t-ubootmod|\ +xiaomi,mi-router-wr30u-ubootmod|\ +xiaomi,redmi-router-ax6000-ubootmod|\ +zyxel,ex5601-t0-ubootmod) + ubootenv_add_ubi_default + ;; +acer,predator-w6|\ +acer,predator-w6d|\ +acer,vero-w6m|\ +glinet,gl-mt2500|\ +glinet,gl-mt6000|\ +glinet,gl-x3000|\ +glinet,gl-xe3000|\ +nradio,c8-668gl) + local envdev=$(find_mmc_part "u-boot-env") + ubootenv_add_uci_config "$envdev" "0x0" "0x80000" + ;; asus,rt-ax59u) ubootenv_add_uci_config "/dev/mtd0" "0x100000" "0x20000" "0x20000" ;; @@ -40,32 +69,23 @@ bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ bananapi,bpi-r4-poe|\ +cmcc,rax3000m|\ jdcloud,re-cp-03) - . /lib/upgrade/common.sh - - bootdev="$(fitblk_get_bootdev)" - case "$bootdev" in - ubi*) + . /lib/upgrade/fit.sh + export_fitblk_bootdev + case "$CI_METHOD" in + ubi) ubootenv_add_ubi_default ;; - mmc*) - ubootenv_add_mmc_default "${bootdev%%p[0-9]*}" + emmc) + bootdev=${EMMC_KERN_DEV%%p[0-9]*} + ubootenv_add_mmc_default "${bootdev#/dev/}" ;; - mtd*) + default) ubootenv_add_nor_default ;; esac ;; -cmcc,rax3000m) - case "$(cmdline_get_var root)" in - /dev/mmc*) - ubootenv_add_mmc_default - ;; - *) - ubootenv_add_ubi_default - ;; - esac - ;; comfast,cf-e393ax) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000" ;; @@ -76,33 +96,19 @@ zbtlink,zbt-z8102ax|\ zbtlink,zbt-z8103ax) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" ;; -dlink,aquila-pro-ai-m30-a1) +dlink,aquila-pro-ai-m30-a1|\ +dlink,aquila-pro-ai-m60-a1) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x40000" ;; -h3c,magic-nx30-pro|\ -jcg,q30-pro|\ -netcore,n60|\ -nokia,ea0326gmp|\ -qihoo,360t7|\ -tplink,tl-xdr4288|\ -tplink,tl-xdr6086|\ -tplink,tl-xdr6088|\ -xiaomi,mi-router-ax3000t-ubootmod|\ -xiaomi,mi-router-wr30u-ubootmod|\ -xiaomi,redmi-router-ax6000-ubootmod|\ -zyxel,ex5601-t0-ubootmod) - ubootenv_add_ubi_default - ;; -glinet,gl-mt2500|\ -glinet,gl-mt6000) - local envdev=$(find_mmc_part "u-boot-env") - ubootenv_add_uci_config "$envdev" "0x0" "0x80000" +gatonetworks,gdsp) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x10000" ;; glinet,gl-mt3000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000" ;; mercusys,mr90x-v1|\ routerich,ax3000|\ +tenbay,wr3000k|\ tplink,re6000xd) local envdev=/dev/mtd$(find_mtd_index "u-boot-env") ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1" @@ -111,7 +117,11 @@ openembed,som7981) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x80000" ubootenv_add_uci_sys_config "/dev/mtd3" "0x0" "0x100000" "0x100000" ;; +openwrt,one) + ubootenv_add_ubi_default + ;; smartrg,sdg-8733|\ +smartrg,sdg-8733a|\ smartrg,sdg-8734) local envdev=$(find_mmc_part "u-boot-env" "mmcblk0") ubootenv_add_uci_config "$envdev" "0x0" "0x8000" "0x8000" diff --git a/package/boot/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-envtools/files/mediatek_mt7622 index 6698e06ee3..fd40b664e4 100644 --- a/package/boot/uboot-envtools/files/mediatek_mt7622 +++ b/package/boot/uboot-envtools/files/mediatek_mt7622 @@ -31,17 +31,16 @@ dlink,eagle-pro-ai-m32-a1|\ dlink,eagle-pro-ai-r32-a1) ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000" ;; +bananapi,bpi-r64|\ linksys,e8450-ubi) - ubootenv_add_ubi_default - ;; -bananapi,bpi-r64) - . /lib/upgrade/common.sh - bootdev="$(fitblk_get_bootdev)" - case "$bootdev" in - mmc*) - ubootenv_add_mmc_default "${bootdev%p[0-9]*}" + . /lib/upgrade/fit.sh + export_fitblk_bootdev + case "$CI_METHOD" in + emmc) + bootdev=${EMMC_KERN_DEV%%p[0-9]*} + ubootenv_add_mmc_default "${bootdev#/dev/}" ;; - ubi*) + ubi) ubootenv_add_ubi_default ;; esac @@ -57,11 +56,13 @@ ubnt,unifi-6-lr-v2-ubootmod|\ ubnt,unifi-6-lr-v3-ubootmod) ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000" ;; -ubnt,unifi-6-lr-v2) +ubnt,unifi-6-lr-v2|\ +ubnt,unifi-6-lr-v3) ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x1000" "1" ;; xiaomi,redmi-router-ax6s) ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000" + ubootenv_add_uci_sys_config "/dev/mtd4" "0x0" "0x10000" "0x40000" ;; esac diff --git a/package/boot/uboot-envtools/files/mediatek_mt7629 b/package/boot/uboot-envtools/files/mediatek_mt7629 index 313fb6a448..ce09caffab 100644 --- a/package/boot/uboot-envtools/files/mediatek_mt7629 +++ b/package/boot/uboot-envtools/files/mediatek_mt7629 @@ -16,6 +16,9 @@ iptime,a6004mx|\ netgear,ex6250-v2) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" ;; +linksys,ea7500-v3) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x20000" + ;; esac config_load ubootenv diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq50xx b/package/boot/uboot-envtools/files/qualcommax_ipq50xx new file mode 100644 index 0000000000..b63451d627 --- /dev/null +++ b/package/boot/uboot-envtools/files/qualcommax_ipq50xx @@ -0,0 +1,23 @@ +[ -e /etc/config/ubootenv ] && exit 0 + +touch /etc/config/ubootenv + +. /lib/uboot-envtools.sh +. /lib/functions.sh + +board=$(board_name) + +case "$board" in +linksys,mx2000|\ +linksys,mx5500|\ +linksys,spnmx56) + idx="$(find_mtd_index u_env)" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" + ;; +esac + +config_load ubootenv +config_foreach ubootenv_add_app_config + +exit 0 diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq60xx b/package/boot/uboot-envtools/files/qualcommax_ipq60xx index 749b053aab..2dc60bebe1 100644 --- a/package/boot/uboot-envtools/files/qualcommax_ipq60xx +++ b/package/boot/uboot-envtools/files/qualcommax_ipq60xx @@ -7,22 +7,27 @@ touch /etc/config/ubootenv board=$(board_name) +ubootenv_add_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" +} + case "$board" in 8devices,mango-dvk|\ -8devices,mango-dvk-sfp) - idx="$(find_mtd_index 0:APPSBLENV)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" +8devices,mango-dvk-sfp|\ +cambiumnetworks,xe3-4) + ubootenv_add_mtd "0:APPSBLENV" "0x0" "0x10000" "0x10000" ;; -netgear,wax214) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2" +linksys,mr7350) + ubootenv_add_mtd "u_env" "0x0" "0x40000" "0x20000" + ;; +netgear,wax214|\ +tplink,eap610-outdoor) + ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000" ;; yuncore,fap650) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" + ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x10000" ;; esac diff --git a/package/boot/uboot-envtools/files/qualcommax_ipq807x b/package/boot/uboot-envtools/files/qualcommax_ipq807x index 4ae0de4e26..21ec0ae5b1 100644 --- a/package/boot/uboot-envtools/files/qualcommax_ipq807x +++ b/package/boot/uboot-envtools/files/qualcommax_ipq807x @@ -7,66 +7,72 @@ touch /etc/config/ubootenv board=$(board_name) +ubootenv_add_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && \ + ubootenv_add_uci_config "/dev/mtd$idx" "${2}" "${3}" "${4}" +} + +ubootenv_add_sys_mtd() { + local idx="$(find_mtd_index "${1}")" + [ -n "$idx" ] && \ + ubootenv_add_uci_sys_config "/dev/mtd$idx" "${2}" "${3}" "${4}" +} + +ubootenv_add_mmc() { + local mmcpart="$(find_mmc_part "${1}")" + [ -n "$mmcpart" ] && \ + ubootenv_add_uci_config "$mmcpart" "${2}" "${3}" "${4}" "${5}" +} + case "$board" in +aliyun,ap8220|\ +compex,wpq873|\ +edgecore,eap102|\ +zyxel,nbg7815) + ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x10000" + ;; dynalink,dl-wrx36|\ netgear,rax120v2|\ +netgear,sxr80|\ +netgear,sxs80|\ netgear,wax218|\ netgear,wax620|\ -netgear,wax630) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2" - ;; -compex,wpq873|\ -edgecore,eap102|\ -zyxel,nbg7815) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1" +netgear,wax630|\ +tplink,eap620hd-v1|\ +tplink,eap660hd-v1) + ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x20000" ;; edimax,cax1800) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000" + ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x20000" + ;; +linksys,homewrk) + ubootenv_add_mtd "0:appsblenv" "0x0" "0x40000" "0x40000" ;; linksys,mx4200v1|\ linksys,mx4200v2|\ linksys,mx5300|\ linksys,mx8500) - idx="$(find_mtd_index u_env)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2" + ubootenv_add_mtd "u_env" "0x0" "0x40000" "0x20000" ;; -netgear,sxr80|\ -netgear,sxs80) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" +linksys,mx4300) + ubootenv_add_mtd "u_env" "0x0" "0x40000" "0x40000" ;; redmi,ax6|\ xiaomi,ax3600|\ xiaomi,ax9000) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x20000" - idx2="$(find_mtd_index bdata)" - [ -n "$idx2" ] && \ - ubootenv_add_uci_sys_config "/dev/mtd$idx2" "0x0" "0x10000" "0x20000" + ubootenv_add_mtd "0:appsblenv" "0x0" "0x10000" "0x20000" + ubootenv_add_sys_mtd "bdata" "0x0" "0x10000" "0x20000" ;; prpl,haze) - mmcpart="$(find_mmc_part 0:APPSBLENV)" - [ -n "$mmcpart" ] && \ - ubootenv_add_uci_config "$mmcpart" "0x0" "0x40000" "0x400" "0x100" + ubootenv_add_mmc "0:APPSBLENV" "0x0" "0x40000" "0x400" "0x100" ;; +asus,rt-ax89x|\ qnap,301w) - idx="$(find_mtd_index 0:appsblenv)" - [ -n "$idx" ] && \ - ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x20000" "0x20000" "1" + ubootenv_add_mtd "0:appsblenv" "0x0" "0x20000" "0x20000" ;; spectrum,sax1v1k) - mmcpart="$(find_mmc_part 0:APPSBLENV)" - [ -n "$mmcpart" ] && \ - ubootenv_add_uci_config "$mmcpart" "0x0" "0x40000" "0x40000" "1" + ubootenv_add_mmc "0:APPSBLENV" "0x0" "0x40000" "0x40000" "1" ;; esac diff --git a/package/boot/uboot-envtools/files/ramips b/package/boot/uboot-envtools/files/ramips index 3deb46c295..ace29907da 100644 --- a/package/boot/uboot-envtools/files/ramips +++ b/package/boot/uboot-envtools/files/ramips @@ -69,6 +69,7 @@ zte,mf283plus) ;; asus,rt-ax53u|\ asus,rt-ax54|\ +asus,4g-ax56|\ belkin,rt1800|\ elecom,wrc-x1800gs|\ h3c,tx1800-plus|\ @@ -79,6 +80,7 @@ jcg,q20|\ linksys,e7350|\ netgear,eax12|\ netgear,wax202|\ +netis,n6|\ zyxel,wsm20) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" ;; @@ -146,6 +148,14 @@ xiaomi,mi-router-cr6608|\ xiaomi,mi-router-cr6609) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x20000" ;; +dna,valokuitu-plus-ex400) + ubootenv_add_uci_config "/dev/ubi0_0" "0x0" "0x1f000" "0x1f000" "1" + ubootenv_add_uci_config "/dev/ubi0_1" "0x0" "0x1f000" "0x1f000" "1" + ;; +netgear,wax214v2) + ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000" + ubootenv_add_uci_sys_config "/dev/mtd1" "0x20000" "0x8000" "0x20000" + ;; esac config_load ubootenv diff --git a/package/boot/uboot-envtools/files/realtek b/package/boot/uboot-envtools/files/realtek index cd2446432d..055730eb27 100644 --- a/package/boot/uboot-envtools/files/realtek +++ b/package/boot/uboot-envtools/files/realtek @@ -28,6 +28,7 @@ zyxel,gs1900-10hp|\ zyxel,gs1900-16|\ zyxel,gs1900-24-v1|\ zyxel,gs1900-24e|\ +zyxel,gs1900-24ep|\ zyxel,gs1900-24hp-v1|\ zyxel,gs1900-24hp-v2) idx="$(find_mtd_index u-boot-env)" diff --git a/package/boot/uboot-envtools/files/rockchip_armv8 b/package/boot/uboot-envtools/files/rockchip_armv8 new file mode 100644 index 0000000000..075776a1ff --- /dev/null +++ b/package/boot/uboot-envtools/files/rockchip_armv8 @@ -0,0 +1,23 @@ +# +# Copyright (C) 2024 OpenWrt.org +# +[ -e /etc/config/ubootenv ] && exit 0 + +touch /etc/config/ubootenv + +. /lib/uboot-envtools.sh +. /lib/functions.sh + +board=$(board_name) + +case "$board" in +xunlong,orangepi-r1-plus|\ +xunlong,orangepi-r1-plus-lts) + ubootenv_add_uci_config "/dev/mmcblk0" "0x3f8000" "0x8000" + ;; +esac + +config_load ubootenv +config_foreach ubootenv_add_app_config + +exit 0 diff --git a/package/boot/uboot-kirkwood/Makefile b/package/boot/uboot-kirkwood/Makefile index 7338e5d868..afeee805a0 100644 --- a/package/boot/uboot-kirkwood/Makefile +++ b/package/boot/uboot-kirkwood/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_VERSION:=2020.04 -PKG_RELEASE:=10 +PKG_RELEASE:=11 PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372 diff --git a/package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch b/package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch index 16a1f08c84..1da50467ef 100644 --- a/package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch +++ b/package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch @@ -1,9 +1,9 @@ -arm: kirkwood: add ZyXEL NSA310 device +arm: kirkwood: add Zyxel NSA310 device -This patch add ZyXEL NSA310 1-Bay Media Server +This patch add Zyxel NSA310 1-Bay Media Server -The ZyXEL NSA310 device is a Kirkwood based NAS: +The Zyxel NSA310 device is a Kirkwood based NAS: - SoC: Marvell 88F6702 1200Mhz - SDRAM memory: 256MB DDR2 400Mhz @@ -512,7 +512,7 @@ NOTE: this patch is ready for upstream, LEDE-specific parts are in +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_TARGET_NSA310=y -+CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server" ++CONFIG_IDENT_STRING="\nZyxel NSA310 1-Bay Power Media Server" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="NSA310> " diff --git a/package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch b/package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch index db9a7a6fb2..71a4a65197 100644 --- a/package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch +++ b/package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch @@ -297,7 +297,7 @@ + /* reset the phy */ + miiphy_reset(name, devadr); + -+ /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */ ++ /* The Zyxel NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */ + /* and has an MCU attached to the LED[2] via tristate interrupt */ + reg = 0; + @@ -496,7 +496,7 @@ +CONFIG_KIRKWOOD=y +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_TARGET_NSA325=y -+CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server" ++CONFIG_IDENT_STRING="\nZyxel NSA325 2-Bay Power Media Server" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="NSA325> " diff --git a/package/boot/uboot-kirkwood/patches/180-netgear-stora.patch b/package/boot/uboot-kirkwood/patches/180-netgear-stora.patch index c6aced4221..bdf82ebea5 100644 --- a/package/boot/uboot-kirkwood/patches/180-netgear-stora.patch +++ b/package/boot/uboot-kirkwood/patches/180-netgear-stora.patch @@ -230,7 +230,7 @@ + --- /dev/null +++ b/board/Marvell/netgear_ms2110/netgear_ms2110.c -@@ -0,0 +1,151 @@ +@@ -0,0 +1,152 @@ +/* + * Copyright (C) 2014-2017 bodhi <mibodhi@gmail.com> + * @@ -264,6 +264,7 @@ +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include "netgear_ms2110.h" ++#include <asm/arch/cpu.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; diff --git a/package/boot/uboot-kirkwood/patches/200-openwrt-config.patch b/package/boot/uboot-kirkwood/patches/200-openwrt-config.patch index 4cf874b368..00bc29f13e 100644 --- a/package/boot/uboot-kirkwood/patches/200-openwrt-config.patch +++ b/package/boot/uboot-kirkwood/patches/200-openwrt-config.patch @@ -1,6 +1,6 @@ --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig -@@ -111,4 +111,7 @@ source "board/alliedtelesis/SBx81LIFXCAT +@@ -115,4 +115,7 @@ source "board/alliedtelesis/SBx81LIFXCAT source "board/Marvell/db-88f6281-bp/Kconfig" source "board/checkpoint/l-50/Kconfig" diff --git a/package/boot/uboot-lantiq/Makefile b/package/boot/uboot-lantiq/Makefile index 927fbcb9c0..efee4507e5 100644 --- a/package/boot/uboot-lantiq/Makefile +++ b/package/boot/uboot-lantiq/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=u-boot PKG_VERSION:=2013.10 -PKG_RELEASE:=66 +PKG_RELEASE:=67 PKG_HASH:=0d71e62beb952b41ebafb20a7ee4df2f960db64c31b054721ceb79ff14014c55 @@ -280,14 +280,14 @@ define U-Boot/fb3370_sfspl endef define U-Boot/p2812hnufx_ram - NAME:=ZyXEL P-2812HNU-Fx (RAM) + NAME:=Zyxel P-2812HNU-Fx (RAM) BUILD_SUBTARGET:=xrx200 BUILD_DEVICES:=zyxel_p-2812hnu-f1 DDR_SETTINGS:=board/zyxel/p2812hnufx/ddr_settings.h endef define U-Boot/p2812hnufx_nandspl - NAME:=ZyXEL P-2812HNU-Fx (NAND SPL) + NAME:=Zyxel P-2812HNU-Fx (NAND SPL) BUILD_SUBTARGET:=xrx200 BUILD_DEVICES:=zyxel_p-2812hnu-f1 UBOOT_IMAGE:=u-boot.ltq.lzo.nandspl diff --git a/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch b/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch index 3f77d98476..91d9099f12 100644 --- a/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch +++ b/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch @@ -1,7 +1,7 @@ From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001 From: Luka Perkov <luka@openwrt.org> Date: Tue, 6 Aug 2013 22:51:00 +0200 -Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx +Subject: MIPS: add board support for Zyxel P-2812HNU-Fx Signed-off-by: Luka Perkov <luka@openwrt.org> @@ -51,7 +51,7 @@ Signed-off-by: Luka Perkov <luka@openwrt.org> +/* + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> + * -+ * The values have been extracted from original ZyXEL U-Boot. ++ * The values have been extracted from original Zyxel U-Boot. + * + * SPDX-License-Identifier: GPL-2.0+ + */ @@ -243,7 +243,7 @@ Signed-off-by: Luka Perkov <luka@openwrt.org> + +#define CONFIG_MACH_TYPE "P-2812HNU-Fx" +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx" ++#define CONFIG_BOARD_NAME "Zyxel P-2812HNU-Fx" + +/* Configure SoC */ +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ diff --git a/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch index 39499fcebc..3f3424da6f 100644 --- a/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch +++ b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch @@ -95,7 +95,7 @@ +void show_boot_progress(int arg) +{ + if (!do_gpio_init) -+ return 0; ++ return; + + if (arg >= 0) { + /* Success - turn off the red power LED and turn on the green power LED */ @@ -107,7 +107,7 @@ + gpio_set_value(GPIO_POWER_RED, 0); + } + -+ return 0; ++ return; +} + +static const struct ltq_eth_port_config eth_port_config[] = { diff --git a/package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch b/package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch index fd709bc2ac..992236cded 100644 --- a/package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch +++ b/package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch @@ -107,7 +107,7 @@ +void show_boot_progress(int arg) +{ + if (!do_gpio_init) -+ return 0; ++ return; + + if (arg >= 0) { + /* Success - turn off the red power LED and turn on the green power LED */ @@ -119,7 +119,7 @@ + gpio_set_value(GPIO_POWER_RED, 0); + } + -+ return 0; ++ return; +} + +static const struct ltq_eth_port_config eth_port_config[] = { diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile index 722f4f30b7..ba0bd113da 100644 --- a/package/boot/uboot-layerscape/Makefile +++ b/package/boot/uboot-layerscape/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-layerscape -PKG_VERSION:=6.6.3.1.0.0 +PKG_VERSION:=6.6.23.2.0.0 PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL:=https://github.com/nxp-qoriq/u-boot -PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0 -PKG_MIRROR_HASH:=dec5b6e4fe328b930f201fbf06a0a7b71a9dd72f38f16c9570188c0a7fea916a +PKG_SOURCE_VERSION:=lf-6.6.23-2.0.0 +PKG_MIRROR_HASH:=41e089fde1d0b3b0998e6af33d5f4c2b62860bda6cd1e6a0e8d47dfd5749005d include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk diff --git a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch index fbd96c0fa9..c2a13e27f7 100644 --- a/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch +++ b/package/boot/uboot-layerscape/patches/0900-layerscape-adjust-LS1021A-IOT-config-for-OpenWrt.patch @@ -17,16 +17,16 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig -@@ -24,7 +24,7 @@ CONFIG_AHCI=y - CONFIG_LAYERSCAPE_NS_ACCESS=y - CONFIG_PCIE1=y - CONFIG_PCIE2=y +@@ -14,7 +14,7 @@ CONFIG_SYS_I2C_MXC_I2C3=y + CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart" + CONFIG_SPL_TEXT_BASE=0x10000000 -CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SYS_MONITOR_LEN=786432 - CONFIG_OF_BOARD_SETUP=y - CONFIG_OF_STDOUT_VIA_ALIAS=y - CONFIG_RAMBOOT_PBL=y -@@ -40,7 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000 + CONFIG_SPL_MMC=y + CONFIG_SPL_SERIAL=y + CONFIG_SPL_STACK=0x1001d000 +@@ -43,7 +43,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_PAD_TO=0x1c000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80100000 @@ -34,8 +34,8 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> +CONFIG_SPL_BSS_MAX_SIZE=0xc0000 CONFIG_SPL_FSL_PBL=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set - CONFIG_SYS_SPL_MALLOC=y -@@ -66,8 +66,11 @@ CONFIG_CMD_MII=y + CONFIG_SPL_SYS_MALLOC=y +@@ -67,8 +67,11 @@ CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 8827bcf8c2..a62ecb9c97 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,8 +1,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.01 -PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3 +PKG_VERSION:=2025.01 +PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host UBOOT_USE_INTREE_DTC:=1 @@ -219,6 +219,18 @@ define U-Boot/mt7629_rfb UBOOT_CONFIG:=mt7629_rfb endef +define U-Boot/mt7981_abt_asr3000 + NAME:=ABT ASR3000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=abt_asr3000 + UBOOT_CONFIG:=mt7981_abt_asr3000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + define U-Boot/mt7981_cmcc_rax3000m-emmc NAME:=CMCC RAX3000M BUILD_SUBTARGET:=filogic @@ -243,6 +255,30 @@ define U-Boot/mt7981_cmcc_rax3000m-nand DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr4 endef +define U-Boot/mt7981_glinet_gl-x3000 + NAME:=GL.iNet GL-X3000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=glinet_gl-x3000 + UBOOT_CONFIG:=mt7981_glinet_gl-x3000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr4 +endef + +define U-Boot/mt7981_glinet_gl-xe3000 + NAME:=GL.iNet GL-XE3000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=glinet_gl-xe3000 + UBOOT_CONFIG:=mt7981_glinet_gl-x3000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr4 +endef + define U-Boot/mt7981_h3c_magic-nx30-pro NAME:=H3C Magic NX30 Pro BUILD_SUBTARGET:=filogic @@ -328,13 +364,26 @@ define U-Boot/mt7981_rfb-emmc DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr3 endef +define U-Boot/mt7981_gatonetworks_gdsp + NAME:=GatoNetworks GDSP + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=gatonetworks_gdsp + UBOOT_CONFIG:=mt7981_gatonetworks_gdsp + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-nor-ddr3 + FIP_COMPRESS:=1 +endef + define U-Boot/mt7981_rfb-nor NAME:=MT7981 Reference Board BUILD_SUBTARGET:=filogic BUILD_DEVICES:=mediatek_mt7981-rfb UBOOT_CONFIG:=mt7981_nor_rfb UBOOT_IMAGE:=u-boot.fip - BL2_BOOTDEV:=spim-nand + BL2_BOOTDEV:=nor BL2_SOC:=mt7981 BL2_DDRTYPE:=ddr3 DEPENDS:=+trusted-firmware-a-mt7981-nor-ddr3 @@ -364,6 +413,18 @@ define U-Boot/mt7981_rfb-snfi DEPENDS:=+trusted-firmware-a-mt7981-snand-ddr3 endef +define U-Boot/mt7981_routerich_ax3000 + NAME:=Routerich AX3000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=routerich_ax3000-ubootmod + UBOOT_CONFIG:=mt7981_routerich_ax3000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + define U-Boot/mt7981_qihoo_360t7 NAME:=Qihoo 360T7 BUILD_SUBTARGET:=filogic @@ -509,6 +570,18 @@ define U-Boot/mt7986_jdcloud_re-cp-03 DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 endef +define U-Boot/mt7986_mercusys_mr90x-v1 + NAME:=MERCUSYS MR90X v1 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mercusys_mr90x-v1-ubi + UBOOT_CONFIG:=mt7986_mercusys_mr90x-v1 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-ubi + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr3 +endef + define U-Boot/mt7986_netcore_n60 NAME:=Netcore N60 BUILD_SUBTARGET:=filogic @@ -557,6 +630,18 @@ define U-Boot/mt7986_tplink_tl-xdr6088 DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr3 endef +define U-Boot/mt7986_tplink_tl-xtr8488 + NAME:=TP-LINK TL-XTR8488 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=tplink_tl-xtr8488 + UBOOT_CONFIG:=mt7986_tplink_tl-xtr8488 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4 +endef + define U-Boot/mt7986_xiaomi_redmi-router-ax6000 NAME:=Xiaomi Redmi AX6000 BUILD_SUBTARGET:=filogic @@ -581,6 +666,18 @@ define U-Boot/mt7986_zyxel_ex5601-t0 DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4 endef +define U-Boot/mt7988_arcadyan_mozart + NAME:=Arcadyan Mozart + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=arcadyan_mozart + UBOOT_CONFIG:=mt7988a_arcadyan_mozart + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb +endef + define U-Boot/mt7988_bananapi_bpi-r4-emmc NAME:=BananaPi BPi-R4 BUILD_SUBTARGET:=filogic @@ -662,7 +759,7 @@ define U-Boot/mt7988_rfb-spim-nand BL2_BOOTDEV:=spim-nand BL2_SOC:=mt7988 BL2_DDRTYPE:=comb - DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-comb + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-comb +trusted-firmware-a-mt7988-spim-nand-ubi-comb endef define U-Boot/mt7988_rfb-snand @@ -734,8 +831,12 @@ UBOOT_TARGETS := \ mt7628_rfb \ mt7628_ravpower_rp-wd009 \ mt7629_rfb \ + mt7981_abt_asr3000 \ mt7981_cmcc_rax3000m-emmc \ mt7981_cmcc_rax3000m-nand \ + mt7981_gatonetworks_gdsp \ + mt7981_glinet_gl-x3000 \ + mt7981_glinet_gl-xe3000 \ mt7981_h3c_magic-nx30-pro \ mt7981_jcg_q30-pro \ mt7981_nokia_ea0326gmp \ @@ -746,6 +847,7 @@ UBOOT_TARGETS := \ mt7981_rfb-nor \ mt7981_rfb-sd \ mt7981_rfb-snfi \ + mt7981_routerich_ax3000 \ mt7981_qihoo_360t7 \ mt7981_xiaomi_mi-router-ax3000t \ mt7981_xiaomi_mi-router-wr30u \ @@ -757,13 +859,16 @@ UBOOT_TARGETS := \ mt7986_bananapi_bpi-r3-mini-snand \ mt7986_glinet_gl-mt6000 \ mt7986_jdcloud_re-cp-03 \ + mt7986_mercusys_mr90x-v1 \ mt7986_netcore_n60 \ mt7986_tplink_tl-xdr4288 \ mt7986_tplink_tl-xdr6086 \ mt7986_tplink_tl-xdr6088 \ + mt7986_tplink_tl-xtr8488 \ mt7986_xiaomi_redmi-router-ax6000 \ mt7986_zyxel_ex5601-t0 \ mt7986_rfb \ + mt7988_arcadyan_mozart \ mt7988_bananapi_bpi-r4-emmc \ mt7988_bananapi_bpi-r4-sdmmc \ mt7988_bananapi_bpi-r4-snand \ @@ -776,6 +881,12 @@ UBOOT_TARGETS := \ mt7988_rfb-emmc \ mt7988_rfb-sd +UBOOT_CUSTOMIZE_CONFIG := \ + --disable TOOLS_KWBIMAGE \ + --disable TOOLS_LIBCRYPTO \ + --disable TOOLS_MKEFICAPSULE \ + --enable SERIAL_RX_BUFFER + ifdef CONFIG_TARGET_mediatek UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin) endif diff --git a/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch b/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch new file mode 100644 index 0000000000..387cf90477 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-01-clk-mediatek-mt7629-fix-parent-clock-of-some-top-clo.patch @@ -0,0 +1,45 @@ +From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:16 +0800 +Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top + clock muxes + +According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL +shares the same parent selection with CLK_TOP_IRRX_SEL, while the +present parent selection for CLK_TOP_F10M_REF_SEL is actually used +for CLK_TOP_SGMII_REF_1_SEL. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/clk/mediatek/clk-mt7629.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7629.c ++++ b/drivers/clk/mediatek/clk-mt7629.c +@@ -186,7 +186,7 @@ static const int pwm_parents[] = { + CLK_TOP_UNIVPLL2_D4 + }; + +-static const int f10m_ref_parents[] = { ++static const int sgmii_ref_1_parents[] = { + CLK_XTAL, + CLK_TOP_SGMIIPLL_D2 + }; +@@ -369,7 +369,7 @@ static const struct mtk_composite top_mu + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), +- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), ++ MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + +@@ -412,7 +412,7 @@ static const struct mtk_composite top_mu + + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), +- MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), ++ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), + }; + diff --git a/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch b/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch new file mode 100644 index 0000000000..c96490e408 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-02-arm-dts-mt7629-fix-sgmii-clock-selection-for-etherne.patch @@ -0,0 +1,28 @@ +From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:20 +0800 +Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for + ethernet + +Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow +sgmiisys1 work correctly. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7629.dtsi | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/arch/arm/dts/mt7629.dtsi ++++ b/arch/arm/dts/mt7629.dtsi +@@ -314,8 +314,10 @@ + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "sgmii_ck", "eth2pll"; + assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, +- <&topckgen CLK_TOP_F10M_REF_SEL>; ++ <&topckgen CLK_TOP_F10M_REF_SEL>, ++ <&topckgen CLK_TOP_SGMII_REF_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, ++ <&topckgen CLK_TOP_SYSPLL4_D16>, + <&topckgen CLK_TOP_SGMIIPLL_D2>; + power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; + resets = <ðsys ETHSYS_FE_RST>; diff --git a/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch b/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch new file mode 100644 index 0000000000..ba3fbf6d7f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-03-net-mediatek-use-correct-register-field-for-SGMII-sp.patch @@ -0,0 +1,64 @@ +From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:23 +0800 +Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII + speed selection + +The register field for SGMII speed selection is a 2-bit field with +value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved). +So it's necessary to set both bits instead of just setting/clearing +only the lower bit. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 12 ++++++------ + drivers/net/mtk_eth.h | 3 ++- + 2 files changed, 8 insertions(+), 7 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct + } + + /* Set SGMII GEN2 speed(2.5G) */ +- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), +- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); ++ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, ++ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); + + /* Disable SGMII AN */ + mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), +@@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice + static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) + { + /* Set SGMII GEN1 speed(1G) */ +- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, +- SGMSYS_SPEED_2500, 0); ++ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); + + /* Enable SGMII AN */ + setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, +@@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk + static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) + { + /* Set SGMII GEN2 speed(2.5G) */ +- setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, +- SGMSYS_SPEED_2500); ++ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, ++ SGMSYS_SPEED_MASK, ++ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); + + /* Disable SGMII AN */ + clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -108,7 +108,8 @@ enum mkt_eth_capabilities { + + #define SGMSYS_GEN2_SPEED 0x2028 + #define SGMSYS_GEN2_SPEED_V2 0x128 +-#define SGMSYS_SPEED_2500 BIT(2) ++#define SGMSYS_SPEED_MASK GENMASK(3, 2) ++#define SGMSYS_SPEED_2500 1 + + /* USXGMII subsystem config registers */ + /* Register to control USXGMII XFI PLL digital */ diff --git a/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch b/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch new file mode 100644 index 0000000000..8c549e76b1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-04-net-mediatek-correct-register-name-of-ethsys-syscfg1.patch @@ -0,0 +1,78 @@ +From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:27 +0800 +Subject: [PATCH 04/10] net: mediatek: correct register name of ethsys syscfg1 + +The SYSCFG0 should be SYSCFG1 according to the programming guide. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 14 +++++++------- + drivers/net/mtk_eth.h | 12 ++++++------ + 2 files changed, 13 insertions(+), 13 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_ + } + + ge_mode = GE_MODE_RGMII; +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, +- SYSCFG0_SGMII_SEL(priv->gmac_id)); ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, ++ SYSCFG1_SGMII_SEL(priv->gmac_id)); + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) + mtk_sgmii_an_init(priv); + else +@@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_ + } + + /* set the gmac to the right mode */ +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, +- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), +- ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, ++ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), ++ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); + + if (priv->force_mode) { + mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +@@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth + } + + /* Set GMAC to the correct mode */ +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, +- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, ++ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + 0); + + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -65,11 +65,11 @@ enum mkt_eth_capabilities { + + /* Ethernet subsystem registers */ + +-#define ETHSYS_SYSCFG0_REG 0x14 +-#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) +-#define SYSCFG0_GE_MODE_M 0x3 +-#define SYSCFG0_SGMII_SEL_M (0x3 << 8) +-#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) ++#define ETHSYS_SYSCFG1_REG 0x14 ++#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) ++#define SYSCFG1_GE_MODE_M 0x3 ++#define SYSCFG1_SGMII_SEL_M (0x3 << 8) ++#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) + + #define ETHSYS_CLKCFG0_REG 0x2c + #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) +@@ -84,7 +84,7 @@ enum mkt_eth_capabilities { + #define QPHY_SEL_MASK 0x3 + #define SGMII_QPHY_SEL 0x2 + +-/* SYSCFG0_GE_MODE: GE Modes */ ++/* SYSCFG1_GE_MODE: GE Modes */ + #define GE_MODE_RGMII 0 + #define GE_MODE_MII 1 + #define GE_MODE_MII_PHY 2 diff --git a/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch b/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch new file mode 100644 index 0000000000..a45e8789d2 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-05-net-mediatek-fix-sgmii-selection-for-mt7622.patch @@ -0,0 +1,90 @@ +From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:41 +0800 +Subject: [PATCH 05/10] net: mediatek: fix sgmii selection for mt7622 + +Unlike other platforms, mt7622 has only one SGMII and it can be +attached to either gmac1 or gmac2. So the register field of the +sgmii selection differs from other platforms as newer platforms can +control each sgmii individually. + +This patch adds a new capability for mt7622 to handle this case. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 10 ++++++++-- + drivers/net/mtk_eth.h | 8 ++++++-- + 2 files changed, 14 insertions(+), 4 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct m + + static void mtk_mac_init(struct mtk_eth_priv *priv) + { +- int i, ge_mode = 0; ++ int i, sgmii_sel_mask = 0, ge_mode = 0; + u32 mcr; + + switch (priv->phy_interface) { +@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_ + } + + ge_mode = GE_MODE_RGMII; +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) ++ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; ++ ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, + SYSCFG1_SGMII_SEL(priv->gmac_id)); ++ + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) + mtk_sgmii_an_init(priv); + else +@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_ + }; + + static const struct mtk_soc_data mt7622_data = { ++ .caps = MT7622_CAPS, + .ana_rgc3 = 0x2028, + .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -23,6 +23,7 @@ enum mkt_eth_capabilities { + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_TRGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, ++ MTK_ETH_PATH_MT7622_SGMII_BIT, + }; + + #define MTK_TRGMII BIT(MTK_TRGMII_BIT) +@@ -36,6 +37,7 @@ enum mkt_eth_capabilities { + #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) + + #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) + + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) + +@@ -45,6 +47,8 @@ enum mkt_eth_capabilities { + + #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) + ++#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) ++ + #define MT7623_CAPS (MTK_GMAC1_TRGMII) + + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) +@@ -68,8 +72,8 @@ enum mkt_eth_capabilities { + #define ETHSYS_SYSCFG1_REG 0x14 + #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) + #define SYSCFG1_GE_MODE_M 0x3 +-#define SYSCFG1_SGMII_SEL_M (0x3 << 8) +-#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) ++#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) ++#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) + + #define ETHSYS_CLKCFG0_REG 0x2c + #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) diff --git a/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch b/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch new file mode 100644 index 0000000000..5bc6e705d0 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-06-net-mediatek-fix-gmac2-usability-for-mt7629.patch @@ -0,0 +1,73 @@ +From d8d7e566545f836dd49611cafbf44eef56434e08 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:46 +0800 +Subject: [PATCH 06/10] net: mediatek: fix gmac2 usability for mt7629 + +MT7629 need extra setting for gmac2 to work. So additional +capability is added for mt7629 to handle this case. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 6 ++++++ + drivers/net/mtk_eth.h | 7 +++++++ + 2 files changed, 13 insertions(+) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1437,6 +1437,11 @@ static void mtk_mac_init(struct mtk_eth_ + int i, sgmii_sel_mask = 0, ge_mode = 0; + u32 mcr; + ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { ++ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, ++ INFRA_MISC2_BONDING_OPTION, priv->gmac_id); ++ } ++ + switch (priv->phy_interface) { + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII: +@@ -2101,6 +2106,7 @@ static const struct mtk_soc_data mt7981_ + }; + + static const struct mtk_soc_data mt7629_data = { ++ .caps = MT7629_CAPS, + .ana_rgc3 = 0x128, + .gdma_count = 2, + .pdma_base = PDMA_V1_BASE, +--- a/drivers/net/mtk_eth.h ++++ b/drivers/net/mtk_eth.h +@@ -24,6 +24,7 @@ enum mkt_eth_capabilities { + MTK_ETH_PATH_GMAC1_TRGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_MT7622_SGMII_BIT, ++ MTK_ETH_PATH_MT7629_GMAC2_BIT, + }; + + #define MTK_TRGMII BIT(MTK_TRGMII_BIT) +@@ -38,6 +39,7 @@ enum mkt_eth_capabilities { + + #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) + #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) ++#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) + + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) + +@@ -51,6 +53,8 @@ enum mkt_eth_capabilities { + + #define MT7623_CAPS (MTK_GMAC1_TRGMII) + ++#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) ++ + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) + + #define MT7986_CAPS (MTK_NETSYS_V2) +@@ -88,6 +92,9 @@ enum mkt_eth_capabilities { + #define QPHY_SEL_MASK 0x3 + #define SGMII_QPHY_SEL 0x2 + ++#define MT7629_INFRA_MISC2_REG 0x70c ++#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) ++ + /* SYSCFG1_GE_MODE: GE Modes */ + #define GE_MODE_RGMII 0 + #define GE_MODE_MII 1 diff --git a/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch b/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch new file mode 100644 index 0000000000..f7a63a5b8a --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-07-net-mediatek-add-support-for-10GBASE-R.patch @@ -0,0 +1,147 @@ +From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:50 +0800 +Subject: [PATCH 07/10] net: mediatek: add support for 10GBASE-R + +This patch adds support for 10GBASE-R interface mode + +Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 81 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_ + + if (!priv->force_mode) { + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) + mtk_xphy_link_adjust(priv); + else +@@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10 + udelay(400); + } + ++static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) ++{ ++ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); ++ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); ++ ndelay(1020); ++ ++ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); ++ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); ++ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); ++ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); ++ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); ++ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); ++ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); ++ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); ++ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); ++ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); ++ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); ++ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); ++ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); ++ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); ++ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); ++ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); ++ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); ++ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); ++ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); ++ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); ++ if (priv->gmac_id == 2) ++ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); ++ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); ++ udelay(150); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); ++ udelay(15); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); ++ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); ++ udelay(400); ++} ++ + static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) + { + mtk_xfi_pll_enable(priv); +@@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct m + mtk_usxgmii_setup_phya_an_10000(priv); + } + ++static void mtk_10gbaser_init(struct mtk_eth_priv *priv) ++{ ++ mtk_xfi_pll_enable(priv); ++ mtk_usxgmii_reset(priv); ++ mtk_usxgmii_setup_phya_force_10000(priv); ++} ++ + static void mtk_mac_init(struct mtk_eth_priv *priv) + { + int i, sgmii_sel_mask = 0, ge_mode = 0; +@@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth + case PHY_INTERFACE_MODE_USXGMII: + mtk_usxgmii_an_init(priv); + break; ++ case PHY_INTERFACE_MODE_10GBASER: ++ mtk_10gbaser_init(priv); ++ break; + default: + break; + } +@@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + 0); + +- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && ++ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && + priv->gmac_id == 1) { + mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, + NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); +@@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice + + /* Set MAC mode */ + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) + mtk_xmac_init(priv); + else +@@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct ude + /* Upstream linux use mediatek,pnswap instead of pn_swap */ + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || + ofnode_read_bool(args.node, "mediatek,pnswap"); +- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { ++ } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { + /* get corresponding usxgmii phandle */ + ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", + NULL, 0, 0, &args); diff --git a/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch b/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch new file mode 100644 index 0000000000..d6a885f889 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-08-net-mediatek-make-sgmii-usxgmii-optional.patch @@ -0,0 +1,144 @@ +From 5ac929fd1ab1d0dc77b9167952aea7cafdb8619f Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:55 +0800 +Subject: [PATCH 08/10] net: mediatek: make sgmii/usxgmii optional + +Not all platforms supports sgmii and/or usxgmii. So we add Kconfig +options for these features and enable them only for supported +platforms. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/Kconfig | 12 ++++++++++++ + drivers/net/mtk_eth.c | 39 +++++++++++++++++++++++++++++---------- + 2 files changed, 41 insertions(+), 10 deletions(-) + +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -975,6 +975,18 @@ config MEDIATEK_ETH + This Driver support MediaTek Ethernet GMAC + Say Y to enable support for the MediaTek Ethernet GMAC. + ++if MEDIATEK_ETH ++ ++config MTK_ETH_SGMII ++ bool ++ default y if ARCH_MEDIATEK && !TARGET_MT7623 ++ ++config MTK_ETH_XGMII ++ bool ++ default y if TARGET_MT7987 || TARGET_MT7988 ++ ++endif # MEDIATEK_ETH ++ + config HIFEMAC_ETH + bool "HiSilicon Fast Ethernet Controller" + select DM_CLK +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1505,7 +1505,7 @@ static void mtk_10gbaser_init(struct mtk + mtk_usxgmii_setup_phya_force_10000(priv); + } + +-static void mtk_mac_init(struct mtk_eth_priv *priv) ++static int mtk_mac_init(struct mtk_eth_priv *priv) + { + int i, sgmii_sel_mask = 0, ge_mode = 0; + u32 mcr; +@@ -1522,13 +1522,16 @@ static void mtk_mac_init(struct mtk_eth_ + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: ++ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { ++ printf("Error: SGMII is not supported on this platform\n"); ++ return -ENOTSUPP; ++ } ++ + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { + mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, + SGMII_QPHY_SEL); + } + +- ge_mode = GE_MODE_RGMII; +- + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; + +@@ -1539,6 +1542,8 @@ static void mtk_mac_init(struct mtk_eth_ + mtk_sgmii_an_init(priv); + else + mtk_sgmii_force_init(priv); ++ ++ ge_mode = GE_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: +@@ -1595,12 +1600,19 @@ static void mtk_mac_init(struct mtk_eth_ + RX_RST | RXC_DQSISEL); + mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); + } ++ ++ return 0; + } + +-static void mtk_xmac_init(struct mtk_eth_priv *priv) ++static int mtk_xmac_init(struct mtk_eth_priv *priv) + { + u32 force_link = 0; + ++ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { ++ printf("Error: 10Gb interface is not supported on this platform\n"); ++ return -ENOTSUPP; ++ } ++ + switch (priv->phy_interface) { + case PHY_INTERFACE_MODE_USXGMII: + mtk_usxgmii_an_init(priv); +@@ -1633,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth + + /* Force GMAC link down */ + mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); ++ ++ return 0; + } + + static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) +@@ -1922,9 +1936,12 @@ static int mtk_eth_probe(struct udevice + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) +- mtk_xmac_init(priv); ++ ret = mtk_xmac_init(priv); + else +- mtk_mac_init(priv); ++ ret = mtk_mac_init(priv); ++ ++ if (ret) ++ return ret; + + /* Probe phy if switch is not specified */ + if (priv->sw == SW_NONE) +@@ -2032,8 +2049,9 @@ static int mtk_eth_of_to_plat(struct ude + } + } + +- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { ++ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && ++ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { + /* get corresponding sgmii phandle */ + ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", + NULL, 0, 0, &args); +@@ -2055,8 +2073,9 @@ static int mtk_eth_of_to_plat(struct ude + /* Upstream linux use mediatek,pnswap instead of pn_swap */ + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || + ofnode_read_bool(args.node, "mediatek,pnswap"); +- } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { ++ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && ++ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { + /* get corresponding usxgmii phandle */ + ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", + NULL, 0, 0, &args); diff --git a/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch b/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch new file mode 100644 index 0000000000..c9ea8f4401 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-09-net-mediatek-don-t-enable-GDMA-cpu-bridge-unconditio.patch @@ -0,0 +1,36 @@ +From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:39:59 +0800 +Subject: [PATCH 09/10] net: mediatek: don't enable GDMA cpu bridge + unconditionally for NETSYSv3 + +Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other +than GMAC0, or when MT7988 internal switch is used. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice + if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { + mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, + GDMA_BRIDGE_TO_CPU); +- } + +- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, +- GDMA_CPU_BRIDGE_EN); ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, ++ GDMA_CPU_BRIDGE_EN); ++ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || ++ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && ++ priv->gmac_id != 0) { ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, ++ GDMA_CPU_BRIDGE_EN); ++ } + } + + udelay(500); diff --git a/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch b/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch new file mode 100644 index 0000000000..a20d79030f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/060-10-net-mediatek-fix-usability-with-wget-command.patch @@ -0,0 +1,37 @@ +From c949686e558e00cbb8c38f7c060701006d70cea8 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 17 Dec 2024 16:40:03 +0800 +Subject: [PATCH 10/10] net: mediatek: fix usability with wget command + +The wget command currently cannot work correctly with mtk_eth driver. +This patch fixed this by increase DMA ring size and invalidate ring data +after use. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth.c ++++ b/drivers/net/mtk_eth.c +@@ -29,8 +29,8 @@ + + #include "mtk_eth.h" + +-#define NUM_TX_DESC 24 +-#define NUM_RX_DESC 24 ++#define NUM_TX_DESC 32 ++#define NUM_RX_DESC 32 + #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) + #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) + #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) +@@ -1897,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevi + + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + ++ invalidate_dcache_range((ulong)rxd->rxd1, ++ (ulong)rxd->rxd1 + PKTSIZE_ALIGN); ++ + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) + rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); diff --git a/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch b/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch new file mode 100644 index 0000000000..b212c6c219 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/061-01-net-mediatek-split-ethernet-switch-code-from-mtk_eth.patch @@ -0,0 +1,6311 @@ +From 626cdca5b68acdc72d2533e2ed2306c06f296725 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 10 Jan 2025 16:41:13 +0800 +Subject: [PATCH 1/3] net: mediatek: split ethernet switch code from mtk_eth.c + +mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also +some ethernet switch initialization code. As we may add more switch +support in the future, it's better to move them out of mtk_eth.c to +avoid increasing the code complexity. + +Since not all switches are supported for a particular board, Kconfig +options are added to allow user to select which switch should be +built into u-boot. If multiple switches are selected, auto-detecting +can also be enabled. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/Kconfig | 21 +- + drivers/net/Makefile | 2 +- + drivers/net/mtk_eth/Kconfig | 35 + + drivers/net/mtk_eth/Makefile | 9 + + drivers/net/mtk_eth/mt7530.c | 281 ++++++++ + drivers/net/mtk_eth/mt7531.c | 293 +++++++++ + drivers/net/mtk_eth/mt753x.c | 262 ++++++++ + drivers/net/mtk_eth/mt753x.h | 286 ++++++++ + drivers/net/mtk_eth/mt7988.c | 160 +++++ + drivers/net/{ => mtk_eth}/mtk_eth.c | 971 ++++------------------------ + drivers/net/{ => mtk_eth}/mtk_eth.h | 301 ++------- + 11 files changed, 1520 insertions(+), 1101 deletions(-) + create mode 100644 drivers/net/mtk_eth/Kconfig + create mode 100644 drivers/net/mtk_eth/Makefile + create mode 100644 drivers/net/mtk_eth/mt7530.c + create mode 100644 drivers/net/mtk_eth/mt7531.c + create mode 100644 drivers/net/mtk_eth/mt753x.c + create mode 100644 drivers/net/mtk_eth/mt753x.h + create mode 100644 drivers/net/mtk_eth/mt7988.c + rename drivers/net/{ => mtk_eth}/mtk_eth.c (62%) + rename drivers/net/{ => mtk_eth}/mtk_eth.h (59%) + +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -966,26 +966,7 @@ config TSEC_ENET + This driver implements support for the (Enhanced) Three-Speed + Ethernet Controller found on Freescale SoCs. + +-config MEDIATEK_ETH +- bool "MediaTek Ethernet GMAC Driver" +- select PHYLIB +- select DM_GPIO +- select DM_RESET +- help +- This Driver support MediaTek Ethernet GMAC +- Say Y to enable support for the MediaTek Ethernet GMAC. +- +-if MEDIATEK_ETH +- +-config MTK_ETH_SGMII +- bool +- default y if ARCH_MEDIATEK && !TARGET_MT7623 +- +-config MTK_ETH_XGMII +- bool +- default y if TARGET_MT7987 || TARGET_MT7988 +- +-endif # MEDIATEK_ETH ++source "drivers/net/mtk_eth/Kconfig" + + config HIFEMAC_ETH + bool "HiSilicon Fast Ethernet Controller" +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -67,7 +67,7 @@ obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio + obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o + obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o + obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o +-obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o ++obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth/ + obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o + obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o + obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o +--- /dev/null ++++ b/drivers/net/mtk_eth/Kconfig +@@ -0,0 +1,35 @@ ++ ++config MEDIATEK_ETH ++ bool "MediaTek Ethernet GMAC Driver" ++ select PHYLIB ++ select DM_GPIO ++ select DM_RESET ++ help ++ This Driver support MediaTek Ethernet GMAC ++ Say Y to enable support for the MediaTek Ethernet GMAC. ++ ++if MEDIATEK_ETH ++ ++config MTK_ETH_SGMII ++ bool ++ default y if ARCH_MEDIATEK && !TARGET_MT7623 ++ ++config MTK_ETH_XGMII ++ bool ++ default y if TARGET_MT7988 ++ ++config MTK_ETH_SWITCH_MT7530 ++ bool "Support for MediaTek MT7530 ethernet switch" ++ default y if TARGET_MT7623 || SOC_MT7621 ++ ++config MTK_ETH_SWITCH_MT7531 ++ bool "Support for MediaTek MT7531 ethernet switch" ++ default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ ++ TARGET_MT7986 ++ ++config MTK_ETH_SWITCH_MT7988 ++ bool "Support for MediaTek MT7988 built-in ethernet switch" ++ depends on TARGET_MT7988 ++ default y ++ ++endif # MEDIATEK_ETH +--- /dev/null ++++ b/drivers/net/mtk_eth/Makefile +@@ -0,0 +1,9 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2025 MediaTek Inc. ++# Author: Weijie Gao <weijie.gao@mediatek.com> ++ ++obj-y += mtk_eth.o ++obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o ++obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o ++obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o +--- /dev/null ++++ b/drivers/net/mtk_eth/mt7530.c +@@ -0,0 +1,281 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#include <miiphy.h> ++#include <linux/delay.h> ++#include <linux/mdio.h> ++#include <linux/mii.h> ++#include "mtk_eth.h" ++#include "mt753x.h" ++ ++#define CHIP_REV 0x7ffc ++#define CHIP_NAME_S 16 ++#define CHIP_NAME_M 0xffff0000 ++#define CHIP_REV_S 0 ++#define CHIP_REV_M 0x0f ++ ++static void mt7530_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, ++ u32 val) ++{ ++ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); ++ ++ mtk_mmd_ind_write(priv->epriv.eth, phy_addr, 0x1f, reg, val); ++} ++ ++static int mt7530_pad_clk_setup(struct mt753x_switch_priv *priv, int mode) ++{ ++ u32 ncpo1, ssc_delta; ++ ++ switch (mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ ncpo1 = 0x0c80; ++ ssc_delta = 0x87; ++ break; ++ ++ default: ++ printf("error: xMII mode %d is not supported\n", mode); ++ return -EINVAL; ++ } ++ ++ /* Disable MT7530 core clock */ ++ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); ++ ++ /* Disable MT7530 PLL */ ++ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, ++ (2 << RG_GSWPLL_POSDIV_200M_S) | ++ (32 << RG_GSWPLL_FBKDIV_200M_S)); ++ ++ /* For MT7530 core clock = 500Mhz */ ++ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2, ++ (1 << RG_GSWPLL_POSDIV_500M_S) | ++ (25 << RG_GSWPLL_FBKDIV_500M_S)); ++ ++ /* Enable MT7530 PLL */ ++ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, ++ (2 << RG_GSWPLL_POSDIV_200M_S) | ++ (32 << RG_GSWPLL_FBKDIV_200M_S) | ++ RG_GSWPLL_EN_PRE); ++ ++ udelay(20); ++ ++ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); ++ ++ /* Setup the MT7530 TRGMII Tx Clock */ ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0); ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | ++ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); ++ ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP2, ++ RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | ++ (1 << RG_SYSPLL_POSDIV_S)); ++ ++ mt7530_core_reg_write(priv, CORE_PLL_GROUP7, ++ RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | ++ RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); ++ ++ /* Enable MT7530 core clock */ ++ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, ++ REG_GSWCK_EN | REG_TRGMIICK_EN); ++ ++ return 0; ++} ++ ++static void mt7530_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u32 pmcr = FORCE_MODE; ++ ++ if (enable) ++ pmcr = priv->pmcr; ++ ++ mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ ++static int mt7530_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) ++{ ++ struct mt753x_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_read(priv->epriv.eth, addr, reg); ++ ++ return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); ++} ++ ++static int mt7530_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, ++ u16 val) ++{ ++ struct mt753x_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_write(priv->epriv.eth, addr, reg, val); ++ ++ return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); ++} ++ ++static int mt7530_mdio_register(struct mt753x_switch_priv *priv) ++{ ++ struct mii_dev *mdio_bus = mdio_alloc(); ++ int ret; ++ ++ if (!mdio_bus) ++ return -ENOMEM; ++ ++ mdio_bus->read = mt7530_mdio_read; ++ mdio_bus->write = mt7530_mdio_write; ++ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); ++ ++ mdio_bus->priv = priv; ++ ++ ret = mdio_register(mdio_bus); ++ if (ret) { ++ mdio_free(mdio_bus); ++ return ret; ++ } ++ ++ priv->mdio_bus = mdio_bus; ++ ++ return 0; ++} ++ ++static int mt7530_setup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u16 phy_addr, phy_val; ++ u32 i, val, txdrv; ++ ++ priv->smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->reg_read = mt753x_mdio_reg_read; ++ priv->reg_write = mt753x_mdio_reg_write; ++ ++ if (!MTK_HAS_CAPS(priv->epriv.soc->caps, MTK_TRGMII_MT7621_CLK)) { ++ /* Select 250MHz clk for RGMII mode */ ++ mtk_ethsys_rmw(priv->epriv.eth, ETHSYS_CLKCFG0_REG, ++ ETHSYS_TRGMII_CLK_SEL362_5, 0); ++ ++ txdrv = 8; ++ } else { ++ txdrv = 4; ++ } ++ ++ /* Modify HWTRAP first to allow direct access to internal PHYs */ ++ mt753x_reg_read(priv, HWTRAP_REG, &val); ++ val |= CHG_TRAP; ++ val &= ~C_MDIO_BPS; ++ mt753x_reg_write(priv, MHWTRAP_REG, val); ++ ++ /* Calculate the phy base address */ ++ val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; ++ priv->phy_base = (val | 0x7) + 1; ++ ++ /* Turn off PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); ++ phy_val |= BMCR_PDOWN; ++ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ /* Force MAC link down before reset */ ++ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); ++ ++ /* MT7530 reset */ ++ mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); ++ udelay(100); ++ ++ val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ MAC_MODE | FORCE_MODE | ++ MAC_TX_EN | MAC_RX_EN | ++ BKOFF_EN | BACKPR_EN | ++ (SPEED_1000M << FORCE_SPD_S) | ++ FORCE_DPX | FORCE_LINK; ++ ++ /* MT7530 Port6: Forced 1000M/FD, FC disabled */ ++ priv->pmcr = val; ++ ++ /* MT7530 Port5: Forced link down */ ++ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); ++ ++ /* Keep MAC link down before starting eth */ ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); ++ ++ /* MT7530 Port6: Set to RGMII */ ++ mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); ++ ++ /* Hardware Trap: Enable Port6, Disable Port5 */ ++ mt753x_reg_read(priv, HWTRAP_REG, &val); ++ val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | ++ (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | ++ (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); ++ val &= ~(C_MDIO_BPS | P6_INTF_DIS); ++ mt753x_reg_write(priv, MHWTRAP_REG, val); ++ ++ /* Setup switch core pll */ ++ mt7530_pad_clk_setup(priv, priv->epriv.phy_interface); ++ ++ /* Lower Tx Driving for TRGMII path */ ++ for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) ++ mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), ++ (txdrv << TD_DM_DRVP_S) | ++ (txdrv << TD_DM_DRVN_S)); ++ ++ for (i = 0 ; i < NUM_TRGMII_CTRL; i++) ++ mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); ++ ++ /* Enable port isolation to block inter-port communication */ ++ mt753x_port_isolation(priv); ++ ++ /* Turn on PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); ++ phy_val &= ~BMCR_PDOWN; ++ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ return mt7530_mdio_register(priv); ++} ++ ++static int mt7530_cleanup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ ++ mdio_unregister(priv->mdio_bus); ++ ++ return 0; ++} ++ ++static int mt7530_detect(struct mtk_eth_priv *priv) ++{ ++ int ret; ++ u32 rev; ++ ++ ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); ++ if (ret) ++ return ret; ++ ++ if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7530) ++ return 0; ++ ++ return -ENODEV; ++} ++ ++MTK_ETH_SWITCH(mt7530) = { ++ .name = "mt7530", ++ .desc = "MediaTek MT7530", ++ .priv_size = sizeof(struct mt753x_switch_priv), ++ .reset_wait_time = 1000, ++ ++ .detect = mt7530_detect, ++ .setup = mt7530_setup, ++ .cleanup = mt7530_cleanup, ++ .mac_control = mt7530_mac_control, ++}; +--- /dev/null ++++ b/drivers/net/mtk_eth/mt7531.c +@@ -0,0 +1,293 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#include <miiphy.h> ++#include <linux/delay.h> ++#include <linux/mdio.h> ++#include <linux/mii.h> ++#include "mtk_eth.h" ++#include "mt753x.h" ++ ++#define CHIP_REV 0x781C ++#define CHIP_NAME_S 16 ++#define CHIP_NAME_M 0xffff0000 ++#define CHIP_REV_S 0 ++#define CHIP_REV_M 0x0f ++#define CHIP_REV_E1 0x0 ++ ++static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg) ++{ ++ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); ++ ++ return mt7531_mmd_read(priv, phy_addr, 0x1f, reg); ++} ++ ++static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg, ++ u32 val) ++{ ++ u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); ++ ++ mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val); ++} ++ ++static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv) ++{ ++ /* Step 1 : Disable MT7531 COREPLL */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); ++ ++ /* Step 2: switch to XTAL output */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); ++ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); ++ ++ /* Step 3: disable PLLGP and enable program PLLGP */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); ++ ++ /* Step 4: program COREPLL output frequency to 500MHz */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, ++ 2 << RG_COREPLL_POSDIV_S); ++ udelay(25); ++ ++ /* Currently, support XTAL 25Mhz only */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, ++ 0x140000 << RG_COREPLL_SDM_PCW_S); ++ ++ /* Set feedback divide ratio update signal to high */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, ++ RG_COREPLL_SDM_PCW_CHG); ++ ++ /* Wait for at least 16 XTAL clocks */ ++ udelay(10); ++ ++ /* Step 5: set feedback divide ratio update signal to low */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); ++ ++ /* add enable 325M clock for SGMII */ ++ mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); ++ ++ /* add enable 250SSC clock for RGMII */ ++ mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); ++ ++ /*Step 6: Enable MT7531 PLL */ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); ++ ++ mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); ++ ++ udelay(25); ++} ++ ++static int mt7531_port_sgmii_init(struct mt753x_switch_priv *priv, u32 port) ++{ ++ if (port != 5 && port != 6) { ++ printf("mt7531: port %d is not a SGMII port\n", port); ++ return -EINVAL; ++ } ++ ++ /* Set SGMII GEN2 speed(2.5G) */ ++ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, ++ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); ++ ++ /* Disable SGMII AN */ ++ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), ++ SGMII_AN_ENABLE, 0); ++ ++ /* SGMII force mode setting */ ++ mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); ++ ++ /* Release PHYA power down state */ ++ mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), ++ SGMII_PHYA_PWD, 0); ++ ++ return 0; ++} ++ ++static int mt7531_port_rgmii_init(struct mt753x_switch_priv *priv, u32 port) ++{ ++ u32 val; ++ ++ if (port != 5) { ++ printf("error: RGMII mode is not available for port %d\n", ++ port); ++ return -EINVAL; ++ } ++ ++ mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); ++ val |= GP_CLK_EN; ++ val &= ~GP_MODE_M; ++ val |= GP_MODE_RGMII << GP_MODE_S; ++ val |= TXCLK_NO_REVERSE; ++ val |= RXCLK_NO_DELAY; ++ val &= ~CLK_SKEW_IN_M; ++ val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; ++ val &= ~CLK_SKEW_OUT_M; ++ val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; ++ mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); ++ ++ return 0; ++} ++ ++static void mt7531_phy_setting(struct mt753x_switch_priv *priv) ++{ ++ int i; ++ u32 val; ++ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ /* Enable HW auto downshift */ ++ mt7531_mii_write(priv, i, 0x1f, 0x1); ++ val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); ++ val |= PHY_EN_DOWN_SHFIT; ++ mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); ++ ++ /* PHY link down power saving enable */ ++ val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); ++ val |= PHY_LINKDOWN_POWER_SAVING_EN; ++ mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); ++ ++ val = mt7531_mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); ++ val &= ~PHY_POWER_SAVING_M; ++ val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; ++ mt7531_mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); ++ } ++} ++ ++static void mt7531_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u32 pmcr = FORCE_MODE_LNK; ++ ++ if (enable) ++ pmcr = priv->pmcr; ++ ++ mt753x_reg_write(priv, PMCR_REG(5), pmcr); ++ mt753x_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ ++static int mt7531_setup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u32 i, val, pmcr, port5_sgmii; ++ u16 phy_addr, phy_val; ++ ++ priv->smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; ++ priv->reg_read = mt753x_mdio_reg_read; ++ priv->reg_write = mt753x_mdio_reg_write; ++ ++ /* Turn off PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); ++ phy_val |= BMCR_PDOWN; ++ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ /* Force MAC link down before reset */ ++ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); ++ ++ /* Switch soft reset */ ++ mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); ++ udelay(100); ++ ++ /* Enable MDC input Schmitt Trigger */ ++ mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, ++ SMT_IOLB_5_SMI_MDC_EN); ++ ++ mt7531_core_pll_setup(priv); ++ ++ mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); ++ port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); ++ ++ /* port5 support either RGMII or SGMII, port6 only support SGMII. */ ++ switch (priv->epriv.phy_interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ if (!port5_sgmii) ++ mt7531_port_rgmii_init(priv, 5); ++ break; ++ ++ case PHY_INTERFACE_MODE_2500BASEX: ++ mt7531_port_sgmii_init(priv, 6); ++ if (port5_sgmii) ++ mt7531_port_sgmii_init(priv, 5); ++ break; ++ ++ default: ++ break; ++ } ++ ++ pmcr = MT7531_FORCE_MODE | ++ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ MAC_MODE | MAC_TX_EN | MAC_RX_EN | ++ BKOFF_EN | BACKPR_EN | ++ FORCE_RX_FC | FORCE_TX_FC | ++ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | ++ FORCE_LINK; ++ ++ priv->pmcr = pmcr; ++ ++ /* Keep MAC link down before starting eth */ ++ mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); ++ mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); ++ ++ /* Enable port isolation to block inter-port communication */ ++ mt753x_port_isolation(priv); ++ ++ /* Turn on PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); ++ phy_val &= ~BMCR_PDOWN; ++ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ mt7531_phy_setting(priv); ++ ++ /* Enable Internal PHYs */ ++ val = mt7531_core_reg_read(priv, CORE_PLL_GROUP4); ++ val |= MT7531_BYPASS_MODE; ++ val &= ~MT7531_POWER_ON_OFF; ++ mt7531_core_reg_write(priv, CORE_PLL_GROUP4, val); ++ ++ return mt7531_mdio_register(priv); ++} ++ ++static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ ++ mdio_unregister(priv->mdio_bus); ++ ++ return 0; ++} ++ ++static int mt7531_detect(struct mtk_eth_priv *priv) ++{ ++ int ret; ++ u32 rev; ++ ++ ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev); ++ if (ret) ++ return ret; ++ ++ if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7531) ++ return 0; ++ ++ return -ENODEV; ++} ++ ++MTK_ETH_SWITCH(mt7531) = { ++ .name = "mt7531", ++ .desc = "MediaTek MT7531", ++ .priv_size = sizeof(struct mt753x_switch_priv), ++ .reset_wait_time = 200, ++ ++ .detect = mt7531_detect, ++ .setup = mt7531_setup, ++ .cleanup = mt7531_cleanup, ++ .mac_control = mt7531_mac_control, ++}; +--- /dev/null ++++ b/drivers/net/mtk_eth/mt753x.c +@@ -0,0 +1,262 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#include <errno.h> ++#include <time.h> ++#include "mtk_eth.h" ++#include "mt753x.h" ++ ++/* ++ * MT753x Internal Register Address Bits ++ * ------------------------------------------------------------------- ++ * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | ++ * |----------------------------------------|---------------|--------| ++ * | Page Address | Reg Address | Unused | ++ * ------------------------------------------------------------------- ++ */ ++ ++int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, ++ u32 *data) ++{ ++ int ret, low_word, high_word; ++ ++ /* Write page address */ ++ ret = mtk_mii_write(priv, smi_addr, 0x1f, reg >> 6); ++ if (ret) ++ return ret; ++ ++ /* Read low word */ ++ low_word = mtk_mii_read(priv, smi_addr, (reg >> 2) & 0xf); ++ if (low_word < 0) ++ return low_word; ++ ++ /* Read high word */ ++ high_word = mtk_mii_read(priv, smi_addr, 0x10); ++ if (high_word < 0) ++ return high_word; ++ ++ if (data) ++ *data = ((u32)high_word << 16) | (low_word & 0xffff); ++ ++ return 0; ++} ++ ++int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) ++{ ++ return __mt753x_mdio_reg_read(priv->epriv.eth, priv->smi_addr, reg, ++ data); ++} ++ ++int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) ++{ ++ int ret; ++ ++ /* Write page address */ ++ ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x1f, reg >> 6); ++ if (ret) ++ return ret; ++ ++ /* Write low word */ ++ ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, (reg >> 2) & 0xf, ++ data & 0xffff); ++ if (ret) ++ return ret; ++ ++ /* Write high word */ ++ return mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x10, data >> 16); ++} ++ ++int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) ++{ ++ return priv->reg_read(priv, reg, data); ++} ++ ++int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) ++{ ++ return priv->reg_write(priv, reg, data); ++} ++ ++void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set) ++{ ++ u32 val; ++ ++ priv->reg_read(priv, reg, &val); ++ val &= ~clr; ++ val |= set; ++ priv->reg_write(priv, reg, val); ++} ++ ++/* Indirect MDIO clause 22/45 access */ ++static int mt7531_mii_rw(struct mt753x_switch_priv *priv, int phy, int reg, ++ u16 data, u32 cmd, u32 st) ++{ ++ u32 val, timeout_ms; ++ ulong timeout; ++ int ret = 0; ++ ++ val = (st << MDIO_ST_S) | ++ ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | ++ ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | ++ ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); ++ ++ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) ++ val |= data & MDIO_RW_DATA_M; ++ ++ mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); ++ ++ timeout_ms = 100; ++ timeout = get_timer(0); ++ while (1) { ++ mt753x_reg_read(priv, MT7531_PHY_IAC, &val); ++ ++ if ((val & PHY_ACS_ST) == 0) ++ break; ++ ++ if (get_timer(timeout) > timeout_ms) ++ return -ETIMEDOUT; ++ } ++ ++ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { ++ mt753x_reg_read(priv, MT7531_PHY_IAC, &val); ++ ret = val & MDIO_RW_DATA_M; ++ } ++ ++ return ret; ++} ++ ++int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg) ++{ ++ u8 phy_addr; ++ ++ if (phy >= MT753X_NUM_PHYS) ++ return -EINVAL; ++ ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); ++ ++ return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, ++ MDIO_ST_C22); ++} ++ ++int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val) ++{ ++ u8 phy_addr; ++ ++ if (phy >= MT753X_NUM_PHYS) ++ return -EINVAL; ++ ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); ++ ++ return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, ++ MDIO_ST_C22); ++} ++ ++int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, ++ u16 reg) ++{ ++ u8 phy_addr; ++ int ret; ++ ++ if (addr >= MT753X_NUM_PHYS) ++ return -EINVAL; ++ ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); ++ ++ ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, ++ MDIO_ST_C45); ++ if (ret) ++ return ret; ++ ++ return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, ++ MDIO_ST_C45); ++} ++ ++int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, ++ u16 reg, u16 val) ++{ ++ u8 phy_addr; ++ int ret; ++ ++ if (addr >= MT753X_NUM_PHYS) ++ return 0; ++ ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); ++ ++ ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, ++ MDIO_ST_C45); ++ if (ret) ++ return ret; ++ ++ return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, ++ MDIO_ST_C45); ++} ++ ++static int mt7531_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) ++{ ++ struct mt753x_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mt7531_mii_read(priv, addr, reg); ++ ++ return mt7531_mmd_read(priv, addr, devad, reg); ++} ++ ++static int mt7531_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, ++ u16 val) ++{ ++ struct mt753x_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mt7531_mii_write(priv, addr, reg, val); ++ ++ return mt7531_mmd_write(priv, addr, devad, reg, val); ++} ++ ++int mt7531_mdio_register(struct mt753x_switch_priv *priv) ++{ ++ struct mii_dev *mdio_bus = mdio_alloc(); ++ int ret; ++ ++ if (!mdio_bus) ++ return -ENOMEM; ++ ++ mdio_bus->read = mt7531_mdio_read; ++ mdio_bus->write = mt7531_mdio_write; ++ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); ++ ++ mdio_bus->priv = priv; ++ ++ ret = mdio_register(mdio_bus); ++ if (ret) { ++ mdio_free(mdio_bus); ++ return ret; ++ } ++ ++ priv->mdio_bus = mdio_bus; ++ ++ return 0; ++} ++ ++void mt753x_port_isolation(struct mt753x_switch_priv *priv) ++{ ++ u32 i; ++ ++ for (i = 0; i < MT753X_NUM_PORTS; i++) { ++ /* Set port matrix mode */ ++ if (i != 6) ++ mt753x_reg_write(priv, PCR_REG(i), ++ (0x40 << PORT_MATRIX_S)); ++ else ++ mt753x_reg_write(priv, PCR_REG(i), ++ (0x3f << PORT_MATRIX_S)); ++ ++ /* Set port mode to user port */ ++ mt753x_reg_write(priv, PVC_REG(i), ++ (0x8100 << STAG_VPID_S) | ++ (VLAN_ATTR_USER << VLAN_ATTR_S)); ++ } ++} +--- /dev/null ++++ b/drivers/net/mtk_eth/mt753x.h +@@ -0,0 +1,286 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#ifndef _MTK_ETH_MT753X_H_ ++#define _MTK_ETH_MT753X_H_ ++ ++#include <phy.h> ++#include <miiphy.h> ++#include <linux/bitops.h> ++#include <linux/bitfield.h> ++ ++struct mtk_eth_priv; ++ ++#define MT753X_NUM_PHYS 5 ++#define MT753X_NUM_PORTS 7 ++#define MT753X_DFL_SMI_ADDR 31 ++#define MT753X_SMI_ADDR_MASK 0x1f ++ ++#define MT753X_PHY_ADDR(base, addr) \ ++ (((base) + (addr)) & 0x1f) ++ ++/* MT7530 Registers */ ++#define PCR_REG(p) (0x2004 + (p) * 0x100) ++#define PORT_MATRIX_S 16 ++#define PORT_MATRIX_M 0xff0000 ++ ++#define PVC_REG(p) (0x2010 + (p) * 0x100) ++#define STAG_VPID_S 16 ++#define STAG_VPID_M 0xffff0000 ++#define VLAN_ATTR_S 6 ++#define VLAN_ATTR_M 0xc0 ++ ++/* VLAN_ATTR: VLAN attributes */ ++#define VLAN_ATTR_USER 0 ++#define VLAN_ATTR_STACK 1 ++#define VLAN_ATTR_TRANSLATION 2 ++#define VLAN_ATTR_TRANSPARENT 3 ++ ++#define PMCR_REG(p) (0x3000 + (p) * 0x100) ++/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR ++ * MT7531 specific fields are defined below ++ */ ++#define FORCE_MODE_EEE1G BIT(25) ++#define FORCE_MODE_EEE100 BIT(26) ++#define FORCE_MODE_TX_FC BIT(27) ++#define FORCE_MODE_RX_FC BIT(28) ++#define FORCE_MODE_DPX BIT(29) ++#define FORCE_MODE_SPD BIT(30) ++#define FORCE_MODE_LNK BIT(31) ++#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ ++ FORCE_MODE_DPX | FORCE_MODE_SPD | \ ++ FORCE_MODE_LNK ++#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ ++ FORCE_MODE_DPX | FORCE_MODE_SPD | \ ++ FORCE_MODE_LNK ++ ++/* MT7531 SGMII Registers */ ++#define MT7531_SGMII_REG_BASE 0x5000 ++#define MT7531_SGMII_REG_PORT_BASE 0x1000 ++#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ ++ (p) * MT7531_SGMII_REG_PORT_BASE + (r)) ++#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) ++#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) ++#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) ++#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) ++#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158) ++/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ ++ ++/* MT753x System Control Register */ ++#define SYS_CTRL_REG 0x7000 ++#define SW_PHY_RST BIT(2) ++#define SW_SYS_RST BIT(1) ++#define SW_REG_RST BIT(0) ++ ++/* MT7531 */ ++#define MT7531_PHY_IAC 0x701c ++/* XXX: all fields are defined under GMAC_PIAC_REG */ ++ ++#define MT7531_CLKGEN_CTRL 0x7500 ++#define CLK_SKEW_OUT_S 8 ++#define CLK_SKEW_OUT_M 0x300 ++#define CLK_SKEW_IN_S 6 ++#define CLK_SKEW_IN_M 0xc0 ++#define RXCLK_NO_DELAY BIT(5) ++#define TXCLK_NO_REVERSE BIT(4) ++#define GP_MODE_S 1 ++#define GP_MODE_M 0x06 ++#define GP_CLK_EN BIT(0) ++ ++/* Values of GP_MODE */ ++#define GP_MODE_RGMII 0 ++#define GP_MODE_MII 1 ++#define GP_MODE_REV_MII 2 ++ ++/* Values of CLK_SKEW_IN */ ++#define CLK_SKEW_IN_NO_CHANGE 0 ++#define CLK_SKEW_IN_DELAY_100PPS 1 ++#define CLK_SKEW_IN_DELAY_200PPS 2 ++#define CLK_SKEW_IN_REVERSE 3 ++ ++/* Values of CLK_SKEW_OUT */ ++#define CLK_SKEW_OUT_NO_CHANGE 0 ++#define CLK_SKEW_OUT_DELAY_100PPS 1 ++#define CLK_SKEW_OUT_DELAY_200PPS 2 ++#define CLK_SKEW_OUT_REVERSE 3 ++ ++#define HWTRAP_REG 0x7800 ++/* MT7530 Modified Hardware Trap Status Registers */ ++#define MHWTRAP_REG 0x7804 ++#define CHG_TRAP BIT(16) ++#define LOOPDET_DIS BIT(14) ++#define P5_INTF_SEL_S 13 ++#define P5_INTF_SEL_M 0x2000 ++#define SMI_ADDR_S 11 ++#define SMI_ADDR_M 0x1800 ++#define XTAL_FSEL_S 9 ++#define XTAL_FSEL_M 0x600 ++#define P6_INTF_DIS BIT(8) ++#define P5_INTF_MODE_S 7 ++#define P5_INTF_MODE_M 0x80 ++#define P5_INTF_DIS BIT(6) ++#define C_MDIO_BPS BIT(5) ++#define CHIP_MODE_S 0 ++#define CHIP_MODE_M 0x0f ++ ++/* P5_INTF_SEL: Interface type of Port5 */ ++#define P5_INTF_SEL_GPHY 0 ++#define P5_INTF_SEL_GMAC5 1 ++ ++/* P5_INTF_MODE: Interface mode of Port5 */ ++#define P5_INTF_MODE_GMII_MII 0 ++#define P5_INTF_MODE_RGMII 1 ++ ++#define MT7530_P6ECR 0x7830 ++#define P6_INTF_MODE_M 0x3 ++#define P6_INTF_MODE_S 0 ++ ++/* P6_INTF_MODE: Interface mode of Port6 */ ++#define P6_INTF_MODE_RGMII 0 ++#define P6_INTF_MODE_TRGMII 1 ++ ++#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) ++#define RD_TAP_S 0 ++#define RD_TAP_M 0x7f ++ ++#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) ++/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ ++ ++/* TOP Signals Status Register */ ++#define MT7531_TOP_SIG_SR 0x780c ++#define PAD_MCM_SMI_EN BIT(0) ++#define PAD_DUAL_SGMII_EN BIT(1) ++ ++/* MT7531 PLLGP Registers */ ++#define MT7531_PLLGP_EN 0x7820 ++#define EN_COREPLL BIT(2) ++#define SW_CLKSW BIT(1) ++#define SW_PLLGP BIT(0) ++ ++#define MT7531_PLLGP_CR0 0x78a8 ++#define RG_COREPLL_EN BIT(22) ++#define RG_COREPLL_POSDIV_S 23 ++#define RG_COREPLL_POSDIV_M 0x3800000 ++#define RG_COREPLL_SDM_PCW_S 1 ++#define RG_COREPLL_SDM_PCW_M 0x3ffffe ++#define RG_COREPLL_SDM_PCW_CHG BIT(0) ++ ++/* MT7531 RGMII and SGMII PLL clock */ ++#define MT7531_ANA_PLLGP_CR2 0x78b0 ++#define MT7531_ANA_PLLGP_CR5 0x78bc ++ ++/* MT7531 GPIO GROUP IOLB SMT0 Control */ ++#define MT7531_SMT0_IOLB 0x7f04 ++#define SMT_IOLB_5_SMI_MDC_EN BIT(5) ++ ++/* MT7530 GPHY MDIO MMD Registers */ ++#define CORE_PLL_GROUP2 0x401 ++#define RG_SYSPLL_EN_NORMAL BIT(15) ++#define RG_SYSPLL_VODEN BIT(14) ++#define RG_SYSPLL_POSDIV_S 5 ++#define RG_SYSPLL_POSDIV_M 0x60 ++ ++#define CORE_PLL_GROUP4 0x403 ++#define MT7531_BYPASS_MODE BIT(4) ++#define MT7531_POWER_ON_OFF BIT(5) ++#define RG_SYSPLL_DDSFBK_EN BIT(12) ++#define RG_SYSPLL_BIAS_EN BIT(11) ++#define RG_SYSPLL_BIAS_LPF_EN BIT(10) ++ ++#define CORE_PLL_GROUP5 0x404 ++#define RG_LCDDS_PCW_NCPO1_S 0 ++#define RG_LCDDS_PCW_NCPO1_M 0xffff ++ ++#define CORE_PLL_GROUP6 0x405 ++#define RG_LCDDS_PCW_NCPO0_S 0 ++#define RG_LCDDS_PCW_NCPO0_M 0xffff ++ ++#define CORE_PLL_GROUP7 0x406 ++#define RG_LCDDS_PWDB BIT(15) ++#define RG_LCDDS_ISO_EN BIT(13) ++#define RG_LCCDS_C_S 4 ++#define RG_LCCDS_C_M 0x70 ++#define RG_LCDDS_PCW_NCPO_CHG BIT(3) ++ ++#define CORE_PLL_GROUP10 0x409 ++#define RG_LCDDS_SSC_DELTA_S 0 ++#define RG_LCDDS_SSC_DELTA_M 0xfff ++ ++#define CORE_PLL_GROUP11 0x40a ++#define RG_LCDDS_SSC_DELTA1_S 0 ++#define RG_LCDDS_SSC_DELTA1_M 0xfff ++ ++#define CORE_GSWPLL_GRP1 0x40d ++#define RG_GSWPLL_POSDIV_200M_S 12 ++#define RG_GSWPLL_POSDIV_200M_M 0x3000 ++#define RG_GSWPLL_EN_PRE BIT(11) ++#define RG_GSWPLL_FBKDIV_200M_S 0 ++#define RG_GSWPLL_FBKDIV_200M_M 0xff ++ ++#define CORE_GSWPLL_GRP2 0x40e ++#define RG_GSWPLL_POSDIV_500M_S 8 ++#define RG_GSWPLL_POSDIV_500M_M 0x300 ++#define RG_GSWPLL_FBKDIV_500M_S 0 ++#define RG_GSWPLL_FBKDIV_500M_M 0xff ++ ++#define CORE_TRGMII_GSW_CLK_CG 0x410 ++#define REG_GSWCK_EN BIT(0) ++#define REG_TRGMIICK_EN BIT(1) ++ ++/* Extend PHY Control Register 3 */ ++#define PHY_EXT_REG_14 0x14 ++ ++/* Fields of PHY_EXT_REG_14 */ ++#define PHY_EN_DOWN_SHFIT BIT(4) ++ ++/* Extend PHY Control Register 4 */ ++#define PHY_EXT_REG_17 0x17 ++ ++/* Fields of PHY_EXT_REG_17 */ ++#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) ++ ++/* PHY RXADC Control Register 7 */ ++#define PHY_DEV1E_REG_0C6 0x0c6 ++ ++/* Fields of PHY_DEV1E_REG_0C6 */ ++#define PHY_POWER_SAVING_S 8 ++#define PHY_POWER_SAVING_M 0x300 ++#define PHY_POWER_SAVING_TX 0x0 ++ ++struct mt753x_switch_priv { ++ struct mtk_eth_switch_priv epriv; ++ struct mii_dev *mdio_bus; ++ u32 smi_addr; ++ u32 phy_base; ++ u32 pmcr; ++ ++ int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data); ++ int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data); ++}; ++ ++int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg, ++ u32 *data); ++int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); ++int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); ++ ++int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data); ++int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data); ++void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set); ++ ++int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg); ++int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val); ++int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad, ++ u16 reg); ++int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad, ++ u16 reg, u16 val); ++ ++int mt7531_mdio_register(struct mt753x_switch_priv *priv); ++ ++void mt753x_port_isolation(struct mt753x_switch_priv *priv); ++ ++#endif /* _MTK_ETH_MT753X_H_ */ +--- /dev/null ++++ b/drivers/net/mtk_eth/mt7988.c +@@ -0,0 +1,160 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#include <miiphy.h> ++#include <linux/delay.h> ++#include <linux/mdio.h> ++#include <linux/mii.h> ++#include <linux/io.h> ++#include "mtk_eth.h" ++#include "mt753x.h" ++ ++static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data) ++{ ++ *data = readl(priv->epriv.ethsys_base + GSW_BASE + reg); ++ ++ return 0; ++} ++ ++static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data) ++{ ++ writel(data, priv->epriv.ethsys_base + GSW_BASE + reg); ++ ++ return 0; ++} ++ ++static void mt7988_phy_setting(struct mt753x_switch_priv *priv) ++{ ++ u16 val; ++ u32 i; ++ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ /* Enable HW auto downshift */ ++ mt7531_mii_write(priv, i, 0x1f, 0x1); ++ val = mt7531_mii_read(priv, i, PHY_EXT_REG_14); ++ val |= PHY_EN_DOWN_SHFIT; ++ mt7531_mii_write(priv, i, PHY_EXT_REG_14, val); ++ ++ /* PHY link down power saving enable */ ++ val = mt7531_mii_read(priv, i, PHY_EXT_REG_17); ++ val |= PHY_LINKDOWN_POWER_SAVING_EN; ++ mt7531_mii_write(priv, i, PHY_EXT_REG_17, val); ++ } ++} ++ ++static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u32 pmcr = FORCE_MODE_LNK; ++ ++ if (enable) ++ pmcr = priv->pmcr; ++ ++ mt7988_reg_write(priv, PMCR_REG(6), pmcr); ++} ++ ++static int mt7988_setup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ u16 phy_addr, phy_val; ++ u32 pmcr; ++ int i; ++ ++ priv->smi_addr = MT753X_DFL_SMI_ADDR; ++ priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; ++ priv->reg_read = mt7988_reg_read; ++ priv->reg_write = mt7988_reg_write; ++ ++ /* Turn off PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); ++ phy_val |= BMCR_PDOWN; ++ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ switch (priv->epriv.phy_interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ /* Use CPU bridge instead of actual USXGMII path */ ++ ++ /* Disable GDM1 RX CRC stripping */ ++ /* mtk_fe_rmw(priv, 0x500, BIT(16), 0); */ ++ ++ /* Set GDM1 no drop */ ++ mtk_fe_rmw(priv->epriv.eth, PSE_NO_DROP_CFG_REG, 0, ++ PSE_NO_DROP_GDM1); ++ ++ /* Enable GSW CPU bridge as USXGMII */ ++ /* mtk_fe_rmw(priv, 0x504, BIT(31), BIT(31)); */ ++ ++ /* Enable GDM1 to GSW CPU bridge */ ++ mtk_gmac_rmw(priv->epriv.eth, GMAC_MAC_MISC_REG, 0, BIT(0)); ++ ++ /* XGMAC force link up */ ++ mtk_gmac_rmw(priv->epriv.eth, GMAC_XGMAC_STS_REG, 0, ++ P1_XGMAC_FORCE_LINK); ++ ++ /* Setup GSW CPU bridge IPG */ ++ mtk_gmac_rmw(priv->epriv.eth, GMAC_GSW_CFG_REG, ++ GSWTX_IPG_M | GSWRX_IPG_M, ++ (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); ++ break; ++ default: ++ printf("Error: MT7988 GSW does not support %s interface\n", ++ phy_string_for_interface(priv->epriv.phy_interface)); ++ break; ++ } ++ ++ pmcr = MT7988_FORCE_MODE | ++ (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ MAC_MODE | MAC_TX_EN | MAC_RX_EN | ++ BKOFF_EN | BACKPR_EN | ++ FORCE_RX_FC | FORCE_TX_FC | ++ (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | ++ FORCE_LINK; ++ ++ priv->pmcr = pmcr; ++ ++ /* Keep MAC link down before starting eth */ ++ mt7988_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); ++ ++ /* Enable port isolation to block inter-port communication */ ++ mt753x_port_isolation(priv); ++ ++ /* Turn on PHYs */ ++ for (i = 0; i < MT753X_NUM_PHYS; i++) { ++ phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); ++ phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR); ++ phy_val &= ~BMCR_PDOWN; ++ mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ mt7988_phy_setting(priv); ++ ++ return mt7531_mdio_register(priv); ++} ++ ++static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv; ++ ++ mdio_unregister(priv->mdio_bus); ++ ++ return 0; ++} ++ ++MTK_ETH_SWITCH(mt7988) = { ++ .name = "mt7988", ++ .desc = "MediaTek MT7988 built-in switch", ++ .priv_size = sizeof(struct mt753x_switch_priv), ++ .reset_wait_time = 50, ++ ++ .setup = mt7988_setup, ++ .cleanup = mt7531_cleanup, ++ .mac_control = mt7988_mac_control, ++}; +--- a/drivers/net/mtk_eth.c ++++ /dev/null +@@ -1,2280 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * Copyright (C) 2018 MediaTek Inc. +- * +- * Author: Weijie Gao <weijie.gao@mediatek.com> +- * Author: Mark Lee <mark-mc.lee@mediatek.com> +- */ +- +-#include <cpu_func.h> +-#include <dm.h> +-#include <log.h> +-#include <malloc.h> +-#include <miiphy.h> +-#include <net.h> +-#include <regmap.h> +-#include <reset.h> +-#include <syscon.h> +-#include <wait_bit.h> +-#include <asm/cache.h> +-#include <asm/gpio.h> +-#include <asm/io.h> +-#include <dm/device_compat.h> +-#include <linux/delay.h> +-#include <linux/err.h> +-#include <linux/ioport.h> +-#include <linux/mdio.h> +-#include <linux/mii.h> +-#include <linux/printk.h> +- +-#include "mtk_eth.h" +- +-#define NUM_TX_DESC 32 +-#define NUM_RX_DESC 32 +-#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) +-#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) +-#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) +- +-#define MT753X_NUM_PHYS 5 +-#define MT753X_NUM_PORTS 7 +-#define MT753X_DFL_SMI_ADDR 31 +-#define MT753X_SMI_ADDR_MASK 0x1f +- +-#define MT753X_PHY_ADDR(base, addr) \ +- (((base) + (addr)) & 0x1f) +- +-#define GDMA_FWD_TO_CPU \ +- (0x20000000 | \ +- GDM_ICS_EN | \ +- GDM_TCS_EN | \ +- GDM_UCS_EN | \ +- STRP_CRC | \ +- (DP_PDMA << MYMAC_DP_S) | \ +- (DP_PDMA << BC_DP_S) | \ +- (DP_PDMA << MC_DP_S) | \ +- (DP_PDMA << UN_DP_S)) +- +-#define GDMA_BRIDGE_TO_CPU \ +- (0xC0000000 | \ +- GDM_ICS_EN | \ +- GDM_TCS_EN | \ +- GDM_UCS_EN | \ +- (DP_PDMA << MYMAC_DP_S) | \ +- (DP_PDMA << BC_DP_S) | \ +- (DP_PDMA << MC_DP_S) | \ +- (DP_PDMA << UN_DP_S)) +- +-#define GDMA_FWD_DISCARD \ +- (0x20000000 | \ +- GDM_ICS_EN | \ +- GDM_TCS_EN | \ +- GDM_UCS_EN | \ +- STRP_CRC | \ +- (DP_DISCARD << MYMAC_DP_S) | \ +- (DP_DISCARD << BC_DP_S) | \ +- (DP_DISCARD << MC_DP_S) | \ +- (DP_DISCARD << UN_DP_S)) +- +-enum mtk_switch { +- SW_NONE, +- SW_MT7530, +- SW_MT7531, +- SW_MT7988, +-}; +- +-/* struct mtk_soc_data - This is the structure holding all differences +- * among various plaforms +- * @caps Flags shown the extra capability for the SoC +- * @ana_rgc3: The offset for register ANA_RGC3 related to +- * sgmiisys syscon +- * @gdma_count: Number of GDMAs +- * @pdma_base: Register base of PDMA block +- * @txd_size: Tx DMA descriptor size. +- * @rxd_size: Rx DMA descriptor size. +- */ +-struct mtk_soc_data { +- u32 caps; +- u32 ana_rgc3; +- u32 gdma_count; +- u32 pdma_base; +- u32 txd_size; +- u32 rxd_size; +-}; +- +-struct mtk_eth_priv { +- char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); +- +- void *tx_ring_noc; +- void *rx_ring_noc; +- +- int rx_dma_owner_idx0; +- int tx_cpu_owner_idx0; +- +- void __iomem *fe_base; +- void __iomem *gmac_base; +- void __iomem *sgmii_base; +- void __iomem *gsw_base; +- +- struct regmap *ethsys_regmap; +- +- struct regmap *infra_regmap; +- +- struct regmap *usxgmii_regmap; +- struct regmap *xfi_pextp_regmap; +- struct regmap *xfi_pll_regmap; +- struct regmap *toprgu_regmap; +- +- struct mii_dev *mdio_bus; +- int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); +- int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); +- int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); +- int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, +- u16 val); +- +- const struct mtk_soc_data *soc; +- int gmac_id; +- int force_mode; +- int speed; +- int duplex; +- int mdc; +- bool pn_swap; +- +- struct phy_device *phydev; +- int phy_interface; +- int phy_addr; +- +- enum mtk_switch sw; +- int (*switch_init)(struct mtk_eth_priv *priv); +- void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable); +- u32 mt753x_smi_addr; +- u32 mt753x_phy_base; +- u32 mt753x_pmcr; +- u32 mt753x_reset_wait_time; +- +- struct gpio_desc rst_gpio; +- int mcm; +- +- struct reset_ctl rst_fe; +- struct reset_ctl rst_mcm; +-}; +- +-static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) +-{ +- writel(val, priv->fe_base + priv->soc->pdma_base + reg); +-} +- +-static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, +- u32 set) +-{ +- clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set); +-} +- +-static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, +- u32 val) +-{ +- u32 gdma_base; +- +- if (no == 2) +- gdma_base = GDMA3_BASE; +- else if (no == 1) +- gdma_base = GDMA2_BASE; +- else +- gdma_base = GDMA1_BASE; +- +- writel(val, priv->fe_base + gdma_base + reg); +-} +- +-static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +-{ +- clrsetbits_le32(priv->fe_base + reg, clr, set); +-} +- +-static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) +-{ +- return readl(priv->gmac_base + reg); +-} +- +-static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) +-{ +- writel(val, priv->gmac_base + reg); +-} +- +-static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) +-{ +- clrsetbits_le32(priv->gmac_base + reg, clr, set); +-} +- +-static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, +- u32 set) +-{ +- uint val; +- +- regmap_read(priv->ethsys_regmap, reg, &val); +- val &= ~clr; +- val |= set; +- regmap_write(priv->ethsys_regmap, reg, val); +-} +- +-static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, +- u32 set) +-{ +- uint val; +- +- regmap_read(priv->infra_regmap, reg, &val); +- val &= ~clr; +- val |= set; +- regmap_write(priv->infra_regmap, reg, val); +-} +- +-static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg) +-{ +- return readl(priv->gsw_base + reg); +-} +- +-static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val) +-{ +- writel(val, priv->gsw_base + reg); +-} +- +-/* Direct MDIO clause 22/45 access via SoC */ +-static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, +- u32 cmd, u32 st) +-{ +- int ret; +- u32 val; +- +- val = (st << MDIO_ST_S) | +- ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | +- (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | +- (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); +- +- if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) +- val |= data & MDIO_RW_DATA_M; +- +- mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); +- +- ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, +- PHY_ACS_ST, 0, 5000, 0); +- if (ret) { +- pr_warn("MDIO access timeout\n"); +- return ret; +- } +- +- if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { +- val = mtk_gmac_read(priv, GMAC_PIAC_REG); +- return val & MDIO_RW_DATA_M; +- } +- +- return 0; +-} +- +-/* Direct MDIO clause 22 read via SoC */ +-static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) +-{ +- return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); +-} +- +-/* Direct MDIO clause 22 write via SoC */ +-static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) +-{ +- return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); +-} +- +-/* Direct MDIO clause 45 read via SoC */ +-static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) +-{ +- int ret; +- +- ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); +- if (ret) +- return ret; +- +- return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, +- MDIO_ST_C45); +-} +- +-/* Direct MDIO clause 45 write via SoC */ +-static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, +- u16 reg, u16 val) +-{ +- int ret; +- +- ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); +- if (ret) +- return ret; +- +- return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, +- MDIO_ST_C45); +-} +- +-/* Indirect MDIO clause 45 read via MII registers */ +-static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, +- u16 reg) +-{ +- int ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, +- (MMD_ADDR << MMD_CMD_S) | +- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); +- if (ret) +- return ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); +- if (ret) +- return ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, +- (MMD_DATA << MMD_CMD_S) | +- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); +- if (ret) +- return ret; +- +- return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); +-} +- +-/* Indirect MDIO clause 45 write via MII registers */ +-static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, +- u16 reg, u16 val) +-{ +- int ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, +- (MMD_ADDR << MMD_CMD_S) | +- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); +- if (ret) +- return ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); +- if (ret) +- return ret; +- +- ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, +- (MMD_DATA << MMD_CMD_S) | +- ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); +- if (ret) +- return ret; +- +- return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); +-} +- +-/* +- * MT7530 Internal Register Address Bits +- * ------------------------------------------------------------------- +- * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | +- * |----------------------------------------|---------------|--------| +- * | Page Address | Reg Address | Unused | +- * ------------------------------------------------------------------- +- */ +- +-static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) +-{ +- int ret, low_word, high_word; +- +- if (priv->sw == SW_MT7988) { +- *data = mtk_gsw_read(priv, reg); +- return 0; +- } +- +- /* Write page address */ +- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); +- if (ret) +- return ret; +- +- /* Read low word */ +- low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf); +- if (low_word < 0) +- return low_word; +- +- /* Read high word */ +- high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10); +- if (high_word < 0) +- return high_word; +- +- if (data) +- *data = ((u32)high_word << 16) | (low_word & 0xffff); +- +- return 0; +-} +- +-static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) +-{ +- int ret; +- +- if (priv->sw == SW_MT7988) { +- mtk_gsw_write(priv, reg, data); +- return 0; +- } +- +- /* Write page address */ +- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); +- if (ret) +- return ret; +- +- /* Write low word */ +- ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf, +- data & 0xffff); +- if (ret) +- return ret; +- +- /* Write high word */ +- return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16); +-} +- +-static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, +- u32 set) +-{ +- u32 val; +- +- mt753x_reg_read(priv, reg, &val); +- val &= ~clr; +- val |= set; +- mt753x_reg_write(priv, reg, val); +-} +- +-/* Indirect MDIO clause 22/45 access */ +-static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data, +- u32 cmd, u32 st) +-{ +- ulong timeout; +- u32 val, timeout_ms; +- int ret = 0; +- +- val = (st << MDIO_ST_S) | +- ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | +- ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | +- ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); +- +- if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) +- val |= data & MDIO_RW_DATA_M; +- +- mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); +- +- timeout_ms = 100; +- timeout = get_timer(0); +- while (1) { +- mt753x_reg_read(priv, MT7531_PHY_IAC, &val); +- +- if ((val & PHY_ACS_ST) == 0) +- break; +- +- if (get_timer(timeout) > timeout_ms) +- return -ETIMEDOUT; +- } +- +- if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { +- mt753x_reg_read(priv, MT7531_PHY_IAC, &val); +- ret = val & MDIO_RW_DATA_M; +- } +- +- return ret; +-} +- +-static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) +-{ +- u8 phy_addr; +- +- if (phy >= MT753X_NUM_PHYS) +- return -EINVAL; +- +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); +- +- return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, +- MDIO_ST_C22); +-} +- +-static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, +- u16 val) +-{ +- u8 phy_addr; +- +- if (phy >= MT753X_NUM_PHYS) +- return -EINVAL; +- +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); +- +- return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, +- MDIO_ST_C22); +-} +- +-static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, +- u16 reg) +-{ +- u8 phy_addr; +- int ret; +- +- if (addr >= MT753X_NUM_PHYS) +- return -EINVAL; +- +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); +- +- ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, +- MDIO_ST_C45); +- if (ret) +- return ret; +- +- return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, +- MDIO_ST_C45); +-} +- +-static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, +- u16 reg, u16 val) +-{ +- u8 phy_addr; +- int ret; +- +- if (addr >= MT753X_NUM_PHYS) +- return 0; +- +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); +- +- ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, +- MDIO_ST_C45); +- if (ret) +- return ret; +- +- return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, +- MDIO_ST_C45); +-} +- +-static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +-{ +- struct mtk_eth_priv *priv = bus->priv; +- +- if (devad < 0) +- return priv->mii_read(priv, addr, reg); +- else +- return priv->mmd_read(priv, addr, devad, reg); +-} +- +-static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, +- u16 val) +-{ +- struct mtk_eth_priv *priv = bus->priv; +- +- if (devad < 0) +- return priv->mii_write(priv, addr, reg, val); +- else +- return priv->mmd_write(priv, addr, devad, reg, val); +-} +- +-static int mtk_mdio_register(struct udevice *dev) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- struct mii_dev *mdio_bus = mdio_alloc(); +- int ret; +- +- if (!mdio_bus) +- return -ENOMEM; +- +- /* Assign MDIO access APIs according to the switch/phy */ +- switch (priv->sw) { +- case SW_MT7530: +- priv->mii_read = mtk_mii_read; +- priv->mii_write = mtk_mii_write; +- priv->mmd_read = mtk_mmd_ind_read; +- priv->mmd_write = mtk_mmd_ind_write; +- break; +- case SW_MT7531: +- case SW_MT7988: +- priv->mii_read = mt7531_mii_ind_read; +- priv->mii_write = mt7531_mii_ind_write; +- priv->mmd_read = mt7531_mmd_ind_read; +- priv->mmd_write = mt7531_mmd_ind_write; +- break; +- default: +- priv->mii_read = mtk_mii_read; +- priv->mii_write = mtk_mii_write; +- priv->mmd_read = mtk_mmd_read; +- priv->mmd_write = mtk_mmd_write; +- } +- +- mdio_bus->read = mtk_mdio_read; +- mdio_bus->write = mtk_mdio_write; +- snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); +- +- mdio_bus->priv = (void *)priv; +- +- ret = mdio_register(mdio_bus); +- +- if (ret) +- return ret; +- +- priv->mdio_bus = mdio_bus; +- +- return 0; +-} +- +-static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg) +-{ +- u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); +- +- return priv->mmd_read(priv, phy_addr, 0x1f, reg); +-} +- +-static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) +-{ +- u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); +- +- priv->mmd_write(priv, phy_addr, 0x1f, reg, val); +-} +- +-static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) +-{ +- u32 ncpo1, ssc_delta; +- +- switch (mode) { +- case PHY_INTERFACE_MODE_RGMII: +- ncpo1 = 0x0c80; +- ssc_delta = 0x87; +- break; +- default: +- printf("error: xMII mode %d not supported\n", mode); +- return -EINVAL; +- } +- +- /* Disable MT7530 core clock */ +- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); +- +- /* Disable MT7530 PLL */ +- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, +- (2 << RG_GSWPLL_POSDIV_200M_S) | +- (32 << RG_GSWPLL_FBKDIV_200M_S)); +- +- /* For MT7530 core clock = 500Mhz */ +- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2, +- (1 << RG_GSWPLL_POSDIV_500M_S) | +- (25 << RG_GSWPLL_FBKDIV_500M_S)); +- +- /* Enable MT7530 PLL */ +- mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, +- (2 << RG_GSWPLL_POSDIV_200M_S) | +- (32 << RG_GSWPLL_FBKDIV_200M_S) | +- RG_GSWPLL_EN_PRE); +- +- udelay(20); +- +- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); +- +- /* Setup the MT7530 TRGMII Tx Clock */ +- mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); +- mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0); +- mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); +- mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); +- mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | +- RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); +- +- mt753x_core_reg_write(priv, CORE_PLL_GROUP2, +- RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | +- (1 << RG_SYSPLL_POSDIV_S)); +- +- mt753x_core_reg_write(priv, CORE_PLL_GROUP7, +- RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | +- RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); +- +- /* Enable MT7530 core clock */ +- mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, +- REG_GSWCK_EN | REG_TRGMIICK_EN); +- +- return 0; +-} +- +-static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable) +-{ +- u32 pmcr = FORCE_MODE; +- +- if (enable) +- pmcr = priv->mt753x_pmcr; +- +- mt753x_reg_write(priv, PMCR_REG(6), pmcr); +-} +- +-static int mt7530_setup(struct mtk_eth_priv *priv) +-{ +- u16 phy_addr, phy_val; +- u32 val, txdrv; +- int i; +- +- if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { +- /* Select 250MHz clk for RGMII mode */ +- mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, +- ETHSYS_TRGMII_CLK_SEL362_5, 0); +- +- txdrv = 8; +- } else { +- txdrv = 4; +- } +- +- /* Modify HWTRAP first to allow direct access to internal PHYs */ +- mt753x_reg_read(priv, HWTRAP_REG, &val); +- val |= CHG_TRAP; +- val &= ~C_MDIO_BPS; +- mt753x_reg_write(priv, MHWTRAP_REG, val); +- +- /* Calculate the phy base address */ +- val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; +- priv->mt753x_phy_base = (val | 0x7) + 1; +- +- /* Turn off PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val |= BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- /* Force MAC link down before reset */ +- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); +- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); +- +- /* MT7530 reset */ +- mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); +- udelay(100); +- +- val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +- MAC_MODE | FORCE_MODE | +- MAC_TX_EN | MAC_RX_EN | +- BKOFF_EN | BACKPR_EN | +- (SPEED_1000M << FORCE_SPD_S) | +- FORCE_DPX | FORCE_LINK; +- +- /* MT7530 Port6: Forced 1000M/FD, FC disabled */ +- priv->mt753x_pmcr = val; +- +- /* MT7530 Port5: Forced link down */ +- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); +- +- /* Keep MAC link down before starting eth */ +- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); +- +- /* MT7530 Port6: Set to RGMII */ +- mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); +- +- /* Hardware Trap: Enable Port6, Disable Port5 */ +- mt753x_reg_read(priv, HWTRAP_REG, &val); +- val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | +- (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | +- (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); +- val &= ~(C_MDIO_BPS | P6_INTF_DIS); +- mt753x_reg_write(priv, MHWTRAP_REG, val); +- +- /* Setup switch core pll */ +- mt7530_pad_clk_setup(priv, priv->phy_interface); +- +- /* Lower Tx Driving for TRGMII path */ +- for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) +- mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), +- (txdrv << TD_DM_DRVP_S) | +- (txdrv << TD_DM_DRVN_S)); +- +- for (i = 0 ; i < NUM_TRGMII_CTRL; i++) +- mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); +- +- /* Turn on PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val &= ~BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- return 0; +-} +- +-static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm) +-{ +- /* Step 1 : Disable MT7531 COREPLL */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); +- +- /* Step 2: switch to XTAL output */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); +- +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); +- +- /* Step 3: disable PLLGP and enable program PLLGP */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); +- +- /* Step 4: program COREPLL output frequency to 500MHz */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, +- 2 << RG_COREPLL_POSDIV_S); +- udelay(25); +- +- /* Currently, support XTAL 25Mhz only */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, +- 0x140000 << RG_COREPLL_SDM_PCW_S); +- +- /* Set feedback divide ratio update signal to high */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, +- RG_COREPLL_SDM_PCW_CHG); +- +- /* Wait for at least 16 XTAL clocks */ +- udelay(10); +- +- /* Step 5: set feedback divide ratio update signal to low */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); +- +- /* add enable 325M clock for SGMII */ +- mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); +- +- /* add enable 250SSC clock for RGMII */ +- mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); +- +- /*Step 6: Enable MT7531 PLL */ +- mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); +- +- mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); +- +- udelay(25); +-} +- +-static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, +- u32 port) +-{ +- if (port != 5 && port != 6) { +- printf("mt7531: port %d is not a SGMII port\n", port); +- return -EINVAL; +- } +- +- /* Set SGMII GEN2 speed(2.5G) */ +- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, +- FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); +- +- /* Disable SGMII AN */ +- mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), +- SGMII_AN_ENABLE, 0); +- +- /* SGMII force mode setting */ +- mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); +- +- /* Release PHYA power down state */ +- mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), +- SGMII_PHYA_PWD, 0); +- +- return 0; +-} +- +-static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port) +-{ +- u32 val; +- +- if (port != 5) { +- printf("error: RGMII mode is not available for port %d\n", +- port); +- return -EINVAL; +- } +- +- mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); +- val |= GP_CLK_EN; +- val &= ~GP_MODE_M; +- val |= GP_MODE_RGMII << GP_MODE_S; +- val |= TXCLK_NO_REVERSE; +- val |= RXCLK_NO_DELAY; +- val &= ~CLK_SKEW_IN_M; +- val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; +- val &= ~CLK_SKEW_OUT_M; +- val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; +- mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); +- +- return 0; +-} +- +-static void mt7531_phy_setting(struct mtk_eth_priv *priv) +-{ +- int i; +- u32 val; +- +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- /* Enable HW auto downshift */ +- priv->mii_write(priv, i, 0x1f, 0x1); +- val = priv->mii_read(priv, i, PHY_EXT_REG_14); +- val |= PHY_EN_DOWN_SHFIT; +- priv->mii_write(priv, i, PHY_EXT_REG_14, val); +- +- /* PHY link down power saving enable */ +- val = priv->mii_read(priv, i, PHY_EXT_REG_17); +- val |= PHY_LINKDOWN_POWER_SAVING_EN; +- priv->mii_write(priv, i, PHY_EXT_REG_17, val); +- +- val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); +- val &= ~PHY_POWER_SAVING_M; +- val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; +- priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); +- } +-} +- +-static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable) +-{ +- u32 pmcr = FORCE_MODE_LNK; +- +- if (enable) +- pmcr = priv->mt753x_pmcr; +- +- mt753x_reg_write(priv, PMCR_REG(5), pmcr); +- mt753x_reg_write(priv, PMCR_REG(6), pmcr); +-} +- +-static int mt7531_setup(struct mtk_eth_priv *priv) +-{ +- u16 phy_addr, phy_val; +- u32 val; +- u32 pmcr; +- u32 port5_sgmii; +- int i; +- +- priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & +- MT753X_SMI_ADDR_MASK; +- +- /* Turn off PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val |= BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- /* Force MAC link down before reset */ +- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); +- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); +- +- /* Switch soft reset */ +- mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); +- udelay(100); +- +- /* Enable MDC input Schmitt Trigger */ +- mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, +- SMT_IOLB_5_SMI_MDC_EN); +- +- mt7531_core_pll_setup(priv, priv->mcm); +- +- mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); +- port5_sgmii = !!(val & PAD_DUAL_SGMII_EN); +- +- /* port5 support either RGMII or SGMII, port6 only support SGMII. */ +- switch (priv->phy_interface) { +- case PHY_INTERFACE_MODE_RGMII: +- if (!port5_sgmii) +- mt7531_port_rgmii_init(priv, 5); +- break; +- case PHY_INTERFACE_MODE_2500BASEX: +- mt7531_port_sgmii_init(priv, 6); +- if (port5_sgmii) +- mt7531_port_sgmii_init(priv, 5); +- break; +- default: +- break; +- } +- +- pmcr = MT7531_FORCE_MODE | +- (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +- MAC_MODE | MAC_TX_EN | MAC_RX_EN | +- BKOFF_EN | BACKPR_EN | +- FORCE_RX_FC | FORCE_TX_FC | +- (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | +- FORCE_LINK; +- +- priv->mt753x_pmcr = pmcr; +- +- /* Keep MAC link down before starting eth */ +- mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); +- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); +- +- /* Turn on PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val &= ~BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- mt7531_phy_setting(priv); +- +- /* Enable Internal PHYs */ +- val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4); +- val |= MT7531_BYPASS_MODE; +- val &= ~MT7531_POWER_ON_OFF; +- mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val); +- +- return 0; +-} +- +-static void mt7988_phy_setting(struct mtk_eth_priv *priv) +-{ +- u16 val; +- u32 i; +- +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- /* Enable HW auto downshift */ +- priv->mii_write(priv, i, 0x1f, 0x1); +- val = priv->mii_read(priv, i, PHY_EXT_REG_14); +- val |= PHY_EN_DOWN_SHFIT; +- priv->mii_write(priv, i, PHY_EXT_REG_14, val); +- +- /* PHY link down power saving enable */ +- val = priv->mii_read(priv, i, PHY_EXT_REG_17); +- val |= PHY_LINKDOWN_POWER_SAVING_EN; +- priv->mii_write(priv, i, PHY_EXT_REG_17, val); +- } +-} +- +-static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable) +-{ +- u32 pmcr = FORCE_MODE_LNK; +- +- if (enable) +- pmcr = priv->mt753x_pmcr; +- +- mt753x_reg_write(priv, PMCR_REG(6), pmcr); +-} +- +-static int mt7988_setup(struct mtk_eth_priv *priv) +-{ +- u16 phy_addr, phy_val; +- u32 pmcr; +- int i; +- +- priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE; +- +- priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & +- MT753X_SMI_ADDR_MASK; +- +- /* Turn off PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val |= BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- switch (priv->phy_interface) { +- case PHY_INTERFACE_MODE_USXGMII: +- /* Use CPU bridge instead of actual USXGMII path */ +- +- /* Set GDM1 no drop */ +- mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1); +- +- /* Enable GDM1 to GSW CPU bridge */ +- mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0)); +- +- /* XGMAC force link up */ +- mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK); +- +- /* Setup GSW CPU bridge IPG */ +- mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M, +- (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S)); +- break; +- default: +- printf("Error: MT7988 GSW does not support %s interface\n", +- phy_string_for_interface(priv->phy_interface)); +- break; +- } +- +- pmcr = MT7988_FORCE_MODE | +- (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +- MAC_MODE | MAC_TX_EN | MAC_RX_EN | +- BKOFF_EN | BACKPR_EN | +- FORCE_RX_FC | FORCE_TX_FC | +- (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX | +- FORCE_LINK; +- +- priv->mt753x_pmcr = pmcr; +- +- /* Keep MAC link down before starting eth */ +- mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); +- +- /* Turn on PHYs */ +- for (i = 0; i < MT753X_NUM_PHYS; i++) { +- phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); +- phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); +- phy_val &= ~BMCR_PDOWN; +- priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); +- } +- +- mt7988_phy_setting(priv); +- +- return 0; +-} +- +-static int mt753x_switch_init(struct mtk_eth_priv *priv) +-{ +- int ret; +- int i; +- +- /* Global reset switch */ +- if (priv->mcm) { +- reset_assert(&priv->rst_mcm); +- udelay(1000); +- reset_deassert(&priv->rst_mcm); +- mdelay(priv->mt753x_reset_wait_time); +- } else if (dm_gpio_is_valid(&priv->rst_gpio)) { +- dm_gpio_set_value(&priv->rst_gpio, 0); +- udelay(1000); +- dm_gpio_set_value(&priv->rst_gpio, 1); +- mdelay(priv->mt753x_reset_wait_time); +- } +- +- ret = priv->switch_init(priv); +- if (ret) +- return ret; +- +- /* Set port isolation */ +- for (i = 0; i < MT753X_NUM_PORTS; i++) { +- /* Set port matrix mode */ +- if (i != 6) +- mt753x_reg_write(priv, PCR_REG(i), +- (0x40 << PORT_MATRIX_S)); +- else +- mt753x_reg_write(priv, PCR_REG(i), +- (0x3f << PORT_MATRIX_S)); +- +- /* Set port mode to user port */ +- mt753x_reg_write(priv, PVC_REG(i), +- (0x8100 << STAG_VPID_S) | +- (VLAN_ATTR_USER << VLAN_ATTR_S)); +- } +- +- return 0; +-} +- +-static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) +-{ +- u16 lcl_adv = 0, rmt_adv = 0; +- u8 flowctrl; +- u32 mcr; +- +- mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); +- mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); +- +- if (priv->phydev->duplex) { +- if (priv->phydev->pause) +- rmt_adv = LPA_PAUSE_CAP; +- if (priv->phydev->asym_pause) +- rmt_adv |= LPA_PAUSE_ASYM; +- +- if (priv->phydev->advertising & ADVERTISED_Pause) +- lcl_adv |= ADVERTISE_PAUSE_CAP; +- if (priv->phydev->advertising & ADVERTISED_Asym_Pause) +- lcl_adv |= ADVERTISE_PAUSE_ASYM; +- +- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); +- +- if (flowctrl & FLOW_CTRL_TX) +- mcr |= XGMAC_FORCE_TX_FC; +- if (flowctrl & FLOW_CTRL_RX) +- mcr |= XGMAC_FORCE_RX_FC; +- +- debug("rx pause %s, tx pause %s\n", +- flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", +- flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); +- } +- +- mcr &= ~(XGMAC_TRX_DISABLE); +- mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); +-} +- +-static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) +-{ +- u16 lcl_adv = 0, rmt_adv = 0; +- u8 flowctrl; +- u32 mcr; +- +- mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +- (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | +- MAC_MODE | FORCE_MODE | +- MAC_TX_EN | MAC_RX_EN | +- DEL_RXFIFO_CLR | +- BKOFF_EN | BACKPR_EN; +- +- switch (priv->phydev->speed) { +- case SPEED_10: +- mcr |= (SPEED_10M << FORCE_SPD_S); +- break; +- case SPEED_100: +- mcr |= (SPEED_100M << FORCE_SPD_S); +- break; +- case SPEED_1000: +- case SPEED_2500: +- mcr |= (SPEED_1000M << FORCE_SPD_S); +- break; +- }; +- +- if (priv->phydev->link) +- mcr |= FORCE_LINK; +- +- if (priv->phydev->duplex) { +- mcr |= FORCE_DPX; +- +- if (priv->phydev->pause) +- rmt_adv = LPA_PAUSE_CAP; +- if (priv->phydev->asym_pause) +- rmt_adv |= LPA_PAUSE_ASYM; +- +- if (priv->phydev->advertising & ADVERTISED_Pause) +- lcl_adv |= ADVERTISE_PAUSE_CAP; +- if (priv->phydev->advertising & ADVERTISED_Asym_Pause) +- lcl_adv |= ADVERTISE_PAUSE_ASYM; +- +- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); +- +- if (flowctrl & FLOW_CTRL_TX) +- mcr |= FORCE_TX_FC; +- if (flowctrl & FLOW_CTRL_RX) +- mcr |= FORCE_RX_FC; +- +- debug("rx pause %s, tx pause %s\n", +- flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", +- flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); +- } +- +- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); +-} +- +-static int mtk_phy_start(struct mtk_eth_priv *priv) +-{ +- struct phy_device *phydev = priv->phydev; +- int ret; +- +- ret = phy_startup(phydev); +- +- if (ret) { +- debug("Could not initialize PHY %s\n", phydev->dev->name); +- return ret; +- } +- +- if (!phydev->link) { +- debug("%s: link down.\n", phydev->dev->name); +- return 0; +- } +- +- if (!priv->force_mode) { +- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || +- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) +- mtk_xphy_link_adjust(priv); +- else +- mtk_phy_link_adjust(priv); +- } +- +- debug("Speed: %d, %s duplex%s\n", phydev->speed, +- (phydev->duplex) ? "full" : "half", +- (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +- +- return 0; +-} +- +-static int mtk_phy_probe(struct udevice *dev) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- struct phy_device *phydev; +- +- phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, +- priv->phy_interface); +- if (!phydev) +- return -ENODEV; +- +- phydev->supported &= PHY_GBIT_FEATURES; +- phydev->advertising = phydev->supported; +- +- priv->phydev = phydev; +- phy_config(phydev); +- +- return 0; +-} +- +-static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) +-{ +- /* Set SGMII GEN1 speed(1G) */ +- clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); +- +- /* Enable SGMII AN */ +- setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, +- SGMII_AN_ENABLE); +- +- /* SGMII AN mode setting */ +- writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); +- +- /* SGMII PN SWAP setting */ +- if (priv->pn_swap) { +- setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, +- SGMII_PN_SWAP_TX_RX); +- } +- +- /* Release PHYA power down state */ +- clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, +- SGMII_PHYA_PWD, 0); +-} +- +-static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) +-{ +- /* Set SGMII GEN2 speed(2.5G) */ +- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, +- SGMSYS_SPEED_MASK, +- FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); +- +- /* Disable SGMII AN */ +- clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, +- SGMII_AN_ENABLE, 0); +- +- /* SGMII force mode setting */ +- writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); +- +- /* SGMII PN SWAP setting */ +- if (priv->pn_swap) { +- setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, +- SGMII_PN_SWAP_TX_RX); +- } +- +- /* Release PHYA power down state */ +- clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, +- SGMII_PHYA_PWD, 0); +-} +- +-static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) +-{ +- u32 val = 0; +- +- /* Add software workaround for USXGMII PLL TCL issue */ +- regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, +- RG_XFI_PLL_ANA_SWWA); +- +- regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); +- val |= RG_XFI_PLL_EN; +- regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); +-} +- +-static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) +-{ +- switch (priv->gmac_id) { +- case 1: +- regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); +- regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); +- regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); +- regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); +- regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); +- break; +- case 2: +- regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); +- regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); +- regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); +- regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); +- regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); +- break; +- } +- +- mdelay(10); +-} +- +-static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) +-{ +- regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); +- regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); +- regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); +- ndelay(1020); +- regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); +- ndelay(1020); +- regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); +- +- regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); +- regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); +- regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); +- regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); +- regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); +- regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); +- regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); +- regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); +- regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); +- regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); +- regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); +- regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); +- regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); +- regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); +- regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); +- regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); +- regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); +- regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); +- regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); +- regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); +- regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); +- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); +- regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); +- regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); +- regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); +- regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); +- regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); +- regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); +- regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); +- regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); +- regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); +- regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); +- regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); +- regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); +- regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); +- udelay(150); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); +- udelay(15); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); +- udelay(100); +- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); +- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); +- regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); +- udelay(400); +-} +- +-static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) +-{ +- regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); +- regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); +- regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); +- ndelay(1020); +- regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); +- ndelay(1020); +- +- regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); +- regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); +- regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); +- regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); +- regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); +- regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); +- regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); +- regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); +- regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); +- regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); +- regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); +- regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); +- regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); +- regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); +- regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); +- regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); +- regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); +- regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); +- regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); +- regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); +- regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); +- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); +- regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); +- regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); +- regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); +- regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); +- regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); +- regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); +- regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); +- regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); +- regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); +- regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); +- regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); +- if (priv->gmac_id == 2) +- regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); +- regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); +- regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); +- udelay(150); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); +- udelay(15); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); +- ndelay(1020); +- regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); +- udelay(100); +- regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); +- regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); +- regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); +- udelay(400); +-} +- +-static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) +-{ +- mtk_xfi_pll_enable(priv); +- mtk_usxgmii_reset(priv); +- mtk_usxgmii_setup_phya_an_10000(priv); +-} +- +-static void mtk_10gbaser_init(struct mtk_eth_priv *priv) +-{ +- mtk_xfi_pll_enable(priv); +- mtk_usxgmii_reset(priv); +- mtk_usxgmii_setup_phya_force_10000(priv); +-} +- +-static int mtk_mac_init(struct mtk_eth_priv *priv) +-{ +- int i, sgmii_sel_mask = 0, ge_mode = 0; +- u32 mcr; +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { +- mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, +- INFRA_MISC2_BONDING_OPTION, priv->gmac_id); +- } +- +- switch (priv->phy_interface) { +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII: +- ge_mode = GE_MODE_RGMII; +- break; +- case PHY_INTERFACE_MODE_SGMII: +- case PHY_INTERFACE_MODE_2500BASEX: +- if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { +- printf("Error: SGMII is not supported on this platform\n"); +- return -ENOTSUPP; +- } +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { +- mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, +- SGMII_QPHY_SEL); +- } +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) +- sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; +- +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, +- SYSCFG1_SGMII_SEL(priv->gmac_id)); +- +- if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) +- mtk_sgmii_an_init(priv); +- else +- mtk_sgmii_force_init(priv); +- +- ge_mode = GE_MODE_RGMII; +- break; +- case PHY_INTERFACE_MODE_MII: +- case PHY_INTERFACE_MODE_GMII: +- ge_mode = GE_MODE_MII; +- break; +- case PHY_INTERFACE_MODE_RMII: +- ge_mode = GE_MODE_RMII; +- break; +- default: +- break; +- } +- +- /* set the gmac to the right mode */ +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, +- SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), +- ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); +- +- if (priv->force_mode) { +- mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | +- (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | +- MAC_MODE | FORCE_MODE | +- MAC_TX_EN | MAC_RX_EN | +- BKOFF_EN | BACKPR_EN | +- FORCE_LINK; +- +- switch (priv->speed) { +- case SPEED_10: +- mcr |= SPEED_10M << FORCE_SPD_S; +- break; +- case SPEED_100: +- mcr |= SPEED_100M << FORCE_SPD_S; +- break; +- case SPEED_1000: +- case SPEED_2500: +- mcr |= SPEED_1000M << FORCE_SPD_S; +- break; +- } +- +- if (priv->duplex) +- mcr |= FORCE_DPX; +- +- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); +- } +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && +- !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { +- /* Lower Tx Driving for TRGMII path */ +- for (i = 0 ; i < NUM_TRGMII_CTRL; i++) +- mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), +- (8 << TD_DM_DRVP_S) | +- (8 << TD_DM_DRVN_S)); +- +- mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, +- RX_RST | RXC_DQSISEL); +- mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); +- } +- +- return 0; +-} +- +-static int mtk_xmac_init(struct mtk_eth_priv *priv) +-{ +- u32 force_link = 0; +- +- if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { +- printf("Error: 10Gb interface is not supported on this platform\n"); +- return -ENOTSUPP; +- } +- +- switch (priv->phy_interface) { +- case PHY_INTERFACE_MODE_USXGMII: +- mtk_usxgmii_an_init(priv); +- break; +- case PHY_INTERFACE_MODE_10GBASER: +- mtk_10gbaser_init(priv); +- break; +- default: +- break; +- } +- +- /* Set GMAC to the correct mode */ +- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, +- SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), +- 0); +- +- if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && +- priv->gmac_id == 1) { +- mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, +- NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); +- } +- +- if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII || +- priv->gmac_id == 2) +- force_link = XGMAC_FORCE_LINK(priv->gmac_id); +- +- mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id), +- XGMAC_FORCE_LINK(priv->gmac_id), force_link); +- +- /* Force GMAC link down */ +- mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); +- +- return 0; +-} +- +-static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) +-{ +- char *pkt_base = priv->pkt_pool; +- struct mtk_tx_dma_v2 *txd; +- struct mtk_rx_dma_v2 *rxd; +- int i; +- +- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); +- udelay(500); +- +- memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); +- memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); +- memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); +- +- flush_dcache_range((ulong)pkt_base, +- (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); +- +- priv->rx_dma_owner_idx0 = 0; +- priv->tx_cpu_owner_idx0 = 0; +- +- for (i = 0; i < NUM_TX_DESC; i++) { +- txd = priv->tx_ring_noc + i * priv->soc->txd_size; +- +- txd->txd1 = virt_to_phys(pkt_base); +- txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? +- 15 : priv->gmac_id + 1); +- else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) +- txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); +- else +- txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); +- +- pkt_base += PKTSIZE_ALIGN; +- } +- +- for (i = 0; i < NUM_RX_DESC; i++) { +- rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; +- +- rxd->rxd1 = virt_to_phys(pkt_base); +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || +- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +- else +- rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +- +- pkt_base += PKTSIZE_ALIGN; +- } +- +- mtk_pdma_write(priv, TX_BASE_PTR_REG(0), +- virt_to_phys(priv->tx_ring_noc)); +- mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); +- mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); +- +- mtk_pdma_write(priv, RX_BASE_PTR_REG(0), +- virt_to_phys(priv->rx_ring_noc)); +- mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); +- mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); +- +- mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); +-} +- +-static void mtk_eth_mdc_init(struct mtk_eth_priv *priv) +-{ +- u32 divider; +- +- if (priv->mdc == 0) +- return; +- +- divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER); +- +- /* Configure MDC turbo mode */ +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO); +- else +- mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO); +- +- /* Configure MDC divider */ +- mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG, +- FIELD_PREP(PHY_MDC_CFG, divider)); +-} +- +-static int mtk_eth_start(struct udevice *dev) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- int i, ret; +- +- /* Reset FE */ +- reset_assert(&priv->rst_fe); +- udelay(1000); +- reset_deassert(&priv->rst_fe); +- mdelay(10); +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || +- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); +- +- /* Packets forward to PDMA */ +- mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); +- +- for (i = 0; i < priv->soc->gdma_count; i++) { +- if (i == priv->gmac_id) +- continue; +- +- mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); +- } +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { +- if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { +- mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, +- GDMA_BRIDGE_TO_CPU); +- +- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, +- GDMA_CPU_BRIDGE_EN); +- } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || +- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && +- priv->gmac_id != 0) { +- mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, +- GDMA_CPU_BRIDGE_EN); +- } +- } +- +- udelay(500); +- +- mtk_eth_fifo_init(priv); +- +- if (priv->switch_mac_control) +- priv->switch_mac_control(priv, true); +- +- /* Start PHY */ +- if (priv->sw == SW_NONE) { +- ret = mtk_phy_start(priv); +- if (ret) +- return ret; +- } +- +- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, +- TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +- udelay(500); +- +- return 0; +-} +- +-static void mtk_eth_stop(struct udevice *dev) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- +- if (priv->switch_mac_control) +- priv->switch_mac_control(priv, false); +- +- mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, +- TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); +- udelay(500); +- +- wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG, +- RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); +-} +- +-static int mtk_eth_write_hwaddr(struct udevice *dev) +-{ +- struct eth_pdata *pdata = dev_get_plat(dev); +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- unsigned char *mac = pdata->enetaddr; +- u32 macaddr_lsb, macaddr_msb; +- +- macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1]; +- macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) | +- ((u32)mac[4] << 8) | (u32)mac[5]; +- +- mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); +- mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); +- +- return 0; +-} +- +-static int mtk_eth_send(struct udevice *dev, void *packet, int length) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- u32 idx = priv->tx_cpu_owner_idx0; +- struct mtk_tx_dma_v2 *txd; +- void *pkt_base; +- +- txd = priv->tx_ring_noc + idx * priv->soc->txd_size; +- +- if (!(txd->txd2 & PDMA_TXD2_DDONE)) { +- debug("mtk-eth: TX DMA descriptor ring is full\n"); +- return -EPERM; +- } +- +- pkt_base = (void *)phys_to_virt(txd->txd1); +- memcpy(pkt_base, packet, length); +- flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + +- roundup(length, ARCH_DMA_MINALIGN)); +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || +- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); +- else +- txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); +- +- priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; +- mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); +- +- return 0; +-} +- +-static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- u32 idx = priv->rx_dma_owner_idx0; +- struct mtk_rx_dma_v2 *rxd; +- uchar *pkt_base; +- u32 length; +- +- rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; +- +- if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { +- debug("mtk-eth: RX DMA descriptor ring is empty\n"); +- return -EAGAIN; +- } +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || +- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); +- else +- length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); +- +- pkt_base = (void *)phys_to_virt(rxd->rxd1); +- invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + +- roundup(length, ARCH_DMA_MINALIGN)); +- +- if (packetp) +- *packetp = pkt_base; +- +- return length; +-} +- +-static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- u32 idx = priv->rx_dma_owner_idx0; +- struct mtk_rx_dma_v2 *rxd; +- +- rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; +- +- invalidate_dcache_range((ulong)rxd->rxd1, +- (ulong)rxd->rxd1 + PKTSIZE_ALIGN); +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || +- MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) +- rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +- else +- rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); +- +- mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); +- priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; +- +- return 0; +-} +- +-static int mtk_eth_probe(struct udevice *dev) +-{ +- struct eth_pdata *pdata = dev_get_plat(dev); +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- ulong iobase = pdata->iobase; +- int ret; +- +- /* Frame Engine Register Base */ +- priv->fe_base = (void *)iobase; +- +- /* GMAC Register Base */ +- priv->gmac_base = (void *)(iobase + GMAC_BASE); +- +- /* MDIO register */ +- ret = mtk_mdio_register(dev); +- if (ret) +- return ret; +- +- /* Prepare for tx/rx rings */ +- priv->tx_ring_noc = (void *) +- noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, +- ARCH_DMA_MINALIGN); +- priv->rx_ring_noc = (void *) +- noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, +- ARCH_DMA_MINALIGN); +- +- /* Set MDC divider */ +- mtk_eth_mdc_init(priv); +- +- /* Set MAC mode */ +- if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || +- priv->phy_interface == PHY_INTERFACE_MODE_XGMII) +- ret = mtk_xmac_init(priv); +- else +- ret = mtk_mac_init(priv); +- +- if (ret) +- return ret; +- +- /* Probe phy if switch is not specified */ +- if (priv->sw == SW_NONE) +- return mtk_phy_probe(dev); +- +- /* Initialize switch */ +- return mt753x_switch_init(priv); +-} +- +-static int mtk_eth_remove(struct udevice *dev) +-{ +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- +- /* MDIO unregister */ +- mdio_unregister(priv->mdio_bus); +- mdio_free(priv->mdio_bus); +- +- /* Stop possibly started DMA */ +- mtk_eth_stop(dev); +- +- return 0; +-} +- +-static int mtk_eth_of_to_plat(struct udevice *dev) +-{ +- struct eth_pdata *pdata = dev_get_plat(dev); +- struct mtk_eth_priv *priv = dev_get_priv(dev); +- struct ofnode_phandle_args args; +- struct regmap *regmap; +- const char *str; +- ofnode subnode; +- int ret; +- +- priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); +- if (!priv->soc) { +- dev_err(dev, "missing soc compatible data\n"); +- return -EINVAL; +- } +- +- pdata->iobase = (phys_addr_t)dev_remap_addr(dev); +- +- /* get corresponding ethsys phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0, +- &args); +- if (ret) +- return ret; +- +- priv->ethsys_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->ethsys_regmap)) +- return PTR_ERR(priv->ethsys_regmap); +- +- if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { +- /* get corresponding infracfg phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", +- NULL, 0, 0, &args); +- +- if (ret) +- return ret; +- +- priv->infra_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->infra_regmap)) +- return PTR_ERR(priv->infra_regmap); +- } +- +- /* Reset controllers */ +- ret = reset_get_by_name(dev, "fe", &priv->rst_fe); +- if (ret) { +- printf("error: Unable to get reset ctrl for frame engine\n"); +- return ret; +- } +- +- priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); +- +- priv->mdc = 0; +- subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio"); +- if (ofnode_valid(subnode)) { +- priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000); +- if (priv->mdc > MDC_MAX_FREQ || +- priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { +- printf("error: MDIO clock frequency out of range\n"); +- return -EINVAL; +- } +- } +- +- /* Interface mode is required */ +- pdata->phy_interface = dev_read_phy_mode(dev); +- priv->phy_interface = pdata->phy_interface; +- if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { +- printf("error: phy-mode is not set\n"); +- return -EINVAL; +- } +- +- /* Force mode or autoneg */ +- subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link"); +- if (ofnode_valid(subnode)) { +- priv->force_mode = 1; +- priv->speed = ofnode_read_u32_default(subnode, "speed", 0); +- priv->duplex = ofnode_read_bool(subnode, "full-duplex"); +- +- if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && +- priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && +- priv->speed != SPEED_10000) { +- printf("error: no valid speed set in fixed-link\n"); +- return -EINVAL; +- } +- } +- +- if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && +- IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { +- /* get corresponding sgmii phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", +- NULL, 0, 0, &args); +- if (ret) +- return ret; +- +- regmap = syscon_node_to_regmap(args.node); +- +- if (IS_ERR(regmap)) +- return PTR_ERR(regmap); +- +- priv->sgmii_base = regmap_get_range(regmap, 0); +- +- if (!priv->sgmii_base) { +- dev_err(dev, "Unable to find sgmii\n"); +- return -ENODEV; +- } +- +- /* Upstream linux use mediatek,pnswap instead of pn_swap */ +- priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || +- ofnode_read_bool(args.node, "mediatek,pnswap"); +- } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || +- priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && +- IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { +- /* get corresponding usxgmii phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", +- NULL, 0, 0, &args); +- if (ret) +- return ret; +- +- priv->usxgmii_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->usxgmii_regmap)) +- return PTR_ERR(priv->usxgmii_regmap); +- +- /* get corresponding xfi_pextp phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", +- NULL, 0, 0, &args); +- if (ret) +- return ret; +- +- priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->xfi_pextp_regmap)) +- return PTR_ERR(priv->xfi_pextp_regmap); +- +- /* get corresponding xfi_pll phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", +- NULL, 0, 0, &args); +- if (ret) +- return ret; +- +- priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->xfi_pll_regmap)) +- return PTR_ERR(priv->xfi_pll_regmap); +- +- /* get corresponding toprgu phandle */ +- ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", +- NULL, 0, 0, &args); +- if (ret) +- return ret; +- +- priv->toprgu_regmap = syscon_node_to_regmap(args.node); +- if (IS_ERR(priv->toprgu_regmap)) +- return PTR_ERR(priv->toprgu_regmap); +- } +- +- /* check for switch first, otherwise phy will be used */ +- priv->sw = SW_NONE; +- priv->switch_init = NULL; +- priv->switch_mac_control = NULL; +- str = dev_read_string(dev, "mediatek,switch"); +- +- if (str) { +- if (!strcmp(str, "mt7530")) { +- priv->sw = SW_MT7530; +- priv->switch_init = mt7530_setup; +- priv->switch_mac_control = mt7530_mac_control; +- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; +- priv->mt753x_reset_wait_time = 1000; +- } else if (!strcmp(str, "mt7531")) { +- priv->sw = SW_MT7531; +- priv->switch_init = mt7531_setup; +- priv->switch_mac_control = mt7531_mac_control; +- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; +- priv->mt753x_reset_wait_time = 200; +- } else if (!strcmp(str, "mt7988")) { +- priv->sw = SW_MT7988; +- priv->switch_init = mt7988_setup; +- priv->switch_mac_control = mt7988_mac_control; +- priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; +- priv->mt753x_reset_wait_time = 50; +- } else { +- printf("error: unsupported switch\n"); +- return -EINVAL; +- } +- +- priv->mcm = dev_read_bool(dev, "mediatek,mcm"); +- if (priv->mcm) { +- ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); +- if (ret) { +- printf("error: no reset ctrl for mcm\n"); +- return ret; +- } +- } else { +- gpio_request_by_name(dev, "reset-gpios", 0, +- &priv->rst_gpio, GPIOD_IS_OUT); +- } +- } else { +- ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, +- 0, &args); +- if (ret) { +- printf("error: phy-handle is not specified\n"); +- return ret; +- } +- +- priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); +- if (priv->phy_addr < 0) { +- printf("error: phy address is not specified\n"); +- return ret; +- } +- } +- +- return 0; +-} +- +-static const struct mtk_soc_data mt7988_data = { +- .caps = MT7988_CAPS, +- .ana_rgc3 = 0x128, +- .gdma_count = 3, +- .pdma_base = PDMA_V3_BASE, +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +-}; +- +-static const struct mtk_soc_data mt7986_data = { +- .caps = MT7986_CAPS, +- .ana_rgc3 = 0x128, +- .gdma_count = 2, +- .pdma_base = PDMA_V2_BASE, +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +-}; +- +-static const struct mtk_soc_data mt7981_data = { +- .caps = MT7981_CAPS, +- .ana_rgc3 = 0x128, +- .gdma_count = 2, +- .pdma_base = PDMA_V2_BASE, +- .txd_size = sizeof(struct mtk_tx_dma_v2), +- .rxd_size = sizeof(struct mtk_rx_dma_v2), +-}; +- +-static const struct mtk_soc_data mt7629_data = { +- .caps = MT7629_CAPS, +- .ana_rgc3 = 0x128, +- .gdma_count = 2, +- .pdma_base = PDMA_V1_BASE, +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +-}; +- +-static const struct mtk_soc_data mt7623_data = { +- .caps = MT7623_CAPS, +- .gdma_count = 2, +- .pdma_base = PDMA_V1_BASE, +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +-}; +- +-static const struct mtk_soc_data mt7622_data = { +- .caps = MT7622_CAPS, +- .ana_rgc3 = 0x2028, +- .gdma_count = 2, +- .pdma_base = PDMA_V1_BASE, +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +-}; +- +-static const struct mtk_soc_data mt7621_data = { +- .caps = MT7621_CAPS, +- .gdma_count = 2, +- .pdma_base = PDMA_V1_BASE, +- .txd_size = sizeof(struct mtk_tx_dma), +- .rxd_size = sizeof(struct mtk_rx_dma), +-}; +- +-static const struct udevice_id mtk_eth_ids[] = { +- { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, +- { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, +- { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, +- { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, +- { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, +- { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, +- { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, +- {} +-}; +- +-static const struct eth_ops mtk_eth_ops = { +- .start = mtk_eth_start, +- .stop = mtk_eth_stop, +- .send = mtk_eth_send, +- .recv = mtk_eth_recv, +- .free_pkt = mtk_eth_free_pkt, +- .write_hwaddr = mtk_eth_write_hwaddr, +-}; +- +-U_BOOT_DRIVER(mtk_eth) = { +- .name = "mtk-eth", +- .id = UCLASS_ETH, +- .of_match = mtk_eth_ids, +- .of_to_plat = mtk_eth_of_to_plat, +- .plat_auto = sizeof(struct eth_pdata), +- .probe = mtk_eth_probe, +- .remove = mtk_eth_remove, +- .ops = &mtk_eth_ops, +- .priv_auto = sizeof(struct mtk_eth_priv), +- .flags = DM_FLAG_ALLOC_PRIV_DMA, +-}; +--- /dev/null ++++ b/drivers/net/mtk_eth/mtk_eth.c +@@ -0,0 +1,1563 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#include <cpu_func.h> ++#include <dm.h> ++#include <log.h> ++#include <malloc.h> ++#include <miiphy.h> ++#include <net.h> ++#include <regmap.h> ++#include <reset.h> ++#include <syscon.h> ++#include <wait_bit.h> ++#include <asm/cache.h> ++#include <asm/gpio.h> ++#include <asm/io.h> ++#include <dm/device_compat.h> ++#include <linux/delay.h> ++#include <linux/err.h> ++#include <linux/ioport.h> ++#include <linux/mdio.h> ++#include <linux/mii.h> ++#include <linux/printk.h> ++ ++#include "mtk_eth.h" ++ ++#define NUM_TX_DESC 32 ++#define NUM_RX_DESC 32 ++#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) ++#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) ++#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) ++ ++#define GDMA_FWD_TO_CPU \ ++ (0x20000000 | \ ++ GDM_ICS_EN | \ ++ GDM_TCS_EN | \ ++ GDM_UCS_EN | \ ++ STRP_CRC | \ ++ (DP_PDMA << MYMAC_DP_S) | \ ++ (DP_PDMA << BC_DP_S) | \ ++ (DP_PDMA << MC_DP_S) | \ ++ (DP_PDMA << UN_DP_S)) ++ ++#define GDMA_BRIDGE_TO_CPU \ ++ (0xC0000000 | \ ++ GDM_ICS_EN | \ ++ GDM_TCS_EN | \ ++ GDM_UCS_EN | \ ++ (DP_PDMA << MYMAC_DP_S) | \ ++ (DP_PDMA << BC_DP_S) | \ ++ (DP_PDMA << MC_DP_S) | \ ++ (DP_PDMA << UN_DP_S)) ++ ++#define GDMA_FWD_DISCARD \ ++ (0x20000000 | \ ++ GDM_ICS_EN | \ ++ GDM_TCS_EN | \ ++ GDM_UCS_EN | \ ++ STRP_CRC | \ ++ (DP_DISCARD << MYMAC_DP_S) | \ ++ (DP_DISCARD << BC_DP_S) | \ ++ (DP_DISCARD << MC_DP_S) | \ ++ (DP_DISCARD << UN_DP_S)) ++ ++struct mtk_eth_priv { ++ char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); ++ ++ void *tx_ring_noc; ++ void *rx_ring_noc; ++ ++ int rx_dma_owner_idx0; ++ int tx_cpu_owner_idx0; ++ ++ void __iomem *fe_base; ++ void __iomem *gmac_base; ++ void __iomem *sgmii_base; ++ ++ struct regmap *ethsys_regmap; ++ ++ struct regmap *infra_regmap; ++ ++ struct regmap *usxgmii_regmap; ++ struct regmap *xfi_pextp_regmap; ++ struct regmap *xfi_pll_regmap; ++ struct regmap *toprgu_regmap; ++ ++ struct mii_dev *mdio_bus; ++ ++ const struct mtk_soc_data *soc; ++ int gmac_id; ++ int force_mode; ++ int speed; ++ int duplex; ++ int mdc; ++ bool pn_swap; ++ ++ struct phy_device *phydev; ++ int phy_interface; ++ int phy_addr; ++ ++ struct mtk_eth_switch_priv *swpriv; ++ const char *swname; ++ ++ struct gpio_desc rst_gpio; ++ int mcm; ++ ++ struct reset_ctl rst_fe; ++ struct reset_ctl rst_mcm; ++}; ++ ++static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) ++{ ++ writel(val, priv->fe_base + priv->soc->pdma_base + reg); ++} ++ ++static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, ++ u32 set) ++{ ++ clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set); ++} ++ ++static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, ++ u32 val) ++{ ++ u32 gdma_base; ++ ++ if (no == 2) ++ gdma_base = GDMA3_BASE; ++ else if (no == 1) ++ gdma_base = GDMA2_BASE; ++ else ++ gdma_base = GDMA1_BASE; ++ ++ writel(val, priv->fe_base + gdma_base + reg); ++} ++ ++void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) ++{ ++ clrsetbits_le32(priv->fe_base + reg, clr, set); ++} ++ ++static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) ++{ ++ return readl(priv->gmac_base + reg); ++} ++ ++static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) ++{ ++ writel(val, priv->gmac_base + reg); ++} ++ ++void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) ++{ ++ clrsetbits_le32(priv->gmac_base + reg, clr, set); ++} ++ ++void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) ++{ ++ uint val; ++ ++ regmap_read(priv->ethsys_regmap, reg, &val); ++ val &= ~clr; ++ val |= set; ++ regmap_write(priv->ethsys_regmap, reg, val); ++} ++ ++static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, ++ u32 set) ++{ ++ uint val; ++ ++ regmap_read(priv->infra_regmap, reg, &val); ++ val &= ~clr; ++ val |= set; ++ regmap_write(priv->infra_regmap, reg, val); ++} ++ ++/* Direct MDIO clause 22/45 access via SoC */ ++static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, ++ u32 cmd, u32 st) ++{ ++ int ret; ++ u32 val; ++ ++ val = (st << MDIO_ST_S) | ++ ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | ++ (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | ++ (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); ++ ++ if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) ++ val |= data & MDIO_RW_DATA_M; ++ ++ mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); ++ ++ ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, ++ PHY_ACS_ST, 0, 5000, 0); ++ if (ret) { ++ pr_warn("MDIO access timeout\n"); ++ return ret; ++ } ++ ++ if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { ++ val = mtk_gmac_read(priv, GMAC_PIAC_REG); ++ return val & MDIO_RW_DATA_M; ++ } ++ ++ return 0; ++} ++ ++/* Direct MDIO clause 22 read via SoC */ ++int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) ++{ ++ return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); ++} ++ ++/* Direct MDIO clause 22 write via SoC */ ++int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) ++{ ++ return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); ++} ++ ++/* Direct MDIO clause 45 read via SoC */ ++int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) ++{ ++ int ret; ++ ++ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); ++ if (ret) ++ return ret; ++ ++ return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, ++ MDIO_ST_C45); ++} ++ ++/* Direct MDIO clause 45 write via SoC */ ++int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, ++ u16 val) ++{ ++ int ret; ++ ++ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); ++ if (ret) ++ return ret; ++ ++ return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, ++ MDIO_ST_C45); ++} ++ ++/* Indirect MDIO clause 45 read via MII registers */ ++int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) ++{ ++ int ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, ++ (MMD_ADDR << MMD_CMD_S) | ++ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, ++ (MMD_DATA << MMD_CMD_S) | ++ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); ++ if (ret) ++ return ret; ++ ++ return mtk_mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); ++} ++ ++/* Indirect MDIO clause 45 write via MII registers */ ++int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, ++ u16 val) ++{ ++ int ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, ++ (MMD_ADDR << MMD_CMD_S) | ++ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG, ++ (MMD_DATA << MMD_CMD_S) | ++ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); ++ if (ret) ++ return ret; ++ ++ return mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); ++} ++ ++static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) ++{ ++ struct mtk_eth_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_read(priv, addr, reg); ++ ++ return mtk_mmd_read(priv, addr, devad, reg); ++} ++ ++static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, ++ u16 val) ++{ ++ struct mtk_eth_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_write(priv, addr, reg, val); ++ ++ return mtk_mmd_write(priv, addr, devad, reg, val); ++} ++ ++static int mtk_mdio_register(struct udevice *dev) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ struct mii_dev *mdio_bus = mdio_alloc(); ++ int ret; ++ ++ if (!mdio_bus) ++ return -ENOMEM; ++ ++ mdio_bus->read = mtk_mdio_read; ++ mdio_bus->write = mtk_mdio_write; ++ snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); ++ ++ mdio_bus->priv = (void *)priv; ++ ++ ret = mdio_register(mdio_bus); ++ ++ if (ret) ++ return ret; ++ ++ priv->mdio_bus = mdio_bus; ++ ++ return 0; ++} ++ ++static int mtk_switch_init(struct mtk_eth_priv *priv) ++{ ++ struct mtk_eth_switch *swdrvs = ll_entry_start(struct mtk_eth_switch, ++ mtk_eth_switch); ++ const u32 n_swdrvs = ll_entry_count(struct mtk_eth_switch, ++ mtk_eth_switch); ++ struct mtk_eth_switch *tmp, *swdrv = NULL; ++ u32 reset_wait_time = 500; ++ size_t priv_size; ++ int ret; ++ ++ if (strcmp(priv->swname, "auto")) { ++ for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { ++ if (!strcmp(tmp->name, priv->swname)) { ++ swdrv = tmp; ++ break; ++ } ++ } ++ } ++ ++ if (swdrv) ++ reset_wait_time = swdrv->reset_wait_time; ++ ++ /* Global reset switch */ ++ if (priv->mcm) { ++ reset_assert(&priv->rst_mcm); ++ udelay(1000); ++ reset_deassert(&priv->rst_mcm); ++ mdelay(reset_wait_time); ++ } else if (dm_gpio_is_valid(&priv->rst_gpio)) { ++ dm_gpio_set_value(&priv->rst_gpio, 0); ++ udelay(1000); ++ dm_gpio_set_value(&priv->rst_gpio, 1); ++ mdelay(reset_wait_time); ++ } ++ ++ if (!swdrv) { ++ for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) { ++ if (!tmp->detect) ++ continue; ++ ++ ret = tmp->detect(priv); ++ if (!ret) { ++ swdrv = tmp; ++ break; ++ } ++ } ++ ++ if (!swdrv) { ++ printf("Error: unable to detect switch\n"); ++ return -ENODEV; ++ } ++ } else { ++ if (swdrv->detect) { ++ ret = swdrv->detect(priv); ++ if (ret) { ++ printf("Error: switch probing failed\n"); ++ return -ENODEV; ++ } ++ } ++ } ++ ++ printf("%s\n", swdrv->desc); ++ ++ priv_size = swdrv->priv_size; ++ if (priv_size < sizeof(struct mtk_eth_switch_priv)) ++ priv_size = sizeof(struct mtk_eth_switch_priv); ++ ++ priv->swpriv = calloc(1, priv_size); ++ if (!priv->swpriv) { ++ printf("Error: no memory for switch data\n"); ++ return -ENOMEM; ++ } ++ ++ priv->swpriv->eth = priv; ++ priv->swpriv->soc = priv->soc; ++ priv->swpriv->phy_interface = priv->phy_interface; ++ priv->swpriv->sw = swdrv; ++ priv->swpriv->ethsys_base = regmap_get_range(priv->ethsys_regmap, 0); ++ ++ ret = swdrv->setup(priv->swpriv); ++ if (ret) { ++ free(priv->swpriv); ++ priv->swpriv = NULL; ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv) ++{ ++ u16 lcl_adv = 0, rmt_adv = 0; ++ u8 flowctrl; ++ u32 mcr; ++ ++ mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id)); ++ mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC); ++ ++ if (priv->phydev->duplex) { ++ if (priv->phydev->pause) ++ rmt_adv = LPA_PAUSE_CAP; ++ if (priv->phydev->asym_pause) ++ rmt_adv |= LPA_PAUSE_ASYM; ++ ++ if (priv->phydev->advertising & ADVERTISED_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_CAP; ++ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ ++ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); ++ ++ if (flowctrl & FLOW_CTRL_TX) ++ mcr |= XGMAC_FORCE_TX_FC; ++ if (flowctrl & FLOW_CTRL_RX) ++ mcr |= XGMAC_FORCE_RX_FC; ++ ++ debug("rx pause %s, tx pause %s\n", ++ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", ++ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); ++ } ++ ++ mcr &= ~(XGMAC_TRX_DISABLE); ++ mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr); ++} ++ ++static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) ++{ ++ u16 lcl_adv = 0, rmt_adv = 0; ++ u8 flowctrl; ++ u32 mcr; ++ ++ mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | ++ MAC_MODE | FORCE_MODE | ++ MAC_TX_EN | MAC_RX_EN | ++ DEL_RXFIFO_CLR | ++ BKOFF_EN | BACKPR_EN; ++ ++ switch (priv->phydev->speed) { ++ case SPEED_10: ++ mcr |= (SPEED_10M << FORCE_SPD_S); ++ break; ++ case SPEED_100: ++ mcr |= (SPEED_100M << FORCE_SPD_S); ++ break; ++ case SPEED_1000: ++ case SPEED_2500: ++ mcr |= (SPEED_1000M << FORCE_SPD_S); ++ break; ++ }; ++ ++ if (priv->phydev->link) ++ mcr |= FORCE_LINK; ++ ++ if (priv->phydev->duplex) { ++ mcr |= FORCE_DPX; ++ ++ if (priv->phydev->pause) ++ rmt_adv = LPA_PAUSE_CAP; ++ if (priv->phydev->asym_pause) ++ rmt_adv |= LPA_PAUSE_ASYM; ++ ++ if (priv->phydev->advertising & ADVERTISED_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_CAP; ++ if (priv->phydev->advertising & ADVERTISED_Asym_Pause) ++ lcl_adv |= ADVERTISE_PAUSE_ASYM; ++ ++ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); ++ ++ if (flowctrl & FLOW_CTRL_TX) ++ mcr |= FORCE_TX_FC; ++ if (flowctrl & FLOW_CTRL_RX) ++ mcr |= FORCE_RX_FC; ++ ++ debug("rx pause %s, tx pause %s\n", ++ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", ++ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); ++ } ++ ++ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); ++} ++ ++static int mtk_phy_start(struct mtk_eth_priv *priv) ++{ ++ struct phy_device *phydev = priv->phydev; ++ int ret; ++ ++ ret = phy_startup(phydev); ++ ++ if (ret) { ++ debug("Could not initialize PHY %s\n", phydev->dev->name); ++ return ret; ++ } ++ ++ if (!phydev->link) { ++ debug("%s: link down.\n", phydev->dev->name); ++ return 0; ++ } ++ ++ if (!priv->force_mode) { ++ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || ++ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) ++ mtk_xphy_link_adjust(priv); ++ else ++ mtk_phy_link_adjust(priv); ++ } ++ ++ debug("Speed: %d, %s duplex%s\n", phydev->speed, ++ (phydev->duplex) ? "full" : "half", ++ (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); ++ ++ return 0; ++} ++ ++static int mtk_phy_probe(struct udevice *dev) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ struct phy_device *phydev; ++ ++ phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, ++ priv->phy_interface); ++ if (!phydev) ++ return -ENODEV; ++ ++ phydev->supported &= PHY_GBIT_FEATURES; ++ phydev->advertising = phydev->supported; ++ ++ priv->phydev = phydev; ++ phy_config(phydev); ++ ++ return 0; ++} ++ ++static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) ++{ ++ /* Set SGMII GEN1 speed(1G) */ ++ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); ++ ++ /* Enable SGMII AN */ ++ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, ++ SGMII_AN_ENABLE); ++ ++ /* SGMII AN mode setting */ ++ writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); ++ ++ /* SGMII PN SWAP setting */ ++ if (priv->pn_swap) { ++ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, ++ SGMII_PN_SWAP_TX_RX); ++ } ++ ++ /* Release PHYA power down state */ ++ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, ++ SGMII_PHYA_PWD, 0); ++} ++ ++static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) ++{ ++ /* Set SGMII GEN2 speed(2.5G) */ ++ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, ++ SGMSYS_SPEED_MASK, ++ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); ++ ++ /* Disable SGMII AN */ ++ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, ++ SGMII_AN_ENABLE, 0); ++ ++ /* SGMII force mode setting */ ++ writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); ++ ++ /* SGMII PN SWAP setting */ ++ if (priv->pn_swap) { ++ setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL, ++ SGMII_PN_SWAP_TX_RX); ++ } ++ ++ /* Release PHYA power down state */ ++ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, ++ SGMII_PHYA_PWD, 0); ++} ++ ++static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv) ++{ ++ u32 val = 0; ++ ++ /* Add software workaround for USXGMII PLL TCL issue */ ++ regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8, ++ RG_XFI_PLL_ANA_SWWA); ++ ++ regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val); ++ val |= RG_XFI_PLL_EN; ++ regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val); ++} ++ ++static void mtk_usxgmii_reset(struct mtk_eth_priv *priv) ++{ ++ switch (priv->gmac_id) { ++ case 1: ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004); ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); ++ break; ++ case 2: ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002); ++ regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000); ++ regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000); ++ break; ++ } ++ ++ mdelay(10); ++} ++ ++static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) ++{ ++ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D); ++ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000); ++ ++ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); ++ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); ++ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); ++ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); ++ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); ++ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); ++ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); ++ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); ++ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); ++ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); ++ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); ++ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); ++ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); ++ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); ++ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); ++ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); ++ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); ++ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); ++ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); ++ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); ++ udelay(150); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); ++ udelay(15); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); ++ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) ++{ ++ regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); ++ regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); ++ ndelay(1020); ++ regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); ++ ndelay(1020); ++ ++ regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); ++ regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); ++ regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); ++ regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); ++ regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); ++ regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); ++ regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); ++ regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); ++ regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); ++ regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); ++ regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); ++ regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); ++ regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); ++ regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); ++ regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); ++ regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); ++ regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); ++ regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); ++ regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); ++ regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); ++ regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); ++ regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); ++ regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); ++ if (priv->gmac_id == 2) ++ regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); ++ regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); ++ regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); ++ udelay(150); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); ++ udelay(15); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); ++ regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); ++ regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) ++{ ++ mtk_xfi_pll_enable(priv); ++ mtk_usxgmii_reset(priv); ++ mtk_usxgmii_setup_phya_an_10000(priv); ++} ++ ++static void mtk_10gbaser_init(struct mtk_eth_priv *priv) ++{ ++ mtk_xfi_pll_enable(priv); ++ mtk_usxgmii_reset(priv); ++ mtk_usxgmii_setup_phya_force_10000(priv); ++} ++ ++static int mtk_mac_init(struct mtk_eth_priv *priv) ++{ ++ int i, sgmii_sel_mask = 0, ge_mode = 0; ++ u32 mcr; ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { ++ mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, ++ INFRA_MISC2_BONDING_OPTION, priv->gmac_id); ++ } ++ ++ switch (priv->phy_interface) { ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ case PHY_INTERFACE_MODE_RGMII: ++ ge_mode = GE_MODE_RGMII; ++ break; ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { ++ printf("Error: SGMII is not supported on this platform\n"); ++ return -ENOTSUPP; ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { ++ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, ++ SGMII_QPHY_SEL); ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) ++ sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; ++ ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, ++ SYSCFG1_SGMII_SEL(priv->gmac_id)); ++ ++ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) ++ mtk_sgmii_an_init(priv); ++ else ++ mtk_sgmii_force_init(priv); ++ ++ ge_mode = GE_MODE_RGMII; ++ break; ++ case PHY_INTERFACE_MODE_MII: ++ case PHY_INTERFACE_MODE_GMII: ++ ge_mode = GE_MODE_MII; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ ge_mode = GE_MODE_RMII; ++ break; ++ default: ++ break; ++ } ++ ++ /* set the gmac to the right mode */ ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, ++ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), ++ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); ++ ++ if (priv->force_mode) { ++ mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | ++ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | ++ MAC_MODE | FORCE_MODE | ++ MAC_TX_EN | MAC_RX_EN | ++ BKOFF_EN | BACKPR_EN | ++ FORCE_LINK; ++ ++ switch (priv->speed) { ++ case SPEED_10: ++ mcr |= SPEED_10M << FORCE_SPD_S; ++ break; ++ case SPEED_100: ++ mcr |= SPEED_100M << FORCE_SPD_S; ++ break; ++ case SPEED_1000: ++ case SPEED_2500: ++ mcr |= SPEED_1000M << FORCE_SPD_S; ++ break; ++ } ++ ++ if (priv->duplex) ++ mcr |= FORCE_DPX; ++ ++ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) && ++ !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) { ++ /* Lower Tx Driving for TRGMII path */ ++ for (i = 0 ; i < NUM_TRGMII_CTRL; i++) ++ mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), ++ (8 << TD_DM_DRVP_S) | ++ (8 << TD_DM_DRVN_S)); ++ ++ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, ++ RX_RST | RXC_DQSISEL); ++ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); ++ } ++ ++ return 0; ++} ++ ++static int mtk_xmac_init(struct mtk_eth_priv *priv) ++{ ++ u32 force_link = 0; ++ ++ if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { ++ printf("Error: 10Gb interface is not supported on this platform\n"); ++ return -ENOTSUPP; ++ } ++ ++ switch (priv->phy_interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ mtk_usxgmii_an_init(priv); ++ break; ++ case PHY_INTERFACE_MODE_10GBASER: ++ mtk_10gbaser_init(priv); ++ break; ++ default: ++ break; ++ } ++ ++ /* Set GMAC to the correct mode */ ++ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, ++ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), ++ 0); ++ ++ if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && ++ priv->gmac_id == 1) { ++ mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, ++ NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); ++ } ++ ++ if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII || ++ priv->gmac_id == 2) ++ force_link = XGMAC_FORCE_LINK(priv->gmac_id); ++ ++ mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id), ++ XGMAC_FORCE_LINK(priv->gmac_id), force_link); ++ ++ /* Force GMAC link down */ ++ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); ++ ++ return 0; ++} ++ ++static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) ++{ ++ char *pkt_base = priv->pkt_pool; ++ struct mtk_tx_dma_v2 *txd; ++ struct mtk_rx_dma_v2 *rxd; ++ int i; ++ ++ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); ++ udelay(500); ++ ++ memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); ++ memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); ++ memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); ++ ++ flush_dcache_range((ulong)pkt_base, ++ (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); ++ ++ priv->rx_dma_owner_idx0 = 0; ++ priv->tx_cpu_owner_idx0 = 0; ++ ++ for (i = 0; i < NUM_TX_DESC; i++) { ++ txd = priv->tx_ring_noc + i * priv->soc->txd_size; ++ ++ txd->txd1 = virt_to_phys(pkt_base); ++ txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ? ++ 15 : priv->gmac_id + 1); ++ else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2)) ++ txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1); ++ else ++ txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1); ++ ++ pkt_base += PKTSIZE_ALIGN; ++ } ++ ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; ++ ++ rxd->rxd1 = virt_to_phys(pkt_base); ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); ++ else ++ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); ++ ++ pkt_base += PKTSIZE_ALIGN; ++ } ++ ++ mtk_pdma_write(priv, TX_BASE_PTR_REG(0), ++ virt_to_phys(priv->tx_ring_noc)); ++ mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); ++ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); ++ ++ mtk_pdma_write(priv, RX_BASE_PTR_REG(0), ++ virt_to_phys(priv->rx_ring_noc)); ++ mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); ++ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); ++ ++ mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); ++} ++ ++static void mtk_eth_mdc_init(struct mtk_eth_priv *priv) ++{ ++ u32 divider; ++ ++ if (priv->mdc == 0) ++ return; ++ ++ divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER); ++ ++ /* Configure MDC turbo mode */ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO); ++ else ++ mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO); ++ ++ /* Configure MDC divider */ ++ mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG, ++ FIELD_PREP(PHY_MDC_CFG, divider)); ++} ++ ++static int mtk_eth_start(struct udevice *dev) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ int i, ret; ++ ++ /* Reset FE */ ++ reset_assert(&priv->rst_fe); ++ udelay(1000); ++ reset_deassert(&priv->rst_fe); ++ mdelay(10); ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2); ++ ++ /* Packets forward to PDMA */ ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); ++ ++ for (i = 0; i < priv->soc->gdma_count; i++) { ++ if (i == priv->gmac_id) ++ continue; ++ ++ mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) { ++ if (priv->swpriv && !strcmp(priv->swpriv->sw->name, "mt7988") && ++ priv->gmac_id == 0) { ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, ++ GDMA_BRIDGE_TO_CPU); ++ ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, ++ GDMA_CPU_BRIDGE_EN); ++ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || ++ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && ++ priv->gmac_id != 0) { ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, ++ GDMA_CPU_BRIDGE_EN); ++ } ++ } ++ ++ udelay(500); ++ ++ mtk_eth_fifo_init(priv); ++ ++ if (priv->swpriv) { ++ /* Enable communication with switch */ ++ if (priv->swpriv->sw->mac_control) ++ priv->swpriv->sw->mac_control(priv->swpriv, true); ++ } else { ++ /* Start PHY */ ++ ret = mtk_phy_start(priv); ++ if (ret) ++ return ret; ++ } ++ ++ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, ++ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); ++ udelay(500); ++ ++ return 0; ++} ++ ++static void mtk_eth_stop(struct udevice *dev) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ ++ if (priv->swpriv) { ++ if (priv->swpriv->sw->mac_control) ++ priv->swpriv->sw->mac_control(priv->swpriv, false); ++ } ++ ++ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, ++ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); ++ udelay(500); ++ ++ wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG, ++ RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); ++} ++ ++static int mtk_eth_write_hwaddr(struct udevice *dev) ++{ ++ struct eth_pdata *pdata = dev_get_plat(dev); ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ unsigned char *mac = pdata->enetaddr; ++ u32 macaddr_lsb, macaddr_msb; ++ ++ macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1]; ++ macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) | ++ ((u32)mac[4] << 8) | (u32)mac[5]; ++ ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); ++ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); ++ ++ return 0; ++} ++ ++static int mtk_eth_send(struct udevice *dev, void *packet, int length) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ u32 idx = priv->tx_cpu_owner_idx0; ++ struct mtk_tx_dma_v2 *txd; ++ void *pkt_base; ++ ++ txd = priv->tx_ring_noc + idx * priv->soc->txd_size; ++ ++ if (!(txd->txd2 & PDMA_TXD2_DDONE)) { ++ debug("mtk-eth: TX DMA descriptor ring is full\n"); ++ return -EPERM; ++ } ++ ++ pkt_base = (void *)phys_to_virt(txd->txd1); ++ memcpy(pkt_base, packet, length); ++ flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + ++ roundup(length, ARCH_DMA_MINALIGN)); ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length); ++ else ++ txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length); ++ ++ priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; ++ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); ++ ++ return 0; ++} ++ ++static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ u32 idx = priv->rx_dma_owner_idx0; ++ struct mtk_rx_dma_v2 *rxd; ++ uchar *pkt_base; ++ u32 length; ++ ++ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; ++ ++ if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { ++ debug("mtk-eth: RX DMA descriptor ring is empty\n"); ++ return -EAGAIN; ++ } ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2); ++ else ++ length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2); ++ ++ pkt_base = (void *)phys_to_virt(rxd->rxd1); ++ invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + ++ roundup(length, ARCH_DMA_MINALIGN)); ++ ++ if (packetp) ++ *packetp = pkt_base; ++ ++ return length; ++} ++ ++static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ u32 idx = priv->rx_dma_owner_idx0; ++ struct mtk_rx_dma_v2 *rxd; ++ ++ rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; ++ ++ invalidate_dcache_range((ulong)rxd->rxd1, ++ (ulong)rxd->rxd1 + PKTSIZE_ALIGN); ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || ++ MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) ++ rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); ++ else ++ rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN); ++ ++ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); ++ priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; ++ ++ return 0; ++} ++ ++static int mtk_eth_probe(struct udevice *dev) ++{ ++ struct eth_pdata *pdata = dev_get_plat(dev); ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ ulong iobase = pdata->iobase; ++ int ret; ++ ++ /* Frame Engine Register Base */ ++ priv->fe_base = (void *)iobase; ++ ++ /* GMAC Register Base */ ++ priv->gmac_base = (void *)(iobase + GMAC_BASE); ++ ++ /* MDIO register */ ++ ret = mtk_mdio_register(dev); ++ if (ret) ++ return ret; ++ ++ /* Prepare for tx/rx rings */ ++ priv->tx_ring_noc = (void *) ++ noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, ++ ARCH_DMA_MINALIGN); ++ priv->rx_ring_noc = (void *) ++ noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, ++ ARCH_DMA_MINALIGN); ++ ++ /* Set MDC divider */ ++ mtk_eth_mdc_init(priv); ++ ++ /* Set MAC mode */ ++ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || ++ priv->phy_interface == PHY_INTERFACE_MODE_XGMII) ++ ret = mtk_xmac_init(priv); ++ else ++ ret = mtk_mac_init(priv); ++ ++ if (ret) ++ return ret; ++ ++ /* Probe phy if switch is not specified */ ++ if (!priv->swname) ++ return mtk_phy_probe(dev); ++ ++ /* Initialize switch */ ++ return mtk_switch_init(priv); ++} ++ ++static int mtk_eth_remove(struct udevice *dev) ++{ ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ ++ /* MDIO unregister */ ++ mdio_unregister(priv->mdio_bus); ++ mdio_free(priv->mdio_bus); ++ ++ /* Stop possibly started DMA */ ++ mtk_eth_stop(dev); ++ ++ if (priv->swpriv) { ++ if (priv->swpriv->sw->cleanup) ++ priv->swpriv->sw->cleanup(priv->swpriv); ++ free(priv->swpriv); ++ } ++ ++ return 0; ++} ++ ++static int mtk_eth_of_to_plat(struct udevice *dev) ++{ ++ struct eth_pdata *pdata = dev_get_plat(dev); ++ struct mtk_eth_priv *priv = dev_get_priv(dev); ++ struct ofnode_phandle_args args; ++ struct regmap *regmap; ++ ofnode subnode; ++ int ret; ++ ++ priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev); ++ if (!priv->soc) { ++ dev_err(dev, "missing soc compatible data\n"); ++ return -EINVAL; ++ } ++ ++ pdata->iobase = (phys_addr_t)dev_remap_addr(dev); ++ ++ /* get corresponding ethsys phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0, ++ &args); ++ if (ret) ++ return ret; ++ ++ priv->ethsys_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->ethsys_regmap)) ++ return PTR_ERR(priv->ethsys_regmap); ++ ++ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) { ++ /* get corresponding infracfg phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg", ++ NULL, 0, 0, &args); ++ ++ if (ret) ++ return ret; ++ ++ priv->infra_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->infra_regmap)) ++ return PTR_ERR(priv->infra_regmap); ++ } ++ ++ /* Reset controllers */ ++ ret = reset_get_by_name(dev, "fe", &priv->rst_fe); ++ if (ret) { ++ printf("error: Unable to get reset ctrl for frame engine\n"); ++ return ret; ++ } ++ ++ priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); ++ ++ priv->mdc = 0; ++ subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio"); ++ if (ofnode_valid(subnode)) { ++ priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000); ++ if (priv->mdc > MDC_MAX_FREQ || ++ priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { ++ printf("error: MDIO clock frequency out of range\n"); ++ return -EINVAL; ++ } ++ } ++ ++ /* Interface mode is required */ ++ pdata->phy_interface = dev_read_phy_mode(dev); ++ priv->phy_interface = pdata->phy_interface; ++ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { ++ printf("error: phy-mode is not set\n"); ++ return -EINVAL; ++ } ++ ++ /* Force mode or autoneg */ ++ subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link"); ++ if (ofnode_valid(subnode)) { ++ priv->force_mode = 1; ++ priv->speed = ofnode_read_u32_default(subnode, "speed", 0); ++ priv->duplex = ofnode_read_bool(subnode, "full-duplex"); ++ ++ if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && ++ priv->speed != SPEED_1000 && priv->speed != SPEED_2500 && ++ priv->speed != SPEED_10000) { ++ printf("error: no valid speed set in fixed-link\n"); ++ return -EINVAL; ++ } ++ } ++ ++ if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && ++ IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { ++ /* get corresponding sgmii phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ regmap = syscon_node_to_regmap(args.node); ++ ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ priv->sgmii_base = regmap_get_range(regmap, 0); ++ ++ if (!priv->sgmii_base) { ++ dev_err(dev, "Unable to find sgmii\n"); ++ return -ENODEV; ++ } ++ ++ /* Upstream linux use mediatek,pnswap instead of pn_swap */ ++ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ++ ofnode_read_bool(args.node, "mediatek,pnswap"); ++ } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || ++ priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && ++ IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { ++ /* get corresponding usxgmii phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->usxgmii_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->usxgmii_regmap)) ++ return PTR_ERR(priv->usxgmii_regmap); ++ ++ /* get corresponding xfi_pextp phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->xfi_pextp_regmap)) ++ return PTR_ERR(priv->xfi_pextp_regmap); ++ ++ /* get corresponding xfi_pll phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->xfi_pll_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->xfi_pll_regmap)) ++ return PTR_ERR(priv->xfi_pll_regmap); ++ ++ /* get corresponding toprgu phandle */ ++ ret = dev_read_phandle_with_args(dev, "mediatek,toprgu", ++ NULL, 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ priv->toprgu_regmap = syscon_node_to_regmap(args.node); ++ if (IS_ERR(priv->toprgu_regmap)) ++ return PTR_ERR(priv->toprgu_regmap); ++ } ++ ++ priv->swname = dev_read_string(dev, "mediatek,switch"); ++ if (priv->swname) { ++ priv->mcm = dev_read_bool(dev, "mediatek,mcm"); ++ if (priv->mcm) { ++ ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); ++ if (ret) { ++ printf("error: no reset ctrl for mcm\n"); ++ return ret; ++ } ++ } else { ++ gpio_request_by_name(dev, "reset-gpios", 0, ++ &priv->rst_gpio, GPIOD_IS_OUT); ++ } ++ } else { ++ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, ++ 0, &args); ++ if (ret) { ++ printf("error: phy-handle is not specified\n"); ++ return ret; ++ } ++ ++ priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); ++ if (priv->phy_addr < 0) { ++ printf("error: phy address is not specified\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct mtk_soc_data mt7988_data = { ++ .caps = MT7988_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 3, ++ .pdma_base = PDMA_V3_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++}; ++ ++static const struct mtk_soc_data mt7986_data = { ++ .caps = MT7986_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V2_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++}; ++ ++static const struct mtk_soc_data mt7981_data = { ++ .caps = MT7981_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V2_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++}; ++ ++static const struct mtk_soc_data mt7629_data = { ++ .caps = MT7629_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V1_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma), ++ .rxd_size = sizeof(struct mtk_rx_dma), ++}; ++ ++static const struct mtk_soc_data mt7623_data = { ++ .caps = MT7623_CAPS, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V1_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma), ++ .rxd_size = sizeof(struct mtk_rx_dma), ++}; ++ ++static const struct mtk_soc_data mt7622_data = { ++ .caps = MT7622_CAPS, ++ .ana_rgc3 = 0x2028, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V1_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma), ++ .rxd_size = sizeof(struct mtk_rx_dma), ++}; ++ ++static const struct mtk_soc_data mt7621_data = { ++ .caps = MT7621_CAPS, ++ .gdma_count = 2, ++ .pdma_base = PDMA_V1_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma), ++ .rxd_size = sizeof(struct mtk_rx_dma), ++}; ++ ++static const struct udevice_id mtk_eth_ids[] = { ++ { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, ++ { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, ++ { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, ++ { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, ++ { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data }, ++ { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data }, ++ { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data }, ++ {} ++}; ++ ++static const struct eth_ops mtk_eth_ops = { ++ .start = mtk_eth_start, ++ .stop = mtk_eth_stop, ++ .send = mtk_eth_send, ++ .recv = mtk_eth_recv, ++ .free_pkt = mtk_eth_free_pkt, ++ .write_hwaddr = mtk_eth_write_hwaddr, ++}; ++ ++U_BOOT_DRIVER(mtk_eth) = { ++ .name = "mtk-eth", ++ .id = UCLASS_ETH, ++ .of_match = mtk_eth_ids, ++ .of_to_plat = mtk_eth_of_to_plat, ++ .plat_auto = sizeof(struct eth_pdata), ++ .probe = mtk_eth_probe, ++ .remove = mtk_eth_remove, ++ .ops = &mtk_eth_ops, ++ .priv_auto = sizeof(struct mtk_eth_priv), ++ .flags = DM_FLAG_ALLOC_PRIV_DMA, ++}; +--- a/drivers/net/mtk_eth.h ++++ /dev/null +@@ -1,600 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * Copyright (C) 2018 MediaTek Inc. +- * +- * Author: Weijie Gao <weijie.gao@mediatek.com> +- * Author: Mark Lee <mark-mc.lee@mediatek.com> +- */ +- +-#ifndef _MTK_ETH_H_ +-#define _MTK_ETH_H_ +- +-#include <linux/bitops.h> +-#include <linux/bitfield.h> +- +-enum mkt_eth_capabilities { +- MTK_TRGMII_BIT, +- MTK_TRGMII_MT7621_CLK_BIT, +- MTK_U3_COPHY_V2_BIT, +- MTK_INFRA_BIT, +- MTK_NETSYS_V2_BIT, +- MTK_NETSYS_V3_BIT, +- +- /* PATH BITS */ +- MTK_ETH_PATH_GMAC1_TRGMII_BIT, +- MTK_ETH_PATH_GMAC2_SGMII_BIT, +- MTK_ETH_PATH_MT7622_SGMII_BIT, +- MTK_ETH_PATH_MT7629_GMAC2_BIT, +-}; +- +-#define MTK_TRGMII BIT(MTK_TRGMII_BIT) +-#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) +-#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +-#define MTK_INFRA BIT(MTK_INFRA_BIT) +-#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) +-#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) +- +-/* Supported path present on SoCs */ +-#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) +- +-#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +-#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) +-#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) +- +-#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +- +-#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) +- +-#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) +- +-#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) +- +-#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) +- +-#define MT7623_CAPS (MTK_GMAC1_TRGMII) +- +-#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) +- +-#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) +- +-#define MT7986_CAPS (MTK_NETSYS_V2) +- +-#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) +- +-/* Frame Engine Register Bases */ +-#define PDMA_V1_BASE 0x0800 +-#define PDMA_V2_BASE 0x6000 +-#define PDMA_V3_BASE 0x6800 +-#define GDMA1_BASE 0x0500 +-#define GDMA2_BASE 0x1500 +-#define GDMA3_BASE 0x0540 +-#define GMAC_BASE 0x10000 +-#define GSW_BASE 0x20000 +- +-/* Ethernet subsystem registers */ +- +-#define ETHSYS_SYSCFG1_REG 0x14 +-#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) +-#define SYSCFG1_GE_MODE_M 0x3 +-#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) +-#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) +- +-#define ETHSYS_CLKCFG0_REG 0x2c +-#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) +- +-/* Top misc registers */ +-#define TOPMISC_NETSYS_PCS_MUX 0x84 +-#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) +-#define MUX_G2_USXGMII_SEL BIT(1) +-#define MUX_HSGMII1_G1_SEL BIT(0) +- +-#define USB_PHY_SWITCH_REG 0x218 +-#define QPHY_SEL_MASK 0x3 +-#define SGMII_QPHY_SEL 0x2 +- +-#define MT7629_INFRA_MISC2_REG 0x70c +-#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) +- +-/* SYSCFG1_GE_MODE: GE Modes */ +-#define GE_MODE_RGMII 0 +-#define GE_MODE_MII 1 +-#define GE_MODE_MII_PHY 2 +-#define GE_MODE_RMII 3 +- +-/* SGMII subsystem config registers */ +-#define SGMSYS_PCS_CONTROL_1 0x0 +-#define SGMII_LINK_STATUS BIT(18) +-#define SGMII_AN_ENABLE BIT(12) +-#define SGMII_AN_RESTART BIT(9) +- +-#define SGMSYS_SGMII_MODE 0x20 +-#define SGMII_AN_MODE 0x31120103 +-#define SGMII_FORCE_MODE 0x31120019 +- +-#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 +-#define SGMII_PHYA_PWD BIT(4) +- +-#define SGMSYS_QPHY_WRAP_CTRL 0xec +-#define SGMII_PN_SWAP_TX_RX 0x03 +- +-#define SGMSYS_GEN2_SPEED 0x2028 +-#define SGMSYS_GEN2_SPEED_V2 0x128 +-#define SGMSYS_SPEED_MASK GENMASK(3, 2) +-#define SGMSYS_SPEED_2500 1 +- +-/* USXGMII subsystem config registers */ +-/* Register to control USXGMII XFI PLL digital */ +-#define XFI_PLL_DIG_GLB8 0x08 +-#define RG_XFI_PLL_EN BIT(31) +- +-/* Register to control USXGMII XFI PLL analog */ +-#define XFI_PLL_ANA_GLB8 0x108 +-#define RG_XFI_PLL_ANA_SWWA 0x02283248 +- +-/* Frame Engine Registers */ +-#define PSE_NO_DROP_CFG_REG 0x108 +-#define PSE_NO_DROP_GDM1 BIT(1) +- +-#define FE_GLO_MISC_REG 0x124 +-#define PDMA_VER_V2 BIT(4) +- +-/* PDMA */ +-#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) +-#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) +-#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) +-#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) +- +-#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) +-#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) +-#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) +-#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) +- +-#define PDMA_GLO_CFG_REG 0x204 +-#define TX_WB_DDONE BIT(6) +-#define RX_DMA_BUSY BIT(3) +-#define RX_DMA_EN BIT(2) +-#define TX_DMA_BUSY BIT(1) +-#define TX_DMA_EN BIT(0) +- +-#define PDMA_RST_IDX_REG 0x208 +-#define RST_DRX_IDX0 BIT(16) +-#define RST_DTX_IDX0 BIT(0) +- +-/* GDMA */ +-#define GDMA_IG_CTRL_REG 0x000 +-#define GDM_ICS_EN BIT(22) +-#define GDM_TCS_EN BIT(21) +-#define GDM_UCS_EN BIT(20) +-#define STRP_CRC BIT(16) +-#define MYMAC_DP_S 12 +-#define MYMAC_DP_M 0xf000 +-#define BC_DP_S 8 +-#define BC_DP_M 0xf00 +-#define MC_DP_S 4 +-#define MC_DP_M 0xf0 +-#define UN_DP_S 0 +-#define UN_DP_M 0x0f +- +-#define GDMA_EG_CTRL_REG 0x004 +-#define GDMA_CPU_BRIDGE_EN BIT(31) +- +-#define GDMA_MAC_LSB_REG 0x008 +- +-#define GDMA_MAC_MSB_REG 0x00c +- +-/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ +-#define DP_PDMA 0 +-#define DP_GDMA1 1 +-#define DP_GDMA2 2 +-#define DP_PPE 4 +-#define DP_QDMA 5 +-#define DP_DISCARD 7 +- +-/* GMAC Registers */ +- +-#define GMAC_PPSC_REG 0x0000 +-#define PHY_MDC_CFG GENMASK(29, 24) +-#define MDC_TURBO BIT(20) +-#define MDC_MAX_FREQ 25000000 +-#define MDC_MAX_DIVIDER 63 +- +-#define GMAC_PIAC_REG 0x0004 +-#define PHY_ACS_ST BIT(31) +-#define MDIO_REG_ADDR_S 25 +-#define MDIO_REG_ADDR_M 0x3e000000 +-#define MDIO_PHY_ADDR_S 20 +-#define MDIO_PHY_ADDR_M 0x1f00000 +-#define MDIO_CMD_S 18 +-#define MDIO_CMD_M 0xc0000 +-#define MDIO_ST_S 16 +-#define MDIO_ST_M 0x30000 +-#define MDIO_RW_DATA_S 0 +-#define MDIO_RW_DATA_M 0xffff +- +-#define GMAC_XGMAC_STS_REG 0x000c +-#define P1_XGMAC_FORCE_LINK BIT(15) +- +-#define GMAC_MAC_MISC_REG 0x0010 +-#define MISC_MDC_TURBO BIT(4) +- +-#define GMAC_GSW_CFG_REG 0x0080 +-#define GSWTX_IPG_M 0xF0000 +-#define GSWTX_IPG_S 16 +-#define GSWRX_IPG_M 0xF +-#define GSWRX_IPG_S 0 +- +-/* MDIO_CMD: MDIO commands */ +-#define MDIO_CMD_ADDR 0 +-#define MDIO_CMD_WRITE 1 +-#define MDIO_CMD_READ 2 +-#define MDIO_CMD_READ_C45 3 +- +-/* MDIO_ST: MDIO start field */ +-#define MDIO_ST_C45 0 +-#define MDIO_ST_C22 1 +- +-#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) +-#define MAC_RX_PKT_LEN_S 24 +-#define MAC_RX_PKT_LEN_M 0x3000000 +-#define IPG_CFG_S 18 +-#define IPG_CFG_M 0xc0000 +-#define MAC_MODE BIT(16) +-#define FORCE_MODE BIT(15) +-#define MAC_TX_EN BIT(14) +-#define MAC_RX_EN BIT(13) +-#define DEL_RXFIFO_CLR BIT(12) +-#define BKOFF_EN BIT(9) +-#define BACKPR_EN BIT(8) +-#define FORCE_RX_FC BIT(5) +-#define FORCE_TX_FC BIT(4) +-#define FORCE_SPD_S 2 +-#define FORCE_SPD_M 0x0c +-#define FORCE_DPX BIT(1) +-#define FORCE_LINK BIT(0) +- +-/* Values of IPG_CFG */ +-#define IPG_96BIT 0 +-#define IPG_96BIT_WITH_SHORT_IPG 1 +-#define IPG_64BIT 2 +- +-/* MAC_RX_PKT_LEN: Max RX packet length */ +-#define MAC_RX_PKT_LEN_1518 0 +-#define MAC_RX_PKT_LEN_1536 1 +-#define MAC_RX_PKT_LEN_1552 2 +-#define MAC_RX_PKT_LEN_JUMBO 3 +- +-/* FORCE_SPD: Forced link speed */ +-#define SPEED_10M 0 +-#define SPEED_100M 1 +-#define SPEED_1000M 2 +- +-#define GMAC_TRGMII_RCK_CTRL 0x300 +-#define RX_RST BIT(31) +-#define RXC_DQSISEL BIT(30) +- +-#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) +-#define TD_DM_DRVN_S 4 +-#define TD_DM_DRVN_M 0xf0 +-#define TD_DM_DRVP_S 0 +-#define TD_DM_DRVP_M 0x0f +- +-/* XGMAC Status Registers */ +-#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) +-#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15)) +- +-/* XGMAC Registers */ +-#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) +-#define XGMAC_TRX_DISABLE 0xf +-#define XGMAC_FORCE_TX_FC BIT(5) +-#define XGMAC_FORCE_RX_FC BIT(4) +- +-/* MT7530 Registers */ +- +-#define PCR_REG(p) (0x2004 + (p) * 0x100) +-#define PORT_MATRIX_S 16 +-#define PORT_MATRIX_M 0xff0000 +- +-#define PVC_REG(p) (0x2010 + (p) * 0x100) +-#define STAG_VPID_S 16 +-#define STAG_VPID_M 0xffff0000 +-#define VLAN_ATTR_S 6 +-#define VLAN_ATTR_M 0xc0 +- +-/* VLAN_ATTR: VLAN attributes */ +-#define VLAN_ATTR_USER 0 +-#define VLAN_ATTR_STACK 1 +-#define VLAN_ATTR_TRANSLATION 2 +-#define VLAN_ATTR_TRANSPARENT 3 +- +-#define PMCR_REG(p) (0x3000 + (p) * 0x100) +-/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR +- * MT7531 specific fields are defined below +- */ +-#define FORCE_MODE_EEE1G BIT(25) +-#define FORCE_MODE_EEE100 BIT(26) +-#define FORCE_MODE_TX_FC BIT(27) +-#define FORCE_MODE_RX_FC BIT(28) +-#define FORCE_MODE_DPX BIT(29) +-#define FORCE_MODE_SPD BIT(30) +-#define FORCE_MODE_LNK BIT(31) +-#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\ +- FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ +- FORCE_MODE_DPX | FORCE_MODE_SPD | \ +- FORCE_MODE_LNK +-#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ +- FORCE_MODE_DPX | FORCE_MODE_SPD | \ +- FORCE_MODE_LNK +- +-/* MT7531 SGMII Registers */ +-#define MT7531_SGMII_REG_BASE 0x5000 +-#define MT7531_SGMII_REG_PORT_BASE 0x1000 +-#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ +- (p) * MT7531_SGMII_REG_PORT_BASE + (r)) +-#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) +-#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) +-#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) +-#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) +-/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ +- +-/* MT753x System Control Register */ +-#define SYS_CTRL_REG 0x7000 +-#define SW_PHY_RST BIT(2) +-#define SW_SYS_RST BIT(1) +-#define SW_REG_RST BIT(0) +- +-/* MT7531 */ +-#define MT7531_PHY_IAC 0x701c +-/* XXX: all fields are defined under GMAC_PIAC_REG */ +- +-#define MT7531_CLKGEN_CTRL 0x7500 +-#define CLK_SKEW_OUT_S 8 +-#define CLK_SKEW_OUT_M 0x300 +-#define CLK_SKEW_IN_S 6 +-#define CLK_SKEW_IN_M 0xc0 +-#define RXCLK_NO_DELAY BIT(5) +-#define TXCLK_NO_REVERSE BIT(4) +-#define GP_MODE_S 1 +-#define GP_MODE_M 0x06 +-#define GP_CLK_EN BIT(0) +- +-/* Values of GP_MODE */ +-#define GP_MODE_RGMII 0 +-#define GP_MODE_MII 1 +-#define GP_MODE_REV_MII 2 +- +-/* Values of CLK_SKEW_IN */ +-#define CLK_SKEW_IN_NO_CHANGE 0 +-#define CLK_SKEW_IN_DELAY_100PPS 1 +-#define CLK_SKEW_IN_DELAY_200PPS 2 +-#define CLK_SKEW_IN_REVERSE 3 +- +-/* Values of CLK_SKEW_OUT */ +-#define CLK_SKEW_OUT_NO_CHANGE 0 +-#define CLK_SKEW_OUT_DELAY_100PPS 1 +-#define CLK_SKEW_OUT_DELAY_200PPS 2 +-#define CLK_SKEW_OUT_REVERSE 3 +- +-#define HWTRAP_REG 0x7800 +-/* MT7530 Modified Hardware Trap Status Registers */ +-#define MHWTRAP_REG 0x7804 +-#define CHG_TRAP BIT(16) +-#define LOOPDET_DIS BIT(14) +-#define P5_INTF_SEL_S 13 +-#define P5_INTF_SEL_M 0x2000 +-#define SMI_ADDR_S 11 +-#define SMI_ADDR_M 0x1800 +-#define XTAL_FSEL_S 9 +-#define XTAL_FSEL_M 0x600 +-#define P6_INTF_DIS BIT(8) +-#define P5_INTF_MODE_S 7 +-#define P5_INTF_MODE_M 0x80 +-#define P5_INTF_DIS BIT(6) +-#define C_MDIO_BPS BIT(5) +-#define CHIP_MODE_S 0 +-#define CHIP_MODE_M 0x0f +- +-/* P5_INTF_SEL: Interface type of Port5 */ +-#define P5_INTF_SEL_GPHY 0 +-#define P5_INTF_SEL_GMAC5 1 +- +-/* P5_INTF_MODE: Interface mode of Port5 */ +-#define P5_INTF_MODE_GMII_MII 0 +-#define P5_INTF_MODE_RGMII 1 +- +-#define MT7530_P6ECR 0x7830 +-#define P6_INTF_MODE_M 0x3 +-#define P6_INTF_MODE_S 0 +- +-/* P6_INTF_MODE: Interface mode of Port6 */ +-#define P6_INTF_MODE_RGMII 0 +-#define P6_INTF_MODE_TRGMII 1 +- +-#define NUM_TRGMII_CTRL 5 +- +-#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) +-#define RD_TAP_S 0 +-#define RD_TAP_M 0x7f +- +-#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) +-/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ +- +-/* TOP Signals Status Register */ +-#define MT7531_TOP_SIG_SR 0x780c +-#define PAD_MCM_SMI_EN BIT(0) +-#define PAD_DUAL_SGMII_EN BIT(1) +- +-/* MT7531 PLLGP Registers */ +-#define MT7531_PLLGP_EN 0x7820 +-#define EN_COREPLL BIT(2) +-#define SW_CLKSW BIT(1) +-#define SW_PLLGP BIT(0) +- +-#define MT7531_PLLGP_CR0 0x78a8 +-#define RG_COREPLL_EN BIT(22) +-#define RG_COREPLL_POSDIV_S 23 +-#define RG_COREPLL_POSDIV_M 0x3800000 +-#define RG_COREPLL_SDM_PCW_S 1 +-#define RG_COREPLL_SDM_PCW_M 0x3ffffe +-#define RG_COREPLL_SDM_PCW_CHG BIT(0) +- +-/* MT7531 RGMII and SGMII PLL clock */ +-#define MT7531_ANA_PLLGP_CR2 0x78b0 +-#define MT7531_ANA_PLLGP_CR5 0x78bc +- +-/* MT7531 GPIO GROUP IOLB SMT0 Control */ +-#define MT7531_SMT0_IOLB 0x7f04 +-#define SMT_IOLB_5_SMI_MDC_EN BIT(5) +- +-/* MT7530 GPHY MDIO Indirect Access Registers */ +-#define MII_MMD_ACC_CTL_REG 0x0d +-#define MMD_CMD_S 14 +-#define MMD_CMD_M 0xc000 +-#define MMD_DEVAD_S 0 +-#define MMD_DEVAD_M 0x1f +- +-/* MMD_CMD: MMD commands */ +-#define MMD_ADDR 0 +-#define MMD_DATA 1 +-#define MMD_DATA_RW_POST_INC 2 +-#define MMD_DATA_W_POST_INC 3 +- +-#define MII_MMD_ADDR_DATA_REG 0x0e +- +-/* MT7530 GPHY MDIO MMD Registers */ +-#define CORE_PLL_GROUP2 0x401 +-#define RG_SYSPLL_EN_NORMAL BIT(15) +-#define RG_SYSPLL_VODEN BIT(14) +-#define RG_SYSPLL_POSDIV_S 5 +-#define RG_SYSPLL_POSDIV_M 0x60 +- +-#define CORE_PLL_GROUP4 0x403 +-#define MT7531_BYPASS_MODE BIT(4) +-#define MT7531_POWER_ON_OFF BIT(5) +-#define RG_SYSPLL_DDSFBK_EN BIT(12) +-#define RG_SYSPLL_BIAS_EN BIT(11) +-#define RG_SYSPLL_BIAS_LPF_EN BIT(10) +- +-#define CORE_PLL_GROUP5 0x404 +-#define RG_LCDDS_PCW_NCPO1_S 0 +-#define RG_LCDDS_PCW_NCPO1_M 0xffff +- +-#define CORE_PLL_GROUP6 0x405 +-#define RG_LCDDS_PCW_NCPO0_S 0 +-#define RG_LCDDS_PCW_NCPO0_M 0xffff +- +-#define CORE_PLL_GROUP7 0x406 +-#define RG_LCDDS_PWDB BIT(15) +-#define RG_LCDDS_ISO_EN BIT(13) +-#define RG_LCCDS_C_S 4 +-#define RG_LCCDS_C_M 0x70 +-#define RG_LCDDS_PCW_NCPO_CHG BIT(3) +- +-#define CORE_PLL_GROUP10 0x409 +-#define RG_LCDDS_SSC_DELTA_S 0 +-#define RG_LCDDS_SSC_DELTA_M 0xfff +- +-#define CORE_PLL_GROUP11 0x40a +-#define RG_LCDDS_SSC_DELTA1_S 0 +-#define RG_LCDDS_SSC_DELTA1_M 0xfff +- +-#define CORE_GSWPLL_GRP1 0x40d +-#define RG_GSWPLL_POSDIV_200M_S 12 +-#define RG_GSWPLL_POSDIV_200M_M 0x3000 +-#define RG_GSWPLL_EN_PRE BIT(11) +-#define RG_GSWPLL_FBKDIV_200M_S 0 +-#define RG_GSWPLL_FBKDIV_200M_M 0xff +- +-#define CORE_GSWPLL_GRP2 0x40e +-#define RG_GSWPLL_POSDIV_500M_S 8 +-#define RG_GSWPLL_POSDIV_500M_M 0x300 +-#define RG_GSWPLL_FBKDIV_500M_S 0 +-#define RG_GSWPLL_FBKDIV_500M_M 0xff +- +-#define CORE_TRGMII_GSW_CLK_CG 0x410 +-#define REG_GSWCK_EN BIT(0) +-#define REG_TRGMIICK_EN BIT(1) +- +-/* Extend PHY Control Register 3 */ +-#define PHY_EXT_REG_14 0x14 +- +-/* Fields of PHY_EXT_REG_14 */ +-#define PHY_EN_DOWN_SHFIT BIT(4) +- +-/* Extend PHY Control Register 4 */ +-#define PHY_EXT_REG_17 0x17 +- +-/* Fields of PHY_EXT_REG_17 */ +-#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) +- +-/* PHY RXADC Control Register 7 */ +-#define PHY_DEV1E_REG_0C6 0x0c6 +- +-/* Fields of PHY_DEV1E_REG_0C6 */ +-#define PHY_POWER_SAVING_S 8 +-#define PHY_POWER_SAVING_M 0x300 +-#define PHY_POWER_SAVING_TX 0x0 +- +-/* PDMA descriptors */ +-struct mtk_rx_dma { +- unsigned int rxd1; +- unsigned int rxd2; +- unsigned int rxd3; +- unsigned int rxd4; +-} __packed __aligned(4); +- +-struct mtk_rx_dma_v2 { +- unsigned int rxd1; +- unsigned int rxd2; +- unsigned int rxd3; +- unsigned int rxd4; +- unsigned int rxd5; +- unsigned int rxd6; +- unsigned int rxd7; +- unsigned int rxd8; +-} __packed __aligned(4); +- +-struct mtk_tx_dma { +- unsigned int txd1; +- unsigned int txd2; +- unsigned int txd3; +- unsigned int txd4; +-} __packed __aligned(4); +- +-struct mtk_tx_dma_v2 { +- unsigned int txd1; +- unsigned int txd2; +- unsigned int txd3; +- unsigned int txd4; +- unsigned int txd5; +- unsigned int txd6; +- unsigned int txd7; +- unsigned int txd8; +-} __packed __aligned(4); +- +-/* PDMA TXD fields */ +-#define PDMA_TXD2_DDONE BIT(31) +-#define PDMA_TXD2_LS0 BIT(30) +-#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) +-#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) +-#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) +-#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) +- +-#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) +-#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) +-#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) +-#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) +- +-#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) +-#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) +- +-/* PDMA RXD fields */ +-#define PDMA_RXD2_DDONE BIT(31) +-#define PDMA_RXD2_LS0 BIT(30) +-#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) +-#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) +-#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) +-#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) +-#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) +-#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) +- +-#endif /* _MTK_ETH_H_ */ +--- /dev/null ++++ b/drivers/net/mtk_eth/mtk_eth.h +@@ -0,0 +1,429 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ * Author: Mark Lee <mark-mc.lee@mediatek.com> ++ */ ++ ++#ifndef _MTK_ETH_H_ ++#define _MTK_ETH_H_ ++ ++#include <linker_lists.h> ++#include <linux/bitops.h> ++#include <linux/bitfield.h> ++ ++struct mtk_eth_priv; ++struct mtk_eth_switch_priv; ++ ++/* struct mtk_soc_data - This is the structure holding all differences ++ * among various plaforms ++ * @caps Flags shown the extra capability for the SoC ++ * @ana_rgc3: The offset for register ANA_RGC3 related to ++ * sgmiisys syscon ++ * @gdma_count: Number of GDMAs ++ * @pdma_base: Register base of PDMA block ++ * @txd_size: Tx DMA descriptor size. ++ * @rxd_size: Rx DMA descriptor size. ++ */ ++struct mtk_soc_data { ++ u32 caps; ++ u32 ana_rgc3; ++ u32 gdma_count; ++ u32 pdma_base; ++ u32 txd_size; ++ u32 rxd_size; ++}; ++ ++struct mtk_eth_switch { ++ const char *name; ++ const char *desc; ++ size_t priv_size; ++ u32 reset_wait_time; ++ ++ int (*detect)(struct mtk_eth_priv *priv); ++ int (*setup)(struct mtk_eth_switch_priv *priv); ++ int (*cleanup)(struct mtk_eth_switch_priv *priv); ++ void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable); ++}; ++ ++#define MTK_ETH_SWITCH(__name) \ ++ ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch) ++ ++struct mtk_eth_switch_priv { ++ struct mtk_eth_priv *eth; ++ const struct mtk_eth_switch *sw; ++ const struct mtk_soc_data *soc; ++ void *ethsys_base; ++ int phy_interface; ++}; ++ ++enum mkt_eth_capabilities { ++ MTK_TRGMII_BIT, ++ MTK_TRGMII_MT7621_CLK_BIT, ++ MTK_U3_COPHY_V2_BIT, ++ MTK_INFRA_BIT, ++ MTK_NETSYS_V2_BIT, ++ MTK_NETSYS_V3_BIT, ++ ++ /* PATH BITS */ ++ MTK_ETH_PATH_GMAC1_TRGMII_BIT, ++ MTK_ETH_PATH_GMAC2_SGMII_BIT, ++ MTK_ETH_PATH_MT7622_SGMII_BIT, ++ MTK_ETH_PATH_MT7629_GMAC2_BIT, ++}; ++ ++#define MTK_TRGMII BIT(MTK_TRGMII_BIT) ++#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) ++#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) ++#define MTK_INFRA BIT(MTK_INFRA_BIT) ++#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) ++#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) ++ ++/* Supported path present on SoCs */ ++#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) ++#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) ++ ++#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) ++ ++#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) ++ ++#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) ++ ++#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) ++ ++#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) ++ ++#define MT7623_CAPS (MTK_GMAC1_TRGMII) ++ ++#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) ++ ++#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) ++ ++#define MT7986_CAPS (MTK_NETSYS_V2) ++ ++#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA) ++ ++#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA) ++ ++/* Frame Engine Register Bases */ ++#define PDMA_V1_BASE 0x0800 ++#define PDMA_V2_BASE 0x6000 ++#define PDMA_V3_BASE 0x6800 ++#define GDMA1_BASE 0x0500 ++#define GDMA2_BASE 0x1500 ++#define GDMA3_BASE 0x0540 ++#define GMAC_BASE 0x10000 ++#define GSW_BASE 0x20000 ++ ++/* Ethernet subsystem registers */ ++#define ETHSYS_SYSCFG1_REG 0x14 ++#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) ++#define SYSCFG1_GE_MODE_M 0x3 ++#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) ++#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) ++ ++#define ETHSYS_CLKCFG0_REG 0x2c ++#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) ++ ++/* Top misc registers */ ++#define TOPMISC_NETSYS_PCS_MUX 0x84 ++#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) ++#define MUX_G2_USXGMII_SEL BIT(1) ++#define MUX_HSGMII1_G1_SEL BIT(0) ++ ++#define USB_PHY_SWITCH_REG 0x218 ++#define QPHY_SEL_MASK 0x3 ++#define SGMII_QPHY_SEL 0x2 ++ ++#define MT7629_INFRA_MISC2_REG 0x70c ++#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) ++ ++/* SYSCFG1_GE_MODE: GE Modes */ ++#define GE_MODE_RGMII 0 ++#define GE_MODE_MII 1 ++#define GE_MODE_MII_PHY 2 ++#define GE_MODE_RMII 3 ++ ++/* SGMII subsystem config registers */ ++#define SGMSYS_PCS_CONTROL_1 0x0 ++#define SGMII_LINK_STATUS BIT(18) ++#define SGMII_AN_ENABLE BIT(12) ++#define SGMII_AN_RESTART BIT(9) ++ ++#define SGMSYS_SGMII_MODE 0x20 ++#define SGMII_AN_MODE 0x31120103 ++#define SGMII_FORCE_MODE 0x31120019 ++ ++#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 ++#define SGMII_PHYA_PWD BIT(4) ++ ++#define SGMSYS_QPHY_WRAP_CTRL 0xec ++#define SGMII_PN_SWAP_TX_RX 0x03 ++ ++#define SGMSYS_GEN2_SPEED 0x2028 ++#define SGMSYS_GEN2_SPEED_V2 0x128 ++#define SGMSYS_SPEED_MASK GENMASK(3, 2) ++#define SGMSYS_SPEED_2500 1 ++ ++/* USXGMII subsystem config registers */ ++/* Register to control USXGMII XFI PLL digital */ ++#define XFI_PLL_DIG_GLB8 0x08 ++#define RG_XFI_PLL_EN BIT(31) ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ ++/* Frame Engine Registers */ ++#define PSE_NO_DROP_CFG_REG 0x108 ++#define PSE_NO_DROP_GDM1 BIT(1) ++ ++#define FE_GLO_MISC_REG 0x124 ++#define PDMA_VER_V2 BIT(4) ++ ++/* PDMA */ ++#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) ++#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) ++#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) ++#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) ++ ++#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) ++#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) ++#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) ++#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) ++ ++#define PDMA_GLO_CFG_REG 0x204 ++#define TX_WB_DDONE BIT(6) ++#define RX_DMA_BUSY BIT(3) ++#define RX_DMA_EN BIT(2) ++#define TX_DMA_BUSY BIT(1) ++#define TX_DMA_EN BIT(0) ++ ++#define PDMA_RST_IDX_REG 0x208 ++#define RST_DRX_IDX0 BIT(16) ++#define RST_DTX_IDX0 BIT(0) ++ ++/* GDMA */ ++#define GDMA_IG_CTRL_REG 0x000 ++#define GDM_ICS_EN BIT(22) ++#define GDM_TCS_EN BIT(21) ++#define GDM_UCS_EN BIT(20) ++#define STRP_CRC BIT(16) ++#define MYMAC_DP_S 12 ++#define MYMAC_DP_M 0xf000 ++#define BC_DP_S 8 ++#define BC_DP_M 0xf00 ++#define MC_DP_S 4 ++#define MC_DP_M 0xf0 ++#define UN_DP_S 0 ++#define UN_DP_M 0x0f ++ ++#define GDMA_EG_CTRL_REG 0x004 ++#define GDMA_CPU_BRIDGE_EN BIT(31) ++ ++#define GDMA_MAC_LSB_REG 0x008 ++ ++#define GDMA_MAC_MSB_REG 0x00c ++ ++/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ ++#define DP_PDMA 0 ++#define DP_GDMA1 1 ++#define DP_GDMA2 2 ++#define DP_PPE 4 ++#define DP_QDMA 5 ++#define DP_DISCARD 7 ++ ++/* GMAC Registers */ ++#define GMAC_PPSC_REG 0x0000 ++#define PHY_MDC_CFG GENMASK(29, 24) ++#define MDC_TURBO BIT(20) ++#define MDC_MAX_FREQ 25000000 ++#define MDC_MAX_DIVIDER 63 ++ ++#define GMAC_PIAC_REG 0x0004 ++#define PHY_ACS_ST BIT(31) ++#define MDIO_REG_ADDR_S 25 ++#define MDIO_REG_ADDR_M 0x3e000000 ++#define MDIO_PHY_ADDR_S 20 ++#define MDIO_PHY_ADDR_M 0x1f00000 ++#define MDIO_CMD_S 18 ++#define MDIO_CMD_M 0xc0000 ++#define MDIO_ST_S 16 ++#define MDIO_ST_M 0x30000 ++#define MDIO_RW_DATA_S 0 ++#define MDIO_RW_DATA_M 0xffff ++ ++#define GMAC_XGMAC_STS_REG 0x000c ++#define P1_XGMAC_FORCE_LINK BIT(15) ++ ++#define GMAC_MAC_MISC_REG 0x0010 ++#define MISC_MDC_TURBO BIT(4) ++ ++#define GMAC_GSW_CFG_REG 0x0080 ++#define GSWTX_IPG_M 0xF0000 ++#define GSWTX_IPG_S 16 ++#define GSWRX_IPG_M 0xF ++#define GSWRX_IPG_S 0 ++ ++/* MDIO_CMD: MDIO commands */ ++#define MDIO_CMD_ADDR 0 ++#define MDIO_CMD_WRITE 1 ++#define MDIO_CMD_READ 2 ++#define MDIO_CMD_READ_C45 3 ++ ++/* MDIO_ST: MDIO start field */ ++#define MDIO_ST_C45 0 ++#define MDIO_ST_C22 1 ++ ++#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) ++#define MAC_RX_PKT_LEN_S 24 ++#define MAC_RX_PKT_LEN_M 0x3000000 ++#define IPG_CFG_S 18 ++#define IPG_CFG_M 0xc0000 ++#define MAC_MODE BIT(16) ++#define FORCE_MODE BIT(15) ++#define MAC_TX_EN BIT(14) ++#define MAC_RX_EN BIT(13) ++#define DEL_RXFIFO_CLR BIT(12) ++#define BKOFF_EN BIT(9) ++#define BACKPR_EN BIT(8) ++#define FORCE_RX_FC BIT(5) ++#define FORCE_TX_FC BIT(4) ++#define FORCE_SPD_S 2 ++#define FORCE_SPD_M 0x0c ++#define FORCE_DPX BIT(1) ++#define FORCE_LINK BIT(0) ++ ++/* Values of IPG_CFG */ ++#define IPG_96BIT 0 ++#define IPG_96BIT_WITH_SHORT_IPG 1 ++#define IPG_64BIT 2 ++ ++/* MAC_RX_PKT_LEN: Max RX packet length */ ++#define MAC_RX_PKT_LEN_1518 0 ++#define MAC_RX_PKT_LEN_1536 1 ++#define MAC_RX_PKT_LEN_1552 2 ++#define MAC_RX_PKT_LEN_JUMBO 3 ++ ++/* FORCE_SPD: Forced link speed */ ++#define SPEED_10M 0 ++#define SPEED_100M 1 ++#define SPEED_1000M 2 ++ ++#define GMAC_TRGMII_RCK_CTRL 0x300 ++#define RX_RST BIT(31) ++#define RXC_DQSISEL BIT(30) ++ ++#define NUM_TRGMII_CTRL 5 ++ ++#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) ++#define TD_DM_DRVN_S 4 ++#define TD_DM_DRVN_M 0xf0 ++#define TD_DM_DRVP_S 0 ++#define TD_DM_DRVP_M 0x0f ++ ++/* XGMAC Status Registers */ ++#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C) ++#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15)) ++ ++/* XGMAC Registers */ ++#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000)) ++#define XGMAC_TRX_DISABLE 0xf ++#define XGMAC_FORCE_TX_FC BIT(5) ++#define XGMAC_FORCE_RX_FC BIT(4) ++ ++/* MDIO Indirect Access Registers */ ++#define MII_MMD_ACC_CTL_REG 0x0d ++#define MMD_CMD_S 14 ++#define MMD_CMD_M 0xc000 ++#define MMD_DEVAD_S 0 ++#define MMD_DEVAD_M 0x1f ++ ++/* MMD_CMD: MMD commands */ ++#define MMD_ADDR 0 ++#define MMD_DATA 1 ++#define MMD_DATA_RW_POST_INC 2 ++#define MMD_DATA_W_POST_INC 3 ++ ++#define MII_MMD_ADDR_DATA_REG 0x0e ++ ++/* PDMA descriptors */ ++struct mtk_rx_dma { ++ unsigned int rxd1; ++ unsigned int rxd2; ++ unsigned int rxd3; ++ unsigned int rxd4; ++} __packed __aligned(4); ++ ++struct mtk_rx_dma_v2 { ++ unsigned int rxd1; ++ unsigned int rxd2; ++ unsigned int rxd3; ++ unsigned int rxd4; ++ unsigned int rxd5; ++ unsigned int rxd6; ++ unsigned int rxd7; ++ unsigned int rxd8; ++} __packed __aligned(4); ++ ++struct mtk_tx_dma { ++ unsigned int txd1; ++ unsigned int txd2; ++ unsigned int txd3; ++ unsigned int txd4; ++} __packed __aligned(4); ++ ++struct mtk_tx_dma_v2 { ++ unsigned int txd1; ++ unsigned int txd2; ++ unsigned int txd3; ++ unsigned int txd4; ++ unsigned int txd5; ++ unsigned int txd6; ++ unsigned int txd7; ++ unsigned int txd8; ++} __packed __aligned(4); ++ ++/* PDMA TXD fields */ ++#define PDMA_TXD2_DDONE BIT(31) ++#define PDMA_TXD2_LS0 BIT(30) ++#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) ++#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) ++#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) ++#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) ++ ++#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) ++#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) ++#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) ++#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) ++ ++#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) ++#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) ++ ++/* PDMA RXD fields */ ++#define PDMA_RXD2_DDONE BIT(31) ++#define PDMA_RXD2_LS0 BIT(30) ++#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) ++#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) ++#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) ++#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) ++#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) ++#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) ++ ++void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); ++void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); ++void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set); ++ ++int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg); ++int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data); ++int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); ++int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, ++ u16 val); ++int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); ++int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, ++ u16 val); ++ ++#endif /* _MTK_ETH_H_ */ diff --git a/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch b/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch new file mode 100644 index 0000000000..183c7129ab --- /dev/null +++ b/package/boot/uboot-mediatek/patches/061-02-net-mediatek-add-support-for-MediaTek-MT7987-SoC.patch @@ -0,0 +1,63 @@ +From fe106f2093733b8bd61946372945dfea552b4755 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 10 Jan 2025 16:41:20 +0800 +Subject: [PATCH 2/3] net: mediatek: add support for MediaTek MT7987 SoC + +This patch adds support for MediaTek MT7987. + +MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs +which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be +connected to a dedicated GMAC. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth/Kconfig | 4 ++-- + drivers/net/mtk_eth/mtk_eth.c | 10 ++++++++++ + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/net/mtk_eth/Kconfig ++++ b/drivers/net/mtk_eth/Kconfig +@@ -16,7 +16,7 @@ config MTK_ETH_SGMII + + config MTK_ETH_XGMII + bool +- default y if TARGET_MT7988 ++ default y if TARGET_MT7987 || TARGET_MT7988 + + config MTK_ETH_SWITCH_MT7530 + bool "Support for MediaTek MT7530 ethernet switch" +@@ -25,7 +25,7 @@ config MTK_ETH_SWITCH_MT7530 + config MTK_ETH_SWITCH_MT7531 + bool "Support for MediaTek MT7531 ethernet switch" + default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \ +- TARGET_MT7986 ++ TARGET_MT7986 || TARGET_MT7987 + + config MTK_ETH_SWITCH_MT7988 + bool "Support for MediaTek MT7988 built-in ethernet switch" +--- a/drivers/net/mtk_eth/mtk_eth.c ++++ b/drivers/net/mtk_eth/mtk_eth.c +@@ -1477,6 +1477,15 @@ static const struct mtk_soc_data mt7988_ + .rxd_size = sizeof(struct mtk_rx_dma_v2), + }; + ++static const struct mtk_soc_data mt7987_data = { ++ .caps = MT7987_CAPS, ++ .ana_rgc3 = 0x128, ++ .gdma_count = 3, ++ .pdma_base = PDMA_V3_BASE, ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++}; ++ + static const struct mtk_soc_data mt7986_data = { + .caps = MT7986_CAPS, + .ana_rgc3 = 0x128, +@@ -1531,6 +1540,7 @@ static const struct mtk_soc_data mt7621_ + + static const struct udevice_id mtk_eth_ids[] = { + { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data }, ++ { .compatible = "mediatek,mt7987-eth", .data = (ulong)&mt7987_data }, + { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data }, + { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data }, + { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data }, diff --git a/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch b/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch new file mode 100644 index 0000000000..8e4f4391b1 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/061-03-net-mediatek-add-support-for-Airoha-AN8855-ethernet-.patch @@ -0,0 +1,1133 @@ +From cedafee9ff39d13aaf8b80361b673445a85f117e Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 10 Jan 2025 16:41:24 +0800 +Subject: [PATCH 3/3] net: mediatek: add support for Airoha AN8855 ethernet + switch + +Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/net/mtk_eth/Kconfig | 4 + + drivers/net/mtk_eth/Makefile | 1 + + drivers/net/mtk_eth/an8855.c | 1096 ++++++++++++++++++++++++++++++++++ + 3 files changed, 1101 insertions(+) + create mode 100644 drivers/net/mtk_eth/an8855.c + +--- a/drivers/net/mtk_eth/Kconfig ++++ b/drivers/net/mtk_eth/Kconfig +@@ -32,4 +32,8 @@ config MTK_ETH_SWITCH_MT7988 + depends on TARGET_MT7988 + default y + ++config MTK_ETH_SWITCH_AN8855 ++ bool "Support for Airoha AN8855 ethernet switch" ++ default y if TARGET_MT7981 || TARGET_MT7987 ++ + endif # MEDIATEK_ETH +--- a/drivers/net/mtk_eth/Makefile ++++ b/drivers/net/mtk_eth/Makefile +@@ -7,3 +7,4 @@ obj-y += mtk_eth.o + obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o + obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o + obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o ++obj-$(CONFIG_MTK_ETH_SWITCH_AN8855) += an8855.o +--- /dev/null ++++ b/drivers/net/mtk_eth/an8855.c +@@ -0,0 +1,1096 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 MediaTek Inc. ++ * ++ * Author: Neal Yen <neal.yen@mediatek.com> ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include <phy.h> ++#include <miiphy.h> ++#include <linux/bitops.h> ++#include <linux/delay.h> ++#include <linux/mdio.h> ++#include <linux/mii.h> ++#include "mtk_eth.h" ++ ++/* AN8855 Register Definitions */ ++#define AN8855_SYS_CTRL_REG 0x100050c0 ++#define AN8855_SW_SYS_RST BIT(31) ++ ++#define AN8855_PMCR_REG(p) (0x10210000 + (p) * 0x200) ++#define AN8855_FORCE_MODE_LNK BIT(31) ++#define AN8855_FORCE_MODE 0xb31593f0 ++ ++#define AN8855_PORT_CTRL_BASE (0x10208000) ++#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r)) ++ ++#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44) ++ ++#define AN8855_PVC(p) AN8855_PORT_CTRL_REG(p, 0x10) ++#define AN8855_STAG_VPID_S 16 ++#define AN8855_STAG_VPID_M 0xffff0000 ++#define AN8855_VLAN_ATTR_S 6 ++#define AN8855_VLAN_ATTR_M 0xc0 ++ ++#define VLAN_ATTR_USER 0 ++ ++#define AN8855_INT_MASK 0x100050F0 ++#define AN8855_INT_SYS_BIT BIT(15) ++ ++#define AN8855_RG_CLK_CPU_ICG 0x10005034 ++#define AN8855_MCU_ENABLE BIT(3) ++ ++#define AN8855_RG_TIMER_CTL 0x1000a100 ++#define AN8855_WDOG_ENABLE BIT(25) ++ ++#define AN8855_CKGCR 0x10213e1c ++ ++#define AN8855_SCU_BASE 0x10000000 ++#define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0) ++#define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054) ++#define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4))) ++#define AN8855_RG_INTB_MODE (AN8855_SCU_BASE + 0x0080) ++#define AN8855_RG_GDMP_RAM (AN8855_SCU_BASE + 0x10000) ++#define AN8855_RG_GPIO_L_INV (AN8855_SCU_BASE + 0x0010) ++#define AN8855_RG_GPIO_CTRL (AN8855_SCU_BASE + 0xa300) ++#define AN8855_RG_GPIO_DATA (AN8855_SCU_BASE + 0xa304) ++#define AN8855_RG_GPIO_OE (AN8855_SCU_BASE + 0xa314) ++ ++#define AN8855_HSGMII_AN_CSR_BASE 0x10220000 ++#define AN8855_SGMII_REG_AN0 (AN8855_HSGMII_AN_CSR_BASE + 0x000) ++#define AN8855_SGMII_REG_AN_13 (AN8855_HSGMII_AN_CSR_BASE + 0x034) ++#define AN8855_SGMII_REG_AN_FORCE_CL37 (AN8855_HSGMII_AN_CSR_BASE + 0x060) ++ ++#define AN8855_HSGMII_CSR_PCS_BASE 0x10220000 ++#define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00) ++#define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24) ++ ++#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000 ++#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018) ++#define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100) ++#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514) ++#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c) ++#define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520) ++ ++#define AN8855_XFI_CSR_PCS_BASE 0x10225000 ++#define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8) ++ ++#define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 ++#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000) ++#define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100) ++#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300) ++ ++#define AN8855_QP_DIG_CSR_BASE 0x1022a000 ++#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310) ++#define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324) ++#define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330) ++ ++#define AN8855_QP_PMA_TOP_BASE 0x1022e000 ++#define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100) ++#define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124) ++ ++#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208) ++#define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230) ++#define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c) ++#define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248) ++#define AN8855_INTF_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x320) ++#define AN8855_INTF_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x324) ++#define AN8855_PLL_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x400) ++#define AN8855_PLL_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x408) ++#define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c) ++#define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410) ++#define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414) ++#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614) ++#define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630) ++#define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c) ++#define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640) ++#define AN8855_RX_CTRL_7 (AN8855_QP_PMA_TOP_BASE + 0x644) ++#define AN8855_RX_CTRL_8 (AN8855_QP_PMA_TOP_BASE + 0x648) ++#define AN8855_RX_CTRL_26 (AN8855_QP_PMA_TOP_BASE + 0x690) ++#define AN8855_RX_CTRL_42 (AN8855_QP_PMA_TOP_BASE + 0x6d0) ++ ++#define AN8855_QP_ANA_CSR_BASE 0x1022f000 ++#define AN8855_RG_QP_RX_DAC_EN (AN8855_QP_ANA_CSR_BASE + 0x00) ++#define AN8855_RG_QP_RXAFE_RESERVE (AN8855_QP_ANA_CSR_BASE + 0x04) ++#define AN8855_RG_QP_CDR_LPF_MJV_LIM (AN8855_QP_ANA_CSR_BASE + 0x0c) ++#define AN8855_RG_QP_CDR_LPF_SETVALUE (AN8855_QP_ANA_CSR_BASE + 0x14) ++#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18) ++#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c) ++#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20) ++#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28) ++#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c) ++#define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40) ++ ++#define AN8855_ETHER_SYS_BASE 0x1028c800 ++#define RG_GPHY_AFE_PWD (AN8855_ETHER_SYS_BASE + 0x40) ++ ++#define AN8855_PKG_SEL 0x10000094 ++#define PAG_SEL_AN8855H 0x2 ++ ++/* PHY LED Register bitmap of define */ ++#define PHY_LED_CTRL_SELECT 0x3e8 ++#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) ++#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) ++#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) ++#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) ++ ++#define PHY_PMA_CTRL (0x340) ++ ++#define PHY_DEV1F 0x1f ++ ++#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2)) ++#define LED_ON_EN (1 << 15) ++#define LED_ON_POL (1 << 14) ++#define LED_ON_EVT_MASK (0x7f) ++ ++/* LED ON Event */ ++#define LED_ON_EVT_FORCE (1 << 6) ++#define LED_ON_EVT_LINK_HD (1 << 5) ++#define LED_ON_EVT_LINK_FD (1 << 4) ++#define LED_ON_EVT_LINK_DOWN (1 << 3) ++#define LED_ON_EVT_LINK_10M (1 << 2) ++#define LED_ON_EVT_LINK_100M (1 << 1) ++#define LED_ON_EVT_LINK_1000M (1 << 0) ++ ++#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2)) ++#define LED_BLK_EVT_MASK (0x3ff) ++/* LED Blinking Event */ ++#define LED_BLK_EVT_FORCE (1 << 9) ++#define LED_BLK_EVT_10M_RX_ACT (1 << 5) ++#define LED_BLK_EVT_10M_TX_ACT (1 << 4) ++#define LED_BLK_EVT_100M_RX_ACT (1 << 3) ++#define LED_BLK_EVT_100M_TX_ACT (1 << 2) ++#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) ++#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) ++ ++#define PHY_LED_BCR (0x21) ++#define LED_BCR_EXT_CTRL (1 << 15) ++#define LED_BCR_CLK_EN (1 << 3) ++#define LED_BCR_TIME_TEST (1 << 2) ++#define LED_BCR_MODE_MASK (3) ++#define LED_BCR_MODE_DISABLE (0) ++ ++#define PHY_LED_ON_DUR (0x22) ++#define LED_ON_DUR_MASK (0xffff) ++ ++#define PHY_LED_BLK_DUR (0x23) ++#define LED_BLK_DUR_MASK (0xffff) ++ ++#define PHY_LED_BLINK_DUR_CTRL (0x720) ++ ++/* Definition of LED */ ++#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \ ++ LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M |\ ++ LED_ON_EVT_LINK_HD | LED_ON_EVT_LINK_FD) ++ ++#define LED_BLK_EVENT (LED_BLK_EVT_1000M_TX_ACT | \ ++ LED_BLK_EVT_1000M_RX_ACT | \ ++ LED_BLK_EVT_100M_TX_ACT | \ ++ LED_BLK_EVT_100M_RX_ACT | \ ++ LED_BLK_EVT_10M_TX_ACT | \ ++ LED_BLK_EVT_10M_RX_ACT) ++ ++#define LED_FREQ AIR_LED_BLK_DUR_64M ++ ++#define AN8855_NUM_PHYS 5 ++#define AN8855_NUM_PORTS 6 ++#define AN8855_PHY_ADDR(base, addr) (((base) + (addr)) & 0x1f) ++ ++/* PHY LED Register bitmap of define */ ++#define PHY_LED_CTRL_SELECT 0x3e8 ++#define PHY_SINGLE_LED_ON_CTRL(i) (0x3e0 + ((i) * 2)) ++#define PHY_SINGLE_LED_BLK_CTRL(i) (0x3e1 + ((i) * 2)) ++#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2)) ++#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2)) ++ ++/* AN8855 LED */ ++enum an8855_led_blk_dur { ++ AIR_LED_BLK_DUR_32M, ++ AIR_LED_BLK_DUR_64M, ++ AIR_LED_BLK_DUR_128M, ++ AIR_LED_BLK_DUR_256M, ++ AIR_LED_BLK_DUR_512M, ++ AIR_LED_BLK_DUR_1024M, ++ AIR_LED_BLK_DUR_LAST ++}; ++ ++enum an8855_led_polarity { ++ LED_LOW, ++ LED_HIGH, ++}; ++ ++enum an8855_led_mode { ++ AN8855_LED_MODE_DISABLE, ++ AN8855_LED_MODE_USER_DEFINE, ++ AN8855_LED_MODE_LAST ++}; ++ ++enum phy_led_idx { ++ P0_LED0, ++ P0_LED1, ++ P0_LED2, ++ P0_LED3, ++ P1_LED0, ++ P1_LED1, ++ P1_LED2, ++ P1_LED3, ++ P2_LED0, ++ P2_LED1, ++ P2_LED2, ++ P2_LED3, ++ P3_LED0, ++ P3_LED1, ++ P3_LED2, ++ P3_LED3, ++ P4_LED0, ++ P4_LED1, ++ P4_LED2, ++ P4_LED3, ++ PHY_LED_MAX ++}; ++ ++struct an8855_led_cfg { ++ u16 en; ++ u8 phy_led_idx; ++ u16 pol; ++ u16 on_cfg; ++ u16 blk_cfg; ++ u8 led_freq; ++}; ++ ++struct an8855_switch_priv { ++ struct mtk_eth_switch_priv epriv; ++ struct mii_dev *mdio_bus; ++ u32 phy_base; ++}; ++ ++/* AN8855 Reference Board */ ++static const struct an8855_led_cfg led_cfg[] = { ++/************************************************************************* ++ * Enable, LED idx, LED Polarity, LED ON event, LED Blink event LED Freq ++ ************************************************************************* ++ */ ++ /* GPIO0 */ ++ {1, P4_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO1 */ ++ {1, P4_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO2 */ ++ {1, P0_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO3 */ ++ {1, P0_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO4 */ ++ {1, P1_LED0, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO5 */ ++ {1, P1_LED1, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO6 */ ++ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO7 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO8 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO9 */ ++ {1, P2_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO10 */ ++ {1, P2_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO11 */ ++ {1, P3_LED0, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO12 */ ++ {1, P3_LED1, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO13 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO14 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO15 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO16 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO17 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO18 */ ++ {0, PHY_LED_MAX, LED_HIGH, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO19 */ ++ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++ /* GPIO20 */ ++ {0, PHY_LED_MAX, LED_LOW, LED_ON_EVENT, LED_BLK_EVENT, LED_FREQ}, ++}; ++ ++static int __an8855_reg_read(struct mtk_eth_priv *priv, u8 phy_base, u32 reg, u32 *data) ++{ ++ int ret, low_word, high_word; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x1f, 0x4); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x10, 0); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x15, ((reg >> 16) & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x16, (reg & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ low_word = mtk_mii_read(priv, phy_base, 0x18); ++ if (low_word < 0) ++ return low_word; ++ ++ high_word = mtk_mii_read(priv, phy_base, 0x17); ++ if (high_word < 0) ++ return high_word; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x1f, 0); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv, phy_base, 0x10, 0); ++ if (ret) ++ return ret; ++ ++ if (data) ++ *data = ((u32)high_word << 16) | (low_word & 0xffff); ++ ++ return 0; ++} ++ ++static int an8855_reg_read(struct an8855_switch_priv *priv, u32 reg, u32 *data) ++{ ++ return __an8855_reg_read(priv->epriv.eth, priv->phy_base, reg, data); ++} ++ ++static int an8855_reg_write(struct an8855_switch_priv *priv, u32 reg, u32 data) ++{ ++ int ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0x4); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x11, ++ ((reg >> 16) & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x12, ++ (reg & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x13, ++ ((data >> 16) & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x14, ++ (data & 0xFFFF)); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x1f, 0); ++ if (ret) ++ return ret; ++ ++ ret = mtk_mii_write(priv->epriv.eth, priv->phy_base, 0x10, 0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int an8855_phy_cl45_read(struct an8855_switch_priv *priv, int port, ++ int devad, int regnum, u16 *data) ++{ ++ u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); ++ ++ *data = mtk_mmd_ind_read(priv->epriv.eth, phy_addr, devad, regnum); ++ ++ return 0; ++} ++ ++static int an8855_phy_cl45_write(struct an8855_switch_priv *priv, int port, ++ int devad, int regnum, u16 data) ++{ ++ u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); ++ ++ mtk_mmd_ind_write(priv->epriv.eth, phy_addr, devad, regnum, data); ++ ++ return 0; ++} ++ ++static int an8855_port_sgmii_init(struct an8855_switch_priv *priv, u32 port) ++{ ++ u32 val = 0; ++ ++ if (port != 5) { ++ printf("an8855: port %d is not a SGMII port\n", port); ++ return -EINVAL; ++ } ++ ++ /* PLL */ ++ an8855_reg_read(priv, AN8855_QP_DIG_MODE_CTRL_1, &val); ++ val &= ~(0x3 << 2); ++ val |= (0x1 << 2); ++ an8855_reg_write(priv, AN8855_QP_DIG_MODE_CTRL_1, val); ++ ++ /* PLL - LPF */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val &= ~(0x3 << 0); ++ val |= (0x1 << 0); ++ val &= ~(0x7 << 2); ++ val |= (0x5 << 2); ++ val &= ~GENMASK(7, 6); ++ val &= ~(0x7 << 8); ++ val |= (0x3 << 8); ++ val |= BIT(29); ++ val &= ~GENMASK(13, 12); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ /* PLL - ICO */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); ++ val |= BIT(2); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val &= ~BIT(14); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ /* PLL - CHP */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val &= ~(0xf << 16); ++ val |= (0x6 << 16); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ /* PLL - PFD */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val &= ~(0x3 << 20); ++ val |= (0x1 << 20); ++ val &= ~(0x3 << 24); ++ val |= (0x1 << 24); ++ val &= ~BIT(26); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ /* PLL - POSTDIV */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val |= BIT(22); ++ val &= ~BIT(27); ++ val &= ~BIT(28); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ /* PLL - SDM */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); ++ val &= ~GENMASK(4, 3); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_2, &val); ++ val &= ~BIT(30); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_2, val); ++ ++ an8855_reg_read(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, &val); ++ val &= ~(0x3 << 16); ++ val |= (0x1 << 16); ++ an8855_reg_write(priv, AN8855_SS_LCPLL_PWCTL_SETTING_2, val); ++ ++ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_2, 0x7a000000); ++ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_PCW_1, 0x7a000000); ++ ++ an8855_reg_read(priv, AN8855_SS_LCPLL_TDC_FLT_5, &val); ++ val &= ~BIT(24); ++ an8855_reg_write(priv, AN8855_SS_LCPLL_TDC_FLT_5, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); ++ val &= ~BIT(8); ++ an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); ++ ++ /* PLL - SS */ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); ++ val &= ~GENMASK(15, 0); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_4, &val); ++ val &= ~GENMASK(1, 0); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_4, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_3, &val); ++ val &= ~GENMASK(31, 16); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_3, val); ++ ++ /* PLL - TDC */ ++ an8855_reg_read(priv, AN8855_PLL_CK_CTRL_0, &val); ++ val &= ~BIT(9); ++ an8855_reg_write(priv, AN8855_PLL_CK_CTRL_0, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_PLL_SDM_ORD, &val); ++ val |= BIT(3); ++ val |= BIT(4); ++ an8855_reg_write(priv, AN8855_RG_QP_PLL_SDM_ORD, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_RX_DAC_EN, &val); ++ val &= ~(0x3 << 16); ++ val |= (0x2 << 16); ++ an8855_reg_write(priv, AN8855_RG_QP_RX_DAC_EN, val); ++ ++ /* TCL Disable (only for Co-SIM) */ ++ an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_0, &val); ++ val &= ~BIT(12); ++ an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_0, val); ++ ++ /* TX Init */ ++ an8855_reg_read(priv, AN8855_RG_QP_TX_MODE_16B_EN, &val); ++ val &= ~BIT(0); ++ val &= ~(0xffff << 16); ++ val |= (0x4 << 16); ++ an8855_reg_write(priv, AN8855_RG_QP_TX_MODE_16B_EN, val); ++ ++ /* RX Control */ ++ an8855_reg_read(priv, AN8855_RG_QP_RXAFE_RESERVE, &val); ++ val |= BIT(11); ++ an8855_reg_write(priv, AN8855_RG_QP_RXAFE_RESERVE, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, &val); ++ val &= ~(0x3 << 4); ++ val |= (0x1 << 4); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_MJV_LIM, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, &val); ++ val &= ~(0xf << 25); ++ val |= (0x1 << 25); ++ val &= ~(0x7 << 29); ++ val |= (0x3 << 29); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_LPF_SETVALUE, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); ++ val &= ~(0x1f << 8); ++ val |= (0xf << 8); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); ++ val &= ~(0x3f << 0); ++ val |= (0x19 << 0); ++ val &= ~BIT(6); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, &val); ++ val &= ~(0x7f << 6); ++ val |= (0x21 << 6); ++ val &= ~(0x3 << 16); ++ val |= (0x2 << 16); ++ val &= ~BIT(13); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, &val); ++ val &= ~BIT(30); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE, val); ++ ++ an8855_reg_read(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, &val); ++ val &= ~(0x7 << 24); ++ val |= (0x4 << 24); ++ an8855_reg_write(priv, AN8855_RG_QP_CDR_PR_CKREF_DIV1, val); ++ ++ an8855_reg_read(priv, AN8855_PLL_CTRL_0, &val); ++ val |= BIT(0); ++ an8855_reg_write(priv, AN8855_PLL_CTRL_0, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_26, &val); ++ val &= ~BIT(23); ++ val |= BIT(26); ++ an8855_reg_write(priv, AN8855_RX_CTRL_26, val); ++ ++ an8855_reg_read(priv, AN8855_RX_DLY_0, &val); ++ val &= ~(0xff << 0); ++ val |= (0x6f << 0); ++ val |= GENMASK(13, 8); ++ an8855_reg_write(priv, AN8855_RX_DLY_0, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_42, &val); ++ val &= ~(0x1fff << 0); ++ val |= (0x150 << 0); ++ an8855_reg_write(priv, AN8855_RX_CTRL_42, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_2, &val); ++ val &= ~(0x1fff << 16); ++ val |= (0x150 << 16); ++ an8855_reg_write(priv, AN8855_RX_CTRL_2, val); ++ ++ an8855_reg_read(priv, AN8855_PON_RXFEDIG_CTRL_9, &val); ++ val &= ~(0x7 << 0); ++ val |= (0x1 << 0); ++ an8855_reg_write(priv, AN8855_PON_RXFEDIG_CTRL_9, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_8, &val); ++ val &= ~(0xfff << 16); ++ val |= (0x200 << 16); ++ val &= ~(0x7fff << 14); ++ val |= (0xfff << 14); ++ an8855_reg_write(priv, AN8855_RX_CTRL_8, val); ++ ++ /* Frequency memter */ ++ an8855_reg_read(priv, AN8855_RX_CTRL_5, &val); ++ val &= ~(0xfffff << 10); ++ val |= (0x10 << 10); ++ an8855_reg_write(priv, AN8855_RX_CTRL_5, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_6, &val); ++ val &= ~(0xfffff << 0); ++ val |= (0x64 << 0); ++ an8855_reg_write(priv, AN8855_RX_CTRL_6, val); ++ ++ an8855_reg_read(priv, AN8855_RX_CTRL_7, &val); ++ val &= ~(0xfffff << 0); ++ val |= (0x2710 << 0); ++ an8855_reg_write(priv, AN8855_RX_CTRL_7, val); ++ ++ /* PCS Init */ ++ an8855_reg_read(priv, AN8855_RG_HSGMII_PCS_CTROL_1, &val); ++ val &= ~BIT(30); ++ an8855_reg_write(priv, AN8855_RG_HSGMII_PCS_CTROL_1, val); ++ ++ /* Rate Adaption */ ++ an8855_reg_read(priv, AN8855_RATE_ADP_P0_CTRL_0, &val); ++ val &= ~BIT(31); ++ an8855_reg_write(priv, AN8855_RATE_ADP_P0_CTRL_0, val); ++ ++ an8855_reg_read(priv, AN8855_RG_RATE_ADAPT_CTRL_0, &val); ++ val |= BIT(0); ++ val |= BIT(4); ++ val |= GENMASK(27, 26); ++ an8855_reg_write(priv, AN8855_RG_RATE_ADAPT_CTRL_0, val); ++ ++ /* Disable AN */ ++ an8855_reg_read(priv, AN8855_SGMII_REG_AN0, &val); ++ val &= ~BIT(12); ++ an8855_reg_write(priv, AN8855_SGMII_REG_AN0, val); ++ ++ /* Force Speed */ ++ an8855_reg_read(priv, AN8855_SGMII_STS_CTRL_0, &val); ++ val |= BIT(2); ++ val |= GENMASK(5, 4); ++ an8855_reg_write(priv, AN8855_SGMII_STS_CTRL_0, val); ++ ++ /* bypass flow control to MAC */ ++ an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_0, 0x01010107); ++ an8855_reg_write(priv, AN8855_MSG_RX_LIK_STS_2, 0x00000EEF); ++ ++ return 0; ++} ++ ++static void an8855_led_set_usr_def(struct an8855_switch_priv *priv, u8 entity, ++ enum an8855_led_polarity pol, u16 on_evt, ++ u16 blk_evt, u8 led_freq) ++{ ++ u32 cl45_data; ++ ++ if (pol == LED_HIGH) ++ on_evt |= LED_ON_POL; ++ else ++ on_evt &= ~LED_ON_POL; ++ ++ /* LED on event */ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_ON_CTRL(entity % 4), ++ on_evt | LED_ON_EN); ++ ++ /* LED blink event */ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_BLK_CTRL(entity % 4), ++ blk_evt); ++ ++ /* LED freq */ ++ switch (led_freq) { ++ case AIR_LED_BLK_DUR_32M: ++ cl45_data = 0x30e; ++ break; ++ ++ case AIR_LED_BLK_DUR_64M: ++ cl45_data = 0x61a; ++ break; ++ ++ case AIR_LED_BLK_DUR_128M: ++ cl45_data = 0xc35; ++ break; ++ ++ case AIR_LED_BLK_DUR_256M: ++ cl45_data = 0x186a; ++ break; ++ ++ case AIR_LED_BLK_DUR_512M: ++ cl45_data = 0x30d4; ++ break; ++ ++ case AIR_LED_BLK_DUR_1024M: ++ cl45_data = 0x61a8; ++ break; ++ ++ default: ++ cl45_data = 0; ++ break; ++ } ++ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_BLK_DUR(entity % 4), ++ cl45_data); ++ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_ON_DUR(entity % 4), ++ (cl45_data >> 1)); ++ ++ /* Disable DATA & BAD_SSD for port LED blink behavior */ ++ cl45_data = mtk_mmd_ind_read(priv->epriv.eth, (entity / 4), 0x1e, PHY_PMA_CTRL); ++ cl45_data &= ~BIT(0); ++ cl45_data &= ~BIT(15); ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_PMA_CTRL, cl45_data); ++} ++ ++static int an8855_led_set_mode(struct an8855_switch_priv *priv, u8 mode) ++{ ++ u16 cl45_data; ++ ++ an8855_phy_cl45_read(priv, 0, 0x1f, PHY_LED_BCR, &cl45_data); ++ ++ switch (mode) { ++ case AN8855_LED_MODE_DISABLE: ++ cl45_data &= ~LED_BCR_EXT_CTRL; ++ cl45_data &= ~LED_BCR_MODE_MASK; ++ cl45_data |= LED_BCR_MODE_DISABLE; ++ break; ++ ++ case AN8855_LED_MODE_USER_DEFINE: ++ cl45_data |= LED_BCR_EXT_CTRL; ++ cl45_data |= LED_BCR_CLK_EN; ++ break; ++ ++ default: ++ printf("an8855: LED mode%d is not supported!\n", mode); ++ return -EINVAL; ++ } ++ ++ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BCR, cl45_data); ++ ++ return 0; ++} ++ ++static int an8855_led_set_state(struct an8855_switch_priv *priv, u8 entity, ++ u8 state) ++{ ++ u16 cl45_data = 0; ++ ++ /* Change to per port contorl */ ++ an8855_phy_cl45_read(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, ++ &cl45_data); ++ ++ if (state == 1) ++ cl45_data |= (1 << (entity % 4)); ++ else ++ cl45_data &= ~(1 << (entity % 4)); ++ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, PHY_LED_CTRL_SELECT, ++ cl45_data); ++ ++ /* LED enable setting */ ++ an8855_phy_cl45_read(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_ON_CTRL(entity % 4), &cl45_data); ++ ++ if (state == 1) ++ cl45_data |= LED_ON_EN; ++ else ++ cl45_data &= ~LED_ON_EN; ++ ++ an8855_phy_cl45_write(priv, (entity / 4), 0x1e, ++ PHY_SINGLE_LED_ON_CTRL(entity % 4), cl45_data); ++ ++ return 0; ++} ++ ++static int an8855_led_init(struct an8855_switch_priv *priv) ++{ ++ u32 val, id, tmp_id = 0; ++ int ret; ++ ++ ret = an8855_led_set_mode(priv, AN8855_LED_MODE_USER_DEFINE); ++ if (ret) { ++ printf("an8855: led_set_mode failed with %d!\n", ret); ++ return ret; ++ } ++ ++ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { ++ ret = an8855_led_set_state(priv, led_cfg[id].phy_led_idx, ++ led_cfg[id].en); ++ if (ret != 0) { ++ printf("an8855: led_set_state failed with %d!\n", ret); ++ return ret; ++ } ++ ++ if (led_cfg[id].en == 1) { ++ an8855_led_set_usr_def(priv, ++ led_cfg[id].phy_led_idx, ++ led_cfg[id].pol, ++ led_cfg[id].on_cfg, ++ led_cfg[id].blk_cfg, ++ led_cfg[id].led_freq); ++ } ++ } ++ ++ /* Setting for System LED & Loop LED */ ++ an8855_reg_write(priv, AN8855_RG_GPIO_OE, 0x0); ++ an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x0); ++ an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, 0); ++ ++ an8855_reg_write(priv, AN8855_RG_GPIO_CTRL, 0x1001); ++ an8855_reg_read(priv, AN8855_RG_GPIO_DATA, &val); ++ val |= GENMASK(3, 1); ++ val &= ~(BIT(0)); ++ val &= ~(BIT(6)); ++ an8855_reg_write(priv, AN8855_RG_GPIO_DATA, val); ++ ++ an8855_reg_read(priv, AN8855_RG_GPIO_OE, &val); ++ val |= 0x41; ++ an8855_reg_write(priv, AN8855_RG_GPIO_OE, val); ++ ++ /* Mapping between GPIO & LED */ ++ val = 0; ++ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { ++ /* Skip GPIO6, due to GPIO6 does not support PORT LED */ ++ if (id == 6) ++ continue; ++ ++ if (led_cfg[id].en == 1) { ++ if (id < 7) ++ val |= led_cfg[id].phy_led_idx << ((id % 4) * 8); ++ else ++ val |= led_cfg[id].phy_led_idx << (((id - 1) % 4) * 8); ++ } ++ ++ if (id < 7) ++ tmp_id = id; ++ else ++ tmp_id = id - 1; ++ ++ if ((tmp_id % 4) == 0x3) { ++ an8855_reg_write(priv, ++ AN8855_RG_GPIO_LED_SEL(tmp_id / 4), ++ val); ++ val = 0; ++ } ++ } ++ ++ /* Turn on LAN LED mode */ ++ val = 0; ++ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { ++ if (led_cfg[id].en == 1) ++ val |= 0x1 << id; ++ } ++ an8855_reg_write(priv, AN8855_RG_GPIO_LED_MODE, val); ++ ++ /* Force clear blink pulse for per port LED */ ++ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0x1f); ++ udelay(1000); ++ an8855_phy_cl45_write(priv, 0, 0x1f, PHY_LED_BLINK_DUR_CTRL, 0); ++ ++ return 0; ++} ++ ++static void an8855_port_isolation(struct an8855_switch_priv *priv) ++{ ++ u32 i; ++ ++ for (i = 0; i < AN8855_NUM_PORTS; i++) { ++ /* Set port matrix mode */ ++ if (i != 5) ++ an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x20); ++ else ++ an8855_reg_write(priv, AN8855_PORTMATRIX_REG(i), 0x1f); ++ ++ /* Set port mode to user port */ ++ an8855_reg_write(priv, AN8855_PVC(i), ++ (0x8100 << AN8855_STAG_VPID_S) | ++ (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); ++ } ++} ++ ++static void an8855_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable) ++{ ++ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; ++ u32 pmcr = AN8855_FORCE_MODE_LNK; ++ ++ if (enable) ++ pmcr = AN8855_FORCE_MODE; ++ ++ an8855_reg_write(priv, AN8855_PMCR_REG(5), pmcr); ++} ++ ++static int an8855_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) ++{ ++ struct an8855_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_read(priv->epriv.eth, addr, reg); ++ ++ return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg); ++} ++ ++static int an8855_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, ++ u16 val) ++{ ++ struct an8855_switch_priv *priv = bus->priv; ++ ++ if (devad < 0) ++ return mtk_mii_write(priv->epriv.eth, addr, reg, val); ++ ++ return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val); ++} ++ ++static int an8855_mdio_register(struct an8855_switch_priv *priv) ++{ ++ struct mii_dev *mdio_bus = mdio_alloc(); ++ int ret; ++ ++ if (!mdio_bus) ++ return -ENOMEM; ++ ++ mdio_bus->read = an8855_mdio_read; ++ mdio_bus->write = an8855_mdio_write; ++ snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name); ++ ++ mdio_bus->priv = priv; ++ ++ ret = mdio_register(mdio_bus); ++ if (ret) { ++ mdio_free(mdio_bus); ++ return ret; ++ } ++ ++ priv->mdio_bus = mdio_bus; ++ ++ return 0; ++} ++ ++static int an8855_setup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; ++ u16 phy_addr, phy_val; ++ u32 i, id, val = 0; ++ int ret; ++ ++ priv->phy_base = 1; ++ ++ /* Turn off PHYs */ ++ for (i = 0; i < AN8855_NUM_PHYS; i++) { ++ phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); ++ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); ++ phy_val |= BMCR_PDOWN; ++ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ /* Force MAC link down before reset */ ++ an8855_reg_write(priv, AN8855_PMCR_REG(5), AN8855_FORCE_MODE_LNK); ++ ++ /* Switch soft reset */ ++ an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST); ++ udelay(100000); ++ ++ an8855_reg_read(priv, AN8855_PKG_SEL, &val); ++ if ((val & 0x7) == PAG_SEL_AN8855H) { ++ /* Release power down */ ++ an8855_reg_write(priv, RG_GPHY_AFE_PWD, 0x0); ++ ++ /* Invert for LED activity change */ ++ an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val); ++ for (id = 0; id < ARRAY_SIZE(led_cfg); id++) { ++ if ((led_cfg[id].pol == LED_HIGH) && ++ (led_cfg[id].en == 1)) ++ val |= 0x1 << id; ++ } ++ an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1)); ++ ++ /* MCU NOP CMD */ ++ an8855_reg_write(priv, AN8855_RG_GDMP_RAM, 0x846); ++ an8855_reg_write(priv, AN8855_RG_GDMP_RAM + 4, 0x4a); ++ ++ /* Enable MCU */ ++ an8855_reg_read(priv, AN8855_RG_CLK_CPU_ICG, &val); ++ an8855_reg_write(priv, AN8855_RG_CLK_CPU_ICG, ++ val | AN8855_MCU_ENABLE); ++ udelay(1000); ++ ++ /* Disable MCU watchdog */ ++ an8855_reg_read(priv, AN8855_RG_TIMER_CTL, &val); ++ an8855_reg_write(priv, AN8855_RG_TIMER_CTL, ++ (val & (~AN8855_WDOG_ENABLE))); ++ ++ /* LED settings for T830 reference board */ ++ ret = an8855_led_init(priv); ++ if (ret < 0) { ++ printf("an8855: an8855_led_init failed with %d\n", ret); ++ return ret; ++ } ++ } ++ ++ switch (priv->epriv.phy_interface) { ++ case PHY_INTERFACE_MODE_2500BASEX: ++ an8855_port_sgmii_init(priv, 5); ++ break; ++ ++ default: ++ break; ++ } ++ ++ an8855_reg_read(priv, AN8855_CKGCR, &val); ++ val &= ~(0x3); ++ an8855_reg_write(priv, AN8855_CKGCR, val); ++ ++ /* Enable port isolation to block inter-port communication */ ++ an8855_port_isolation(priv); ++ ++ /* Turn on PHYs */ ++ for (i = 0; i < AN8855_NUM_PHYS; i++) { ++ phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); ++ phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR); ++ phy_val &= ~BMCR_PDOWN; ++ mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val); ++ } ++ ++ return an8855_mdio_register(priv); ++} ++ ++static int an8855_cleanup(struct mtk_eth_switch_priv *swpriv) ++{ ++ struct an8855_switch_priv *priv = (struct an8855_switch_priv *)swpriv; ++ ++ mdio_unregister(priv->mdio_bus); ++ ++ return 0; ++} ++ ++static int an8855_detect(struct mtk_eth_priv *priv) ++{ ++ int ret; ++ u32 val; ++ ++ ret = __an8855_reg_read(priv, 1, 0x10005000, &val); ++ if (ret) ++ return ret; ++ ++ if (val == 0x8855) ++ return 0; ++ ++ return -ENODEV; ++} ++ ++MTK_ETH_SWITCH(an8855) = { ++ .name = "an8855", ++ .desc = "Airoha AN8855", ++ .priv_size = sizeof(struct an8855_switch_priv), ++ .reset_wait_time = 100, ++ ++ .detect = an8855_detect, ++ .setup = an8855_setup, ++ .cleanup = an8855_cleanup, ++ .mac_control = an8855_mac_control, ++}; diff --git a/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch b/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch new file mode 100644 index 0000000000..374093734f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch @@ -0,0 +1,26 @@ +From 92090b92fab207250d5b8d5a4a36aa34f5a91f19 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:16:33 +0800 +Subject: [PATCH 01/15] board: mediatek: mt7622: remove board_late_init + +The function board_late_init defined for mt7622 is useless now. Just +remove it. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + board/mediatek/mt7622/mt7622_rfb.c | 7 ------- + 1 file changed, 7 deletions(-) + +--- a/board/mediatek/mt7622/mt7622_rfb.c ++++ b/board/mediatek/mt7622/mt7622_rfb.c +@@ -15,10 +15,3 @@ int board_init(void) + { + return 0; + } +- +-int board_late_init(void) +-{ +- gd->env_valid = 1; //to load environment variable from persistent store +- env_relocate(); +- return 0; +-} diff --git a/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch b/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch new file mode 100644 index 0000000000..4e16fe78d4 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch @@ -0,0 +1,48 @@ +From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:16:38 +0800 +Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in + INFRA_MUX struct + +This patch adds missing initialization of fields in INFRA_MUX struct +which caused uart broken after any other infra mux being enabled by +'clk_prepare_enable' + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/clk/mediatek/clk-mt7981.c | 1 + + drivers/clk/mediatek/clk-mt7986.c | 1 + + drivers/clk/mediatek/clk-mt7988.c | 1 + + 3 files changed, 3 insertions(+) + +--- a/drivers/clk/mediatek/clk-mt7981.c ++++ b/drivers/clk/mediatek/clk-mt7981.c +@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci + .id = _id, .mux_reg = (_reg) + 0x8, \ + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } +--- a/drivers/clk/mediatek/clk-mt7986.c ++++ b/drivers/clk/mediatek/clk-mt7986.c +@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci + .id = _id, .mux_reg = (_reg) + 0x8, \ + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } +--- a/drivers/clk/mediatek/clk-mt7988.c ++++ b/drivers/clk/mediatek/clk-mt7988.c +@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_ + .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ + .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, .parent = _parents, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + } diff --git a/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch b/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch new file mode 100644 index 0000000000..b17986ead5 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch @@ -0,0 +1,25 @@ +From 7958b41b8c6a15c3c993affd2091f8c921b6a8a1 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:17:38 +0800 +Subject: [PATCH 03/15] configs: mt7629: move image load address to 0x42000000 + +Update the image load address to ensure it matches the mt7629 NOR +controller's DMA alignment requirements. + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + configs/mt7629_rfb_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/configs/mt7629_rfb_defconfig ++++ b/configs/mt7629_rfb_defconfig +@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000 + CONFIG_SPL_TEXT_BASE=0x201000 + CONFIG_SPL_STACK_R=y + CONFIG_SYS_BOOTM_LEN=0x4000000 +-CONFIG_SYS_LOAD_ADDR=0x42007f1c ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SPL_PAYLOAD="u-boot-lzma.img" + CONFIG_BUILD_TARGET="u-boot-mtk.bin" + CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" diff --git a/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch b/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch new file mode 100644 index 0000000000..e03c9b0305 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch @@ -0,0 +1,24 @@ +From c7a3761ddfce2bd56ad319a254d5269cb26fa18f Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:17:44 +0800 +Subject: [PATCH 04/15] configs: mt7988: move image load address to 0x44000000 + +This patch sets mt7988 image load address to 0x44000000 to support loading +larger images. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + configs/mt7988_rfb_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/configs/mt7988_rfb_defconfig ++++ b/configs/mt7988_rfb_defconfig +@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" + CONFIG_TARGET_MT7988=y +-CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SYS_LOAD_ADDR=0x44000000 + CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_DEBUG_UART=y diff --git a/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch b/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch new file mode 100644 index 0000000000..4b90136687 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch @@ -0,0 +1,23 @@ +From a2c2ac46ca4c4ef5fe043e584cf867a20e93226d Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:17:51 +0800 +Subject: [PATCH 05/15] spi: mtk_spim: add support to use DT live tree + +Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/spi/mtk_spim.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -648,7 +648,7 @@ static int mtk_spim_probe(struct udevice + struct mtk_spim_priv *priv = dev_get_priv(dev); + int ret; + +- priv->base = devfdt_get_addr_ptr(dev); ++ priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + diff --git a/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch b/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch new file mode 100644 index 0000000000..c30105bb5f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch @@ -0,0 +1,27 @@ +From 7725d4ba16577b74567f7cffb2faffa8bdc5ad61 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:17:55 +0800 +Subject: [PATCH 06/15] spi: mtk_spim: check slave device mode in spi-mem's + supports_op + +Call spi_mem_default_supports_op() in supports_op to honor the +slave's supported single/dual/quad mode settings. + +Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/spi/mtk_spim.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct + struct udevice *bus = dev_get_parent(slave->dev); + struct mtk_spim_priv *priv = dev_get_priv(bus); + ++ if (!spi_mem_default_supports_op(slave, op)) ++ return false; ++ + if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || + op->addr.buswidth > 4 || op->dummy.buswidth > 4 || + op->data.buswidth > 4) diff --git a/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch b/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch new file mode 100644 index 0000000000..bfcbd644aa --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch @@ -0,0 +1,96 @@ +From c7a602028669f4409538c3ce0a63c4054d0f2b7a Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:01 +0800 +Subject: [PATCH 07/15] arm: dts: mediatek: add quad mode capabilities for SPI + flashes + +Explicitly add quad mode capabilities or the SPI controller may +start transfer in single mode. + +Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7981-rfb.dts | 4 ++++ + arch/arm/dts/mt7986a-rfb.dts | 4 ++++ + arch/arm/dts/mt7986b-rfb.dts | 4 ++++ + arch/arm/dts/mt7988-rfb.dts | 4 ++++ + 4 files changed, 16 insertions(+) + +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -143,6 +143,8 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +@@ -164,6 +166,8 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7986a-rfb.dts ++++ b/arch/arm/dts/mt7986a-rfb.dts +@@ -190,12 +190,16 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7986b-rfb.dts ++++ b/arch/arm/dts/mt7986b-rfb.dts +@@ -177,12 +177,16 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -144,6 +144,8 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +@@ -165,6 +167,8 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + diff --git a/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch b/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch new file mode 100644 index 0000000000..a11742a213 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch @@ -0,0 +1,98 @@ +From 7071ba2658ef6175183cc5dc85819293811490b3 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:06 +0800 +Subject: [PATCH 08/15] pwm: mediatek: add pwm3 support for mt7981 + +This patch adds pwm channel 2 (pwm3) support for mt7981 + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7981-emmc-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981-sd-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981.dtsi | 10 ++++++++-- + drivers/pwm/pwm-mtk.c | 2 +- + 5 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/arm/dts/mt7981-emmc-rfb.dts ++++ b/arch/arm/dts/mt7981-emmc-rfb.dts +@@ -95,6 +95,14 @@ + }; + }; + ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; ++ + mmc0_pins_default: mmc0default { + mux { + function = "flash"; +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -123,6 +123,14 @@ + groups = "pwm0_1", "pwm1_0", "pwm2"; + }; + }; ++ ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; + }; + + &spi0 { +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -95,6 +95,14 @@ + }; + }; + ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; ++ + mmc0_pins_default: mmc0default { + mux { + function = "flash"; +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -137,8 +137,14 @@ + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; +- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>; ++ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>, ++ <&infracfg CLK_INFRA_PWM1_SEL>, ++ <&infracfg CLK_INFRA_PWM2_SEL>, ++ <&infracfg CLK_INFRA_PWM3_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, ++ <&topckgen CLK_TOP_PWM_SEL>, ++ <&topckgen CLK_TOP_PWM_SEL>, ++ <&topckgen CLK_TOP_PWM_SEL>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + status = "disabled"; + }; +--- a/drivers/pwm/pwm-mtk.c ++++ b/drivers/pwm/pwm-mtk.c +@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_d + }; + + static const struct mtk_pwm_soc mt7981_data = { +- .num_pwms = 2, ++ .num_pwms = 3, + .pwm45_fixup = false, + .reg_ver = PWM_REG_V2, + }; diff --git a/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch b/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch new file mode 100644 index 0000000000..cc23dda975 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch @@ -0,0 +1,61 @@ +From dfbadb86b3bc43c004671ab6eb46ee160a192e98 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:11 +0800 +Subject: [PATCH 09/15] pci: mediatek: add support for multiple ports in + mediatek pcie gen3 driver + +One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 +on this port represents the controller itself and bus 1 represents +the external PCIe device. + +If multiple PCIe controllers are probed in U-Boot, U-Boot will use +bus numbers greater than 2 as input parameters. Therefore, we should +convert the BDF bus number to either 0 or 1 by subtracting the +offset by controller->seq_. + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/pci/pcie_mediatek_gen3.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/drivers/pci/pcie_mediatek_gen3.c ++++ b/drivers/pci/pcie_mediatek_gen3.c +@@ -83,6 +83,28 @@ struct mtk_pcie { + struct phy phy; + }; + ++static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf) ++{ ++ int bdfs[3]; ++ ++ bdfs[0] = PCI_BUS(bdf); ++ bdfs[1] = PCI_DEV(bdf); ++ bdfs[2] = PCI_FUNC(bdf); ++ ++ /* ++ * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on ++ * this port represents the controller itself and bus 1 represents the ++ * external PCIe device. If multiple PCIe controllers are probed in U-Boot, ++ * U-Boot will use bus numbers greater than 2 as input parameters. Therefore, ++ * we should convert the BDF bus number to either 0 or 1 by subtracting the ++ * offset by controller->seq_ ++ */ ++ ++ bdfs[0] = bdfs[0] - controller->seq_; ++ ++ return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); ++} ++ + static void mtk_pcie_config_tlp_header(const struct udevice *bus, + pci_dev_t devfn, + int where, int size) +@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(c + int bytes; + u32 val; + ++ devfn = convert_bdf(bus, devfn); ++ + size = 1 << size; + bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); + diff --git a/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch b/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch new file mode 100644 index 0000000000..0b72a0d232 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch @@ -0,0 +1,219 @@ +From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:17 +0800 +Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988 + +This patch adds PCIe support for mt7988 + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7988-rfb.dts | 18 ++++ + arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++ + 2 files changed, 180 insertions(+) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -63,6 +63,24 @@ + }; + }; + ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* PCIE2 not working in u-boot */ ++&pcie2 { ++ status = "disabled"; ++}; ++ ++/* PCIE3 not working in u-boot */ ++&pcie3 { ++ status = "disabled"; ++}; ++ + &pinctrl { + i2c1_pins: i2c1-pins { + mux { +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -188,6 +188,152 @@ + status = "okay"; + }; + ++ pcie2: pcie@11280000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11280000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <3>; ++ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ phys = <&xphyu3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc2 0>, ++ <0 0 0 2 &pcie_intc2 1>, ++ <0 0 0 3 &pcie_intc2 2>, ++ <0 0 0 4 &pcie_intc2 3>; ++ ++ pcie_intc2: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie3: pcie@11290000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11290000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <2>; ++ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc3 0>, ++ <0 0 0 2 &pcie_intc3 1>, ++ <0 0 0 3 &pcie_intc3 2>, ++ <0 0 0 4 &pcie_intc3 3>; ++ pcie_intc3: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie0: pcie@11300000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11300000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <0>; ++ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie1: pcie@11310000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11310000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <1>; ++ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7988", + "mediatek,generic-tphy-v2"; +@@ -214,6 +360,22 @@ + status = "okay"; + }; + }; ++ ++ xphy: xphy@11e10000 { ++ compatible = "mediatek,mt7988", "mediatek,xsphy"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ xphyu3port0: usb-phy@11e13000 { ++ reg = <0 0x11e13400 0 0x500>; ++ clocks = <&dummy_clk>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; + + xfi_pextp0: syscon@11f20000 { + compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; diff --git a/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch b/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch new file mode 100644 index 0000000000..73caeca7ca --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch @@ -0,0 +1,36 @@ +From 4a85182570200bf5e87e2a9920e9d28e968bc6e0 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:22 +0800 +Subject: [PATCH 11/15] arm: dts: medaitek: fix internal switch link speed of + mt7988 + +The CPU port of mt7988 internal switch uses 10Gb link speed. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7988-rfb.dts | 2 +- + arch/arm/dts/mt7988-sd-rfb.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -57,7 +57,7 @@ + mediatek,switch = "mt7988"; + + fixed-link { +- speed = <1000>; ++ speed = <10000>; + full-duplex; + pause; + }; +--- a/arch/arm/dts/mt7988-sd-rfb.dts ++++ b/arch/arm/dts/mt7988-sd-rfb.dts +@@ -48,7 +48,7 @@ + mediatek,switch = "mt7988"; + + fixed-link { +- speed = <1000>; ++ speed = <10000>; + full-duplex; + pause; + }; diff --git a/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch b/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch new file mode 100644 index 0000000000..f1c9aaa76f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch @@ -0,0 +1,103 @@ +From 64cf3dd0ef520a81a27359d83d58b64939e2aa06 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:27 +0800 +Subject: [PATCH 12/15] arm: dts: mediatek: add support for all three GMACs for + mt7988 + +This patch add all three GMACs nodes for mt7988. Each GMAC can be +configured to connect to different ethernet switches/PHYs. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7988-rfb.dts | 3 +-- + arch/arm/dts/mt7988-sd-rfb.dts | 3 +-- + arch/arm/dts/mt7988.dtsi | 42 ++++++++++++++++++++++++++++++++-- + 3 files changed, 42 insertions(+), 6 deletions(-) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -50,9 +50,8 @@ + status = "okay"; + }; + +-ð { ++ð0 { + status = "okay"; +- mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + +--- a/arch/arm/dts/mt7988-sd-rfb.dts ++++ b/arch/arm/dts/mt7988-sd-rfb.dts +@@ -41,9 +41,8 @@ + status = "okay"; + }; + +-ð { ++ð0 { + status = "okay"; +- mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -587,11 +587,11 @@ + #reset-cells = <1>; + }; + +- eth: ethernet@15100000 { ++ eth0: ethernet@15110100 { + compatible = "mediatek,mt7988-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <0>; + mediatek,ethsys = <ðdma>; +- mediatek,sgmiisys = <&sgmiisys0>; + mediatek,usxgmiisys = <&usxgmiisys0>; + mediatek,xfi_pextp = <&xfi_pextp0>; + mediatek,xfi_pll = <&xfi_pll>; +@@ -602,6 +602,44 @@ + #address-cells = <1>; + #size-cells = <0>; + mediatek,mcm; ++ status = "disabled"; ++ }; ++ ++ eth1: ethernet@15110200 { ++ compatible = "mediatek,mt7988-eth", "syscon"; ++ reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <1>; ++ mediatek,ethsys = <ðdma>; ++ mediatek,sgmiisys = <&sgmiisys1>; ++ mediatek,usxgmiisys = <&usxgmiisys1>; ++ mediatek,xfi_pextp = <&xfi_pextp1>; ++ mediatek,xfi_pll = <&xfi_pll>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,toprgu = <&watchdog>; ++ resets = <ðdma ETHDMA_FE_RST>; ++ reset-names = "fe"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,mcm; ++ status = "disabled"; ++ }; ++ ++ eth2: ethernet@15110300 { ++ compatible = "mediatek,mt7988-eth", "syscon"; ++ reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <2>; ++ mediatek,ethsys = <ðdma>; ++ mediatek,sgmiisys = <&sgmiisys0>; ++ mediatek,usxgmiisys = <&usxgmiisys0>; ++ mediatek,xfi_pextp = <&xfi_pextp0>; ++ mediatek,xfi_pll = <&xfi_pll>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,toprgu = <&watchdog>; ++ resets = <ðdma ETHDMA_FE_RST>; ++ reset-names = "fe"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,mcm; + status = "disabled"; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch b/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch new file mode 100644 index 0000000000..ec948ef207 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch @@ -0,0 +1,81 @@ +From 1090c6df3767da2c56d5827ba65ce91af8745420 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:41 +0800 +Subject: [PATCH 13/15] arm: dts: medaitek: add flash interface driving + settings for mt7988 + +Add driving settings for both SPI and SD/eMMC interfaces to support ensure +flash devices is accessible for ram-booting. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7988-rfb.dts | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -101,6 +101,19 @@ + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; ++ ++ conf-pu { ++ pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ + }; + + spi2_pins: spi2-pins { +@@ -108,6 +121,18 @@ + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; ++ ++ conf-pu { ++ pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; + }; + + mmc0_pins_default: mmc0default { +@@ -121,18 +146,25 @@ + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + + conf-clk { + pins = "EMMC_CK"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + + conf-dsl { + pins = "EMMC_DSL"; ++ mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + + conf-rst { + pins = "EMMC_RSTB"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch b/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch new file mode 100644 index 0000000000..a6b47d7cc8 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch @@ -0,0 +1,62 @@ +From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:55 +0800 +Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node + +1. Fix mmc clock order of mt7981 to match the clock name +2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0 +3. Increase the CLK pin driving strength to 8mA + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++-- + arch/arm/dts/mt7981.dtsi | 12 ++++++------ + 2 files changed, 10 insertions(+), 8 deletions(-) + +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -118,7 +118,7 @@ + }; + conf-clk { + pins = "SPI1_CS"; +- drive-strength = <MTK_DRIVE_6mA>; ++ drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + conf-rst { +@@ -140,10 +140,12 @@ + }; + + &mmc0 { ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; +- max-frequency = <52000000>; ++ max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <0>; + vmmc-supply = <®_3p3v>; +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -306,13 +306,13 @@ + reg = <0x11230000 0x1000>, + <0x11C20000 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&topckgen CLK_TOP_EMMC_400M>, +- <&topckgen CLK_TOP_EMMC_208M>, ++ clocks = <&topckgen CLK_TOP_EMMC_208M>, ++ <&topckgen CLK_TOP_EMMC_400M>, + <&infracfg CLK_INFRA_MSDC_CK>; +- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, +- <&topckgen CLK_TOP_EMMC_208M_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, +- <&topckgen CLK_TOP_CB_M_D2>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; diff --git a/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch b/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch new file mode 100644 index 0000000000..81fcac7819 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch @@ -0,0 +1,36 @@ +From 8707ea0360046522d0784135b6c9a7c564f9515c Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 17 Jan 2025 17:18:59 +0800 +Subject: [PATCH 15/15] MAINTAINERS: update file list for MediaTek ARM platform + +Add driver files for MediaTek ARM platform + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + MAINTAINERS | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c + F: drivers/phy/phy-mtk-* + F: drivers/pinctrl/mediatek/ + F: drivers/power/domain/mtk-power-domain.c ++F: drivers/pci/pcie_mediatek_gen3.c ++F: drivers/pci/pcie_mediatek.c ++F: drivers/pwm/pwm-mtk.c + F: drivers/ram/mediatek/ + F: drivers/spi/mtk_snfi_spi.c + F: drivers/spi/mtk_spim.c ++F: drivers/spi/mtk_snor.c + F: drivers/timer/mtk_timer.c + F: drivers/usb/host/xhci-mtk.c + F: drivers/usb/mtu3/ +@@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c + F: drivers/net/mtk_eth.c + F: drivers/net/mtk_eth.h + F: drivers/reset/reset-mediatek.c ++F: drivers/serial/serial_mtk.c + F: include/dt-bindings/clock/mediatek,* + F: include/dt-bindings/power/mediatek,* + F: tools/mtk_image.c diff --git a/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch b/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch new file mode 100644 index 0000000000..e6d0ec35fa --- /dev/null +++ b/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch @@ -0,0 +1,138 @@ +From 24e660265f11dad63687c5529cf732538946a197 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 24 Jan 2025 11:39:02 +0800 +Subject: [PATCH] pinctrl: mediatek: update mt7981 pinctrl driver based on + upstream kernel + +Update mt7981 pinctrl driver based on upstream kernel + +Signed-off-by: Sam Shih <sam.shih@mediatek.com> +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ++++++++++++++++++++--- + 1 file changed, 45 insertions(+), 6 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_ + MT7981_TYPE1_PIN(56, "WF_HB10"), + }; + ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. ++ * The hardware probably has multiple combinations of these pinouts. ++ */ ++ + /* WA_AICE */ + static const int mt7981_wa_aice1_pins[] = { 0, 1, }; + static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; +@@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs + static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; + static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + ++static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; ++static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; ++ + /* GBE_LED0 */ + static const int mt7981_gbe_led0_pins[] = { 8, }; + static const int mt7981_gbe_led0_funcs[] = { 3, }; +@@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[] + static const int mt7981_drv_vbus_funcs[] = { 1, }; + + /* EMMC */ ++static const int mt7981_emmc_reset_pins[] = { 15, }; ++static const int mt7981_emmc_reset_funcs[] = { 2, }; ++ ++static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; ++static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++ ++static const int mt7981_emmc_8_pins[] = { ++ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; ++static const int mt7981_emmc_8_funcs[] = { ++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++ + static const int mt7981_emmc_45_pins[] = { + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; + static const int mt7981_emmc_45_funcs[] = { +@@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[] + static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; + static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + ++static const int mt7981_uart1_2_pins[] = { 9, 10, }; ++static const int mt7981_uart1_2_funcs[] = { 2, 2, }; ++ ++static const int mt7981_uart1_3_pins[] = { 26, 27, }; ++static const int mt7981_uart1_3_funcs[] = { 2, 2, }; ++ + /* UART2 */ + static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; + static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; +@@ -832,6 +857,8 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), + /* @GPIO(4,7) WM_JTAG(3) */ + PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), ++ /* @GPIO(4,5) WM_JTAG(4) */ ++ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), + /* @GPIO(8) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), + /* @GPIO(4,6) PTA_EXT(4) */ +@@ -844,7 +871,7 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), + /* @GPIO(6,7) I2C(5) */ + PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), +- /* @GPIO(8): DFD_NTRST(6) */ ++ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ + PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), + /* @GPIO(9,10): WM_AICE(2) */ + PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), +@@ -870,6 +897,12 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("udi", mt7981_udi), + /* @GPIO(14) DRV_VBUS(1) */ + PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), ++ /* @GPIO(15): EMMC_RSTB(2) */ ++ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), ++ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), ++ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), + /* @GPIO(15,25): EMMC(2) */ + PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), + /* @GPIO(16,21): SNFI(3) */ +@@ -888,8 +921,12 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), + /* @GPIO(26,29): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), ++ /* @GPIO(9,10): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), ++ /* @GPIO(26,27): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), + /* @GPIO(22,25): UART2(3) */ +- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), ++ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), + /* @GPIO(20,21): WM_UART(4) */ +@@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7 + */ + static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", + "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; +-static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", +- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", +- "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; ++static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0", ++ "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0", ++ "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1", ++ "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; + static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; + static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; + static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", +@@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_grou + static const char *const mt7981_pcm_groups[] = { "pcm", }; + static const char *const mt7981_udi_groups[] = { "udi", }; + static const char *const mt7981_usb_groups[] = { "drv_vbus", }; +-static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; ++static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4", ++ "emmc_8", "emmc_45", "snfi", }; + static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", + "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; + static const char *const mt7981_ant_groups[] = { "ant_sel", }; diff --git a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch index 0e63b1e2d3..f5823a53d1 100644 --- a/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch +++ b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch @@ -38,7 +38,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig -@@ -238,6 +238,8 @@ config SYS_MAX_FLASH_BANKS_DETECT +@@ -246,6 +246,8 @@ config SYS_MAX_FLASH_BANKS_DETECT to reduce the effective number of flash bank, between 0 and CONFIG_SYS_MAX_FLASH_BANKS @@ -49,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config SYS_NAND_MAX_OOBFREE --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR +@@ -40,3 +40,5 @@ obj-$(CONFIG_$(PHASE_)SPI_FLASH_SUPPORT) obj-$(CONFIG_SPL_UBI) += ubispl/ endif @@ -1313,7 +1313,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + -+#include <common.h> ++#include <config.h> +#include <dm.h> +#include <malloc.h> +#include <mapmem.h> @@ -1896,7 +1896,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#ifndef _MTK_SNAND_OS_H_ +#define _MTK_SNAND_OS_H_ + -+#include <common.h> ++#include <config.h> +#include <cpu_func.h> +#include <errno.h> +#include <div64.h> diff --git a/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch index 3d7c4a9bf6..27b56f7bd3 100644 --- a/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch +++ b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch @@ -47,7 +47,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + -+#include <common.h> ++#include <config.h> +#include <dm.h> +#include <dm/uclass.h> +#include <malloc.h> diff --git a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch index 9b02b4dc63..946248bbb4 100644 --- a/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch +++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch @@ -89,14 +89,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> depends on ENV_IS_IN_UBI --- a/env/Makefile +++ b/env/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MMC) += mmc.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) += fat.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o -+obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o +@@ -24,6 +24,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_NOWHERE) += + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MMC) += mmc.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += fat.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o ++obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o --- a/env/env.c +++ b/env/env.c @@ -46,6 +46,9 @@ static enum env_location env_locations[] @@ -370,7 +370,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +}; --- a/include/env_internal.h +++ b/include/env_internal.h -@@ -109,6 +109,7 @@ enum env_location { +@@ -108,6 +108,7 @@ enum env_location { ENVL_FAT, ENVL_FLASH, ENVL_MMC, diff --git a/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch b/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch index d90ca64704..aa19a11587 100644 --- a/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch +++ b/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c -@@ -1057,6 +1057,9 @@ int mtd_id_parse(const char *id, const c +@@ -1054,6 +1054,9 @@ int mtd_id_parse(const char *id, const c } else if (strncmp(p, "spi-nand", 8) == 0) { *dev_type = MTD_DEV_TYPE_SPINAND; p += 8; @@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> return 1; --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h -@@ -16,11 +16,13 @@ +@@ -17,11 +17,13 @@ #define MTD_DEV_TYPE_NAND 0x0002 #define MTD_DEV_TYPE_ONENAND 0x0004 #define MTD_DEV_TYPE_SPINAND 0x0008 diff --git a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch index 23634e6425..cbf6faf8c6 100644 --- a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch +++ b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch @@ -13,13 +13,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> drivers/mtd/Makefile | 1 + drivers/mtd/nmbm/Kconfig | 29 + drivers/mtd/nmbm/Makefile | 5 + - drivers/mtd/nmbm/nmbm-core.c | 2936 +++++++++++++++++++++++++++++++ + drivers/mtd/nmbm/nmbm-core.c | 3040 +++++++++++++++++++++++++++++++ drivers/mtd/nmbm/nmbm-debug.h | 37 + drivers/mtd/nmbm/nmbm-debug.inl | 39 + drivers/mtd/nmbm/nmbm-private.h | 137 ++ - include/nmbm/nmbm-os.h | 66 + - include/nmbm/nmbm.h | 102 ++ - 10 files changed, 3354 insertions(+) + include/nmbm/nmbm-os.h | 68 + + include/nmbm/nmbm.h | 105 ++ + 10 files changed, 3463 insertions(+) create mode 100644 drivers/mtd/nmbm/Kconfig create mode 100644 drivers/mtd/nmbm/Makefile create mode 100644 drivers/mtd/nmbm/nmbm-core.c @@ -31,16 +31,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig -@@ -274,4 +274,6 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/nvmxip/Kconfig" +@@ -276,6 +276,8 @@ config SYS_NAND_MAX_CHIPS + help + The maximum number of NAND chips per device to be supported. +source "drivers/mtd/nmbm/Kconfig" + - endmenu + source "drivers/mtd/spi/Kconfig" + + source "drivers/mtd/ubi/Kconfig" --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -41,3 +41,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/ +@@ -42,3 +42,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/ endif obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ @@ -87,10 +89,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +obj-$(CONFIG_NMBM) += nmbm-core.o --- /dev/null +++ b/drivers/mtd/nmbm/nmbm-core.c -@@ -0,0 +1,2936 @@ +@@ -0,0 +1,3040 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* -+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ @@ -347,6 +349,37 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +} + +/* ++ * nmbm_panic_write_phys_page - Panic write page with retry ++ * @ni: NMBM instance structure ++ * @addr: linear address where the data will be written to ++ * @data: the main data to be written ++ * ++ * Write a page for at most NMBM_TRY_COUNT times. ++ */ ++static bool nmbm_panic_write_phys_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data) ++{ ++ int tries, ret; ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_err(ni, "%s called with NMBM_F_READ_ONLY set\n", addr); ++ return false; ++ } ++ ++ for (tries = 0; tries < NMBM_TRY_COUNT; tries++) { ++ ret = ni->lower.panic_write_page(ni->lower.arg, addr, data); ++ if (!ret) ++ return true; ++ ++ nmbm_reset_chip(ni); ++ } ++ ++ nlog_err(ni, "Panic page write failed at address 0x%08llx\n", addr); ++ ++ return false; ++} ++ ++/* + * nmbm_erase_phys_block - Erase a block with retry + * @ni: NMBM instance structure + * @addr: Linear address @@ -750,7 +783,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + addr = ba2addr(ni, ba); + + for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { -+ schedule(); ++ WATCHDOG_RESET(); + + ret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL, + NMBM_MODE_PLACE_OOB); @@ -789,7 +822,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + bool success; + + while (ba < limit) { -+ schedule(); ++ WATCHDOG_RESET(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -840,7 +873,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + addr = ba2addr(ni, ba); + + for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { -+ schedule(); ++ WATCHDOG_RESET(); + + /* Prepare page data. fill 0xff to unused region */ + memcpy(ni->page_cache, data, size); @@ -884,7 +917,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + bool success; + + while (ba > limit) { -+ schedule(); ++ WATCHDOG_RESET(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -939,7 +972,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + int ret; + + while (sizeremain) { -+ schedule(); ++ WATCHDOG_RESET(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -989,7 +1022,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + int ret; + + while (sizeremain) { -+ schedule(); ++ WATCHDOG_RESET(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -1045,7 +1078,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + bool success; + + while (sizeremain && ba < limit) { -+ schedule(); ++ WATCHDOG_RESET(); + + chunksize = sizeremain; + if (chunksize > ni->lower.erasesize) @@ -1307,7 +1340,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Try to write new info table next to the existing table */ + while (write_ba >= ni->mapping_blocks_ba) { -+ schedule(); ++ WATCHDOG_RESET(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1426,7 +1459,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Try to write temporary info table into spare unmapped blocks */ + while (write_ba >= ni->mapping_blocks_ba) { -+ schedule(); ++ WATCHDOG_RESET(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1512,7 +1545,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Write new backup info table. */ + while (write_ba >= main_table_end_ba) { -+ schedule(); ++ WATCHDOG_RESET(); + + success = nmbm_write_info_table(ni, write_ba, + ni->mapping_blocks_top_ba, @@ -1901,7 +1934,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + int ret; + + while (sizeremain && ba < limit) { -+ schedule(); ++ WATCHDOG_RESET(); + + if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) + goto next_block; @@ -1994,7 +2027,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + bool success; + + while (ba < limit - size2blk(ni, ni->info_table_size)) { -+ schedule(); ++ WATCHDOG_RESET(); + + success = nmbm_try_load_info_table(ni, ba, table_end_ba, + write_count, @@ -2206,7 +2239,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + limit = block_count - ni->lower.max_reserved_blocks; + + while (ba >= limit) { -+ schedule(); ++ WATCHDOG_RESET(); + + ba--; + addr = ba2addr(ni, ba); @@ -2220,7 +2253,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + */ + for (off = 0; off < ni->lower.erasesize; + off += ni->lower.writesize) { -+ schedule(); ++ WATCHDOG_RESET(); + + ret = nmbn_read_data(ni, addr + off, &sig, + sizeof(sig)); @@ -2279,7 +2312,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + return false; + } + -+ if (!nld->oobsize || !is_power_of_2(nld->oobsize)) { ++ if (!nld->oobsize) { + nmbm_log_lower(nld, NMBM_LOG_ERR, + "Page spare size %u is not valid\n", nld->oobsize); + return false; @@ -2592,7 +2625,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + end_ba = addr2ba(ni, addr + size - 1); + + while (start_ba <= end_ba) { -+ schedule(); ++ WATCHDOG_RESET(); + + ret = nmbm_erase_logic_block(ni, start_ba); + if (ret) { @@ -2724,7 +2757,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + } + + while (sizeremain) { -+ schedule(); ++ WATCHDOG_RESET(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -2820,6 +2853,53 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +} + +/* ++ * nmbm_panic_write_logic_page - Panic write page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer contains main data. optional. ++ */ ++static int nmbm_panic_write_logic_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data) ++{ ++ uint32_t lb, pb, offset; ++ uint64_t paddr; ++ bool success; ++ ++ /* Extract block address and in-block offset */ ++ lb = addr2ba(ni, addr); ++ offset = addr & ni->erasesize_mask; ++ ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[lb]; ++ ++ /* Whether the logic block is good (has valid mapping) */ ++ if ((int32_t)pb < 0) { ++ nlog_debug(ni, "Logic block %u is a bad block\n", lb); ++ return -EIO; ++ } ++ ++ /* Fail if physical block is marked bad */ ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD) ++ return -EIO; ++ ++ /* Assemble new address */ ++ paddr = ba2addr(ni, pb) + offset; ++ ++ success = nmbm_panic_write_phys_page(ni, paddr, data); ++ if (success) ++ return 0; ++ ++ /* ++ * Do not remap bad block here. Just mark this block in state table. ++ * Remap this block on erasing. ++ */ ++ nmbm_set_block_state(ni, pb, BLOCK_ST_NEED_REMAP); ++ nmbm_update_info_table(ni); ++ ++ return -EIO; ++} ++ ++/* + * nmbm_write_single_page - Write one page based on logic address + * @ni: NMBM instance structure + * @addr: logic linear address @@ -2849,6 +2929,32 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +} + +/* ++ * nmbm_panic_write_single_page - Panic write one page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer contains main data. optional. ++ */ ++int nmbm_panic_write_single_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data) ++{ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ return nmbm_panic_write_logic_page(ni, addr, data); ++} ++ ++/* + * nmbm_write_range - Write data without oob + * @ni: NMBM instance structure + * @addr: logic linear address @@ -2891,7 +2997,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + } + + while (sizeremain) { -+ schedule(); ++ WATCHDOG_RESET(); + + leading = off & ni->writesize_mask; + chunksize = ni->lower.writesize - leading; @@ -3248,7 +3354,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#endif /* _NMBM_PRIVATE_H_ */ --- /dev/null +++ b/include/nmbm/nmbm-os.h -@@ -0,0 +1,66 @@ +@@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -3263,7 +3369,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + +#include <div64.h> +#include <stdbool.h> -+#include <watchdog.h> ++#include <cyclic.h> +#include <u-boot/crc.h> +#include <linux/errno.h> +#include <linux/log2.h> @@ -3314,10 +3420,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#define NMBM_DEFAULT_LOG_LEVEL 1 +#endif + ++#define WATCHDOG_RESET schedule ++ +#endif /* _NMBM_OS_H_ */ --- /dev/null +++ b/include/nmbm/nmbm.h -@@ -0,0 +1,102 @@ +@@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -3372,6 +3480,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + */ + int (*read_page)(void *arg, uint64_t addr, void *buf, void *oob, enum nmbm_oob_mode mode); + int (*write_page)(void *arg, uint64_t addr, const void *buf, const void *oob, enum nmbm_oob_mode mode); ++ int (*panic_write_page)(void *arg, uint64_t addr, const void *buf); + int (*erase_block)(void *arg, uint64_t addr); + + int (*is_bad_block)(void *arg, uint64_t addr); @@ -3408,6 +3517,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +int nmbm_write_single_page(struct nmbm_instance *ni, uint64_t addr, + const void *data, const void *oob, + enum nmbm_oob_mode mode); ++int nmbm_panic_write_single_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data); +int nmbm_write_range(struct nmbm_instance *ni, uint64_t addr, size_t size, + const void *data, enum nmbm_oob_mode mode, + size_t *retlen); diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch index da4dce917b..3792fae430 100644 --- a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/common/board_r.c +++ b/common/board_r.c -@@ -373,6 +373,20 @@ static int initr_nand(void) +@@ -381,6 +381,20 @@ static int initr_nand(void) } #endif @@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> #if defined(CONFIG_CMD_ONENAND) /* go init the NAND */ static int initr_onenand(void) -@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -694,6 +708,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch index 4eb2bc9ccf..ab5df08c5c 100644 --- a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE +@@ -1492,6 +1492,12 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -35,9 +35,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> obj-$(CONFIG_CMD_MUX) += mux.o obj-$(CONFIG_CMD_NAND) += nand.o +obj-$(CONFIG_CMD_NMBM) += nmbm.o - obj-$(CONFIG_CMD_NET) += net.o - obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o - obj-$(CONFIG_CMD_ONENAND) += onenand.o + ifdef CONFIG_NET + obj-$(CONFIG_CMD_NET) += net.o net-common.o + else ifdef CONFIG_NET_LWIP --- /dev/null +++ b/cmd/nmbm.c @@ -0,0 +1,327 @@ diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch index c6358f3287..0943a63217 100644 --- a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch +++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch @@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> --- a/cmd/mtd.c +++ b/cmd/mtd.c -@@ -504,6 +504,42 @@ out_put_mtd: +@@ -730,6 +730,42 @@ out_put_mtd: return CMD_RET_SUCCESS; } @@ -63,15 +63,15 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> #ifdef CONFIG_AUTO_COMPLETE static int mtd_name_complete(int argc, char *const argv[], char last_char, int maxv, char *cmdv[]) -@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd, +@@ -777,6 +813,7 @@ U_BOOT_LONGHELP(mtd, "\n" "Specific functions:\n" "mtd bad <name>\n" + "mtd markbad <name> <off>\n" - "\n" - "With:\n" - "\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n" -@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" + #if CONFIG_IS_ENABLED(CMD_MTD_OTP) + "mtd otpread <name> [u|f] <off> <size>\n" + "mtd otpwrite <name> <off> <hex string>\n" +@@ -817,4 +854,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase, mtd_name_complete), U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad, diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch index dbb1e2e59d..fd95cc2a8b 100644 --- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch +++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch @@ -7,29 +7,29 @@ Add an env driver for NMBM upper MTD layer Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- - cmd/nvedit.c | 3 +- env/Kconfig | 19 ++++- env/Makefile | 1 + env/env.c | 3 + env/nmbm.c | 155 +++++++++++++++++++++++++++++++++++++++++ include/env_internal.h | 1 + tools/Makefile | 1 + - 7 files changed, 180 insertions(+), 3 deletions(-) + 6 files changed, 178 insertions(+), 2 deletions(-) create mode 100644 env/nmbm.c --- a/env/Kconfig +++ b/env/Kconfig -@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT - def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ - !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \ +@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ -+ !ENV_IS_IN_NMBM && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ - !ENV_IS_IN_UBI && !ENV_IS_IN_MTD -@@ -315,6 +316,21 @@ config ENV_RANGE - Specifying a range with more erase blocks than are needed to hold - CONFIG_ENV_SIZE allows bad blocks within the range to be avoided. +- !ENV_IS_IN_UBI && !ENV_IS_IN_MTD ++ !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD + select ENV_IS_NOWHERE + + config ENV_IS_NOWHERE +@@ -305,6 +305,21 @@ config ENV_IS_IN_NAND + Currently, CONFIG_ENV_OFFSET_REDUND is not supported when + using CONFIG_ENV_OFFSET_OOB. +config ENV_IS_IN_NMBM + bool "Environment in a NMBM upper MTD layer" @@ -46,10 +46,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + area within the first NAND device. CONFIG_ENV_OFFSET must be + aligned to an erase block boundary. + - config ENV_IS_IN_NVRAM - bool "Environment in a non-volatile RAM" - depends on !CHAIN_OF_TRUST -@@ -591,7 +607,7 @@ config ENV_MTD_NAME + config ENV_RANGE + hex "Length of the region in which the environment can be written" + depends on ENV_IS_IN_NAND +@@ -591,7 +606,7 @@ config ENV_MTD_NAME config ENV_OFFSET hex "Environment offset" depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ @@ -60,13 +60,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> default 0xF0000 if ARCH_SUNXI --- a/env/Makefile +++ b/env/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) + - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o -+obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NMBM) += nmbm.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o - obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o +@@ -26,6 +26,7 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FAT) += + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_EXT4) += ext4.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o ++obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NMBM) += nmbm.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o + obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o --- a/env/env.c +++ b/env/env.c @@ -240,7 +240,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +}; --- a/include/env_internal.h +++ b/include/env_internal.h -@@ -111,6 +111,7 @@ enum env_location { +@@ -110,6 +110,7 @@ enum env_location { ENVL_MMC, ENVL_MTD, ENVL_NAND, diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch index e6e12ae24c..419673f7e2 100644 --- a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE +@@ -1492,6 +1492,14 @@ config CMD_NAND_TORTURE endif # CMD_NAND @@ -49,8 +49,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> obj-$(CONFIG_CMD_NAND) += nand.o +obj-$(CONFIG_CMD_NAND_EXT) += nand-ext.o obj-$(CONFIG_CMD_NMBM) += nmbm.o - obj-$(CONFIG_CMD_NET) += net.o - obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o + ifdef CONFIG_NET + obj-$(CONFIG_CMD_NET) += net.o net-common.o --- /dev/null +++ b/cmd/nand-ext.c @@ -0,0 +1,1062 @@ diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch index da09cd9c08..230bbf0fa3 100644 --- a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp +@@ -3248,6 +3248,100 @@ static int spi_nor_init_params(struct sp return 0; } @@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) { size_t i; -@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor) +@@ -4450,6 +4544,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->write = spi_nor_write_data; nor->read_reg = spi_nor_read_reg; nor->write_reg = spi_nor_write_reg; @@ -124,7 +124,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h -@@ -29,6 +29,7 @@ +@@ -32,6 +32,7 @@ #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ @@ -132,7 +132,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> #define SNOR_MFR_CYPRESS 0x34 /* -@@ -571,6 +572,7 @@ struct spi_nor { +@@ -590,6 +591,7 @@ struct spi_nor { void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch index f7cbd8d052..68b2eee61e 100644 --- a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch +++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch @@ -12,7 +12,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/cmd/sf.c +++ b/cmd/sf.c -@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char +@@ -421,6 +421,14 @@ static int do_spi_protect(int argc, char return ret == 0 ? 0 : 1; } @@ -27,7 +27,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> enum { STAGE_ERASE, STAGE_CHECK, -@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl * +@@ -615,6 +623,8 @@ static int do_spi_flash(struct cmd_tbl * ret = do_spi_flash_erase(argc, argv); else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0) ret = do_spi_protect(argc, argv); @@ -36,11 +36,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); else -@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf, +@@ -643,8 +653,9 @@ U_BOOT_LONGHELP(sf, + " at address 'sector'" + #endif #ifdef CONFIG_CMD_SF_TEST - "\nsf test offset len - run a very basic destructive test" +- "\nsf test offset len - run a very basic destructive test" ++ "\nsf test offset len - run a very basic destructive test" #endif -+ "sf uuid - read uuid from flash" ++ "\nsf uuid - read uuid from flash" ); U_BOOT_CMD( diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch index 0438895fdb..7daae5c484 100644 --- a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch @@ -7,48 +7,24 @@ Add ability to use shortkey to select item for bootmenu command Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- - cmd/bootmenu.c | 34 ++++++++++++++++++++++++----- - common/menu.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++-- - include/menu.h | 12 +++++++---- - 3 files changed, 93 insertions(+), 11 deletions(-) + cmd/bootmenu.c | 28 +++++++++++++++++++++++--- + common/menu.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++ + include/cli.h | 2 ++ + include/menu.h | 3 +++ + 4 files changed, 84 insertions(+), 3 deletions(-) --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -89,6 +89,7 @@ static char *bootmenu_choice_entry(void - struct bootmenu_data *menu = data; - struct bootmenu_entry *iter; - enum bootmenu_key key = BKEY_NONE; -+ int choice = -1; - int i; - - cli_ch_init(cch); -@@ -96,10 +97,10 @@ static char *bootmenu_choice_entry(void - while (1) { - if (menu->delay >= 0) { - /* Autoboot was not stopped */ -- key = bootmenu_autoboot_loop(menu, cch); -+ key = bootmenu_autoboot_loop(menu, cch, &choice); - } else { - /* Some key was pressed, so autoboot was stopped */ -- key = bootmenu_loop(menu, cch); -+ key = bootmenu_loop(menu, cch, &choice); - } - - switch (key) { -@@ -113,6 +114,12 @@ static char *bootmenu_choice_entry(void +@@ -114,6 +114,8 @@ static char *bootmenu_choice_entry(void ++menu->active; /* no menu key selected, regenerate menu */ return NULL; + case BKEY_CHOICE: -+ menu->active = choice; -+ if (!menu->last_choiced) { -+ menu->last_choiced = true; -+ return NULL; -+ } ++ menu->active = cch->choice; case BKEY_SELECT: iter = menu->first; for (i = 0; i < menu->active; ++i) -@@ -170,6 +177,9 @@ static int prepare_bootmenu_entry(struct +@@ -182,6 +184,9 @@ static int prepare_bootmenu_entry(struct unsigned short int i = *index; struct bootmenu_entry *entry = NULL; struct bootmenu_entry *iter = *current; @@ -58,24 +34,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> while ((option = bootmenu_getoption(i))) { -@@ -184,11 +194,24 @@ static int prepare_bootmenu_entry(struct +@@ -196,11 +201,28 @@ static int prepare_bootmenu_entry(struct if (!entry) return -ENOMEM; - entry->title = strndup(option, sep - option); -+ /* Add KEY_CHOICE support: '%d. %s\0' : len --> len + 4 */ ++ /* Add BKEY_CHOICE support: '%c. %s\0' : len --> len + 4 */ + len = sep - option + 4; ++ + choice_option = malloc(len); + if (!choice_option) { + free(entry->title); + free(entry); + return -ENOMEM; + } ++ + if (!get_choice_char(i, &choice_char)) + len = snprintf(choice_option, len, "%c. %s", choice_char, option); + else + len = snprintf(choice_option, len, " %s", option); ++ + entry->title = strndup(choice_option, len); ++ if (!entry->title) { free(entry); return -ENOMEM; @@ -84,20 +64,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> entry->command = strdup(sep + 1); if (!entry->command) { -@@ -334,6 +357,7 @@ static struct bootmenu_data *bootmenu_cr - menu->delay = delay; - menu->active = 0; - menu->first = NULL; -+ menu->last_choiced = false; +@@ -382,9 +404,9 @@ static struct bootmenu_data *bootmenu_cr - default_str = env_get("bootmenu_default"); - if (default_str) -@@ -369,9 +393,9 @@ static struct bootmenu_data *bootmenu_cr - - /* Add Quit entry if entering U-Boot console is disabled */ + /* Add Quit entry if exiting bootmenu is disabled */ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) -- entry->title = strdup("U-Boot console"); -+ entry->title = strdup("0. U-Boot console"); +- entry->title = strdup("Exit"); ++ entry->title = strdup("0. Exit"); else - entry->title = strdup("Quit"); + entry->title = strdup("0. Quit"); @@ -106,7 +78,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> free(entry); --- a/common/menu.c +++ b/common/menu.c -@@ -49,6 +49,33 @@ struct menu { +@@ -8,6 +8,7 @@ + #include <cli.h> + #include <malloc.h> + #include <errno.h> ++#include <linux/ctype.h> + #include <linux/delay.h> + #include <linux/list.h> + #include <watchdog.h> +@@ -49,6 +50,33 @@ struct menu { int item_cnt; }; @@ -140,184 +120,87 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> /* * An iterator function for menu items. callback will be called for each item * in m, with m, a pointer to the item, and extra being passed to callback. If -@@ -428,7 +455,7 @@ int menu_destroy(struct menu *m) - } - - enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, -- struct cli_ch_state *cch) -+ struct cli_ch_state *cch, int *choice) +@@ -441,6 +469,7 @@ enum bootmenu_key bootmenu_autoboot_loop { enum bootmenu_key key = BKEY_NONE; int i, c; -@@ -463,6 +490,19 @@ enum bootmenu_key bootmenu_autoboot_loop - break; - default: - key = BKEY_NONE; -+ if (cch->esc_len || !choice) -+ break; -+ -+ *choice = find_choice(c); -+ if ((*choice >= 0 && -+ *choice < menu->count - 1)) { -+ key = BKEY_CHOICE; -+ } else if (c == '0') { -+ *choice = menu->count - 1; -+ key = BKEY_CHOICE; -+ } else { -+ key = BKEY_NONE; -+ } - break; - } - break; -@@ -483,7 +523,8 @@ enum bootmenu_key bootmenu_autoboot_loop - return key; - } - --enum bootmenu_key bootmenu_conv_key(int ichar) -+enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar, -+ int *choice) - { - enum bootmenu_key key; - -@@ -515,6 +556,20 @@ enum bootmenu_key bootmenu_conv_key(int - case ' ': - key = BKEY_SPACE; - break; -+ case '0' ... '9': -+ case 'a' ... 'z': -+ if (choice && menu) { -+ *choice = find_choice(ichar); -+ if ((*choice >= 0 && *choice < menu->count - 1)) { ++ int choice; + + while (menu->delay > 0) { + if (ansi) +@@ -458,6 +487,18 @@ enum bootmenu_key bootmenu_autoboot_loop + menu->delay = -1; + c = getchar(); + ++ choice = find_choice(c); ++ if ((choice >= 0 && ++ choice < menu->count - 1)) { ++ cch->choice = choice; + key = BKEY_CHOICE; + break; -+ } else if (ichar == '0') { -+ *choice = menu->count - 1; ++ } else if (c == '0') { ++ cch->choice = menu->count - 1; + key = BKEY_CHOICE; + break; + } -+ } -+ fallthrough; - default: - key = BKEY_NONE; - break; -@@ -524,11 +579,16 @@ enum bootmenu_key bootmenu_conv_key(int - } ++ + ichar = cli_ch_process(cch, c); - enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, -- struct cli_ch_state *cch) -+ struct cli_ch_state *cch, int *choice) + switch (ichar) { +@@ -537,6 +578,7 @@ enum bootmenu_key bootmenu_loop(struct b { enum bootmenu_key key; - int c; + int c, errchar = 0; ++ int choice; -+ if (menu->last_choiced) { -+ menu->last_choiced = false; -+ return BKEY_SELECT; -+ } -+ c = cli_ch_process(cch, 0); if (!c) { - while (!c && !tstc()) { -@@ -542,7 +602,7 @@ enum bootmenu_key bootmenu_loop(struct b +@@ -548,6 +590,18 @@ enum bootmenu_key bootmenu_loop(struct b + } + if (!c) { + c = getchar(); ++ ++ choice = find_choice(c); ++ if ((choice >= 0 && ++ choice < menu->count - 1)) { ++ cch->choice = choice; ++ return BKEY_CHOICE; ++ ++ } else if (c == '0') { ++ cch->choice = menu->count - 1; ++ return BKEY_CHOICE; ++ } ++ + c = cli_ch_process(cch, c); } } +--- a/include/cli.h ++++ b/include/cli.h +@@ -23,6 +23,8 @@ struct cli_ch_state { + char esc_save[8]; + int emit_upto; + bool emitting; ++ /* mediatek bootmenu choice feature */ ++ char choice; + }; -- key = bootmenu_conv_key(c); -+ key = bootmenu_conv_key(menu, c, choice); - - return key; - } + /** --- a/include/menu.h +++ b/include/menu.h -@@ -6,6 +6,8 @@ - #ifndef __MENU_H__ - #define __MENU_H__ - -+#include <linux/ctype.h> -+ - struct cli_ch_state; - struct menu; +@@ -37,6 +37,8 @@ int menu_default_choice(struct menu *m, + */ + int menu_show(int bootdelay); -@@ -19,6 +21,8 @@ int menu_get_choice(struct menu *m, void - int menu_item_add(struct menu *m, char *item_key, void *item_data); - int menu_destroy(struct menu *m); - int menu_default_choice(struct menu *m, void **choice); -+/* Add KEY_CHOICE support */ +int get_choice_char(int index, char *result); - - /** - * menu_show() Show a boot menu -@@ -41,6 +45,7 @@ struct bootmenu_data { ++ + struct bootmenu_data { + int delay; /* delay for autoboot */ int active; /* active menu entry */ - int count; /* total count of menu entries */ - struct bootmenu_entry *first; /* first menu entry */ -+ bool last_choiced; - }; - - /** enum bootmenu_key - keys that can be returned by the bootmenu */ -@@ -51,6 +56,7 @@ enum bootmenu_key { +@@ -51,6 +53,7 @@ enum bootmenu_key { + BKEY_UP, + BKEY_DOWN, BKEY_SELECT, ++ BKEY_CHOICE, BKEY_QUIT, BKEY_SAVE, -+ BKEY_CHOICE, - - /* 'extra' keys, which are used by menus but not cedit */ - BKEY_PLUS, -@@ -81,7 +87,7 @@ enum bootmenu_key { - * anything else: KEY_NONE - */ - enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, -- struct cli_ch_state *cch); -+ struct cli_ch_state *cch, int *choice); - - /** - * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled -@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop - * Space: BKEY_SPACE - */ - enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, -- struct cli_ch_state *cch); -+ struct cli_ch_state *cch, int *choice); - - /** - * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key -@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b - * @ichar: Keypress to convert (ASCII, including control characters) - * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none - */ --enum bootmenu_key bootmenu_conv_key(int ichar); -+enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar, -+ int *choice); - #endif /* __MENU_H__ */ ---- a/cmd/eficonfig.c -+++ b/cmd/eficonfig.c -@@ -239,7 +239,7 @@ char *eficonfig_choice_entry(void *data) - cli_ch_init(cch); - - while (1) { -- key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch); -+ key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch, NULL); - - switch (key) { - case BKEY_UP: -@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order - - cli_ch_init(cch); - while (1) { -- key = bootmenu_loop(NULL, cch); -+ key = bootmenu_loop(NULL, cch, NULL); - - switch (key) { - case BKEY_PLUS: ---- a/boot/bootflow_menu.c -+++ b/boot/bootflow_menu.c -@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri - - key = 0; - if (ichar) { -- key = bootmenu_conv_key(ichar); -+ key = bootmenu_conv_key(NULL, ichar, NULL); - if (key == BKEY_NONE) - key = ichar; - } diff --git a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch index f017ce92ad..8501105863 100644 --- a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch +++ b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c -@@ -17,7 +17,11 @@ +@@ -18,7 +18,11 @@ uint32_t __weak spl_nand_get_uboot_raw_page(void) { diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index ef20c2dfb6..8c2bcd5437 100644 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -89,7 +89,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> reg = <0x11014000 0x1000>; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME +@@ -148,9 +148,11 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string diff --git a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch index 6202ddf3b0..cd1b7df44e 100644 --- a/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch +++ b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch @@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> }; --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi -@@ -77,6 +77,22 @@ +@@ -53,6 +53,22 @@ #size-cells = <0>; }; @@ -55,19 +55,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> reg = <0x11014000 0x1000>; --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -22,6 +22,7 @@ CONFIG_SYS_MAXARGS=8 - CONFIG_SYS_PBSIZE=1049 +@@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="MT7622> " + CONFIG_SYS_MAXARGS=8 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y -@@ -41,6 +42,10 @@ CONFIG_SYSCON=y - CONFIG_CLK=y +@@ -37,6 +38,9 @@ CONFIG_CLK=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y -+CONFIG_MTD=y + CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTK_SPI_NAND=y +CONFIG_MTK_SPI_NAND_MTD=y diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch index 9dc1a57722..a2c36d8e6b 100644 --- a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt7981-rfb.dtb \ diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch index 15e943b1c0..39b254133e 100644 --- a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch +++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch @@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c -@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor +@@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: @@ -23,17 +23,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] = +@@ -83,7 +83,9 @@ const struct flash_info spi_nor_ids[] = { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, - { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, + { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, ++ { INFO("en25qx128", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ -@@ -149,6 +150,11 @@ const struct flash_info spi_nor_ids[] = +@@ -149,6 +151,11 @@ const struct flash_info spi_nor_ids[] = {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { @@ -45,7 +46,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] = +@@ -520,6 +527,16 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { @@ -62,7 +63,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] = +@@ -583,6 +600,11 @@ const struct flash_info spi_nor_ids[] = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch index 20489d8726..aa03c9b3b9 100644 --- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch +++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -22,15 +22,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile -@@ -1,4 +1,4 @@ +@@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o -+spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o +-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o ++spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o + spinand-objs += toshiba.o winbond.o xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops +@@ -826,6 +826,7 @@ static const struct nand_ops spinand_ops }; static const struct spinand_manufacturer *spinand_manufacturers[] = { @@ -539,7 +540,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> static int winbond_spinand_init(struct spinand_device *spinand) --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -245,6 +245,7 @@ struct spinand_manufacturer { +@@ -244,6 +244,7 @@ struct spinand_manufacturer { }; /* SPI NAND manufacturers */ diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch index 5c90e24ebf..ae69334be6 100644 --- a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig -@@ -815,6 +815,14 @@ config MMC_MTK +@@ -876,6 +876,14 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. @@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config FSL_SDHC_V2_3 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile -@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm +@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o @@ -42,7 +42,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +endif --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c -@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev +@@ -783,18 +783,24 @@ static int msdc_ops_send_cmd(struct udev if (cmd_ret && !(cmd_ret == -EIO && (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || diff --git a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch index ed74eab1e4..f42efe0e3f 100644 --- a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch +++ b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch @@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> -static struct ubi_volume *ubi_find_volume(char *volume) +struct ubi_volume *ubi_find_volume(char *volume) { - struct ubi_volume *vol = NULL; + struct ubi_volume *vol; int i; @@ -262,7 +262,7 @@ static struct ubi_volume *ubi_find_volum return NULL; @@ -45,10 +45,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> struct ubi_volume *vol; --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h -@@ -51,6 +51,10 @@ extern void ubi_exit(void); +@@ -50,6 +50,10 @@ extern void ubi_exit(void); extern int ubi_part(char *part_name, const char *vid_header_offset); - extern int ubi_volume_write(char *volume, void *buf, size_t size); - extern int ubi_volume_read(char *volume, char *buf, size_t size); + extern int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size); + extern int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size); +extern int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, + bool skipcheck); +extern struct ubi_volume *ubi_find_volume(char *volume); diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch index fb8d15ddf9..6eac7e11ad 100644 --- a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch +++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/env/Kconfig +++ b/env/Kconfig -@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND +@@ -688,6 +688,12 @@ config ENV_UBI_VOLUME_REDUND help Name of the redundant volume that you want to store the environment in. @@ -29,7 +29,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> depends on ENV_IS_IN_UBI --- a/env/ubi.c +++ b/env/ubi.c -@@ -106,6 +106,18 @@ static int env_ubi_save(void) +@@ -105,6 +105,18 @@ static int env_ubi_save(void) #endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ #endif /* CONFIG_CMD_SAVEENV */ @@ -48,7 +48,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT static int env_ubi_load(void) { -@@ -135,6 +147,11 @@ static int env_ubi_load(void) +@@ -134,6 +146,10 @@ static int env_ubi_load(void) return -EIO; } @@ -56,17 +56,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME); + env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND); + } -+ - read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, + read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0, CONFIG_ENV_SIZE); if (read1_fail) -@@ -172,6 +189,9 @@ static int env_ubi_load(void) +@@ -171,6 +187,9 @@ static int env_ubi_load(void) return -EIO; } + if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) + env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME); + - if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) { + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to read env from %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch index f22449ae76..cdb83005d9 100644 --- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch +++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch @@ -12,7 +12,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -10,6 +10,11 @@ +@@ -9,9 +9,47 @@ #include <init.h> #include <asm/global_data.h> @@ -24,8 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support DECLARE_GLOBAL_DATA_PTR; int board_init(void) -@@ -23,3 +28,36 @@ int board_late_init(void) - env_relocate(); + { return 0; } + @@ -64,7 +63,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -6,6 +6,11 @@ - #include <common.h> + #include <config.h> #include <asm/global_data.h> +#include <mtd.h> @@ -114,11 +113,10 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support +} --- a/board/mediatek/mt7981/mt7981_rfb.c +++ b/board/mediatek/mt7981/mt7981_rfb.c -@@ -4,7 +4,58 @@ +@@ -4,7 +4,57 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -+#include <common.h> +#include <config.h> +#include <env.h> +#include <init.h> @@ -175,11 +173,10 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support +} --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c -@@ -4,7 +4,60 @@ +@@ -4,7 +4,59 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -+#include <common.h> +#include <config.h> +#include <env.h> +#include <init.h> diff --git a/package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch b/package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch new file mode 100644 index 0000000000..deeb374905 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-01-mtd-spinand-add-support-for-FORESEE-F35SQA002G.patch @@ -0,0 +1,149 @@ +From 49c8e854869d673df8452f24dfa8989cd0f615a8 Mon Sep 17 00:00:00 2001 +From: Martin Kurbanov <mmkurbanov@salutedevices.com> +Date: Mon, 2 Oct 2023 17:04:58 +0300 +Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA002G + +Add support for FORESEE F35SQA002G SPI NAND. +Datasheet: + https://www.longsys.com/uploads/LM-00006FORESEEF35SQA002GDatasheet_1650183701.pdf + +Signed-off-by: Martin Kurbanov <mmkurbanov@salutedevices.com> +Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> +Link: https://lore.kernel.org/linux-mtd/20231002140458.147605-1-mmkurbanov@salutedevices.com +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/foresee.c | 95 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 98 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/foresee.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + +-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o ++spinand-objs := core.o esmt.o foresee.o etron.o gigadevice.o macronix.o micron.o paragon.o + spinand-objs += toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -834,6 +834,7 @@ static const struct spinand_manufacturer + &toshiba_spinand_manufacturer, + &winbond_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, ++ &foresee_spinand_manufacturer, + &xtx_spinand_manufacturer, + }; + +--- /dev/null ++++ b/drivers/mtd/nand/spi/foresee.c +@@ -0,0 +1,97 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2023, SberDevices. All Rights Reserved. ++ * ++ * Author: Martin Kurbanov <mmkurbanov@salutedevices.com> ++ */ ++ ++#ifndef __UBOOT__ ++#include <linux/device.h> ++#include <linux/kernel.h> ++#endif ++#include <linux/mtd/spinand.h> ++ ++#define SPINAND_MFR_FORESEE 0xCD ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ return -ERANGE; ++} ++ ++static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section) ++ return -ERANGE; ++ ++ /* Reserve 2 bytes for the BBM. */ ++ region->offset = 2; ++ region->length = 62; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = { ++ .ecc = f35sqa002g_ooblayout_ecc, ++ .rfree = f35sqa002g_ooblayout_free, ++}; ++ ++static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status) ++{ ++ struct nand_device *nand = spinand_to_nand(spinand); ++ ++ switch (status & STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case STATUS_ECC_HAS_BITFLIPS: ++ return 1; ++ ++ default: ++ break; ++ } ++ ++ /* More than 1-bit error was detected in one or more sectors and ++ * cannot be corrected. ++ */ ++ return -EBADMSG; ++} ++ ++static const struct spinand_info foresee_spinand_table[] = { ++ SPINAND_INFO("F35SQA002G", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&f35sqa002g_ooblayout, ++ f35sqa002g_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer foresee_spinand_manufacturer = { ++ .id = SPINAND_MFR_FORESEE, ++ .name = "FORESEE", ++ .chips = foresee_spinand_table, ++ .nchips = ARRAY_SIZE(foresee_spinand_table), ++ .ops = &foresee_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -252,6 +252,7 @@ extern const struct spinand_manufacturer + extern const struct spinand_manufacturer toshiba_spinand_manufacturer; + extern const struct spinand_manufacturer winbond_spinand_manufacturer; + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; ++extern const struct spinand_manufacturer foresee_spinand_manufacturer; + extern const struct spinand_manufacturer xtx_spinand_manufacturer; + + /** diff --git a/package/boot/uboot-mediatek/patches/101-02-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch b/package/boot/uboot-mediatek/patches/101-02-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch new file mode 100644 index 0000000000..3ad206e399 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/101-02-mtd-spinand-add-support-for-FORESEE-F35SQA001G.patch @@ -0,0 +1,38 @@ +From ae461cde5c559675fc4c0ba351c7c31ace705f56 Mon Sep 17 00:00:00 2001 +From: Bohdan Chubuk <chbgdn@gmail.com> +Date: Sun, 10 Nov 2024 22:50:47 +0200 +Subject: [PATCH] mtd: spinand: add support for FORESEE F35SQA001G + +Add support for FORESEE F35SQA001G SPI NAND. + +Similar to F35SQA002G, but differs in capacity. +Datasheet: + - https://cdn.ozdisan.com/ETicaret_Dosya/704795_871495.pdf + +Tested on Xiaomi AX3000T flashed with OpenWRT. + +Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com> +Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> +--- + drivers/mtd/nand/spi/foresee.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/nand/spi/foresee.c ++++ b/drivers/mtd/nand/spi/foresee.c +@@ -83,6 +83,16 @@ static const struct spinand_info foresee + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&f35sqa002g_ooblayout, + f35sqa002g_ecc_get_status)), ++ SPINAND_INFO("F35SQA001G", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(1, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&f35sqa002g_ooblayout, ++ f35sqa002g_ecc_get_status)), + }; + + static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { diff --git a/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-01-mt7622-enable-pstore.patch index 601e394f5e..f085615e70 100644 --- a/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-01-mt7622-enable-pstore.patch @@ -10,20 +10,20 @@ + }; + + reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <1>; + ranges; + + /* 64 KiB reserved for ramoops/pstore */ + ramoops@42ff0000 { + compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; ++ reg = <0x42ff0000 0x10000>; + record-size = <0x1000>; + }; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { -+ reg = <0 0x43000000 0 0x30000>; ++ reg = <0x43000000 0x30000>; + no-map; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch index 9bfea8f737..81bf3d4eed 100644 --- a/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch @@ -10,26 +10,26 @@ + }; + + reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <1>; + ranges; + + /* 64 KiB reserved for ramoops/pstore */ + ramoops@42ff0000 { + compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; ++ reg = <0x42ff0000 0x10000>; + record-size = <0x1000>; + }; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { -+ reg = <0 0x43000000 0 0x30000>; ++ reg = <0x43000000 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; -+ reg = <0 0x4fc00000 0 0x00100000>; ++ reg = <0x4fc00000 0x00100000>; + }; + }; + diff --git a/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-03-mt7986-enable-pstore.patch index d6ae7f0f13..01ad0f919d 100644 --- a/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-03-mt7986-enable-pstore.patch @@ -10,26 +10,26 @@ + }; + + reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <1>; + ranges; + + /* 64 KiB reserved for ramoops/pstore */ + ramoops@42ff0000 { + compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; ++ reg = <0x42ff0000 0x10000>; + record-size = <0x1000>; + }; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { -+ reg = <0 0x43000000 0 0x30000>; ++ reg = <0x43000000 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; -+ reg = <0 0x4fc00000 0 0x00100000>; ++ reg = <0x4fc00000 0x00100000>; + }; + }; + diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-04-mt7988-enable-pstore.patch index 747aa2e5da..1f339d4b5b 100644 --- a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/103-04-mt7988-enable-pstore.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi -@@ -62,6 +62,30 @@ +@@ -63,6 +63,30 @@ #clock-cells = <0>; }; diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch index 535af4fa09..b9357ea6f9 100644 --- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch +++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch @@ -1,326 +1,268 @@ --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig -@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 - CONFIG_DEBUG_UART_CLOCK=40000000 +@@ -5,37 +5,76 @@ CONFIG_ARCH_MEDIATEK=y + CONFIG_TEXT_BASE=0x41e00000 + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 + CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb" ++CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_TARGET_MT7988=y CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 + CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y CONFIG_DEBUG_UART=y -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y + # CONFIG_EFI_LOADER is not set +CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y -+CONFIG_SPI_BOOT=y -+CONFIG_SD_BOOT=y -+CONFIG_NAND_BOOT=y -+CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y ++CONFIG_SD_BOOT=y ++CONFIG_SPI_BOOT=y # CONFIG_AUTOBOOT is not set CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 -@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049 ++CONFIG_PRE_CONSOLE_BUFFER=y + CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y + CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y + # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_ELF is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_ELF=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y - CONFIG_CMD_PING=y -+CONFIG_CMD_SF=y - CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y +-CONFIG_CMD_PING=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_UBI=y -+CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y + CONFIG_CMD_SMC=y +-CONFIG_DOS_PARTITION=y +-CONFIG_EFI_PARTITION=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y + CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PCI=y -+CONFIG_MTD=y + CONFIG_USE_IPADDR=y + CONFIG_IPADDR="192.168.1.1" + CONFIG_USE_NETMASK=y +@@ -44,21 +83,32 @@ CONFIG_USE_SERVERIP=y + CONFIG_SERVERIP="192.168.1.2" + CONFIG_PROT_TCP=y + CONFIG_NET_RANDOM_ETHADDR=y +-CONFIG_REGMAP=y +-CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y + CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y + CONFIG_MMC_HS200_SUPPORT=y + CONFIG_MMC_MTK=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_MTD_RAW_NAND is not set -+CONFIG_DM_PCI=y + CONFIG_PHY_FIXED=y + CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y + CONFIG_PINCTRL=y + CONFIG_PINCONF=y + CONFIG_PINCTRL_MT7988=y + CONFIG_POWER_DOMAIN=y + CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y + CONFIG_DM_PWM=y + CONFIG_PWM_MTK=y + CONFIG_RAM=y +@@ -67,5 +117,8 @@ CONFIG_MTK_SERIAL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y + CONFIG_MTK_SPIM=y +-CONFIG_LZO=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 - CONFIG_DOS_PARTITION=y - CONFIG_EFI_PARTITION=y - CONFIG_PARTITION_TYPE_GUID=y -@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y - CONFIG_REGMAP=y - CONFIG_SYSCON=y - CONFIG_CLK=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y - CONFIG_MMC_HS200_SUPPORT=y - CONFIG_MMC_MTK=y - CONFIG_MTD=y ++CONFIG_ZSTD=y + CONFIG_HEXDUMP=y --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig -@@ -11,7 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 +@@ -6,36 +6,76 @@ CONFIG_TEXT_BASE=0x41e00000 + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" ++CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_TARGET_MT7988=y + CONFIG_SYS_LOAD_ADDR=0x44000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 + CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PCI=y CONFIG_DEBUG_UART=y + # CONFIG_EFI_LOADER is not set -# CONFIG_AUTOBOOT is not set -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y +CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y -+CONFIG_SPI_BOOT=y -+CONFIG_SD_BOOT=y -+CONFIG_NAND_BOOT=y -+CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y ++CONFIG_SD_BOOT=y ++CONFIG_SPI_BOOT=y ++CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_LOG=y -@@ -22,15 +39,120 @@ CONFIG_SYS_PBSIZE=1049 ++CONFIG_BOARD_LATE_INIT=y + CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y + # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_ELF is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_ELF=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y - CONFIG_CMD_PING=y -+CONFIG_CMD_SF=y - CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y +-CONFIG_CMD_PING=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_UBI=y -+CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_MTD_RAW_NAND is not set -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y ++CONFIG_CMD_HASH=y + CONFIG_CMD_SMC=y +-CONFIG_DOS_PARTITION=y +-CONFIG_EFI_PARTITION=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y + CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_EMBED=y -+CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" - CONFIG_DOS_PARTITION=y - CONFIG_EFI_PARTITION=y - CONFIG_PARTITION_TYPE_GUID=y -@@ -46,6 +168,9 @@ CONFIG_PROT_TCP=y - CONFIG_REGMAP=y - CONFIG_SYSCON=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y + CONFIG_USE_IPADDR=y + CONFIG_IPADDR="192.168.1.1" + CONFIG_USE_NETMASK=y +@@ -44,9 +84,13 @@ CONFIG_USE_SERVERIP=y + CONFIG_SERVERIP="192.168.1.2" + CONFIG_PROT_TCP=y + CONFIG_NET_RANDOM_ETHADDR=y +-CONFIG_REGMAP=y +-CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y CONFIG_CLK=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y CONFIG_MTD=y +@@ -64,13 +108,20 @@ CONFIG_SPI_FLASH_WINBOND=y + CONFIG_SPI_FLASH_XMC=y + CONFIG_SPI_FLASH_XTX=y + CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y + CONFIG_PHY_FIXED=y + CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y + CONFIG_PINCTRL=y + CONFIG_PINCONF=y + CONFIG_PINCTRL_MT7988=y + CONFIG_POWER_DOMAIN=y + CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y + CONFIG_DM_PWM=y + CONFIG_PWM_MTK=y + CONFIG_RAM=y +@@ -79,5 +130,8 @@ CONFIG_MTK_SERIAL=y + CONFIG_SPI=y + CONFIG_DM_SPI=y + CONFIG_MTK_SPIM=y +-CONFIG_LZO=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_ZSTD=y + CONFIG_HEXDUMP=y --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts -@@ -144,6 +144,23 @@ - compatible = "spi-nand"; - reg = <0>; +@@ -195,6 +195,23 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; diff --git a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch index 3a3f8d0e1e..67bf1955c2 100644 --- a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch +++ b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch @@ -1,6 +1,6 @@ --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig -@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y +@@ -31,6 +31,9 @@ CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch index bd4c6b55f0..20c618e065 100644 --- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch +++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch @@ -1,9 +1,9 @@ --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig -@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y + # CONFIG_EFI_LOADER is not set -# CONFIG_AUTOBOOT is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_PRODUCT_NAME="" @@ -22,9 +22,9 @@ +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb" - CONFIG_LOGLEVEL=7 - CONFIG_LOG=y -@@ -24,9 +39,23 @@ CONFIG_SYS_PBSIZE=1049 + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 +@@ -25,9 +40,23 @@ CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set @@ -49,7 +49,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y -@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y +@@ -37,13 +66,35 @@ CONFIG_CMD_PART=y CONFIG_CMD_READ=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y @@ -87,10 +87,10 @@ CONFIG_CLK=y --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig -@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -12,7 +12,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y + # CONFIG_EFI_LOADER is not set -# CONFIG_AUTOBOOT is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_PRODUCT_NAME="" @@ -106,13 +106,12 @@ +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_BOOT=y -+CONFIG_NAND_BOOT=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="mt7981-rfb" - CONFIG_LOGLEVEL=7 - CONFIG_LOG=y -@@ -22,23 +38,74 @@ CONFIG_SYS_PBSIZE=1049 + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 +@@ -23,23 +38,74 @@ CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set @@ -191,10 +190,10 @@ CONFIG_MTD_SPI_NAND=y --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig -@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -14,7 +14,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 - CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y + # CONFIG_EFI_LOADER is not set -# CONFIG_AUTOBOOT is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SMBIOS_PRODUCT_NAME="" @@ -213,9 +212,9 @@ +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb" - CONFIG_LOGLEVEL=7 - CONFIG_LOG=y -@@ -24,9 +39,23 @@ CONFIG_SYS_PBSIZE=1049 + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 +@@ -25,9 +40,23 @@ CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set @@ -240,7 +239,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y -@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y +@@ -37,13 +66,35 @@ CONFIG_CMD_PART=y CONFIG_CMD_READ=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y @@ -278,7 +277,7 @@ CONFIG_CLK=y --- a/configs/mt7981_snfi_nand_rfb_defconfig +++ b/configs/mt7981_snfi_nand_rfb_defconfig -@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 +@@ -12,7 +12,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_SYS_LOAD_ADDR=0x46000000 CONFIG_DEBUG_UART=y @@ -297,13 +296,12 @@ +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_SPI_BOOT=y -+CONFIG_NAND_BOOT=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb" CONFIG_LOGLEVEL=7 CONFIG_LOG=y -@@ -22,22 +38,73 @@ CONFIG_SYS_PBSIZE=1049 +@@ -22,22 +37,73 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set diff --git a/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch index a58c81b656..eb68af9ee8 100644 --- a/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch +++ b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch @@ -1,9 +1,9 @@ --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts -@@ -143,6 +143,37 @@ - compatible = "spi-nand"; - reg = <0>; +@@ -153,6 +153,37 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; @@ -38,10 +38,10 @@ }; }; -@@ -164,6 +195,37 @@ - compatible = "jedec,spi-nor"; - reg = <0>; +@@ -176,6 +207,37 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch deleted file mode 100644 index 3bf033f814..0000000000 --- a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -116,7 +116,6 @@ dumpimage-mkimage-objs := aisimage.o \ - imximage.o \ - imx8image.o \ - imx8mimage.o \ -- kwbimage.o \ - generated/lib/md5.o \ - lpc32xximage.o \ - mxsimage.o \ diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch index 9a9224963d..6929453250 100644 --- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch +++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT $@ +@@ -1094,7 +1094,7 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; } quiet_cmd_lzma = LZMA $@ diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch index 86a424e8b7..d04a61432e 100644 --- a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch +++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d +@@ -1162,6 +1162,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1190,6 +1191,13 @@ err_cert: +@@ -1215,6 +1216,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch index f8e8659952..2a71a4eb92 100644 --- a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch +++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch @@ -58,7 +58,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -77,6 +77,37 @@ config PHY_ADIN +@@ -83,6 +83,37 @@ config PHY_ADIN help Add support for configuring RGMII on Analog Devices ADIN PHYs. @@ -122,7 +122,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + +/* INCLUDE FILE DECLARATIONS + */ -+#include <common.h> ++#include <config.h> +#include <phy.h> +#include <errno.h> +#include <version.h> @@ -1028,7 +1028,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + +/* INCLUDE FILE DECLARATIONS +*/ -+#include <common.h> ++#include <config.h> +#include <eth_phy.h> +#include <phy.h> +#include <errno.h> @@ -1421,7 +1421,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + } + +#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI -+ ret = ubi_volume_read("en8811h-fw", firmware_buf, EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); ++ ret = ubi_volume_read("en8811h-fw", firmware_buf, 0, EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); + if (ret) { + printf("[Airoha] read firmware from UBI failed.\n"); + free(firmware_buf); @@ -1909,7 +1909,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + --- a/drivers/net/eth-phy-uclass.c +++ b/drivers/net/eth-phy-uclass.c -@@ -155,7 +155,7 @@ static int eth_phy_of_to_plat(struct ude +@@ -154,7 +154,7 @@ static int eth_phy_of_to_plat(struct ude return 0; } diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index 28175e02e8..082f99b767 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -1,6 +1,6 @@ --- a/cmd/bootm.c +++ b/cmd/bootm.c -@@ -245,6 +245,67 @@ U_BOOT_CMD( +@@ -260,6 +260,67 @@ U_BOOT_CMD( /* iminfo - print header info for a requested image */ /*******************************************************************/ #if defined(CONFIG_CMD_IMI) @@ -70,7 +70,7 @@ { --- a/boot/image-fit.c +++ b/boot/image-fit.c -@@ -2051,6 +2051,47 @@ static const char *fit_get_image_type_pr +@@ -2047,6 +2047,47 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -120,7 +120,7 @@ int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec, +@@ -1112,6 +1112,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch index a99b77be08..1c1071bafc 100644 --- a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch +++ b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch @@ -1,6 +1,6 @@ --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -452,7 +452,11 @@ static void menu_display_statusline(stru +@@ -463,7 +463,11 @@ static void menu_display_statusline(stru printf(ANSI_CURSOR_POSITION, 1, 1); puts(ANSI_CLEAR_LINE); printf(ANSI_CURSOR_POSITION, 2, 3); @@ -13,7 +13,7 @@ puts(ANSI_CLEAR_LINE_TO_END); printf(ANSI_CURSOR_POSITION, 3, 1); puts(ANSI_CLEAR_LINE); -@@ -537,6 +541,7 @@ static enum bootmenu_ret bootmenu_show(i +@@ -548,6 +552,7 @@ static enum bootmenu_ret bootmenu_show(i return BOOTMENU_RET_FAIL; } @@ -24,10 +24,10 @@ --- a/include/menu.h +++ b/include/menu.h @@ -45,6 +45,7 @@ struct bootmenu_data { - int active; /* active menu entry */ + int last_active; /* last active menu entry */ int count; /* total count of menu entries */ struct bootmenu_entry *first; /* first menu entry */ + char *mtitle; /* custom menu title */ - bool last_choiced; }; + /** enum bootmenu_key - keys that can be returned by the bootmenu */ diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index 7bf87ef7b5..85d65ab48b 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS +@@ -692,6 +692,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. @@ -15,7 +15,7 @@ help --- a/cmd/nvedit.c +++ b/cmd/nvedit.c -@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in +@@ -273,6 +273,60 @@ static int do_env_ask(struct cmd_tbl *cm } #endif @@ -69,14 +69,14 @@ + unmap_sysmem(buf); + + /* Continue calling setenv code */ -+ return _do_env_set(flag, 3, local_args, H_INTERACTIVE); ++ return env_do_env_set(flag, 3, local_args, H_INTERACTIVE); +} +#endif + #if defined(CONFIG_CMD_ENV_CALLBACK) static int print_static_binding(const char *var_name, const char *callback_name, void *priv) -@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = { +@@ -1089,6 +1143,9 @@ static struct cmd_tbl cmd_env_sub[] = { U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""), #endif U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), @@ -86,7 +86,7 @@ #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env, +@@ -1172,6 +1229,9 @@ U_BOOT_LONGHELP(env, #if defined(CONFIG_CMD_NVEDIT_EFI) "env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n" #endif @@ -96,7 +96,7 @@ #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -@@ -1392,6 +1452,17 @@ U_BOOT_CMD( +@@ -1280,6 +1340,17 @@ U_BOOT_CMD( ); #endif diff --git a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch index fd5fdd814b..e03b212a74 100644 --- a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch +++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch @@ -1,6 +1,6 @@ --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c -@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_ +@@ -79,7 +79,7 @@ ulong mmc_berase(struct blk_desc *block_ u32 start_rem, blkcnt_rem, erase_args = 0; struct mmc *mmc = find_mmc_device(dev_num); lbaint_t blk = 0, blk_r = 0; diff --git a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch index f087bec72a..c2ecbb2c33 100644 --- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch +++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch @@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com> --- a/boot/image-fdt.c +++ b/boot/image-fdt.c -@@ -637,6 +637,12 @@ int image_setup_libfdt(struct bootm_head +@@ -612,6 +612,12 @@ int image_setup_libfdt(struct bootm_head images->fit_uname_cfg, strlen(images->fit_uname_cfg) + 1, 1); diff --git a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch b/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch index cb1648f5e8..6ed50907e3 100644 --- a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch +++ b/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch @@ -18,7 +18,7 @@ Signed-off-by: John Crispin <john@phrozen.org> #include <dt-bindings/clock/mt7981-clk.h> #include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/pinctrl/mt65xx.h> -@@ -342,4 +343,50 @@ +@@ -346,4 +347,50 @@ status = "disabled"; }; @@ -31,11 +31,11 @@ Signed-off-by: John Crispin <john@phrozen.org> + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; -+ clocks = <&infracfg_ao CK_INFRA_IUSB_SYS_CK>, -+ <&infracfg_ao CK_INFRA_IUSB_CK>, -+ <&infracfg_ao CK_INFRA_IUSB_133_CK>, -+ <&infracfg_ao CK_INFRA_IUSB_66M_CK>, -+ <&topckgen CK_TOP_U2U3_XHCI_SEL>; ++ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, ++ <&infracfg CLK_INFRA_IUSB_CK>, ++ <&infracfg CLK_INFRA_IUSB_133_CK>, ++ <&infracfg CLK_INFRA_IUSB_66M_CK>, ++ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", @@ -54,7 +54,7 @@ Signed-off-by: John Crispin <john@phrozen.org> + + u2port0: usb-phy@11e10000 { + reg = <0x11e10000 0x700>; -+ clocks = <&topckgen CK_TOP_USB_FRMCNT_SEL>; ++ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; @@ -62,7 +62,7 @@ Signed-off-by: John Crispin <john@phrozen.org> + + u3port0: usb-phy@11e10700 { + reg = <0x11e10700 0x900>; -+ clocks = <&topckgen CK_TOP_USB3_PHY_SEL>; ++ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; diff --git a/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch b/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch index 86c48badda..5fc3d0a344 100644 --- a/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch +++ b/package/boot/uboot-mediatek/patches/300-mt7623-fix-mmc-get-env-dev.patch @@ -2,7 +2,7 @@ +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -5,6 +5,7 @@ - #include <common.h> + #include <config.h> #include <mmc.h> +#include <part.h> #include <asm/global_data.h> diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 65990156c2..66dd43da4b 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -1,8 +1,8 @@ --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -6,9 +6,16 @@ +@@ -5,9 +5,16 @@ + */ - #include <common.h> #include <config.h> +#include <dm.h> +#include <button.h> @@ -17,11 +17,12 @@ #include <mtd.h> #include <linux/mtd/mtd.h> -@@ -24,7 +31,22 @@ int board_init(void) +@@ -21,6 +28,28 @@ int board_init(void) + return 0; + } - int board_late_init(void) - { -- gd->env_valid = 1; //to load environment variable from persistent store ++int board_late_init(void) ++{ + struct udevice *dev; + + if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { @@ -38,12 +39,16 @@ + } + } + - env_relocate(); - return 0; - } ++ env_relocate(); ++ return 0; ++ } ++ + int board_nmbm_init(void) + { + #ifdef CONFIG_ENABLE_NAND_NMBM --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -151,4 +151,11 @@ config MTK_BROM_HEADER_INFO +@@ -155,4 +155,11 @@ config MTK_BROM_HEADER_INFO source "board/mediatek/mt7629/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch index b8d89058a2..a6e4229dd5 100644 --- a/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch @@ -3,7 +3,7 @@ @@ -4,9 +4,18 @@ */ - #include <common.h> + #include <config.h> +#include <dm.h> +#include <button.h> +#include <env.h> diff --git a/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch index 45290149f3..01b4b52952 100644 --- a/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch @@ -1,8 +1,8 @@ --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c -@@ -6,9 +6,16 @@ +@@ -5,9 +5,16 @@ + */ - #include <common.h> #include <config.h> +#include <dm.h> +#include <button.h> @@ -17,7 +17,7 @@ #include <mtd.h> #include <linux/mtd/mtd.h> -@@ -24,7 +31,22 @@ int board_init(void) +@@ -23,7 +30,22 @@ int board_init(void) int board_late_init(void) { diff --git a/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch index fc44334982..b3ac2aa27f 100644 --- a/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch @@ -1,8 +1,8 @@ --- a/board/mediatek/mt7981/mt7981_rfb.c +++ b/board/mediatek/mt7981/mt7981_rfb.c -@@ -6,9 +6,16 @@ +@@ -5,9 +5,16 @@ + */ - #include <common.h> #include <config.h> +#include <dm.h> +#include <button.h> @@ -17,7 +17,7 @@ #include <mtd.h> #include <linux/mtd/mtd.h> -@@ -24,7 +31,22 @@ int board_init(void) +@@ -23,7 +30,22 @@ int board_init(void) int board_late_init(void) { diff --git a/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch index 2bbc5c1005..3f239c984a 100644 --- a/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch @@ -1,10 +1,9 @@ --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c -@@ -4,7 +4,43 @@ +@@ -4,7 +4,42 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -+#include <common.h> +#include <config.h> +#include <dm.h> +#include <button.h> diff --git a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch index 28d7e0a3f6..308108e621 100644 --- a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch +++ b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch @@ -1,6 +1,6 @@ --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c -@@ -11,7 +11,9 @@ +@@ -10,7 +10,9 @@ #include <env.h> #include <init.h> #include <asm/global_data.h> @@ -10,7 +10,7 @@ #ifndef CONFIG_RESET_BUTTON_LABEL #define CONFIG_RESET_BUTTON_LABEL "reset" -@@ -44,3 +46,54 @@ int board_late_init(void) +@@ -43,3 +45,54 @@ int board_late_init(void) env_relocate(); return 0; } diff --git a/package/boot/uboot-mediatek/patches/311-mt7986-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/311-mt7986-select-rootdisk.patch index 3312162765..3588dc2a88 100644 --- a/package/boot/uboot-mediatek/patches/311-mt7986-select-rootdisk.patch +++ b/package/boot/uboot-mediatek/patches/311-mt7986-select-rootdisk.patch @@ -1,6 +1,6 @@ --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c -@@ -11,7 +11,9 @@ +@@ -10,7 +10,9 @@ #include <env.h> #include <init.h> #include <asm/global_data.h> @@ -10,7 +10,7 @@ #ifndef CONFIG_RESET_BUTTON_LABEL #define CONFIG_RESET_BUTTON_LABEL "reset" -@@ -83,3 +85,54 @@ int board_nmbm_init(void) +@@ -82,3 +84,54 @@ int board_nmbm_init(void) return 0; } diff --git a/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch index 70cbf6b463..44caf8465c 100644 --- a/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch +++ b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch @@ -1,6 +1,6 @@ --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -11,7 +11,9 @@ +@@ -10,7 +10,9 @@ #include <env.h> #include <init.h> #include <asm/global_data.h> @@ -10,7 +10,7 @@ #ifndef CONFIG_RESET_BUTTON_LABEL #define CONFIG_RESET_BUTTON_LABEL "reset" -@@ -22,10 +24,43 @@ +@@ -21,10 +23,43 @@ #include <nmbm/nmbm.h> #include <nmbm/nmbm-mtd.h> @@ -54,7 +54,7 @@ return 0; } -@@ -83,3 +118,84 @@ int board_nmbm_init(void) +@@ -82,3 +117,84 @@ int board_nmbm_init(void) return 0; } diff --git a/package/boot/uboot-mediatek/patches/314-mt7981-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/314-mt7981-select-rootdisk.patch new file mode 100644 index 0000000000..0d515384b7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/314-mt7981-select-rootdisk.patch @@ -0,0 +1,102 @@ +--- a/board/mediatek/mt7981/mt7981_rfb.c ++++ b/board/mediatek/mt7981/mt7981_rfb.c +@@ -10,7 +10,9 @@ + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <asm/io.h> + #include <linux/delay.h> ++#include <linux/libfdt.h> + + #ifndef CONFIG_RESET_BUTTON_LABEL + #define CONFIG_RESET_BUTTON_LABEL "reset" +@@ -80,3 +82,54 @@ int board_nmbm_init(void) + + return 0; + } ++ ++#define MT7981_BOOT_NOR 0 ++#define MT7981_BOOT_SPIM_NAND 1 /* ToDo: fallback to SD */ ++#define MT7981_BOOT_EMMC 2 ++#define MT7981_BOOT_SNFI_NAND 3 /* ToDo (treated as SD) */ ++ ++int ft_system_setup(void *blob, struct bd_info *bd) ++{ ++ const u32 *media_handle_p; ++ int chosen, len, ret; ++ const char *media; ++ u32 media_handle; ++ ++ switch ((readl(0x11d006f0) & 0xc0) >> 6) { ++ case MT7981_BOOT_NOR: ++ media = "rootdisk-nor"; ++ break ++ ;; ++ case MT7981_BOOT_SPIM_NAND: ++ media = "rootdisk-spim-nand"; ++ break ++ ;; ++ case MT7981_BOOT_EMMC: ++ media = "rootdisk-emmc"; ++ break ++ ;; ++ case MT7981_BOOT_SNFI_NAND: ++ media = "rootdisk-sd"; ++ break ++ ;; ++ } ++ ++ chosen = fdt_path_offset(blob, "/chosen"); ++ if (chosen <= 0) ++ return 0; ++ ++ media_handle_p = fdt_getprop(blob, chosen, media, &len); ++ if (media_handle_p <= 0 || len != 4) ++ return 0; ++ ++ media_handle = *media_handle_p; ++ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle)); ++ if (ret) { ++ printf("cannot set media phandle %s as rootdisk /chosen node\n", media); ++ return ret; ++ } ++ ++ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle)); ++ ++ return 0; ++} +--- a/configs/mt7981_emmc_rfb_defconfig ++++ b/configs/mt7981_emmc_rfb_defconfig +@@ -113,3 +113,4 @@ CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y + CONFIG_FAT_WRITE=y + CONFIG_HEXDUMP=y ++CONFIG_OF_SYSTEM_SETUP=y +--- a/configs/mt7981_nor_rfb_defconfig ++++ b/configs/mt7981_nor_rfb_defconfig +@@ -126,3 +126,4 @@ CONFIG_DM_SPI=y + CONFIG_MTK_SPIM=y + CONFIG_HEXDUMP=y + CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_OF_SYSTEM_SETUP=y +--- a/configs/mt7981_rfb_defconfig ++++ b/configs/mt7981_rfb_defconfig +@@ -134,3 +134,4 @@ CONFIG_SPI=y + CONFIG_DM_SPI=y + CONFIG_MTK_SPIM=y + CONFIG_HEXDUMP=y ++CONFIG_OF_SYSTEM_SETUP=y +--- a/configs/mt7981_sd_rfb_defconfig ++++ b/configs/mt7981_sd_rfb_defconfig +@@ -113,3 +113,4 @@ CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y + CONFIG_FAT_WRITE=y + CONFIG_HEXDUMP=y ++CONFIG_OF_SYSTEM_SETUP=y +--- a/configs/mt7981_snfi_nand_rfb_defconfig ++++ b/configs/mt7981_snfi_nand_rfb_defconfig +@@ -119,3 +119,4 @@ CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y + CONFIG_HEXDUMP=y + CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_OF_SYSTEM_SETUP=y diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch index ab3424e6b5..05ccdb8c75 100644 --- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch @@ -1,6 +1,6 @@ --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig -@@ -7,34 +7,106 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 +@@ -7,34 +7,67 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 @@ -8,138 +8,110 @@ +CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" ++CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_TARGET_MT7623=y ++CONFIG_RESET_BUTTON_LABEL="factory" + CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x84000000 ++CONFIG_PCI=y ++CONFIG_AHCI=y + # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_AUTOBOOT_KEYED=y -+CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_BOARD_LATE_INIT=y +# CONFIG_BOOTSTD is not set -+# CONFIG_BOOT_DEFAULTS is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 -+CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2.dtb" + CONFIG_SYS_PBSIZE=1049 ++CONFIG_LOGLEVEL=7 CONFIG_SYS_CONSOLE_IS_IN_ENV=y -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r2_env" -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_RESET_BUTTON_LABEL="factory" -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_CMD_ENV_FLAGS=y ++CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="U-Boot> " -+CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="MT7623> " CONFIG_SYS_MAXARGS=8 - CONFIG_SYS_PBSIZE=1049 - CONFIG_SYS_BOOTM_LEN=0x4000000 ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y -+CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -+# CONFIG_CMD_GPT is not set -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_MBR=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y -# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_SATA=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SATA=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y -+CONFIG_CMD_SCSI=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_ETH=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_DM_MMC=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PCI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_FS_UUID=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r2_env" ++CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y -@@ -46,6 +118,12 @@ CONFIG_CLK=y +@@ -42,18 +75,31 @@ CONFIG_SERVERIP="192.168.1.2" + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y + CONFIG_CLK=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y + # CONFIG_MMC_QUIRKS is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PHY=y -+CONFIG_PINCONF=y CONFIG_PHY_FIXED=y CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y CONFIG_PINCTRL=y -@@ -55,10 +133,13 @@ CONFIG_POWER_DOMAIN=y + CONFIG_PINCONF=y + CONFIG_PINCTRL_MT7623=y + CONFIG_POWER_DOMAIN=y CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y CONFIG_SYSRESET=y - CONFIG_SYSRESET_WATCHDOG=y +@@ -61,4 +107,5 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y -+CONFIG_VERSION_VARIABLE=y CONFIG_WDT_MTK=y ++CONFIG_RANDOM_UUID=y CONFIG_LZMA=y - # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set --- /dev/null -+++ b/bananapi_bpi-r2_env ++++ b/defenvs/bananapi_bpi-r2_env @@ -0,0 +1,69 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch index 58c62dc3ef..243ba9d7c2 100644 --- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch @@ -1,6 +1,6 @@ --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig -@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 +@@ -7,32 +7,65 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 @@ -8,139 +8,108 @@ +CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" ++CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_TARGET_MT7623=y ++CONFIG_RESET_BUTTON_LABEL="factory" + CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x84000000 ++CONFIG_PCI=y ++CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y -+CONFIG_LOGLEVEL=7 -+CONFIG_LOG=y -+CONFIG_AUTOBOOT_KEYED=y -+CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_BOARD_LATE_INIT=y +# CONFIG_BOOTSTD is not set -+# CONFIG_BOOT_DEFAULTS is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 -+CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y CONFIG_DEFAULT_FDT_FILE="mt7623a-unielec-u7623-02-emmc.dtb" + CONFIG_SYS_PBSIZE=1049 ++CONFIG_LOGLEVEL=7 CONFIG_SYS_CONSOLE_IS_IN_ENV=y -+CONFIG_DEFAULT_ENV_FILE="unielec_u7623-02_env" -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_RESET_BUTTON_LABEL="factory" -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_CMD_ENV_FLAGS=y ++CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="U-Boot> " -+CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="MT7623> " CONFIG_SYS_MAXARGS=8 - CONFIG_SYS_PBSIZE=1049 - CONFIG_SYS_BOOTM_LEN=0x4000000 ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y -+CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -+# CONFIG_CMD_GPT is not set -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_MBR=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y -# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_SATA=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SATA=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y -+CONFIG_CMD_READ=y -+CONFIG_CMD_SCSI=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_ETH=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_DM_MMC=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PCI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=0 -+CONFIG_ENV_OVERWRITE=y - CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/unielec_u7623-02_env" ++CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y -@@ -45,6 +121,11 @@ CONFIG_CLK=y +@@ -40,18 +73,31 @@ CONFIG_SERVERIP="192.168.1.2" + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y + CONFIG_CLK=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y + # CONFIG_MMC_QUIRKS is not set CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PHY=y CONFIG_PHY_FIXED=y CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y CONFIG_PINCTRL=y -@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y + CONFIG_PINCONF=y + CONFIG_PINCTRL_MT7623=y + CONFIG_POWER_DOMAIN=y CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y CONFIG_SYSRESET=y - CONFIG_SYSRESET_WATCHDOG=y +@@ -59,4 +105,5 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y -+CONFIG_VERSION_VARIABLE=y CONFIG_WDT_MTK=y ++CONFIG_RANDOM_UUID=y CONFIG_LZMA=y --- /dev/null -+++ b/unielec_u7623-02_env ++++ b/defenvs/unielec_u7623-02_env @@ -0,0 +1,47 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch index 6ee8729674..3a2faf5aec 100644 --- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch +++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch @@ -1,172 +1,136 @@ --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig -@@ -0,0 +1,164 @@ +@@ -0,0 +1,128 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_ENV_SIZE=0x80000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_ENV_OFFSET_REDUND=0x480000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-sdmmc_env" -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_UBI=y -+CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x480000 -+CONFIG_ENV_SIZE=0x80000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-sdmmc_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r64-sdmmc_env ++++ b/defenvs/bananapi_bpi-r64-sdmmc_env @@ -0,0 +1,81 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -251,161 +215,126 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig -@@ -0,0 +1,152 @@ +@@ -0,0 +1,117 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_ENV_SIZE=0x80000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_ENV_OFFSET_REDUND=0x480000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-emmc_env" -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-bananapi-bpi-r64" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mt7622-bananapi-bpi-r64" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y ++CONFIG_CMD_CACHE=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_MMC_ENV_DEV=0 -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x480000 -+CONFIG_ENV_SIZE=0x80000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-emmc_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=0 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r64-emmc_env ++++ b/defenvs/bananapi_bpi-r64-emmc_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -465,154 +394,117 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-snand_defconfig -@@ -0,0 +1,145 @@ +@@ -0,0 +1,108 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env" ++CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7622-bananapi-bpi-r64.dtb" ++CONFIG_BOARD_LATE_INIT=y +CONFIG_SYS_PROMPT="MT7622> " ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_EFIDEBUG=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_USB=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_UBI=y -+CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_EFIDEBUG=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r64-snand_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.3" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_MTK=y +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_MTK=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.3" ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r64-snand_env ++++ b/defenvs/bananapi_bpi-r64-snand_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -663,8 +555,8 @@ +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data +ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 -+ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ; fi -+ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ; fi ++ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi ++ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi +_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch index dcbf8b953f..395b4494af 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch +++ b/package/boot/uboot-mediatek/patches/407-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch @@ -18,10 +18,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x280000 + CONFIG_SYS_LOAD_ADDR=0x4007ff28 CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 - CONFIG_SYS_LOAD_ADDR=0x4007ff28 -@@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y +@@ -26,6 +28,9 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y @@ -29,5 +29,5 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +CONFIG_ENV_MTD_NAME="spi-nand0" +CONFIG_ENV_SIZE_REDUND=0x40000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y - CONFIG_NET_RANDOM_ETHADDR=y CONFIG_USE_IPADDR=y + CONFIG_IPADDR="192.168.1.1" diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index ca8fb32bea..3a76d8fd32 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -1,146 +1,116 @@ --- /dev/null +++ b/configs/mt7622_linksys_e8450_defconfig -@@ -0,0 +1,140 @@ +@@ -0,0 +1,110 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BOOTP_SEND_HOSTNAME=y -+CONFIG_DEFAULT_ENV_FILE="linksys_e8450_env" +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi" ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=25000000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi" ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-linksys-e8450" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mt7622-linksys-e8450" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPARTS=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_UBI=y -+CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_USB=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/linksys_e8450_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_MTD=y +CONFIG_DM_MTD=y -+CONFIG_DM_GPIO=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts @@ -0,0 +1,214 @@ @@ -360,7 +330,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1192,6 +1192,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ @@ -369,7 +339,7 @@ mt7629-rfb.dtb \ mt7981-rfb.dtb \ --- /dev/null -+++ b/linksys_e8450_env ++++ b/defenvs/linksys_e8450_env @@ -0,0 +1,55 @@ +ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index bbd05fe41f..a80fd3576f 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -1,452 +1,350 @@ --- /dev/null +++ b/configs/mt7622_ubnt_unifi-6-lr-v1_defconfig -@@ -0,0 +1,147 @@ +@@ -0,0 +1,113 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" -+CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="nor0" -+CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0xc0000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_BOARD_LATE_INIT=y ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" +CONFIG_RESET_BUTTON_SETTLE_DELAY=400 -+CONFIG_BOOTP_SEND_HOSTNAME=y -+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env" ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=25000000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" +CONFIG_DEBUG_UART=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y ++# CONFIG_LEGACY_IMAGE_FORMAT is not set +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " -+# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_EFI is not set -+# CONFIG_EFI_LOADER is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_BOOTEFI is not set -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y +# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_GPIO=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPARTS=y -+# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+# CONFIG_CMD_UNLZ4 is not set -+CONFIG_CMD_ASKENV=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SOURCE=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_MDIO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_MMC is not set -+CONFIG_DM_SERIAL=y -+CONFIG_DM_SPI=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_HUSH_PARSER=y -+# CONFIG_PARTITION_UUIDS is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+# CONFIG_LED is not set -+# CONFIG_LZ4 is not set ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_PHY=y -+CONFIG_PHY_FIXED=y -+CONFIG_PHYLIB_10G=y -+CONFIG_PHY_AQUANTIA=y ++CONFIG_GPIO_HOG=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 ++CONFIG_PHY_AQUANTIA=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_ETH_PHY=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_MTD=y -+# CONFIG_MMC is not set ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y ++CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y -+CONFIG_MTK_SNFI_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SNOR=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_HEXDUMP=y ++CONFIG_MTK_SNFI_SPI=y +CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_SPI_FLASH=y -+CONFIG_SPI_FLASH_BAR=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_UNLOCK_ALL=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7622_ubnt_unifi-6-lr-v2_defconfig -@@ -0,0 +1,147 @@ +@@ -0,0 +1,113 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" -+CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="nor0" -+CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0xc0000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_BOARD_LATE_INIT=y ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" +CONFIG_RESET_BUTTON_SETTLE_DELAY=400 -+CONFIG_BOOTP_SEND_HOSTNAME=y -+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr-v2_env" ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=25000000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" +CONFIG_DEBUG_UART=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y ++# CONFIG_LEGACY_IMAGE_FORMAT is not set +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " -+# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_EFI is not set -+# CONFIG_EFI_LOADER is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_BOOTEFI is not set -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y +# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_GPIO=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPARTS=y -+# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+# CONFIG_CMD_UNLZ4 is not set -+CONFIG_CMD_ASKENV=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SOURCE=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_MDIO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_MMC is not set -+CONFIG_DM_SERIAL=y -+CONFIG_DM_SPI=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_HUSH_PARSER=y -+# CONFIG_PARTITION_UUIDS is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+# CONFIG_LED is not set -+# CONFIG_LZ4 is not set ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr-v2_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_PHY=y -+CONFIG_PHY_FIXED=y -+CONFIG_PHYLIB_10G=y -+CONFIG_PHY_AQUANTIA=y ++CONFIG_GPIO_HOG=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 ++CONFIG_PHY_AQUANTIA=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_ETH_PHY=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_MTD=y -+# CONFIG_MMC is not set ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y ++CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y -+CONFIG_MTK_SNFI_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SNOR=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_HEXDUMP=y ++CONFIG_MTK_SNFI_SPI=y +CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_SPI_FLASH=y -+CONFIG_SPI_FLASH_BAR=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_UNLOCK_ALL=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7622_ubnt_unifi-6-lr-v3_defconfig -@@ -0,0 +1,146 @@ +@@ -0,0 +1,112 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7622=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" -+CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="nor0" -+CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0xc0000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_BOARD_LATE_INIT=y ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr-v3" +CONFIG_RESET_BUTTON_SETTLE_DELAY=400 -+CONFIG_BOOTP_SEND_HOSTNAME=y -+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env" ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=25000000 -+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr-v3" +CONFIG_DEBUG_UART=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y ++# CONFIG_LEGACY_IMAGE_FORMAT is not set +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr-v3" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr-v3" ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7622> " -+# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_EFI is not set -+# CONFIG_EFI_LOADER is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_BOOTEFI is not set -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CDP=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y +# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_GPIO=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPARTS=y -+# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y -+# CONFIG_CMD_UNLZ4 is not set -+CONFIG_CMD_ASKENV=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SOURCE=y +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_MDIO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_MMC is not set -+CONFIG_DM_SERIAL=y -+CONFIG_DM_SPI=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_HUSH_PARSER=y -+# CONFIG_PARTITION_UUIDS is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+# CONFIG_LED is not set -+# CONFIG_LZ4 is not set ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/ubnt_unifi-6-lr_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_PHY=y -+CONFIG_PHY_FIXED=y -+CONFIG_PHY_REALTEK=y ++CONFIG_GPIO_HOG=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADDR_ENABLE=y -+CONFIG_PHY_ADDR=0 ++CONFIG_PHY_REALTEK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_ETH_PHY=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_MTD=y -+# CONFIG_MMC is not set ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y ++CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y -+CONFIG_MTK_SNFI_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SNOR=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_HEXDUMP=y ++CONFIG_MTK_SNFI_SPI=y +CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_SPI_FLASH=y -+CONFIG_SPI_FLASH_BAR=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_UNLOCK_ALL=y -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_HEXDUMP=y --- /dev/null +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts @@ -0,0 +1,193 @@ @@ -841,7 +739,7 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1423,6 +1423,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1193,6 +1193,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ @@ -851,7 +749,7 @@ mt7629-rfb.dtb \ mt7981-rfb.dtb \ --- /dev/null -+++ b/ubnt_unifi-6-lr_env ++++ b/defenvs/ubnt_unifi-6-lr_env @@ -0,0 +1,50 @@ +ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -904,7 +802,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/ubnt_unifi-6-lr-v2_env ++++ b/defenvs/ubnt_unifi-6-lr-v2_env @@ -0,0 +1,50 @@ +ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -957,7 +855,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m"--- /dev/null --- /dev/null -+++ b/ubnt_unifi-6-lr-v3_env ++++ b/defenvs/ubnt_unifi-6-lr-v3_env @@ -0,0 +1,50 @@ +ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -1011,15 +909,15 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- a/common/board_r.c +++ b/common/board_r.c -@@ -66,6 +66,7 @@ +@@ -67,6 +67,7 @@ + #include <wdt.h> #include <asm-generic/gpio.h> - #include <efi_loader.h> #include <relocate.h> +#include <spi_flash.h> DECLARE_GLOBAL_DATA_PTR; -@@ -397,6 +398,20 @@ static int initr_onenand(void) +@@ -405,6 +406,20 @@ static int initr_onenand(void) } #endif @@ -1040,7 +938,7 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -692,6 +707,9 @@ static init_fnc_t init_sequence_r[] = { +@@ -711,6 +726,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_NMBM_MTD initr_nmbm, #endif diff --git a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch index 4ee87ce3d2..f117829316 100644 --- a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch +++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch @@ -125,31 +125,28 @@ Subject: [PATCH] add support for RAVPower RP-WD009 +} --- /dev/null +++ b/configs/ravpower-rp-wd009-ram_defconfig -@@ -0,0 +1,71 @@ +@@ -0,0 +1,61 @@ +CONFIG_MIPS=y -+CONFIG_SYS_LOAD_ADDR=0x80010000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_MEMTEST_START=0x80100000 -+CONFIG_SYS_MEMTEST_END=0x80400000 ++CONFIG_DEFAULT_DEVICE_TREE="ravpower-rp-wd009" ++CONFIG_SYS_LOAD_ADDR=0x80010000 +CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7628=y ++CONFIG_BOARD_RAVPOWER_RP_WD009=y ++CONFIG_SYS_MIPS_TIMER_FREQ=290000000 +CONFIG_MIPS_BOOT_FDT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_FIT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe && mtd read firmware 82000000 && bootm 82000000" +CONFIG_USE_PREBOOT=y ++CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_CONSOLE_INFO_QUIET=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_BOARD_RAVPOWER_RP_WD009=y -+CONFIG_SYS_MIPS_TIMER_FREQ=290000000 -+CONFIG_SYS_BOOTPARAMS_LEN=0x20000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMINFO=y -+# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y @@ -161,18 +158,18 @@ Subject: [PATCH] add support for RAVPower RP-WD009 +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_MTDPARTS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)" -+CONFIG_DEFAULT_DEVICE_TREE="ravpower-rp-wd009" ++CONFIG_VERSION_VARIABLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_DM_DEVICE_REMOVE is not set -+CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y -+CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y @@ -181,22 +178,15 @@ Subject: [PATCH] add support for RAVPower RP-WD009 +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_MTD=y -+CONFIG_MTD_UBI_BEB_LIMIT=22 +CONFIG_MT7628_ETH=y +CONFIG_PHY=y ++CONFIG_BAUDRATE=57600 +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_SYSRESET_SYSCON=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_LZMA=y -+CONFIG_BAUDRATE=57600 -+CONFIG_SYS_MAXARGS=64 -+CONFIG_SYS_CBSIZE=512 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/include/configs/ravpower-rp-wd009.h @@ -0,0 +1,17 @@ @@ -234,7 +224,7 @@ Subject: [PATCH] add support for RAVPower RP-WD009 config BOARD_VOCORE2 bool "VoCore2" select SPL_SERIAL -@@ -53,6 +61,7 @@ config SYS_CONFIG_NAME +@@ -52,6 +60,7 @@ config SYS_CONFIG_NAME default "mt7628" if BOARD_MT7628_RFB source "board/gardena/smart-gateway-mt7688/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch index b9b241a51d..b53c48337f 100644 --- a/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch +++ b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch @@ -1,126 +1,88 @@ --- /dev/null +++ b/configs/mt7621_zbtlink_zbt-wg3526-16m_defconfig -@@ -0,0 +1,138 @@ +@@ -0,0 +1,97 @@ +CONFIG_MIPS=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x1000 -+CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="nor0" -+CONFIG_ENV_SIZE_REDUND=0x10000 ++CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x30000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_RESET_BUTTON_SETTLE_DELAY=400 -+CONFIG_BOOTP_SEND_HOSTNAME=y -+# CONFIG_BOOTSTD is not set -+CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env" +CONFIG_DEFAULT_DEVICE_TREE="zbtlink,zbt-wg3526" -+CONFIG_SPL_BSS_MAX_SIZE=0x80000 -+CONFIG_SPL_BSS_START_ADDR=0x80140000 +CONFIG_SPL_SERIAL=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 ++CONFIG_SPL_BSS_START_ADDR=0x80140000 ++CONFIG_SPL_BSS_MAX_SIZE=0x80000 ++CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xbe000c00 +CONFIG_DEBUG_UART_CLOCK=50000000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_SYS_LOAD_ADDR=0x83000000 -+CONFIG_SYS_MIPS_TIMER_FREQ=440000000 +CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7621=y ++CONFIG_SYS_MIPS_TIMER_FREQ=440000000 +# CONFIG_MIPS_CACHE_SETUP is not set +# CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y ++# CONFIG_BOOTSTD is not set +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set -+CONFIG_HUSH_PARSER=y -+CONFIG_LOGLEVEL=6 -+# CONFIG_LOG is not set -+# CONFIG_SYS_LONGHELP is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_LOGLEVEL=6 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_TPL=y +# CONFIG_TPL_FRAMEWORK is not set -+CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_HUSH_PARSER=y ++# CONFIG_SYS_LONGHELP is not set ++# CONFIG_SYS_XTRACE is not set ++# CONFIG_CMD_BOOTD is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set -+# CONFIG_EFI is not set -+# CONFIG_EFI_LOADER is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_BOOTEFI is not set -+# CONFIG_CMD_BOOTD is not set -+# CONFIG_CMD_BOOTP is not set -+CONFIG_CMD_BOOTM=y -+# CONFIG_CMD_BOOTDEV is not set -+# CONFIG_CMD_BOOTFLOW is not set -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_ECHO=y +# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_GPIO=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPART=y -+# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y ++# CONFIG_CMD_BOOTP is not set +CONFIG_CMD_PING=y -+CONFIG_CMD_TFTPBOOT=y -+# CONFIG_CMD_UNLZ4 is not set -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SOURCE=y ++CONFIG_CMD_HASH=y +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x10000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+# CONFIG_NET_RANDOM_ETHADDR is not set ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/zbtlink_zbt-wg3526-16m_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +CONFIG_MMC=y +# CONFIG_MMC_QUIRKS is not set +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y -+CONFIG_MTD=y +CONFIG_DM_MTD=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+# CONFIG_SPI_FLASH_BAR is not set -+# CONFIG_SPI_FLASH_EON is not set -+# CONFIG_SPI_FLASH_GIGADEVICE is not set -+# CONFIG_SPI_FLASH_ISSI is not set -+# CONFIG_SPI_FLASH_MACRONIX is not set -+# CONFIG_SPI_FLASH_SPANSION is not set -+# CONFIG_SPI_FLASH_STMICRO is not set +CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_XMC is not set -+# CONFIG_SPI_FLASH_XTX is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PHY=y @@ -130,17 +92,14 @@ +CONFIG_MT7621_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_RESETCTL=y -+# CONFIG_SYS_XTRACE is not set -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_VERSION_VARIABLE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +# CONFIG_BINMAN_FDT is not set +CONFIG_LZMA=y -+CONFIG_SPL_LZMA=y +# CONFIG_GZIP is not set ++CONFIG_SPL_LZMA=y --- /dev/null -+++ b/zbtlink_zbt-wg3526-16m_env ++++ b/defenvs/zbtlink_zbt-wg3526-16m_env @@ -0,0 +1,36 @@ +ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -212,7 +171,7 @@ + + reset { + label = "reset"; -+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>; ++ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + @@ -221,7 +180,7 @@ + + led_status: status { + label = "green:status"; -+ gpios = <&gpio 24 GPIO_ACTIVE_LOW>; ++ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch b/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch index 2304fcd5ce..7526043760 100644 --- a/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch +++ b/package/boot/uboot-mediatek/patches/429-add-netcore-n60.patch @@ -1,188 +1,133 @@ --- /dev/null +++ b/configs/mt7986_netcore_n60_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,127 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-netcore-n60" -+CONFIG_DEFAULT_ENV_FILE="netcore_n60_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-netcore-n60.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-netcore-n60.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/netcore_n60_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7986a-netcore-n60.dts @@ -0,0 +1,185 @@ @@ -372,7 +317,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/netcore_n60_env ++++ b/defenvs/netcore_n60_env @@ -0,0 +1,57 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -418,14 +363,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +ethaddr_factory=mtd read factory 0x40080000 0x1fe000 0x1000 && env readmem -b ethaddr 0x40080f20 0x6 ; setenv ethaddr_factory +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch index cbcda89119..8a089f8e56 100644 --- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -1,802 +1,556 @@ --- /dev/null +++ b/configs/mt7986a_bpi-r3-emmc_defconfig -@@ -0,0 +1,197 @@ +@@ -0,0 +1,136 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_emmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7986a_bpi-r3-nor_defconfig -@@ -0,0 +1,193 @@ +@@ -0,0 +1,136 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_ENV_OFFSET=0x0 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_USB=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y -+CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7622=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MTD=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_MTD_NAME="u-boot-env" -+CONFIG_ENV_OFFSET=0x0 -+CONFIG_ENV_OFFSET_REDUND=0x20000 -+CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SIZE_REDUND=0x20000 ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_nor_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y +CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+#CONFIG_MTD_SPI_NAND=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7986a_bpi-r3-sd_defconfig -@@ -0,0 +1,197 @@ +@@ -0,0 +1,136 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_sdmmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7986a_bpi-r3-snand_defconfig -@@ -0,0 +1,198 @@ +@@ -0,0 +1,131 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y -+CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7622=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3_snand_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y +CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+#CONFIG_DM_SPI_FLASH=y -+#CONFIG_SPI_FLASH_MTD=y -+#CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+#CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r3_sdmmc_env ++++ b/defenvs/bananapi_bpi-r3_sdmmc_env @@ -0,0 +1,81 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -880,7 +634,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r3_nor_env ++++ b/defenvs/bananapi_bpi-r3_nor_env @@ -0,0 +1,60 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -943,7 +697,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r3_snand_env ++++ b/defenvs/bananapi_bpi-r3_snand_env @@ -0,0 +1,73 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -1019,7 +773,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r3_emmc_env ++++ b/defenvs/bananapi_bpi-r3_emmc_env @@ -0,0 +1,61 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch index 88b2c63632..81a1ac8f59 100644 --- a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch +++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch @@ -1,165 +1,92 @@ --- /dev/null +++ b/configs/mt7986_xiaomi_redmi-ax6000_defconfig -@@ -0,0 +1,179 @@ +@@ -0,0 +1,103 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-xiaomi_redmi-ax6000" -+CONFIG_DEFAULT_ENV_FILE="xiaomi_redmi-ax6000_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-xiaomi_redmi-ax6000.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+# CONFIG_LED is not set -+# CONFIG_LED_BLINK is not set -+# CONFIG_LED_GPIO is not set ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-xiaomi_redmi-ax6000.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+# CONFIG_CMD_EXT4 is not set -+# CONFIG_CMD_FAT is not set -+CONFIG_CMD_FDT=y -+# CONFIG_CMD_FS_GENERIC is not set -+# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y -+# CONFIG_CMD_GPT is not set -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+# CONFIG_CMD_LED is not set -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+# CONFIG_CMD_PCI is not set -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+# CONFIG_CMD_PWM is not set ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+# CONFIG_CMD_USB is not set -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_USB is not set -+# CONFIG_DM_PWM is not set -+# CONFIG_PWM_MTK is not set -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+# CONFIG_DM_SCSI is not set -+# CONFIG_AHCI is not set -+CONFIG_PHY=y -+# CONFIG_PHY_MTK_TPHY is not set -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+# CONFIG_PCI is not set -+# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_DM_PCI is not set -+# CONFIG_PCIE_MEDIATEK is not set -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+# CONFIG_PINCTRL_MT7622 is not set -+CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_SPI=y -+# CONFIG_I2C is not set -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+# CONFIG_USB is not set -+# CONFIG_USB_HOST is not set -+# CONFIG_USB_XHCI_HCD is not set -+# CONFIG_USB_XHCI_MTK is not set -+# CONFIG_USB_STORAGE is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/xiaomi_redmi-ax6000_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++# CONFIG_I2C is not set ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7986=y @@ -167,19 +94,16 @@ +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_RANDOM_UUID=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/arch/arm/dts/mt7986a-xiaomi_redmi-ax6000.dts @@ -0,0 +1,161 @@ @@ -345,7 +269,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/xiaomi_redmi-ax6000_env ++++ b/defenvs/xiaomi_redmi-ax6000_env @@ -0,0 +1,55 @@ +ethaddr_factory=mtd read factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40080004 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -390,7 +314,7 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs diff --git a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch index 365f280947..414334124a 100644 --- a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch +++ b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch @@ -1,558 +1,393 @@ --- /dev/null +++ b/configs/mt7986_tplink_tl-xdr4288_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,127 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" -+CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr4288_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/tplink_tl-xdr4288_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7986_tplink_tl-xdr6086_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,127 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" -+CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr6086_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/tplink_tl-xdr6086_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7986_tplink_tl-xdr6088_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,127 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" -+CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr6088_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/tplink_tl-xdr6088_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7986a-tplink-tl-xdr608x.dts @@ -0,0 +1,196 @@ @@ -753,7 +588,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/tplink_tl-xdr4288_env ++++ b/defenvs/tplink_tl-xdr4288_env @@ -0,0 +1,57 @@ +ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -800,20 +635,20 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/tplink_tl-xdr6086_env ++++ b/defenvs/tplink_tl-xdr6086_env @@ -0,0 +1,57 @@ +ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -860,20 +695,20 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/tplink_tl-xdr6088_env ++++ b/defenvs/tplink_tl-xdr6088_env @@ -0,0 +1,57 @@ +ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -920,14 +755,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch index 4f98c95893..4758ad13c0 100644 --- a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch +++ b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch @@ -1,181 +1,128 @@ --- /dev/null +++ b/configs/mt7981_qihoo-360t7_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981_qihoo-360t7" -+CONFIG_DEFAULT_ENV_FILE="qihoo-360t7_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_qihoo-360t7.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_qihoo-360t7.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/qihoo-360t7_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981_qihoo-360t7.dts @@ -0,0 +1,185 @@ @@ -365,7 +312,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/qihoo-360t7_env ++++ b/defenvs/qihoo-360t7_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -411,14 +358,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch index 2bd1afe7a8..5fb150dc2c 100644 --- a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch +++ b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch @@ -1,181 +1,128 @@ --- /dev/null +++ b/configs/mt7981_xiaomi_mi-router-wr30u_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-wr30u" -+CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-wr30u_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-wr30u.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-wr30u.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/xiaomi_mi-router-wr30u_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981_xiaomi_mi-router-wr30u.dts @@ -0,0 +1,221 @@ @@ -401,7 +348,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/xiaomi_mi-router-wr30u_env ++++ b/defenvs/xiaomi_mi-router-wr30u_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -447,14 +394,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch index d5a149b903..bbf100f8a7 100644 --- a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch +++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch @@ -1,181 +1,128 @@ --- /dev/null +++ b/configs/mt7981_h3c_magic-nx30-pro_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981_h3c_magic-nx30-pro" -+CONFIG_DEFAULT_ENV_FILE="h3c_magic-nx30-pro_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_h3c_magic-nx30-pro.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_h3c_magic-nx30-pro.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/h3c_magic-nx30-pro_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981_h3c_magic-nx30-pro.dts @@ -0,0 +1,205 @@ @@ -385,7 +332,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/h3c_magic-nx30-pro_env ++++ b/defenvs/h3c_magic-nx30-pro_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -431,14 +378,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch index e0a059eb7b..aedf9fe4ba 100644 --- a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch +++ b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch @@ -138,7 +138,7 @@ +}; --- /dev/null +++ b/configs/mt7986a_glinet_gl-mt6000_defconfig -@@ -0,0 +1,105 @@ +@@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -149,13 +149,12 @@ +CONFIG_ENV_SIZE=0x80000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000" -+CONFIG_SYS_PROMPT="MT7986> " +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y @@ -167,8 +166,10 @@ +CONFIG_LOG=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7986> " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y @@ -181,14 +182,14 @@ +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y -+CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 @@ -200,17 +201,15 @@ +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_DEFAULT_ENV_FILE="glinet_gl-mt6000_env" ++CONFIG_DEFAULT_ENV_FILE="defenvs/glinet_gl-mt6000_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y @@ -243,9 +242,8 @@ +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y +CONFIG_HEXDUMP=y -+CONFIG_LMB_MAX_REGIONS=64 --- /dev/null -+++ b/glinet_gl-mt6000_env ++++ b/defenvs/glinet_gl-mt6000_env @@ -0,0 +1,25 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch index 26e0e30a99..70abc45ff3 100644 --- a/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch +++ b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch @@ -1,359 +1,253 @@ --- /dev/null +++ b/configs/mt7981_cmcc_rax3000m-emmc_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-emmc" -+CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-emmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-emmc.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-emmc.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_USB=y +CONFIG_CMD_TFTPSRV=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y ++CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/cmcc_rax3000m-emmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_CMD_SF=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7981_cmcc_rax3000m-nand_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-nand" -+CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-nand_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-nand.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-nand.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/cmcc_rax3000m-nand_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981-cmcc-rax3000m.dtsi @@ -0,0 +1,85 @@ @@ -579,13 +473,13 @@ + }; +}; --- /dev/null -+++ b/cmcc_rax3000m-emmc_env ++++ b/defenvs/cmcc_rax3000m-emmc_env @@ -0,0 +1,55 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x46000000 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 -+bootargs=root=/dev/mmcblk0p65 ++bootargs=root=/dev/fit0 rootwait +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi +bootconf=config-1#mt7981b-cmcc-rax3000m-emmc +bootdelay=0 @@ -637,7 +531,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/cmcc_rax3000m-nand_env ++++ b/defenvs/cmcc_rax3000m-nand_env @@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -683,14 +577,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch index 639cae174e..3a23171dff 100644 --- a/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch +++ b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch @@ -1,181 +1,128 @@ --- /dev/null +++ b/configs/mt7981_jcg_q30-pro_defconfig -@@ -0,0 +1,175 @@ +@@ -0,0 +1,122 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981_jcg_q30-pro" -+CONFIG_DEFAULT_ENV_FILE="jcg_q30-pro_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_jcg_q30-pro.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_jcg_q30-pro.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/jcg_q30-pro_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7981=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981_jcg_q30-pro.dts @@ -0,0 +1,179 @@ @@ -359,7 +306,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/jcg_q30-pro_env ++++ b/defenvs/jcg_q30-pro_env @@ -0,0 +1,57 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -405,14 +352,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +ethaddr_factory=mtd read factory 0x40080000 0xa0000 0x800 && env readmem -b ethaddr 0x4008002a 0x6 ; setenv ethaddr_factory +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first diff --git a/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch index 7f0564fd49..c9094f377c 100644 --- a/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch +++ b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch @@ -1,192 +1,133 @@ --- /dev/null +++ b/configs/mt7986_zyxel_ex5601-t0_defconfig -@@ -0,0 +1,186 @@ +@@ -0,0 +1,127 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-zyxel_ex5601-t0" -+CONFIG_DEFAULT_ENV_FILE="zyxel_ex5601-t0_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-zyxel_ex5601-t0.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-zyxel_ex5601-t0.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="EX5601> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/zyxel_ex5601-t0_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++# CONFIG_I2C is not set ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_DM_PCI is not set -+# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y -+# CONFIG_I2C is not set +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7986a-zyxel_ex5601-t0.dts @@ -0,0 +1,181 @@ @@ -372,7 +313,7 @@ +}; + --- /dev/null -+++ b/zyxel_ex5601-t0_env ++++ b/defenvs/zyxel_ex5601-t0_env @@ -0,0 +1,55 @@ +ethaddr_factory=mtd read Factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008002A 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 @@ -417,7 +358,7 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs diff --git a/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch index 9b50166a94..c7bf7dd95c 100644 --- a/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch +++ b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch @@ -1,169 +1,112 @@ --- /dev/null +++ b/configs/mt7981_xiaomi_mi-router-ax3000t_defconfig -@@ -0,0 +1,163 @@ +@@ -0,0 +1,106 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-ax3000t" -+CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-ax3000t_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-ax3000t.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-ax3000t.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+# CONFIG_CMD_EXT4 is not set -+# CONFIG_CMD_FAT is not set -+CONFIG_CMD_FDT=y -+# CONFIG_CMD_FS_GENERIC is not set -+# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+# CONFIG_CMD_PCI is not set -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+# CONFIG_CMD_PWM is not set ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+# CONFIG_CMD_USB is not set -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_USB is not set -+# CONFIG_DM_PWM is not set -+# CONFIG_PWM_MTK is not set -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/xiaomi_mi-router-ax3000t_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+# CONFIG_DM_SCSI is not set -+# CONFIG_AHCI is not set -+CONFIG_PHY=y -+# CONFIG_PHY_MTK_TPHY is not set -+CONFIG_PHY_FIXED=y -+CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+# CONFIG_PCI is not set ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_DM_PCI is not set -+# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+# CONFIG_USB is not set -+# CONFIG_USB_HOST is not set -+# CONFIG_USB_XHCI_HCD is not set -+# CONFIG_USB_XHCI_MTK is not set -+# CONFIG_USB_STORAGE is not set -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981_xiaomi_mi-router-ax3000t.dts @@ -0,0 +1,187 @@ @@ -235,7 +178,7 @@ + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "2500base-x"; -+ mediatek,switch = "mt7531"; ++ mediatek,switch = "auto"; + reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + + fixed-link { @@ -355,7 +298,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/xiaomi_mi-router-ax3000t_env ++++ b/defenvs/xiaomi_mi-router-ax3000t_env @@ -0,0 +1,55 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -400,14 +343,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch index dc8dfe0140..651188c958 100644 --- a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch +++ b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7986a_jdcloud_re-cp-03_defconfig -@@ -0,0 +1,112 @@ +@@ -0,0 +1,109 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -11,14 +11,13 @@ +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-jdcloud_re-cp-03" -+CONFIG_SYS_PROMPT="MT7986> " +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=30 @@ -30,8 +29,10 @@ +CONFIG_LOG=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7986> " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y @@ -43,14 +44,14 @@ +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y -+CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y -+CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PSTORE=y @@ -68,17 +69,15 @@ +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_DEFAULT_ENV_FILE="jdcloud_re-cp-03_env" ++CONFIG_DEFAULT_ENV_FILE="defenvs/jdcloud_re-cp-03_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y @@ -107,12 +106,10 @@ +CONFIG_PWM_MTK=y +CONFIG_RAM=y +CONFIG_SCSI=y -+CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_LMB_MAX_REGIONS=64 --- /dev/null +++ b/arch/arm/dts/mt7986a-jdcloud_re-cp-03.dts @@ -0,0 +1,148 @@ @@ -265,7 +262,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/jdcloud_re-cp-03_env ++++ b/defenvs/jdcloud_re-cp-03_env @@ -0,0 +1,55 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch index 5409f7fa0d..e24b520c7b 100644 --- a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch +++ b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch @@ -1,417 +1,290 @@ --- /dev/null +++ b/configs/mt7986a_bpi-r3-mini-emmc_defconfig -@@ -0,0 +1,203 @@ +@@ -0,0 +1,143 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_emmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set -+CONFIG_CMD_MDIO=y -+CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MDIO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3-mini_emmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_PHY_ETHERNET_ID=y -+CONFIG_PHY_FIXED=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_MEDIATEK_ETH=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_AIROHA=y +CONFIG_PHY_AIROHA_EN8811H=y +CONFIG_PHY_AIROHA_FW_IN_MMC=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y ++CONFIG_PHY_ETHERNET_ID=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_MEDIATEK_ETH=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/configs/mt7986a_bpi-r3-mini-snand_defconfig -@@ -0,0 +1,203 @@ +@@ -0,0 +1,136 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7986=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_snand_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7986> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set -+CONFIG_CMD_MDIO=y -+CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r3-mini_snand_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_DM_MDIO=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_AIROHA=y ++CONFIG_PHY_AIROHA_EN8811H=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_PHY_FIXED=y -+CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_MEDIATEK_ETH=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y +CONFIG_RAM=y ++CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y ++CONFIG_MTK_SPIM=y +CONFIG_USB=y -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_MMC_MTK=y -+CONFIG_MEDIATEK_ETH=y -+CONFIG_PHY_AIROHA=y -+CONFIG_PHY_AIROHA_EN8811H=y -+CONFIG_PHY_AIROHA_FW_IN_UBI=y -+CONFIG_PINCTRL=y -+CONFIG_PINCONF=y -+CONFIG_PINCTRL_MT7986=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+#CONFIG_DM_SPI_FLASH=y -+#CONFIG_SPI_FLASH_MTD=y -+#CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+#CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y --- /dev/null -+++ b/bananapi_bpi-r3-mini_snand_env ++++ b/defenvs/bananapi_bpi-r3-mini_snand_env @@ -0,0 +1,61 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -475,7 +348,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r3-mini_emmc_env ++++ b/defenvs/bananapi_bpi-r3-mini_emmc_env @@ -0,0 +1,59 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 diff --git a/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch b/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch index 0b72e1ee98..086307cca6 100644 --- a/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch +++ b/package/boot/uboot-mediatek/patches/443-add-nokia_ea0326gmp.patch @@ -1,169 +1,112 @@ --- /dev/null +++ b/configs/mt7981_nokia_ea0326gmp_defconfig -@@ -0,0 +1,163 @@ +@@ -0,0 +1,106 @@ +CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_TARGET_MT7981=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-nokia-ea0326gmp" -+CONFIG_DEFAULT_ENV_FILE="nokia_ea0326gmp_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-nokia-ea0326gmp.dtb" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-nokia-ea0326gmp.dtb" +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="MT7981> " -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+# CONFIG_CMD_EXT4 is not set -+# CONFIG_CMD_FAT is not set -+CONFIG_CMD_FDT=y -+# CONFIG_CMD_FS_GENERIC is not set -+# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+# CONFIG_CMD_PCI is not set -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+# CONFIG_CMD_PWM is not set ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+# CONFIG_CMD_USB is not set -+# CONFIG_CMD_FLASH is not set -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+# CONFIG_DM_USB is not set -+# CONFIG_DM_PWM is not set -+# CONFIG_PWM_MTK is not set -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/nokia_ea0326gmp_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y -+CONFIG_DM_GPIO=y -+# CONFIG_DM_SCSI is not set -+# CONFIG_AHCI is not set -+CONFIG_PHY=y -+# CONFIG_PHY_MTK_TPHY is not set -+CONFIG_PHY_FIXED=y -+CONFIG_MTK_AHCI=y -+CONFIG_DM_ETH=y -+CONFIG_MEDIATEK_ETH=y -+# CONFIG_PCI is not set ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +# CONFIG_MMC is not set -+# CONFIG_DM_MMC is not set +CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_UBI_FASTMAP=y -+# CONFIG_DM_PCI is not set -+# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7981=y +CONFIG_POWER_DOMAIN=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y ++CONFIG_MTK_SPIM=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+# CONFIG_USB is not set -+# CONFIG_USB_HOST is not set -+# CONFIG_USB_XHCI_HCD is not set -+# CONFIG_USB_XHCI_MTK is not set -+# CONFIG_USB_STORAGE is not set -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_UBI=y -+CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 -+CONFIG_ENV_UBI_VOLUME="ubootenv" -+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_MTK_SPIM=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7981-nokia-ea0326gmp.dts @@ -0,0 +1,186 @@ @@ -354,7 +297,7 @@ + status = "disabled"; +}; --- /dev/null -+++ b/nokia_ea0326gmp_env ++++ b/defenvs/nokia_ea0326gmp_env @@ -0,0 +1,55 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -399,14 +342,14 @@ +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title diff --git a/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch b/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch new file mode 100644 index 0000000000..0d8601368f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/444-add-abt_asr3000.patch @@ -0,0 +1,346 @@ +--- /dev/null ++++ b/configs/mt7981_abt_asr3000_defconfig +@@ -0,0 +1,106 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-abt-asr3000" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-abt-asr3000.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/abt_asr3000_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/arch/arm/dts/mt7981-abt-asr3000.dts +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "ABT ASR3000"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ ++ button-reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button-wps { ++ label = "mesh"; ++ linux,code = <BTN_9>; ++ linux,input-type = <EV_SW>; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "red:wan"; ++ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led-1 { ++ label = "green:wan"; ++ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ mesh_led: led-2 { ++ label = "green:mesh"; ++ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ led-3 { ++ label = "green:wlan2g"; ++ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ ++ led-4 { ++ label = "green:wlan5g"; ++ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "art"; ++ reg = <0x180000 0x100000>; ++ }; ++ ++ partition@280000 { ++ label = "factory"; ++ reg = <0x280000 0x100000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ compatible = "linux,ubi"; ++ }; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/defenvs/abt_asr3000_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 rootwait ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-abt_asr3000-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-abt_asr3000-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-abt_asr3000-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-abt_asr3000-squashfs-sysupgrade.itb ++bootled_pwr=green:mesh ++bootled_rec=green:mesh ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch index 0a69e74e02..fe28a46c92 100644 --- a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch +++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig -@@ -0,0 +1,180 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -8,182 +8,139 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_emmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4_emmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig -@@ -0,0 +1,180 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -191,182 +148,139 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_sdmmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4_sdmmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-snand_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -374,183 +288,138 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_snand_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4_snand_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r4_sdmmc_env ++++ b/defenvs/bananapi_bpi-r4_sdmmc_env @@ -0,0 +1,66 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -602,7 +471,7 @@ +sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol +sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol +snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 -+ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2 ++ubi_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi +ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production @@ -619,7 +488,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r4_snand_env ++++ b/defenvs/bananapi_bpi-r4_snand_env @@ -0,0 +1,67 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -666,7 +535,7 @@ +part_recovery=recovery +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery @@ -689,7 +558,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r4_emmc_env ++++ b/defenvs/bananapi_bpi-r4_emmc_env @@ -0,0 +1,57 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -828,7 +697,7 @@ + status = "okay"; +}; + -+ð { ++ð0 { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; @@ -998,7 +867,7 @@ +}; --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-poe-emmc_defconfig -@@ -0,0 +1,180 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -1006,182 +875,139 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_emmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4-poe_emmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-poe-sdmmc_defconfig -@@ -0,0 +1,180 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -1189,182 +1015,139 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_sdmmc_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4-poe_sdmmc_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y +CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y ++CONFIG_AHCI_PCI=y +CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y -+CONFIG_OF_EMBED=y -+CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_ENV_OFFSET=0x400000 -+CONFIG_ENV_OFFSET_REDUND=0x440000 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_ENV_SIZE_REDUND=0x40000 -+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null +++ b/configs/mt7988a_bananapi_bpi-r4-poe-snand_defconfig -@@ -0,0 +1,182 @@ +@@ -0,0 +1,137 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -1372,183 +1155,138 @@ +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PCI=y +CONFIG_DEBUG_UART=y -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" -+CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_snand_env" -+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" -+CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_SMBIOS_PRODUCT_NAME="" -+CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AHCI=y ++CONFIG_FIT=y +CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y -+CONFIG_CFB_CONSOLE_ANSI=y -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_BUTTON=y -+CONFIG_BUTTON_GPIO=y -+CONFIG_GPIO_HOG=y -+CONFIG_CMD_ENV_FLAGS=y -+CONFIG_FIT=y -+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y -+CONFIG_LED=y -+CONFIG_LED_BLINK=y -+CONFIG_LED_GPIO=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y -+CONFIG_CMD_BOOTMENU=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_BUTTON=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_CDP=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " +CONFIG_CMD_CPU=y -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_DNS=y -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_EXT4=y -+CONFIG_CMD_FAT=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_FS_GENERIC=y -+CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_HASH=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_LED=y -+CONFIG_CMD_LICENSE=y -+CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_MBR is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y -+CONFIG_CMD_PSTORE=y -+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 +CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y -+CONFIG_CMD_TFTPBOOT=y -+CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_PART=y -+CONFIG_CMD_RARP=y -+CONFIG_CMD_SETEXPR=y -+CONFIG_CMD_SLEEP=y -+CONFIG_CMD_SNTP=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_STRINGS=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_UUID=y -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_USB=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_MTK=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_VERSION_VARIABLE=y -+CONFIG_PARTITION_UUIDS=y -+CONFIG_NETCONSOLE=y -+CONFIG_DM_GPIO=y -+CONFIG_DM_SCSI=y -+CONFIG_AHCI=y -+CONFIG_AHCI_PCI=y -+CONFIG_SCSI_AHCI=y -+CONFIG_SCSI=y -+CONFIG_CMD_SCSI=y -+CONFIG_PHY=y -+CONFIG_PHY_MTK_TPHY=y -+CONFIG_MTK_AHCI=y -+CONFIG_PCI=y -+CONFIG_MTD=y -+CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_DM_PCI=y -+CONFIG_PCIE_MEDIATEK=y -+CONFIG_PINCTRL_MT7988=y -+CONFIG_PRE_CONSOLE_BUFFER=y -+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 -+CONFIG_RAM=y -+CONFIG_DM_SERIAL=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MMC=y -+CONFIG_MMC_DEFAULT_DEV=1 -+CONFIG_MMC_SUPPORTS_TUNING=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_MTK_SPI_NAND=y -+CONFIG_MTK_SPI_NAND_MTD=y -+CONFIG_SYSRESET_WATCHDOG=y -+CONFIG_WDT_MTK=y -+CONFIG_LZO=y -+CONFIG_ZSTD=y -+CONFIG_HEXDUMP=y -+CONFIG_RANDOM_UUID=y -+CONFIG_REGEX=y -+CONFIG_USB=y -+CONFIG_USB_HOST=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_MTK=y -+CONFIG_USB_STORAGE=y +CONFIG_OF_EMBED=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_ENV_SIZE_REDUND=0x1f000 +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/bananapi_bpi-r4-poe_snand_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y +CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHY_FIXED=y -+CONFIG_DM_ETH=y +CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7988=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y -+#CONFIG_MTK_SNOR=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_SPI_FLASH_WINBOND=y -+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -+CONFIG_CMD_SF=y -+CONFIG_CMD_NAND=y -+CONFIG_CMD_NAND_TRIMFFS=y -+CONFIG_LMB_MAX_REGIONS=64 -+CONFIG_USE_IPADDR=y -+CONFIG_IPADDR="192.168.1.1" -+CONFIG_USE_SERVERIP=y -+CONFIG_SERVERIP="192.168.1.254" ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y --- /dev/null -+++ b/bananapi_bpi-r4-poe_emmc_env ++++ b/defenvs/bananapi_bpi-r4-poe_emmc_env @@ -0,0 +1,57 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -1608,7 +1346,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r4-poe_sdmmc_env ++++ b/defenvs/bananapi_bpi-r4-poe_sdmmc_env @@ -0,0 +1,66 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -1660,7 +1398,7 @@ +sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol +sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol +snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 -+ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2 ++ubi_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi +ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production @@ -1677,7 +1415,7 @@ +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/bananapi_bpi-r4-poe_snand_env ++++ b/defenvs/bananapi_bpi-r4-poe_snand_env @@ -0,0 +1,67 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -1724,7 +1462,7 @@ +part_recovery=recovery +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 +snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 -+ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery diff --git a/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch b/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch new file mode 100644 index 0000000000..da6e31b203 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/451-add-tplink-xtr8488.patch @@ -0,0 +1,389 @@ +--- /dev/null ++++ b/configs/mt7986_tplink_tl-xtr8488_defconfig +@@ -0,0 +1,127 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xtr8488" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xtr8488.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/tplink_tl-xtr8488_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_MTK_AHCI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/arch/arm/dts/mt7986a-tplink-tl-xtr8488.dts +@@ -0,0 +1,196 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "TP-Link TL-XTR8488"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 15 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&gpio 16 GPIO_ACTIVE_LOW>; ++ }; ++ ++ turbo { ++ label = "turbo"; ++ linux,code = <BTN_1>; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ status_green { ++ label = "green:status"; ++ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ turbo { ++ label = "green:turbo"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "config"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "factory"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7800000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/defenvs/tplink_tl-xtr8488_env +@@ -0,0 +1,57 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-tplink_tl-xtr8488-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-tplink_tl-xtr8488-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-tplink_tl-xtr8488-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-tplink_tl-xtr8488-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch b/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch index 28cc5d73d7..6fd39756d4 100644 --- a/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch +++ b/package/boot/uboot-mediatek/patches/452-add-xiaomi-redmi-ax6s.patch @@ -15,7 +15,7 @@ Subject: [PATCH] add xiaomi redmi ax6s --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1195,6 +1195,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-linksys-e8450-ubi.dtb \ mt7622-ubnt-unifi-6-lr.dtb \ mt7622-ubnt-unifi-6-lr-v3.dtb \ @@ -194,7 +194,7 @@ Subject: [PATCH] add xiaomi redmi ax6s +}; --- /dev/null +++ b/configs/mt7622_xiaomi_redmi-router-ax6s-ubi-loader_defconfig -@@ -0,0 +1,98 @@ +@@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y @@ -203,10 +203,10 @@ Subject: [PATCH] add xiaomi redmi ax6s +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-xiaomi-redmi-router-ax6s" ++CONFIG_SYS_LOAD_ADDR=0x40080000 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=25000000 -+CONFIG_SYS_LOAD_ADDR=0x40080000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y @@ -217,7 +217,6 @@ Subject: [PATCH] add xiaomi redmi ax6s +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_LOG=y +CONFIG_BOARD_LATE_INIT=y -+CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PROMPT="MT7622> " @@ -245,17 +244,17 @@ Subject: [PATCH] add xiaomi redmi ax6s +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_DEFAULT_ENV_FILE="xiaomi-redmi-router-ax6s-ubi-loader_env" ++CONFIG_DEFAULT_ENV_FILE="defenvs/xiaomi-redmi-router-ax6s-ubi-loader_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_PROT_UDP=y +CONFIG_BOOTP_SEND_HOSTNAME=y -+CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_BUTTON=y @@ -294,7 +293,7 @@ Subject: [PATCH] add xiaomi redmi ax6s +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y --- /dev/null -+++ b/xiaomi-redmi-router-ax6s-ubi-loader_env ++++ b/defenvs/xiaomi-redmi-router-ax6s-ubi-loader_env @@ -0,0 +1,22 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 @@ -315,6 +314,6 @@ Subject: [PATCH] add xiaomi redmi ax6s +ubi_init=ubi part ubi || run ubi_format +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize +ubi_read_production=run ubi_init && ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run ubi_write_production && reset diff --git a/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch b/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch index 25d2733d1c..d49b07f66e 100644 --- a/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch +++ b/package/boot/uboot-mediatek/patches/453-add-openwrt-one.patch @@ -149,7 +149,7 @@ + + partition@200000 { + label = "ubi"; -+ reg = <0x100000 0x7f00000>; ++ reg = <0x100000 0xff00000>; + }; + }; + }; @@ -206,3639 +206,263 @@ +}; --- /dev/null +++ b/configs/mt7981_openwrt-one-nor_defconfig -@@ -0,0 +1,1811 @@ -+# -+# Automatically generated file; DO NOT EDIT. -+# U-Boot 2024.01 Configuration -+# -+ -+# -+# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 13.2.0 r26144+12-219018185e) 13.2.0 -+# -+CONFIG_CREATE_ARCH_SYMLINK=y -+CONFIG_SYS_CACHE_SHIFT_6=y -+CONFIG_SYS_CACHELINE_SIZE=64 -+CONFIG_LINKER_LIST_ALIGN=8 -+# CONFIG_ARC is not set +@@ -0,0 +1,124 @@ +CONFIG_ARM=y -+# CONFIG_M68K is not set -+# CONFIG_MICROBLAZE is not set -+# CONFIG_MIPS is not set -+# CONFIG_NIOS2 is not set -+# CONFIG_PPC is not set -+# CONFIG_RISCV is not set -+# CONFIG_SANDBOX is not set -+# CONFIG_SH is not set -+# CONFIG_X86 is not set -+# CONFIG_XTENSA is not set -+CONFIG_SYS_ARCH="arm" -+CONFIG_SYS_CPU="armv8" -+CONFIG_SYS_SOC="mediatek" -+CONFIG_SYS_VENDOR="mediatek" -+CONFIG_SYS_BOARD="mt7981" -+CONFIG_SYS_CONFIG_NAME="mt7981" -+ -+# -+# Skipping low level initialization functions -+# -+# CONFIG_SKIP_LOWLEVEL_INIT is not set -+# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set +CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_SYS_NONCACHED_MEMORY=0x100000 -+# CONFIG_SYS_ICACHE_OFF is not set -+# CONFIG_SYS_DCACHE_OFF is not set -+ -+# -+# ARM architecture -+# -+CONFIG_ARM64=y -+CONFIG_ARM64_CRC32=y -+CONFIG_COUNTER_FREQUENCY=0 +CONFIG_POSITION_INDEPENDENT=y -+CONFIG_INIT_SP_RELATIVE=y -+CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 -+# CONFIG_GIC_V3_ITS is not set -+CONFIG_STATIC_RELA=y -+CONFIG_DMA_ADDR_T_64BIT=y -+CONFIG_GPIO_EXTRA_HEADER=y -+CONFIG_ARM_ASM_UNIFIED=y -+# CONFIG_SYS_ARM_CACHE_CP15 is not set -+# CONFIG_SYS_ARM_MMU is not set -+# CONFIG_SYS_ARM_MPU is not set -+CONFIG_SYS_ARM_ARCH=8 -+CONFIG_SYS_ARM_CACHE_WRITEBACK=y -+# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set -+# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set -+# CONFIG_ARCH_CPU_INIT is not set -+CONFIG_SYS_ARCH_TIMER=y -+CONFIG_ARM_SMCCC=y -+# CONFIG_SYS_L2_PL310 is not set -+# CONFIG_SPL_SYS_L2_PL310 is not set -+# CONFIG_SYS_L2CACHE_OFF is not set -+# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set -+# CONFIG_USE_ARCH_MEMCPY is not set -+# CONFIG_USE_ARCH_MEMSET is not set -+CONFIG_ARM64_SUPPORT_AARCH32=y -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_HISTB is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_MVEBU is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_TARGET_STV0991 is not set -+# CONFIG_ARCH_BCM283X is not set -+# CONFIG_ARCH_BCMSTB is not set -+# CONFIG_ARCH_BCMBCA is not set -+# CONFIG_TARGET_VEXPRESS_CA9X4 is not set -+# CONFIG_TARGET_BCMNS is not set -+# CONFIG_TARGET_BCMNS2 is not set -+# CONFIG_TARGET_BCMNS3 is not set -+# CONFIG_ARCH_EXYNOS is not set -+# CONFIG_ARCH_S5PC1XX is not set -+# CONFIG_ARCH_HIGHBANK is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_IPQ40XX is not set -+# CONFIG_ARCH_KEYSTONE is not set -+# CONFIG_ARCH_K3 is not set -+# CONFIG_ARCH_OMAP2PLUS is not set -+# CONFIG_ARCH_MESON is not set +CONFIG_ARCH_MEDIATEK=y -+# CONFIG_ARCH_LPC32XX is not set -+# CONFIG_ARCH_IMX8 is not set -+# CONFIG_ARCH_IMX8M is not set -+# CONFIG_ARCH_IMX8ULP is not set -+# CONFIG_ARCH_IMX9 is not set -+# CONFIG_ARCH_IMXRT is not set -+# CONFIG_ARCH_MX23 is not set -+# CONFIG_ARCH_MX28 is not set -+# CONFIG_ARCH_MX31 is not set -+# CONFIG_ARCH_MX7ULP is not set -+# CONFIG_ARCH_MX7 is not set -+# CONFIG_ARCH_MX6 is not set -+# CONFIG_ARCH_MX5 is not set -+# CONFIG_ARCH_NEXELL is not set -+# CONFIG_ARCH_NPCM is not set -+# CONFIG_ARCH_APPLE is not set -+# CONFIG_ARCH_OWL is not set -+# CONFIG_ARCH_QEMU is not set -+# CONFIG_ARCH_RMOBILE is not set -+# CONFIG_ARCH_SNAPDRAGON is not set -+# CONFIG_ARCH_SOCFPGA is not set -+# CONFIG_ARCH_SUNXI is not set -+# CONFIG_ARCH_U8500 is not set -+# CONFIG_ARCH_VERSAL is not set -+# CONFIG_ARCH_VERSAL_NET is not set -+# CONFIG_ARCH_VF610 is not set -+# CONFIG_ARCH_ZYNQ is not set -+# CONFIG_ARCH_ZYNQMP_R5 is not set -+# CONFIG_ARCH_ZYNQMP is not set -+# CONFIG_ARCH_TEGRA is not set -+# CONFIG_ARCH_VEXPRESS64 is not set -+# CONFIG_TARGET_CORSTONE1000 is not set -+# CONFIG_TARGET_TOTAL_COMPUTE is not set -+# CONFIG_TARGET_LS2080A_EMU is not set -+# CONFIG_TARGET_LS1088AQDS is not set -+# CONFIG_TARGET_LS2080AQDS is not set -+# CONFIG_TARGET_LS2080ARDB is not set -+# CONFIG_TARGET_LS2081ARDB is not set -+# CONFIG_TARGET_LX2160ARDB is not set -+# CONFIG_TARGET_LX2160AQDS is not set -+# CONFIG_TARGET_LX2162AQDS is not set -+# CONFIG_TARGET_HIKEY is not set -+# CONFIG_TARGET_HIKEY960 is not set -+# CONFIG_TARGET_POPLAR is not set -+# CONFIG_TARGET_LS1012AQDS is not set -+# CONFIG_TARGET_LS1012ARDB is not set -+# CONFIG_TARGET_LS1012A2G5RDB is not set -+# CONFIG_TARGET_LS1012AFRWY is not set -+# CONFIG_TARGET_LS1012AFRDM is not set -+# CONFIG_TARGET_LS1028AQDS is not set -+# CONFIG_TARGET_LS1028ARDB is not set -+# CONFIG_TARGET_LS1088ARDB is not set -+# CONFIG_TARGET_LS1021AQDS is not set -+# CONFIG_TARGET_LS1021ATWR is not set -+# CONFIG_TARGET_PG_WCOM_SELI8 is not set -+# CONFIG_TARGET_PG_WCOM_EXPU1 is not set -+# CONFIG_TARGET_LS1021ATSN is not set -+# CONFIG_TARGET_LS1021AIOT is not set -+# CONFIG_TARGET_LS1043AQDS is not set -+# CONFIG_TARGET_LS1043ARDB is not set -+# CONFIG_TARGET_LS1046AQDS is not set -+# CONFIG_TARGET_LS1046ARDB is not set -+# CONFIG_TARGET_LS1046AFRWY is not set -+# CONFIG_TARGET_SL28 is not set -+# CONFIG_TARGET_TEN64 is not set -+# CONFIG_ARCH_UNIPHIER is not set -+# CONFIG_ARCH_SYNQUACER is not set -+# CONFIG_ARCH_STM32 is not set -+# CONFIG_ARCH_STI is not set -+# CONFIG_ARCH_STM32MP is not set -+# CONFIG_ARCH_ROCKCHIP is not set -+# CONFIG_ARCH_OCTEONTX is not set -+# CONFIG_ARCH_OCTEONTX2 is not set -+# CONFIG_TARGET_THUNDERX_88XX is not set -+# CONFIG_ARCH_ASPEED is not set -+# CONFIG_TARGET_DURIAN is not set -+# CONFIG_TARGET_POMELO is not set -+# CONFIG_TARGET_PRESIDIO_ASIC is not set -+# CONFIG_TARGET_XENGUEST_ARM64 is not set -+# CONFIG_ARCH_GXP is not set -+# CONFIG_STATIC_MACH_TYPE is not set +CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_LEN=0x400000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SOURCE_FILE="" -+CONFIG_SF_DEFAULT_SPEED=1000000 -+CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_ENV_SIZE=0x8000 -+CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="openwrt-one" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000 -+CONFIG_DM_RESET=y -+CONFIG_SYS_MONITOR_LEN=0 -+# CONFIG_MT8512 is not set -+# CONFIG_TARGET_MT7622 is not set -+# CONFIG_TARGET_MT7623 is not set -+# CONFIG_TARGET_MT7629 is not set +CONFIG_TARGET_MT7981=y -+# CONFIG_TARGET_MT7986 is not set -+# CONFIG_TARGET_MT7988 is not set -+# CONFIG_TARGET_MT8183 is not set -+# CONFIG_TARGET_MT8512 is not set -+# CONFIG_TARGET_MT8516 is not set -+# CONFIG_TARGET_MT8518 is not set -+CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64" +CONFIG_RESET_BUTTON_LABEL="back" -+CONFIG_RESET_BUTTON_SETTLE_DELAY=0 -+CONFIG_ERR_PTR_OFFSET=0x0 -+# CONFIG_SPL is not set -+CONFIG_BOOTSTAGE_STASH_ADDR=0x0 ++CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+# CONFIG_DEBUG_UART_BOARD_INIT is not set -+CONFIG_IDENT_STRING="" -+CONFIG_SYS_CLK_FREQ=0 -+# CONFIG_CHIP_DIP_SCAN is not set -+# CONFIG_CMO_BY_VA_ONLY is not set -+# CONFIG_ARMV8_MULTIENTRY is not set -+# CONFIG_ARMV8_SET_SMPEN is not set -+# CONFIG_ARMV8_SWITCH_TO_EL1 is not set -+ -+# -+# ARMv8 secure monitor firmware -+# -+# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set -+CONFIG_PSCI_RESET=y -+# CONFIG_ARMV8_PSCI is not set -+# CONFIG_ARMV8_EA_EL3_FIRST is not set -+# CONFIG_ARMV8_CRYPTO is not set -+# CONFIG_CMD_DEKBLOB is not set -+# CONFIG_IMX_CAAM_DEK_ENCAP is not set -+# CONFIG_IMX_OPTEE_DEK_ENCAP is not set -+# CONFIG_IMX_SECO_DEK_ENCAP is not set -+# CONFIG_IMX_ELE_DEK_ENCAP is not set -+# CONFIG_CMD_HDMIDETECT is not set -+CONFIG_IMX_DCD_ADDR=0x00910000 -+CONFIG_SYS_MEM_TOP_HIDE=0x0 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+ -+# -+# ARM debug -+# -+CONFIG_BUILD_TARGET="" -+# CONFIG_PCI is not set -+CONFIG_FWU_NUM_BANKS=2 -+CONFIG_FWU_NUM_IMAGES_PER_BANK=2 +CONFIG_DEBUG_UART=y -+# CONFIG_AHCI is not set -+# CONFIG_OF_BOARD_FIXUP is not set -+ -+# -+# Functionality shared between NXP SoCs -+# -+# CONFIG_NXP_ESBC is not set -+ -+# -+# General setup -+# -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_CC_IS_GCC=y -+CONFIG_GCC_VERSION=130200 -+CONFIG_CLANG_VERSION=0 -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set -+# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set -+# CONFIG_OPTIMIZE_INLINING is not set -+CONFIG_ARCH_SUPPORTS_LTO=y -+# CONFIG_LTO is not set -+CONFIG_CC_HAS_ASM_INLINE=y -+# CONFIG_XEN is not set -+# CONFIG_ENV_VARS_UBOOT_CONFIG is not set -+# CONFIG_SYS_BOOT_GET_CMDLINE is not set -+# CONFIG_SYS_BOOT_GET_KBD is not set -+CONFIG_SYS_MALLOC_F=y -+# CONFIG_VALGRIND is not set -+CONFIG_EXPERT=y -+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y -+# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set -+# CONFIG_TOOLS_DEBUG is not set -+CONFIG_PHYS_64BIT=y -+CONFIG_FDT_64BIT=y -+# CONFIG_REMAKE_ELF is not set -+# CONFIG_HAS_BOARD_SIZE_LIMIT is not set -+# CONFIG_SYS_CUSTOM_LDSCRIPT is not set -+CONFIG_PLATFORM_ELFENTRY="_start" -+CONFIG_STACK_SIZE=0x1000000 -+CONFIG_SYS_SRAM_BASE=0x0 -+CONFIG_SYS_SRAM_SIZE=0x0 -+# CONFIG_MP is not set -+CONFIG_HAVE_TEXT_BASE=y -+# CONFIG_HAVE_SYS_UBOOT_START is not set -+CONFIG_SYS_UBOOT_START=0x41e00000 -+# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set -+# CONFIG_API is not set -+ -+# -+# Boot options -+# -+ -+# -+# Boot images -+# -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+# CONFIG_TIMESTAMP is not set +CONFIG_FIT=y -+CONFIG_FIT_EXTERNAL_OFFSET=0x0 -+CONFIG_FIT_FULL_CHECK=y -+# CONFIG_FIT_SIGNATURE is not set -+# CONFIG_FIT_CIPHER is not set -+# CONFIG_FIT_VERBOSE is not set -+# CONFIG_FIT_BEST_MATCH is not set -+CONFIG_FIT_PRINT=y -+# CONFIG_SPL_LOAD_FIT_FULL is not set -+CONFIG_PXE_UTILS=y -+CONFIG_BOOTSTD=y -+# CONFIG_BOOTSTD_FULL is not set -+# CONFIG_BOOTSTD_DEFAULTS is not set -+CONFIG_BOOTSTD_BOOTCOMMAND=y -+CONFIG_BOOTMETH_GLOBAL=y -+# CONFIG_BOOTMETH_CROS is not set -+CONFIG_BOOTMETH_EXTLINUX=y -+CONFIG_BOOTMETH_EXTLINUX_PXE=y -+CONFIG_BOOTMETH_EFILOADER=y -+CONFIG_BOOTMETH_VBE=y -+CONFIG_BOOTMETH_VBE_REQUEST=y -+CONFIG_BOOTMETH_VBE_SIMPLE=y -+CONFIG_BOOTMETH_VBE_SIMPLE_OS=y -+# CONFIG_BOOTMETH_SCRIPT is not set -+CONFIG_LEGACY_IMAGE_FORMAT=y -+# CONFIG_SUPPORT_RAW_INITRD is not set -+# CONFIG_CHROMEOS is not set -+# CONFIG_CHROMEOS_VBOOT is not set -+# CONFIG_RAMBOOT_PBL is not set -+CONFIG_SYS_BOOT_RAMDISK_HIGH=y -+# CONFIG_DISTRO_DEFAULTS is not set -+ -+# -+# Boot timing -+# -+# CONFIG_BOOTSTAGE is not set -+CONFIG_BOOTSTAGE_STASH_SIZE=0x1000 -+# CONFIG_SHOW_BOOT_PROGRESS is not set -+ -+# -+# Boot media -+# -+CONFIG_NAND_BOOT=y -+# CONFIG_ONENAND_BOOT is not set -+# CONFIG_QSPI_BOOT is not set -+# CONFIG_SATA_BOOT is not set -+# CONFIG_SD_BOOT is not set -+# CONFIG_SD_BOOT_QSPI is not set +CONFIG_SPI_BOOT=y -+ -+# -+# Autoboot options -+# -+CONFIG_AUTOBOOT=y -+CONFIG_BOOTDELAY=2 -+# CONFIG_AUTOBOOT_KEYED is not set -+# CONFIG_AUTOBOOT_USE_MENUKEY is not set +CONFIG_AUTOBOOT_MENU_SHOW=y -+# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set -+# CONFIG_BOOT_RETRY is not set -+ -+# -+# Image support -+# -+# CONFIG_IMAGE_PRE_LOAD is not set -+ -+# -+# Devicetree fixup -+# -+# CONFIG_OF_BOARD_SETUP is not set -+# CONFIG_OF_SYSTEM_SETUP is not set -+# CONFIG_OF_STDOUT_VIA_ALIAS is not set -+# CONFIG_FDT_FIXUP_PARTITIONS is not set -+# CONFIG_FDT_SIMPLEFB is not set -+CONFIG_ARCH_FIXUP_FDT_MEMORY=y -+# CONFIG_USE_BOOTARGS is not set -+# CONFIG_BOOTARGS_SUBST is not set -+# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="openwrt-one" -+# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set -+# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set -+ -+# -+# Configuration editor -+# -+# CONFIG_CEDIT is not set -+ -+# -+# Console -+# -+CONFIG_MENU=y -+# CONFIG_CONSOLE_RECORD is not set -+# CONFIG_DISABLE_CONSOLE is not set ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 -+# CONFIG_SILENT_CONSOLE is not set -+# CONFIG_SPL_SILENT_CONSOLE is not set -+# CONFIG_TPL_SILENT_CONSOLE is not set -+# CONFIG_PRE_CONSOLE_BUFFER is not set -+CONFIG_CONSOLE_FLUSH_SUPPORT=y -+# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set -+# CONFIG_CONSOLE_MUX is not set -+# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set -+# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set -+# CONFIG_SYS_CONSOLE_INFO_QUIET is not set -+# CONFIG_SYS_STDIO_DEREGISTER is not set -+# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+ -+# -+# Logging -+# +CONFIG_LOG=y -+CONFIG_LOG_MAX_LEVEL=6 -+CONFIG_LOG_DEFAULT_LEVEL=6 -+CONFIG_LOG_CONSOLE=y -+# CONFIG_LOGF_FILE is not set -+# CONFIG_LOGF_LINE is not set -+# CONFIG_LOGF_FUNC is not set -+CONFIG_LOGF_FUNC_PAD=20 -+# CONFIG_LOG_SYSLOG is not set -+# CONFIG_LOG_ERROR_RETURN is not set -+ -+# -+# Init options -+# -+# CONFIG_BOARD_TYPES is not set -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DISPLAY_BOARDINFO=y -+# CONFIG_DISPLAY_BOARDINFO_LATE is not set -+ -+# -+# Start-up hooks -+# -+# CONFIG_CYCLIC is not set -+CONFIG_EVENT=y -+CONFIG_EVENT_DYNAMIC=y -+# CONFIG_EVENT_DEBUG is not set -+# CONFIG_ARCH_MISC_INIT is not set -+# CONFIG_BOARD_EARLY_INIT_F is not set -+# CONFIG_BOARD_EARLY_INIT_R is not set -+# CONFIG_BOARD_POSTCLK_INIT is not set +CONFIG_BOARD_LATE_INIT=y -+# CONFIG_CLOCKS is not set -+# CONFIG_HWCONFIG is not set -+CONFIG_LAST_STAGE_INIT=y -+# CONFIG_MISC_INIT_R is not set -+# CONFIG_SYS_MALLOC_BOOTPARAMS is not set -+# CONFIG_ID_EEPROM is not set -+# CONFIG_RESET_PHY_R is not set -+ -+# -+# Security support -+# -+CONFIG_HASH=y -+# CONFIG_STACKPROTECTOR is not set -+# CONFIG_BOARD_RNG_SEED is not set -+ -+# -+# Update support -+# -+# CONFIG_UPDATE_TFTP is not set -+# CONFIG_ANDROID_AB is not set -+ -+# -+# Blob list -+# -+# CONFIG_BLOBLIST is not set -+CONFIG_SUPPORT_SPL=y -+# CONFIG_VPL is not set -+ -+# -+# Command line interface -+# -+CONFIG_CMDLINE=y +CONFIG_HUSH_PARSER=y -+CONFIG_CMDLINE_EDITING=y -+# CONFIG_CMDLINE_PS_SUPPORT is not set -+CONFIG_AUTO_COMPLETE=y -+CONFIG_SYS_LONGHELP=y +CONFIG_SYS_PROMPT="OpenWrt One> " -+CONFIG_SYS_PROMPT_HUSH_PS2="> " +CONFIG_SYS_MAXARGS=16 -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_SYS_XTRACE=y -+CONFIG_BUILD_BIN2C=y -+ -+# -+# Commands -+# -+ -+# -+# Info commands -+# -+CONFIG_CMD_BDI=y -+# CONFIG_CMD_BDINFO_EXTRA is not set -+# CONFIG_CMD_CONFIG is not set -+CONFIG_CMD_CONSOLE=y +CONFIG_CMD_CPU=y -+# CONFIG_CMD_HISTORY is not set +CONFIG_CMD_LICENSE=y -+# CONFIG_CMD_PMC is not set -+ -+# -+# Boot commands -+# -+CONFIG_CMD_BOOTD=y -+CONFIG_CMD_BOOTM=y -+# CONFIG_CMD_BOOTDEV is not set -+CONFIG_CMD_BOOTFLOW=y -+# CONFIG_CMD_BOOTMETH is not set -+CONFIG_BOOTM_EFI=y -+# CONFIG_CMD_BOOTZ is not set -+CONFIG_CMD_BOOTI=y -+CONFIG_BOOTM_LINUX=y +# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_OPENRTOS is not set -+# CONFIG_BOOTM_OSE is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set -+CONFIG_SYS_BOOTM_LEN=0x4000000 -+CONFIG_CMD_BOOTEFI=y -+CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y -+# CONFIG_CMD_BOOTEFI_HELLO is not set -+# CONFIG_CMD_BOOTEFI_SELFTEST is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_ADTIMG is not set -+CONFIG_CMD_ELF=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_GO=y -+CONFIG_CMD_RUN=y -+CONFIG_CMD_IMI=y -+# CONFIG_CMD_IMLS is not set -+CONFIG_CMD_XIMG=y -+# CONFIG_CMD_ZBOOT is not set -+ -+# -+# Environment commands -+# +CONFIG_CMD_ASKENV=y -+CONFIG_CMD_EXPORTENV=y -+CONFIG_CMD_IMPORTENV=y -+CONFIG_CMD_EDITENV=y -+# CONFIG_CMD_GREPENV is not set -+CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_ENV_EXISTS=y -+CONFIG_CMD_ENV_READMEM=y -+# CONFIG_CMD_ENV_CALLBACK is not set +CONFIG_CMD_ENV_FLAGS=y -+# CONFIG_CMD_NVEDIT_EFI is not set -+# CONFIG_CMD_NVEDIT_INDIRECT is not set -+# CONFIG_CMD_NVEDIT_INFO is not set -+# CONFIG_CMD_NVEDIT_LOAD is not set -+# CONFIG_CMD_NVEDIT_SELECT is not set -+ -+# -+# Memory commands -+# -+# CONFIG_CMD_BINOP is not set -+# CONFIG_CMD_BLOBLIST is not set -+CONFIG_CMD_CRC32=y -+# CONFIG_CRC32_VERIFY is not set -+# CONFIG_CMD_EEPROM is not set -+# CONFIG_LOOPW is not set -+# CONFIG_CMD_MD5SUM is not set -+# CONFIG_CMD_MEMINFO is not set -+CONFIG_CMD_MEMORY=y -+# CONFIG_CMD_MEM_SEARCH is not set -+# CONFIG_CMD_MX_CYCLIC is not set -+CONFIG_CMD_RANDOM=y -+# CONFIG_CMD_MEMTEST is not set -+# CONFIG_CMD_SHA1SUM is not set +CONFIG_CMD_STRINGS=y -+ -+# -+# Compression commands -+# -+CONFIG_CMD_LZMADEC=y +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_ZIP is not set -+ -+# -+# Device access commands -+# -+# CONFIG_CMD_ARMFLASH is not set -+# CONFIG_CMD_BIND is not set -+# CONFIG_CMD_CLK is not set -+# CONFIG_CMD_DEMO is not set -+# CONFIG_CMD_DFU is not set +CONFIG_CMD_DM=y -+CONFIG_CMD_FLASH=y -+# CONFIG_CMD_FPGAD is not set -+# CONFIG_CMD_FUSE is not set +CONFIG_CMD_GPIO=y -+# CONFIG_CMD_GPIO_READ is not set +CONFIG_CMD_PWM=y -+# CONFIG_CMD_GPT is not set -+# CONFIG_RANDOM_UUID is not set -+# CONFIG_CMD_IDE is not set -+# CONFIG_CMD_IO is not set -+# CONFIG_CMD_IOTRACE is not set -+# CONFIG_CMD_I2C is not set -+CONFIG_CMD_LOADB=y -+# CONFIG_CMD_LOADM is not set -+CONFIG_CMD_LOADS=y -+# CONFIG_LOADS_ECHO is not set -+# CONFIG_CMD_SAVES is not set -+# CONFIG_SYS_LOADS_BAUD_CHANGE is not set -+CONFIG_CMD_LOADXY_TIMEOUT=90 -+# CONFIG_CMD_LSBLK is not set -+# CONFIG_CMD_MBR is not set -+# CONFIG_CMD_CLONE is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND_EXT=y -+# CONFIG_CMD_ONENAND is not set -+# CONFIG_CMD_OSD is not set -+# CONFIG_CMD_PART is not set +CONFIG_CMD_PCI=y -+CONFIG_CMD_PINMUX=y -+# CONFIG_CMD_POWEROFF is not set -+# CONFIG_CMD_READ is not set -+# CONFIG_CMD_SATA is not set -+# CONFIG_CMD_SDRAM is not set -+CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y -+# CONFIG_CMD_SPI is not set -+# CONFIG_CMD_TSI148 is not set -+# CONFIG_CMD_UNIVERSE is not set +CONFIG_CMD_USB=y -+# CONFIG_CMD_USB_SDP is not set -+# CONFIG_CMD_RKMTD is not set -+# CONFIG_CMD_WRITE is not set -+ -+# -+# Shell scripting commands -+# -+# CONFIG_CMD_CAT is not set -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_SETEXPR=y -+# CONFIG_CMD_SETEXPR_FMT is not set -+# CONFIG_CMD_XXD is not set -+ -+# -+# Android support commands -+# -+CONFIG_CMD_NET=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_DHCP=y -+# CONFIG_BOOTP_MAY_FAIL is not set -+CONFIG_BOOTP_BOOTPATH=y -+# CONFIG_BOOTP_VENDOREX is not set -+# CONFIG_BOOTP_BOOTFILESIZE is not set -+CONFIG_BOOTP_DNS=y -+# CONFIG_BOOTP_DNS2 is not set -+CONFIG_BOOTP_GATEWAY=y -+CONFIG_BOOTP_HOSTNAME=y -+# CONFIG_BOOTP_PREFER_SERVERIP is not set -+CONFIG_BOOTP_SUBNETMASK=y -+# CONFIG_BOOTP_NISDOMAIN is not set -+# CONFIG_BOOTP_NTPSERVER is not set -+# CONFIG_BOOTP_TIMEOFFSET is not set -+# CONFIG_CMD_PCAP is not set -+CONFIG_BOOTP_PXE=y -+CONFIG_BOOTP_PXE_CLIENTARCH=0x16 -+# CONFIG_BOOTP_PXE_DHCP_OPTION is not set -+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8" -+CONFIG_CMD_TFTPBOOT=y -+# CONFIG_CMD_TFTPPUT is not set +CONFIG_CMD_TFTPSRV=y -+CONFIG_NET_TFTP_VARS=y +CONFIG_CMD_RARP=y -+# CONFIG_CMD_NFS is not set -+# CONFIG_SYS_DISABLE_AUTOLOAD is not set -+# CONFIG_CMD_WGET is not set -+# CONFIG_CMD_MII is not set -+# CONFIG_CMD_MDIO is not set -+CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_ETHSW is not set ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+# CONFIG_CMD_WOL is not set -+ -+# -+# Misc commands -+# -+# CONFIG_CMD_2048 is not set -+# CONFIG_CMD_BSP is not set -+CONFIG_CMD_BLOCK_CACHE=y -+CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y -+# CONFIG_CMD_CONITRACE is not set -+# CONFIG_CMD_CLS is not set -+# CONFIG_CMD_EFIDEBUG is not set -+CONFIG_CMD_EFICONFIG=y -+# CONFIG_CMD_EXCEPTION is not set -+CONFIG_CMD_LED=y -+# CONFIG_CMD_INI is not set -+# CONFIG_CMD_DATE is not set -+# CONFIG_CMD_TIME is not set -+# CONFIG_CMD_GETTIME is not set -+# CONFIG_CMD_PAUSE is not set -+CONFIG_CMD_SLEEP=y -+# CONFIG_CMD_TIMER is not set -+# CONFIG_CMD_SYSBOOT is not set -+# CONFIG_CMD_QFW is not set +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_PSTORE_MEM_SIZE=0x10000 -+CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000 -+CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000 -+CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000 -+CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000 -+CONFIG_CMD_PSTORE_ECC_SIZE=0 -+# CONFIG_CMD_TERMINAL is not set +CONFIG_CMD_UUID=y -+ -+# -+# TI specific command line interface -+# -+ -+# -+# Power commands -+# -+ -+# -+# Security commands -+# -+# CONFIG_CMD_AES is not set -+# CONFIG_CMD_BLOB is not set +CONFIG_CMD_HASH=y -+# CONFIG_CMD_HVC is not set +CONFIG_CMD_SMC=y -+# CONFIG_HASH_VERIFY is not set -+ -+# -+# Firmware commands -+# -+ -+# -+# Filesystem commands -+# -+# CONFIG_CMD_BTRFS is not set -+# CONFIG_CMD_EROFS is not set -+# CONFIG_CMD_EXT2 is not set -+# CONFIG_CMD_EXT4 is not set +CONFIG_CMD_FAT=y -+# CONFIG_CMD_SQUASHFS is not set +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y -+# CONFIG_CMD_JFFS2 is not set -+# CONFIG_CMD_MTDPARTS is not set -+CONFIG_MTDIDS_DEFAULT="" -+CONFIG_MTDPARTS_DEFAULT="" -+# CONFIG_CMD_REISER is not set -+# CONFIG_CMD_ZFS is not set -+ -+# -+# Debug commands -+# -+# CONFIG_CMD_DIAG is not set -+# CONFIG_CMD_EVENT is not set -+# CONFIG_CMD_LOG is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+ -+# -+# Partition Types -+# -+CONFIG_PARTITIONS=y -+# CONFIG_MAC_PARTITION is not set -+CONFIG_DOS_PARTITION=y -+# CONFIG_ISO_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+CONFIG_PARTITION_UUIDS=y -+CONFIG_SUPPORT_OF_CONTROL=y -+ -+# -+# Device Tree Control -+# -+CONFIG_OF_CONTROL=y -+CONFIG_OF_REAL=y -+# CONFIG_OF_LIVE is not set -+CONFIG_OF_SEPARATE=y -+# CONFIG_OF_EMBED is not set -+# CONFIG_OF_BOARD is not set -+# CONFIG_OF_OMIT_DTB is not set -+CONFIG_DEVICE_TREE_INCLUDES="" -+CONFIG_OF_LIST="openwrt-one" -+# CONFIG_MULTI_DTB_FIT is not set -+CONFIG_OF_TAG_MIGRATE=y -+# CONFIG_OF_DTB_PROPS_REMOVE is not set -+ -+# -+# Environment -+# -+CONFIG_ENV_SUPPORT=y -+CONFIG_SAVEENV=y +CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_MIN_ENTRIES=64 -+CONFIG_ENV_MAX_ENTRIES=512 -+CONFIG_ENV_IS_DEFAULT=y -+CONFIG_ENV_IS_NOWHERE=y -+# CONFIG_ENV_IS_IN_EEPROM is not set -+# CONFIG_ENV_IS_IN_FAT is not set -+# CONFIG_ENV_IS_IN_EXT4 is not set -+# CONFIG_ENV_IS_IN_FLASH is not set -+# CONFIG_ENV_IS_IN_MTD is not set -+# CONFIG_ENV_IS_IN_NAND is not set -+# CONFIG_ENV_IS_IN_NVRAM is not set -+# CONFIG_ENV_IS_IN_ONENAND is not set -+# CONFIG_ENV_IS_IN_REMOTE is not set -+# CONFIG_ENV_IS_IN_SPI_FLASH is not set -+# CONFIG_ENV_IS_IN_UBI is not set +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_DEFAULT_ENV_FILE="openwrt-one-nor_env" ++CONFIG_DEFAULT_ENV_FILE="defenvs/openwrt-one-nor_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+# CONFIG_ENV_IMPORT_FDT is not set -+# CONFIG_ENV_APPEND is not set -+# CONFIG_ENV_WRITEABLE_LIST is not set -+# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set -+# CONFIG_USE_BOOTFILE is not set -+# CONFIG_USE_ETHPRIME is not set -+# CONFIG_USE_HOSTNAME is not set -+# CONFIG_VERSION_VARIABLE is not set -+CONFIG_NET=y -+CONFIG_ARP_TIMEOUT=5000 -+CONFIG_NET_RETRY_COUNT=5 -+CONFIG_PROT_UDP=y -+CONFIG_BOOTDEV_ETH=y -+# CONFIG_BOOTP_SEND_HOSTNAME is not set ++CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y -+# CONFIG_NETCONSOLE is not set -+# CONFIG_IP_DEFRAG is not set -+# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set -+CONFIG_TFTP_BLOCKSIZE=1468 -+# CONFIG_TFTP_PORT is not set -+CONFIG_TFTP_WINDOWSIZE=1 -+# CONFIG_TFTP_TSIZE is not set -+# CONFIG_SERVERIP_FROM_PROXYDHCP is not set -+CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100 -+# CONFIG_KEEP_SERVERADDR is not set -+# CONFIG_UDP_CHECKSUM is not set -+# CONFIG_BOOTP_SERVERIP is not set -+CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64 -+# CONFIG_USE_GATEWAYIP is not set -+# CONFIG_USE_IPADDR is not set -+# CONFIG_USE_NETMASK is not set -+# CONFIG_USE_ROOTPATH is not set -+# CONFIG_USE_SERVERIP is not set -+# CONFIG_PROT_TCP is not set -+# CONFIG_IPV6 is not set -+CONFIG_SYS_RX_ETH_BUFFER=4 -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_DM=y -+# CONFIG_DM_WARN is not set -+# CONFIG_DM_DEBUG is not set -+# CONFIG_DM_STATS is not set -+CONFIG_DM_DEVICE_REMOVE=y -+CONFIG_DM_EVENT=y -+CONFIG_DM_STDIO=y -+CONFIG_DM_SEQ_ALIAS=y -+# CONFIG_DM_DMA is not set -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+# CONFIG_DEVRES is not set -+CONFIG_SIMPLE_BUS=y -+# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set -+# CONFIG_SIMPLE_PM_BUS is not set -+CONFIG_OF_TRANSLATE=y -+# CONFIG_TRANSLATION_OFFSET is not set -+CONFIG_DM_DEV_READ_INLINE=y -+# CONFIG_OFNODE_MULTI_TREE is not set -+# CONFIG_BOUNCE_BUFFER is not set -+# CONFIG_ADC is not set -+# CONFIG_ADC_EXYNOS is not set -+# CONFIG_ADC_SANDBOX is not set -+# CONFIG_SARADC_MESON is not set -+# CONFIG_SARADC_ROCKCHIP is not set -+# CONFIG_SATA is not set -+# CONFIG_SCSI_AHCI is not set -+ -+# -+# SATA/SCSI device support -+# -+# CONFIG_AXI is not set -+ -+# -+# Bus devices -+# -+CONFIG_BLK=y -+CONFIG_BLOCK_CACHE=y -+# CONFIG_BLKMAP is not set -+# CONFIG_EFI_MEDIA is not set -+# CONFIG_IDE is not set -+# CONFIG_LBA48 is not set -+# CONFIG_SYS_64BIT_LBA is not set -+# CONFIG_RKMTD is not set -+# CONFIG_BOOTCOUNT_LIMIT is not set -+ -+# -+# Button Support -+# +CONFIG_BUTTON=y -+# CONFIG_BUTTON_ADC is not set +CONFIG_BUTTON_GPIO=y -+ -+# -+# Cache Controller drivers -+# -+# CONFIG_CACHE is not set -+# CONFIG_L2X0_CACHE is not set -+# CONFIG_V5L2_CACHE is not set -+# CONFIG_NCORE_CACHE is not set -+# CONFIG_SIFIVE_CCACHE is not set -+ -+# -+# Clock -+# +CONFIG_CLK=y -+# CONFIG_CLK_CCF is not set -+# CONFIG_CLK_GPIO is not set -+# CONFIG_CLK_CDCE9XX is not set -+# CONFIG_CLK_ICS8N3QV01 is not set -+# CONFIG_CLK_K210 is not set -+# CONFIG_CLK_MPC83XX is not set -+# CONFIG_CLK_XLNX_CLKWZRD is not set -+# CONFIG_CLK_AT91 is not set -+# CONFIG_CLK_RCAR is not set -+# CONFIG_CLK_RCAR_CPG_LIB is not set -+# CONFIG_CLK_SIFIVE is not set -+# CONFIG_CLK_TI_AM3_DPLL is not set -+# CONFIG_CLK_TI_CTRL is not set -+# CONFIG_CLK_TI_GATE is not set -+# CONFIG_CLK_K3 is not set -+CONFIG_CPU=y -+# CONFIG_CPU_IMX is not set -+ -+# -+# Hardware crypto devices -+# -+# CONFIG_DM_HASH is not set -+# CONFIG_FSL_CAAM is not set -+CONFIG_CAAM_64BIT=y -+# CONFIG_SYS_FSL_SEC_BE is not set -+# CONFIG_SYS_FSL_SEC_LE is not set -+# CONFIG_NPCM_AES is not set -+# CONFIG_NPCM_SHA is not set -+# CONFIG_DDR_SPD is not set -+# CONFIG_IMX_SNPS_DDR_PHY is not set -+ -+# -+# Demo for driver model -+# -+# CONFIG_DM_DEMO is not set -+ -+# -+# DFU support -+# -+ -+# -+# DMA Support -+# -+# CONFIG_DMA is not set -+# CONFIG_DMA_LPC32XX is not set -+# CONFIG_TI_EDMA3 is not set -+# CONFIG_DMA_LEGACY is not set -+ -+# -+# Extcon Support -+# -+# CONFIG_EXTCON is not set -+ -+# -+# Fastboot support -+# -+# CONFIG_UDP_FUNCTION_FASTBOOT is not set -+# CONFIG_TCP_FUNCTION_FASTBOOT is not set -+CONFIG_FIRMWARE=y -+CONFIG_ARM_PSCI_FW=y -+# CONFIG_ZYNQMP_FIRMWARE is not set -+# CONFIG_ARM_SMCCC_FEATURES is not set -+# CONFIG_ARM_FFA_TRANSPORT is not set -+# CONFIG_SCMI_FIRMWARE is not set -+# CONFIG_DM_FUZZING_ENGINE is not set -+ -+# -+# FPGA support -+# -+# CONFIG_FPGA_ALTERA is not set -+# CONFIG_FPGA_SOCFPGA is not set -+# CONFIG_FPGA_LATTICE is not set -+# CONFIG_FPGA_XILINX is not set -+# CONFIG_DM_FPGA is not set -+# CONFIG_FWU_MDATA is not set -+CONFIG_GPIO=y +CONFIG_GPIO_HOG=y -+# CONFIG_DM_GPIO_LOOKUP_LABEL is not set -+# CONFIG_ALTERA_PIO is not set -+# CONFIG_BCM2835_GPIO is not set -+# CONFIG_DWAPB_GPIO is not set -+# CONFIG_AT91_GPIO is not set -+# CONFIG_ATMEL_PIO4 is not set -+# CONFIG_ASPEED_GPIO is not set -+# CONFIG_DA8XX_GPIO is not set -+# CONFIG_HIKEY_GPIO is not set -+# CONFIG_INTEL_BROADWELL_GPIO is not set -+# CONFIG_INTEL_GPIO is not set -+# CONFIG_INTEL_ICH6_GPIO is not set -+# CONFIG_IMX_RGPIO2P is not set -+# CONFIG_IPROC_GPIO is not set -+# CONFIG_HSDK_CREG_GPIO is not set -+# CONFIG_KIRKWOOD_GPIO is not set -+# CONFIG_LPC32XX_GPIO is not set -+# CONFIG_MCP230XX_GPIO is not set -+# CONFIG_MSM_GPIO is not set -+# CONFIG_MXC_GPIO is not set -+# CONFIG_MXS_GPIO is not set -+# CONFIG_NPCM_GPIO is not set -+# CONFIG_CMD_PCA953X is not set -+# CONFIG_ROCKCHIP_GPIO is not set -+# CONFIG_XILINX_GPIO is not set -+# CONFIG_TCA642X is not set -+# CONFIG_TEGRA_GPIO is not set -+# CONFIG_TEGRA186_GPIO is not set -+# CONFIG_VYBRID_GPIO is not set -+# CONFIG_SIFIVE_GPIO is not set -+# CONFIG_ZYNQ_GPIO is not set -+# CONFIG_DM_74X164 is not set -+# CONFIG_PCA953X is not set -+# CONFIG_MPC8XXX_GPIO is not set -+# CONFIG_MPC8XX_GPIO is not set -+# CONFIG_NX_GPIO is not set -+# CONFIG_NOMADIK_GPIO is not set -+# CONFIG_ZYNQMP_GPIO_MODEPIN is not set -+# CONFIG_SLG7XL45106_I2C_GPO is not set -+# CONFIG_TURRIS_OMNIA_MCU is not set -+# CONFIG_FTGPIO010 is not set -+ -+# -+# Hardware Spinlock Support -+# -+# CONFIG_DM_HWSPINLOCK is not set -+CONFIG_I2C=y -+# CONFIG_DM_I2C is not set -+# CONFIG_SYS_I2C_LEGACY is not set -+# CONFIG_SPL_SYS_I2C_LEGACY is not set -+# CONFIG_SYS_I2C_FSL is not set -+# CONFIG_SYS_I2C_DW is not set -+# CONFIG_SYS_I2C_IMX_LPI2C is not set -+# CONFIG_SYS_I2C_MTK is not set -+# CONFIG_SYS_I2C_MICROCHIP is not set -+# CONFIG_SYS_I2C_MXC is not set -+# CONFIG_SYS_I2C_NPCM is not set -+# CONFIG_SYS_I2C_SOFT is not set -+# CONFIG_SYS_I2C_MV is not set -+# CONFIG_SYS_I2C_MVTWSI is not set -+CONFIG_INPUT=y -+# CONFIG_DM_KEYBOARD is not set -+# CONFIG_CROS_EC_KEYB is not set -+# CONFIG_TEGRA_KEYBOARD is not set -+# CONFIG_TWL4030_INPUT is not set -+ -+# -+# IOMMU device drivers -+# -+# CONFIG_IOMMU is not set -+ -+# -+# LED Support -+# +CONFIG_LED=y -+# CONFIG_LED_PWM is not set +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y -+# CONFIG_LED_STATUS is not set -+ -+# -+# Mailbox Controller Support -+# -+# CONFIG_DM_MAILBOX is not set -+ -+# -+# Memory Controller drivers -+# -+# CONFIG_MEMORY is not set -+# CONFIG_ATMEL_EBI is not set -+# CONFIG_MFD_ATMEL_SMC is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MISC is not set -+# CONFIG_NVMEM is not set -+# CONFIG_SPL_NVMEM is not set -+# CONFIG_SMSC_LPC47M is not set -+# CONFIG_SMSC_SIO1007 is not set -+# CONFIG_CROS_EC is not set -+# CONFIG_DS4510 is not set -+# CONFIG_FSL_SEC_MON is not set -+# CONFIG_IRQ is not set -+# CONFIG_NPCM_HOST is not set -+# CONFIG_NUVOTON_NCT6102D is not set -+# CONFIG_PWRSEQ is not set -+# CONFIG_PCA9551_LED is not set -+# CONFIG_TEST_DRV is not set -+# CONFIG_USB_HUB_USB251XB is not set -+# CONFIG_TWL4030_LED is not set -+# CONFIG_WINBOND_W83627 is not set -+# CONFIG_FS_LOADER is not set -+ -+# -+# MMC Host controller Support -+# +# CONFIG_MMC is not set -+# CONFIG_MMC_BROKEN_CD is not set -+# CONFIG_DM_MMC is not set -+# CONFIG_FSL_ESDHC is not set -+# CONFIG_FSL_ESDHC_IMX is not set -+ -+# -+# MTD Support -+# -+CONFIG_MTD_PARTITIONS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y -+# CONFIG_MTD_NOR_FLASH is not set -+# CONFIG_MTD_CONCAT is not set -+# CONFIG_SYS_MTDPARTS_RUNTIME is not set -+# CONFIG_FLASH_CFI_DRIVER is not set -+# CONFIG_CFI_FLASH is not set -+# CONFIG_ALTERA_QSPI is not set -+# CONFIG_HBMC_AM654 is not set -+# CONFIG_SAMSUNG_ONENAND is not set -+# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set -+CONFIG_MTD_NAND_CORE=y -+# CONFIG_MTD_RAW_NAND is not set +CONFIG_MTD_SPI_NAND=y -+ -+# -+# SPI Flash Support -+# +CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_BUS=0 -+CONFIG_SF_DEFAULT_CS=0 -+# CONFIG_BOOTDEV_SPI_FLASH is not set +CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_SMART_HWCAPS=y -+# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set -+# CONFIG_SPI_FLASH_SOFT_RESET is not set -+# CONFIG_SPI_FLASH_BAR is not set -+CONFIG_SPI_FLASH_LOCK=y -+CONFIG_SPI_FLASH_UNLOCK_ALL=y -+# CONFIG_SPI_FLASH_ATMEL is not set +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y -+# CONFIG_SPI_FLASH_S28HX_T is not set +CONFIG_SPI_FLASH_STMICRO=y -+# CONFIG_SPI_FLASH_MT35XU is not set -+# CONFIG_SPI_FLASH_SST is not set +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y -+# CONFIG_SPI_FLASH_ZBIT is not set -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+# CONFIG_SPI_FLASH_DATAFLASH is not set +CONFIG_SPI_FLASH_MTD=y -+ -+# -+# UBI support -+# +CONFIG_UBI_SILENCE_MSG=y -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_MODULE=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_LIMIT=20 -+# CONFIG_MTD_UBI_FASTMAP is not set -+# CONFIG_NVMXIP is not set -+# CONFIG_NVMXIP_QSPI is not set -+# CONFIG_NMBM is not set -+ -+# -+# Multiplexer drivers -+# -+# CONFIG_MULTIPLEXER is not set -+# CONFIG_BITBANGMII is not set -+# CONFIG_MV88E6352_SWITCH is not set -+CONFIG_PHYLIB=y -+# CONFIG_PHY_ADDR_ENABLE is not set -+# CONFIG_B53_SWITCH is not set -+# CONFIG_MV88E61XX_SWITCH is not set -+# CONFIG_PHYLIB_10G is not set -+# CONFIG_PHY_ADIN is not set -+# CONFIG_PHY_AIROHA is not set -+# CONFIG_PHY_AQUANTIA is not set -+# CONFIG_PHY_ATHEROS is not set -+# CONFIG_SPL_PHY_ATHEROS is not set -+# CONFIG_PHY_BROADCOM is not set -+# CONFIG_PHY_CORTINA is not set -+# CONFIG_PHY_DAVICOM is not set -+# CONFIG_PHY_ET1011C is not set -+# CONFIG_PHY_LXT is not set -+# CONFIG_PHY_MARVELL is not set -+# CONFIG_PHY_MARVELL_10G is not set -+# CONFIG_PHY_MESON_GXL is not set -+# CONFIG_PHY_MICREL is not set -+# CONFIG_PHY_MOTORCOMM is not set -+# CONFIG_PHY_MSCC is not set -+# CONFIG_PHY_NATSEMI is not set -+# CONFIG_PHY_NXP_C45_TJA11XX is not set -+# CONFIG_PHY_NXP_TJA11XX is not set -+# CONFIG_PHY_REALTEK is not set -+# CONFIG_PHY_SMSC is not set -+# CONFIG_PHY_TERANETICS is not set -+# CONFIG_PHY_TI is not set -+# CONFIG_PHY_TI_DP83867 is not set -+# CONFIG_PHY_TI_DP83869 is not set -+# CONFIG_PHY_TI_GENERIC is not set -+# CONFIG_PHY_VITESSE is not set -+# CONFIG_PHY_XILINX is not set -+# CONFIG_PHY_XILINX_GMII2RGMII is not set -+# CONFIG_PHY_XWAY is not set -+# CONFIG_PHY_ETHERNET_ID is not set +CONFIG_PHY_FIXED=y -+# CONFIG_PHY_NCSI is not set -+# CONFIG_FSL_MEMAC is not set -+CONFIG_PHY_RESET_DELAY=0 -+# CONFIG_FSL_PFE is not set -+CONFIG_ETH=y -+CONFIG_DM_ETH=y -+# CONFIG_DM_MDIO is not set -+# CONFIG_DM_ETH_PHY is not set -+CONFIG_NETDEVICES=y -+# CONFIG_PHY_GIGE is not set -+# CONFIG_ALTERA_TSE is not set -+# CONFIG_BCM_SF2_ETH is not set -+# CONFIG_BCMGENET is not set -+# CONFIG_BNXT_ETH is not set -+# CONFIG_CALXEDA_XGMAC is not set -+# CONFIG_DRIVER_DM9000 is not set -+# CONFIG_DWC_ETH_QOS is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_ETH_DESIGNWARE is not set -+# CONFIG_ETH_DESIGNWARE_MESON8B is not set -+# CONFIG_ETHOC is not set -+# CONFIG_FMAN_ENET is not set -+# CONFIG_FTMAC100 is not set -+# CONFIG_FTGMAC100 is not set -+# CONFIG_MCFFEC is not set -+# CONFIG_FSLDMAFEC is not set -+# CONFIG_KS8851_MLL is not set -+# CONFIG_LITEETH is not set -+# CONFIG_MACB is not set -+# CONFIG_NET_NPCM750 is not set -+# CONFIG_PCH_GBE is not set -+# CONFIG_RGMII is not set -+# CONFIG_MII is not set -+# CONFIG_RMII is not set -+# CONFIG_PCNET is not set -+# CONFIG_QE_UEC is not set -+# CONFIG_RTL8139 is not set -+# CONFIG_SMC911X is not set -+# CONFIG_SUN7I_GMAC is not set -+# CONFIG_SUN4I_EMAC is not set -+# CONFIG_SUN8I_EMAC is not set -+# CONFIG_SH_ETHER is not set -+# CONFIG_DRIVER_TI_CPSW is not set -+# CONFIG_DRIVER_TI_EMAC is not set -+# CONFIG_DRIVER_TI_KEYSTONE_NET is not set -+# CONFIG_TULIP is not set -+# CONFIG_XILINX_AXIEMAC is not set -+# CONFIG_VSC7385_ENET is not set -+# CONFIG_XILINX_EMACLITE is not set -+# CONFIG_ZYNQ_GEM is not set -+# CONFIG_SYS_DPAA_QBMAN is not set -+# CONFIG_TSEC_ENET is not set +CONFIG_MEDIATEK_ETH=y -+# CONFIG_HIFEMAC_ETH is not set -+# CONFIG_HIGMACV300_ETH is not set -+# CONFIG_NVME is not set -+# CONFIG_NVME_APPLE is not set -+ -+# -+# PCI Endpoint -+# -+# CONFIG_PCI_ENDPOINT is not set -+# CONFIG_X86_PCH7 is not set -+# CONFIG_X86_PCH9 is not set -+ -+# -+# PHY Subsystem -+# +CONFIG_PHY=y -+# CONFIG_NOP_PHY is not set -+# CONFIG_MIPI_DPHY_HELPERS is not set -+# CONFIG_BCM_SR_PCIE_PHY is not set -+# CONFIG_OMAP_USB2_PHY is not set +CONFIG_PHY_MTK_TPHY=y -+ -+# -+# Rockchip PHY driver -+# -+# CONFIG_PHY_CADENCE_SIERRA is not set -+# CONFIG_PHY_CADENCE_TORRENT is not set -+# CONFIG_MSM8916_USB_PHY is not set -+# CONFIG_MVEBU_COMPHY_SUPPORT is not set -+ -+# -+# Pin controllers -+# +CONFIG_PINCTRL=y -+CONFIG_PINCTRL_FULL=y -+CONFIG_PINCTRL_GENERIC=y -+CONFIG_PINMUX=y +CONFIG_PINCONF=y -+CONFIG_PINCONF_RECURSIVE=y -+# CONFIG_PINCTRL_AT91 is not set -+# CONFIG_PINCTRL_AT91PIO4 is not set -+# CONFIG_PINCTRL_INTEL is not set -+# CONFIG_PINCTRL_QE is not set -+# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set -+# CONFIG_PINCTRL_SINGLE is not set -+# CONFIG_PINCTRL_STM32 is not set -+# CONFIG_PINCTRL_STMFX is not set -+# CONFIG_PINCTRL_K210 is not set -+CONFIG_PINCTRL_MTK=y -+# CONFIG_PINCTRL_MT7622 is not set -+# CONFIG_PINCTRL_MT7623 is not set -+# CONFIG_PINCTRL_MT7629 is not set +CONFIG_PINCTRL_MT7981=y -+# CONFIG_PINCTRL_MT7986 is not set -+# CONFIG_PINCTRL_MT7988 is not set -+# CONFIG_PINCTRL_MT8512 is not set -+# CONFIG_PINCTRL_MT8516 is not set -+# CONFIG_PINCTRL_MT8518 is not set -+CONFIG_POWER=y -+# CONFIG_POWER_LEGACY is not set -+# CONFIG_ACPI_PMC is not set -+ -+# -+# Power Domain Support -+# +CONFIG_POWER_DOMAIN=y -+# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set +CONFIG_MTK_POWER_DOMAIN=y -+# CONFIG_DM_PMIC is not set -+# CONFIG_PMIC_TPS65217 is not set -+# CONFIG_POWER_TPS65218 is not set -+# CONFIG_POWER_TPS62362 is not set -+# CONFIG_DM_REGULATOR is not set -+# CONFIG_TPS6586X_POWER is not set -+# CONFIG_POWER_MT6323 is not set +CONFIG_DM_PWM=y -+# CONFIG_PWM_ASPEED is not set -+# CONFIG_PWM_CADENCE_TTC is not set -+# CONFIG_PWM_CROS_EC is not set -+# CONFIG_PWM_EXYNOS is not set -+# CONFIG_PWM_IMX is not set -+# CONFIG_PWM_MESON is not set +CONFIG_PWM_MTK=y -+# CONFIG_PWM_ROCKCHIP is not set -+# CONFIG_PWM_SANDBOX is not set -+# CONFIG_PWM_SIFIVE is not set -+# CONFIG_PWM_TEGRA is not set -+# CONFIG_PWM_SUNXI is not set -+# CONFIG_U_QE is not set -+# CONFIG_RAM is not set -+ -+# -+# Reboot Mode Support -+# -+# CONFIG_DM_REBOOT_MODE is not set -+ -+# -+# Remote Processor drivers -+# -+ -+# -+# Reset Controller Support -+# -+# CONFIG_RESET_AST2500 is not set -+# CONFIG_RESET_AST2600 is not set -+CONFIG_RESET_MEDIATEK=y -+# CONFIG_RESET_HISILICON is not set -+# CONFIG_RESET_SYSCON is not set -+# CONFIG_RESET_SCMI is not set -+# CONFIG_RESET_DRA7 is not set -+# CONFIG_DM_RNG is not set -+ -+# -+# Real Time Clock -+# -+# CONFIG_DM_RTC is not set -+# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set -+# CONFIG_RTC_DS1337 is not set -+# CONFIG_RTC_DS1338 is not set -+# CONFIG_RTC_DS1374 is not set -+# CONFIG_RTC_DS3231 is not set -+# CONFIG_RTC_PCF8563 is not set -+# CONFIG_RTC_PT7C4338 is not set -+# CONFIG_RTC_PL031 is not set -+# CONFIG_RTC_S35392A is not set -+# CONFIG_RTC_MC13XXX is not set -+# CONFIG_RTC_MC146818 is not set -+# CONFIG_RTC_M41T62 is not set -+# CONFIG_SCSI is not set -+# CONFIG_DM_SCSI is not set -+CONFIG_SERIAL=y -+CONFIG_BAUDRATE=115200 -+# CONFIG_DEFAULT_ENV_IS_RW is not set -+CONFIG_REQUIRE_SERIAL_CONSOLE=y -+# CONFIG_SPECIFY_CONSOLE_INDEX is not set -+CONFIG_SERIAL_PRESENT=y +CONFIG_DM_SERIAL=y -+# CONFIG_SERIAL_RX_BUFFER is not set -+# CONFIG_SERIAL_PUTS is not set -+# CONFIG_SERIAL_SEARCH_ALL is not set -+# CONFIG_SERIAL_PROBE_ALL is not set -+# CONFIG_VPL_DM_SERIAL is not set -+CONFIG_DEBUG_UART_MTK=y -+CONFIG_DEBUG_UART_SHIFT=0 -+# CONFIG_DEBUG_UART_ANNOUNCE is not set -+# CONFIG_DEBUG_UART_SKIP_INIT is not set -+# CONFIG_ALTERA_JTAG_UART is not set -+# CONFIG_ALTERA_UART is not set -+# CONFIG_ARC_SERIAL is not set -+# CONFIG_ARM_DCC is not set -+# CONFIG_ATMEL_USART is not set -+# CONFIG_BCM6345_SERIAL is not set -+# CONFIG_COREBOOT_SERIAL is not set -+# CONFIG_CORTINA_UART is not set -+# CONFIG_FSL_LINFLEXUART is not set -+# CONFIG_FSL_LPUART is not set -+# CONFIG_MVEBU_A3700_UART is not set -+# CONFIG_MCFUART is not set -+# CONFIG_NULLDEV_SERIAL is not set -+# CONFIG_SYS_NS16550 is not set -+# CONFIG_PL01X_SERIAL is not set -+# CONFIG_ROCKCHIP_SERIAL is not set -+# CONFIG_XILINX_UARTLITE is not set -+# CONFIG_MSM_SERIAL is not set -+# CONFIG_MSM_GENI_SERIAL is not set -+# CONFIG_MXS_AUART_SERIAL is not set -+# CONFIG_OMAP_SERIAL is not set -+# CONFIG_SIFIVE_SERIAL is not set -+# CONFIG_ZYNQ_SERIAL is not set +CONFIG_MTK_SERIAL=y -+# CONFIG_MT7620_SERIAL is not set -+# CONFIG_NPCM_SERIAL is not set -+# CONFIG_SM is not set -+# CONFIG_MESON_SM is not set -+# CONFIG_SMEM is not set -+ -+# -+# Sound support -+# -+# CONFIG_SOUND is not set -+ -+# -+# SOC (System On Chip) specific Drivers -+# -+# CONFIG_SOC_DEVICE is not set -+# CONFIG_SOC_TI is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_SPI_MEM=y -+# CONFIG_SPI_DIRMAP is not set -+# CONFIG_ALTERA_SPI is not set -+# CONFIG_APPLE_SPI is not set -+# CONFIG_ATCSPI200_SPI is not set -+# CONFIG_ATMEL_SPI is not set -+# CONFIG_BCMSTB_SPI is not set -+# CONFIG_CORTINA_SFLASH is not set -+# CONFIG_CADENCE_QSPI is not set -+# CONFIG_CF_SPI is not set -+# CONFIG_DESIGNWARE_SPI is not set -+# CONFIG_EXYNOS_SPI is not set -+# CONFIG_FSL_DSPI is not set -+# CONFIG_FSL_QSPI is not set -+# CONFIG_GXP_SPI is not set -+# CONFIG_ICH_SPI is not set -+# CONFIG_IPROC_QSPI is not set -+# CONFIG_KIRKWOOD_SPI is not set -+# CONFIG_MICROCHIP_COREQSPI is not set -+# CONFIG_MPC8XXX_SPI is not set -+# CONFIG_MTK_SNOR is not set -+# CONFIG_MTK_SNFI_SPI is not set +CONFIG_MTK_SPIM=y -+# CONFIG_MVEBU_A3700_SPI is not set -+# CONFIG_MXS_SPI is not set -+# CONFIG_SPI_MXIC is not set -+# CONFIG_NPCM_FIU_SPI is not set -+# CONFIG_NPCM_PSPI is not set -+# CONFIG_NXP_FSPI is not set -+# CONFIG_OMAP3_SPI is not set -+# CONFIG_PL022_SPI is not set -+# CONFIG_ROCKCHIP_SFC is not set -+# CONFIG_ROCKCHIP_SPI is not set -+# CONFIG_SPI_ASPEED_SMC is not set -+# CONFIG_SPI_SIFIVE is not set -+# CONFIG_SOFT_SPI is not set -+# CONFIG_SPI_SN_F_OSPI is not set -+# CONFIG_SPI_SUNXI is not set -+# CONFIG_TEGRA114_SPI is not set -+# CONFIG_TEGRA20_SFLASH is not set -+# CONFIG_TEGRA20_SLINK is not set -+# CONFIG_TEGRA210_QSPI is not set -+# CONFIG_TI_QSPI is not set -+# CONFIG_XILINX_SPI is not set -+# CONFIG_ZYNQ_SPI is not set -+# CONFIG_ZYNQ_QSPI is not set -+# CONFIG_ZYNQMP_GQSPI is not set -+# CONFIG_SH_QSPI is not set -+# CONFIG_MXC_SPI is not set -+ -+# -+# SPMI support -+# -+# CONFIG_SPMI is not set -+# CONFIG_SYSINFO is not set -+ -+# -+# System reset device drivers -+# -+# CONFIG_SYSRESET is not set -+# CONFIG_TEE is not set -+# CONFIG_DM_THERMAL is not set -+ -+# -+# Timer Support -+# -+# CONFIG_TIMER is not set -+ -+# -+# TPM support -+# +CONFIG_USB=y -+CONFIG_DM_USB=y -+# CONFIG_DM_USB_GADGET is not set -+ -+# -+# USB Host Controller Drivers -+# -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y -+# CONFIG_USB_XHCI_DWC3 is not set -+# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set +CONFIG_USB_XHCI_MTK=y -+# CONFIG_USB_XHCI_FSL is not set -+# CONFIG_USB_XHCI_BRCM is not set -+# CONFIG_USB_EHCI_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_DWC2 is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_ISP1760 is not set -+# CONFIG_USB_CDNS3 is not set -+# CONFIG_USB_DWC3 is not set -+# CONFIG_USB_MTU3 is not set -+ -+# -+# Legacy MUSB Support -+# -+# CONFIG_USB_MUSB_HCD is not set -+# CONFIG_USB_MUSB_UDC is not set -+ -+# -+# MUSB Controller Driver -+# -+# CONFIG_USB_MUSB_HOST is not set -+# CONFIG_USB_MUSB_PIO_ONLY is not set -+ -+# -+# USB Phy -+# -+# CONFIG_TWL4030_USB is not set -+# CONFIG_ROCKCHIP_USB2_PHY is not set -+ -+# -+# ULPI drivers -+# -+ -+# -+# USB peripherals -+# +CONFIG_USB_STORAGE=y -+# CONFIG_USB_KEYBOARD is not set -+# CONFIG_USB_ONBOARD_HUB is not set -+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000 -+# CONFIG_USB_HOST_ETHER is not set -+# CONFIG_USB_GADGET is not set -+# CONFIG_SPL_USB_GADGET is not set -+ -+# -+# UFS Host Controller Support -+# -+# CONFIG_TI_J721E_UFS is not set -+ -+# -+# Graphics support -+# -+# CONFIG_VIDEO is not set -+ -+# -+# VirtIO Drivers -+# -+# CONFIG_VIRTIO_MMIO is not set -+ -+# -+# 1-Wire support -+# -+# CONFIG_W1 is not set -+ -+# -+# 1-wire EEPROM support -+# -+# CONFIG_W1_EEPROM is not set -+ -+# -+# Watchdog Timer Support -+# -+# CONFIG_WATCHDOG is not set -+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 -+# CONFIG_IMX_WATCHDOG is not set -+# CONFIG_ULP_WATCHDOG is not set -+# CONFIG_WDT is not set -+# CONFIG_PHYS_TO_BUS is not set -+ -+# -+# File systems -+# -+# CONFIG_FS_BTRFS is not set -+# CONFIG_FS_CBFS is not set -+# CONFIG_FS_EXT4 is not set -+CONFIG_FS_FAT=y -+CONFIG_FAT_WRITE=y -+CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 -+# CONFIG_FS_JFFS2 is not set +CONFIG_UBIFS_SILENCE_MSG=y -+CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y -+# CONFIG_FS_CRAMFS is not set -+# CONFIG_YAFFS2 is not set -+# CONFIG_FS_SQUASHFS is not set -+# CONFIG_FS_EROFS is not set -+ -+# -+# Library routines -+# -+# CONFIG_ADDR_MAP is not set -+# CONFIG_SYS_TIMER_COUNTS_DOWN is not set -+# CONFIG_PHYSMEM is not set -+# CONFIG_BCH is not set -+# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set -+CONFIG_CHARSET=y -+# CONFIG_DYNAMIC_CRC_TABLE is not set -+CONFIG_LIB_UUID=y -+# CONFIG_SEMIHOSTING is not set -+CONFIG_PRINTF=y -+CONFIG_SPRINTF=y -+CONFIG_STRTO=y -+CONFIG_SYS_HZ=1000 -+# CONFIG_PANIC_HANG is not set -+CONFIG_REGEX=y -+CONFIG_LIB_RAND=y -+# CONFIG_LIB_HW_RAND is not set -+CONFIG_SUPPORT_ACPI=y -+# CONFIG_ACPI is not set -+CONFIG_RBTREE=y -+# CONFIG_BITREVERSE is not set -+# CONFIG_TRACE is not set -+# CONFIG_CIRCBUF is not set -+# CONFIG_CMD_DHRYSTONE is not set -+ -+# -+# Security support -+# -+# CONFIG_AES is not set -+# CONFIG_ECDSA is not set -+# CONFIG_RSA is not set -+# CONFIG_TPM is not set -+ -+# -+# Android Verified Boot -+# -+ -+# -+# Hashing Support -+# -+# CONFIG_BLAKE2 is not set -+CONFIG_SHA1=y -+CONFIG_SHA256=y -+# CONFIG_SHA512 is not set -+# CONFIG_SHA384 is not set -+# CONFIG_SHA_HW_ACCEL is not set -+CONFIG_MD5=y -+CONFIG_CRC8=y -+CONFIG_CRC32=y -+ -+# -+# Compression Support -+# -+# CONFIG_LZ4 is not set -+CONFIG_LZMA=y -+CONFIG_LZO=y -+CONFIG_GZIP=y -+# CONFIG_ZLIB_UNCOMPRESS is not set -+# CONFIG_BZIP2 is not set -+CONFIG_ZLIB=y -+# CONFIG_ZSTD is not set -+CONFIG_VPL_LZMA=y -+# CONFIG_SPL_GZIP is not set -+# CONFIG_ERRNO_STR is not set +CONFIG_HEXDUMP=y -+# CONFIG_GETOPT is not set -+CONFIG_OF_LIBFDT=y -+CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 -+CONFIG_SYS_FDT_PAD=0x3000 -+ -+# -+# System tables -+# -+CONFIG_GENERATE_SMBIOS_TABLE=y -+# CONFIG_LIB_RATIONAL is not set -+CONFIG_SMBIOS=y -+# CONFIG_SMBIOS_PARSER is not set -+CONFIG_EFI_LOADER=y -+CONFIG_CMD_BOOTEFI_BOOTMGR=y -+CONFIG_EFI_VARIABLE_FILE_STORE=y -+# CONFIG_EFI_VARIABLE_NO_STORE is not set -+# CONFIG_EFI_VARIABLES_PRESEED is not set -+CONFIG_EFI_VAR_BUF_SIZE=131072 -+# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set -+# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set -+CONFIG_EFI_CAPSULE_MAX=15 -+CONFIG_EFI_DEVICE_PATH_TO_TEXT=y -+CONFIG_EFI_DEVICE_PATH_UTIL=y -+CONFIG_EFI_DT_FIXUP=y -+CONFIG_EFI_LOADER_HII=y -+CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y -+CONFIG_EFI_UNICODE_CAPITALIZATION=y -+# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set -+CONFIG_EFI_PLATFORM_LANG_CODES="en-US" -+CONFIG_EFI_HAVE_RUNTIME_RESET=y -+CONFIG_EFI_LOAD_FILE2_INITRD=y -+CONFIG_EFI_ECPT=y -+CONFIG_EFI_EBBR_2_1_CONFORMANCE=y -+# CONFIG_OPTEE_LIB is not set -+# CONFIG_OPTEE_IMAGE is not set -+# CONFIG_BOOTM_OPTEE is not set -+# CONFIG_TEST_FDTDEC is not set -+CONFIG_LIB_ELF=y -+CONFIG_LMB=y -+CONFIG_LMB_USE_MAX_REGIONS=y -+CONFIG_LMB_MAX_REGIONS=64 -+# CONFIG_PHANDLE_CHECK_SEQ is not set -+ -+# -+# Testing -+# -+# CONFIG_UNIT_TEST is not set -+# CONFIG_POST is not set -+ -+# -+# Tools options -+# -+CONFIG_MKIMAGE_DTC_PATH="dtc" -+CONFIG_TOOLS_CRC32=y -+# CONFIG_TOOLS_LIBCRYPTO is not set -+CONFIG_TOOLS_FIT=y -+CONFIG_TOOLS_FIT_FULL_CHECK=y -+CONFIG_TOOLS_FIT_PRINT=y -+CONFIG_TOOLS_FIT_RSASSA_PSS=y -+CONFIG_TOOLS_FIT_SIGNATURE=y -+CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000 -+CONFIG_TOOLS_FIT_VERBOSE=y -+CONFIG_TOOLS_MD5=y -+CONFIG_TOOLS_OF_LIBFDT=y -+CONFIG_TOOLS_SHA1=y -+CONFIG_TOOLS_SHA256=y -+CONFIG_TOOLS_SHA384=y -+CONFIG_TOOLS_SHA512=y -+# CONFIG_TOOLS_MKEFICAPSULE is not set -+# CONFIG_FSPI_CONF_HEADER is not set -+# CONFIG_TOOLS_MKFWUMDATA is not set --- /dev/null +++ b/configs/mt7981_openwrt-one-spi-nand_defconfig -@@ -0,0 +1,1815 @@ -+# -+# Automatically generated file; DO NOT EDIT. -+# U-Boot 2024.01 Configuration -+# -+ -+# -+# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r25206+8-d5e2177a6b) 12.3.0 -+# -+CONFIG_CREATE_ARCH_SYMLINK=y -+CONFIG_SYS_CACHE_SHIFT_6=y -+CONFIG_SYS_CACHELINE_SIZE=64 -+CONFIG_LINKER_LIST_ALIGN=8 -+# CONFIG_ARC is not set +@@ -0,0 +1,125 @@ +CONFIG_ARM=y -+# CONFIG_M68K is not set -+# CONFIG_MICROBLAZE is not set -+# CONFIG_MIPS is not set -+# CONFIG_NIOS2 is not set -+# CONFIG_PPC is not set -+# CONFIG_RISCV is not set -+# CONFIG_SANDBOX is not set -+# CONFIG_SH is not set -+# CONFIG_X86 is not set -+# CONFIG_XTENSA is not set -+CONFIG_SYS_ARCH="arm" -+CONFIG_SYS_CPU="armv8" -+CONFIG_SYS_SOC="mediatek" -+CONFIG_SYS_VENDOR="mediatek" -+CONFIG_SYS_BOARD="mt7981" -+CONFIG_SYS_CONFIG_NAME="mt7981" -+ -+# -+# Skipping low level initialization functions -+# -+# CONFIG_SKIP_LOWLEVEL_INIT is not set -+# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set +CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_SYS_NONCACHED_MEMORY=0x100000 -+# CONFIG_SYS_ICACHE_OFF is not set -+# CONFIG_SYS_DCACHE_OFF is not set -+ -+# -+# ARM architecture -+# -+CONFIG_ARM64=y -+CONFIG_ARM64_CRC32=y -+CONFIG_COUNTER_FREQUENCY=0 +CONFIG_POSITION_INDEPENDENT=y -+CONFIG_INIT_SP_RELATIVE=y -+CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 -+# CONFIG_GIC_V3_ITS is not set -+CONFIG_STATIC_RELA=y -+CONFIG_DMA_ADDR_T_64BIT=y -+CONFIG_GPIO_EXTRA_HEADER=y -+CONFIG_ARM_ASM_UNIFIED=y -+# CONFIG_SYS_ARM_CACHE_CP15 is not set -+# CONFIG_SYS_ARM_MMU is not set -+# CONFIG_SYS_ARM_MPU is not set -+CONFIG_SYS_ARM_ARCH=8 -+CONFIG_SYS_ARM_CACHE_WRITEBACK=y -+# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set -+# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set -+# CONFIG_ARCH_CPU_INIT is not set -+CONFIG_SYS_ARCH_TIMER=y -+CONFIG_ARM_SMCCC=y -+# CONFIG_SYS_L2_PL310 is not set -+# CONFIG_SPL_SYS_L2_PL310 is not set -+# CONFIG_SYS_L2CACHE_OFF is not set -+# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set -+# CONFIG_USE_ARCH_MEMCPY is not set -+# CONFIG_USE_ARCH_MEMSET is not set -+CONFIG_ARM64_SUPPORT_AARCH32=y -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_HISTB is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_MVEBU is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_TARGET_STV0991 is not set -+# CONFIG_ARCH_BCM283X is not set -+# CONFIG_ARCH_BCMSTB is not set -+# CONFIG_ARCH_BCMBCA is not set -+# CONFIG_TARGET_VEXPRESS_CA9X4 is not set -+# CONFIG_TARGET_BCMNS is not set -+# CONFIG_TARGET_BCMNS2 is not set -+# CONFIG_TARGET_BCMNS3 is not set -+# CONFIG_ARCH_EXYNOS is not set -+# CONFIG_ARCH_S5PC1XX is not set -+# CONFIG_ARCH_HIGHBANK is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_IPQ40XX is not set -+# CONFIG_ARCH_KEYSTONE is not set -+# CONFIG_ARCH_K3 is not set -+# CONFIG_ARCH_OMAP2PLUS is not set -+# CONFIG_ARCH_MESON is not set +CONFIG_ARCH_MEDIATEK=y -+# CONFIG_ARCH_LPC32XX is not set -+# CONFIG_ARCH_IMX8 is not set -+# CONFIG_ARCH_IMX8M is not set -+# CONFIG_ARCH_IMX8ULP is not set -+# CONFIG_ARCH_IMX9 is not set -+# CONFIG_ARCH_IMXRT is not set -+# CONFIG_ARCH_MX23 is not set -+# CONFIG_ARCH_MX28 is not set -+# CONFIG_ARCH_MX31 is not set -+# CONFIG_ARCH_MX7ULP is not set -+# CONFIG_ARCH_MX7 is not set -+# CONFIG_ARCH_MX6 is not set -+# CONFIG_ARCH_MX5 is not set -+# CONFIG_ARCH_NEXELL is not set -+# CONFIG_ARCH_NPCM is not set -+# CONFIG_ARCH_APPLE is not set -+# CONFIG_ARCH_OWL is not set -+# CONFIG_ARCH_QEMU is not set -+# CONFIG_ARCH_RMOBILE is not set -+# CONFIG_ARCH_SNAPDRAGON is not set -+# CONFIG_ARCH_SOCFPGA is not set -+# CONFIG_ARCH_SUNXI is not set -+# CONFIG_ARCH_U8500 is not set -+# CONFIG_ARCH_VERSAL is not set -+# CONFIG_ARCH_VERSAL_NET is not set -+# CONFIG_ARCH_VF610 is not set -+# CONFIG_ARCH_ZYNQ is not set -+# CONFIG_ARCH_ZYNQMP_R5 is not set -+# CONFIG_ARCH_ZYNQMP is not set -+# CONFIG_ARCH_TEGRA is not set -+# CONFIG_ARCH_VEXPRESS64 is not set -+# CONFIG_TARGET_CORSTONE1000 is not set -+# CONFIG_TARGET_TOTAL_COMPUTE is not set -+# CONFIG_TARGET_LS2080A_EMU is not set -+# CONFIG_TARGET_LS1088AQDS is not set -+# CONFIG_TARGET_LS2080AQDS is not set -+# CONFIG_TARGET_LS2080ARDB is not set -+# CONFIG_TARGET_LS2081ARDB is not set -+# CONFIG_TARGET_LX2160ARDB is not set -+# CONFIG_TARGET_LX2160AQDS is not set -+# CONFIG_TARGET_LX2162AQDS is not set -+# CONFIG_TARGET_HIKEY is not set -+# CONFIG_TARGET_HIKEY960 is not set -+# CONFIG_TARGET_POPLAR is not set -+# CONFIG_TARGET_LS1012AQDS is not set -+# CONFIG_TARGET_LS1012ARDB is not set -+# CONFIG_TARGET_LS1012A2G5RDB is not set -+# CONFIG_TARGET_LS1012AFRWY is not set -+# CONFIG_TARGET_LS1012AFRDM is not set -+# CONFIG_TARGET_LS1028AQDS is not set -+# CONFIG_TARGET_LS1028ARDB is not set -+# CONFIG_TARGET_LS1088ARDB is not set -+# CONFIG_TARGET_LS1021AQDS is not set -+# CONFIG_TARGET_LS1021ATWR is not set -+# CONFIG_TARGET_PG_WCOM_SELI8 is not set -+# CONFIG_TARGET_PG_WCOM_EXPU1 is not set -+# CONFIG_TARGET_LS1021ATSN is not set -+# CONFIG_TARGET_LS1021AIOT is not set -+# CONFIG_TARGET_LS1043AQDS is not set -+# CONFIG_TARGET_LS1043ARDB is not set -+# CONFIG_TARGET_LS1046AQDS is not set -+# CONFIG_TARGET_LS1046ARDB is not set -+# CONFIG_TARGET_LS1046AFRWY is not set -+# CONFIG_TARGET_SL28 is not set -+# CONFIG_TARGET_TEN64 is not set -+# CONFIG_ARCH_UNIPHIER is not set -+# CONFIG_ARCH_SYNQUACER is not set -+# CONFIG_ARCH_STM32 is not set -+# CONFIG_ARCH_STI is not set -+# CONFIG_ARCH_STM32MP is not set -+# CONFIG_ARCH_ROCKCHIP is not set -+# CONFIG_ARCH_OCTEONTX is not set -+# CONFIG_ARCH_OCTEONTX2 is not set -+# CONFIG_TARGET_THUNDERX_88XX is not set -+# CONFIG_ARCH_ASPEED is not set -+# CONFIG_TARGET_DURIAN is not set -+# CONFIG_TARGET_POMELO is not set -+# CONFIG_TARGET_PRESIDIO_ASIC is not set -+# CONFIG_TARGET_XENGUEST_ARM64 is not set -+# CONFIG_ARCH_GXP is not set -+# CONFIG_STATIC_MACH_TYPE is not set +CONFIG_TEXT_BASE=0x41e00000 -+CONFIG_SYS_MALLOC_LEN=0x400000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SOURCE_FILE="" -+CONFIG_SF_DEFAULT_SPEED=1000000 -+CONFIG_SF_DEFAULT_MODE=0x0 -+CONFIG_ENV_SIZE=0x1f000 -+CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="openwrt-one" +CONFIG_OF_LIBFDT_OVERLAY=y -+CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000 -+CONFIG_DM_RESET=y -+CONFIG_SYS_MONITOR_LEN=0 -+# CONFIG_MT8512 is not set -+# CONFIG_TARGET_MT7622 is not set -+# CONFIG_TARGET_MT7623 is not set -+# CONFIG_TARGET_MT7629 is not set +CONFIG_TARGET_MT7981=y -+# CONFIG_TARGET_MT7986 is not set -+# CONFIG_TARGET_MT7988 is not set -+# CONFIG_TARGET_MT8183 is not set -+# CONFIG_TARGET_MT8512 is not set -+# CONFIG_TARGET_MT8516 is not set -+# CONFIG_TARGET_MT8518 is not set -+CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64" +CONFIG_RESET_BUTTON_LABEL="back" -+CONFIG_RESET_BUTTON_SETTLE_DELAY=0 -+CONFIG_ERR_PTR_OFFSET=0x0 -+# CONFIG_SPL is not set -+CONFIG_BOOTSTAGE_STASH_ADDR=0x0 ++CONFIG_SYS_LOAD_ADDR=0x46000000 +CONFIG_DEBUG_UART_BASE=0x11002000 +CONFIG_DEBUG_UART_CLOCK=40000000 -+# CONFIG_DEBUG_UART_BOARD_INIT is not set -+CONFIG_IDENT_STRING="" -+CONFIG_SYS_CLK_FREQ=0 -+# CONFIG_CHIP_DIP_SCAN is not set -+# CONFIG_CMO_BY_VA_ONLY is not set -+# CONFIG_ARMV8_MULTIENTRY is not set -+# CONFIG_ARMV8_SET_SMPEN is not set -+# CONFIG_ARMV8_SWITCH_TO_EL1 is not set -+ -+# -+# ARMv8 secure monitor firmware -+# -+# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set -+CONFIG_PSCI_RESET=y -+# CONFIG_ARMV8_PSCI is not set -+# CONFIG_ARMV8_EA_EL3_FIRST is not set -+# CONFIG_ARMV8_CRYPTO is not set -+# CONFIG_CMD_DEKBLOB is not set -+# CONFIG_IMX_CAAM_DEK_ENCAP is not set -+# CONFIG_IMX_OPTEE_DEK_ENCAP is not set -+# CONFIG_IMX_SECO_DEK_ENCAP is not set -+# CONFIG_IMX_ELE_DEK_ENCAP is not set -+# CONFIG_CMD_HDMIDETECT is not set -+CONFIG_IMX_DCD_ADDR=0x00910000 -+CONFIG_SYS_MEM_TOP_HIDE=0x0 -+CONFIG_SYS_LOAD_ADDR=0x46000000 -+ -+# -+# ARM debug -+# -+CONFIG_BUILD_TARGET="" -+# CONFIG_PCI is not set -+CONFIG_FWU_NUM_BANKS=2 -+CONFIG_FWU_NUM_IMAGES_PER_BANK=2 +CONFIG_DEBUG_UART=y -+# CONFIG_AHCI is not set -+# CONFIG_OF_BOARD_FIXUP is not set -+ -+# -+# Functionality shared between NXP SoCs -+# -+# CONFIG_NXP_ESBC is not set -+ -+# -+# General setup -+# -+CONFIG_LOCALVERSION="" -+CONFIG_LOCALVERSION_AUTO=y -+CONFIG_CC_IS_GCC=y -+CONFIG_GCC_VERSION=120300 -+CONFIG_CLANG_VERSION=0 -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set -+# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set -+# CONFIG_OPTIMIZE_INLINING is not set -+CONFIG_ARCH_SUPPORTS_LTO=y -+# CONFIG_LTO is not set -+CONFIG_CC_HAS_ASM_INLINE=y -+# CONFIG_XEN is not set -+# CONFIG_ENV_VARS_UBOOT_CONFIG is not set -+# CONFIG_SYS_BOOT_GET_CMDLINE is not set -+# CONFIG_SYS_BOOT_GET_KBD is not set -+CONFIG_SYS_MALLOC_F=y -+# CONFIG_VALGRIND is not set -+CONFIG_EXPERT=y -+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y -+# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set -+# CONFIG_TOOLS_DEBUG is not set -+CONFIG_PHYS_64BIT=y -+CONFIG_FDT_64BIT=y -+# CONFIG_REMAKE_ELF is not set -+# CONFIG_HAS_BOARD_SIZE_LIMIT is not set -+# CONFIG_SYS_CUSTOM_LDSCRIPT is not set -+CONFIG_PLATFORM_ELFENTRY="_start" -+CONFIG_STACK_SIZE=0x1000000 -+CONFIG_SYS_SRAM_BASE=0x0 -+CONFIG_SYS_SRAM_SIZE=0x0 -+# CONFIG_MP is not set -+CONFIG_HAVE_TEXT_BASE=y -+# CONFIG_HAVE_SYS_UBOOT_START is not set -+CONFIG_SYS_UBOOT_START=0x41e00000 -+# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set -+# CONFIG_API is not set -+ -+# -+# Boot options -+# -+ -+# -+# Boot images -+# -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+# CONFIG_TIMESTAMP is not set +CONFIG_FIT=y -+CONFIG_FIT_EXTERNAL_OFFSET=0x0 -+CONFIG_FIT_FULL_CHECK=y -+# CONFIG_FIT_SIGNATURE is not set -+# CONFIG_FIT_CIPHER is not set -+# CONFIG_FIT_VERBOSE is not set -+# CONFIG_FIT_BEST_MATCH is not set -+CONFIG_FIT_PRINT=y -+# CONFIG_SPL_LOAD_FIT_FULL is not set -+CONFIG_PXE_UTILS=y -+CONFIG_BOOTSTD=y -+# CONFIG_BOOTSTD_FULL is not set -+# CONFIG_BOOTSTD_DEFAULTS is not set -+CONFIG_BOOTSTD_BOOTCOMMAND=y -+CONFIG_BOOTMETH_GLOBAL=y -+# CONFIG_BOOTMETH_CROS is not set -+CONFIG_BOOTMETH_EXTLINUX=y -+CONFIG_BOOTMETH_EXTLINUX_PXE=y -+CONFIG_BOOTMETH_EFILOADER=y -+CONFIG_BOOTMETH_VBE=y -+CONFIG_BOOTMETH_VBE_REQUEST=y -+CONFIG_BOOTMETH_VBE_SIMPLE=y -+CONFIG_BOOTMETH_VBE_SIMPLE_OS=y -+# CONFIG_BOOTMETH_SCRIPT is not set -+CONFIG_LEGACY_IMAGE_FORMAT=y -+# CONFIG_SUPPORT_RAW_INITRD is not set -+# CONFIG_CHROMEOS is not set -+# CONFIG_CHROMEOS_VBOOT is not set -+# CONFIG_RAMBOOT_PBL is not set -+CONFIG_SYS_BOOT_RAMDISK_HIGH=y -+# CONFIG_DISTRO_DEFAULTS is not set -+ -+# -+# Boot timing -+# -+# CONFIG_BOOTSTAGE is not set -+CONFIG_BOOTSTAGE_STASH_SIZE=0x1000 -+# CONFIG_SHOW_BOOT_PROGRESS is not set -+ -+# -+# Boot media -+# -+CONFIG_NAND_BOOT=y -+# CONFIG_ONENAND_BOOT is not set -+# CONFIG_QSPI_BOOT is not set -+# CONFIG_SATA_BOOT is not set -+# CONFIG_SD_BOOT is not set -+# CONFIG_SD_BOOT_QSPI is not set +CONFIG_SPI_BOOT=y -+ -+# -+# Autoboot options -+# -+CONFIG_AUTOBOOT=y -+CONFIG_BOOTDELAY=2 -+# CONFIG_AUTOBOOT_KEYED is not set -+# CONFIG_AUTOBOOT_USE_MENUKEY is not set +CONFIG_AUTOBOOT_MENU_SHOW=y -+# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set -+# CONFIG_BOOT_RETRY is not set -+ -+# -+# Image support -+# -+# CONFIG_IMAGE_PRE_LOAD is not set -+ -+# -+# Devicetree fixup -+# -+# CONFIG_OF_BOARD_SETUP is not set -+# CONFIG_OF_SYSTEM_SETUP is not set -+# CONFIG_OF_STDOUT_VIA_ALIAS is not set -+# CONFIG_FDT_FIXUP_PARTITIONS is not set -+# CONFIG_FDT_SIMPLEFB is not set -+CONFIG_ARCH_FIXUP_FDT_MEMORY=y -+# CONFIG_USE_BOOTARGS is not set -+# CONFIG_BOOTARGS_SUBST is not set -+# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="openwrt-one" -+# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set -+# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set -+ -+# -+# Configuration editor -+# -+# CONFIG_CEDIT is not set -+ -+# -+# Console -+# -+CONFIG_MENU=y -+# CONFIG_CONSOLE_RECORD is not set -+# CONFIG_DISABLE_CONSOLE is not set ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 -+# CONFIG_SILENT_CONSOLE is not set -+# CONFIG_SPL_SILENT_CONSOLE is not set -+# CONFIG_TPL_SILENT_CONSOLE is not set -+# CONFIG_PRE_CONSOLE_BUFFER is not set -+CONFIG_CONSOLE_FLUSH_SUPPORT=y -+# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set -+# CONFIG_CONSOLE_MUX is not set -+# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set -+# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set -+# CONFIG_SYS_CONSOLE_INFO_QUIET is not set -+# CONFIG_SYS_STDIO_DEREGISTER is not set -+# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+ -+# -+# Logging -+# +CONFIG_LOG=y -+CONFIG_LOG_MAX_LEVEL=6 -+CONFIG_LOG_DEFAULT_LEVEL=6 -+CONFIG_LOG_CONSOLE=y -+# CONFIG_LOGF_FILE is not set -+# CONFIG_LOGF_LINE is not set -+# CONFIG_LOGF_FUNC is not set -+CONFIG_LOGF_FUNC_PAD=20 -+# CONFIG_LOG_SYSLOG is not set -+# CONFIG_LOG_ERROR_RETURN is not set -+ -+# -+# Init options -+# -+# CONFIG_BOARD_TYPES is not set -+CONFIG_DISPLAY_CPUINFO=y -+CONFIG_DISPLAY_BOARDINFO=y -+# CONFIG_DISPLAY_BOARDINFO_LATE is not set -+ -+# -+# Start-up hooks -+# -+# CONFIG_CYCLIC is not set -+CONFIG_EVENT=y -+CONFIG_EVENT_DYNAMIC=y -+# CONFIG_EVENT_DEBUG is not set -+# CONFIG_ARCH_MISC_INIT is not set -+# CONFIG_BOARD_EARLY_INIT_F is not set -+# CONFIG_BOARD_EARLY_INIT_R is not set -+# CONFIG_BOARD_POSTCLK_INIT is not set +CONFIG_BOARD_LATE_INIT=y -+# CONFIG_CLOCKS is not set -+# CONFIG_HWCONFIG is not set -+CONFIG_LAST_STAGE_INIT=y -+# CONFIG_MISC_INIT_R is not set -+# CONFIG_SYS_MALLOC_BOOTPARAMS is not set -+# CONFIG_ID_EEPROM is not set -+# CONFIG_RESET_PHY_R is not set -+ -+# -+# Security support -+# -+CONFIG_HASH=y -+# CONFIG_STACKPROTECTOR is not set -+# CONFIG_BOARD_RNG_SEED is not set -+ -+# -+# Update support -+# -+# CONFIG_UPDATE_TFTP is not set -+# CONFIG_ANDROID_AB is not set -+ -+# -+# Blob list -+# -+# CONFIG_BLOBLIST is not set -+CONFIG_SUPPORT_SPL=y -+# CONFIG_VPL is not set -+ -+# -+# Command line interface -+# -+CONFIG_CMDLINE=y +CONFIG_HUSH_PARSER=y -+CONFIG_CMDLINE_EDITING=y -+# CONFIG_CMDLINE_PS_SUPPORT is not set -+CONFIG_AUTO_COMPLETE=y -+CONFIG_SYS_LONGHELP=y +CONFIG_SYS_PROMPT="OpenWrt One> " -+CONFIG_SYS_PROMPT_HUSH_PS2="> " +CONFIG_SYS_MAXARGS=16 -+CONFIG_SYS_CBSIZE=512 -+CONFIG_SYS_PBSIZE=1049 -+CONFIG_SYS_XTRACE=y -+CONFIG_BUILD_BIN2C=y -+ -+# -+# Commands -+# -+ -+# -+# Info commands -+# -+CONFIG_CMD_BDI=y -+# CONFIG_CMD_BDINFO_EXTRA is not set -+# CONFIG_CMD_CONFIG is not set -+CONFIG_CMD_CONSOLE=y +CONFIG_CMD_CPU=y -+# CONFIG_CMD_HISTORY is not set +CONFIG_CMD_LICENSE=y -+# CONFIG_CMD_PMC is not set -+ -+# -+# Boot commands -+# -+CONFIG_CMD_BOOTD=y -+CONFIG_CMD_BOOTM=y -+# CONFIG_CMD_BOOTDEV is not set -+CONFIG_CMD_BOOTFLOW=y -+# CONFIG_CMD_BOOTMETH is not set -+CONFIG_BOOTM_EFI=y -+# CONFIG_CMD_BOOTZ is not set -+CONFIG_CMD_BOOTI=y -+CONFIG_BOOTM_LINUX=y +# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_OPENRTOS is not set -+# CONFIG_BOOTM_OSE is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_CMD_VBE is not set +# CONFIG_BOOTM_VXWORKS is not set -+CONFIG_SYS_BOOTM_LEN=0x4000000 -+CONFIG_CMD_BOOTEFI=y -+CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y -+# CONFIG_CMD_BOOTEFI_HELLO is not set -+# CONFIG_CMD_BOOTEFI_SELFTEST is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y -+# CONFIG_CMD_ADTIMG is not set -+CONFIG_CMD_ELF=y -+CONFIG_CMD_FDT=y -+CONFIG_CMD_GO=y -+CONFIG_CMD_RUN=y -+CONFIG_CMD_IMI=y -+# CONFIG_CMD_IMLS is not set -+CONFIG_CMD_XIMG=y -+# CONFIG_CMD_ZBOOT is not set -+ -+# -+# Environment commands -+# +CONFIG_CMD_ASKENV=y -+CONFIG_CMD_EXPORTENV=y -+CONFIG_CMD_IMPORTENV=y -+CONFIG_CMD_EDITENV=y -+# CONFIG_CMD_GREPENV is not set -+CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ERASEENV=y -+CONFIG_CMD_ENV_EXISTS=y -+CONFIG_CMD_ENV_READMEM=y -+# CONFIG_CMD_ENV_CALLBACK is not set +CONFIG_CMD_ENV_FLAGS=y -+# CONFIG_CMD_NVEDIT_EFI is not set -+# CONFIG_CMD_NVEDIT_INDIRECT is not set -+# CONFIG_CMD_NVEDIT_INFO is not set -+# CONFIG_CMD_NVEDIT_LOAD is not set -+# CONFIG_CMD_NVEDIT_SELECT is not set -+ -+# -+# Memory commands -+# -+# CONFIG_CMD_BINOP is not set -+# CONFIG_CMD_BLOBLIST is not set -+CONFIG_CMD_CRC32=y -+# CONFIG_CRC32_VERIFY is not set -+# CONFIG_CMD_EEPROM is not set -+# CONFIG_LOOPW is not set -+# CONFIG_CMD_MD5SUM is not set -+# CONFIG_CMD_MEMINFO is not set -+CONFIG_CMD_MEMORY=y -+# CONFIG_CMD_MEM_SEARCH is not set -+# CONFIG_CMD_MX_CYCLIC is not set -+CONFIG_CMD_RANDOM=y -+# CONFIG_CMD_MEMTEST is not set -+# CONFIG_CMD_SHA1SUM is not set +CONFIG_CMD_STRINGS=y -+ -+# -+# Compression commands -+# -+CONFIG_CMD_LZMADEC=y +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_ZIP is not set -+ -+# -+# Device access commands -+# -+# CONFIG_CMD_ARMFLASH is not set -+# CONFIG_CMD_BIND is not set -+# CONFIG_CMD_CLK is not set -+# CONFIG_CMD_DEMO is not set -+# CONFIG_CMD_DFU is not set +CONFIG_CMD_DM=y -+CONFIG_CMD_FLASH=y -+# CONFIG_CMD_FPGAD is not set -+# CONFIG_CMD_FUSE is not set +CONFIG_CMD_GPIO=y -+# CONFIG_CMD_GPIO_READ is not set +CONFIG_CMD_PWM=y -+# CONFIG_CMD_GPT is not set -+# CONFIG_RANDOM_UUID is not set -+# CONFIG_CMD_IDE is not set -+# CONFIG_CMD_IO is not set -+# CONFIG_CMD_IOTRACE is not set -+# CONFIG_CMD_I2C is not set -+CONFIG_CMD_LOADB=y -+# CONFIG_CMD_LOADM is not set -+CONFIG_CMD_LOADS=y -+# CONFIG_LOADS_ECHO is not set -+# CONFIG_CMD_SAVES is not set -+# CONFIG_SYS_LOADS_BAUD_CHANGE is not set -+CONFIG_CMD_LOADXY_TIMEOUT=90 -+# CONFIG_CMD_LSBLK is not set -+# CONFIG_CMD_MBR is not set -+# CONFIG_CMD_CLONE is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_NAND_EXT=y -+# CONFIG_CMD_ONENAND is not set -+# CONFIG_CMD_OSD is not set -+# CONFIG_CMD_PART is not set +CONFIG_CMD_PCI=y -+CONFIG_CMD_PINMUX=y -+# CONFIG_CMD_POWEROFF is not set -+# CONFIG_CMD_READ is not set -+# CONFIG_CMD_SATA is not set -+# CONFIG_CMD_SDRAM is not set -+CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y -+# CONFIG_CMD_SPI is not set -+# CONFIG_CMD_TSI148 is not set -+# CONFIG_CMD_UNIVERSE is not set +CONFIG_CMD_USB=y -+# CONFIG_CMD_USB_SDP is not set -+# CONFIG_CMD_RKMTD is not set -+# CONFIG_CMD_WRITE is not set -+ -+# -+# Shell scripting commands -+# -+# CONFIG_CMD_CAT is not set -+CONFIG_CMD_ECHO=y -+CONFIG_CMD_ITEST=y -+CONFIG_CMD_SOURCE=y -+CONFIG_CMD_SETEXPR=y -+# CONFIG_CMD_SETEXPR_FMT is not set -+# CONFIG_CMD_XXD is not set -+ -+# -+# Android support commands -+# -+CONFIG_CMD_NET=y -+CONFIG_CMD_BOOTP=y -+CONFIG_CMD_DHCP=y -+# CONFIG_BOOTP_MAY_FAIL is not set -+CONFIG_BOOTP_BOOTPATH=y -+# CONFIG_BOOTP_VENDOREX is not set -+# CONFIG_BOOTP_BOOTFILESIZE is not set -+CONFIG_BOOTP_DNS=y -+# CONFIG_BOOTP_DNS2 is not set -+CONFIG_BOOTP_GATEWAY=y -+CONFIG_BOOTP_HOSTNAME=y -+# CONFIG_BOOTP_PREFER_SERVERIP is not set -+CONFIG_BOOTP_SUBNETMASK=y -+# CONFIG_BOOTP_NISDOMAIN is not set -+# CONFIG_BOOTP_NTPSERVER is not set -+# CONFIG_BOOTP_TIMEOFFSET is not set -+# CONFIG_CMD_PCAP is not set -+CONFIG_BOOTP_PXE=y -+CONFIG_BOOTP_PXE_CLIENTARCH=0x16 -+# CONFIG_BOOTP_PXE_DHCP_OPTION is not set -+CONFIG_BOOTP_VCI_STRING="U-Boot.armv8" -+CONFIG_CMD_TFTPBOOT=y -+# CONFIG_CMD_TFTPPUT is not set +CONFIG_CMD_TFTPSRV=y -+CONFIG_NET_TFTP_VARS=y +CONFIG_CMD_RARP=y -+# CONFIG_CMD_NFS is not set -+# CONFIG_SYS_DISABLE_AUTOLOAD is not set -+# CONFIG_CMD_WGET is not set -+# CONFIG_CMD_MII is not set -+# CONFIG_CMD_MDIO is not set -+CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y -+CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y -+# CONFIG_CMD_ETHSW is not set ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+# CONFIG_CMD_WOL is not set -+ -+# -+# Misc commands -+# -+# CONFIG_CMD_2048 is not set -+# CONFIG_CMD_BSP is not set -+CONFIG_CMD_BLOCK_CACHE=y -+CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y -+# CONFIG_CMD_CONITRACE is not set -+# CONFIG_CMD_CLS is not set -+# CONFIG_CMD_EFIDEBUG is not set -+CONFIG_CMD_EFICONFIG=y -+# CONFIG_CMD_EXCEPTION is not set -+CONFIG_CMD_LED=y -+# CONFIG_CMD_INI is not set -+# CONFIG_CMD_DATE is not set -+# CONFIG_CMD_TIME is not set -+# CONFIG_CMD_GETTIME is not set -+# CONFIG_CMD_PAUSE is not set -+CONFIG_CMD_SLEEP=y -+# CONFIG_CMD_TIMER is not set -+# CONFIG_CMD_SYSBOOT is not set -+# CONFIG_CMD_QFW is not set +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 -+CONFIG_CMD_PSTORE_MEM_SIZE=0x10000 -+CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000 -+CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000 -+CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000 -+CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000 -+CONFIG_CMD_PSTORE_ECC_SIZE=0 -+# CONFIG_CMD_TERMINAL is not set +CONFIG_CMD_UUID=y -+ -+# -+# TI specific command line interface -+# -+ -+# -+# Power commands -+# -+ -+# -+# Security commands -+# -+# CONFIG_CMD_AES is not set -+# CONFIG_CMD_BLOB is not set +CONFIG_CMD_HASH=y -+# CONFIG_CMD_HVC is not set +CONFIG_CMD_SMC=y -+# CONFIG_HASH_VERIFY is not set -+ -+# -+# Firmware commands -+# -+ -+# -+# Filesystem commands -+# -+# CONFIG_CMD_BTRFS is not set -+# CONFIG_CMD_EROFS is not set -+# CONFIG_CMD_EXT2 is not set -+# CONFIG_CMD_EXT4 is not set +CONFIG_CMD_FAT=y -+# CONFIG_CMD_SQUASHFS is not set +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y -+# CONFIG_CMD_JFFS2 is not set -+# CONFIG_CMD_MTDPARTS is not set -+CONFIG_MTDIDS_DEFAULT="" -+CONFIG_MTDPARTS_DEFAULT="" -+# CONFIG_CMD_REISER is not set -+# CONFIG_CMD_ZFS is not set -+ -+# -+# Debug commands -+# -+# CONFIG_CMD_DIAG is not set -+# CONFIG_CMD_EVENT is not set -+# CONFIG_CMD_LOG is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBI_RENAME=y -+CONFIG_CMD_UBIFS=y -+ -+# -+# Partition Types -+# -+CONFIG_PARTITIONS=y -+# CONFIG_MAC_PARTITION is not set -+CONFIG_DOS_PARTITION=y -+# CONFIG_ISO_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+CONFIG_PARTITION_UUIDS=y -+CONFIG_SUPPORT_OF_CONTROL=y -+ -+# -+# Device Tree Control -+# -+CONFIG_OF_CONTROL=y -+CONFIG_OF_REAL=y -+# CONFIG_OF_LIVE is not set -+CONFIG_OF_SEPARATE=y -+# CONFIG_OF_EMBED is not set -+# CONFIG_OF_BOARD is not set -+# CONFIG_OF_OMIT_DTB is not set -+CONFIG_DEVICE_TREE_INCLUDES="" -+CONFIG_OF_LIST="openwrt-one" -+# CONFIG_MULTI_DTB_FIT is not set -+CONFIG_OF_TAG_MIGRATE=y -+# CONFIG_OF_DTB_PROPS_REMOVE is not set -+ -+# -+# Environment -+# -+CONFIG_ENV_SUPPORT=y -+CONFIG_SAVEENV=y +CONFIG_ENV_OVERWRITE=y -+CONFIG_ENV_MIN_ENTRIES=64 -+CONFIG_ENV_MAX_ENTRIES=512 -+# CONFIG_ENV_IS_NOWHERE is not set -+# CONFIG_ENV_IS_IN_EEPROM is not set -+# CONFIG_ENV_IS_IN_FAT is not set -+# CONFIG_ENV_IS_IN_EXT4 is not set -+# CONFIG_ENV_IS_IN_FLASH is not set -+# CONFIG_ENV_IS_IN_MTD is not set -+# CONFIG_ENV_IS_IN_NAND is not set -+# CONFIG_ENV_IS_IN_NVRAM is not set -+# CONFIG_ENV_IS_IN_ONENAND is not set -+# CONFIG_ENV_IS_IN_REMOTE is not set -+# CONFIG_ENV_IS_IN_SPI_FLASH is not set +CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="ubi" +CONFIG_ENV_UBI_VOLUME="ubootenv" +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" -+# CONFIG_ENV_UBI_VOLUME_CREATE is not set -+CONFIG_ENV_UBI_VID_OFFSET=0 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y -+CONFIG_DEFAULT_ENV_FILE="openwrt-one-spi-nand_env" ++CONFIG_DEFAULT_ENV_FILE="defenvs/openwrt-one-spi-nand_env" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -+# CONFIG_ENV_IMPORT_FDT is not set -+# CONFIG_ENV_APPEND is not set -+# CONFIG_ENV_WRITEABLE_LIST is not set -+# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set -+# CONFIG_USE_BOOTFILE is not set -+# CONFIG_USE_ETHPRIME is not set -+# CONFIG_USE_HOSTNAME is not set -+# CONFIG_VERSION_VARIABLE is not set -+CONFIG_NET=y -+CONFIG_ARP_TIMEOUT=5000 -+CONFIG_NET_RETRY_COUNT=5 -+CONFIG_PROT_UDP=y -+CONFIG_BOOTDEV_ETH=y -+# CONFIG_BOOTP_SEND_HOSTNAME is not set ++CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y -+# CONFIG_NETCONSOLE is not set -+# CONFIG_IP_DEFRAG is not set -+# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set -+CONFIG_TFTP_BLOCKSIZE=1468 -+# CONFIG_TFTP_PORT is not set -+CONFIG_TFTP_WINDOWSIZE=1 -+# CONFIG_TFTP_TSIZE is not set -+# CONFIG_SERVERIP_FROM_PROXYDHCP is not set -+CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100 -+# CONFIG_KEEP_SERVERADDR is not set -+# CONFIG_UDP_CHECKSUM is not set -+# CONFIG_BOOTP_SERVERIP is not set -+CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64 -+# CONFIG_USE_GATEWAYIP is not set -+# CONFIG_USE_IPADDR is not set -+# CONFIG_USE_NETMASK is not set -+# CONFIG_USE_ROOTPATH is not set -+# CONFIG_USE_SERVERIP is not set -+# CONFIG_PROT_TCP is not set -+# CONFIG_IPV6 is not set -+CONFIG_SYS_RX_ETH_BUFFER=4 -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_DM=y -+# CONFIG_DM_WARN is not set -+# CONFIG_DM_DEBUG is not set -+# CONFIG_DM_STATS is not set -+CONFIG_DM_DEVICE_REMOVE=y -+CONFIG_DM_EVENT=y -+CONFIG_DM_STDIO=y -+CONFIG_DM_SEQ_ALIAS=y -+# CONFIG_DM_DMA is not set -+CONFIG_REGMAP=y -+CONFIG_SYSCON=y -+# CONFIG_DEVRES is not set -+CONFIG_SIMPLE_BUS=y -+# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set -+# CONFIG_SIMPLE_PM_BUS is not set -+CONFIG_OF_TRANSLATE=y -+# CONFIG_TRANSLATION_OFFSET is not set -+CONFIG_DM_DEV_READ_INLINE=y -+# CONFIG_OFNODE_MULTI_TREE is not set -+# CONFIG_BOUNCE_BUFFER is not set -+# CONFIG_ADC is not set -+# CONFIG_ADC_EXYNOS is not set -+# CONFIG_ADC_SANDBOX is not set -+# CONFIG_SARADC_MESON is not set -+# CONFIG_SARADC_ROCKCHIP is not set -+# CONFIG_SATA is not set -+# CONFIG_SCSI_AHCI is not set -+ -+# -+# SATA/SCSI device support -+# -+# CONFIG_AXI is not set -+ -+# -+# Bus devices -+# -+CONFIG_BLK=y -+CONFIG_BLOCK_CACHE=y -+# CONFIG_BLKMAP is not set -+# CONFIG_EFI_MEDIA is not set -+# CONFIG_IDE is not set -+# CONFIG_LBA48 is not set -+# CONFIG_SYS_64BIT_LBA is not set -+# CONFIG_RKMTD is not set -+# CONFIG_BOOTCOUNT_LIMIT is not set -+ -+# -+# Button Support -+# +CONFIG_BUTTON=y -+# CONFIG_BUTTON_ADC is not set +CONFIG_BUTTON_GPIO=y -+ -+# -+# Cache Controller drivers -+# -+# CONFIG_CACHE is not set -+# CONFIG_L2X0_CACHE is not set -+# CONFIG_V5L2_CACHE is not set -+# CONFIG_NCORE_CACHE is not set -+# CONFIG_SIFIVE_CCACHE is not set -+ -+# -+# Clock -+# +CONFIG_CLK=y -+# CONFIG_CLK_CCF is not set -+# CONFIG_CLK_GPIO is not set -+# CONFIG_CLK_CDCE9XX is not set -+# CONFIG_CLK_ICS8N3QV01 is not set -+# CONFIG_CLK_K210 is not set -+# CONFIG_CLK_MPC83XX is not set -+# CONFIG_CLK_XLNX_CLKWZRD is not set -+# CONFIG_CLK_AT91 is not set -+# CONFIG_CLK_RCAR is not set -+# CONFIG_CLK_RCAR_CPG_LIB is not set -+# CONFIG_CLK_SIFIVE is not set -+# CONFIG_CLK_TI_AM3_DPLL is not set -+# CONFIG_CLK_TI_CTRL is not set -+# CONFIG_CLK_TI_GATE is not set -+# CONFIG_CLK_K3 is not set -+CONFIG_CPU=y -+# CONFIG_CPU_IMX is not set -+ -+# -+# Hardware crypto devices -+# -+# CONFIG_DM_HASH is not set -+# CONFIG_FSL_CAAM is not set -+CONFIG_CAAM_64BIT=y -+# CONFIG_SYS_FSL_SEC_BE is not set -+# CONFIG_SYS_FSL_SEC_LE is not set -+# CONFIG_NPCM_AES is not set -+# CONFIG_NPCM_SHA is not set -+# CONFIG_DDR_SPD is not set -+# CONFIG_IMX_SNPS_DDR_PHY is not set -+ -+# -+# Demo for driver model -+# -+# CONFIG_DM_DEMO is not set -+ -+# -+# DFU support -+# -+ -+# -+# DMA Support -+# -+# CONFIG_DMA is not set -+# CONFIG_DMA_LPC32XX is not set -+# CONFIG_TI_EDMA3 is not set -+# CONFIG_DMA_LEGACY is not set -+ -+# -+# Extcon Support -+# -+# CONFIG_EXTCON is not set -+ -+# -+# Fastboot support -+# -+# CONFIG_UDP_FUNCTION_FASTBOOT is not set -+# CONFIG_TCP_FUNCTION_FASTBOOT is not set -+CONFIG_FIRMWARE=y -+CONFIG_ARM_PSCI_FW=y -+# CONFIG_ZYNQMP_FIRMWARE is not set -+# CONFIG_ARM_SMCCC_FEATURES is not set -+# CONFIG_ARM_FFA_TRANSPORT is not set -+# CONFIG_SCMI_FIRMWARE is not set -+# CONFIG_DM_FUZZING_ENGINE is not set -+ -+# -+# FPGA support -+# -+# CONFIG_FPGA_ALTERA is not set -+# CONFIG_FPGA_SOCFPGA is not set -+# CONFIG_FPGA_LATTICE is not set -+# CONFIG_FPGA_XILINX is not set -+# CONFIG_DM_FPGA is not set -+# CONFIG_FWU_MDATA is not set -+CONFIG_GPIO=y +CONFIG_GPIO_HOG=y -+# CONFIG_DM_GPIO_LOOKUP_LABEL is not set -+# CONFIG_ALTERA_PIO is not set -+# CONFIG_BCM2835_GPIO is not set -+# CONFIG_DWAPB_GPIO is not set -+# CONFIG_AT91_GPIO is not set -+# CONFIG_ATMEL_PIO4 is not set -+# CONFIG_ASPEED_GPIO is not set -+# CONFIG_DA8XX_GPIO is not set -+# CONFIG_HIKEY_GPIO is not set -+# CONFIG_INTEL_BROADWELL_GPIO is not set -+# CONFIG_INTEL_GPIO is not set -+# CONFIG_INTEL_ICH6_GPIO is not set -+# CONFIG_IMX_RGPIO2P is not set -+# CONFIG_IPROC_GPIO is not set -+# CONFIG_HSDK_CREG_GPIO is not set -+# CONFIG_KIRKWOOD_GPIO is not set -+# CONFIG_LPC32XX_GPIO is not set -+# CONFIG_MCP230XX_GPIO is not set -+# CONFIG_MSM_GPIO is not set -+# CONFIG_MXC_GPIO is not set -+# CONFIG_MXS_GPIO is not set -+# CONFIG_NPCM_GPIO is not set -+# CONFIG_CMD_PCA953X is not set -+# CONFIG_ROCKCHIP_GPIO is not set -+# CONFIG_XILINX_GPIO is not set -+# CONFIG_TCA642X is not set -+# CONFIG_TEGRA_GPIO is not set -+# CONFIG_TEGRA186_GPIO is not set -+# CONFIG_VYBRID_GPIO is not set -+# CONFIG_SIFIVE_GPIO is not set -+# CONFIG_ZYNQ_GPIO is not set -+# CONFIG_DM_74X164 is not set -+# CONFIG_PCA953X is not set -+# CONFIG_MPC8XXX_GPIO is not set -+# CONFIG_MPC8XX_GPIO is not set -+# CONFIG_NX_GPIO is not set -+# CONFIG_NOMADIK_GPIO is not set -+# CONFIG_ZYNQMP_GPIO_MODEPIN is not set -+# CONFIG_SLG7XL45106_I2C_GPO is not set -+# CONFIG_TURRIS_OMNIA_MCU is not set -+# CONFIG_FTGPIO010 is not set -+ -+# -+# Hardware Spinlock Support -+# -+# CONFIG_DM_HWSPINLOCK is not set -+CONFIG_I2C=y -+# CONFIG_DM_I2C is not set -+# CONFIG_SYS_I2C_LEGACY is not set -+# CONFIG_SPL_SYS_I2C_LEGACY is not set -+# CONFIG_SYS_I2C_FSL is not set -+# CONFIG_SYS_I2C_DW is not set -+# CONFIG_SYS_I2C_IMX_LPI2C is not set -+# CONFIG_SYS_I2C_MTK is not set -+# CONFIG_SYS_I2C_MICROCHIP is not set -+# CONFIG_SYS_I2C_MXC is not set -+# CONFIG_SYS_I2C_NPCM is not set -+# CONFIG_SYS_I2C_SOFT is not set -+# CONFIG_SYS_I2C_MV is not set -+# CONFIG_SYS_I2C_MVTWSI is not set -+CONFIG_INPUT=y -+# CONFIG_DM_KEYBOARD is not set -+# CONFIG_CROS_EC_KEYB is not set -+# CONFIG_TEGRA_KEYBOARD is not set -+# CONFIG_TWL4030_INPUT is not set -+ -+# -+# IOMMU device drivers -+# -+# CONFIG_IOMMU is not set -+ -+# -+# LED Support -+# +CONFIG_LED=y -+# CONFIG_LED_PWM is not set +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y -+# CONFIG_LED_STATUS is not set -+ -+# -+# Mailbox Controller Support -+# -+# CONFIG_DM_MAILBOX is not set -+ -+# -+# Memory Controller drivers -+# -+# CONFIG_MEMORY is not set -+# CONFIG_ATMEL_EBI is not set -+# CONFIG_MFD_ATMEL_SMC is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MISC is not set -+# CONFIG_NVMEM is not set -+# CONFIG_SPL_NVMEM is not set -+# CONFIG_SMSC_LPC47M is not set -+# CONFIG_SMSC_SIO1007 is not set -+# CONFIG_CROS_EC is not set -+# CONFIG_DS4510 is not set -+# CONFIG_FSL_SEC_MON is not set -+# CONFIG_IRQ is not set -+# CONFIG_NPCM_HOST is not set -+# CONFIG_NUVOTON_NCT6102D is not set -+# CONFIG_PWRSEQ is not set -+# CONFIG_PCA9551_LED is not set -+# CONFIG_TEST_DRV is not set -+# CONFIG_USB_HUB_USB251XB is not set -+# CONFIG_TWL4030_LED is not set -+# CONFIG_WINBOND_W83627 is not set -+# CONFIG_FS_LOADER is not set -+ -+# -+# MMC Host controller Support -+# +# CONFIG_MMC is not set -+# CONFIG_MMC_BROKEN_CD is not set -+# CONFIG_DM_MMC is not set -+# CONFIG_FSL_ESDHC is not set -+# CONFIG_FSL_ESDHC_IMX is not set -+ -+# -+# MTD Support -+# -+CONFIG_MTD_PARTITIONS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y -+# CONFIG_MTD_NOR_FLASH is not set -+# CONFIG_MTD_CONCAT is not set -+# CONFIG_SYS_MTDPARTS_RUNTIME is not set -+# CONFIG_FLASH_CFI_DRIVER is not set -+# CONFIG_CFI_FLASH is not set -+# CONFIG_ALTERA_QSPI is not set -+# CONFIG_HBMC_AM654 is not set -+# CONFIG_SAMSUNG_ONENAND is not set -+# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set -+CONFIG_MTD_NAND_CORE=y -+# CONFIG_MTD_RAW_NAND is not set +CONFIG_MTD_SPI_NAND=y -+ -+# -+# SPI Flash Support -+# +CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_BUS=0 -+CONFIG_SF_DEFAULT_CS=0 -+# CONFIG_BOOTDEV_SPI_FLASH is not set +CONFIG_SPI_FLASH_SFDP_SUPPORT=y -+CONFIG_SPI_FLASH_SMART_HWCAPS=y -+# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set -+# CONFIG_SPI_FLASH_SOFT_RESET is not set -+# CONFIG_SPI_FLASH_BAR is not set -+CONFIG_SPI_FLASH_LOCK=y -+CONFIG_SPI_FLASH_UNLOCK_ALL=y -+# CONFIG_SPI_FLASH_ATMEL is not set +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y -+# CONFIG_SPI_FLASH_S28HX_T is not set +CONFIG_SPI_FLASH_STMICRO=y -+# CONFIG_SPI_FLASH_MT35XU is not set -+# CONFIG_SPI_FLASH_SST is not set +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y -+# CONFIG_SPI_FLASH_ZBIT is not set -+CONFIG_SPI_FLASH_USE_4K_SECTORS=y -+# CONFIG_SPI_FLASH_DATAFLASH is not set +CONFIG_SPI_FLASH_MTD=y -+ -+# -+# UBI support -+# -+CONFIG_UBI_SILENCE_MSG=y -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_MODULE=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_LIMIT=20 -+# CONFIG_MTD_UBI_FASTMAP is not set -+# CONFIG_NVMXIP is not set -+# CONFIG_NVMXIP_QSPI is not set -+# CONFIG_NMBM is not set -+ -+# -+# Multiplexer drivers -+# -+# CONFIG_MULTIPLEXER is not set -+# CONFIG_BITBANGMII is not set -+# CONFIG_MV88E6352_SWITCH is not set -+CONFIG_PHYLIB=y -+# CONFIG_PHY_ADDR_ENABLE is not set -+# CONFIG_B53_SWITCH is not set -+# CONFIG_MV88E61XX_SWITCH is not set -+# CONFIG_PHYLIB_10G is not set -+# CONFIG_PHY_ADIN is not set -+# CONFIG_PHY_AIROHA is not set -+# CONFIG_PHY_AQUANTIA is not set -+# CONFIG_PHY_ATHEROS is not set -+# CONFIG_SPL_PHY_ATHEROS is not set -+# CONFIG_PHY_BROADCOM is not set -+# CONFIG_PHY_CORTINA is not set -+# CONFIG_PHY_DAVICOM is not set -+# CONFIG_PHY_ET1011C is not set -+# CONFIG_PHY_LXT is not set -+# CONFIG_PHY_MARVELL is not set -+# CONFIG_PHY_MARVELL_10G is not set -+# CONFIG_PHY_MESON_GXL is not set -+# CONFIG_PHY_MICREL is not set -+# CONFIG_PHY_MOTORCOMM is not set -+# CONFIG_PHY_MSCC is not set -+# CONFIG_PHY_NATSEMI is not set -+# CONFIG_PHY_NXP_C45_TJA11XX is not set -+# CONFIG_PHY_NXP_TJA11XX is not set -+# CONFIG_PHY_REALTEK is not set -+# CONFIG_PHY_SMSC is not set -+# CONFIG_PHY_TERANETICS is not set -+# CONFIG_PHY_TI is not set -+# CONFIG_PHY_TI_DP83867 is not set -+# CONFIG_PHY_TI_DP83869 is not set -+# CONFIG_PHY_TI_GENERIC is not set -+# CONFIG_PHY_VITESSE is not set -+# CONFIG_PHY_XILINX is not set -+# CONFIG_PHY_XILINX_GMII2RGMII is not set -+# CONFIG_PHY_XWAY is not set -+# CONFIG_PHY_ETHERNET_ID is not set +CONFIG_PHY_FIXED=y -+# CONFIG_PHY_NCSI is not set -+# CONFIG_FSL_MEMAC is not set -+CONFIG_PHY_RESET_DELAY=0 -+# CONFIG_FSL_PFE is not set -+CONFIG_ETH=y -+CONFIG_DM_ETH=y -+# CONFIG_DM_MDIO is not set -+# CONFIG_DM_ETH_PHY is not set -+CONFIG_NETDEVICES=y -+# CONFIG_PHY_GIGE is not set -+# CONFIG_ALTERA_TSE is not set -+# CONFIG_BCM_SF2_ETH is not set -+# CONFIG_BCMGENET is not set -+# CONFIG_BNXT_ETH is not set -+# CONFIG_CALXEDA_XGMAC is not set -+# CONFIG_DRIVER_DM9000 is not set -+# CONFIG_DWC_ETH_QOS is not set -+# CONFIG_EEPRO100 is not set -+# CONFIG_ETH_DESIGNWARE is not set -+# CONFIG_ETH_DESIGNWARE_MESON8B is not set -+# CONFIG_ETHOC is not set -+# CONFIG_FMAN_ENET is not set -+# CONFIG_FTMAC100 is not set -+# CONFIG_FTGMAC100 is not set -+# CONFIG_MCFFEC is not set -+# CONFIG_FSLDMAFEC is not set -+# CONFIG_KS8851_MLL is not set -+# CONFIG_LITEETH is not set -+# CONFIG_MACB is not set -+# CONFIG_NET_NPCM750 is not set -+# CONFIG_PCH_GBE is not set -+# CONFIG_RGMII is not set -+# CONFIG_MII is not set -+# CONFIG_RMII is not set -+# CONFIG_PCNET is not set -+# CONFIG_QE_UEC is not set -+# CONFIG_RTL8139 is not set -+# CONFIG_SMC911X is not set -+# CONFIG_SUN7I_GMAC is not set -+# CONFIG_SUN4I_EMAC is not set -+# CONFIG_SUN8I_EMAC is not set -+# CONFIG_SH_ETHER is not set -+# CONFIG_DRIVER_TI_CPSW is not set -+# CONFIG_DRIVER_TI_EMAC is not set -+# CONFIG_DRIVER_TI_KEYSTONE_NET is not set -+# CONFIG_TULIP is not set -+# CONFIG_XILINX_AXIEMAC is not set -+# CONFIG_VSC7385_ENET is not set -+# CONFIG_XILINX_EMACLITE is not set -+# CONFIG_ZYNQ_GEM is not set -+# CONFIG_SYS_DPAA_QBMAN is not set -+# CONFIG_TSEC_ENET is not set +CONFIG_MEDIATEK_ETH=y -+# CONFIG_HIFEMAC_ETH is not set -+# CONFIG_HIGMACV300_ETH is not set -+# CONFIG_NVME is not set -+# CONFIG_NVME_APPLE is not set -+ -+# -+# PCI Endpoint -+# -+# CONFIG_PCI_ENDPOINT is not set -+# CONFIG_X86_PCH7 is not set -+# CONFIG_X86_PCH9 is not set -+ -+# -+# PHY Subsystem -+# +CONFIG_PHY=y -+# CONFIG_NOP_PHY is not set -+# CONFIG_MIPI_DPHY_HELPERS is not set -+# CONFIG_BCM_SR_PCIE_PHY is not set -+# CONFIG_OMAP_USB2_PHY is not set +CONFIG_PHY_MTK_TPHY=y -+ -+# -+# Rockchip PHY driver -+# -+# CONFIG_PHY_CADENCE_SIERRA is not set -+# CONFIG_PHY_CADENCE_TORRENT is not set -+# CONFIG_MSM8916_USB_PHY is not set -+# CONFIG_MVEBU_COMPHY_SUPPORT is not set -+ -+# -+# Pin controllers -+# +CONFIG_PINCTRL=y -+CONFIG_PINCTRL_FULL=y -+CONFIG_PINCTRL_GENERIC=y -+CONFIG_PINMUX=y +CONFIG_PINCONF=y -+CONFIG_PINCONF_RECURSIVE=y -+# CONFIG_PINCTRL_AT91 is not set -+# CONFIG_PINCTRL_AT91PIO4 is not set -+# CONFIG_PINCTRL_INTEL is not set -+# CONFIG_PINCTRL_QE is not set -+# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set -+# CONFIG_PINCTRL_SINGLE is not set -+# CONFIG_PINCTRL_STM32 is not set -+# CONFIG_PINCTRL_STMFX is not set -+# CONFIG_PINCTRL_K210 is not set -+CONFIG_PINCTRL_MTK=y -+# CONFIG_PINCTRL_MT7622 is not set -+# CONFIG_PINCTRL_MT7623 is not set -+# CONFIG_PINCTRL_MT7629 is not set +CONFIG_PINCTRL_MT7981=y -+# CONFIG_PINCTRL_MT7986 is not set -+# CONFIG_PINCTRL_MT7988 is not set -+# CONFIG_PINCTRL_MT8512 is not set -+# CONFIG_PINCTRL_MT8516 is not set -+# CONFIG_PINCTRL_MT8518 is not set -+CONFIG_POWER=y -+# CONFIG_POWER_LEGACY is not set -+# CONFIG_ACPI_PMC is not set -+ -+# -+# Power Domain Support -+# +CONFIG_POWER_DOMAIN=y -+# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set +CONFIG_MTK_POWER_DOMAIN=y -+# CONFIG_DM_PMIC is not set -+# CONFIG_PMIC_TPS65217 is not set -+# CONFIG_POWER_TPS65218 is not set -+# CONFIG_POWER_TPS62362 is not set -+# CONFIG_DM_REGULATOR is not set -+# CONFIG_TPS6586X_POWER is not set -+# CONFIG_POWER_MT6323 is not set +CONFIG_DM_PWM=y -+# CONFIG_PWM_ASPEED is not set -+# CONFIG_PWM_CADENCE_TTC is not set -+# CONFIG_PWM_CROS_EC is not set -+# CONFIG_PWM_EXYNOS is not set -+# CONFIG_PWM_IMX is not set -+# CONFIG_PWM_MESON is not set +CONFIG_PWM_MTK=y -+# CONFIG_PWM_ROCKCHIP is not set -+# CONFIG_PWM_SANDBOX is not set -+# CONFIG_PWM_SIFIVE is not set -+# CONFIG_PWM_TEGRA is not set -+# CONFIG_PWM_SUNXI is not set -+# CONFIG_U_QE is not set -+# CONFIG_RAM is not set -+ -+# -+# Reboot Mode Support -+# -+# CONFIG_DM_REBOOT_MODE is not set -+ -+# -+# Remote Processor drivers -+# -+ -+# -+# Reset Controller Support -+# -+# CONFIG_RESET_AST2500 is not set -+# CONFIG_RESET_AST2600 is not set -+CONFIG_RESET_MEDIATEK=y -+# CONFIG_RESET_HISILICON is not set -+# CONFIG_RESET_SYSCON is not set -+# CONFIG_RESET_SCMI is not set -+# CONFIG_RESET_DRA7 is not set -+# CONFIG_DM_RNG is not set -+ -+# -+# Real Time Clock -+# -+# CONFIG_DM_RTC is not set -+# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set -+# CONFIG_RTC_DS1337 is not set -+# CONFIG_RTC_DS1338 is not set -+# CONFIG_RTC_DS1374 is not set -+# CONFIG_RTC_DS3231 is not set -+# CONFIG_RTC_PCF8563 is not set -+# CONFIG_RTC_PT7C4338 is not set -+# CONFIG_RTC_PL031 is not set -+# CONFIG_RTC_S35392A is not set -+# CONFIG_RTC_MC13XXX is not set -+# CONFIG_RTC_MC146818 is not set -+# CONFIG_RTC_M41T62 is not set -+# CONFIG_SCSI is not set -+# CONFIG_DM_SCSI is not set -+CONFIG_SERIAL=y -+CONFIG_BAUDRATE=115200 -+# CONFIG_DEFAULT_ENV_IS_RW is not set -+CONFIG_REQUIRE_SERIAL_CONSOLE=y -+# CONFIG_SPECIFY_CONSOLE_INDEX is not set -+CONFIG_SERIAL_PRESENT=y +CONFIG_DM_SERIAL=y -+# CONFIG_SERIAL_RX_BUFFER is not set -+# CONFIG_SERIAL_PUTS is not set -+# CONFIG_SERIAL_SEARCH_ALL is not set -+# CONFIG_SERIAL_PROBE_ALL is not set -+# CONFIG_VPL_DM_SERIAL is not set -+CONFIG_DEBUG_UART_MTK=y -+CONFIG_DEBUG_UART_SHIFT=0 -+# CONFIG_DEBUG_UART_ANNOUNCE is not set -+# CONFIG_DEBUG_UART_SKIP_INIT is not set -+# CONFIG_ALTERA_JTAG_UART is not set -+# CONFIG_ALTERA_UART is not set -+# CONFIG_ARC_SERIAL is not set -+# CONFIG_ARM_DCC is not set -+# CONFIG_ATMEL_USART is not set -+# CONFIG_BCM6345_SERIAL is not set -+# CONFIG_COREBOOT_SERIAL is not set -+# CONFIG_CORTINA_UART is not set -+# CONFIG_FSL_LINFLEXUART is not set -+# CONFIG_FSL_LPUART is not set -+# CONFIG_MVEBU_A3700_UART is not set -+# CONFIG_MCFUART is not set -+# CONFIG_NULLDEV_SERIAL is not set -+# CONFIG_SYS_NS16550 is not set -+# CONFIG_PL01X_SERIAL is not set -+# CONFIG_ROCKCHIP_SERIAL is not set -+# CONFIG_XILINX_UARTLITE is not set -+# CONFIG_MSM_SERIAL is not set -+# CONFIG_MSM_GENI_SERIAL is not set -+# CONFIG_MXS_AUART_SERIAL is not set -+# CONFIG_OMAP_SERIAL is not set -+# CONFIG_SIFIVE_SERIAL is not set -+# CONFIG_ZYNQ_SERIAL is not set +CONFIG_MTK_SERIAL=y -+# CONFIG_MT7620_SERIAL is not set -+# CONFIG_NPCM_SERIAL is not set -+# CONFIG_SM is not set -+# CONFIG_MESON_SM is not set -+# CONFIG_SMEM is not set -+ -+# -+# Sound support -+# -+# CONFIG_SOUND is not set -+ -+# -+# SOC (System On Chip) specific Drivers -+# -+# CONFIG_SOC_DEVICE is not set -+# CONFIG_SOC_TI is not set +CONFIG_SPI=y +CONFIG_DM_SPI=y -+CONFIG_SPI_MEM=y -+# CONFIG_SPI_DIRMAP is not set -+# CONFIG_ALTERA_SPI is not set -+# CONFIG_APPLE_SPI is not set -+# CONFIG_ATCSPI200_SPI is not set -+# CONFIG_ATMEL_SPI is not set -+# CONFIG_BCMSTB_SPI is not set -+# CONFIG_CORTINA_SFLASH is not set -+# CONFIG_CADENCE_QSPI is not set -+# CONFIG_CF_SPI is not set -+# CONFIG_DESIGNWARE_SPI is not set -+# CONFIG_EXYNOS_SPI is not set -+# CONFIG_FSL_DSPI is not set -+# CONFIG_FSL_QSPI is not set -+# CONFIG_GXP_SPI is not set -+# CONFIG_ICH_SPI is not set -+# CONFIG_IPROC_QSPI is not set -+# CONFIG_KIRKWOOD_SPI is not set -+# CONFIG_MICROCHIP_COREQSPI is not set -+# CONFIG_MPC8XXX_SPI is not set -+# CONFIG_MTK_SNOR is not set -+# CONFIG_MTK_SNFI_SPI is not set +CONFIG_MTK_SPIM=y -+# CONFIG_MVEBU_A3700_SPI is not set -+# CONFIG_MXS_SPI is not set -+# CONFIG_SPI_MXIC is not set -+# CONFIG_NPCM_FIU_SPI is not set -+# CONFIG_NPCM_PSPI is not set -+# CONFIG_NXP_FSPI is not set -+# CONFIG_OMAP3_SPI is not set -+# CONFIG_PL022_SPI is not set -+# CONFIG_ROCKCHIP_SFC is not set -+# CONFIG_ROCKCHIP_SPI is not set -+# CONFIG_SPI_ASPEED_SMC is not set -+# CONFIG_SPI_SIFIVE is not set -+# CONFIG_SOFT_SPI is not set -+# CONFIG_SPI_SN_F_OSPI is not set -+# CONFIG_SPI_SUNXI is not set -+# CONFIG_TEGRA114_SPI is not set -+# CONFIG_TEGRA20_SFLASH is not set -+# CONFIG_TEGRA20_SLINK is not set -+# CONFIG_TEGRA210_QSPI is not set -+# CONFIG_TI_QSPI is not set -+# CONFIG_XILINX_SPI is not set -+# CONFIG_ZYNQ_SPI is not set -+# CONFIG_ZYNQ_QSPI is not set -+# CONFIG_ZYNQMP_GQSPI is not set -+# CONFIG_SH_QSPI is not set -+# CONFIG_MXC_SPI is not set -+ -+# -+# SPMI support -+# -+# CONFIG_SPMI is not set -+# CONFIG_SYSINFO is not set -+ -+# -+# System reset device drivers -+# -+# CONFIG_SYSRESET is not set -+# CONFIG_TEE is not set -+# CONFIG_DM_THERMAL is not set -+ -+# -+# Timer Support -+# -+# CONFIG_TIMER is not set -+ -+# -+# TPM support -+# +CONFIG_USB=y -+CONFIG_DM_USB=y -+# CONFIG_DM_USB_GADGET is not set -+ -+# -+# USB Host Controller Drivers -+# -+CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y -+# CONFIG_USB_XHCI_DWC3 is not set -+# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set +CONFIG_USB_XHCI_MTK=y -+# CONFIG_USB_XHCI_FSL is not set -+# CONFIG_USB_XHCI_BRCM is not set -+# CONFIG_USB_EHCI_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_DWC2 is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_ISP1760 is not set -+# CONFIG_USB_CDNS3 is not set -+# CONFIG_USB_DWC3 is not set -+# CONFIG_USB_MTU3 is not set -+ -+# -+# Legacy MUSB Support -+# -+# CONFIG_USB_MUSB_HCD is not set -+# CONFIG_USB_MUSB_UDC is not set -+ -+# -+# MUSB Controller Driver -+# -+# CONFIG_USB_MUSB_HOST is not set -+# CONFIG_USB_MUSB_PIO_ONLY is not set -+ -+# -+# USB Phy -+# -+# CONFIG_TWL4030_USB is not set -+# CONFIG_ROCKCHIP_USB2_PHY is not set -+ -+# -+# ULPI drivers -+# -+ -+# -+# USB peripherals -+# +CONFIG_USB_STORAGE=y -+# CONFIG_USB_KEYBOARD is not set -+# CONFIG_USB_ONBOARD_HUB is not set -+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000 -+# CONFIG_USB_HOST_ETHER is not set -+# CONFIG_USB_GADGET is not set -+# CONFIG_SPL_USB_GADGET is not set -+ -+# -+# UFS Host Controller Support -+# -+# CONFIG_TI_J721E_UFS is not set -+ -+# -+# Graphics support -+# -+# CONFIG_VIDEO is not set -+ -+# -+# VirtIO Drivers -+# -+# CONFIG_VIRTIO_MMIO is not set -+ -+# -+# 1-Wire support -+# -+# CONFIG_W1 is not set -+ -+# -+# 1-wire EEPROM support -+# -+# CONFIG_W1_EEPROM is not set -+ -+# -+# Watchdog Timer Support -+# -+# CONFIG_WATCHDOG is not set -+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 -+# CONFIG_IMX_WATCHDOG is not set -+# CONFIG_ULP_WATCHDOG is not set -+# CONFIG_WDT is not set -+# CONFIG_PHYS_TO_BUS is not set -+ -+# -+# File systems -+# -+# CONFIG_FS_BTRFS is not set -+# CONFIG_FS_CBFS is not set -+# CONFIG_FS_EXT4 is not set -+CONFIG_FS_FAT=y -+CONFIG_FAT_WRITE=y -+CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 -+# CONFIG_FS_JFFS2 is not set -+CONFIG_UBIFS_SILENCE_MSG=y -+CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y -+# CONFIG_FS_CRAMFS is not set -+# CONFIG_YAFFS2 is not set -+# CONFIG_FS_SQUASHFS is not set -+# CONFIG_FS_EROFS is not set -+ -+# -+# Library routines -+# -+# CONFIG_ADDR_MAP is not set -+# CONFIG_SYS_TIMER_COUNTS_DOWN is not set -+# CONFIG_PHYSMEM is not set -+# CONFIG_BCH is not set -+# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set -+CONFIG_CHARSET=y -+# CONFIG_DYNAMIC_CRC_TABLE is not set -+CONFIG_LIB_UUID=y -+# CONFIG_SEMIHOSTING is not set -+CONFIG_PRINTF=y -+CONFIG_SPRINTF=y -+CONFIG_STRTO=y -+CONFIG_SYS_HZ=1000 -+# CONFIG_PANIC_HANG is not set -+CONFIG_REGEX=y -+CONFIG_LIB_RAND=y -+# CONFIG_LIB_HW_RAND is not set -+CONFIG_SUPPORT_ACPI=y -+# CONFIG_ACPI is not set -+CONFIG_RBTREE=y -+# CONFIG_BITREVERSE is not set -+# CONFIG_TRACE is not set -+# CONFIG_CIRCBUF is not set -+# CONFIG_CMD_DHRYSTONE is not set -+ -+# -+# Security support -+# -+# CONFIG_AES is not set -+# CONFIG_ECDSA is not set -+# CONFIG_RSA is not set -+# CONFIG_TPM is not set -+ -+# -+# Android Verified Boot -+# -+ -+# -+# Hashing Support -+# -+# CONFIG_BLAKE2 is not set -+CONFIG_SHA1=y -+CONFIG_SHA256=y -+# CONFIG_SHA512 is not set -+# CONFIG_SHA384 is not set -+# CONFIG_SHA_HW_ACCEL is not set -+CONFIG_MD5=y -+CONFIG_CRC8=y -+CONFIG_CRC32=y -+ -+# -+# Compression Support -+# -+# CONFIG_LZ4 is not set -+CONFIG_LZMA=y -+CONFIG_LZO=y -+CONFIG_GZIP=y -+# CONFIG_ZLIB_UNCOMPRESS is not set -+# CONFIG_BZIP2 is not set -+CONFIG_ZLIB=y -+# CONFIG_ZSTD is not set -+CONFIG_VPL_LZMA=y -+# CONFIG_SPL_GZIP is not set -+# CONFIG_ERRNO_STR is not set +CONFIG_HEXDUMP=y -+# CONFIG_GETOPT is not set -+CONFIG_OF_LIBFDT=y -+CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 -+CONFIG_SYS_FDT_PAD=0x3000 -+ -+# -+# System tables -+# -+CONFIG_GENERATE_SMBIOS_TABLE=y -+# CONFIG_LIB_RATIONAL is not set -+CONFIG_SMBIOS=y -+# CONFIG_SMBIOS_PARSER is not set -+CONFIG_EFI_LOADER=y -+CONFIG_CMD_BOOTEFI_BOOTMGR=y -+CONFIG_EFI_VARIABLE_FILE_STORE=y -+# CONFIG_EFI_VARIABLE_NO_STORE is not set -+# CONFIG_EFI_VARIABLES_PRESEED is not set -+CONFIG_EFI_VAR_BUF_SIZE=131072 -+# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set -+# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set -+CONFIG_EFI_CAPSULE_MAX=15 -+CONFIG_EFI_DEVICE_PATH_TO_TEXT=y -+CONFIG_EFI_DEVICE_PATH_UTIL=y -+CONFIG_EFI_DT_FIXUP=y -+CONFIG_EFI_LOADER_HII=y -+CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y -+CONFIG_EFI_UNICODE_CAPITALIZATION=y -+# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set -+CONFIG_EFI_PLATFORM_LANG_CODES="en-US" -+CONFIG_EFI_HAVE_RUNTIME_RESET=y -+CONFIG_EFI_LOAD_FILE2_INITRD=y -+CONFIG_EFI_ECPT=y -+CONFIG_EFI_EBBR_2_1_CONFORMANCE=y -+# CONFIG_OPTEE_LIB is not set -+# CONFIG_OPTEE_IMAGE is not set -+# CONFIG_BOOTM_OPTEE is not set -+# CONFIG_TEST_FDTDEC is not set -+CONFIG_LIB_ELF=y -+CONFIG_LMB=y -+CONFIG_LMB_USE_MAX_REGIONS=y -+CONFIG_LMB_MAX_REGIONS=64 -+# CONFIG_PHANDLE_CHECK_SEQ is not set -+ -+# -+# Testing -+# -+# CONFIG_UNIT_TEST is not set -+# CONFIG_POST is not set -+ -+# -+# Tools options -+# -+CONFIG_MKIMAGE_DTC_PATH="dtc" -+CONFIG_TOOLS_CRC32=y -+CONFIG_TOOLS_LIBCRYPTO=y -+CONFIG_TOOLS_FIT=y -+CONFIG_TOOLS_FIT_FULL_CHECK=y -+CONFIG_TOOLS_FIT_PRINT=y -+CONFIG_TOOLS_FIT_RSASSA_PSS=y -+CONFIG_TOOLS_FIT_SIGNATURE=y -+CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000 -+CONFIG_TOOLS_FIT_VERBOSE=y -+CONFIG_TOOLS_MD5=y -+CONFIG_TOOLS_OF_LIBFDT=y -+CONFIG_TOOLS_SHA1=y -+CONFIG_TOOLS_SHA256=y -+CONFIG_TOOLS_SHA384=y -+CONFIG_TOOLS_SHA512=y -+# CONFIG_TOOLS_MKEFICAPSULE is not set -+# CONFIG_FSPI_CONF_HEADER is not set -+# CONFIG_TOOLS_MKFWUMDATA is not set --- /dev/null -+++ b/openwrt-one-nor_env -@@ -0,0 +1,46 @@ ++++ b/defenvs/openwrt-one-nor_env +@@ -0,0 +1,48 @@ ++ethaddr_factory=mtd read factory 0x46000000 0x0 0x20000 && env readmem -b ethaddr 0x4600002a 0x6 ; setenv ethaddr_factory +bl2_mtd_write=mtd erase bl2-nor && mtd write bl2-nor $loadaddr 0x0 0x40000 +bl2_tftp_write=tftpboot $loadaddr $bootfile_bl2_nor && run bl2_mtd_write +bootcmd=run check_button ; run led_start ; mtd read recovery ${loadaddr} ; bootm ; run led_loop_error @@ -3878,16 +502,18 @@ +serverip=192.168.11.23 +tftp_boot=run led_start ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf +tftp_write=run led_start ; tftpboot $loadaddr $bootfile && mtd erase recovery 0x0 ${filesize} && mtd write recovery $loadaddr 0x0 ${filesize} ++usb_pgood_delay=4000 +usb_recovery=run led_start ; usb start && run usb_recovery_bl2 && run usb_recovery_ubi && run led_loop_done +usb_recovery_bl2=fatload usb 0:1 ${loadaddr} ${recoverfile_bl2} && run recovery_write_bl2 +usb_recovery_ubi=fatload usb 0:1 ${loadaddr} ${recoverfile_ubi} && run recovery_write_ubi -+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" -+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; bootmenu +_init_env=setenv _init_env ; echo Initialize Env ; run ubi_create_env ; saveenv +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null -+++ b/openwrt-one-spi-nand_env -@@ -0,0 +1,59 @@ ++++ b/defenvs/openwrt-one-spi-nand_env +@@ -0,0 +1,62 @@ ++ethaddr_factory=mtd read factory 0x46000000 0x0 0x20000 && env readmem -b ethaddr 0x4600002a 0x6 ; setenv ethaddr_factory +ipaddr=192.168.11.11 +serverip=192.168.11.23 +loadaddr=0x46000000 @@ -3928,6 +554,7 @@ +check_buttons=if button front ; then run boot_recovery ; run boot_tftp ; run led_loop_error ; else if button back ; then ; run usb_recover ; run led_loop_error ; fi ; fi +led_boot=led green on ; led white on ; led red on +led_done=led green on ; led white off ; led red off ++led_loop_done=led white off ; led green on ; echo done ; while true ; do sleep 1 ; done +led_loop_error=led white off ; led green off ; while true ; do led red on ; sleep 1 ; led red off ; sleep 1 ; done +led_start=led white on ; led green off ; led red off +preboot=run led_boot @@ -3938,12 +565,13 @@ +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++usb_pgood_delay=4000 +usb_recover=run led_start ; usb start && run usb_recover_production && run led_loop_done +usb_recover_production=fatload usb 0:1 ${loadaddr} ${bootfile_upg} && iminfo $loadaddr && run ubi_write_production +ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip $filesize static && ubi write $loadaddr fip $filesize +ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize +ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv -+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; bootmenu +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch b/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch new file mode 100644 index 0000000000..00d58cd59b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/454-add-glinet-x3000.patch @@ -0,0 +1,277 @@ +--- /dev/null ++++ b/arch/arm/dts/mt7981-glinet-gl-x3000.dts +@@ -0,0 +1,144 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "GL.iNet GL-X3000"; ++ compatible = "glinet,gl-x3000", "mediatek,mt7981"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wifi2g { ++ label = "green:wifi2g"; ++ gpios = <&gpio 30 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wifi5g { ++ label = "green:wifi5g"; ++ gpios = <&gpio 38 GPIO_ACTIVE_LOW>; ++ }; ++ ++ 5g_led1 { ++ label = "green:5g:led1"; ++ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ }; ++ ++ 5g_led2 { ++ label = "green:5g:led2"; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ 5g_led3 { ++ label = "green:5g:led3"; ++ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ }; ++ ++ 5g_led4 { ++ label = "green:5g:led4"; ++ gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ power { ++ label = "green:power"; ++ gpios = <&gpio 39 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wan { ++ label = "green:wan"; ++ gpios = <&gpio 31 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <1>; ++ phy-mode = "gmii"; ++ phy-handle = <&phy0>; ++ ++ mdio { ++ phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-id03a2.9461"; ++ reg = <0x0>; ++ phy-mode = "gmii"; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <8>; ++ cap-mmc-hw-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0-pins-default { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ conf-cmd-dat { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", ++ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", ++ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; ++ input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ conf-clk { ++ pins = "SPI1_CS"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ conf-rst { ++ pins = "GPIO_WPS"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/mt7981_glinet_gl-x3000_defconfig +@@ -0,0 +1,98 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x80000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-glinet-gl-x3000" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_ENV_VARS_UBOOT_CONFIG=y ++# CONFIG_EXPERT is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_FIT=y ++# CONFIG_BOOTSTD is not set ++# CONFIG_LEGACY_IMAGE_FORMAT is not set ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-glinet-gl-x3000.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_LOGLEVEL=7 ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_ELF is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++# CONFIG_CMD_UNLZ4 is not set ++# CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_GPT_RENAME=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_READ=y ++CONFIG_CMD_WRITE=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/glinet_gl-x3000_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/defenvs/glinet_gl-x3000_env +@@ -0,0 +1,26 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++bootdelay=3 ++bootfile_bl2=openwrt-mediatek-filogic-glinet_gl-x3000-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-glinet_gl-x3000-bl31-uboot.fip ++bootfile_firmware=openwrt-mediatek-filogic-glinet_gl-x3000-squashfs-factory.bin ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_title= *** U-Boot Boot Menu for GL-iNet GL-X3000 *** ++bootmenu_0=Startup system (Default).=run boot_system ++bootmenu_1=Load Firmware via TFTP then write to eMMC.=run boot_tftp_firmware ; run bootmenu_confirm_return ++bootmenu_2=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_3=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_4=Reboot.=reset ++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset ++filesize_to_blk=setexpr cnt $filesize + 0x1ff && setexpr cnt $cnt / 0x200 ++mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size ++boot_system=run init_modem && part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm ++boot_tftp_firmware=tftpboot $loadaddr $bootfile_firmware && run emmc_write_firmware ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++emmc_write_firmware=part start mmc 0 kernel part_addr && run filesize_to_blk && mmc write $loadaddr $part_addr $cnt ++emmc_write_bl2=run filesize_to_blk && test 0x$cnt -le 0x800 && mmc partconf 0 1 1 1 && mmc write $loadaddr 0x0 0x800 ; mmc partconf 0 1 1 0 ++emmc_write_fip=part start mmc 0 fip part_addr && part size mmc 0 fip part_size && run filesize_to_blk && test 0x$cnt -le 0x$part_size && mmc write $loadaddr $part_addr $cnt ++init_modem=gpio set 10; gpio set 5; gpio set 9; gpio set 11; sleep 0.1; gpio clear 10; sleep 1 ++reset_factory=eraseenv && reset diff --git a/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch new file mode 100644 index 0000000000..539f5bf4d3 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch @@ -0,0 +1,302 @@ +--- /dev/null ++++ b/configs/mt7988a_arcadyan_mozart_defconfig +@@ -0,0 +1,113 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-arcadyan-mozart" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7988=y ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-arcadyan-mozart.dtb" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/arcadyan_mozart_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/defenvs/arcadyan_mozart_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-1 ++bootconf_extra= ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-arcadyan_mozart-initramfs.itb ++bootfile_bl2=openwrt-mediatek-filogic-arcadyan_mozart-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-arcadyan_mozart-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-arcadyan_mozart-squashfs-sysupgrade.itb ++bootled_pwr=blue:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/arch/arm/dts/mt7988a-arcadyan-mozart.dts +@@ -0,0 +1,125 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++/dts-v1/; ++#include "mt7988.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ model = "MediaTek / Arcadyan - Mozart"; ++ compatible = "arcadyan,mozart", "mediatek,mt7988"; ++ ++ chosen { ++ stdout-path = &uart0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x40000000>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 143 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-red { ++ label = "red:status"; ++ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-green { ++ label = "blue:status"; ++ gpios = <&gpio 30 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-blue { ++ label = "blue:status"; ++ gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++ð0 { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "usxgmii"; ++ mediatek,switch = "mt7988"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; diff --git a/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch b/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch new file mode 100644 index 0000000000..118959b8ee --- /dev/null +++ b/package/boot/uboot-mediatek/patches/457-initialized-the-watchdog-subsystem-later.patch @@ -0,0 +1,54 @@ +From 9c1ad8a18ac1a20aee7a617964bcae3e90dac700 Mon Sep 17 00:00:00 2001 +From: Enrico Mioso <mrkiko.rs@gmail.com> +Date: Wed, 23 Oct 2024 17:46:35 +0200 +Subject: [PATCH] uboot-mediatek: initialized the watchdog subsystem later + +Initialize the watchdog subsystem later during initialization, to allow for +the gpio-wdt driver to work. + +Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com> +--- + common/board_r.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +--- a/common/board_r.c ++++ b/common/board_r.c +@@ -682,19 +682,13 @@ static init_fnc_t init_sequence_r[] = { + serial_initialize, + initr_announce, + dm_announce, +-#if CONFIG_IS_ENABLED(WDT) +- initr_watchdog, +-#endif +- INIT_FUNC_WATCHDOG_RESET + arch_initr_trap, + #if defined(CONFIG_BOARD_EARLY_INIT_R) + board_early_init_r, + #endif +- INIT_FUNC_WATCHDOG_RESET + #ifdef CONFIG_POST + post_output_backlog, + #endif +- INIT_FUNC_WATCHDOG_RESET + #if defined(CONFIG_PCI_INIT_R) && defined(CONFIG_SYS_EARLY_PCI_INIT) + /* + * Do early PCI configuration _before_ the flash gets initialised, +@@ -709,7 +703,6 @@ static init_fnc_t init_sequence_r[] = { + #ifdef CONFIG_MTD_NOR_FLASH + initr_flash, + #endif +- INIT_FUNC_WATCHDOG_RESET + #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) + /* initialize higher level parts of CPU like time base and timers */ + cpu_init_r, +@@ -738,6 +731,10 @@ static init_fnc_t init_sequence_r[] = { + #ifdef CONFIG_PVBLOCK + initr_pvblock, + #endif ++#if CONFIG_IS_ENABLED(WDT) ++ initr_watchdog, ++#endif ++ INIT_FUNC_WATCHDOG_RESET + initr_env, + #ifdef CONFIG_SYS_MALLOC_BOOTPARAMS + initr_malloc_bootparams, diff --git a/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch b/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch new file mode 100644 index 0000000000..b7c70bb185 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/458-add-GatoNetworks-GDSP.patch @@ -0,0 +1,403 @@ +From 57d0f608d925cb688b5c9b71512fca7d228f07f6 Mon Sep 17 00:00:00 2001 +From: Enrico Mioso <mrkiko.rs@gmail.com> +Date: Wed, 23 Oct 2024 20:39:28 +0200 +Subject: [PATCH] add GatoNetworks GDSP + +Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com> +--- + arch/arm/dts/mt7981-gatonetworks_gdsp.dts | 200 +++++++++++++++++++++ + configs/mt7981_gatonetworks_gdsp_defconfig | 144 +++++++++++++++ + gatonetworks_gdsp_env | 38 ++++ + 3 files changed, 382 insertions(+) + create mode 100644 arch/arm/dts/mt7981-gatonetworks_gdsp.dts + create mode 100644 configs/mt7981_gatonetworks_gdsp_defconfig + create mode 100644 gatonetworks_gdsp_env + +--- /dev/null ++++ b/arch/arm/dts/mt7981-gatonetworks_gdsp.dts +@@ -0,0 +1,200 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "GatoNetworks GDSP"; ++ compatible = "gatonetworks,gdsp", "mediatek,mt7981"; ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ sim1 { ++ label = "sim1"; ++ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sim2 { ++ label = "sim2"; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg1 { ++ label = "sg1"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg2 { ++ label = "sg2"; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg3 { ++ label = "sg3"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg4 { ++ label = "sg4"; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg5 { ++ label = "sg5"; ++ gpios = <&gpio 8 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sg6 { ++ label = "sg6"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ gpio-watchdog { ++ compatible = "linux,wdt-gpio"; ++ gpios = <&gpio 6 GPIO_ACTIVE_LOW>; ++ hw_algo = "toggle"; ++ hw_margin_ms = <25000>; ++ always-running; ++ u-boot,autostart; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&spi2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@00000 { ++ label = "BL2"; ++ reg = <0x00000 0x0040000>; ++ read-only; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x0010000>; ++ }; ++ ++ partition@50000 { ++ label = "Factory"; ++ reg = <0x50000 0x00B0000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "FIP"; ++ reg = <0x100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "firmware"; ++ reg = <0x180000 0x1E80000>; ++ }; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ uart1_pins: uart1-pins { ++ mux { ++ function = "uart"; ++ groups = "uart1_0"; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_0_tx_rx"; ++ }; ++ }; ++ ++ spi2_flash_pins: spi2-pins { ++ mux { ++ function = "spi"; ++ groups = "spi2", "spi2_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/mt7981_gatonetworks_gdsp_defconfig +@@ -0,0 +1,141 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x10000 ++CONFIG_ENV_OFFSET=0x0 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-gatonetworks_gdsp" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_WATCHDOG_TIMEOUT_MSECS=25000 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_SPI_BOOT=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_USE_PREBOOT=y ++CONFIG_DEFAULT_FDT_FILE="mt7981-gatonetworks_gdsp" ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_LOGLEVEL=7 ++CONFIG_CONSOLE_MUX=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="GDSP> " ++CONFIG_SYS_MAXARGS=16 ++CONFIG_CMD_BDINFO_EXTRA=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_HISTORY=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_CALLBACK=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CRC32_VERIFY=y ++CONFIG_LOOPW=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MEMTEST=y ++CONFIG_CMD_STRINGS=y ++# CONFIG_CMD_UNLZ4 is not set ++# CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPIO_READ=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_MTD=y ++# CONFIG_CMD_NAND_EXT is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_CAT=y ++CONFIG_CMD_SETEXPR_FMT=y ++CONFIG_CMD_XXD=y ++CONFIG_CMD_TFTPPUT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++# CONFIG_CMD_EFICONFIG is not set ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="u-boot-env" ++CONFIG_ENV_SIZE_REDUND=0x0 ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/gatonetworks_gdsp_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_ISSI=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_UBI_SILENCE_MSG=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_WDT=y ++CONFIG_WDT_GPIO=y ++CONFIG_UBIFS_SILENCE_MSG=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/defenvs/gatonetworks_gdsp_env +@@ -0,0 +1,38 @@ ++load_factory_data=if env exists factory_data_present ; then else mtd read Factory $loadaddr 0x0 0x1000 ; setenv factory_data_present 1 ; fi ++lan_mac_factory=run load_factory_data ; setexpr macoffs $loadaddr + 0x2a ; env readmem -b lan_mac $macoffs 0x6 ; setenv lan_mac_factory ; setenv macoffs ++wan_mac_factory=run load_factory_data ; setexpr macoffs $loadaddr + 0x24 ; env readmem -b wan_mac $macoffs 0x6 ; setenv wan_mac_factory ; setenv macoffs ++label_mac_factory=run load_factory_data ; setexpr macoffs $loadaddr + 0x4 ; env readmem -b label_mac $macoffs 0x6 ; setenv label_mac_factory ; setenv macoffs ++ethaddr_factory=setenv ethaddr $lan_mac ; setenv ethaddr_factory ++wifi_mac_factory=setenv wifi_mac $label_mac ; setenv wifi_mac_factory ++env_cleanup=setenv load_factory_data ; setenv factory_data_present ; setenv env_cleanup ++ipaddr=192.168.1.1 ++serverip=192.168.1.10 ++loadaddr=0x46000000 ++bootcmd=run boot_nor ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-gatonetworks_gdsp-initramfs-kernel.bin ++bootfile_upg=openwrt-mediatek-filogic-gatonetworks_gdsp-squashfs-sysupgrade.bin ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )[0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return ++bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return ++bootmenu_4=Reset all settings to factory defaults.=run reset_factory ; reset ++bootmenu_5=Reboot.=reset ++boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever ++boot_nor=mtd read firmware ${loadaddr} ; bootm $loadaddr ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done ++boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production ++reset_factory=env default -a && saveenv && reset ++nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x1e80000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run lan_mac_factory ; run wan_mac_factory ; run label_mac_factory ; run env_cleanup ; run ethaddr_factory ; run wifi_mac_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch b/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch new file mode 100644 index 0000000000..5b0968aff6 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/459-add-mercusys-mr90x-v1.patch @@ -0,0 +1,342 @@ +--- /dev/null ++++ b/configs/mt7986_mercusys_mr90x-v1_defconfig +@@ -0,0 +1,106 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986b-mercusys_mr90x-v1" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007ef00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986b-mercusys_mr90x-v1.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/mercusys_mr90x-v1_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++# CONFIG_I2C is not set ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_RANDOM_UUID=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/arch/arm/dts/mt7986b-mercusys_mr90x-v1.dts +@@ -0,0 +1,174 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2024 ++ * Author: Mikhail Zhilkin <csharper2005@gmail.com> ++ */ ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "MERCUSYS MR90X v1"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "green:lan2"; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-1 { ++ label = "green:lan1"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-2 { ++ label = "green:lan0"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-3 { ++ label = "green:wan"; ++ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-4 { ++ label = "amber:status"; ++ gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led_status_green: led-5 { ++ label = "green:status"; ++ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <20000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ reg = <0x0 0x100000>; ++ label = "bl2"; ++ }; ++ ++ partition@100000 { ++ reg = <0x100000 0x100000>; ++ label = "factory"; ++ }; ++ ++ partition@200000 { ++ reg = <0x200000 0x7e00000>; ++ label = "ubi"; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/defenvs/mercusys_mr90x-v1_env +@@ -0,0 +1,53 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=console=ttyS0,115200n8 console_msg_format=syslog ++bootcmd=run check_buttons ; run boot_production ; run boot_recovery ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-mercusys_mr90x-v1-ubi-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-mercusys_mr90x-v1-ubi-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-mercusys_mr90x-v1-ubi-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-mercusys_mr90x-v1-ubi-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NAND][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_production ; noboot= ; replacevol= ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_recovery ; noboot= ; replacevol= ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_default=run led_boot ; run bootcmd ; run boot_recovery ; replacevol=1 ; run boot_tftp_forever ++boot_production=run led_boot ; run ubi_read_production && bootm $loadaddr#$bootconf ++boot_recovery=run led_boot ; run ubi_read_recovery && bootm $loadaddr#$bootconf ++boot_tftp=run led_boot ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_forever=run led_boot ; while true ; do run boot_tftp ; sleep 1 ; done ++boot_tftp_production=run led_boot ; tftpboot $loadaddr $bootfile_upg && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_production ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run led_boot ; tftpboot $loadaddr $bootfile && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_recovery ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=run led_boot ; tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory ++boot_tftp_write_bl2=run led_boot ; tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++check_buttons=if button reset ; then run boot_tftp ; fi ++ethaddr_factory=mtd read factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40088000 0x6 ; setenv ethaddr_factory ++led_boot=led green:status off ; led amber:status on ++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x40000 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip $filesize static && ubi write $loadaddr fip $filesize ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; bootmenu ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch b/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch new file mode 100644 index 0000000000..23d9917b79 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/460-add-routerich-ax3000.patch @@ -0,0 +1,359 @@ +--- /dev/null ++++ b/configs/mt7981_routerich_ax3000_defconfig +@@ -0,0 +1,105 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-routerich_ax3000" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7981=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_PRE_CON_BUF_ADDR=0x4007ef00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-routerich_ax3000.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="defenvs/routerich_ax3000_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y +--- /dev/null ++++ b/arch/arm/dts/mt7981-routerich_ax3000.dts +@@ -0,0 +1,187 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Routerich AX3000"; ++ compatible = "routerich,ax3000", "mediatek,mt7981"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ button-0 { ++ label = "mesh"; ++ linux,code = <BTN_0>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button-1 { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "red:wlan5g"; ++ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-1 { ++ label = "red:wan"; ++ gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-2 { ++ label = "blue:power"; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-3 { ++ label = "blue:lan1"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-4 { ++ label = "blue:lan2"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-5 { ++ label = "blue:lan3"; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-6 { ++ label = "blue:wan"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-7 { ++ label = "blue:wlan2g"; ++ gpios = <&gpio 34 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-8 { ++ label = "blue:mesh"; ++ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "uboot-env-orig"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@160000 { ++ label = "Factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/defenvs/routerich_ax3000_env +@@ -0,0 +1,58 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=run check_buttons ; if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-routerich_ax3000-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-routerich_ax3000-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-routerich_ax3000-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-routerich_ax3000-ubootmod-squashfs-sysupgrade.itb ++bootled_pwr=blue:power ++bootled_rec=blue:power ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++check_buttons=if button reset ; then run boot_tftp ; fi ++ethaddr_factory=mtd read Factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40080004 0x6 ; setenv ethaddr_factory ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mvebu/Makefile b/package/boot/uboot-mvebu/Makefile index 535180f4c8..d4c86aca29 100644 --- a/package/boot/uboot-mvebu/Makefile +++ b/package/boot/uboot-mvebu/Makefile @@ -8,10 +8,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.04 +PKG_VERSION:=2024.10 PKG_RELEASE:=1 -PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a +PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -77,6 +77,9 @@ UBOOT_TARGETS:= \ eDPU \ rb5009 +UBOOT_CUSTOMIZE_CONFIG := \ + --disable TOOLS_MKEFICAPSULE + define Package/u-boot/install $(if $(findstring cortexa53,$(BUILD_SUBTARGET)),,$(Package/u-boot/install/default)) endef diff --git a/package/boot/uboot-mvebu/patches/0001-arm-mvebu-turris_omnia-Enable-LTO-by-default-on-Turr.patch b/package/boot/uboot-mvebu/patches/0001-arm-mvebu-turris_omnia-Enable-LTO-by-default-on-Turr.patch deleted file mode 100644 index 3381e055f4..0000000000 --- a/package/boot/uboot-mvebu/patches/0001-arm-mvebu-turris_omnia-Enable-LTO-by-default-on-Turr.patch +++ /dev/null @@ -1,30 +0,0 @@ -From ca4ecdce4cdcfab7df101b5df6ddad43d2f549e1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org> -Date: Thu, 4 Apr 2024 09:50:50 +0200 -Subject: [PATCH] arm: mvebu: turris_omnia: Enable LTO by default on Turris - Omnia -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -U-Boot builds for Turris Omnia are approaching the limit of 0xf0000 -bytes, which is the size of the U-Boot partition on Omnia. - -Enable LTO to get more size optimized binaries. - -Signed-off-by: Marek Behún <kabel@kernel.org> -Reviewed-by: Stefan Roese <sr@denx.de> ---- - configs/turris_omnia_defconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/configs/turris_omnia_defconfig -+++ b/configs/turris_omnia_defconfig -@@ -31,6 +31,7 @@ CONFIG_AHCI=y - CONFIG_OF_BOARD_FIXUP=y - CONFIG_SYS_MEMTEST_START=0x00800000 - CONFIG_SYS_MEMTEST_END=0x00ffffff -+CONFIG_LTO=y - CONFIG_HAS_BOARD_SIZE_LIMIT=y - CONFIG_BOARD_SIZE_LIMIT=983040 - CONFIG_FIT=y diff --git a/package/boot/uboot-mvebu/patches/100-mvebu-armada-8k-respect-CONFIG_DISTRO_DEFAULTS.patch b/package/boot/uboot-mvebu/patches/100-mvebu-armada-8k-respect-CONFIG_DISTRO_DEFAULTS.patch deleted file mode 100644 index f32f246022..0000000000 --- a/package/boot/uboot-mvebu/patches/100-mvebu-armada-8k-respect-CONFIG_DISTRO_DEFAULTS.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a322b1cbb3f3e606d33a11fd18df20811e5c16f2 Mon Sep 17 00:00:00 2001 -From: Robert Marko <robimarko@gmail.com> -Date: Fri, 21 Jun 2024 11:41:30 +0200 -Subject: [PATCH 1/3] mvebu: armada-8k: respect CONFIG_DISTRO_DEFAULTS - -Currently, Armada 8k config header is setting boot devices and including -<config_distro_bootcmd.h> regardless of the CONFIG_DISTRO_DEFAULTS being -enabled or not, thus populating the environment for distro boot even on -devices that have no need for it. - -So, lets simply respect the value of CONFIG_DISTRO_DEFAULTS. - -Signed-off-by: Robert Marko <robimarko@gmail.com> ---- - include/configs/mvebu_armada-8k.h | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/include/configs/mvebu_armada-8k.h -+++ b/include/configs/mvebu_armada-8k.h -@@ -30,7 +30,7 @@ - /* - * PCI configuration - */ -- -+#ifdef CONFIG_DISTRO_DEFAULTS - #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ -@@ -40,6 +40,9 @@ - func(DHCP, dhcp, na) - - #include <config_distro_bootcmd.h> -+#else -+#define BOOTENV -+#endif - - #define CFG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0x6d00000\0" \ diff --git a/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch b/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch index eb7bbdbf48..0fe3a4cbb6 100644 --- a/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch +++ b/package/boot/uboot-mvebu/patches/101-net-mvpp2-fix-10GBase-R-support.patch @@ -18,7 +18,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com> --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c -@@ -3255,6 +3255,76 @@ static int gop_gpcs_reset(struct mvpp2_p +@@ -3254,6 +3254,76 @@ static int gop_gpcs_reset(struct mvpp2_p return 0; } @@ -95,7 +95,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com> static int gop_mpcs_mode(struct mvpp2_port *port) { u32 val; -@@ -3397,7 +3467,10 @@ static int gop_port_init(struct mvpp2_po +@@ -3396,7 +3466,10 @@ static int gop_port_init(struct mvpp2_po num_of_act_lanes = 2; mac_num = 0; /* configure PCS */ diff --git a/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch b/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch index b1b94cc566..4730532100 100644 --- a/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch +++ b/package/boot/uboot-mvebu/patches/102-arm-mvebu-add-support-for-MikroTik-RB5009UG-S-IN.patch @@ -31,7 +31,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com> --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -333,6 +333,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ +@@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-uDPU.dtb \ armada-7040-db-nand.dtb \ armada-7040-db.dtb \ diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 48d72ca55c..ed93b63c34 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,11 +5,11 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.07 +PKG_VERSION:=2025.01 PKG_RELEASE:=1 -PKG_HASH:=f591da9ab90ef3d6b3d173766d0ddff90c4ed7330680897486117df390d83c8f +PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f -PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de> +PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de> UBOOT_USE_BINMAN:=1 UBOOT_USE_INTREE_DTC:=1 @@ -24,6 +24,24 @@ define U-Boot/Default endef +# RK3308 boards + +define U-Boot/rk3308/Default + BUILD_SUBTARGET:=armv8 + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308 + ATF:=rk3308_bl31_v2.26.elf + TPL:=rk3308_ddr_589MHz_uart2_m1_v2.07.bin +endef + +define U-Boot/rock-pi-s-rk3308 + $(U-Boot/rk3308/Default) + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308-rock-pi-s + TPL:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin + NAME:=ROCK Pi S + BUILD_DEVICES:= \ + radxa_rock-pi-s +endef + # RK3328 boards define U-Boot/rk3328/Default @@ -88,6 +106,13 @@ define U-Boot/rock-pi-e-rk3328 radxa_rock-pi-e endef +define U-Boot/rock-pi-e-v3-rk3328 + $(U-Boot/rk3328/Default) + NAME:=ROCK Pi E v3.0 + BUILD_DEVICES:= \ + radxa_rock-pi-e-v3 +endef + # RK3399 boards define U-Boot/rk3399/Default @@ -113,7 +138,7 @@ endef define U-Boot/rock-pi-4-rk3399 $(U-Boot/rk3399/Default) - NAME:=Rock Pi 4 + NAME:=ROCK Pi 4 BUILD_DEVICES:= \ radxa_rock-pi-4a endef @@ -135,6 +160,13 @@ define U-Boot/rk3566/Default TPL:=rk3566_ddr_1056MHz_v1.21.bin endef +define U-Boot/nanopi-r3s-rk3566 + $(U-Boot/rk3566/Default) + NAME:=NanoPi R3S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r3s +endef + define U-Boot/radxa-cm3-io-rk3566 $(U-Boot/rk3566/Default) NAME:=CM3 IO @@ -142,6 +174,21 @@ define U-Boot/radxa-cm3-io-rk3566 radxa_cm3-io endef +define U-Boot/radxa-zero-3-rk3566 + $(U-Boot/rk3566/Default) + NAME:=ZERO 3E/3W + BUILD_DEVICES:= \ + radxa_zero-3e \ + radxa_zero-3w +endef + +define U-Boot/rock-3c-rk3566 + $(U-Boot/rk3566/Default) + NAME:=ROCK 3C + BUILD_DEVICES:= \ + radxa_rock-3c +endef + # RK3568 boards define U-Boot/rk3568/Default @@ -174,16 +221,88 @@ endef define U-Boot/radxa-e25-rk3568 $(U-Boot/rk3568/Default) + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568-e25 + TPL:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin NAME:=E25 BUILD_DEVICES:= \ radxa_e25 endef +define U-Boot/rock-3a-rk3568 + $(U-Boot/rk3568/Default) + NAME:=ROCK 3A + BUILD_DEVICES:= \ + radxa_rock-3a +endef + +define U-Boot/rock-3b-rk3568 + $(U-Boot/rk3568/Default) + NAME:=ROCK 3B + BUILD_DEVICES:= \ + radxa_rock-3b +endef + + +# RK3588 boards + +define U-Boot/rk3588/Default + BUILD_SUBTARGET:=armv8 + DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3588 + ATF:=rk3588_bl31_v1.45.elf + TPL:=rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin +endef + +define U-Boot/nanopc-t6-rk3588 + $(U-Boot/rk3588/Default) + NAME:=NanoPC T6 + BUILD_DEVICES:= \ + friendlyarm_nanopc-t6 +endef + +define U-Boot/rock5b-rk3588 + $(U-Boot/rk3588/Default) + NAME:=ROCK 5B + BUILD_DEVICES:= \ + radxa_rock-5b +endef + +define U-Boot/sige7-rk3588 + $(U-Boot/rk3588/Default) + NAME:=Sige7 + BUILD_DEVICES:= \ + armsom_sige7 +endef + + +# RK3588S boards + +define U-Boot/nanopi-r6c-rk3588s + $(U-Boot/rk3588/Default) + NAME:=NanoPi R6C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r6c +endef + +define U-Boot/nanopi-r6s-rk3588s + $(U-Boot/rk3588/Default) + NAME:=NanoPi R6S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r6s +endef + +define U-Boot/rock5a-rk3588s + $(U-Boot/rk3588/Default) + NAME:=ROCK 5A + BUILD_DEVICES:= \ + radxa_rock-5a +endef + UBOOT_TARGETS := \ nanopc-t4-rk3399 \ nanopi-r4s-rk3399 \ rock-pi-4-rk3399 \ rockpro64-rk3399 \ + rock-pi-s-rk3308 \ nanopi-r2c-rk3328 \ nanopi-r2c-plus-rk3328 \ nanopi-r2s-rk3328 \ @@ -192,11 +311,23 @@ UBOOT_TARGETS := \ roc-cc-rk3328 \ rock64-rk3328 \ rock-pi-e-rk3328 \ + rock-pi-e-v3-rk3328 \ + nanopi-r3s-rk3566 \ radxa-cm3-io-rk3566 \ + radxa-zero-3-rk3566 \ + rock-3c-rk3566 \ bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ - radxa-e25-rk3568 + radxa-e25-rk3568 \ + rock-3a-rk3568 \ + rock-3b-rk3568 \ + nanopc-t6-rk3588 \ + rock5b-rk3588 \ + sige7-rk3588 \ + nanopi-r6c-rk3588s \ + nanopi-r6s-rk3588s \ + rock5a-rk3588s UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-add-FriendlyElec-NanoPi-R3S.patch b/package/boot/uboot-rockchip/patches/100-rockchip-add-FriendlyElec-NanoPi-R3S.patch new file mode 100644 index 0000000000..65d4b0416e --- /dev/null +++ b/package/boot/uboot-rockchip/patches/100-rockchip-add-FriendlyElec-NanoPi-R3S.patch @@ -0,0 +1,661 @@ +--- /dev/null ++++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +@@ -0,0 +1,25 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> ++ * ++ * Copyright (c) 2024 Kevin Zhang <kevin@kevinzhang.me> ++ */ ++ ++#include "rk356x-u-boot.dtsi" ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++}; ++ ++&vcc5v0_usb { ++ /delete-property/ regulator-always-on; ++ /delete-property/ regulator-boot-on; ++}; ++ +--- /dev/null ++++ b/configs/nanopi-r3s-rk3566_defconfig +@@ -0,0 +1,73 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3566-nanopi-r3s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_TARGET_NANOPI_R3S_RK3566=y ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_RTL8169=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +--- /dev/null ++++ b/arch/arm/dts/rk3566-nanopi-r3s.dts +@@ -0,0 +1,554 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. ++ * ++ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * ++ * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com> ++ */ ++ ++/dts-v1/; ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/leds/common.h> ++#include <dt-bindings/pinctrl/rockchip.h> ++#include <dt-bindings/soc/rockchip,vop2.h> ++#include "rk3566.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R3S"; ++ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&reset_button_pin>; ++ ++ button-reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; ++ ++ power_led: led-0 { ++ color = <LED_COLOR_ID_RED>; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ lan_led: led-1 { ++ color = <LED_COLOR_ID_GREEN>; ++ function = LED_FUNCTION_LAN; ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wan_led: led-2 { ++ color = <LED_COLOR_ID_GREEN>; ++ function = LED_FUNCTION_WAN; ++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ vcc3v3_sys: regulator-vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vdd_usbc>; ++ }; ++ ++ vcc5v0_usb: regulator-vcc5v0_usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vdd_usbc: regulator-vdd-usbc { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_usbc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&rgmii_phy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m0_miim ++ &gmac1m0_tx_bus2_level3 ++ &gmac1m0_rx_bus2 ++ &gmac1m0_rgmii_clk_level2 ++ &gmac1m0_rgmii_bus_level3>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; ++ wakeup-source; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ interrupt-parent = <&gpio4>; ++ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-leds { ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ power_led_pin: power-led-pin { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gmac { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic-int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rockchip-key { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ rtc { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en: vcc5v0-usb-host-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_3v3>; ++ vccio5-supply = <&vcc_1v8>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ no-sdio; ++ no-mmc; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ extcon = <&usb2phy0>; ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; diff --git a/package/boot/uboot-sifiveu/Makefile b/package/boot/uboot-sifiveu/Makefile index 4cbfe344af..9c91fc726d 100644 --- a/package/boot/uboot-sifiveu/Makefile +++ b/package/boot/uboot-sifiveu/Makefile @@ -7,8 +7,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_RELEASE:=1 -PKG_VERSION:=2022.10 -PKG_HASH:=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8 +PKG_VERSION:=2023.10 +PKG_HASH:=e00e6c6f014e046101739d08d06f328811cebcf5ae101348f409cbbd55ce6900 UBOOT_USE_INTREE_DTC:=1 @@ -58,7 +58,7 @@ define Build/InstallDev $(INSTALL_BIN) $(PKG_BUILD_DIR)/spl/u-boot-spl.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)-spl $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(DTS_DIR)/$(UBOOT_DTS) $(STAGING_DIR_IMAGE)/$(UBOOT_DTS) - mkimage -C none -A arm -T script -d uEnv-$(UENV).txt \ + mkimage -C none -A riscv -T script -d uEnv-$(UENV).txt \ $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr endef diff --git a/package/boot/uboot-sifiveu/patches/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch b/package/boot/uboot-sifiveu/patches/0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch index 7e11d4c18b..233df7acb6 100644 --- a/package/boot/uboot-sifiveu/patches/0002-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch +++ b/package/boot/uboot-sifiveu/patches/0001-board-sifive-spl-Initialized-the-PWM-setting-in-the-.patch @@ -1,19 +1,42 @@ -From 725595e667cc4423347c255da8ca4c5b3aa0980a Mon Sep 17 00:00:00 2001 +From 2ba4e6d78e0a63e5d491f9b01b498899e58cb58d Mon Sep 17 00:00:00 2001 From: Vincent Chen <vincent.chen@sifive.com> Date: Mon, 15 Nov 2021 03:31:04 -0800 -Subject: [PATCH 2/8] board: sifive: spl: Initialized the PWM setting in the +Subject: [PATCH 1/5] board: sifive: spl: Initialized the PWM setting in the SPL stage LEDs and multiple fans can be controlled by SPL. This patch ensures that all fans have been enabled in the SPL stage. In addition, the LED's color will be set to yellow. + +Upstream-Status: Pending +Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- - board/sifive/unmatched/Makefile | 1 + - board/sifive/unmatched/pwm.c | 57 +++++++++++++++++++++++++++++++++ - board/sifive/unmatched/spl.c | 2 ++ - 3 files changed, 60 insertions(+) + arch/riscv/include/asm/arch-fu740/eeprom.h | 15 ++++++ + board/sifive/unmatched/Makefile | 1 + + board/sifive/unmatched/pwm.c | 57 ++++++++++++++++++++++ + board/sifive/unmatched/spl.c | 2 + + 4 files changed, 75 insertions(+) + create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h create mode 100644 board/sifive/unmatched/pwm.c +--- /dev/null ++++ b/arch/riscv/include/asm/arch-fu740/eeprom.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2021 SiFive, Inc. ++ * ++ * Zong Li <zong.li@sifve.com> ++ */ ++ ++#ifndef _ASM_RISCV_EEPROM_H ++#define _ASM_RISCV_EEPROM_H ++ ++#define PCB_REVISION_REV3 0x3 ++ ++u8 get_pcb_revision_from_eeprom(void); ++ ++#endif /* _ASM_RISCV_EEPROM_H */ --- a/board/sifive/unmatched/Makefile +++ b/board/sifive/unmatched/Makefile @@ -9,3 +9,4 @@ obj-y += spl.o diff --git a/package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch b/package/boot/uboot-sifiveu/patches/0002-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch index a98271acbc..6235f6cb2d 100644 --- a/package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch +++ b/package/boot/uboot-sifiveu/patches/0002-board-sifive-Set-LED-s-color-to-purple-in-the-U-boot.patch @@ -1,13 +1,16 @@ -From 7ead6d662a2f9d8498af6650ea38418c64b52048 Mon Sep 17 00:00:00 2001 +From 0dfab8fab80107aa4ad7d41a8ff47e5ff59632f9 Mon Sep 17 00:00:00 2001 From: Vincent Chen <vincent.chen@sifive.com> Date: Mon, 24 Jan 2022 02:42:02 -0800 -Subject: [PATCH 3/8] board: sifive: Set LED's color to purple in the U-boot +Subject: [PATCH 2/5] board: sifive: Set LED's color to purple in the U-boot stage Set LED's color to purple in the U-boot stage. Because there are still some functions to be executed before board_early_init_f(), it means the LED's is not changed to purple instantly when entering the U-boot stage. + +Upstream-Status: Pending +Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- board/sifive/unmatched/pwm.c | 7 +++++++ board/sifive/unmatched/unmatched.c | 6 ++++++ @@ -52,7 +55,7 @@ stage. /* enable all cache ways */ --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig -@@ -62,3 +62,4 @@ CONFIG_DM_SCSI=y +@@ -63,3 +63,4 @@ CONFIG_DM_SCSI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/package/boot/uboot-sifiveu/patches/0004-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch b/package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch index b5bffd22bd..3a381444a1 100644 --- a/package/boot/uboot-sifiveu/patches/0004-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch +++ b/package/boot/uboot-sifiveu/patches/0003-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch @@ -1,20 +1,23 @@ -From 6ef7023c0dcfde320015ab19e0e0d423921be77d Mon Sep 17 00:00:00 2001 +From 1a48019dd4b69dd76551217a61cc4cab9e92fd39 Mon Sep 17 00:00:00 2001 From: Vincent Chen <vincent.chen@sifive.com> Date: Mon, 15 Nov 2021 03:39:07 -0800 -Subject: [PATCH 1/2] board: sifive: Set LED's color to blue before jumping to +Subject: [PATCH 3/5] board: sifive: Set LED's color to blue before jumping to Linux The LED's color wil be changed from purple to blue before executing the sysboot command. Because the sysboot command includes the image loading from the boot partition, It means the LED's color is blue when executing "Retrieving file: /Image.gz". + +Upstream-Status: Pending +Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- include/configs/sifive-unmatched.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h -@@ -49,7 +49,12 @@ +@@ -48,6 +48,11 @@ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ @@ -26,5 +29,4 @@ from the boot partition, It means the LED's color is blue when executing + "sysboot ${devtype} ${devnum}:${distro_bootpart} any " \ + "${scriptaddr} ${prefix}${boot_syslinux_conf};\0" - #define CONFIG_SYS_EEPROM_BUS_NUM 0 - + #endif /* __SIFIVE_UNMATCHED_H */ diff --git a/package/boot/uboot-sifiveu/patches/0004-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch b/package/boot/uboot-sifiveu/patches/0004-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch new file mode 100644 index 0000000000..1db843c153 --- /dev/null +++ b/package/boot/uboot-sifiveu/patches/0004-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch @@ -0,0 +1,67 @@ +From 877afdf63129caa64d70d4a1252eec44778cfa0e Mon Sep 17 00:00:00 2001 +From: Vincent Chen <vincent.chen@sifive.com> +Date: Mon, 24 Jan 2022 02:57:40 -0800 +Subject: [PATCH 4/5] board: sifive: spl: Set remote thermal of TMP451 to 85 + deg C + + for the unmatched board + +For TMP451 on the unmatched board, the default value of the remote +thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL. + +Upstream-Status: Pending +Signed-off-by: Vincent Chen <vincent.chen@sifive.com> +Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> +--- + board/sifive/unmatched/spl.c | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +--- a/board/sifive/unmatched/spl.c ++++ b/board/sifive/unmatched/spl.c +@@ -10,6 +10,8 @@ + #include <spl.h> + #include <misc.h> + #include <log.h> ++#include <config.h> ++#include <i2c.h> + #include <linux/delay.h> + #include <linux/io.h> + #include <asm/gpio.h> +@@ -26,6 +28,24 @@ + #define MODE_SELECT_SD 0xb + #define MODE_SELECT_MASK GENMASK(3, 0) + ++#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19 ++#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55 ++ ++static inline int init_tmp451_remote_therm_limit(void) ++{ ++ struct udevice *dev; ++ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE; ++ int ret; ++ ++ ret = i2c_get_chip_for_busnum(0, 0x4c, 0x1, &dev); ++ ++ if (!ret) ++ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET, ++ &r_therm_limit, ++ sizeof(unsigned char)); ++ return ret; ++} ++ + static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width) + { + int ret; +@@ -92,6 +112,12 @@ int spl_board_init_f(void) + + pwm_device_init(); + ++ ret = init_tmp451_remote_therm_limit(); ++ if (ret) { ++ debug("TMP451 remote THERM limit init failed: %d\n", ret); ++ goto end; ++ } ++ + ret = spl_gemgxl_init(); + if (ret) { + debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); diff --git a/package/boot/uboot-sifiveu/patches/0005-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch b/package/boot/uboot-sifiveu/patches/0005-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch deleted file mode 100644 index dc0d04151f..0000000000 --- a/package/boot/uboot-sifiveu/patches/0005-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 07f84ed283b913cbdf87181ae2ed65467d923df5 Mon Sep 17 00:00:00 2001 -From: Vincent Chen <vincent.chen@sifive.com> -Date: Mon, 24 Jan 2022 02:57:40 -0800 -Subject: [PATCH 2/2] board: sifive: spl: Set remote thermal of TMP451 to 85 - deg C for the unmatched board - -For TMP451 on the unmatched board, the default value of the remote -thermal threshold is 108 deg C. This commit initilizes it to 85 deg C at SPL. ---- - board/sifive/unmatched/spl.c | 29 +++++++++++++++++++++++++++++ - drivers/misc/Kconfig | 10 ++++++++++ - include/configs/sifive-unmatched.h | 4 ++++ - scripts/config_whitelist.txt | 1 + - 4 files changed, 44 insertions(+) - ---- a/board/sifive/unmatched/spl.c -+++ b/board/sifive/unmatched/spl.c -@@ -10,6 +10,8 @@ - #include <spl.h> - #include <misc.h> - #include <log.h> -+#include <config.h> -+#include <i2c.h> - #include <linux/delay.h> - #include <linux/io.h> - #include <asm/gpio.h> -@@ -26,6 +28,27 @@ - #define MODE_SELECT_SD 0xb - #define MODE_SELECT_MASK GENMASK(3, 0) - -+#define TMP451_REMOTE_THERM_LIMIT_REG_OFFSET 0x19 -+#define TMP451_REMOTE_THERM_LIMIT_INIT_VALUE 0x55 -+ -+static inline int init_tmp451_remote_therm_limit(void) -+{ -+ struct udevice *dev; -+ unsigned char r_therm_limit = TMP451_REMOTE_THERM_LIMIT_INIT_VALUE; -+ int ret; -+ -+ ret = i2c_get_chip_for_busnum(CONFIG_SYS_TMP451_BUS_NUM, -+ CONFIG_SYS_I2C_TMP451_ADDR, -+ CONFIG_SYS_I2C_TMP451_ADDR_LEN, -+ &dev); -+ -+ if (!ret) -+ ret = dm_i2c_write(dev, TMP451_REMOTE_THERM_LIMIT_REG_OFFSET, -+ &r_therm_limit, -+ sizeof(unsigned char)); -+ return ret; -+} -+ - static inline int spl_reset_device_by_gpio(const char *label, int pin, int low_width) - { - int ret; -@@ -92,6 +115,12 @@ int spl_board_init_f(void) - - pwm_device_init(); - -+ ret = init_tmp451_remote_therm_limit(); -+ if (ret) { -+ debug("TMP451 remote THERM limit init failed: %d\n", ret); -+ goto end; -+ } -+ - ret = spl_gemgxl_init(); - if (ret) { - debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret); ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -536,8 +536,18 @@ config SYS_I2C_EEPROM_ADDR - depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM - default 0 - -+config SYS_I2C_TMP451_ADDR -+ hex "Chip address of the TMP451 device" -+ default 0 -+ - if I2C_EEPROM - -+config SYS_I2C_TMP451_ADDR_LEN -+ int "Length in bytes of the TMP451 memory array address" -+ default 1 -+ help -+ Note: This is NOT the chip address length! -+ - config SYS_I2C_EEPROM_ADDR_OVERFLOW - hex "EEPROM Address Overflow" - default 0x0 ---- a/include/configs/sifive-unmatched.h -+++ b/include/configs/sifive-unmatched.h -@@ -15,6 +15,10 @@ - - #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - -+#define CONFIG_SYS_TMP451_BUS_NUM 0 -+#define CONFIG_SYS_I2C_TMP451_ADDR 0x4c -+#define CONFIG_SYS_I2C_TMP451_ADDR_LEN 0x1 -+ - /* Environment options */ - - #define BOOT_TARGET_DEVICES(func) \ ---- a/scripts/config_whitelist.txt -+++ b/scripts/config_whitelist.txt -@@ -1268,6 +1268,7 @@ CONFIG_SYS_TIMER_BASE - CONFIG_SYS_TIMER_COUNTER - CONFIG_SYS_TIMER_COUNTS_DOWN - CONFIG_SYS_TIMER_RATE -+CONFIG_SYS_TMP451_BUS_NUM - CONFIG_SYS_TMPVIRT - CONFIG_SYS_TSEC1_OFFSET - CONFIG_SYS_TX_ETH_BUFFER diff --git a/package/boot/uboot-sifiveu/patches/0008-riscv-dts-Add-few-PMU-events.patch b/package/boot/uboot-sifiveu/patches/0005-riscv-dts-Add-few-PMU-events.patch index 3f3feb9da7..225c845d3c 100644 --- a/package/boot/uboot-sifiveu/patches/0008-riscv-dts-Add-few-PMU-events.patch +++ b/package/boot/uboot-sifiveu/patches/0005-riscv-dts-Add-few-PMU-events.patch @@ -1,7 +1,7 @@ -From c29e4d84cfa17ab96eff2a9044f486ba3c8b5c43 Mon Sep 17 00:00:00 2001 +From 9b2868e9fda750c985313a40e60b67f96dc77ed1 Mon Sep 17 00:00:00 2001 From: Atish Patra <atish.patra@wdc.com> Date: Mon, 25 Oct 2021 11:35:41 -0700 -Subject: [PATCH] riscv: dts: Add few PMU events +Subject: [PATCH 5/5] riscv: dts: Add few PMU events fu740 has 2 HPM counters and many HPM events defined in the fu740 manual[1]. This patch adds some of these events and their mapping as per the @@ -9,6 +9,7 @@ OpenSBI PMU DT binding for now. [1]https://sifive.cdn.prismic.io/sifive/de1491e5-077c-461d-9605-e8a0ce57337d_fu740-c000-manual-v1p3.pdf +Upstream-Status: Pending Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/dts/fu740-c000.dtsi | 11 +++++++++++ diff --git a/package/boot/uboot-sifiveu/patches/0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch b/package/boot/uboot-sifiveu/patches/0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch new file mode 100644 index 0000000000..380342d4a8 --- /dev/null +++ b/package/boot/uboot-sifiveu/patches/0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch @@ -0,0 +1,22 @@ +From 45f9941ddc6346b38aa9eb7f033e1e169b63bdc7 Mon Sep 17 00:00:00 2001 +From: Thomas Perrot <thomas.perrot@bootlin.com> +Date: Fri, 8 Dec 2023 11:24:37 +0100 +Subject: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to + 1600MT/s + +Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> +--- + arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi ++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi +@@ -77,7 +77,7 @@ + 0x0 0x100b2000 0x0 0x2000 + 0x0 0x100b8000 0x0 0x1000>; + clocks = <&prci FU740_PRCI_CLK_DDRPLL>; +- clock-frequency = <933333324>; ++ clock-frequency = <800000004>; + bootph-pre-ram; + }; + }; diff --git a/package/boot/uboot-sifiveu/patches/0009-riscv-Fix-build-against-binutils.patch b/package/boot/uboot-sifiveu/patches/0009-riscv-Fix-build-against-binutils.patch deleted file mode 100644 index f7c6a62291..0000000000 --- a/package/boot/uboot-sifiveu/patches/0009-riscv-Fix-build-against-binutils.patch +++ /dev/null @@ -1,48 +0,0 @@ -commit 1dde977518f13824b847e23275001191139bc384 -Author: Alexandre Ghiti <alexandre.ghiti@canonical.com> -Date: Mon Oct 3 18:07:54 2022 +0200 - - riscv: Fix build against binutils 2.38 - - The following description is copied from the equivalent patch for the - Linux Kernel proposed by Aurelien Jarno: - - >From version 2.38, binutils default to ISA spec version 20191213. This - means that the csr read/write (csrr*/csrw*) instructions and fence.i - instruction has separated from the `I` extension, become two standalone - extensions: Zicsr and Zifencei. As the kernel uses those instruction, - this causes the following build failure: - - arch/riscv/cpu/mtrap.S: Assembler messages: - arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' - arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' - arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' - arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' - - Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> - Reviewed-by: Bin Meng <bmeng.cn@gmail.com> - Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> - Tested-by: Heiko Stuebner <heiko@sntech.de> - Tested-by: Christian Stewart <christian@paral.in> - Reviewed-by: Rick Chen <rick@andestech.com> - ---- a/arch/riscv/Makefile -+++ b/arch/riscv/Makefile -@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) - CMODEL = medany - endif - --ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ -+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) -+ -+# Newer binutils versions default to ISA spec version 20191213 which moves some -+# instructions from the I extension to the Zicsr and Zifencei extensions. -+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) -+ifeq ($(toolchain-need-zicsr-zifencei),y) -+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei -+endif -+ -+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ - -mcmodel=$(CMODEL) - - PLATFORM_CPPFLAGS += $(ARCH_FLAGS) diff --git a/package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch b/package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch index 789172f21b..fcc30ce35c 100644 --- a/package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch +++ b/package/boot/uboot-sifiveu/patches/100-mkimage-check-environment-for-dtc-binary-location.patch @@ -17,7 +17,7 @@ Cc: Simon Glass <sjg@chromium.org> --- a/tools/fit_image.c +++ b/tools/fit_image.c -@@ -729,9 +729,14 @@ static int fit_handle_file(struct image_ +@@ -754,9 +754,14 @@ static int fit_handle_file(struct image_ } *cmd = '\0'; } else if (params->datafile) { diff --git a/package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch b/package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch index 65d14f5bec..f83814b9b2 100644 --- a/package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch +++ b/package/boot/uboot-sifiveu/patches/110-no-kwbimage.patch @@ -1,10 +1,10 @@ --- a/tools/Makefile +++ b/tools/Makefile -@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \ +@@ -114,7 +114,6 @@ dumpimage-mkimage-objs := aisimage.o \ imximage.o \ imx8image.o \ imx8mimage.o \ - kwbimage.o \ - lib/md5.o \ + generated/lib/md5.o \ lpc32xximage.o \ mxsimage.o \ diff --git a/package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch index 8b110a880f..cd65c1321f 100644 --- a/package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch +++ b/package/boot/uboot-sifiveu/patches/130-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1122,6 +1122,7 @@ static int fit_config_add_verification_d +@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1175,6 +1176,13 @@ err_cert: +@@ -1178,6 +1179,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-stm32/Makefile b/package/boot/uboot-stm32/Makefile new file mode 100644 index 0000000000..6234827a28 --- /dev/null +++ b/package/boot/uboot-stm32/Makefile @@ -0,0 +1,54 @@ +# +# Copyright (C) 2024 Bootlin +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_VERSION:=2024.10 +PKG_RELEASE:=1 + +PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0 +PKG_MAINTAINER:=Thomas Richard <thomas.richard@bootlin.com> + +UBOOT_USE_INTREE_DTC:=1 + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk + +define U-Boot/Default + BUILD_TARGET:=stm32 + UBOOT_IMAGE:=u-boot.bin u-boot.dtb +endef + +define U-Boot/stm32mp13 + BUILD_SUBTARGET:=stm32mp1 + UBOOT_CONFIG:=stm32mp13 +endef + +define U-Boot/stm32mp135f-dk + $(call U-Boot/stm32mp13) + NAME:=STM32MP135F-DK + DEVICE_TREE:=stm32mp135f-dk +endef + +UBOOT_TARGETS := stm32mp135f-dk + +UBOOT_MAKE_FLAGS += DEVICE_TREE=$(DEVICE_TREE) + +UBOOT_CUSTOMIZE_CONFIG := \ + --disable TOOLS_MKEFICAPSULE + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(foreach img,$(UBOOT_IMAGE), \ + $(CP) $(PKG_BUILD_DIR)/$(img) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(img); \ + ) +endef + +define Package/u-boot/install/default +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index c6f98a0db4..5531de2794 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -9,9 +9,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.01 - -PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3 +PKG_VERSION:=2025.01 +PKG_HASH:=cdef7d507c93f1bbd9f015ea9bc21fa074268481405501945abc6f854d5b686f PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu> @@ -114,6 +113,7 @@ endef define U-Boot/Hummingbird_A31 BUILD_SUBTARGET:=cortexa7 NAME:=Hummingbird A31 board + BUILD_DEVICES:=merrii_hummingbird endef define U-Boot/Marsboard_A10 @@ -428,6 +428,11 @@ UBOOT_TARGETS := \ UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes +UBOOT_CUSTOMIZE_CONFIG := \ + --disable TOOLS_KWBIMAGE \ + --disable TOOLS_LIBCRYPTO \ + --disable TOOLS_MKEFICAPSULE + UBOOT_MAKE_FLAGS += \ BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin SCP=/dev/null diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index 8605436b1a..cef2835e45 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -14,7 +14,7 @@ More specifically, the following settings are now used: --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -131,11 +131,12 @@ void clock_set_pll1(unsigned int clk) +@@ -128,11 +128,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; diff --git a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch index b5fa2a1415..64a3f25798 100644 --- a/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch +++ b/package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch @@ -18,7 +18,7 @@ required setting for the PLL LDO is 1.37v as per the A31 manual. --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c -@@ -28,13 +28,26 @@ void clock_init_safe(void) +@@ -27,13 +27,26 @@ void clock_init_safe(void) struct sunxi_prcm_reg * const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; |