diff options
Diffstat (limited to 'target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch')
| -rw-r--r-- | target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch b/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch new file mode 100644 index 0000000000..dfb7e483a7 --- /dev/null +++ b/target/linux/ath79/patches-6.6/317-MIPS-pci-ar724x-clear-power-down-of-pll-on-AR934x.patch @@ -0,0 +1,34 @@ +From f2ca10b22ace3ce53b4e3f189bf1dd53a4482475 Mon Sep 17 00:00:00 2001 +From: INAGAKI Hiroshi <musashino.open@gmail.com> +Date: Fri, 26 Apr 2024 23:53:58 +0900 +Subject: [PATCH 1/2] MIPS: pci-ar724x: clear power down of pll on AR934x + +Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to +PPL_RESET bit of AR724x. + +Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> +--- + +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -347,6 +347,8 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) ++ + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 +--- a/arch/mips/pci/pci-ar724x.c ++++ b/arch/mips/pci/pci-ar724x.c +@@ -360,7 +360,8 @@ static void ar724x_pci_hw_init(struct ar + } else { + /* remove the reset of the PCIE PLL */ + ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); +- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; ++ ppl &= ~(AR934X_PLL_PCIE_CONFIG_PLL_PWD | ++ AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET); + ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); + + /* deassert bypass for the PCIE PLL */ |