1 files changed, 0 insertions, 50 deletions
diff --git a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
deleted file mode 100644
index ca37fc793a..0000000000
--- a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:50:07 +0000
-Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
-
-Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
-of the previously hardcoded PCW_CHG_MASK macro if set.
-This will needed for clocks on the MT7988 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-pll.c | 5 +++--
- drivers/clk/mediatek/clk-pll.h | 1 +
- 2 files changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -23,7 +23,7 @@
- #define CON0_BASE_EN		BIT(0)
- #define CON0_PWR_ON		BIT(0)
- #define CON0_ISO_EN		BIT(1)
--#define PCW_CHG_MASK		BIT(31)
-+#define PCW_CHG_BIT		31
- 
- #define AUDPLL_TUNER_EN		BIT(31)
- 
-@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	chg = readl(pll->pcw_chg_addr) |
-+	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
---- a/drivers/clk/mediatek/clk-pll.h
-+++ b/drivers/clk/mediatek/clk-pll.h
-@@ -46,6 +46,7 @@ struct mtk_pll_data {
- 	const char *parent_name;
- 	u32 en_reg;
- 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
-+	u8 pcw_chg_bit;
- };
- 
- int mtk_clk_register_plls(struct device_node *node,