2158 files changed, 81313 insertions, 177085 deletions

diff --git a/target/Config.in b/target/Config.in
index ac0f1f9826..c2395923d4 100644
--- a/target/Config.in
+++ b/target/Config.in
@@ -156,6 +156,10 @@ config i386
 config i686
 	bool 
 
+config loongarch64
+	select ARCH_64BIT
+	bool
+
 config m68k
 	bool
 
@@ -220,6 +224,7 @@ config ARCH
 	default "armeb"     if armeb
 	default "i386"      if i386
 	default "i686"      if i686
+	default "loongarch64" if loongarch64
 	default "m68k"      if m68k
 	default "mips"      if mips
 	default "mipsel"    if mipsel
diff --git a/target/imagebuilder/Makefile b/target/imagebuilder/Makefile
index bfc72dacd0..7fd2aa0920 100644
--- a/target/imagebuilder/Makefile
+++ b/target/imagebuilder/Makefile
@@ -22,6 +22,8 @@ IB_IDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(STAGING_DIR_IMAGE))
 BUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))
 BUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(PKG_BUILD_DIR)/staging_dir/host
 
+PACKAGE_SUFFIX:=$(if $(CONFIG_USE_APK),apk,ipk)
+
 all: compile
 
 $(BIN_DIR)/$(IB_NAME).tar.zst: clean
@@ -35,41 +37,52 @@ $(BIN_DIR)/$(IB_NAME).tar.zst: clean
 		$(INCLUDE_DIR) $(SCRIPT_DIR) \
 		$(TOPDIR)/rules.mk \
 		./files/Makefile \
-		./files/repositories.conf \
 		$(TMP_DIR)/.targetinfo \
 		$(TMP_DIR)/.packageinfo \
 		$(PKG_BUILD_DIR)/
 
-ifeq ($(CONFIG_IB_STANDALONE),)
+	$(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
+
+ifneq ($(CONFIG_USE_APK),)
+  ifeq ($(CONFIG_IB_STANDALONE),)
+	$(call FeedSourcesAppendAPK,$(PKG_BUILD_DIR)/repositories)
+	$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories
+  endif
+
+	$(INSTALL_DATA) ./files/README.apk.md $(PKG_BUILD_DIR)/packages/README.md
+else
+  ifeq ($(CONFIG_IB_STANDALONE),)
 	echo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf
-	$(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf)
+	$(call FeedSourcesAppendOPKG,$(PKG_BUILD_DIR)/repositories.conf)
 	$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf
-endif
 
-	$(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
+  endif
+
 	# create an empty package index so `opkg` doesn't report an error
 	touch $(PKG_BUILD_DIR)/packages/Packages
-	$(INSTALL_DATA) ./files/README.md $(PKG_BUILD_DIR)/packages/
+	$(INSTALL_DATA) ./files/README.opkg.md $(PKG_BUILD_DIR)/packages/README.md
 
 	echo ''                                                        >> $(PKG_BUILD_DIR)/repositories.conf
 	echo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf
 	echo 'src imagebuilder file:packages'                          >> $(PKG_BUILD_DIR)/repositories.conf
+endif
 
 ifeq ($(CONFIG_BUILDBOT),)
   ifeq ($(CONFIG_IB_STANDALONE),)
 	$(FIND) $(call FeedPackageDir,libc) -type f \
-		\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk' \) \
+		\( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' -or -name 'kmod-*.$(PACKAGE_SUFFIX)' \) \
 		-exec $(CP) -t $(PKG_BUILD_DIR)/packages {} +
   else
-	$(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' \
+	$(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.$(PACKAGE_SUFFIX)' \
 		-exec $(CP) -t $(PKG_BUILD_DIR)/packages/ {} +
   endif
 else
 	$(FIND) $(call FeedPackageDir,libc) -type f \
-		\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' \) \
+		\( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' \) \
 		-exec $(CP) -t $(IB_LDIR)/ {} +
 endif
 
+ifneq ($(CONFIG_USE_APK),y)
 ifneq ($(CONFIG_SIGNATURE_CHECK),)
 	echo ''                                                        >> $(PKG_BUILD_DIR)/repositories.conf
 	echo 'option check_signature'                                  >> $(PKG_BUILD_DIR)/repositories.conf
@@ -77,6 +90,7 @@ ifneq ($(CONFIG_SIGNATURE_CHECK),)
 	$(CP) -L $(STAGING_DIR_ROOT)/etc/opkg/keys/ $(PKG_BUILD_DIR)/
 	$(CP) -L $(STAGING_DIR_ROOT)/usr/sbin/opkg-key $(PKG_BUILD_DIR)/scripts/
 endif
+endif
 
 	$(CP) -L $(TOPDIR)/target/linux/Makefile $(PKG_BUILD_DIR)/target/linux
 	$(CP) -L $(TOPDIR)/target/linux/generic $(PKG_BUILD_DIR)/target/linux
diff --git a/target/imagebuilder/files/Makefile b/target/imagebuilder/files/Makefile
index 78a75e96a8..7d01bc0e42 100644
--- a/target/imagebuilder/files/Makefile
+++ b/target/imagebuilder/files/Makefile
@@ -85,6 +85,8 @@ help: FORCE
 # override variables from rules.mk
 PACKAGE_DIR:=$(TOPDIR)/packages
 LISTS_DIR:=$(subst $(space),/,$(patsubst %,..,$(subst /,$(space),$(TARGET_DIR))))$(DL_DIR)
+PACKAGE_DIR_ALL:=$(TOPDIR)/packages
+
 export OPKG_KEYS:=$(TOPDIR)/keys
 OPKG:=$(call opkg,$(TARGET_DIR)) \
 	-f $(TOPDIR)/repositories.conf \
@@ -92,6 +94,11 @@ OPKG:=$(call opkg,$(TARGET_DIR)) \
 	--cache $(DL_DIR) \
 	--lists-dir $(LISTS_DIR)
 
+APK:=$(call apk,$(TARGET_DIR)) \
+	--cache-dir $(DL_DIR) \
+	--allow-untrusted
+
+
 include $(INCLUDE_DIR)/target.mk
 -include .profiles.mk
 
@@ -152,20 +159,29 @@ _call_manifest: FORCE
 	mkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR)
 	$(MAKE) package_reload >/dev/null
 	$(MAKE) package_install >/dev/null
+ifeq ($(CONFIG_USE_APK),)
 	$(OPKG) list-installed $(if $(STRIP_ABI),--strip-abi)
+else
+	$(APK) list --quiet --manifest --no-network
+endif
 
 package_index: FORCE
 	@echo >&2
 	@echo Building package index... >&2
 	@mkdir -p $(TMP_DIR) $(TARGET_DIR)/tmp
+ifeq ($(CONFIG_USE_APK),)
 	(cd $(PACKAGE_DIR); $(SCRIPT_DIR)/ipkg-make-index.sh . > Packages && \
 		gzip -9nc Packages > Packages.gz; \
 		$(if $(CONFIG_SIGNATURE_CHECK), \
 			$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY)) \
 	) >/dev/null 2>/dev/null
 	$(OPKG) update >&2 || true
+else
+	(cd $(PACKAGE_DIR); $(APK) mkndx --output packages.adb *.apk) >&2
+endif
 
 package_reload:
+ifeq ($(CONFIG_USE_APK),)
 	if [ -d "$(PACKAGE_DIR)" ] && ( \
 			[ ! -f "$(PACKAGE_DIR)/Packages" ] || \
 			[ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || \
@@ -176,29 +192,52 @@ package_reload:
 		mkdir -p $(TARGET_DIR)/tmp; \
 		$(OPKG) update >&2 || true; \
 	fi
+else
+	if [ -d "$(PACKAGE_DIR)" ] && ( \
+			[ ! -f "$(PACKAGE_DIR)/packages.adb" ] || \
+			[ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/packages.adb`" ] ); then \
+		echo "Package list missing or not up-to-date, generating it." >&2 ;\
+		$(MAKE) package_index; \
+	else \
+		mkdir -p $(TARGET_DIR)/tmp; \
+		$(APK) update >&2 || true; \
+	fi
+endif
 
 package_list: FORCE
 	@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
 	@$(OPKG) list --size 2>/dev/null
+else
+	@$(APK) list --size 2>/dev/null
+endif
 
 package_install: FORCE
 	@echo
 	@echo Installing packages...
+ifeq ($(CONFIG_USE_APK),)
 	$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/libc_*.ipk $(PACKAGE_DIR)/libc_*.ipk))
 	$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/kernel_*.ipk $(PACKAGE_DIR)/kernel_*.ipk))
 	$(OPKG) install $(BUILD_PACKAGES)
+else
+	$(APK) add --initdb --no-scripts $(firstword $(wildcard $(LINUX_DIR)/libc-*.apk $(PACKAGE_DIR)/libc_*.apk))
+	$(APK) add --no-scripts $(firstword $(wildcard $(LINUX_DIR)/kernel-*.apk $(PACKAGE_DIR)/kernel_*.apk))
+	$(APK) add --no-scripts $(BUILD_PACKAGES)
+endif
 
 prepare_rootfs: FORCE
 	@echo
 	@echo Finalizing root filesystem...
 
 	$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
+ifeq ($(CONFIG_USE_APK),)
 	$(if $(CONFIG_SIGNATURE_CHECK), \
 		$(if $(ADD_LOCAL_KEY), \
 			OPKG_KEYS=$(TARGET_DIR)/etc/opkg/keys/ \
 			$(SCRIPT_DIR)/opkg-key add $(BUILD_KEY).pub \
 		) \
 	)
+endif
 	$(call prepare_rootfs,$(TARGET_DIR),$(USER_FILES),$(DISABLED_SERVICES))
 
 build_image: FORCE
@@ -245,6 +284,7 @@ ifneq ($(PROFILE),)
 endif
 
 _check_keys: FORCE
+ifeq ($(CONFIG_USE_APK),)
 ifneq ($(CONFIG_SIGNATURE_CHECK),)
 	@if [ ! -s $(BUILD_KEY) -o ! -s $(BUILD_KEY).pub ]; then \
 		echo Generate local signing keys... >&2; \
@@ -260,6 +300,9 @@ ifneq ($(CONFIG_SIGNATURE_CHECK),)
 			-s $(BUILD_KEY); \
 	fi
 endif
+else
+	# TODO
+endif
 
 image:
 	$(MAKE) -s _check_profile
@@ -287,7 +330,11 @@ ifeq ($(PACKAGE),)
 	@exit 1
 endif
 	@$(MAKE) -s package_reload
-	@$(OPKG) whatdepends -A $(PACKAGE)
+ifeq ($(CONFIG_USE_APK),)
+	@$(OPKG) list --depends $(PACKAGE)
+else
+	@$(APK) list --depends $(PACKAGE)
+endif
 
 package_depends: FORCE
 ifeq ($(PACKAGE),)
@@ -295,7 +342,10 @@ ifeq ($(PACKAGE),)
 	@exit 1
 endif
 	@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
 	@$(OPKG) depends -A $(PACKAGE)
-
+else
+	@$(OPKG) whatdepends -A $(PACKAGE)
+endif
 
 .SILENT: help info image manifest package_whatdepends package_depends
diff --git a/target/imagebuilder/files/README.apk.md b/target/imagebuilder/files/README.apk.md
new file mode 100644
index 0000000000..e82a937e37
--- /dev/null
+++ b/target/imagebuilder/files/README.apk.md
@@ -0,0 +1,10 @@
+# ./packages folder
+
+Add `.apk` packages to this folder will allow the ImageBuilder to install them.
+
+For more complex setups consider adding a custom feed containing packages.
+
+    file:///path/to/Packages.adb
+
+Whenever the ImageBuilder builds a firmware image this folder will be reloaded
+and a new package index created.
diff --git a/target/imagebuilder/files/README.md b/target/imagebuilder/files/README.opkg.md
index 9a9616d06d..9a9616d06d 100644
--- a/target/imagebuilder/files/README.md
+++ b/target/imagebuilder/files/README.opkg.md
diff --git a/target/linux/airoha/Makefile b/target/linux/airoha/Makefile
index 0a66ef839c..99ce7443ec 100644
--- a/target/linux/airoha/Makefile
+++ b/target/linux/airoha/Makefile
@@ -6,7 +6,7 @@ BOARDNAME:=Airoha ARM
 CPU_TYPE:=cortex-a7
 FEATURES:=dt squashfs nand ramdisk gpio source-only
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/airoha/config-6.1 b/target/linux/airoha/config-6.1
deleted file mode 100644
index e609c29db2..0000000000
--- a/target/linux/airoha/config-6.1
+++ /dev/null
@@ -1,294 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AIROHA=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_EN7523=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_EN7523=y
-CONFIG_GPIO_GENERIC=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PINCTRL=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-# CONFIG_SERIAL_8250_SHARE_IRQ is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_AIROHA_EN7523=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/airoha/config-6.6 b/target/linux/airoha/config-6.6
new file mode 100644
index 0000000000..ce93f7d9ff
--- /dev/null
+++ b/target/linux/airoha/config-6.6
@@ -0,0 +1,303 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_EN7523=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_EN7523=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PINCTRL=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_AIROHA_EN7523=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_STACKTRACE=y
+# CONFIG_SWAP is not set
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
deleted file mode 100644
index dc28bd1df9..0000000000
--- a/target/linux/airoha/patches-6.1/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
+++ /dev/null
@@ -1,341 +0,0 @@
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -330,6 +330,12 @@ config SPI_DLN2
- 	 This driver can also be built as a module.  If so, the module
- 	 will be called spi-dln2.
- 
-+config SPI_AIROHA_EN7523
-+	bool "Airoha EN7523 SPI controller support"
-+	depends on ARCH_AIROHA
-+	help
-+	  This enables SPI controller support for the Airoha EN7523 SoC.
-+
- config SPI_EP93XX
- 	tristate "Cirrus Logic EP93xx SPI controller"
- 	depends on ARCH_EP93XX || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_DW_BT1)		+= spi-dw-bt1.
- obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
- obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-pci.o
- obj-$(CONFIG_SPI_EP93XX)		+= spi-ep93xx.o
-+obj-$(CONFIG_SPI_AIROHA_EN7523)		+= spi-en7523.o
- obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
- obj-$(CONFIG_SPI_FSI)			+= spi-fsi.o
- obj-$(CONFIG_SPI_FSL_CPM)		+= spi-fsl-cpm.o
---- /dev/null
-+++ b/drivers/spi/spi-en7523.c
-@@ -0,0 +1,313 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/spi/spi.h>
-+
-+
-+#define ENSPI_READ_IDLE_EN			0x0004
-+#define ENSPI_MTX_MODE_TOG			0x0014
-+#define ENSPI_RDCTL_FSM				0x0018
-+#define ENSPI_MANUAL_EN				0x0020
-+#define ENSPI_MANUAL_OPFIFO_EMPTY		0x0024
-+#define ENSPI_MANUAL_OPFIFO_WDATA		0x0028
-+#define ENSPI_MANUAL_OPFIFO_FULL		0x002C
-+#define ENSPI_MANUAL_OPFIFO_WR			0x0030
-+#define ENSPI_MANUAL_DFIFO_FULL			0x0034
-+#define ENSPI_MANUAL_DFIFO_WDATA		0x0038
-+#define ENSPI_MANUAL_DFIFO_EMPTY		0x003C
-+#define ENSPI_MANUAL_DFIFO_RD			0x0040
-+#define ENSPI_MANUAL_DFIFO_RDATA		0x0044
-+#define ENSPI_IER				0x0090
-+#define ENSPI_NFI2SPI_EN			0x0130
-+
-+// TODO not in spi block
-+#define ENSPI_CLOCK_DIVIDER			((void __iomem *)0x1fa201c4)
-+
-+#define	OP_CSH					0x00
-+#define	OP_CSL					0x01
-+#define	OP_CK					0x02
-+#define	OP_OUTS					0x08
-+#define	OP_OUTD					0x09
-+#define	OP_OUTQ					0x0A
-+#define	OP_INS					0x0C
-+#define	OP_INS0					0x0D
-+#define	OP_IND					0x0E
-+#define	OP_INQ					0x0F
-+#define	OP_OS2IS				0x10
-+#define	OP_OS2ID				0x11
-+#define	OP_OS2IQ				0x12
-+#define	OP_OD2IS				0x13
-+#define	OP_OD2ID				0x14
-+#define	OP_OD2IQ				0x15
-+#define	OP_OQ2IS				0x16
-+#define	OP_OQ2ID				0x17
-+#define	OP_OQ2IQ				0x18
-+#define	OP_OSNIS				0x19
-+#define	OP_ODNID				0x1A
-+
-+#define MATRIX_MODE_AUTO		1
-+#define   CONF_MTX_MODE_AUTO		0
-+#define   MANUALEN_AUTO			0
-+#define MATRIX_MODE_MANUAL		0
-+#define   CONF_MTX_MODE_MANUAL		9
-+#define   MANUALEN_MANUAL		1
-+
-+#define _ENSPI_MAX_XFER			0x1ff
-+
-+#define REG(x)			(iobase + x)
-+
-+
-+static void __iomem *iobase;
-+
-+
-+static void opfifo_write(u32 cmd, u32 len)
-+{
-+	u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
-+
-+	writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
-+
-+	/* Wait for room in OPFIFO */
-+	while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
-+		;
-+
-+	/* Shift command into OPFIFO */
-+	writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
-+
-+	/* Wait for command to finish */
-+	while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
-+		;
-+}
-+
-+static void set_cs(int state)
-+{
-+	if (state)
-+		opfifo_write(OP_CSH, 1);
-+	else
-+		opfifo_write(OP_CSL, 1);
-+}
-+
-+static void manual_begin_cmd(void)
-+{
-+	/* Disable read idle state */
-+	writel(0, REG(ENSPI_READ_IDLE_EN));
-+
-+	/* Wait for FSM to reach idle state */
-+	while (readl(REG(ENSPI_RDCTL_FSM)))
-+		;
-+
-+	/* Set SPI core to manual mode */
-+	writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
-+	writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
-+}
-+
-+static void manual_end_cmd(void)
-+{
-+	/* Set SPI core to auto mode */
-+	writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
-+	writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
-+
-+	/* Enable read idle state */
-+	writel(1, REG(ENSPI_READ_IDLE_EN));
-+}
-+
-+static void dfifo_read(u8 *buf, int len)
-+{
-+	int i;
-+
-+	for (i = 0; i < len; i++) {
-+		/* Wait for requested data to show up in DFIFO */
-+		while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
-+			;
-+		buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
-+		/* Queue up next byte */
-+		writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
-+	}
-+}
-+
-+static void dfifo_write(const u8 *buf, int len)
-+{
-+	int i;
-+
-+	for (i = 0; i < len; i++) {
-+		/* Wait for room in DFIFO */
-+		while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
-+			;
-+		writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
-+	}
-+}
-+
-+#if 0
-+static void set_spi_clock_speed(int freq_mhz)
-+{
-+	u32 tmp, val;
-+
-+	tmp = readl(ENSPI_CLOCK_DIVIDER);
-+	tmp &= 0xffff0000;
-+	writel(tmp, ENSPI_CLOCK_DIVIDER);
-+
-+	val = (400 / (freq_mhz * 2));
-+	tmp |= (val << 8) | 1;
-+	writel(tmp, ENSPI_CLOCK_DIVIDER);
-+}
-+#endif
-+
-+static void init_hw(void)
-+{
-+	/* Disable manual/auto mode clash interrupt */
-+	writel(0, REG(ENSPI_IER));
-+
-+	// TODO via clk framework
-+	// set_spi_clock_speed(50);
-+
-+	/* Disable DMA */
-+	writel(0, REG(ENSPI_NFI2SPI_EN));
-+}
-+
-+static int xfer_read(struct spi_transfer *xfer)
-+{
-+	int opcode;
-+	uint8_t *buf = xfer->rx_buf;
-+
-+	switch (xfer->rx_nbits) {
-+	case SPI_NBITS_SINGLE:
-+		opcode = OP_INS;
-+		break;
-+	case SPI_NBITS_DUAL:
-+		opcode = OP_IND;
-+		break;
-+	case SPI_NBITS_QUAD:
-+		opcode = OP_INQ;
-+		break;
-+	}
-+
-+	opfifo_write(opcode, xfer->len);
-+	dfifo_read(buf, xfer->len);
-+
-+	return xfer->len;
-+}
-+
-+static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
-+{
-+	int opcode;
-+	const uint8_t *buf = xfer->tx_buf;
-+
-+	if (next_xfer_is_rx) {
-+		/* need to use Ox2Ix opcode to set the core to input afterwards */
-+		switch (xfer->tx_nbits) {
-+		case SPI_NBITS_SINGLE:
-+			opcode = OP_OS2IS;
-+			break;
-+		case SPI_NBITS_DUAL:
-+			opcode = OP_OS2ID;
-+			break;
-+		case SPI_NBITS_QUAD:
-+			opcode = OP_OS2IQ;
-+			break;
-+		}
-+	} else {
-+		switch (xfer->tx_nbits) {
-+		case SPI_NBITS_SINGLE:
-+			opcode = OP_OUTS;
-+			break;
-+		case SPI_NBITS_DUAL:
-+			opcode = OP_OUTD;
-+			break;
-+		case SPI_NBITS_QUAD:
-+			opcode = OP_OUTQ;
-+			break;
-+		}
-+	}
-+
-+	opfifo_write(opcode, xfer->len);
-+	dfifo_write(buf, xfer->len);
-+
-+	return xfer->len;
-+}
-+
-+size_t max_transfer_size(struct spi_device *spi)
-+{
-+	return _ENSPI_MAX_XFER;
-+}
-+
-+int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
-+{
-+	struct spi_transfer *xfer;
-+	int next_xfer_is_rx = 0;
-+
-+	manual_begin_cmd();
-+	set_cs(0);
-+	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+		if (xfer->tx_buf) {
-+			if (!list_is_last(&xfer->transfer_list, &msg->transfers)
-+			    && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
-+				next_xfer_is_rx = 1;
-+			else
-+				next_xfer_is_rx = 0;
-+			msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
-+		} else if (xfer->rx_buf) {
-+			msg->actual_length += xfer_read(xfer);
-+		}
-+	}
-+	set_cs(1);
-+	manual_end_cmd();
-+
-+	msg->status = 0;
-+	spi_finalize_current_message(ctrl);
-+
-+	return 0;
-+}
-+
-+static int spi_probe(struct platform_device *pdev)
-+{
-+	struct spi_controller *ctrl;
-+	int err;
-+
-+	ctrl = devm_spi_alloc_master(&pdev->dev, 0);
-+	if (!ctrl) {
-+		dev_err(&pdev->dev, "Error allocating SPI controller\n");
-+		return -ENOMEM;
-+	}
-+
-+	iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+	if (IS_ERR(iobase)) {
-+		dev_err(&pdev->dev, "Could not map SPI register address");
-+		return -ENOMEM;
-+	}
-+
-+	init_hw();
-+
-+	ctrl->dev.of_node = pdev->dev.of_node;
-+	ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
-+	ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
-+	ctrl->max_transfer_size = max_transfer_size;
-+	ctrl->transfer_one_message = transfer_one_message;
-+	err = devm_spi_register_controller(&pdev->dev, ctrl);
-+	if (err) {
-+		dev_err(&pdev->dev, "Could not register SPI controller\n");
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id spi_of_ids[] = {
-+	{ .compatible = "airoha,en7523-spi" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, spi_of_ids);
-+
-+static struct platform_driver spi_driver = {
-+	.probe = spi_probe,
-+	.driver = {
-+		.name = "airoha-en7523-spi",
-+		.of_match_table = spi_of_ids,
-+	},
-+};
-+
-+module_platform_driver(spi_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
-+MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
diff --git a/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
new file mode 100644
index 0000000000..30ba1ab412
--- /dev/null
+++ b/target/linux/airoha/patches-6.6/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch
@@ -0,0 +1,341 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -353,6 +353,12 @@ config SPI_DLN2
+ 	 This driver can also be built as a module.  If so, the module
+ 	 will be called spi-dln2.
+ 
++config SPI_AIROHA_EN7523
++	bool "Airoha EN7523 SPI controller support"
++	depends on ARCH_AIROHA
++	help
++	  This enables SPI controller support for the Airoha EN7523 SoC.
++
+ config SPI_EP93XX
+ 	tristate "Cirrus Logic EP93xx SPI controller"
+ 	depends on ARCH_EP93XX || COMPILE_TEST
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_DW_BT1)		+= spi-dw-bt1.
+ obj-$(CONFIG_SPI_DW_MMIO)		+= spi-dw-mmio.o
+ obj-$(CONFIG_SPI_DW_PCI)		+= spi-dw-pci.o
+ obj-$(CONFIG_SPI_EP93XX)		+= spi-ep93xx.o
++obj-$(CONFIG_SPI_AIROHA_EN7523)		+= spi-en7523.o
+ obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
+ obj-$(CONFIG_SPI_FSI)			+= spi-fsi.o
+ obj-$(CONFIG_SPI_FSL_CPM)		+= spi-fsl-cpm.o
+--- /dev/null
++++ b/drivers/spi/spi-en7523.c
+@@ -0,0 +1,313 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/mod_devicetable.h>
++#include <linux/spi/spi.h>
++
++
++#define ENSPI_READ_IDLE_EN			0x0004
++#define ENSPI_MTX_MODE_TOG			0x0014
++#define ENSPI_RDCTL_FSM				0x0018
++#define ENSPI_MANUAL_EN				0x0020
++#define ENSPI_MANUAL_OPFIFO_EMPTY		0x0024
++#define ENSPI_MANUAL_OPFIFO_WDATA		0x0028
++#define ENSPI_MANUAL_OPFIFO_FULL		0x002C
++#define ENSPI_MANUAL_OPFIFO_WR			0x0030
++#define ENSPI_MANUAL_DFIFO_FULL			0x0034
++#define ENSPI_MANUAL_DFIFO_WDATA		0x0038
++#define ENSPI_MANUAL_DFIFO_EMPTY		0x003C
++#define ENSPI_MANUAL_DFIFO_RD			0x0040
++#define ENSPI_MANUAL_DFIFO_RDATA		0x0044
++#define ENSPI_IER				0x0090
++#define ENSPI_NFI2SPI_EN			0x0130
++
++// TODO not in spi block
++#define ENSPI_CLOCK_DIVIDER			((void __iomem *)0x1fa201c4)
++
++#define	OP_CSH					0x00
++#define	OP_CSL					0x01
++#define	OP_CK					0x02
++#define	OP_OUTS					0x08
++#define	OP_OUTD					0x09
++#define	OP_OUTQ					0x0A
++#define	OP_INS					0x0C
++#define	OP_INS0					0x0D
++#define	OP_IND					0x0E
++#define	OP_INQ					0x0F
++#define	OP_OS2IS				0x10
++#define	OP_OS2ID				0x11
++#define	OP_OS2IQ				0x12
++#define	OP_OD2IS				0x13
++#define	OP_OD2ID				0x14
++#define	OP_OD2IQ				0x15
++#define	OP_OQ2IS				0x16
++#define	OP_OQ2ID				0x17
++#define	OP_OQ2IQ				0x18
++#define	OP_OSNIS				0x19
++#define	OP_ODNID				0x1A
++
++#define MATRIX_MODE_AUTO		1
++#define   CONF_MTX_MODE_AUTO		0
++#define   MANUALEN_AUTO			0
++#define MATRIX_MODE_MANUAL		0
++#define   CONF_MTX_MODE_MANUAL		9
++#define   MANUALEN_MANUAL		1
++
++#define _ENSPI_MAX_XFER			0x1ff
++
++#define REG(x)			(iobase + x)
++
++
++static void __iomem *iobase;
++
++
++static void opfifo_write(u32 cmd, u32 len)
++{
++	u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
++
++	writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
++
++	/* Wait for room in OPFIFO */
++	while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
++		;
++
++	/* Shift command into OPFIFO */
++	writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
++
++	/* Wait for command to finish */
++	while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
++		;
++}
++
++static void set_cs(int state)
++{
++	if (state)
++		opfifo_write(OP_CSH, 1);
++	else
++		opfifo_write(OP_CSL, 1);
++}
++
++static void manual_begin_cmd(void)
++{
++	/* Disable read idle state */
++	writel(0, REG(ENSPI_READ_IDLE_EN));
++
++	/* Wait for FSM to reach idle state */
++	while (readl(REG(ENSPI_RDCTL_FSM)))
++		;
++
++	/* Set SPI core to manual mode */
++	writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
++	writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
++}
++
++static void manual_end_cmd(void)
++{
++	/* Set SPI core to auto mode */
++	writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
++	writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
++
++	/* Enable read idle state */
++	writel(1, REG(ENSPI_READ_IDLE_EN));
++}
++
++static void dfifo_read(u8 *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		/* Wait for requested data to show up in DFIFO */
++		while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
++			;
++		buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
++		/* Queue up next byte */
++		writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
++	}
++}
++
++static void dfifo_write(const u8 *buf, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i++) {
++		/* Wait for room in DFIFO */
++		while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
++			;
++		writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
++	}
++}
++
++#if 0
++static void set_spi_clock_speed(int freq_mhz)
++{
++	u32 tmp, val;
++
++	tmp = readl(ENSPI_CLOCK_DIVIDER);
++	tmp &= 0xffff0000;
++	writel(tmp, ENSPI_CLOCK_DIVIDER);
++
++	val = (400 / (freq_mhz * 2));
++	tmp |= (val << 8) | 1;
++	writel(tmp, ENSPI_CLOCK_DIVIDER);
++}
++#endif
++
++static void init_hw(void)
++{
++	/* Disable manual/auto mode clash interrupt */
++	writel(0, REG(ENSPI_IER));
++
++	// TODO via clk framework
++	// set_spi_clock_speed(50);
++
++	/* Disable DMA */
++	writel(0, REG(ENSPI_NFI2SPI_EN));
++}
++
++static int xfer_read(struct spi_transfer *xfer)
++{
++	int opcode;
++	uint8_t *buf = xfer->rx_buf;
++
++	switch (xfer->rx_nbits) {
++	case SPI_NBITS_SINGLE:
++		opcode = OP_INS;
++		break;
++	case SPI_NBITS_DUAL:
++		opcode = OP_IND;
++		break;
++	case SPI_NBITS_QUAD:
++		opcode = OP_INQ;
++		break;
++	}
++
++	opfifo_write(opcode, xfer->len);
++	dfifo_read(buf, xfer->len);
++
++	return xfer->len;
++}
++
++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
++{
++	int opcode;
++	const uint8_t *buf = xfer->tx_buf;
++
++	if (next_xfer_is_rx) {
++		/* need to use Ox2Ix opcode to set the core to input afterwards */
++		switch (xfer->tx_nbits) {
++		case SPI_NBITS_SINGLE:
++			opcode = OP_OS2IS;
++			break;
++		case SPI_NBITS_DUAL:
++			opcode = OP_OS2ID;
++			break;
++		case SPI_NBITS_QUAD:
++			opcode = OP_OS2IQ;
++			break;
++		}
++	} else {
++		switch (xfer->tx_nbits) {
++		case SPI_NBITS_SINGLE:
++			opcode = OP_OUTS;
++			break;
++		case SPI_NBITS_DUAL:
++			opcode = OP_OUTD;
++			break;
++		case SPI_NBITS_QUAD:
++			opcode = OP_OUTQ;
++			break;
++		}
++	}
++
++	opfifo_write(opcode, xfer->len);
++	dfifo_write(buf, xfer->len);
++
++	return xfer->len;
++}
++
++size_t max_transfer_size(struct spi_device *spi)
++{
++	return _ENSPI_MAX_XFER;
++}
++
++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
++{
++	struct spi_transfer *xfer;
++	int next_xfer_is_rx = 0;
++
++	manual_begin_cmd();
++	set_cs(0);
++	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++		if (xfer->tx_buf) {
++			if (!list_is_last(&xfer->transfer_list, &msg->transfers)
++			    && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
++				next_xfer_is_rx = 1;
++			else
++				next_xfer_is_rx = 0;
++			msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
++		} else if (xfer->rx_buf) {
++			msg->actual_length += xfer_read(xfer);
++		}
++	}
++	set_cs(1);
++	manual_end_cmd();
++
++	msg->status = 0;
++	spi_finalize_current_message(ctrl);
++
++	return 0;
++}
++
++static int spi_probe(struct platform_device *pdev)
++{
++	struct spi_controller *ctrl;
++	int err;
++
++	ctrl = devm_spi_alloc_master(&pdev->dev, 0);
++	if (!ctrl) {
++		dev_err(&pdev->dev, "Error allocating SPI controller\n");
++		return -ENOMEM;
++	}
++
++	iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
++	if (IS_ERR(iobase)) {
++		dev_err(&pdev->dev, "Could not map SPI register address");
++		return -ENOMEM;
++	}
++
++	init_hw();
++
++	ctrl->dev.of_node = pdev->dev.of_node;
++	ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
++	ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
++	ctrl->max_transfer_size = max_transfer_size;
++	ctrl->transfer_one_message = transfer_one_message;
++	err = devm_spi_register_controller(&pdev->dev, ctrl);
++	if (err) {
++		dev_err(&pdev->dev, "Could not register SPI controller\n");
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static const struct of_device_id spi_of_ids[] = {
++	{ .compatible = "airoha,en7523-spi" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, spi_of_ids);
++
++static struct platform_driver spi_driver = {
++	.probe = spi_probe,
++	.driver = {
++		.name = "airoha-en7523-spi",
++		.of_match_table = spi_of_ids,
++	},
++};
++
++module_platform_driver(spi_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
++MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
diff --git a/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi b/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
index 2921bfedb9..9d98776626 100644
--- a/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
+++ b/target/linux/apm821xx/dts/netgear-wndap6x0.dtsi
@@ -224,7 +224,6 @@
 
 	rtl8367b {
 		compatible = "realtek,rtl8367b";
-		cpu_port = <5>;
 		realtek,extif0 = <1 2 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
 	};
diff --git a/target/linux/armsr/Makefile b/target/linux/armsr/Makefile
index 7de77decb5..02b0eda607 100644
--- a/target/linux/armsr/Makefile
+++ b/target/linux/armsr/Makefile
@@ -9,7 +9,7 @@ BOARDNAME:=Arm SystemReady (EFI) compliant
 FEATURES:=fpu pci pcie rtc usb boot-part rootfs-part
 FEATURES+=cpiogz ext4 ramdisk squashfs targz vmdk
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/armsr/armv7/config-6.1 b/target/linux/armsr/armv7/config-6.1
deleted file mode 100644
index 664ef2e05b..0000000000
--- a/target/linux/armsr/armv7/config-6.1
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_VIRT=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_CACHE_L2X0=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMA_OPS=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HAVE_SMP=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEON=y
-CONFIG_NR_CPUS=4
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
diff --git a/target/linux/armsr/armv7/config-6.6 b/target/linux/armsr/armv7/config-6.6
new file mode 100644
index 0000000000..18f5cd7c79
--- /dev/null
+++ b/target/linux/armsr/armv7/config-6.6
@@ -0,0 +1,83 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_CACHE_L2X0=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMA_OPS=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HAVE_SMP=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_NEON=y
+CONFIG_NR_CPUS=4
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYS_OFFSET=0
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/target/linux/armsr/armv8/config-6.1 b/target/linux/armsr/armv8/config-6.1
deleted file mode 100644
index 0ead973064..0000000000
--- a/target/linux/armsr/armv8/config-6.1
+++ /dev/null
@@ -1,800 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_HMAT=y
-CONFIG_ACPI_PCC=y
-CONFIG_AHCI_IMX=y
-CONFIG_AHCI_MVEBU=y
-CONFIG_AHCI_QORIQ=y
-CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM2835=y
-# CONFIG_ARCH_BCMBCA is not set
-CONFIG_ARCH_BCM_IPROC=y
-CONFIG_ARCH_BRCMSTB=y
-CONFIG_ARCH_HISI=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_LAYERSCAPE=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NXP=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_R8A774A1=y
-CONFIG_ARCH_R8A774B1=y
-CONFIG_ARCH_R8A774C0=y
-CONFIG_ARCH_R8A774E1=y
-# CONFIG_ARCH_R8A77950 is not set
-# CONFIG_ARCH_R8A77951 is not set
-# CONFIG_ARCH_R8A77960 is not set
-# CONFIG_ARCH_R8A77961 is not set
-# CONFIG_ARCH_R8A77965 is not set
-# CONFIG_ARCH_R8A77970 is not set
-# CONFIG_ARCH_R8A77980 is not set
-# CONFIG_ARCH_R8A77990 is not set
-# CONFIG_ARCH_R8A77995 is not set
-# CONFIG_ARCH_R8A779A0 is not set
-# CONFIG_ARCH_R8A779F0 is not set
-# CONFIG_ARCH_R8A779G0 is not set
-CONFIG_ARCH_R9A07G043=y
-CONFIG_ARCH_R9A07G044=y
-CONFIG_ARCH_R9A07G054=y
-CONFIG_ARCH_R9A09G011=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SYNQUACER=y
-CONFIG_ARCH_THUNDER=y
-CONFIG_ARCH_THUNDER2=y
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_AMU_EXTN=y
-CONFIG_ARM64_BTI=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_E0PD=y
-CONFIG_ARM64_EPAN=y
-CONFIG_ARM64_ERRATUM_1024718=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_1319367=y
-CONFIG_ARM64_ERRATUM_1418040=y
-CONFIG_ARM64_ERRATUM_1463225=y
-CONFIG_ARM64_ERRATUM_1508412=y
-CONFIG_ARM64_ERRATUM_1530923=y
-CONFIG_ARM64_ERRATUM_1542419=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2441007=y
-CONFIG_ARM64_ERRATUM_2441009=y
-CONFIG_ARM64_ERRATUM_2457168=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_834220=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_MTE=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_TLB_RANGE=y
-CONFIG_ARM64_VA_BITS=48
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-# CONFIG_ARM_DMC620_PMU is not set
-# CONFIG_ARM_MHU_V2 is not set
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_SBSA_WATCHDOG=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-CONFIG_ARM_SMC_WATCHDOG=y
-CONFIG_ARM_SMMU=y
-# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_PMU is not set
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_ATOMIC64_SELFTEST=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-# CONFIG_AXI_DMAC is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BCM2711_THERMAL is not set
-CONFIG_BCM2835_MBOX=y
-CONFIG_BCM2835_POWER=y
-# CONFIG_BCM2835_THERMAL is not set
-# CONFIG_BCM2835_VCHIQ is not set
-CONFIG_BCM2835_WDT=y
-# CONFIG_BCMGENET is not set
-# CONFIG_BCM_CYGNUS_PHY is not set
-# CONFIG_BCM_FLEXRM_MBOX is not set
-# CONFIG_BCM_NS_THERMAL is not set
-# CONFIG_BCM_PDC_MBOX is not set
-# CONFIG_BCM_SR_THERMAL is not set
-CONFIG_BCM_VIDEOCORE=y
-# CONFIG_BGMAC_PLATFORM is not set
-CONFIG_BLK_PM=y
-# CONFIG_BRCMSTB_PM is not set
-# CONFIG_BRCMSTB_THERMAL is not set
-CONFIG_BRCM_USB_PINMAP=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23144=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CAVIUM_ERRATUM_30115=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLK_BCM2711_DVP=y
-CONFIG_CLK_BCM2835=y
-CONFIG_CLK_BCM_NS2=y
-CONFIG_CLK_BCM_SR=y
-CONFIG_CLK_IMX8MM=y
-CONFIG_CLK_IMX8MN=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MQ=y
-CONFIG_CLK_IMX8QXP=y
-CONFIG_CLK_IMX8ULP=y
-CONFIG_CLK_IMX93=y
-CONFIG_CLK_INTEL_SOCFPGA=y
-CONFIG_CLK_INTEL_SOCFPGA64=y
-CONFIG_CLK_LS1028A_PLLDIG=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_QORIQ=y
-CONFIG_CLK_RASPBERRYPI=y
-CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
-CONFIG_CLK_RENESAS=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
-# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
-# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
-CONFIG_CLK_VEXPRESS_OSC=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=19
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=32
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set
-# CONFIG_COMMON_CLK_FSL_SAI is not set
-CONFIG_COMMON_CLK_HI3516CV300=y
-CONFIG_COMMON_CLK_HI3519=y
-CONFIG_COMMON_CLK_HI3559A=y
-CONFIG_COMMON_CLK_HI3660=y
-CONFIG_COMMON_CLK_HI3670=y
-CONFIG_COMMON_CLK_HI3798CV200=y
-CONFIG_COMMON_CLK_HI6220=y
-CONFIG_COMMON_CLK_HI655X=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMMON_CLK_ZYNQMP=y
-CONFIG_COMMON_RESET_HI3660=y
-CONFIG_COMMON_RESET_HI6220=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DEV_ALLWINNER is not set
-# CONFIG_CRYPTO_DEV_BCM_SPU is not set
-# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
-# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
-# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
-# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
-# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
-# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512_ARM64=y
-CONFIG_CRYPTO_SIMD=y
-# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
-# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
-# CONFIG_DEV_DAX_HMEM is not set
-CONFIG_DMA_BCM2835=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-# CONFIG_DRM_FSL_LDB is not set
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_IMX8QM_LDB is not set
-# CONFIG_DRM_IMX8QXP_LDB is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
-# CONFIG_DRM_IMX_DCSS is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_QXL=y
-# CONFIG_DRM_RCAR_DU is not set
-# CONFIG_DRM_ROCKCHIP is not set
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-# CONFIG_DRM_V3D is not set
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-# CONFIG_DWMAC_SUN8I is not set
-# CONFIG_DWMAC_SUNXI is not set
-CONFIG_DW_WATCHDOG=y
-CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_VARS_PSTORE=y
-# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_MX3=y
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-# CONFIG_FB_XILINX is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_FSL_DPAA is not set
-# CONFIG_FSL_DPAA2_QDMA is not set
-CONFIG_FSL_ERRATUM_A008585=y
-# CONFIG_FSL_IMX8_DDR_PMU is not set
-# CONFIG_FSL_PQ_MDIO is not set
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-# CONFIG_GIANFAR is not set
-CONFIG_GPIO_BCM_XGS_IPROC=y
-CONFIG_GPIO_BRCMSTB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_RASPBERRYPI_EXP=y
-CONFIG_GPIO_ROCKCHIP=y
-CONFIG_GPIO_THUNDERX=y
-CONFIG_GPIO_XLP=y
-CONFIG_GPIO_ZYNQ=y
-CONFIG_GPIO_ZYNQMP_MODEPIN=y
-CONFIG_HDMI=y
-CONFIG_HI3660_MBOX=y
-CONFIG_HI6220_MBOX=y
-CONFIG_HISILICON_ERRATUM_161600802=y
-CONFIG_HISILICON_LPC=y
-CONFIG_HISI_PMU=y
-CONFIG_HISI_THERMAL=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
-# CONFIG_HW_RANDOM_HISI is not set
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALTERA=y
-# CONFIG_I2C_BCM2835 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HIX5HD2 is not set
-CONFIG_I2C_IMX=y
-CONFIG_I2C_IMX_LPI2C=y
-CONFIG_I2C_RIIC=y
-# CONFIG_I2C_RZV2M is not set
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_I2C_SYNQUACER=y
-CONFIG_I2C_THUNDERX=y
-# CONFIG_I2C_XLP9XX is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMX2_WDT is not set
-# CONFIG_IMX8MM_THERMAL is not set
-# CONFIG_IMX8QXP_ADC is not set
-# CONFIG_IMX_DMA is not set
-# CONFIG_IMX_DSP is not set
-CONFIG_IMX_INTMUX=y
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MBOX=y
-# CONFIG_IMX_MU_MSI is not set
-CONFIG_IMX_SCU=y
-CONFIG_IMX_SCU_PD=y
-# CONFIG_IMX_SC_THERMAL is not set
-# CONFIG_IMX_SC_WDT is not set
-# CONFIG_IMX_SDMA is not set
-# CONFIG_IMX_WEIM is not set
-# CONFIG_INPUT_HISI_POWERKEY is not set
-# CONFIG_INPUT_IBM_PANEL is not set
-# CONFIG_INTEL_STRATIX10_RSU is not set
-# CONFIG_INTEL_STRATIX10_SERVICE is not set
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=y
-CONFIG_INTERCONNECT_IMX8MM=y
-CONFIG_INTERCONNECT_IMX8MN=y
-CONFIG_INTERCONNECT_IMX8MP=y
-CONFIG_INTERCONNECT_IMX8MQ=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_DART is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPMMU_VMSA is not set
-# CONFIG_K3_DMA is not set
-CONFIG_KCMP=y
-# CONFIG_KEYBOARD_IMX_SC_KEY is not set
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-CONFIG_KSM=y
-CONFIG_KVM=y
-CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_PLATFORM is not set
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MARVELL_10G_PHY=y
-# CONFIG_MARVELL_CN10K_DDR_PMU is not set
-# CONFIG_MARVELL_CN10K_TAD_PMU is not set
-CONFIG_MDIO_BCM_IPROC=y
-CONFIG_MDIO_BUS_MUX_BCM_IPROC=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MFD_ALTERA_A10SR is not set
-CONFIG_MFD_ALTERA_SYSMGR=y
-# CONFIG_MFD_AXP20X_RSB is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_HI655X_PMIC=y
-# CONFIG_MFD_KHADAS_MCU is not set
-CONFIG_MFD_SUN4I_GPADC=y
-# CONFIG_MFD_SUN6I_PRCM is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_VEXPRESS_SYSREG=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BCM2835=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CAVIUM_THUNDERX=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_IPROC=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-CONFIG_MMC_SDHCI_PCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHI=y
-CONFIG_MMC_SDHI_INTERNAL_DMAC=y
-# CONFIG_MMC_SDHI_SYS_DMAC is not set
-# CONFIG_MMC_SH_MMCIF is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MVNETA is not set
-# CONFIG_MVPP2 is not set
-# CONFIG_MV_XOR is not set
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_CLK=y
-CONFIG_MXC_CLK_SCU=y
-# CONFIG_MXS_DMA is not set
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_VENDOR_ALLWINNER is not set
-CONFIG_NODES_SHIFT=4
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=256
-CONFIG_NUMA=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-# CONFIG_NVHE_EL2_DEBUG is not set
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-# CONFIG_NVMEM_IMX_IIM is not set
-# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
-CONFIG_NVMEM_IMX_OCOTP_SCU=y
-# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-# CONFIG_NVMEM_ROCKCHIP_OTP is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-# CONFIG_NVMEM_SUNXI_SID is not set
-# CONFIG_NVMEM_ZYNQMP is not set
-CONFIG_PCC=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_BRCMSTB=y
-CONFIG_PCIE_HISI_STB=y
-CONFIG_PCIE_IPROC_MSI=y
-CONFIG_PCIE_IPROC_PLATFORM=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_MOBIVEIL_PLAT=y
-# CONFIG_PCIE_RCAR_EP is not set
-CONFIG_PCIE_RCAR_HOST=y
-CONFIG_PCIE_ROCKCHIP=y
-# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCIE_XILINX_NWL=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PCI_HISI=y
-CONFIG_PCI_HOST_THUNDER_ECAM=y
-CONFIG_PCI_HOST_THUNDER_PEM=y
-CONFIG_PCI_IMX6=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_PASID=y
-# CONFIG_PCI_RCAR_GEN2 is not set
-CONFIG_PHY_BCM_SR_PCIE=y
-CONFIG_PHY_BCM_SR_USB=y
-CONFIG_PHY_BRCM_SATA=y
-CONFIG_PHY_BRCM_USB=y
-CONFIG_PHY_FSL_IMX8M_PCIE=y
-# CONFIG_PHY_FSL_LYNX_28G is not set
-CONFIG_PHY_HI3660_USB=y
-CONFIG_PHY_HI3670_PCIE=y
-CONFIG_PHY_HI3670_USB=y
-CONFIG_PHY_HI6220_USB=y
-CONFIG_PHY_HISI_INNO_USB2=y
-# CONFIG_PHY_HISTB_COMBPHY is not set
-# CONFIG_PHY_MIXEL_LVDS_PHY is not set
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_NS2_PCIE=y
-CONFIG_PHY_NS2_USB_DRD=y
-# CONFIG_PHY_RCAR_GEN2 is not set
-CONFIG_PHY_RCAR_GEN3_PCIE=y
-CONFIG_PHY_RCAR_GEN3_USB2=y
-CONFIG_PHY_RCAR_GEN3_USB3=y
-# CONFIG_PHY_ROCKCHIP_DP is not set
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-CONFIG_PHY_ROCKCHIP_EMMC=y
-# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-# CONFIG_PHY_ROCKCHIP_USB is not set
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN50I_USB3=y
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-CONFIG_PHY_SUN9I_USB=y
-# CONFIG_PHY_XILINX_ZYNQMP is not set
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX8DXL=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX93=y
-# CONFIG_PINCTRL_IMXRT1050 is not set
-# CONFIG_PINCTRL_IMXRT1170 is not set
-CONFIG_PINCTRL_IMX_SCU=y
-CONFIG_PINCTRL_IPROC_GPIO=y
-CONFIG_PINCTRL_NS2_MUX=y
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SUN20I_D1 is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-CONFIG_PINCTRL_SUN50I_H6=y
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_SUN50I_H6_R=y
-CONFIG_PINCTRL_SUN5I=y
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_H3_R is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_ZYNQMP=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PTP_1588_CLOCK_DTE is not set
-# CONFIG_PWM_BCM2835 is not set
-CONFIG_QCOM_FALKOR_ERRATUM_1003=y
-CONFIG_QCOM_FALKOR_ERRATUM_1009=y
-CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
-CONFIG_QCOM_QDF2400_ERRATUM_0065=y
-CONFIG_QORIQ_THERMAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RELOCATABLE=y
-# CONFIG_RAVB is not set
-CONFIG_RCAR_DMAC=y
-# CONFIG_RCAR_GEN3_THERMAL is not set
-# CONFIG_RCAR_THERMAL is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ANATOP=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_HI655X=y
-CONFIG_REGULATOR_PFUZE100=y
-# CONFIG_REGULATOR_VEXPRESS is not set
-CONFIG_RENESAS_OSTM=y
-# CONFIG_RENESAS_RZAWDT is not set
-# CONFIG_RENESAS_RZG2LWDT is not set
-# CONFIG_RENESAS_RZN1WDT is not set
-CONFIG_RENESAS_USB_DMAC=y
-# CONFIG_RENESAS_WDT is not set
-# CONFIG_RESET_BRCMSTB is not set
-CONFIG_RESET_IMX7=y
-# CONFIG_RESET_RASPBERRYPI is not set
-CONFIG_RESET_RZG2L_USBPHY_CTRL=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-# CONFIG_ROCKCHIP_MBOX is not set
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_SARADC is not set
-# CONFIG_ROCKCHIP_THERMAL is not set
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-# CONFIG_RTC_DRV_BRCMSTB is not set
-# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_IMX_SC is not set
-CONFIG_RTC_DRV_MV=y
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-# CONFIG_RTC_DRV_SH is not set
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RZG2L_ADC is not set
-# CONFIG_RZG2L_THERMAL is not set
-CONFIG_RZ_DMAC=y
-CONFIG_SATA_SIL24=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SENSORS_ARM_SCPI is not set
-CONFIG_SERIAL_8250_BCM2835AUX=y
-CONFIG_SERIAL_8250_BCM7271=y
-# CONFIG_SERIAL_8250_EXAR is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_FSL_LINFLEXUART=y
-CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-# CONFIG_SMC91X is not set
-# CONFIG_SND_SOC_RCAR is not set
-# CONFIG_SND_SOC_RZ is not set
-# CONFIG_SND_SOC_SH4_FSI is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-# CONFIG_SNI_NETSEC is not set
-CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
-CONFIG_SOC_IMX8M=y
-CONFIG_SOC_IMX9=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-# CONFIG_SPI_BCM2835 is not set
-CONFIG_SPI_FSL_LPSPI=y
-# CONFIG_SPI_FSL_QUADSPI is not set
-# CONFIG_SPI_HISI_KUNPENG is not set
-# CONFIG_SPI_HISI_SFC is not set
-# CONFIG_SPI_HISI_SFC_V3XX is not set
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_ROCKCHIP_SFC is not set
-# CONFIG_SPI_RSPI is not set
-# CONFIG_SPI_SH_HSPI is not set
-# CONFIG_SPI_SH_MSIOF is not set
-# CONFIG_SPI_SUN4I is not set
-# CONFIG_SPI_SUN6I is not set
-# CONFIG_SPI_SYNQUACER is not set
-CONFIG_SPI_THUNDERX=y
-# CONFIG_SPI_XLP is not set
-CONFIG_STUB_CLK_HI3660=y
-CONFIG_STUB_CLK_HI6220=y
-CONFIG_SUN50I_A100_CCU=y
-CONFIG_SUN50I_A100_R_CCU=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_H616_CCU=y
-CONFIG_SUN50I_H6_CCU=y
-CONFIG_SUN50I_H6_R_CCU=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_SUN6I_MSGBOX=y
-CONFIG_SUN6I_RTC_CCU=y
-# CONFIG_SUN8I_A83T_CCU is not set
-CONFIG_SUN8I_DE2_CCU=y
-# CONFIG_SUN8I_H3_CCU is not set
-CONFIG_SUN8I_R_CCU=y
-CONFIG_SUN8I_THERMAL=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUNXI_RSB=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_TCG_TIS_SYNQUACER is not set
-CONFIG_THREAD_INFO_IN_TASK=y
-# CONFIG_THUNDERX2_PMU is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_TURRIS_MOX_RWTM is not set
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_ANX7411 is not set
-# CONFIG_TYPEC_DP_ALTMODE is not set
-# CONFIG_TYPEC_FUSB302 is not set
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_FSA4480 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_RT1711H is not set
-# CONFIG_TYPEC_RT1719 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-CONFIG_TYPEC_TCPCI=y
-# CONFIG_TYPEC_TCPCI_MAXIM is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_TYPEC_WUSB3801 is not set
-# CONFIG_UACCE is not set
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-# CONFIG_USB_BRCMSTB is not set
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_GENERIC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_PCI=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_DUAL_ROLE=y
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_HAPS=y
-# CONFIG_USB_DWC3_HOST is not set
-CONFIG_USB_DWC3_IMX8MP=y
-# CONFIG_USB_DWC3_OF_SIMPLE is not set
-CONFIG_USB_DWC3_PCI=y
-# CONFIG_USB_DWC3_ULPI is not set
-CONFIG_USB_DWC3_XILINX=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EMXX is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OHCI_EXYNOS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_OTG=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_RENESAS_USB3=y
-CONFIG_USB_RENESAS_USBHS=y
-CONFIG_USB_RENESAS_USBHS_HCD=y
-CONFIG_USB_RENESAS_USBHS_UDC=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_HISTB=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-# CONFIG_VIRTIO_IOMMU is not set
-CONFIG_VIRTUALIZATION=y
-CONFIG_VMAP_STACK=y
-CONFIG_WDAT_WDT=y
-# CONFIG_XILINX_AMS is not set
-# CONFIG_XILINX_INTC is not set
-CONFIG_XLNX_EVENT_MANAGER=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZYNQMP_FIRMWARE=y
-# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
-CONFIG_ZYNQMP_PM_DOMAINS=y
-CONFIG_ZYNQMP_POWER=y
diff --git a/target/linux/armsr/armv8/config-6.6 b/target/linux/armsr/armv8/config-6.6
new file mode 100644
index 0000000000..aa5774a7b6
--- /dev/null
+++ b/target/linux/armsr/armv8/config-6.6
@@ -0,0 +1,852 @@
+CONFIG_64BIT=y
+CONFIG_ACPI_APEI=y
+# CONFIG_ACPI_FFH is not set
+# CONFIG_ACPI_FPDT is not set
+CONFIG_ACPI_HMAT=y
+CONFIG_ACPI_PCC=y
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM2835=y
+# CONFIG_ARCH_BCMBCA is not set
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774B1=y
+CONFIG_ARCH_R8A774C0=y
+CONFIG_ARCH_R8A774E1=y
+# CONFIG_ARCH_R8A77950 is not set
+# CONFIG_ARCH_R8A77951 is not set
+# CONFIG_ARCH_R8A77960 is not set
+# CONFIG_ARCH_R8A77961 is not set
+# CONFIG_ARCH_R8A77965 is not set
+# CONFIG_ARCH_R8A77970 is not set
+# CONFIG_ARCH_R8A77980 is not set
+# CONFIG_ARCH_R8A77990 is not set
+# CONFIG_ARCH_R8A77995 is not set
+# CONFIG_ARCH_R8A779A0 is not set
+# CONFIG_ARCH_R8A779F0 is not set
+# CONFIG_ARCH_R8A779G0 is not set
+CONFIG_ARCH_R9A07G043=y
+CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A07G054=y
+CONFIG_ARCH_R9A09G011=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_THUNDER2=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_ARM64_BTI=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_MTE=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_TLB_RANGE=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
+CONFIG_ARMADA_37XX_WATCHDOG=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+# CONFIG_ARM_DMC620_PMU is not set
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMC_WATCHDOG=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_PMU is not set
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+# CONFIG_AXI_DMAC is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BCM2711_THERMAL is not set
+CONFIG_BCM2835_MBOX=y
+CONFIG_BCM2835_POWER=y
+# CONFIG_BCM2835_THERMAL is not set
+# CONFIG_BCM2835_VCHIQ is not set
+CONFIG_BCM2835_WDT=y
+# CONFIG_BCMASP is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_BCM_CYGNUS_PHY is not set
+# CONFIG_BCM_FLEXRM_MBOX is not set
+# CONFIG_BCM_NS_THERMAL is not set
+# CONFIG_BCM_PDC_MBOX is not set
+# CONFIG_BCM_SR_THERMAL is not set
+CONFIG_BCM_VIDEOCORE=y
+# CONFIG_BGMAC_PLATFORM is not set
+CONFIG_BLK_PM=y
+# CONFIG_BRCMSTB_PM is not set
+# CONFIG_BRCMSTB_THERMAL is not set
+CONFIG_BRCM_USB_PINMAP=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLK_BCM2711_DVP=y
+CONFIG_CLK_BCM2835=y
+CONFIG_CLK_BCM_NS2=y
+CONFIG_CLK_BCM_SR=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MQ=y
+CONFIG_CLK_IMX8QXP=y
+CONFIG_CLK_IMX8ULP=y
+CONFIG_CLK_IMX93=y
+CONFIG_CLK_INTEL_SOCFPGA=y
+CONFIG_CLK_INTEL_SOCFPGA64=y
+CONFIG_CLK_LS1028A_PLLDIG=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLK_RASPBERRYPI=y
+CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
+# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
+# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=19
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=32
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set
+# CONFIG_COMMON_CLK_FSL_SAI is not set
+CONFIG_COMMON_CLK_HI3516CV300=y
+CONFIG_COMMON_CLK_HI3519=y
+CONFIG_COMMON_CLK_HI3559A=y
+CONFIG_COMMON_CLK_HI3660=y
+CONFIG_COMMON_CLK_HI3670=y
+CONFIG_COMMON_CLK_HI3798CV200=y
+CONFIG_COMMON_CLK_HI6220=y
+CONFIG_COMMON_CLK_HI655X=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_ZYNQMP=y
+CONFIG_COMMON_RESET_HI3660=y
+CONFIG_COMMON_RESET_HI6220=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ALLWINNER is not set
+# CONFIG_CRYPTO_DEV_BCM_SPU is not set
+# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
+# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
+# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
+# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
+# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SIMD=y
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+# CONFIG_DEV_DAX_HMEM is not set
+CONFIG_DMA_BCM2835=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+# CONFIG_DMA_NUMA_CMA is not set
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DRM=y
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+# CONFIG_DRM_FSL_LDB is not set
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+# CONFIG_DRM_IMX8QM_LDB is not set
+# CONFIG_DRM_IMX8QXP_LDB is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_IMX_DCSS is not set
+# CONFIG_DRM_IMX_LCDC is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
+# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
+CONFIG_DRM_QXL=y
+# CONFIG_DRM_RCAR_DU is not set
+# CONFIG_DRM_ROCKCHIP is not set
+# CONFIG_DRM_RZG2L_MIPI_DSI is not set
+# CONFIG_DRM_SHMOBILE is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+# CONFIG_DRM_V3D is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VRAM_HELPER=y
+# CONFIG_DWMAC_SUN8I is not set
+# CONFIG_DWMAC_SUNXI is not set
+CONFIG_DW_WATCHDOG=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_VARS_PSTORE=y
+# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MX3=y
+# CONFIG_FB_SH_MOBILE_LCDC is not set
+# CONFIG_FB_XILINX is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FSL_DPAA is not set
+# CONFIG_FSL_DPAA2_QDMA is not set
+CONFIG_FSL_ERRATUM_A008585=y
+# CONFIG_FSL_IMX8_DDR_PMU is not set
+# CONFIG_FSL_PQ_MDIO is not set
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+# CONFIG_GIANFAR is not set
+CONFIG_GPIO_BCM_XGS_IPROC=y
+CONFIG_GPIO_BRCMSTB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_RASPBERRYPI_EXP=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_THUNDERX=y
+CONFIG_GPIO_XLP=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_GPIO_ZYNQMP_MODEPIN=y
+CONFIG_HDMI=y
+CONFIG_HI3660_MBOX=y
+CONFIG_HI6220_MBOX=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_HISILICON_LPC=y
+CONFIG_HISI_PMU=y
+CONFIG_HISI_THERMAL=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+# CONFIG_HW_RANDOM_HISI is not set
+# CONFIG_HW_RANDOM_HISTB is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALTERA=y
+# CONFIG_I2C_BCM2835 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HIX5HD2 is not set
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_RIIC=y
+# CONFIG_I2C_RZV2M is not set
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_SYNQUACER=y
+CONFIG_I2C_THUNDERX=y
+# CONFIG_I2C_XLP9XX is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMX2_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+# CONFIG_IMX8QXP_ADC is not set
+# CONFIG_IMX93_ADC is not set
+# CONFIG_IMX_DMA is not set
+# CONFIG_IMX_DSP is not set
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MBOX=y
+# CONFIG_IMX_MU_MSI is not set
+CONFIG_IMX_SCU=y
+CONFIG_IMX_SCU_PD=y
+# CONFIG_IMX_SC_THERMAL is not set
+# CONFIG_IMX_SC_WDT is not set
+# CONFIG_IMX_SDMA is not set
+# CONFIG_IMX_WEIM is not set
+# CONFIG_INPUT_BBNSM_PWRKEY is not set
+# CONFIG_INPUT_HISI_POWERKEY is not set
+# CONFIG_INPUT_IBM_PANEL is not set
+# CONFIG_INTEL_STRATIX10_RSU is not set
+# CONFIG_INTEL_STRATIX10_SERVICE is not set
+CONFIG_INTERCONNECT=y
+CONFIG_INTERCONNECT_IMX=y
+CONFIG_INTERCONNECT_IMX8MM=y
+CONFIG_INTERCONNECT_IMX8MN=y
+CONFIG_INTERCONNECT_IMX8MP=y
+CONFIG_INTERCONNECT_IMX8MQ=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPMMU_VMSA is not set
+# CONFIG_K3_DMA is not set
+CONFIG_KCMP=y
+# CONFIG_KEYBOARD_IMX_SC_KEY is not set
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+CONFIG_KSM=y
+# CONFIG_KUNPENG_HCCS is not set
+CONFIG_KVM=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MARVELL_10G_PHY=y
+# CONFIG_MARVELL_CN10K_DDR_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
+# CONFIG_MARVELL_GTI_WDT is not set
+CONFIG_MDIO_BCM_IPROC=y
+CONFIG_MDIO_BUS_MUX_BCM_IPROC=y
+CONFIG_MDIO_SUN4I=y
+# CONFIG_MFD_ALTERA_A10SR is not set
+CONFIG_MFD_ALTERA_SYSMGR=y
+# CONFIG_MFD_AXP20X_RSB is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_HI655X_PMIC=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_SUN4I_GPADC=y
+# CONFIG_MFD_SUN6I_PRCM is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CAVIUM_THUNDERX=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IPROC=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SDHI_INTERNAL_DMAC=y
+# CONFIG_MMC_SDHI_SYS_DMAC is not set
+# CONFIG_MMC_SH_MMCIF is not set
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MVNETA is not set
+# CONFIG_MVPP2 is not set
+# CONFIG_MV_XOR is not set
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_CLK=y
+CONFIG_MXC_CLK_SCU=y
+# CONFIG_MXS_DMA is not set
+CONFIG_NEED_SG_DMA_LENGTH=y
+# CONFIG_NET_VENDOR_ALLWINNER is not set
+CONFIG_NODES_SHIFT=4
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NUMA=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_IMX_OCOTP_SCU=y
+# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+# CONFIG_NVMEM_SUNXI_SID is not set
+# CONFIG_NVMEM_ZYNQMP is not set
+CONFIG_PCC=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_ARMADA_8K=y
+CONFIG_PCIE_BRCMSTB=y
+CONFIG_PCIE_HISI_STB=y
+CONFIG_PCIE_IPROC_MSI=y
+CONFIG_PCIE_IPROC_PLATFORM=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_MOBIVEIL_PLAT=y
+# CONFIG_PCIE_RCAR_EP is not set
+CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_ROCKCHIP=y
+# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCIE_XILINX_CPM=y
+CONFIG_PCIE_XILINX_NWL=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_IMX6=y
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_PASID=y
+# CONFIG_PCI_RCAR_GEN2 is not set
+CONFIG_PHY_BCM_SR_PCIE=y
+CONFIG_PHY_BCM_SR_USB=y
+CONFIG_PHY_BRCM_SATA=y
+CONFIG_PHY_BRCM_USB=y
+CONFIG_PHY_FSL_IMX8M_PCIE=y
+# CONFIG_PHY_FSL_LYNX_28G is not set
+CONFIG_PHY_HI3660_USB=y
+CONFIG_PHY_HI3670_PCIE=y
+CONFIG_PHY_HI3670_USB=y
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_HISI_INNO_USB2=y
+# CONFIG_PHY_HISTB_COMBPHY is not set
+# CONFIG_PHY_MIXEL_LVDS_PHY is not set
+CONFIG_PHY_MVEBU_A3700_COMPHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+CONFIG_PHY_MVEBU_A38X_COMPHY=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_NS2_PCIE=y
+CONFIG_PHY_NS2_USB_DRD=y
+# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set
+# CONFIG_PHY_RCAR_GEN2 is not set
+CONFIG_PHY_RCAR_GEN3_PCIE=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=y
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+# CONFIG_PHY_ROCKCHIP_USB is not set
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+CONFIG_PHY_SUN9I_USB=y
+# CONFIG_PHY_XILINX_ZYNQMP is not set
+CONFIG_PINCTRL_IMX=y
+CONFIG_PINCTRL_IMX8DXL=y
+CONFIG_PINCTRL_IMX8MM=y
+CONFIG_PINCTRL_IMX8MN=y
+CONFIG_PINCTRL_IMX8MP=y
+CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_PINCTRL_IMX8QM=y
+CONFIG_PINCTRL_IMX8QXP=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_PINCTRL_IMX93=y
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PINCTRL_IMX_SCU=y
+CONFIG_PINCTRL_IPROC_GPIO=y
+CONFIG_PINCTRL_NS2_MUX=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SUN20I_D1 is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A64=y
+CONFIG_PINCTRL_SUN50I_A64_R=y
+CONFIG_PINCTRL_SUN50I_H5=y
+CONFIG_PINCTRL_SUN50I_H6=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN5I=y
+# CONFIG_PINCTRL_SUN6I_A31 is not set
+# CONFIG_PINCTRL_SUN6I_A31_R is not set
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN8I_A33 is not set
+# CONFIG_PINCTRL_SUN8I_A83T is not set
+# CONFIG_PINCTRL_SUN8I_A83T_R is not set
+# CONFIG_PINCTRL_SUN8I_H3 is not set
+# CONFIG_PINCTRL_SUN8I_H3_R is not set
+# CONFIG_PINCTRL_SUN8I_V3S is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+# CONFIG_PINCTRL_SUN9I_A80_R is not set
+CONFIG_PINCTRL_ZYNQMP=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_HISI=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PTP_1588_CLOCK_DTE is not set
+# CONFIG_PWM_BCM2835 is not set
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
+# CONFIG_RAVB is not set
+CONFIG_RCAR_DMAC=y
+# CONFIG_RCAR_GEN3_THERMAL is not set
+# CONFIG_RCAR_THERMAL is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RELOCATABLE=y
+# CONFIG_RENESAS_ETHER_SWITCH is not set
+CONFIG_RENESAS_OSTM=y
+# CONFIG_RENESAS_RZAWDT is not set
+# CONFIG_RENESAS_RZG2LWDT is not set
+# CONFIG_RENESAS_RZN1WDT is not set
+CONFIG_RENESAS_USB_DMAC=y
+# CONFIG_RENESAS_WDT is not set
+# CONFIG_RESET_BRCMSTB is not set
+CONFIG_RESET_IMX7=y
+# CONFIG_RESET_RASPBERRYPI is not set
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ROCKCHIP_MBOX is not set
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+# CONFIG_ROCKCHIP_THERMAL is not set
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_RTC_DRV_BBNSM is not set
+# CONFIG_RTC_DRV_BRCMSTB is not set
+# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_IMX_SC is not set
+CONFIG_RTC_DRV_MV=y
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+# CONFIG_RTC_DRV_SH is not set
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RZG2L_ADC is not set
+# CONFIG_RZG2L_THERMAL is not set
+CONFIG_RZ_DMAC=y
+CONFIG_RZ_MTU3=y
+CONFIG_SATA_SIL24=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+# CONFIG_SENSORS_ARM_SCPI is not set
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_BCM7271=y
+# CONFIG_SERIAL_8250_EXAR is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MVEBU_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=18
+# CONFIG_SMC91X is not set
+# CONFIG_SND_SOC_RCAR is not set
+# CONFIG_SND_SOC_RZ is not set
+# CONFIG_SND_SOC_SH4_FSI is not set
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+# CONFIG_SND_SUN8I_CODEC is not set
+# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
+# CONFIG_SNI_NETSEC is not set
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+CONFIG_SOC_IMX8M=y
+CONFIG_SOC_IMX9=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPI_ARMADA_3700=y
+# CONFIG_SPI_BCM2835 is not set
+CONFIG_SPI_FSL_LPSPI=y
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_HISI_KUNPENG is not set
+# CONFIG_SPI_HISI_SFC is not set
+# CONFIG_SPI_HISI_SFC_V3XX is not set
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_ROCKCHIP_SFC is not set
+# CONFIG_SPI_RSPI is not set
+# CONFIG_SPI_RZV2M_CSI is not set
+# CONFIG_SPI_SH_HSPI is not set
+# CONFIG_SPI_SH_MSIOF is not set
+# CONFIG_SPI_SUN4I is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SPI_SYNQUACER is not set
+CONFIG_SPI_THUNDERX=y
+# CONFIG_SPI_XLP is not set
+# CONFIG_SSIF_IPMI_BMC is not set
+CONFIG_STUB_CLK_HI3660=y
+CONFIG_STUB_CLK_HI6220=y
+# CONFIG_SUN20I_GPADC is not set
+# CONFIG_SUN20I_PPU is not set
+CONFIG_SUN50I_A100_CCU=y
+CONFIG_SUN50I_A100_R_CCU=y
+CONFIG_SUN50I_A64_CCU=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SUN50I_H6_CCU=y
+CONFIG_SUN50I_H6_R_CCU=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=y
+# CONFIG_SUN8I_A83T_CCU is not set
+CONFIG_SUN8I_DE2_CCU=y
+# CONFIG_SUN8I_H3_CCU is not set
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_TCG_TIS_SYNQUACER is not set
+CONFIG_THREAD_INFO_IN_TASK=y
+# CONFIG_THUNDERX2_PMU is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+# CONFIG_TURRIS_MOX_RWTM is not set
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+# CONFIG_TYPEC_DP_ALTMODE is not set
+# CONFIG_TYPEC_FUSB302 is not set
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1711H is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_TCPCI=y
+# CONFIG_TYPEC_TCPCI_MAXIM is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UACCE is not set
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+# CONFIG_USB_BRCMSTB is not set
+# CONFIG_USB_CDNS2_UDC is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_GENERIC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_PCI=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_HAPS=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_IMX8MP=y
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_DWC3_PCI=y
+# CONFIG_USB_DWC3_ULPI is not set
+CONFIG_USB_DWC3_XILINX=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_ORION=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EMXX is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_RENESAS_USB3=y
+CONFIG_USB_RENESAS_USBF=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_RENESAS_USBHS_HCD=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_RZV2M_USB3DRD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_HISTB=y
+CONFIG_USB_XHCI_MVEBU=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USB_XHCI_RCAR is not set
+CONFIG_USB_XHCI_RZV2M=y
+CONFIG_VEXPRESS_CONFIG=y
+# CONFIG_VFIO_AMBA is not set
+CONFIG_VIDEOMODE_HELPERS=y
+# CONFIG_VIDEO_IMX7_CSI is not set
+# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set
+# CONFIG_VIDEO_IMX8_ISI is not set
+# CONFIG_VIDEO_RZG2L_CRU is not set
+# CONFIG_VIDEO_RZG2L_CSI2 is not set
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
+# CONFIG_VIRTIO_IOMMU is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_STACK=y
+CONFIG_WDAT_WDT=y
+# CONFIG_XILINX_AMS is not set
+# CONFIG_XILINX_INTC is not set
+CONFIG_XLNX_EVENT_MANAGER=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZYNQMP_FIRMWARE=y
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
+CONFIG_ZYNQMP_PM_DOMAINS=y
+CONFIG_ZYNQMP_POWER=y
diff --git a/target/linux/armsr/base-files/etc/board.d/03_gpio_switches b/target/linux/armsr/base-files/etc/board.d/03_gpio_switches
index cf07bc0f54..72f310277a 100644
--- a/target/linux/armsr/base-files/etc/board.d/03_gpio_switches
+++ b/target/linux/armsr/base-files/etc/board.d/03_gpio_switches
@@ -3,18 +3,26 @@
 
 . /lib/functions/uci-defaults.sh
 
+KERNEL_MAJOR=$(uname -r | awk -F '.' '{print $1}')
+KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}')
+
 board_config_update
 
 board=$(board_name)
 
 case "$board" in
 traverse,ten64)
-	ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "376"
-	ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "377"
-	ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "378"
-	ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "379"
-	ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "369"
-	ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "373"
+	if [ "${KERNEL_MAJOR}" -ge "6" ] && [ "${KERNEL_MINOR}" -ge "6" ]; then
+		I2C_GPIO_BASE=640
+	else
+		I2C_GPIO_BASE=368
+	fi
+	ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "$(($I2C_GPIO_BASE + 8))"
+	ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "$(($I2C_GPIO_BASE + 9))"
+	ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "$((I2C_GPIO_BASE + 10))"
+	ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "$(($I2C_GPIO_BASE + 11))"
+	ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "$(($I2C_GPIO_BASE + 1))"
+	ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "$(($I2C_GPIO_BASE + 5))"
 	;;
 esac
 
diff --git a/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio b/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio
new file mode 100644
index 0000000000..dc8648e570
--- /dev/null
+++ b/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio
@@ -0,0 +1,37 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This script migrates GPIO switch pin numbers
+# from kernel versions prior to 6.6
+# See https://lists.openwrt.org/pipermail/openwrt-devel/2024-March/042448.html
+
+. /lib/functions.sh
+
+ten64_update_gpioswitch_num() {
+	local section="$1"
+	config_get gpio_pin  "${section}" gpio_pin
+	config_get gpio_name "${section}" name
+	if [ -z "${gpio_pin}" ]; then
+		return
+	fi
+	local this_pin_name=$(uci get "system.${section}.name")
+	if [ "${gpio_pin}" -lt 640 ]; then
+		new_pin_value=$(( $gpio_pin + 272 ))
+		uci set "system.${section}.gpio_pin=${new_pin_value}"
+	fi
+}
+
+board=$(board_name)
+if [ "${board}" != "traverse,ten64" ]; then
+	exit 0
+fi
+
+KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}')
+if [ "${KERNEL_MINOR}" -lt "6" ]; then
+	exit 0
+fi
+
+config_load system
+config_foreach ten64_update_gpioswitch_num gpio_switch
+
+exit 0
\ No newline at end of file
diff --git a/target/linux/armsr/config-6.1 b/target/linux/armsr/config-6.1
deleted file mode 100644
index d1dac69da4..0000000000
--- a/target/linux/armsr/config-6.1
+++ /dev/null
@@ -1,336 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_9P_FS=y
-# CONFIG_9P_FS_POSIX_ACL is not set
-# CONFIG_9P_FS_SECURITY is not set
-# CONFIG_A64FX_DIAG is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_EINJ=y
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_CCA_REQUIRED=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPPC_CPUFREQ=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-CONFIG_ACPI_GENERIC_GSI=y
-CONFIG_ACPI_GTDT=y
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_ACPI_IORT=y
-CONFIG_ACPI_MCFG=y
-# CONFIG_ACPI_PCI_SLOT is not set
-# CONFIG_ACPI_PFRUT is not set
-CONFIG_ACPI_PPTT=y
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TINY_POWER_BUTTON is not set
-# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SMMU_V3_PMU is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=y
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FB_EFI=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_HISI is not set
-CONFIG_GPIO_PL061=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HZ_PERIODIC=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_HID_ACPI=y
-# CONFIG_I2C_HISI is not set
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MIGRATION=y
-# CONFIG_MLXBF_GIGE is not set
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVMDIO=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_9P=y
-# CONFIG_NET_9P_DEBUG is not set
-# CONFIG_NET_9P_FD is not set
-CONFIG_NET_9P_VIRTIO=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NR_CPUS=256
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_PADATA=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-# CONFIG_PCIE_HISI_ERR is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_EFI=y
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_VIRTIO=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFB=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_ACPI=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UCS2_STRING=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_XPS=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/armsr/config-6.6 b/target/linux/armsr/config-6.6
new file mode 100644
index 0000000000..8b4f291c9f
--- /dev/null
+++ b/target/linux/armsr/config-6.6
@@ -0,0 +1,338 @@
+CONFIG_64BIT=y
+CONFIG_9P_FS=y
+# CONFIG_9P_FS_POSIX_ACL is not set
+# CONFIG_9P_FS_SECURITY is not set
+# CONFIG_A64FX_DIAG is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_EINJ=y
+# CONFIG_ACPI_APEI_ERST_DEBUG is not set
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPPC_CPUFREQ=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_GTDT=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_MCFG=y
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PRMT=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU_V3_PMU is not set
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=y
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FB_EFI=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_GPIO_HISI is not set
+CONFIG_GPIO_PL061=y
+# CONFIG_GPIO_VF610 is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HZ_PERIODIC=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_HID_ACPI=y
+# CONFIG_I2C_HISI is not set
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MIGRATION=y
+# CONFIG_MLXBF_GIGE is not set
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MVMDIO=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_9P=y
+# CONFIG_NET_9P_DEBUG is not set
+# CONFIG_NET_9P_FD is not set
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+# CONFIG_PCIE_HISI_ERR is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RATIONAL=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_HOST=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_UACCE is not set
+CONFIG_UCS2_STRING=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VMAP_STACK=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/armsr/modules.mk b/target/linux/armsr/modules.mk
index 7dd3739ffa..d5a5d5c407 100644
--- a/target/linux/armsr/modules.mk
+++ b/target/linux/armsr/modules.mk
@@ -92,6 +92,7 @@ define KernelPackage/fsl-enetc-net
     CONFIG_FSL_ENETC_QOS=y
   FILES:= \
     $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc.ko \
+    $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-core.ko@ge6.3 \
     $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-vf.ko \
     $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko \
     $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-ierb.ko
diff --git a/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch b/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch
new file mode 100644
index 0000000000..c9dbdf2521
--- /dev/null
+++ b/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch
@@ -0,0 +1,23 @@
+From b77c0ecdc7915e5c5c515da1aa6cfaf6f4eb8351 Mon Sep 17 00:00:00 2001
+From: Mathew McBride <matt@traverse.com.au>
+Date: Wed, 28 Sep 2022 16:39:31 +1000
+Subject: [PATCH] arm: disable code size reduction measures
+ (gc-sections,-f*-sections)
+
+This interferes with the EFI boot stub on armv7l.
+
+Signed-off-by: Mathew McBride <matt@traverse.com.au>
+---
+ arch/arm/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -128,7 +128,6 @@ config ARM
+ 	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
+ 	select IRQ_FORCED_THREADING
+ 	select LOCK_MM_AND_FIND_VMA
+-	select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
+ 	select MODULES_USE_ELF_REL
+ 	select NEED_DMA_MAP_STATE
+ 	select OF_EARLY_FLATTREE if OF
diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile
index 10608bff77..d02a32071b 100644
--- a/target/linux/at91/Makefile
+++ b/target/linux/at91/Makefile
@@ -10,8 +10,7 @@ BOARDNAME:=Microchip (Atmel AT91)
 FEATURES:=ext4 squashfs targz usbgadget ubifs
 SUBTARGETS:=sama7 sama5 sam9x
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch b/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch
deleted file mode 100644
index 5d399f6535..0000000000
--- a/target/linux/at91/patches-5.15/100-clk-at91-re-factor-clocks-suspend-resume.patch
+++ /dev/null
@@ -1,1342 +0,0 @@
-From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:05 +0300
-Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume
-
-SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
-most of the SoC's components are powered off (including PMC). Resuming
-from this mode is done with the help of bootloader. Peripherals are not
-aware of the power saving mode thus most of them are disabling clocks in
-proper suspend API and re-enable them in resume API without taking into
-account the previously setup rate. Moreover some of the peripherals are
-acting as wakeup sources and are not disabling the clocks in this
-scenario, when suspending. Since backup mode cuts the power for
-peripherals, in resume part these clocks needs to be re-configured.
-
-The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
-(as it was the only one supporting backup mode). SAMA7G supports also
-backup mode and its PMC is different (few new functionalities, different
-registers offsets, different offsets in registers for each
-functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
-.save_context()/.resume_context() support to each clocks driver and call
-this from PMC driver.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-generated.c    |  46 +++++--
- drivers/clk/at91/clk-main.c         |  66 ++++++++++
- drivers/clk/at91/clk-master.c       | 194 ++++++++++++++++++++++++++--
- drivers/clk/at91/clk-peripheral.c   |  40 +++++-
- drivers/clk/at91/clk-pll.c          |  39 ++++++
- drivers/clk/at91/clk-programmable.c |  29 ++++-
- drivers/clk/at91/clk-sam9x60-pll.c  |  68 +++++++++-
- drivers/clk/at91/clk-system.c       |  20 +++
- drivers/clk/at91/clk-usb.c          |  27 ++++
- drivers/clk/at91/clk-utmi.c         |  39 ++++++
- drivers/clk/at91/pmc.c              | 147 +--------------------
- drivers/clk/at91/pmc.h              |  24 ++--
- 12 files changed, 558 insertions(+), 181 deletions(-)
-
---- a/drivers/clk/at91/clk-generated.c
-+++ b/drivers/clk/at91/clk-generated.c
-@@ -27,6 +27,7 @@ struct clk_generated {
- 	u32 id;
- 	u32 gckdiv;
- 	const struct clk_pcr_layout *layout;
-+	struct at91_clk_pms pms;
- 	u8 parent_id;
- 	int chg_pid;
- };
-@@ -34,25 +35,35 @@ struct clk_generated {
- #define to_clk_generated(hw) \
- 	container_of(hw, struct clk_generated, hw)
- 
--static int clk_generated_enable(struct clk_hw *hw)
-+static int clk_generated_set(struct clk_generated *gck, int status)
- {
--	struct clk_generated *gck = to_clk_generated(hw);
- 	unsigned long flags;
--
--	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
--		 __func__, gck->gckdiv, gck->parent_id);
-+	unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
- 
- 	spin_lock_irqsave(gck->lock, flags);
- 	regmap_write(gck->regmap, gck->layout->offset,
- 		     (gck->id & gck->layout->pid_mask));
- 	regmap_update_bits(gck->regmap, gck->layout->offset,
- 			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
--			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
-+			   gck->layout->cmd | enable,
- 			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
- 			   gck->layout->cmd |
- 			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
--			   AT91_PMC_PCR_GCKEN);
-+			   enable);
- 	spin_unlock_irqrestore(gck->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int clk_generated_enable(struct clk_hw *hw)
-+{
-+	struct clk_generated *gck = to_clk_generated(hw);
-+
-+	pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
-+		 __func__, gck->gckdiv, gck->parent_id);
-+
-+	clk_generated_set(gck, 1);
-+
- 	return 0;
- }
- 
-@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct
- 	return 0;
- }
- 
-+static int clk_generated_save_context(struct clk_hw *hw)
-+{
-+	struct clk_generated *gck = to_clk_generated(hw);
-+
-+	gck->pms.status = clk_generated_is_enabled(&gck->hw);
-+
-+	return 0;
-+}
-+
-+static void clk_generated_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_generated *gck = to_clk_generated(hw);
-+
-+	if (gck->pms.status)
-+		clk_generated_set(gck, gck->pms.status);
-+}
-+
- static const struct clk_ops generated_ops = {
- 	.enable = clk_generated_enable,
- 	.disable = clk_generated_disable,
-@@ -258,6 +286,8 @@ static const struct clk_ops generated_op
- 	.get_parent = clk_generated_get_parent,
- 	.set_parent = clk_generated_set_parent,
- 	.set_rate = clk_generated_set_rate,
-+	.save_context = clk_generated_save_context,
-+	.restore_context = clk_generated_restore_context,
- };
- 
- /**
-@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma
- 	if (ret) {
- 		kfree(gck);
- 		hw = ERR_PTR(ret);
--	} else {
--		pmc_register_id(id);
- 	}
- 
- 	return hw;
---- a/drivers/clk/at91/clk-main.c
-+++ b/drivers/clk/at91/clk-main.c
-@@ -28,6 +28,7 @@
- struct clk_main_osc {
- 	struct clk_hw hw;
- 	struct regmap *regmap;
-+	struct at91_clk_pms pms;
- };
- 
- #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
-@@ -37,6 +38,7 @@ struct clk_main_rc_osc {
- 	struct regmap *regmap;
- 	unsigned long frequency;
- 	unsigned long accuracy;
-+	struct at91_clk_pms pms;
- };
- 
- #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
-@@ -51,6 +53,7 @@ struct clk_rm9200_main {
- struct clk_sam9x5_main {
- 	struct clk_hw hw;
- 	struct regmap *regmap;
-+	struct at91_clk_pms pms;
- 	u8 parent;
- };
- 
-@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru
- 	return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
- }
- 
-+static int clk_main_osc_save_context(struct clk_hw *hw)
-+{
-+	struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+	osc->pms.status = clk_main_osc_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_main_osc_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+	if (osc->pms.status)
-+		clk_main_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_osc_ops = {
- 	.prepare = clk_main_osc_prepare,
- 	.unprepare = clk_main_osc_unprepare,
- 	.is_prepared = clk_main_osc_is_prepared,
-+	.save_context = clk_main_osc_save_context,
-+	.restore_context = clk_main_osc_restore_context,
- };
- 
- struct clk_hw * __init
-@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec
- 	return osc->accuracy;
- }
- 
-+static int clk_main_rc_osc_save_context(struct clk_hw *hw)
-+{
-+	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+	osc->pms.status = clk_main_rc_osc_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_main_rc_osc_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+	if (osc->pms.status)
-+		clk_main_rc_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_rc_osc_ops = {
- 	.prepare = clk_main_rc_osc_prepare,
- 	.unprepare = clk_main_rc_osc_unprepare,
- 	.is_prepared = clk_main_rc_osc_is_prepared,
- 	.recalc_rate = clk_main_rc_osc_recalc_rate,
- 	.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
-+	.save_context = clk_main_rc_osc_save_context,
-+	.restore_context = clk_main_rc_osc_restore_context,
- };
- 
- struct clk_hw * __init
-@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str
- 	return clk_main_parent_select(status);
- }
- 
-+static int clk_sam9x5_main_save_context(struct clk_hw *hw)
-+{
-+	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+
-+	clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);
-+	clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);
-+
-+	return 0;
-+}
-+
-+static void clk_sam9x5_main_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+	int ret;
-+
-+	ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);
-+	if (ret)
-+		return;
-+
-+	if (clkmain->pms.status)
-+		clk_sam9x5_main_prepare(hw);
-+}
-+
- static const struct clk_ops sam9x5_main_ops = {
- 	.prepare = clk_sam9x5_main_prepare,
- 	.is_prepared = clk_sam9x5_main_is_prepared,
- 	.recalc_rate = clk_sam9x5_main_recalc_rate,
- 	.set_parent = clk_sam9x5_main_set_parent,
- 	.get_parent = clk_sam9x5_main_get_parent,
-+	.save_context = clk_sam9x5_main_save_context,
-+	.restore_context = clk_sam9x5_main_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -37,6 +37,7 @@ struct clk_master {
- 	spinlock_t *lock;
- 	const struct clk_master_layout *layout;
- 	const struct clk_master_characteristics *characteristics;
-+	struct at91_clk_pms pms;
- 	u32 *mux_table;
- 	u32 mckr;
- 	int chg_pid;
-@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca
- 	return rate;
- }
- 
-+static int clk_master_div_save_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+	struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+	unsigned long flags;
-+	unsigned int mckr, div;
-+
-+	spin_lock_irqsave(master->lock, flags);
-+	regmap_read(master->regmap, master->layout->offset, &mckr);
-+	spin_unlock_irqrestore(master->lock, flags);
-+
-+	mckr &= master->layout->mask;
-+	div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+	div = master->characteristics->divisors[div];
-+
-+	master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+	master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);
-+
-+	return 0;
-+}
-+
-+static void clk_master_div_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+	unsigned long flags;
-+	unsigned int mckr;
-+	u8 div;
-+
-+	spin_lock_irqsave(master->lock, flags);
-+	regmap_read(master->regmap, master->layout->offset, &mckr);
-+	spin_unlock_irqrestore(master->lock, flags);
-+
-+	mckr &= master->layout->mask;
-+	div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+	div = master->characteristics->divisors[div];
-+
-+	if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))
-+		pr_warn("MCKR DIV not configured properly by firmware!\n");
-+}
-+
- static const struct clk_ops master_div_ops = {
- 	.prepare = clk_master_prepare,
- 	.is_prepared = clk_master_is_prepared,
- 	.recalc_rate = clk_master_div_recalc_rate,
-+	.save_context = clk_master_div_save_context,
-+	.restore_context = clk_master_div_restore_context,
- };
- 
- static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc
- 	const struct clk_master_characteristics *characteristics =
- 						master->characteristics;
- 	unsigned long flags;
-+	unsigned int mckr, tmp;
- 	int div, i;
-+	int ret;
- 
- 	div = DIV_ROUND_CLOSEST(parent_rate, rate);
- 	if (div > ARRAY_SIZE(characteristics->divisors))
-@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc
- 		return -EINVAL;
- 
- 	spin_lock_irqsave(master->lock, flags);
--	regmap_update_bits(master->regmap, master->layout->offset,
--			   (MASTER_DIV_MASK << MASTER_DIV_SHIFT),
--			   (div << MASTER_DIV_SHIFT));
-+	ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+	if (ret)
-+		goto unlock;
-+
-+	tmp = mckr & master->layout->mask;
-+	tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+	if (tmp == div)
-+		goto unlock;
-+
-+	mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
-+	mckr |= (div << MASTER_DIV_SHIFT);
-+	ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+	if (ret)
-+		goto unlock;
-+
- 	while (!clk_master_ready(master))
- 		cpu_relax();
-+unlock:
- 	spin_unlock_irqrestore(master->lock, flags);
- 
- 	return 0;
-@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate
- 	return 0;
- }
- 
-+static void clk_master_div_restore_context_chg(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+	int ret;
-+
-+	ret = clk_master_div_set_rate(hw, master->pms.rate,
-+				      master->pms.parent_rate);
-+	if (ret)
-+		pr_warn("Failed to restore MCK DIV clock\n");
-+}
-+
- static const struct clk_ops master_div_ops_chg = {
- 	.prepare = clk_master_prepare,
- 	.is_prepared = clk_master_is_prepared,
- 	.recalc_rate = clk_master_div_recalc_rate,
- 	.determine_rate = clk_master_div_determine_rate,
- 	.set_rate = clk_master_div_set_rate,
-+	.save_context = clk_master_div_save_context,
-+	.restore_context = clk_master_div_restore_context_chg,
- };
- 
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
-@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru
- {
- 	struct clk_master *master = to_clk_master(hw);
- 	unsigned long flags;
--	unsigned int pres;
-+	unsigned int pres, mckr, tmp;
-+	int ret;
- 
- 	pres = DIV_ROUND_CLOSEST(parent_rate, rate);
- 	if (pres > MASTER_PRES_MAX)
-@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru
- 		pres = ffs(pres) - 1;
- 
- 	spin_lock_irqsave(master->lock, flags);
--	regmap_update_bits(master->regmap, master->layout->offset,
--			   (MASTER_PRES_MASK << master->layout->pres_shift),
--			   (pres << master->layout->pres_shift));
-+	ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+	if (ret)
-+		goto unlock;
-+
-+	mckr &= master->layout->mask;
-+	tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+	if (pres == tmp)
-+		goto unlock;
-+
-+	mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
-+	mckr |= (pres << master->layout->pres_shift);
-+	ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+	if (ret)
-+		goto unlock;
- 
- 	while (!clk_master_ready(master))
- 		cpu_relax();
-+unlock:
- 	spin_unlock_irqrestore(master->lock, flags);
- 
--	return 0;
-+	return ret;
- }
- 
- static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
-@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str
- 	return mckr & AT91_PMC_CSS;
- }
- 
-+static int clk_master_pres_save_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+	struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+	unsigned long flags;
-+	unsigned int val, pres;
-+
-+	spin_lock_irqsave(master->lock, flags);
-+	regmap_read(master->regmap, master->layout->offset, &val);
-+	spin_unlock_irqrestore(master->lock, flags);
-+
-+	val &= master->layout->mask;
-+	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+		pres = 3;
-+	else
-+		pres = (1 << pres);
-+
-+	master->pms.parent = val & AT91_PMC_CSS;
-+	master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+	master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);
-+
-+	return 0;
-+}
-+
-+static void clk_master_pres_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+	unsigned long flags;
-+	unsigned int val, pres;
-+
-+	spin_lock_irqsave(master->lock, flags);
-+	regmap_read(master->regmap, master->layout->offset, &val);
-+	spin_unlock_irqrestore(master->lock, flags);
-+
-+	val &= master->layout->mask;
-+	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+		pres = 3;
-+	else
-+		pres = (1 << pres);
-+
-+	if (master->pms.rate !=
-+	    DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||
-+	    (master->pms.parent != (val & AT91_PMC_CSS)))
-+		pr_warn("MCKR PRES was not configured properly by firmware!\n");
-+}
-+
-+static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+
-+	clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
-+}
-+
- static const struct clk_ops master_pres_ops = {
- 	.prepare = clk_master_prepare,
- 	.is_prepared = clk_master_is_prepared,
- 	.recalc_rate = clk_master_pres_recalc_rate,
- 	.get_parent = clk_master_pres_get_parent,
-+	.save_context = clk_master_pres_save_context,
-+	.restore_context = clk_master_pres_restore_context,
- };
- 
- static const struct clk_ops master_pres_ops_chg = {
-@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_
- 	.recalc_rate = clk_master_pres_recalc_rate,
- 	.get_parent = clk_master_pres_get_parent,
- 	.set_rate = clk_master_pres_set_rate,
-+	.save_context = clk_master_pres_save_context,
-+	.restore_context = clk_master_pres_restore_context_chg,
- };
- 
- static struct clk_hw * __init
-@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent
- 	return 0;
- }
- 
--static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+static void clk_sama7g5_master_set(struct clk_master *master,
-+				   unsigned int status)
- {
--	struct clk_master *master = to_clk_master(hw);
- 	unsigned long flags;
- 	unsigned int val, cparent;
-+	unsigned int enable = status ? PMC_MCR_EN : 0;
- 
- 	spin_lock_irqsave(master->lock, flags);
- 
- 	regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
- 	regmap_read(master->regmap, PMC_MCR, &val);
- 	regmap_update_bits(master->regmap, PMC_MCR,
--			   PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV |
-+			   enable | PMC_MCR_CSS | PMC_MCR_DIV |
- 			   PMC_MCR_CMD | PMC_MCR_ID_MSK,
--			   PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |
-+			   enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- 			   (master->div << MASTER_DIV_SHIFT) |
- 			   PMC_MCR_CMD | PMC_MCR_ID(master->id));
- 
-@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str
- 		cpu_relax();
- 
- 	spin_unlock_irqrestore(master->lock, flags);
-+}
-+
-+static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+
-+	clk_sama7g5_master_set(master, 1);
- 
- 	return 0;
- }
-@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s
- 	return 0;
- }
- 
-+static int clk_sama7g5_master_save_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+
-+	master->pms.status = clk_sama7g5_master_is_enabled(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_sama7g5_master_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_master *master = to_clk_master(hw);
-+
-+	if (master->pms.status)
-+		clk_sama7g5_master_set(master, master->pms.status);
-+}
-+
- static const struct clk_ops sama7g5_master_ops = {
- 	.enable = clk_sama7g5_master_enable,
- 	.disable = clk_sama7g5_master_disable,
-@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast
- 	.set_rate = clk_sama7g5_master_set_rate,
- 	.get_parent = clk_sama7g5_master_get_parent,
- 	.set_parent = clk_sama7g5_master_set_parent,
-+	.save_context = clk_sama7g5_master_save_context,
-+	.restore_context = clk_sama7g5_master_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-peripheral.c
-+++ b/drivers/clk/at91/clk-peripheral.c
-@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral {
- 	u32 id;
- 	u32 div;
- 	const struct clk_pcr_layout *layout;
-+	struct at91_clk_pms pms;
- 	bool auto_div;
- 	int chg_pid;
- };
-@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi
- 	periph->div = shift;
- }
- 
--static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,
-+				     unsigned int status)
- {
--	struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
- 	unsigned long flags;
-+	unsigned int enable = status ? AT91_PMC_PCR_EN : 0;
- 
- 	if (periph->id < PERIPHERAL_ID_MIN)
- 		return 0;
-@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable(
- 		     (periph->id & periph->layout->pid_mask));
- 	regmap_update_bits(periph->regmap, periph->layout->offset,
- 			   periph->layout->div_mask | periph->layout->cmd |
--			   AT91_PMC_PCR_EN,
-+			   enable,
- 			   field_prep(periph->layout->div_mask, periph->div) |
--			   periph->layout->cmd |
--			   AT91_PMC_PCR_EN);
-+			   periph->layout->cmd | enable);
- 	spin_unlock_irqrestore(periph->lock, flags);
- 
- 	return 0;
- }
- 
-+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+{
-+	struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+	return clk_sam9x5_peripheral_set(periph, 1);
-+}
-+
- static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
- {
- 	struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat
- 	return -EINVAL;
- }
- 
-+static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw)
-+{
-+	struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+	periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+	if (periph->pms.status)
-+		clk_sam9x5_peripheral_set(periph, periph->pms.status);
-+}
-+
- static const struct clk_ops sam9x5_peripheral_ops = {
- 	.enable = clk_sam9x5_peripheral_enable,
- 	.disable = clk_sam9x5_peripheral_disable,
-@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip
- 	.recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- 	.round_rate = clk_sam9x5_peripheral_round_rate,
- 	.set_rate = clk_sam9x5_peripheral_set_rate,
-+	.save_context = clk_sam9x5_peripheral_save_context,
-+	.restore_context = clk_sam9x5_peripheral_restore_context,
- };
- 
- static const struct clk_ops sam9x5_peripheral_chg_ops = {
-@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip
- 	.recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- 	.determine_rate = clk_sam9x5_peripheral_determine_rate,
- 	.set_rate = clk_sam9x5_peripheral_set_rate,
-+	.save_context = clk_sam9x5_peripheral_save_context,
-+	.restore_context = clk_sam9x5_peripheral_restore_context,
- };
- 
- struct clk_hw * __init
-@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru
- 		hw = ERR_PTR(ret);
- 	} else {
- 		clk_sam9x5_peripheral_autodiv(periph);
--		pmc_register_id(id);
- 	}
- 
- 	return hw;
---- a/drivers/clk/at91/clk-pll.c
-+++ b/drivers/clk/at91/clk-pll.c
-@@ -40,6 +40,7 @@ struct clk_pll {
- 	u16 mul;
- 	const struct clk_pll_layout *layout;
- 	const struct clk_pll_characteristics *characteristics;
-+	struct at91_clk_pms pms;
- };
- 
- static inline bool clk_pll_ready(struct regmap *regmap, int id)
-@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h
- 	return 0;
- }
- 
-+static int clk_pll_save_context(struct clk_hw *hw)
-+{
-+	struct clk_pll *pll = to_clk_pll(hw);
-+	struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+	pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+	pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);
-+	pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));
-+
-+	return 0;
-+}
-+
-+static void clk_pll_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_pll *pll = to_clk_pll(hw);
-+	unsigned long calc_rate;
-+	unsigned int pllr, pllr_out, pllr_count;
-+	u8 out = 0;
-+
-+	if (pll->characteristics->out)
-+		out = pll->characteristics->out[pll->range];
-+
-+	regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-+
-+	calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *
-+		     (PLL_MUL(pllr, pll->layout) + 1);
-+	pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT;
-+	pllr_out = (pllr >> PLL_OUT_SHIFT) & out;
-+
-+	if (pll->pms.rate != calc_rate ||
-+	    pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||
-+	    pllr_count != PLL_MAX_COUNT ||
-+	    (out && pllr_out != out))
-+		pr_warn("PLLAR was not configured properly by firmware\n");
-+}
-+
- static const struct clk_ops pll_ops = {
- 	.prepare = clk_pll_prepare,
- 	.unprepare = clk_pll_unprepare,
-@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = {
- 	.recalc_rate = clk_pll_recalc_rate,
- 	.round_rate = clk_pll_round_rate,
- 	.set_rate = clk_pll_set_rate,
-+	.save_context = clk_pll_save_context,
-+	.restore_context = clk_pll_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-programmable.c
-+++ b/drivers/clk/at91/clk-programmable.c
-@@ -24,6 +24,7 @@ struct clk_programmable {
- 	u32 *mux_table;
- 	u8 id;
- 	const struct clk_programmable_layout *layout;
-+	struct at91_clk_pms pms;
- };
- 
- #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
-@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str
- 	return 0;
- }
- 
-+static int clk_programmable_save_context(struct clk_hw *hw)
-+{
-+	struct clk_programmable *prog = to_clk_programmable(hw);
-+	struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+	prog->pms.parent = clk_programmable_get_parent(hw);
-+	prog->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+	prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate);
-+
-+	return 0;
-+}
-+
-+static void clk_programmable_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_programmable *prog = to_clk_programmable(hw);
-+	int ret;
-+
-+	ret = clk_programmable_set_parent(hw, prog->pms.parent);
-+	if (ret)
-+		return;
-+
-+	clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate);
-+}
-+
- static const struct clk_ops programmable_ops = {
- 	.recalc_rate = clk_programmable_recalc_rate,
- 	.determine_rate = clk_programmable_determine_rate,
- 	.get_parent = clk_programmable_get_parent,
- 	.set_parent = clk_programmable_set_parent,
- 	.set_rate = clk_programmable_set_rate,
-+	.save_context = clk_programmable_save_context,
-+	.restore_context = clk_programmable_restore_context,
- };
- 
- struct clk_hw * __init
-@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re
- 	if (ret) {
- 		kfree(prog);
- 		hw = ERR_PTR(ret);
--	} else {
--		pmc_register_pck(id);
- 	}
- 
- 	return hw;
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -38,12 +38,14 @@ struct sam9x60_pll_core {
- 
- struct sam9x60_frac {
- 	struct sam9x60_pll_core core;
-+	struct at91_clk_pms pms;
- 	u32 frac;
- 	u16 mul;
- };
- 
- struct sam9x60_div {
- 	struct sam9x60_pll_core core;
-+	struct at91_clk_pms pms;
- 	u8 div;
- };
- 
-@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re
- 		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
- }
- 
--static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
- {
--	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- 	struct sam9x60_frac *frac = to_sam9x60_frac(core);
- 	struct regmap *regmap = core->regmap;
- 	unsigned int val, cfrac, cmul;
-@@ -141,6 +142,13 @@ unlock:
- 	return 0;
- }
- 
-+static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+	return sam9x60_frac_pll_set(core);
-+}
-+
- static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
- {
- 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -280,6 +288,25 @@ unlock:
- 	return ret;
- }
- 
-+static int sam9x60_frac_pll_save_context(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+	struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+	frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);
-+
-+	return 0;
-+}
-+
-+static void sam9x60_frac_pll_restore_context(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+	struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+	if (frac->pms.status)
-+		sam9x60_frac_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_frac_pll_ops = {
- 	.prepare = sam9x60_frac_pll_prepare,
- 	.unprepare = sam9x60_frac_pll_unprepare,
-@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac
- 	.recalc_rate = sam9x60_frac_pll_recalc_rate,
- 	.round_rate = sam9x60_frac_pll_round_rate,
- 	.set_rate = sam9x60_frac_pll_set_rate,
-+	.save_context = sam9x60_frac_pll_save_context,
-+	.restore_context = sam9x60_frac_pll_restore_context,
- };
- 
- static const struct clk_ops sam9x60_frac_pll_ops_chg = {
-@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac
- 	.recalc_rate = sam9x60_frac_pll_recalc_rate,
- 	.round_rate = sam9x60_frac_pll_round_rate,
- 	.set_rate = sam9x60_frac_pll_set_rate_chg,
-+	.save_context = sam9x60_frac_pll_save_context,
-+	.restore_context = sam9x60_frac_pll_restore_context,
- };
- 
--static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
--	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- 	struct sam9x60_div *div = to_sam9x60_div(core);
- 	struct regmap *regmap = core->regmap;
- 	unsigned long flags;
-@@ -334,6 +364,13 @@ unlock:
- 	return 0;
- }
- 
-+static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+	return sam9x60_div_pll_set(core);
-+}
-+
- static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
- {
- 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -482,6 +519,25 @@ unlock:
- 	return 0;
- }
- 
-+static int sam9x60_div_pll_save_context(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+	struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+	div->pms.status = sam9x60_div_pll_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void sam9x60_div_pll_restore_context(struct clk_hw *hw)
-+{
-+	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+	struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+	if (div->pms.status)
-+		sam9x60_div_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- 	.prepare = sam9x60_div_pll_prepare,
- 	.unprepare = sam9x60_div_pll_unprepare,
-@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_
- 	.recalc_rate = sam9x60_div_pll_recalc_rate,
- 	.round_rate = sam9x60_div_pll_round_rate,
- 	.set_rate = sam9x60_div_pll_set_rate,
-+	.save_context = sam9x60_div_pll_save_context,
-+	.restore_context = sam9x60_div_pll_restore_context,
- };
- 
- static const struct clk_ops sam9x60_div_pll_ops_chg = {
-@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_
- 	.recalc_rate = sam9x60_div_pll_recalc_rate,
- 	.round_rate = sam9x60_div_pll_round_rate,
- 	.set_rate = sam9x60_div_pll_set_rate_chg,
-+	.save_context = sam9x60_div_pll_save_context,
-+	.restore_context = sam9x60_div_pll_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-system.c
-+++ b/drivers/clk/at91/clk-system.c
-@@ -20,6 +20,7 @@
- struct clk_system {
- 	struct clk_hw hw;
- 	struct regmap *regmap;
-+	struct at91_clk_pms pms;
- 	u8 id;
- };
- 
-@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct
- 	return !!(status & (1 << sys->id));
- }
- 
-+static int clk_system_save_context(struct clk_hw *hw)
-+{
-+	struct clk_system *sys = to_clk_system(hw);
-+
-+	sys->pms.status = clk_system_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_system_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_system *sys = to_clk_system(hw);
-+
-+	if (sys->pms.status)
-+		clk_system_prepare(&sys->hw);
-+}
-+
- static const struct clk_ops system_ops = {
- 	.prepare = clk_system_prepare,
- 	.unprepare = clk_system_unprepare,
- 	.is_prepared = clk_system_is_prepared,
-+	.save_context = clk_system_save_context,
-+	.restore_context = clk_system_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-usb.c
-+++ b/drivers/clk/at91/clk-usb.c
-@@ -24,6 +24,7 @@
- struct at91sam9x5_clk_usb {
- 	struct clk_hw hw;
- 	struct regmap *regmap;
-+	struct at91_clk_pms pms;
- 	u32 usbs_mask;
- 	u8 num_parents;
- };
-@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s
- 	return 0;
- }
- 
-+static int at91sam9x5_usb_save_context(struct clk_hw *hw)
-+{
-+	struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+	struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+	usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw);
-+	usb->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+	usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate);
-+
-+	return 0;
-+}
-+
-+static void at91sam9x5_usb_restore_context(struct clk_hw *hw)
-+{
-+	struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+	int ret;
-+
-+	ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent);
-+	if (ret)
-+		return;
-+
-+	at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate);
-+}
-+
- static const struct clk_ops at91sam9x5_usb_ops = {
- 	.recalc_rate = at91sam9x5_clk_usb_recalc_rate,
- 	.determine_rate = at91sam9x5_clk_usb_determine_rate,
- 	.get_parent = at91sam9x5_clk_usb_get_parent,
- 	.set_parent = at91sam9x5_clk_usb_set_parent,
- 	.set_rate = at91sam9x5_clk_usb_set_rate,
-+	.save_context = at91sam9x5_usb_save_context,
-+	.restore_context = at91sam9x5_usb_restore_context,
- };
- 
- static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
---- a/drivers/clk/at91/clk-utmi.c
-+++ b/drivers/clk/at91/clk-utmi.c
-@@ -23,6 +23,7 @@ struct clk_utmi {
- 	struct clk_hw hw;
- 	struct regmap *regmap_pmc;
- 	struct regmap *regmap_sfr;
-+	struct at91_clk_pms pms;
- };
- 
- #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
-@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat
- 	return UTMI_RATE;
- }
- 
-+static int clk_utmi_save_context(struct clk_hw *hw)
-+{
-+	struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+	utmi->pms.status = clk_utmi_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_utmi_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+	if (utmi->pms.status)
-+		clk_utmi_prepare(hw);
-+}
-+
- static const struct clk_ops utmi_ops = {
- 	.prepare = clk_utmi_prepare,
- 	.unprepare = clk_utmi_unprepare,
- 	.is_prepared = clk_utmi_is_prepared,
- 	.recalc_rate = clk_utmi_recalc_rate,
-+	.save_context = clk_utmi_save_context,
-+	.restore_context = clk_utmi_restore_context,
- };
- 
- static struct clk_hw * __init
-@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared(
- 	return 0;
- }
- 
-+static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
-+{
-+	struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+	utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
-+
-+	return 0;
-+}
-+
-+static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
-+{
-+	struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+	if (utmi->pms.status)
-+		clk_utmi_sama7g5_prepare(hw);
-+}
-+
- static const struct clk_ops sama7g5_utmi_ops = {
- 	.prepare = clk_utmi_sama7g5_prepare,
- 	.is_prepared = clk_utmi_sama7g5_is_prepared,
- 	.recalc_rate = clk_utmi_recalc_rate,
-+	.save_context = clk_utmi_sama7g5_save_context,
-+	.restore_context = clk_utmi_sama7g5_restore_context,
- };
- 
- struct clk_hw * __init
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -3,6 +3,7 @@
-  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
-  */
- 
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -14,8 +15,6 @@
- 
- #include <asm/proc-fns.h>
- 
--#include <dt-bindings/clock/at91.h>
--
- #include "pmc.h"
- 
- #define PMC_MAX_IDS 128
-@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig
- }
- 
- #ifdef CONFIG_PM
--static struct regmap *pmcreg;
--
--static u8 registered_ids[PMC_MAX_IDS];
--static u8 registered_pcks[PMC_MAX_PCKS];
--
--static struct
--{
--	u32 scsr;
--	u32 pcsr0;
--	u32 uckr;
--	u32 mor;
--	u32 mcfr;
--	u32 pllar;
--	u32 mckr;
--	u32 usb;
--	u32 imr;
--	u32 pcsr1;
--	u32 pcr[PMC_MAX_IDS];
--	u32 audio_pll0;
--	u32 audio_pll1;
--	u32 pckr[PMC_MAX_PCKS];
--} pmc_cache;
--
--/*
-- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
-- * without alteration in the table, and 0 is for unused clocks.
-- */
--void pmc_register_id(u8 id)
-+static int at91_pmc_suspend(void)
- {
--	int i;
--
--	for (i = 0; i < PMC_MAX_IDS; i++) {
--		if (registered_ids[i] == 0) {
--			registered_ids[i] = id;
--			break;
--		}
--		if (registered_ids[i] == id)
--			break;
--	}
-+	return clk_save_context();
- }
- 
--/*
-- * As Programmable Clock 0 is valid on AT91 chips, there is an offset
-- * of 1 between the stored value and the real clock ID.
-- */
--void pmc_register_pck(u8 pck)
-+static void at91_pmc_resume(void)
- {
--	int i;
--
--	for (i = 0; i < PMC_MAX_PCKS; i++) {
--		if (registered_pcks[i] == 0) {
--			registered_pcks[i] = pck + 1;
--			break;
--		}
--		if (registered_pcks[i] == (pck + 1))
--			break;
--	}
--}
--
--static int pmc_suspend(void)
--{
--	int i;
--	u8 num;
--
--	regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
--	regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
--	regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
--	regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
--	regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
--	regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
--	regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
--	regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
--	regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
--	regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
--
--	for (i = 0; registered_ids[i]; i++) {
--		regmap_write(pmcreg, AT91_PMC_PCR,
--			     (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
--		regmap_read(pmcreg, AT91_PMC_PCR,
--			    &pmc_cache.pcr[registered_ids[i]]);
--	}
--	for (i = 0; registered_pcks[i]; i++) {
--		num = registered_pcks[i] - 1;
--		regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
--	}
--
--	return 0;
--}
--
--static bool pmc_ready(unsigned int mask)
--{
--	unsigned int status;
--
--	regmap_read(pmcreg, AT91_PMC_SR, &status);
--
--	return ((status & mask) == mask) ? 1 : 0;
--}
--
--static void pmc_resume(void)
--{
--	int i;
--	u8 num;
--	u32 tmp;
--	u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
--
--	regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
--	if (pmc_cache.mckr != tmp)
--		pr_warn("MCKR was not configured properly by the firmware\n");
--	regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
--	if (pmc_cache.pllar != tmp)
--		pr_warn("PLLAR was not configured properly by the firmware\n");
--
--	regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
--	regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
--	regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
--	regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
--	regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
--	regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
--	regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
--	regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
--
--	for (i = 0; registered_ids[i]; i++) {
--		regmap_write(pmcreg, AT91_PMC_PCR,
--			     pmc_cache.pcr[registered_ids[i]] |
--			     AT91_PMC_PCR_CMD);
--	}
--	for (i = 0; registered_pcks[i]; i++) {
--		num = registered_pcks[i] - 1;
--		regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
--	}
--
--	if (pmc_cache.uckr & AT91_PMC_UPLLEN)
--		mask |= AT91_PMC_LOCKU;
--
--	while (!pmc_ready(mask))
--		cpu_relax();
-+	clk_restore_context();
- }
- 
- static struct syscore_ops pmc_syscore_ops = {
--	.suspend = pmc_suspend,
--	.resume = pmc_resume,
-+	.suspend = at91_pmc_suspend,
-+	.resume = at91_pmc_resume,
- };
- 
- static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void)
- 		of_node_put(np);
- 		return -ENODEV;
- 	}
--
--	pmcreg = device_node_to_regmap(np);
- 	of_node_put(np);
--	if (IS_ERR(pmcreg))
--		return PTR_ERR(pmcreg);
- 
- 	register_syscore_ops(&pmc_syscore_ops);
- 
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -13,6 +13,8 @@
- #include <linux/regmap.h>
- #include <linux/spinlock.h>
- 
-+#include <dt-bindings/clock/at91.h>
-+
- extern spinlock_t pmc_pcr_lock;
- 
- struct pmc_data {
-@@ -98,6 +100,20 @@ struct clk_pcr_layout {
- 	u32 pid_mask;
- };
- 
-+/**
-+ * struct at91_clk_pms - Power management state for AT91 clock
-+ * @rate: clock rate
-+ * @parent_rate: clock parent rate
-+ * @status: clock status (enabled or disabled)
-+ * @parent: clock parent index
-+ */
-+struct at91_clk_pms {
-+	unsigned long rate;
-+	unsigned long parent_rate;
-+	unsigned int status;
-+	unsigned int parent;
-+};
-+
- #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
- #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
- 
-@@ -248,12 +264,4 @@ struct clk_hw * __init
- at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
- 			       const char *parent_name);
- 
--#ifdef CONFIG_PM
--void pmc_register_id(u8 id);
--void pmc_register_pck(u8 pck);
--#else
--static inline void pmc_register_id(u8 id) {}
--static inline void pmc_register_pck(u8 pck) {}
--#endif
--
- #endif /* __PMC_H_ */
diff --git a/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch b/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch
deleted file mode 100644
index 19f1f6fdf2..0000000000
--- a/target/linux/at91/patches-5.15/101-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:06 +0300
-Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for
- backup mode
-
-Before going to backup mode architecture specific PM code sets the first
-word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).
-Thus take this into account when suspending/resuming clocks. This will
-avoid executing unnecessary instructions when suspending to non backup
-modes.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -8,6 +8,7 @@
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/mfd/syscon.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig
- }
- 
- #ifdef CONFIG_PM
-+
-+/* Address in SECURAM that say if we suspend to backup mode. */
-+static void __iomem *at91_pmc_backup_suspend;
-+
- static int at91_pmc_suspend(void)
- {
-+	unsigned int backup;
-+
-+	if (!at91_pmc_backup_suspend)
-+		return 0;
-+
-+	backup = readl_relaxed(at91_pmc_backup_suspend);
-+	if (!backup)
-+		return 0;
-+
- 	return clk_save_context();
- }
- 
- static void at91_pmc_resume(void)
- {
-+	unsigned int backup;
-+
-+	if (!at91_pmc_backup_suspend)
-+		return;
-+
-+	backup = readl_relaxed(at91_pmc_backup_suspend);
-+	if (!backup)
-+		return;
-+
- 	clk_restore_context();
- }
- 
-@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void)
- 	}
- 	of_node_put(np);
- 
-+	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
-+	if (!np)
-+		return -ENODEV;
-+
-+	if (!of_device_is_available(np)) {
-+		of_node_put(np);
-+		return -ENODEV;
-+	}
-+	of_node_put(np);
-+
-+	at91_pmc_backup_suspend = of_iomap(np, 0);
-+	if (!at91_pmc_backup_suspend) {
-+		pr_warn("%s(): unable to map securam\n", __func__);
-+		return -ENOMEM;
-+	}
-+
- 	register_syscore_ops(&pmc_syscore_ops);
- 
- 	return 0;
diff --git a/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch b/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch
deleted file mode 100644
index 726d9b33e4..0000000000
--- a/target/linux/at91/patches-5.15/102-clk-at91-clk-master-add-register-definition-for-sama.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:08 +0300
-Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
- sama7g5's master clock
-
-SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
-register at offset 0x30 (relative to PMC). In the last/first phase of
-suspend/resume procedure (which is architecture specific) the parent
-of master clocks are changed (via assembly code) for more power saving
-(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
-and at91_mckx_ps_restore). Thus the macros corresponding to register
-at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
-commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
-master clock") introduced the proper macros but didn't adapted the
-clk-master.c as well. Thus, this commit adapt the clk-master.c to use
-the macros introduced in commit ec03f18cc222 ("clk: at91: add register
-definition for sama7g5's master clock").
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -17,15 +17,7 @@
- #define MASTER_DIV_SHIFT	8
- #define MASTER_DIV_MASK		0x7
- 
--#define PMC_MCR			0x30
--#define PMC_MCR_ID_MSK		GENMASK(3, 0)
--#define PMC_MCR_CMD		BIT(7)
--#define PMC_MCR_DIV		GENMASK(10, 8)
--#define PMC_MCR_CSS		GENMASK(20, 16)
- #define PMC_MCR_CSS_SHIFT	(16)
--#define PMC_MCR_EN		BIT(28)
--
--#define PMC_MCR_ID(x)		((x) & PMC_MCR_ID_MSK)
- 
- #define MASTER_MAX_ID		4
- 
-@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc
- {
- 	unsigned long flags;
- 	unsigned int val, cparent;
--	unsigned int enable = status ? PMC_MCR_EN : 0;
-+	unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
- 
- 	spin_lock_irqsave(master->lock, flags);
- 
--	regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
--	regmap_read(master->regmap, PMC_MCR, &val);
--	regmap_update_bits(master->regmap, PMC_MCR,
--			   enable | PMC_MCR_CSS | PMC_MCR_DIV |
--			   PMC_MCR_CMD | PMC_MCR_ID_MSK,
-+	regmap_write(master->regmap, AT91_PMC_MCR_V2,
-+		     AT91_PMC_MCR_V2_ID(master->id));
-+	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+			   enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
-+			   AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
- 			   enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- 			   (master->div << MASTER_DIV_SHIFT) |
--			   PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+			   AT91_PMC_MCR_V2_CMD |
-+			   AT91_PMC_MCR_V2_ID(master->id));
- 
--	cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
-+	cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
- 
- 	/* Wait here only if parent is being changed. */
- 	while ((cparent != master->parent) && !clk_master_ready(master))
-@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s
- 
- 	spin_lock_irqsave(master->lock, flags);
- 
--	regmap_write(master->regmap, PMC_MCR, master->id);
--	regmap_update_bits(master->regmap, PMC_MCR,
--			   PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
--			   PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+			   AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
-+			   AT91_PMC_MCR_V2_ID_MSK,
-+			   AT91_PMC_MCR_V2_CMD |
-+			   AT91_PMC_MCR_V2_ID(master->id));
- 
- 	spin_unlock_irqrestore(master->lock, flags);
- }
-@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled
- 
- 	spin_lock_irqsave(master->lock, flags);
- 
--	regmap_write(master->regmap, PMC_MCR, master->id);
--	regmap_read(master->regmap, PMC_MCR, &val);
-+	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
- 
- 	spin_unlock_irqrestore(master->lock, flags);
- 
--	return !!(val & PMC_MCR_EN);
-+	return !!(val & AT91_PMC_MCR_V2_EN);
- }
- 
- static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct
- 	master->mux_table = mux_table;
- 
- 	spin_lock_irqsave(master->lock, flags);
--	regmap_write(master->regmap, PMC_MCR, master->id);
--	regmap_read(master->regmap, PMC_MCR, &val);
--	master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
--	master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
-+	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+	master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
-+	master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
- 	spin_unlock_irqrestore(master->lock, flags);
- 
- 	hw = &master->hw;
diff --git a/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch b/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch
deleted file mode 100644
index a5b57a67ad..0000000000
--- a/target/linux/at91/patches-5.15/103-clk-at91-clk-master-improve-readability-by-using-loc.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:09 +0300
-Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using
- local variables
-
-Improve readability in clk_sama7g5_master_set() by using local
-variables.
-
-Suggested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc
- 	unsigned long flags;
- 	unsigned int val, cparent;
- 	unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
-+	unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;
-+	unsigned int div = master->div << MASTER_DIV_SHIFT;
- 
- 	spin_lock_irqsave(master->lock, flags);
- 
-@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc
- 	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
- 			   enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
- 			   AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
--			   enable | (master->parent << PMC_MCR_CSS_SHIFT) |
--			   (master->div << MASTER_DIV_SHIFT) |
--			   AT91_PMC_MCR_V2_CMD |
-+			   enable | parent | div | AT91_PMC_MCR_V2_CMD |
- 			   AT91_PMC_MCR_V2_ID(master->id));
- 
- 	cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
diff --git a/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch b/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch
deleted file mode 100644
index 2918de1700..0000000000
--- a/target/linux/at91/patches-5.15/104-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:10 +0300
-Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available
- pmcs
-
-Add SAMA7G5 to the list of available PMCs such that the suspend/resume
-code for clocks to be used on backup mode.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op
- 	.resume = at91_pmc_resume,
- };
- 
--static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-+static const struct of_device_id pmc_dt_ids[] = {
- 	{ .compatible = "atmel,sama5d2-pmc" },
-+	{ .compatible = "microchip,sama7g5-pmc", },
- 	{ /* sentinel */ }
- };
- 
-@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void)
- {
- 	struct device_node *np;
- 
--	np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
-+	np = of_find_matching_node(NULL, pmc_dt_ids);
- 	if (!np)
- 		return -ENODEV;
- 
diff --git a/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch b/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch
deleted file mode 100644
index ea869c9485..0000000000
--- a/target/linux/at91/patches-5.15/105-clk-at91-clk-master-mask-mckr-against-layout-mask.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:13 +0300
-Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask
-
-Mask values read/written from/to MCKR against layout->mask as this
-mask may be different b/w PMC versions.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc
- 	if (ret)
- 		goto unlock;
- 
--	tmp = mckr & master->layout->mask;
--	tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+	mckr &= master->layout->mask;
-+	tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
- 	if (tmp == div)
- 		goto unlock;
- 
-@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec
- 	regmap_read(master->regmap, master->layout->offset, &val);
- 	spin_unlock_irqrestore(master->lock, flags);
- 
-+	val &= master->layout->mask;
- 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- 	if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
- 		pres = 3;
-@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str
- 	regmap_read(master->regmap, master->layout->offset, &mckr);
- 	spin_unlock_irqrestore(master->lock, flags);
- 
-+	mckr &= master->layout->mask;
-+
- 	return mckr & AT91_PMC_CSS;
- }
- 
diff --git a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch b/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch
deleted file mode 100644
index e5ebdc4ea4..0000000000
--- a/target/linux/at91/patches-5.15/106-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch
+++ /dev/null
@@ -1,312 +0,0 @@
-From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:15 +0300
-Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part
- of PLL
-
-SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
-one fractional part and one divider. On SAMA7G5 the CPU PLL could be
-changed at run-time to implement DVFS. The hardware clock tree on
-SAMA7G5 for CPU PLL is as follows:
-
-                       +---- div1 ----------------> cpuck
-                       |
-FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
-
-The div1 block is not implemented in Linux; on prescaler block it has
-been discovered a bug on some scenarios and will be removed from Linux
-in next commits. Thus, the final clock tree that will be used in Linux
-will be as follows:
-
-                       +-----------> cpuck
-                       |
-FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
-
-It has been proposed in [1] to not introduce a new CPUFreq driver but
-to overload the proper clock drivers with proper operation such that
-cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
-clock notifiers which applies safe dividers before FRAC PLL is changed.
-The current commit treats only the DIV PLL by adding a notifier that
-sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
-provided by initialization clock code (sama7g5.c). The div0 is treated
-in next commits (to keep the changes as clean as possible).
-
-[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++-------
- drivers/clk/at91/pmc.h             |   3 +-
- drivers/clk/at91/sam9x60.c         |   6 +-
- drivers/clk/at91/sama7g5.c         |  13 +++-
- 4 files changed, 95 insertions(+), 29 deletions(-)
-
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -5,6 +5,7 @@
-  */
- 
- #include <linux/bitfield.h>
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -47,12 +48,15 @@ struct sam9x60_div {
- 	struct sam9x60_pll_core core;
- 	struct at91_clk_pms pms;
- 	u8 div;
-+	u8 safe_div;
- };
- 
- #define to_sam9x60_pll_core(hw)	container_of(hw, struct sam9x60_pll_core, hw)
- #define to_sam9x60_frac(core)	container_of(core, struct sam9x60_frac, core)
- #define to_sam9x60_div(core)	container_of(core, struct sam9x60_div, core)
- 
-+static struct sam9x60_div *notifier_div;
-+
- static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
- {
- 	unsigned int status;
-@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac
- 	.restore_context = sam9x60_frac_pll_restore_context,
- };
- 
-+/* This function should be called with spinlock acquired. */
-+static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
-+				    bool enable)
-+{
-+	struct regmap *regmap = core->regmap;
-+	u32 ena_msk = enable ? core->layout->endiv_mask : 0;
-+	u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
-+
-+	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-+			   core->layout->div_mask | ena_msk,
-+			   (div << core->layout->div_shift) | ena_val);
-+
-+	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-+			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-+			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
-+
-+	while (!sam9x60_pll_ready(regmap, core->id))
-+		cpu_relax();
-+}
-+
- static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
- 	struct sam9x60_div *div = to_sam9x60_div(core);
-@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa
- 	if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
- 		goto unlock;
- 
--	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
--			   core->layout->div_mask | core->layout->endiv_mask,
--			   (div->div << core->layout->div_shift) |
--			   (1 << core->layout->endiv_shift));
--
--	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
--			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
--			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
--	while (!sam9x60_pll_ready(regmap, core->id))
--		cpu_relax();
-+	sam9x60_div_pll_set_div(core, div->div, 1);
- 
- unlock:
- 	spin_unlock_irqrestore(core->lock, flags);
-@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(
- 	if (cdiv == div->div)
- 		goto unlock;
- 
--	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
--			   core->layout->div_mask,
--			   (div->div << core->layout->div_shift));
--
--	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
--			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
--			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
--	while (!sam9x60_pll_ready(regmap, core->id))
--		cpu_relax();
-+	sam9x60_div_pll_set_div(core, div->div, 0);
- 
- unlock:
- 	spin_unlock_irqrestore(core->lock, irqflags);
-@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont
- 		sam9x60_div_pll_set(core);
- }
- 
-+static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
-+				       unsigned long code, void *data)
-+{
-+	struct sam9x60_div *div = notifier_div;
-+	struct sam9x60_pll_core core = div->core;
-+	struct regmap *regmap = core.regmap;
-+	unsigned long irqflags;
-+	u32 val, cdiv;
-+	int ret = NOTIFY_DONE;
-+
-+	if (code != PRE_RATE_CHANGE)
-+		return ret;
-+
-+	/*
-+	 * We switch to safe divider to avoid overclocking of other domains
-+	 * feed by us while the frac PLL (our parent) is changed.
-+	 */
-+	div->div = div->safe_div;
-+
-+	spin_lock_irqsave(core.lock, irqflags);
-+	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
-+			   core.id);
-+	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
-+	cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
-+
-+	/* Stop if nothing changed. */
-+	if (cdiv == div->safe_div)
-+		goto unlock;
-+
-+	sam9x60_div_pll_set_div(&core, div->div, 0);
-+	ret = NOTIFY_OK;
-+
-+unlock:
-+	spin_unlock_irqrestore(core.lock, irqflags);
-+
-+	return ret;
-+}
-+
-+static struct notifier_block sam9x60_div_pll_notifier = {
-+	.notifier_call = sam9x60_div_pll_notifier_fn,
-+};
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- 	.prepare = sam9x60_div_pll_prepare,
- 	.unprepare = sam9x60_div_pll_unprepare,
-@@ -647,7 +694,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- 			     const char *name, const char *parent_name, u8 id,
- 			     const struct clk_pll_characteristics *characteristics,
--			     const struct clk_pll_layout *layout, u32 flags)
-+			     const struct clk_pll_layout *layout, u32 flags,
-+			     u32 safe_div)
- {
- 	struct sam9x60_div *div;
- 	struct clk_hw *hw;
-@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm
- 	unsigned int val;
- 	int ret;
- 
--	if (id > PLL_MAX_ID || !lock)
-+	/* We only support one changeable PLL. */
-+	if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))
- 		return ERR_PTR(-EINVAL);
- 
-+	if (safe_div >= PLL_DIV_MAX)
-+		safe_div = PLL_DIV_MAX - 1;
-+
- 	div = kzalloc(sizeof(*div), GFP_KERNEL);
- 	if (!div)
- 		return ERR_PTR(-ENOMEM);
-@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm
- 	div->core.layout = layout;
- 	div->core.regmap = regmap;
- 	div->core.lock = lock;
-+	div->safe_div = safe_div;
- 
- 	spin_lock_irqsave(div->core.lock, irqflags);
- 
-@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm
- 	if (ret) {
- 		kfree(div);
- 		hw = ERR_PTR(ret);
-+	} else if (div->safe_div) {
-+		notifier_div = div;
-+		clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);
- 	}
- 
- 	return hw;
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -214,7 +214,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- 			     const char *name, const char *parent_name, u8 id,
- 			     const struct clk_pll_characteristics *characteristics,
--			     const struct clk_pll_layout *layout, u32 flags);
-+			     const struct clk_pll_layout *layout, u32 flags,
-+			     u32 safe_div);
- 
- struct clk_hw * __init
- sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
---- a/drivers/clk/at91/sam9x60.c
-+++ b/drivers/clk/at91/sam9x60.c
-@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str
- 					    * This feeds CPU. It should not
- 					    * be disabled.
- 					    */
--					  CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
-+					  CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
-@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str
- 					  &pll_div_layout,
- 					  CLK_SET_RATE_GATE |
- 					  CLK_SET_PARENT_GATE |
--					  CLK_SET_RATE_PARENT);
-+					  CLK_SET_RATE_PARENT, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
-@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str
- 	hw = at91_clk_register_master_div(regmap, "masterck_div",
- 					  "masterck_pres", &sam9x60_master_layout,
- 					  &mck_characteristics, &mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -127,6 +127,8 @@ static const struct clk_pll_characterist
-  * @t:		clock type
-  * @f:		clock flags
-  * @eid:	export index in sama7g5->chws[] array
-+ * @safe_div:	intermediate divider need to be set on PRE_RATE_CHANGE
-+ *		notification
-  */
- static const struct {
- 	const char *n;
-@@ -136,6 +138,7 @@ static const struct {
- 	unsigned long f;
- 	u8 t;
- 	u8 eid;
-+	u8 safe_div;
- } sama7g5_plls[][PLL_ID_MAX] = {
- 	[PLL_ID_CPU] = {
- 		{ .n = "cpupll_fracck",
-@@ -156,7 +159,12 @@ static const struct {
- 		  .t = PLL_TYPE_DIV,
- 		   /* This feeds CPU. It should not be disabled. */
- 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
--		  .eid = PMC_CPUPLL, },
-+		  .eid = PMC_CPUPLL,
-+		  /*
-+		   * Safe div=15 should be safe even for switching b/w 1GHz and
-+		   * 90MHz (frac pll might go up to 1.2GHz).
-+		   */
-+		  .safe_div = 15, },
- 	},
- 
- 	[PLL_ID_SYS] = {
-@@ -966,7 +974,8 @@ static void __init sama7g5_pmc_setup(str
- 					sama7g5_plls[i][j].p, i,
- 					sama7g5_plls[i][j].c,
- 					sama7g5_plls[i][j].l,
--					sama7g5_plls[i][j].f);
-+					sama7g5_plls[i][j].f,
-+					sama7g5_plls[i][j].safe_div);
- 				break;
- 
- 			default:
diff --git a/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch b/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch
deleted file mode 100644
index 83839e6a74..0000000000
--- a/target/linux/at91/patches-5.15/107-clk-at91-clk-master-add-notifier-for-divider.patch
+++ /dev/null
@@ -1,519 +0,0 @@
-From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:16 +0300
-Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider
-
-SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
-parent with cpuck as seen in the following clock tree:
-
-                       +----------> cpuck
-                       |
-FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
-
-mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
-while changing FRAC PLL or DIV PLL the commit implements a notifier for
-mck0 which applies a safe divider to register (maximum value of the divider
-which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
-overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
-events.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/at91rm9200.c  |   2 +-
- drivers/clk/at91/at91sam9260.c |   2 +-
- drivers/clk/at91/at91sam9g45.c |   2 +-
- drivers/clk/at91/at91sam9n12.c |   2 +-
- drivers/clk/at91/at91sam9rl.c  |   2 +-
- drivers/clk/at91/at91sam9x5.c  |   2 +-
- drivers/clk/at91/clk-master.c  | 244 +++++++++++++++++++++++----------
- drivers/clk/at91/dt-compat.c   |   2 +-
- drivers/clk/at91/pmc.h         |   2 +-
- drivers/clk/at91/sama5d2.c     |   2 +-
- drivers/clk/at91/sama5d3.c     |   2 +-
- drivers/clk/at91/sama5d4.c     |   2 +-
- drivers/clk/at91/sama7g5.c     |   2 +-
- 13 files changed, 186 insertions(+), 82 deletions(-)
-
---- a/drivers/clk/at91/at91rm9200.c
-+++ b/drivers/clk/at91/at91rm9200.c
-@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(
- 					  "masterck_pres",
- 					  &at91rm9200_master_layout,
- 					  &rm9200_mck_characteristics,
--					  &rm9200_mck_lock, CLK_SET_RATE_GATE);
-+					  &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/at91sam9260.c
-+++ b/drivers/clk/at91/at91sam9260.c
-@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup
- 					  &at91rm9200_master_layout,
- 					  data->mck_characteristics,
- 					  &at91sam9260_mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/at91sam9g45.c
-+++ b/drivers/clk/at91/at91sam9g45.c
-@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup
- 					  &at91rm9200_master_layout,
- 					  &mck_characteristics,
- 					  &at91sam9g45_mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/at91sam9n12.c
-+++ b/drivers/clk/at91/at91sam9n12.c
-@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup
- 					  &at91sam9x5_master_layout,
- 					  &mck_characteristics,
- 					  &at91sam9n12_mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/at91sam9rl.c
-+++ b/drivers/clk/at91/at91sam9rl.c
-@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(
- 					  "masterck_pres",
- 					  &at91rm9200_master_layout,
- 					  &sam9rl_mck_characteristics,
--					  &sam9rl_mck_lock, CLK_SET_RATE_GATE);
-+					  &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/at91sam9x5.c
-+++ b/drivers/clk/at91/at91sam9x5.c
-@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(
- 					  "masterck_pres",
- 					  &at91sam9x5_master_layout,
- 					  &mck_characteristics, &mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -5,6 +5,7 @@
- 
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
-+#include <linux/clk.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
- #include <linux/mfd/syscon.h>
-@@ -36,8 +37,12 @@ struct clk_master {
- 	u8 id;
- 	u8 parent;
- 	u8 div;
-+	u32 safe_div;
- };
- 
-+/* MCK div reference to be used by notifier. */
-+static struct clk_master *master_div;
-+
- static inline bool clk_master_ready(struct clk_master *master)
- {
- 	unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
-@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o
- 	.restore_context = clk_master_div_restore_context,
- };
- 
--static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
--				   unsigned long parent_rate)
-+/* This function must be called with lock acquired. */
-+static int clk_master_div_set(struct clk_master *master,
-+			      unsigned long parent_rate, int div)
- {
--	struct clk_master *master = to_clk_master(hw);
- 	const struct clk_master_characteristics *characteristics =
- 						master->characteristics;
--	unsigned long flags;
--	unsigned int mckr, tmp;
--	int div, i;
-+	unsigned long rate = parent_rate;
-+	unsigned int max_div = 0, div_index = 0, max_div_index = 0;
-+	unsigned int i, mckr, tmp;
- 	int ret;
- 
--	div = DIV_ROUND_CLOSEST(parent_rate, rate);
--	if (div > ARRAY_SIZE(characteristics->divisors))
--		return -EINVAL;
--
- 	for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
- 		if (!characteristics->divisors[i])
- 			break;
- 
--		if (div == characteristics->divisors[i]) {
--			div = i;
--			break;
-+		if (div == characteristics->divisors[i])
-+			div_index = i;
-+
-+		if (max_div < characteristics->divisors[i]) {
-+			max_div = characteristics->divisors[i];
-+			max_div_index = i;
- 		}
- 	}
- 
--	if (i == ARRAY_SIZE(characteristics->divisors))
--		return -EINVAL;
-+	if (div > max_div)
-+		div_index = max_div_index;
- 
--	spin_lock_irqsave(master->lock, flags);
- 	ret = regmap_read(master->regmap, master->layout->offset, &mckr);
- 	if (ret)
--		goto unlock;
-+		return ret;
- 
- 	mckr &= master->layout->mask;
- 	tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
--	if (tmp == div)
--		goto unlock;
-+	if (tmp == div_index)
-+		return 0;
-+
-+	rate /= characteristics->divisors[div_index];
-+	if (rate < characteristics->output.min)
-+		pr_warn("master clk div is underclocked");
-+	else if (rate > characteristics->output.max)
-+		pr_warn("master clk div is overclocked");
- 
- 	mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
--	mckr |= (div << MASTER_DIV_SHIFT);
-+	mckr |= (div_index << MASTER_DIV_SHIFT);
- 	ret = regmap_write(master->regmap, master->layout->offset, mckr);
- 	if (ret)
--		goto unlock;
-+		return ret;
- 
- 	while (!clk_master_ready(master))
- 		cpu_relax();
--unlock:
--	spin_unlock_irqrestore(master->lock, flags);
-+
-+	master->div = characteristics->divisors[div_index];
- 
- 	return 0;
- }
- 
--static int clk_master_div_determine_rate(struct clk_hw *hw,
--					 struct clk_rate_request *req)
-+static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
-+						    unsigned long parent_rate)
- {
- 	struct clk_master *master = to_clk_master(hw);
--	const struct clk_master_characteristics *characteristics =
--						master->characteristics;
--	struct clk_hw *parent;
--	unsigned long parent_rate, tmp_rate, best_rate = 0;
--	int i, best_diff = INT_MIN, tmp_diff;
--
--	parent = clk_hw_get_parent(hw);
--	if (!parent)
--		return -EINVAL;
--
--	parent_rate = clk_hw_get_rate(parent);
--	if (!parent_rate)
--		return -EINVAL;
- 
--	for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
--		if (!characteristics->divisors[i])
--			break;
--
--		tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
--						 characteristics->divisors[i]);
--		tmp_diff = abs(tmp_rate - req->rate);
--
--		if (!best_rate || best_diff > tmp_diff) {
--			best_diff = tmp_diff;
--			best_rate = tmp_rate;
--		}
--
--		if (!best_diff)
--			break;
--	}
--
--	req->best_parent_rate = best_rate;
--	req->best_parent_hw = parent;
--	req->rate = best_rate;
--
--	return 0;
-+	return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
- }
- 
- static void clk_master_div_restore_context_chg(struct clk_hw *hw)
- {
- 	struct clk_master *master = to_clk_master(hw);
-+	unsigned long flags;
- 	int ret;
- 
--	ret = clk_master_div_set_rate(hw, master->pms.rate,
--				      master->pms.parent_rate);
-+	spin_lock_irqsave(master->lock, flags);
-+	ret = clk_master_div_set(master, master->pms.parent_rate,
-+				 DIV_ROUND_CLOSEST(master->pms.parent_rate,
-+						   master->pms.rate));
-+	spin_unlock_irqrestore(master->lock, flags);
- 	if (ret)
- 		pr_warn("Failed to restore MCK DIV clock\n");
- }
-@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte
- static const struct clk_ops master_div_ops_chg = {
- 	.prepare = clk_master_prepare,
- 	.is_prepared = clk_master_is_prepared,
--	.recalc_rate = clk_master_div_recalc_rate,
--	.determine_rate = clk_master_div_determine_rate,
--	.set_rate = clk_master_div_set_rate,
-+	.recalc_rate = clk_master_div_recalc_rate_chg,
- 	.save_context = clk_master_div_save_context,
- 	.restore_context = clk_master_div_restore_context_chg,
- };
- 
-+static int clk_master_div_notifier_fn(struct notifier_block *notifier,
-+				      unsigned long code, void *data)
-+{
-+	const struct clk_master_characteristics *characteristics =
-+						master_div->characteristics;
-+	struct clk_notifier_data *cnd = data;
-+	unsigned long flags, new_parent_rate, new_rate;
-+	unsigned int mckr, div, new_div = 0;
-+	int ret, i;
-+	long tmp_diff;
-+	long best_diff = -1;
-+
-+	spin_lock_irqsave(master_div->lock, flags);
-+	switch (code) {
-+	case PRE_RATE_CHANGE:
-+		/*
-+		 * We want to avoid any overclocking of MCK DIV domain. To do
-+		 * this we set a safe divider (the underclocking is not of
-+		 * interest as we can go as low as 32KHz). The relation
-+		 * b/w this clock and its parents are as follows:
-+		 *
-+		 * FRAC PLL -> DIV PLL -> MCK DIV
-+		 *
-+		 * With the proper safe divider we should be good even with FRAC
-+		 * PLL at its maximum value.
-+		 */
-+		ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+				  &mckr);
-+		if (ret) {
-+			ret = NOTIFY_STOP_MASK;
-+			goto unlock;
-+		}
-+
-+		mckr &= master_div->layout->mask;
-+		div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+
-+		/* Switch to safe divider. */
-+		clk_master_div_set(master_div,
-+				   cnd->old_rate * characteristics->divisors[div],
-+				   master_div->safe_div);
-+		break;
-+
-+	case POST_RATE_CHANGE:
-+		/*
-+		 * At this point we want to restore MCK DIV domain to its maximum
-+		 * allowed rate.
-+		 */
-+		ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+				  &mckr);
-+		if (ret) {
-+			ret = NOTIFY_STOP_MASK;
-+			goto unlock;
-+		}
-+
-+		mckr &= master_div->layout->mask;
-+		div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+		new_parent_rate = cnd->new_rate * characteristics->divisors[div];
-+
-+		for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
-+			if (!characteristics->divisors[i])
-+				break;
-+
-+			new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
-+							 characteristics->divisors[i]);
-+
-+			tmp_diff = characteristics->output.max - new_rate;
-+			if (tmp_diff < 0)
-+				continue;
-+
-+			if (best_diff < 0 || best_diff > tmp_diff) {
-+				new_div = characteristics->divisors[i];
-+				best_diff = tmp_diff;
-+			}
-+
-+			if (!tmp_diff)
-+				break;
-+		}
-+
-+		if (!new_div) {
-+			ret = NOTIFY_STOP_MASK;
-+			goto unlock;
-+		}
-+
-+		/* Update the div to preserve MCK DIV clock rate. */
-+		clk_master_div_set(master_div, new_parent_rate,
-+				   new_div);
-+
-+		ret = NOTIFY_OK;
-+		break;
-+
-+	default:
-+		ret = NOTIFY_DONE;
-+		break;
-+	}
-+
-+unlock:
-+	spin_unlock_irqrestore(master_div->lock, flags);
-+
-+	return ret;
-+}
-+
-+static struct notifier_block clk_master_div_notifier = {
-+	.notifier_call = clk_master_div_notifier_fn,
-+};
-+
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
- 					 struct clk_hw *parent,
- 					 unsigned long parent_rate,
-@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct
- 	struct clk_master *master;
- 	struct clk_init_data init;
- 	struct clk_hw *hw;
-+	unsigned int mckr;
-+	unsigned long irqflags;
- 	int ret;
- 
- 	if (!name || !num_parents || !parent_names || !lock)
-@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct
- 	master->chg_pid = chg_pid;
- 	master->lock = lock;
- 
-+	if (ops == &master_div_ops_chg) {
-+		spin_lock_irqsave(master->lock, irqflags);
-+		regmap_read(master->regmap, master->layout->offset, &mckr);
-+		spin_unlock_irqrestore(master->lock, irqflags);
-+
-+		mckr &= layout->mask;
-+		mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+		master->div = characteristics->divisors[mckr];
-+	}
-+
- 	hw = &master->hw;
- 	ret = clk_hw_register(NULL, &master->hw);
- 	if (ret) {
-@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm
- 		const char *name, const char *parent_name,
- 		const struct clk_master_layout *layout,
- 		const struct clk_master_characteristics *characteristics,
--		spinlock_t *lock, u32 flags)
-+		spinlock_t *lock, u32 flags, u32 safe_div)
- {
- 	const struct clk_ops *ops;
-+	struct clk_hw *hw;
- 
- 	if (flags & CLK_SET_RATE_GATE)
- 		ops = &master_div_ops;
- 	else
- 		ops = &master_div_ops_chg;
- 
--	return at91_clk_register_master_internal(regmap, name, 1,
--						 &parent_name, layout,
--						 characteristics, ops,
--						 lock, flags, -EINVAL);
-+	hw = at91_clk_register_master_internal(regmap, name, 1,
-+					       &parent_name, layout,
-+					       characteristics, ops,
-+					       lock, flags, -EINVAL);
-+
-+	if (!IS_ERR(hw) && safe_div) {
-+		master_div = to_clk_master(hw);
-+		master_div->safe_div = safe_div;
-+		clk_notifier_register(hw->clk,
-+				      &clk_master_div_notifier);
-+	}
-+
-+	return hw;
- }
- 
- static unsigned long
---- a/drivers/clk/at91/dt-compat.c
-+++ b/drivers/clk/at91/dt-compat.c
-@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n
- 
- 	hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
- 					  layout, characteristics,
--					  &mck_lock, CLK_SET_RATE_GATE);
-+					  &mck_lock, CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto out_free_characteristics;
- 
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm
- 			     const char *parent_names,
- 			     const struct clk_master_layout *layout,
- 			     const struct clk_master_characteristics *characteristics,
--			     spinlock_t *lock, u32 flags);
-+			     spinlock_t *lock, u32 flags, u32 safe_div);
- 
- struct clk_hw * __init
- at91_clk_sama7g5_register_master(struct regmap *regmap,
---- a/drivers/clk/at91/sama5d2.c
-+++ b/drivers/clk/at91/sama5d2.c
-@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str
- 					  "masterck_pres",
- 					  &at91sam9x5_master_layout,
- 					  &mck_characteristics, &mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/sama5d3.c
-+++ b/drivers/clk/at91/sama5d3.c
-@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str
- 					  "masterck_pres",
- 					  &at91sam9x5_master_layout,
- 					  &mck_characteristics, &mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/sama5d4.c
-+++ b/drivers/clk/at91/sama5d4.c
-@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str
- 					  "masterck_pres",
- 					  &at91sam9x5_master_layout,
- 					  &mck_characteristics, &mck_lock,
--					  CLK_SET_RATE_GATE);
-+					  CLK_SET_RATE_GATE, 0);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str
- 	parent_names[0] = "cpupll_divpmcck";
- 	hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
- 					  &mck0_layout, &mck0_characteristics,
--					  &pmc_mck0_lock, 0);
-+					  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
- 	if (IS_ERR(hw))
- 		goto err_free;
- 
diff --git a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch b/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch
deleted file mode 100644
index 6cdec0add7..0000000000
--- a/target/linux/at91/patches-5.15/108-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:18 +0300
-Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz
-
-MCK0 could go as low as 32KHz. Set this limit.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/sama7g5.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -849,7 +849,7 @@ static const struct {
- 
- /* MCK0 characteristics. */
- static const struct clk_master_characteristics mck0_characteristics = {
--	.output = { .min = 50000000, .max = 200000000 },
-+	.output = { .min = 32768, .max = 200000000 },
- 	.divisors = { 1, 2, 4, 3, 5 },
- 	.have_div3_pres = 1,
- };
diff --git a/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch b/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch
deleted file mode 100644
index 5b69d0cbc1..0000000000
--- a/target/linux/at91/patches-5.15/109-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:19 +0300
-Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get()
-
-In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get()
-will return the cached rate. Thus, use clk_core_get_rate_recalc() which
-takes proper action when clock flags contains CLK_GET_RATE_NOCACHE.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-[sboyd@kernel.org: Grab prepare lock around operation]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/clk.c
-+++ b/drivers/clk/clk.c
-@@ -3145,7 +3145,10 @@ static int clk_rate_get(void *data, u64
- {
- 	struct clk_core *core = data;
- 
--	*val = core->rate;
-+	clk_prepare_lock();
-+	*val = clk_core_get_rate_recalc(core);
-+	clk_prepare_unlock();
-+
- 	return 0;
- }
- 
diff --git a/target/linux/at91/sam9x/config-5.15 b/target/linux/at91/sam9x/config-5.15
deleted file mode 100644
index 34c6d96b1c..0000000000
--- a/target/linux/at91/sam9x/config-5.15
+++ /dev/null
@@ -1,317 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_V4 is not set
-CONFIG_ARCH_MULTI_V4T=y
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_AT91RM9200_WATCHDOG is not set
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-CONFIG_ATMEL_AIC_IRQ=y
-CONFIG_ATMEL_CLOCKSOURCE_PIT=y
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PIT=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_ST=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CPU_32v4T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM920T=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_NO_EFFICIENT_FFS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CRC7=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXT4_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ=128
-CONFIG_HZ_FIXED=128
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-# CONFIG_PINCTRL_AT91PIO4 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SAMA5D4_WATCHDOG=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOC_AT91RM9200=y
-CONFIG_SOC_AT91SAM9=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAM9X60=y
-CONFIG_SOC_SAM_V4_V5=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/at91/sama5/config-5.15 b/target/linux/at91/sama5/config-5.15
deleted file mode 100644
index 47596039c8..0000000000
--- a/target/linux/at91/sama5/config-5.15
+++ /dev/null
@@ -1,493 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AT91_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_AT91_ADC=y
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BATTERY_ACT8945A=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DRM=y
-CONFIG_DRM_ATMEL_HLCDC=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DP_AUX_BUS=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DTC=y
-CONFIG_DVB_CORE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_QT1070=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_ACT8945A=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_NEON is not set
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8865=y
-CONFIG_REGULATOR_ACT8945A=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_AT91SAM9 is not set
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ARM=y
-# CONFIG_SND_AT73C213 is not set
-# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set
-# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set
-CONFIG_SND_ATMEL_SOC=y
-CONFIG_SND_ATMEL_SOC_CLASSD=y
-CONFIG_SND_ATMEL_SOC_DMA=y
-CONFIG_SND_ATMEL_SOC_I2S=y
-CONFIG_SND_ATMEL_SOC_PDC=y
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-CONFIG_SND_ATMEL_SOC_SSC=y
-CONFIG_SND_ATMEL_SOC_SSC_DMA=y
-# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set
-# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set
-CONFIG_SND_ATMEL_SOC_WM8904=y
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
-# CONFIG_SND_MCHP_SOC_SPDIFRX is not set
-# CONFIG_SND_MCHP_SOC_SPDIFTX is not set
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-CONFIG_SND_SOC_MIKROE_PROTO=y
-CONFIG_SND_SOC_WM8731=y
-CONFIG_SND_SOC_WM8904=y
-CONFIG_SND_SPI=y
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_TIMER=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAMA5=y
-CONFIG_SOC_SAMA5D2=y
-CONFIG_SOC_SAMA5D3=y
-CONFIG_SOC_SAMA5D4=y
-# CONFIG_SOC_SAMA7G5 is not set
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SQUASHFS is not set
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TOUCHSCREEN_ATMEL_MXT=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-# CONFIG_USB_PWC is not set
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-# CONFIG_VIDEO_CPIA2 is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/at91/sama7/config-5.15 b/target/linux/at91/sama7/config-5.15
deleted file mode 100644
index 228007b8c3..0000000000
--- a/target/linux/at91/sama7/config-5.15
+++ /dev/null
@@ -1,406 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_PATCH_IDIV is not set
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-# CONFIG_AT91SAM9X_WATCHDOG is not set
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-# CONFIG_ATMEL_EBI is not set
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-# CONFIG_AT_HDMAC is not set
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CAN=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=9
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=256
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-# CONFIG_COMPACTION is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-# CONFIG_CPU_SW_DOMAIN_PAN is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y
-CONFIG_DEBUG_AT91_UART=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/at91.S"
-CONFIG_DEBUG_UART_PHYS=0xe1824200
-CONFIG_DEBUG_UART_VIRT=0xe0824200
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-# CONFIG_EFI_PARTITION is not set
-CONFIG_EXT4_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRACE_PERIOD=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_CONFIGFS=y
-# CONFIG_IIO_HRTIMER_TRIGGER is not set
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SW_TRIGGER=y
-# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCKD=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LSM="N"
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_ATMELMCI is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEON=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NFS_FS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCCARD=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AT91_POWEROFF is not set
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MCP16502=y
-CONFIG_ROOT_NFS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ATMEL_SOC=y
-# CONFIG_SND_ATMEL_SOC_CLASSD is not set
-# CONFIG_SND_ATMEL_SOC_I2S is not set
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_MCHP_SOC_I2S_MCC=y
-CONFIG_SND_MCHP_SOC_SPDIFRX=y
-CONFIG_SND_MCHP_SOC_SPDIFTX=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_MIKROE_PROTO is not set
-CONFIG_SND_SOC_PCM5102A=y
-CONFIG_SND_SOC_SPDIF=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_SAMA5D2 is not set
-# CONFIG_SOC_SAMA5D3 is not set
-# CONFIG_SOC_SAMA5D4 is not set
-CONFIG_SOC_SAMA7=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-# CONFIG_SPI_ATMEL_QUADSPI is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUNRPC=y
-# CONFIG_SWAP is not set
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-# CONFIG_VIDEO_ATMEL_XISC is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/ath79/Makefile b/target/linux/ath79/Makefile
index 3ef4b32c72..821b096772 100644
--- a/target/linux/ath79/Makefile
+++ b/target/linux/ath79/Makefile
@@ -9,6 +9,7 @@ SUBTARGETS:=generic mikrotik nand tiny
 FEATURES:=ramdisk squashfs usbgadget
 
 KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/ath79/config-6.1 b/target/linux/ath79/config-6.1
index f2a6969aa1..87f520228f 100644
--- a/target/linux/ath79/config-6.1
+++ b/target/linux/ath79/config-6.1
@@ -81,7 +81,7 @@ CONFIG_GPIO_74X164=y
 CONFIG_GPIO_ATH79=y
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_GENERIC=y
-# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LATCH_MIKROTIK is not set
 # CONFIG_GPIO_RB91X_KEY is not set
 CONFIG_HARDWARE_WATCHPOINTS=y
 CONFIG_HAS_DMA=y
diff --git a/target/linux/ath79/config-6.6 b/target/linux/ath79/config-6.6
new file mode 100644
index 0000000000..290f5b833e
--- /dev/null
+++ b/target/linux/ath79/config-6.6
@@ -0,0 +1,223 @@
+CONFIG_AG71XX=y
+# CONFIG_AG71XX_DEBUG is not set
+CONFIG_AG71XX_DEBUG_FS=y
+CONFIG_AR8216_PHY=y
+CONFIG_AR8216_PHY_LEDS=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATH79=y
+CONFIG_ATH79_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_ATH79=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_LATCH_MIKROTIK is not set
+# CONFIG_GPIO_RB91X_KEY is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_RESET is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+# CONFIG_MFD_RB4XX_CPLD is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_PARSER_CYBERTAN=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_ELF_FW=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_AR71XX=y
+CONFIG_PCI_AR724X=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_AR7100_USB is not set
+# CONFIG_PHY_AR7200_USB is not set
+# CONFIG_PHY_ATH79_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_RESET_ATH79=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+CONFIG_SERIAL_AR933X_NR_UARTS=2
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_AR934X=y
+CONFIG_SPI_ATH79=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_RB4XX is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
index d2161e4a74..67d954dd14 100644
--- a/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
+++ b/target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts
@@ -147,7 +147,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
index 7219b0dacf..383506bed4 100644
--- a/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
+++ b/target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi
@@ -146,7 +146,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x0050000 0x0010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts
index 5b44505ce2..9682646241 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts
@@ -31,7 +31,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts
index 6b89fcd0ff..fa2f23c181 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndr3700.dts
@@ -31,7 +31,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts
index cf23786ae3..2f519e1157 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndr3800.dts
@@ -32,7 +32,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts b/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts
index 72b169fc76..7d0883507d 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts
@@ -32,7 +32,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts
index 2e141d07e5..bd399c88cd 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts
@@ -31,7 +31,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts
index 83b8f216cc..d73bca0e71 100644
--- a/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts
+++ b/target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts
@@ -32,7 +32,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
index d5ceb8b44a..fe72ad21e8 100644
--- a/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
+++ b/target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts
@@ -146,7 +146,7 @@
 				read-only;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				reg = <0x3f0000 0x10000>;
 				label = "art";
 				read-only;
diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
index bfee490051..b1f8bd3a89 100644
--- a/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
+++ b/target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
@@ -171,7 +171,7 @@
 				openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
index c197a90ec5..3d9ab10322 100644
--- a/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
+++ b/target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
@@ -101,7 +101,7 @@
 				label = "firmware";
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				reg = <0x3f0000 0x10000>;
 				label = "art";
 				read-only;
diff --git a/target/linux/ath79/dts/ar7240_tplink.dtsi b/target/linux/ath79/dts/ar7240_tplink.dtsi
index 17c826c6c0..28e9a96b66 100644
--- a/target/linux/ath79/dts/ar7240_tplink.dtsi
+++ b/target/linux/ath79/dts/ar7240_tplink.dtsi
@@ -99,7 +99,7 @@
 				label = "firmware";
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				reg = <0x3f0000 0x10000>;
 				label = "art";
 				read-only;
diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
index d8baa07111..8550989250 100644
--- a/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
+++ b/target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts
@@ -174,7 +174,7 @@
 				openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts
index 324207656f..aa734966d5 100644
--- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts
+++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts
@@ -31,7 +31,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x10000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts
index fbd3cb8ec8..27c31c3c12 100644
--- a/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts
+++ b/target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts
@@ -31,7 +31,7 @@
 		openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x10000>;
 		read-only;
diff --git a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
index efedf2a31b..77eeedc588 100644
--- a/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
+++ b/target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
@@ -128,7 +128,7 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi b/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi
index 9d4ab231cc..9834bf70c2 100644
--- a/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi
+++ b/target/linux/ath79/dts/ar7242_ubnt_sw.dtsi
@@ -100,7 +100,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				reg = <0x7f0000 0x010000>;
 				label = "art";
 				read-only;
diff --git a/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi
index d9b01e17e3..96018dce5e 100644
--- a/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi
+++ b/target/linux/ath79/dts/ar724x_ubnt_xm.dtsi
@@ -58,7 +58,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
index 77e7925715..a82546c1c1 100644
--- a/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
+++ b/target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi
@@ -134,7 +134,7 @@
 				read-only;
 			};
 
-			art: partition@1fe0000 {
+			partition@1fe0000 {
 				label = "art";
 				reg = <0x1fe0000 0x020000>;
 				read-only;
@@ -144,6 +144,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_11000: calibration@11000 {
+						reg = <0x11000 0x440>;
+					};
+
 					macaddr_art_1120c: macaddr@1120c {
 						reg = <0x1120c 0x6>;
 					};
@@ -248,7 +252,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x11000>;
+	nvmem-cells = <&cal_art_11000>;
+	nvmem-cell-names = "calibration";
 };
 
 &uart {
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
index 1857b2b4a6..ed4ca5297e 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts
@@ -87,16 +87,26 @@
 				};
 			};
 
-			partition@1 {
+			partition@20000 {
 				compatible = "tplink,firmware";
 				label = "firmware";
 				reg = <0x020000 0x3D0000>;
 			};
 
-			art: partition@2 {
+			partition@3f0000 {
 				label = "art";
-				reg = <0x3F0000 0x010000>;
+				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -129,7 +139,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
index 7957c438d6..8958ddd3a8 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
@@ -120,10 +120,20 @@
 				reg = <0x020000 0x7D0000>;
 			};
 
-			art: partition@7F0000 {
+			partition@7f0000 {
 				label = "art";
-				reg = <0x7F0000 0x010000>;
+				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -145,7 +155,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
index e786ad2760..d3f189479a 100644
--- a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
@@ -142,10 +142,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -166,7 +176,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9330_dlink_dir-505.dts b/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
index c5109ff800..c6fc0d97aa 100644
--- a/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
+++ b/target/linux/ath79/dts/ar9330_dlink_dir-505.dts
@@ -104,7 +104,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x10000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
index 088973048d..fe1d3186cf 100644
--- a/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
+++ b/target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
@@ -93,18 +93,18 @@
 				read-only;
 			};
 
-			partition@1 {
+			partition@40000 {
 				label = "u-boot-env";
 				reg = <0x040000 0x010000>;
 			};
 
-			partition@2 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@3 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -117,6 +117,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -147,7 +151,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
index 38704f9169..51a2c8b2af 100644
--- a/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
+++ b/target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi
@@ -122,7 +122,7 @@
 				reg = <0x8c0000 0x700000>;
 			};
 
-			art: partition@fc0000 {
+			partition@fc0000 {
 				label = "ART";
 				reg = <0xfc0000 0x040000>;
 				read-only;
@@ -139,6 +139,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -162,5 +166,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
index 98ef9abcc0..121dcbcb0e 100644
--- a/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
+++ b/target/linux/ath79/dts/ar9330_pqi_air-pen.dts
@@ -85,7 +85,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -99,6 +99,10 @@
 						reg = <0x2 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
@@ -149,7 +153,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
index ebd6d5384f..b4a4e6894d 100644
--- a/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
+++ b/target/linux/ath79/dts/ar9330_ziking_cpe46b.dts
@@ -76,7 +76,7 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -91,6 +91,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -114,5 +118,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
index 73699d9bfa..6c38f54593 100644
--- a/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
+++ b/target/linux/ath79/dts/ar9331_8dev_carambola2.dts
@@ -90,7 +90,7 @@
 				reg = <0x50000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -107,6 +107,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -119,6 +123,7 @@
 
 &eth0 {
 	status = "okay";
+
 	nvmem-cells = <&macaddr_art_0>;
 	nvmem-cell-names = "mac-address";
 
@@ -132,11 +137,14 @@
 
 &eth1 {
 	status = "okay";
+
 	nvmem-cells = <&macaddr_art_6>;
 	nvmem-cell-names = "mac-address";
 };
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&macaddr_art_6>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_arduino_yun.dts b/target/linux/ath79/dts/ar9331_arduino_yun.dts
index c866889ce4..bb2a42612f 100644
--- a/target/linux/ath79/dts/ar9331_arduino_yun.dts
+++ b/target/linux/ath79/dts/ar9331_arduino_yun.dts
@@ -171,10 +171,20 @@
 				reg = <0xfe0000 0x10000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -193,5 +203,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
index ee90617160..0616228193 100644
--- a/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
+++ b/target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
@@ -72,18 +72,18 @@
 				read-only;
 			};
 
-			partition@1 {
+			partition@40000 {
 				label = "u-boot-env";
 				reg = <0x040000 0x010000>;
 			};
 
-			partition@2 {
+			partition@50000 {
 				compatible = "denx,uimage";
 				label = "firmware";
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@3 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -93,6 +93,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						compatible = "mac-base";
 						reg = <0x1002 0x6>;
@@ -118,5 +122,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_etactica_eg200.dts b/target/linux/ath79/dts/ar9331_etactica_eg200.dts
index ad3b88ab2b..a887056d73 100644
--- a/target/linux/ath79/dts/ar9331_etactica_eg200.dts
+++ b/target/linux/ath79/dts/ar9331_etactica_eg200.dts
@@ -108,7 +108,7 @@
 				reg = <0x50000 0xfa0000>;
 			};
 
-			art: art@ff0000 {
+			art@ff0000 {
 				reg = <0xff0000 0x10000>;
 				read-only;
 
@@ -120,6 +120,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -128,5 +132,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_glinet_6408.dts b/target/linux/ath79/dts/ar9331_glinet_6408.dts
index eae6be3004..ef800a6ce4 100644
--- a/target/linux/ath79/dts/ar9331_glinet_6408.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_6408.dts
@@ -46,10 +46,20 @@
 				label = "firmware";
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				reg = <0x7f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -66,8 +76,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_glinet_6416.dts b/target/linux/ath79/dts/ar9331_glinet_6416.dts
index 62d0acbf5d..02c3372d3c 100644
--- a/target/linux/ath79/dts/ar9331_glinet_6416.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_6416.dts
@@ -46,10 +46,20 @@
 				label = "firmware";
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				reg = <0xff0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -66,8 +76,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
index 37418bfc4a..067d760b04 100644
--- a/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts
@@ -113,7 +113,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -126,6 +126,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -156,5 +160,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
index e9b1c18924..f440d63b16 100644
--- a/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
+++ b/target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts
@@ -107,7 +107,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -120,6 +120,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -129,5 +133,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts b/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts
index 5701dff64c..a2b6edbd5e 100644
--- a/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts
+++ b/target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts
@@ -98,7 +98,7 @@
 				compatible = "tplink,firmware";
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -111,6 +111,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -128,5 +132,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
index 5d0c02a649..10b6051c3b 100644
--- a/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
+++ b/target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts
@@ -109,10 +109,20 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				reg = <0xff0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -152,8 +162,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
 
-	nvmem-cells = <&macaddr_bdinfo_18a 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_bdinfo_18a 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_onion_omega.dts b/target/linux/ath79/dts/ar9331_onion_omega.dts
index 5d9e96e048..c13a33fb6c 100644
--- a/target/linux/ath79/dts/ar9331_onion_omega.dts
+++ b/target/linux/ath79/dts/ar9331_onion_omega.dts
@@ -119,10 +119,20 @@
 				reg = <0x020000 0xfd0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -131,8 +141,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts b/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts
index 4868ba2fa0..a06ec37348 100644
--- a/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts
+++ b/target/linux/ath79/dts/ar9331_pisen_ts-d084.dts
@@ -73,10 +73,20 @@
 				label = "firmware";
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				reg = <0x7f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -112,7 +122,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts b/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts
index 63f394a4f9..dd3269db8b 100644
--- a/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts
+++ b/target/linux/ath79/dts/ar9331_pisen_wmm003n.dts
@@ -81,10 +81,20 @@
 				label = "firmware";
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				reg = <0x7f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -121,7 +131,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
index 054ccea522..c2c54b4662 100644
--- a/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
+++ b/target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts
@@ -160,10 +160,20 @@
 				};
 			};
 
-			art: partition@30000 {
+			partition@30000 {
 				label = "art";
 				reg = <0x30000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 
 			partition@40000 {
@@ -203,7 +213,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_config_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_config_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
index 0a965c2fa9..551782daa8 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
@@ -141,10 +141,20 @@
 				read-only;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -172,7 +182,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
index df39577110..592e8596e3 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
@@ -129,10 +129,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -160,7 +170,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi
index a8608a77e1..6c702a7eb3 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi
@@ -78,10 +78,20 @@
 				label = "firmware";
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				reg = <0x3f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -120,7 +130,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi
index d1336e9689..ca449338f7 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi
@@ -45,10 +45,20 @@
 				label = "firmware";
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				reg = <0x7f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -65,8 +75,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
index 04537fd33a..b1b6577ae2 100644
--- a/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
+++ b/target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi
@@ -124,10 +124,20 @@
 				label = "firmware";
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				reg = <0x3f0000 0x10000>;
 				label = "art";
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -157,7 +167,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
index 30f42862b2..69dd46f0c7 100644
--- a/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
+++ b/target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts
@@ -56,7 +56,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &art {
@@ -68,5 +69,9 @@
 		macaddr_art_0: macaddr@0 {
 			reg = <0x0 0x6>;
 		};
+
+		cal_art_1000: calibration@1000 {
+			reg = <0x1000 0x440>;
+		};
 	};
 };
diff --git a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
index 1b90deace5..0e455ab982 100644
--- a/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
+++ b/target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts
@@ -87,7 +87,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &art {
@@ -99,5 +100,9 @@
 		macaddr_art_0: macaddr@0 {
 			reg = <0x0 0x6>;
 		};
+
+		cal_art_1000: calibration@1000 {
+			reg = <0x1000 0x440>;
+		};
 	};
 };
diff --git a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
index d41dcaa328..885e8bb420 100644
--- a/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
+++ b/target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi
@@ -132,7 +132,7 @@
 				reg = <0x8c0000 0x700000>;
 			};
 
-			art: partition@fc0000 {
+			partition@fc0000 {
 				label = "ART";
 				reg = <0xfc0000 0x040000>;
 				read-only;
@@ -149,6 +149,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -172,5 +176,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
index 1011ab4980..bc75391dc6 100644
--- a/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
+++ b/target/linux/ath79/dts/ar9341_pcs_cr3000.dts
@@ -118,7 +118,7 @@
 				reg = <0x050000 0x07a0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -133,6 +133,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -142,7 +146,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &eth0 {
diff --git a/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts b/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts
index 496d6579e7..cb0fe378a4 100644
--- a/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts
+++ b/target/linux/ath79/dts/ar9341_pisen_wmb001n.dts
@@ -176,7 +176,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
@@ -189,6 +189,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -222,5 +226,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
index 5a5e785d92..16d2087372 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts
@@ -87,10 +87,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -115,8 +125,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi b/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi
index 71e2c7b8d8..93f3a48f05 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi
@@ -50,10 +50,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -81,7 +91,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts
index 417461a595..f743bcf3ec 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts
@@ -67,10 +67,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -87,8 +97,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
index 3efd824246..c13c03d14b 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts
@@ -88,10 +88,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -118,8 +128,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts
index 180504523c..ad4a85b8cb 100644
--- a/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts
+++ b/target/linux/ath79/dts/ar9341_tplink_tl-wr941nd-v5.dts
@@ -77,10 +77,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -97,8 +107,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
index 5f9d8e42fb..0c98a6634e 100644
--- a/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
+++ b/target/linux/ath79/dts/ar9342_mikrotik_routerboard-911g.dtsi
@@ -22,7 +22,7 @@
 	};
 
 	gpio_latch: gpio_latch {
-		compatible = "gpio-latch";
+		compatible = "gpio-latch-mikrotik";
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpios = <&gpio 0 GPIO_ACTIVE_HIGH>,
diff --git a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
index 779b3b681f..ed85c79b5e 100644
--- a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
+++ b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
@@ -73,7 +73,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -87,6 +87,10 @@
 						reg = <0x0 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -99,6 +103,8 @@
 &wmac {
 	status = "okay";
 
-	ieee80211-freq-limit = <2402000 2482000>;
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
+
+	ieee80211-freq-limit = <2402000 2482001>;
 };
diff --git a/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi b/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi
index cd39410be5..385eb95638 100644
--- a/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi
+++ b/target/linux/ath79/dts/ar9342_ubnt_xw.dtsi
@@ -62,7 +62,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi
index b30d545fa3..b6c1a4c02b 100644
--- a/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi
+++ b/target/linux/ath79/dts/ar9342_zyxel_nwa11xx.dtsi
@@ -111,7 +111,7 @@
 				};
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
index 6bfa82356b..0db71ea765 100644
--- a/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
+++ b/target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts
@@ -100,7 +100,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -117,6 +117,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -149,11 +153,14 @@
 
 &eth1 {
 	status = "okay";
+
 	nvmem-cells = <&macaddr_art_6>;
 	nvmem-cell-names = "mac-address";
 };
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
index 8a354dfe37..57b93e6310 100644
--- a/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
+++ b/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
@@ -98,10 +98,20 @@
 				compatible = "denx,uimage";
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -122,7 +132,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &mdio0 {
diff --git a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
index e503be08ce..3043155261 100644
--- a/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
+++ b/target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi
@@ -114,7 +114,7 @@
 				reg = <0x70000 0xf80000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
@@ -124,6 +124,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						compatible = "mac-base";
 						reg = <0x1002 0x6>;
@@ -158,7 +162,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pcie {
diff --git a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi
index 96235dbbc4..3c718f5c6e 100644
--- a/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi
+++ b/target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi
@@ -135,7 +135,7 @@
 				};
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts b/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
index 01b1053142..d67e9f2a52 100644
--- a/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
+++ b/target/linux/ath79/dts/ar9344_moxa_awk-1137c.dts
@@ -153,7 +153,7 @@
 				read-only;
 			};
 
-			art: partition@fe0000 {
+			partition@fe0000 {
 				label = "art";
 				reg = <0xfe0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
index 739ba583a8..d1ce727489 100644
--- a/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
+++ b/target/linux/ath79/dts/ar9344_openmesh_om5p.dts
@@ -135,7 +135,7 @@
 				reg = <0x850000 0x7a0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "ART";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -152,6 +152,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -177,5 +181,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9344_pcs_cap324.dts b/target/linux/ath79/dts/ar9344_pcs_cap324.dts
index f7f3ef06c9..e03d0593ba 100644
--- a/target/linux/ath79/dts/ar9344_pcs_cap324.dts
+++ b/target/linux/ath79/dts/ar9344_pcs_cap324.dts
@@ -110,7 +110,7 @@
 				reg = <0x050000 0x0fa0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -125,6 +125,14 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x440>;
+					};
 				};
 			};
 		};
@@ -137,10 +145,8 @@
 	ath9k: wifi@0,0 {
 		compatible = "168c,0030";
 		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&macaddr_art_0 (-2)>;
-		nvmem-cell-names = "mac-address";
-		mtd-cal-data = <&art 0x5000>;
-		qca,no-eeprom;
+		nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_5000>;
+		nvmem-cell-names = "mac-address", "calibration";
 		ieee80211-freq-limit = <2402000 2482000>;
 		#gpio-cells = <2>;
 		gpio-controller;
@@ -151,9 +157,8 @@
 	status = "okay";
 
 	ieee80211-freq-limit = <4900000 5990000>;
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 (-1)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 (-1)>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &mdio0 {
diff --git a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
index 6f35bd2c1e..972febe2fd 100644
--- a/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
+++ b/target/linux/ath79/dts/ar9344_pcs_cr5000.dts
@@ -99,7 +99,7 @@
 				reg = <0x050000 0x07a0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -113,6 +113,10 @@
 						reg = <0x0 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_5002: macaddr@5002 {
 						reg = <0x5002 0x6>;
 					};
@@ -218,5 +222,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
index df8f28c7d7..4707b754a3 100644
--- a/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
+++ b/target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi
@@ -101,10 +101,20 @@
 				};
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
-				reg = <0x060000 0x010000>;
+				reg = <0x60000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -117,5 +127,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9344_samsung_wam250.dts b/target/linux/ath79/dts/ar9344_samsung_wam250.dts
index da8c9ac165..6b66dbe0d4 100644
--- a/target/linux/ath79/dts/ar9344_samsung_wam250.dts
+++ b/target/linux/ath79/dts/ar9344_samsung_wam250.dts
@@ -136,7 +136,7 @@
 				reg = <0x070000 0xf80000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -146,6 +146,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						compatible = "mac-base";
 						reg = <0x1002 0x6>;
@@ -169,5 +173,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi
index 64959c9dc2..94e19a929c 100644
--- a/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi
+++ b/target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi
@@ -93,10 +93,20 @@
 				};
 			};
 
-			art: partition@30000 {
+			partition@30000 {
 				label = "art";
 				reg = <0x30000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 
 			partition@40000 {
@@ -155,9 +165,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_config_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_config_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pinmux {
diff --git a/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi b/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi
index f15c1c320a..b65b284979 100644
--- a/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi
+++ b/target/linux/ath79/dts/ar9344_tplink_cpe.dtsi
@@ -81,10 +81,20 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -93,9 +103,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &eth0 {
diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi
index 7f49b9bde7..94bfef57f6 100644
--- a/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi
+++ b/target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi
@@ -103,7 +103,7 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
index 456efc8b75..875406a425 100644
--- a/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
+++ b/target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts
@@ -119,10 +119,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -147,10 +157,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &eth0 {
diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-nxxx.dtsi b/target/linux/ath79/dts/ar9344_wd_mynet-nxxx.dtsi
index 73e2c2566f..ebcf249b5d 100644
--- a/target/linux/ath79/dts/ar9344_wd_mynet-nxxx.dtsi
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-nxxx.dtsi
@@ -58,7 +58,7 @@
 				reg = <0x070000 0xf80000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
index 1b531aa035..67ff1c9d07 100644
--- a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
@@ -114,7 +114,7 @@
 				reg = <0x7e0000 0x10000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
index 36802a5275..b0002e455f 100644
--- a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
+++ b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
@@ -130,7 +130,8 @@
 				reg = <0x50000 0xfa0000>;
 			};
 
-			art: art@ff0000 {
+			art@ff0000 {
+				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
 
@@ -146,6 +147,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -154,7 +159,9 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pinmux {
diff --git a/target/linux/ath79/dts/ath79.dtsi b/target/linux/ath79/dts/ath79.dtsi
index 89d9058414..8849d729ac 100644
--- a/target/linux/ath79/dts/ath79.dtsi
+++ b/target/linux/ath79/dts/ath79.dtsi
@@ -52,6 +52,7 @@
 
 			interrupts = <4>;
 			phy-mode = "mii";
+			syscon-no-reset;
 
 			mdio0: mdio {
 				status = "disabled";
@@ -75,6 +76,7 @@
 
 			interrupts = <5>;
 			phy-mode = "mii";
+			syscon-no-reset;
 
 			mdio1: mdio {
 				status = "disabled";
diff --git a/target/linux/ath79/dts/qca9531_8dev_carambola3.dts b/target/linux/ath79/dts/qca9531_8dev_carambola3.dts
new file mode 100644
index 0000000000..a1149aeaeb
--- /dev/null
+++ b/target/linux/ath79/dts/qca9531_8dev_carambola3.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca953x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "8dev,carambola3", "qca,qca9531";
+	model = "8devices Carambola3";
+
+	aliases {
+		label-mac-device = &wmac;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		lan {
+			label = "green:lan";
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan {
+			label = "green:wan";
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+
+	dr_mode = "host";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&spi {
+	status = "okay";
+
+	/* Winbond W25Q256 SPI flash */
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <45000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x000000 0x040000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x040000 0x040000>;
+			};
+
+			partition@80000 {
+				label = "art";
+				reg = <0x080000 0x040000>;
+				read-only;
+
+				nvmem-layout {
+			     		compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_art_0: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+
+					macaddr_art_6: macaddr@6 {
+						reg = <0x6 0x6>;
+					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
+			};
+
+			partition@c0000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x0c0000 0xf40000>;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&swphy0>;
+
+	nvmem-cells = <&macaddr_art_6>;
+	nvmem-cell-names = "mac-address";
+
+	gmac-config {
+		device = <&gmac>;
+
+		switch-phy-addr-swap = <1>;
+		switch-phy-swap = <1>;
+	};
+};
+
+&eth1 {
+	nvmem-cells = <&macaddr_art_0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
+};
diff --git a/target/linux/ath79/dts/qca9531_8dev_lima.dts b/target/linux/ath79/dts/qca9531_8dev_lima.dts
index 19097d7183..884d1a588e 100644
--- a/target/linux/ath79/dts/qca9531_8dev_lima.dts
+++ b/target/linux/ath79/dts/qca9531_8dev_lima.dts
@@ -63,7 +63,7 @@
 				reg = <0x040000 0x040000>;
 			};
 
-			art: partition@80000 {
+			partition@80000 {
 				label = "art";
 				reg = <0x080000 0x040000>;
 				read-only;
@@ -80,6 +80,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -120,5 +124,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts b/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
index 9c801d8b60..c68b49d6c2 100644
--- a/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
+++ b/target/linux/ath79/dts/qca9531_alcatel_hh40v.dts
@@ -119,7 +119,7 @@
 				reg = <0x150000 0xea0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
index e24ef54112..b40b1406a3 100644
--- a/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
+++ b/target/linux/ath79/dts/qca9531_asus_rp-ac51.dts
@@ -103,7 +103,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
index 1c96bd9a6a..2d0ad0af33 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts
@@ -93,7 +93,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -106,6 +106,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -143,7 +147,6 @@
 &wmac {
 	status = "okay";
 
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&macaddr_art_0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
index 08a0a99c2b..e18f162396 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts
@@ -93,7 +93,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
index 9a616921e5..5af98bf46b 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts
@@ -108,7 +108,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -125,6 +125,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -165,5 +169,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
index ec99ee0c4f..2cf35b0820 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e5.dts
@@ -92,7 +92,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -109,6 +109,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -144,7 +148,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pinmux {
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
index 535676aab2..19256aa10d 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts
@@ -118,6 +118,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -181,7 +185,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 10>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 10>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-ew71-v2.dts b/target/linux/ath79/dts/qca9531_comfast_cf-ew71-v2.dts
index 05873f173d..2277646500 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-ew71-v2.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-ew71-v2.dts
@@ -87,7 +87,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -102,6 +102,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -137,7 +141,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 3>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 3>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
index 5f9240d6c1..e5eac04138 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts
@@ -94,7 +94,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -110,6 +110,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -148,7 +152,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 3>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 3>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
index d13e4966ae..b3df965670 100644
--- a/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
+++ b/target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts
@@ -108,6 +108,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -145,8 +149,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_art_0 10>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 10>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_compex_wpj531-16m.dts b/target/linux/ath79/dts/qca9531_compex_wpj531-16m.dts
index 7a8f6edcee..5506da5125 100644
--- a/target/linux/ath79/dts/qca9531_compex_wpj531-16m.dts
+++ b/target/linux/ath79/dts/qca9531_compex_wpj531-16m.dts
@@ -105,10 +105,20 @@
 				compatible = "denx,uimage";
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -131,7 +141,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts b/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
index 8f2027f250..198b08c56e 100644
--- a/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
+++ b/target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts
@@ -109,10 +109,20 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x10000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 
 			partition@20000 {
@@ -163,5 +173,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
index 29886a4d3e..5a88731e66 100644
--- a/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
+++ b/target/linux/ath79/dts/qca9531_engenius_ews511ap.dts
@@ -117,7 +117,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -127,6 +127,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -151,5 +155,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
index 461392660f..3084baa1e6 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi
@@ -114,7 +114,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -129,6 +129,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -181,7 +185,9 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pinmux {
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
index b6a37754fa..4d809b922a 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
@@ -112,7 +112,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -128,6 +128,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -160,5 +164,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-e750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-e750.dts
index e0c65b7f1b..ba12915570 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-e750.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-e750.dts
@@ -79,7 +79,7 @@
 				reg = <0x40000 0x10000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x50000 0x10000>;
 				read-only;
@@ -92,6 +92,10 @@
 					macaddr_art_0: macaddr@0 {
 						reg = <0x0 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -141,5 +145,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi b/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi
index 114ad46135..f6ff4f3a10 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-s200.dtsi
@@ -131,7 +131,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -192,6 +192,7 @@
 
 &wmac {
 	status = "okay";
+
 	nvmem-cells = <&calibration_art_1000>;
 	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
index 75a8dca7d2..5135155472 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts
@@ -106,7 +106,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -121,6 +121,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -151,5 +155,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
index 106d81ff11..6d1674caf3 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-x750.dts
@@ -101,7 +101,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -117,6 +117,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -149,5 +153,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
index 2e7137bc3a..ae80e30000 100644
--- a/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
+++ b/target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts
@@ -108,7 +108,7 @@
 				reg = <0x40000 0x10000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x50000 0x10000>;
 				read-only;
@@ -123,6 +123,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -173,5 +177,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
index d4e35c84b3..b9d991217b 100644
--- a/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
+++ b/target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts
@@ -111,6 +111,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -148,5 +152,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
index ddc3e0f3c6..a376a93046 100644
--- a/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
+++ b/target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi
@@ -107,10 +107,20 @@
 				};
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
 				reg = <0x060000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -133,5 +143,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_telco_t1.dts b/target/linux/ath79/dts/qca9531_telco_t1.dts
index 543fad3c4f..1cb40b3aae 100644
--- a/target/linux/ath79/dts/qca9531_telco_t1.dts
+++ b/target/linux/ath79/dts/qca9531_telco_t1.dts
@@ -96,7 +96,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -113,6 +113,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -148,7 +152,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pinmux {
diff --git a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
index fa17cd3ce3..0daabc69a7 100644
--- a/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts
@@ -124,7 +124,7 @@
 				read-only;
 			};
 
-			romfile: partition@7d0000 {
+			partition@7d0000 {
 				label = "romfile";
 				reg = <0x7d0000 0x010000>;
 				read-only;
@@ -148,7 +148,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -158,6 +158,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -184,9 +188,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_romfile_f100 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_romfile_f100 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
index be1dc66aff..b46dbc98c2 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts
@@ -174,10 +174,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -200,9 +210,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &usb0 {
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts b/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
index fb9fb12b6b..0d8654b18c 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts
@@ -132,10 +132,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -158,9 +168,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &usb0 {
diff --git a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
index 676f8adf1f..ff1cff9384 100644
--- a/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
+++ b/target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts
@@ -126,7 +126,7 @@
 				reg = <0x020000 0x730000>;
 			};
 
-			info: partition@750000 {
+			partition@750000 {
 				label = "info";
 				reg = <0x750000 0x010000>;
 				read-only;
@@ -150,7 +150,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -160,6 +160,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -185,9 +189,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9531_wallys_dr531.dts b/target/linux/ath79/dts/qca9531_wallys_dr531.dts
index 9e90f99728..d16c82666e 100644
--- a/target/linux/ath79/dts/qca9531_wallys_dr531.dts
+++ b/target/linux/ath79/dts/qca9531_wallys_dr531.dts
@@ -147,10 +147,20 @@
 				reg = <0x050000 0x7a0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -167,5 +177,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9531_yuncore_a770.dts b/target/linux/ath79/dts/qca9531_yuncore_a770.dts
index 4ad19fe600..203a192f16 100644
--- a/target/linux/ath79/dts/qca9531_yuncore_a770.dts
+++ b/target/linux/ath79/dts/qca9531_yuncore_a770.dts
@@ -88,7 +88,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -106,6 +106,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -143,5 +147,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts b/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
index e4b6f5fc68..8331ec7247 100644
--- a/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
+++ b/target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts
@@ -112,7 +112,7 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -130,6 +130,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					macaddr_art_1002: macaddr@1002 {
 						reg = <0x1002 0x6>;
 					};
@@ -172,7 +176,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_6>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi b/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
index d5609f7af1..0364cf2cd7 100644
--- a/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
+++ b/target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi
@@ -86,10 +86,20 @@
 				read-only;
 			};
 
-			art: partition@10000 {
+			partition@10000 {
 				label = "art";
 				reg = <0x10000 0x10000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 
 			partition@20000 {
@@ -120,5 +130,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi b/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
index c78f52152d..bd43ccad79 100644
--- a/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
+++ b/target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi
@@ -122,7 +122,7 @@
 				reg = <0x8c0000 0x700000>;
 			};
 
-			art: partition@fc0000 {
+			partition@fc0000 {
 				label = "ART";
 				reg = <0xfc0000 0x040000>;
 				read-only;
@@ -141,6 +141,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -169,7 +173,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi b/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
index 010b752995..07edeed806 100644
--- a/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
+++ b/target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi
@@ -104,7 +104,7 @@
 				reg = <0x8c0000 0x700000>;
 			};
 
-			art: partition@fc0000 {
+			partition@fc0000 {
 				label = "ART";
 				reg = <0xfc0000 0x040000>;
 				read-only;
@@ -119,6 +119,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -147,7 +151,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_qca_ap143-16m.dts b/target/linux/ath79/dts/qca9533_qca_ap143-16m.dts
index ce59e8a54b..c227d679e6 100644
--- a/target/linux/ath79/dts/qca9533_qca_ap143-16m.dts
+++ b/target/linux/ath79/dts/qca9533_qca_ap143-16m.dts
@@ -41,7 +41,7 @@
 		reg = <0xe90000 0x160000>;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -58,6 +58,10 @@
 			macaddr_art_6: macaddr@6 {
 				reg = <0x6 0x6>;
 			};
+
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
 		};
 	};
 };
@@ -73,5 +77,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_qca_ap143-8m.dts b/target/linux/ath79/dts/qca9533_qca_ap143-8m.dts
index f04885e47d..5a6977efdc 100644
--- a/target/linux/ath79/dts/qca9533_qca_ap143-8m.dts
+++ b/target/linux/ath79/dts/qca9533_qca_ap143-8m.dts
@@ -41,7 +41,7 @@
 		reg = <0x690000 0x160000>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -58,6 +58,10 @@
 			macaddr_art_6: macaddr@6 {
 				reg = <0x6 0x6>;
 			};
+
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
 		};
 	};
 };
@@ -73,5 +77,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_cpexxx.dtsi b/target/linux/ath79/dts/qca9533_tplink_cpexxx.dtsi
index f17dd513e2..d3b323e8c5 100644
--- a/target/linux/ath79/dts/qca9533_tplink_cpexxx.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_cpexxx.dtsi
@@ -102,10 +102,20 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -123,7 +133,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
index 7bad615a6c..377c37cc20 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi
@@ -101,10 +101,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -126,7 +136,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
index f1cdde13a2..bec3a47aa0 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts
@@ -147,10 +147,20 @@
 				read-only;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -172,7 +182,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr802n.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wr802n.dtsi
index b2d525acb7..0a585c0d73 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr802n.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr802n.dtsi
@@ -71,10 +71,20 @@
 				compatible = "tplink,firmware";
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -96,7 +106,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi b/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
index 9487e67e99..29633865b6 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi
@@ -109,10 +109,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -135,7 +145,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
index d6768e1af2..c931e62607 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts
@@ -134,10 +134,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -160,7 +170,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts b/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
index 4d4acd202c..59863fd52c 100644
--- a/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
+++ b/target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts
@@ -145,10 +145,20 @@
 				reg = <0x020000 0xfd0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -171,7 +181,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_ubnt_aircube-isp.dts b/target/linux/ath79/dts/qca9533_ubnt_aircube-isp.dts
index c5d6e66c9a..b6e6fc91df 100644
--- a/target/linux/ath79/dts/qca9533_ubnt_aircube-isp.dts
+++ b/target/linux/ath79/dts/qca9533_ubnt_aircube-isp.dts
@@ -62,7 +62,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -79,6 +79,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -105,5 +109,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9533_yuncore_a930.dts b/target/linux/ath79/dts/qca9533_yuncore_a930.dts
index 30b340768f..518d88e62c 100644
--- a/target/linux/ath79/dts/qca9533_yuncore_a930.dts
+++ b/target/linux/ath79/dts/qca9533_yuncore_a930.dts
@@ -75,7 +75,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -92,6 +92,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -114,5 +118,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca953x_tplink_tl-wr810n.dtsi b/target/linux/ath79/dts/qca953x_tplink_tl-wr810n.dtsi
index e3b35b810d..3038588370 100644
--- a/target/linux/ath79/dts/qca953x_tplink_tl-wr810n.dtsi
+++ b/target/linux/ath79/dts/qca953x_tplink_tl-wr810n.dtsi
@@ -88,10 +88,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -114,7 +124,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9550_airtight_c-75.dts b/target/linux/ath79/dts/qca9550_airtight_c-75.dts
index 6ade40bfe1..ad19bab4e2 100644
--- a/target/linux/ath79/dts/qca9550_airtight_c-75.dts
+++ b/target/linux/ath79/dts/qca9550_airtight_c-75.dts
@@ -150,7 +150,7 @@
 				reg = <0x060000 0xf90000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -167,6 +167,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -201,5 +205,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts
new file mode 100644
index 0000000000..6ef2eb846d
--- /dev/null
+++ b/target/linux/ath79/dts/qca9550_dell_apl26-0ae.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "qca955x.dtsi"
+
+/ {
+	model = "Dell SonicPoint ACe (APL26-0AE)";
+	compatible = "dell,apl26-0ae", "qca,qca9550", "qca,qca9558";
+
+	aliases {
+		label-mac-device = &eth0;
+		led-boot = &led_wrench;
+		led-failsafe = &led_wrench;
+		led-upgrade = &led_wrench;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		/* Accessible only after disassembling the casing */
+		button-service {
+			label = "service";
+			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&jtag_disable_pins>;
+
+		led-lan1-amber {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <1>;
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		led-lan1-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <1>;
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		led-lan2-amber {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <2>;
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+		};
+
+		led-lan2-green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			function-enumerator = <2>;
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+
+		led-wlan2g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+			linux,default-trigger = "phy1tpt";
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		led-wlan5g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_5GHZ;
+			linux,default-trigger = "phy0tpt";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wrench: led-wrench {
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_sysinfo_50 0>;
+	nvmem-cell-names = "mac-address";
+	phy-handle = <&phy0>;
+	pll-data = <0xa6000000 0x00000101 0x00001616>;
+};
+
+&eth1 {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_sysinfo_50 1>;
+	nvmem-cell-names = "mac-address";
+	pll-data = <0x03000101 0x00000101 0x00001616>;
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+
+		qca,ar8327-initvals = <
+			0x04 0x07680000 /* PORT0 PAD MODE CTRL */
+			0x0c 0x00000080 /* PORT6 PAD MODE CTRL */
+			0x10 0x40000000 /* POWER_ON_STRAP */
+			0x50 0xffb7c405 /* LED0 CTRL */
+			0x54 0xffb7c305 /* LED1 CTRL */
+			0x58 0xffb7c033 /* LED2 CTRL */
+			0x5c 0x03ffff00 /* LED3 CTRL */
+			0x7c 0x0000007e /* PORT0_STATUS */
+			0x94 0x0000007e /* PORT6_STATUS */
+		>;
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+
+		/* OEM overwrites EEPROM stored adress and so do we */
+		nvmem-cells = <&macaddr_sysinfo_50 2>;
+		nvmem-cell-names = "mac-address";
+	};
+};
+
+&spi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		broken-flash-reset;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0000000 0x0080000>;
+				read-only;
+			};
+
+			partition@80000 {
+				label = "u-boot-env";
+				reg = <0x0080000 0x0040000>;
+			};
+
+			partition@c0000 {
+				label = "sysinfo";
+				reg = <0x00c0000 0x0040000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_sysinfo_50: macaddr@50 {
+						compatible = "mac-base";
+						reg = <0x50 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@100000 {
+				label = "art";
+				reg = <0x0100000 0x0010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
+			};
+
+			partition@110000 {
+				label = "firmware";
+				reg = <0x0110000 0x1ef0000>;
+				compatible = "denx,uimage";
+			};
+		};
+	};
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_sysinfo_50 10>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
+};
diff --git a/target/linux/ath79/dts/qca9557_8dev_rambutan.dts b/target/linux/ath79/dts/qca9557_8dev_rambutan.dts
index f01ac7fc91..c71bc7ed9f 100644
--- a/target/linux/ath79/dts/qca9557_8dev_rambutan.dts
+++ b/target/linux/ath79/dts/qca9557_8dev_rambutan.dts
@@ -41,7 +41,7 @@
 			reg = <0x300000 0x200000>;
 		};
 
-		art: partition@500000 {
+		partition@500000 {
 			label = "art";
 			reg = <0x500000 0x100000>;
 			read-only;
@@ -58,6 +58,10 @@
 				macaddr_art_6: macaddr@6 {
 					reg = <0x6 0x6>;
 				};
+
+				cal_art_1000: calibration@1000 {
+					reg = <0x1000 0x440>;
+				};
 			};
 		};
 
@@ -111,7 +115,9 @@
 	status = "okay";
 
 	gpio-controller;
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
index 8cf1f00255..46b3640073 100644
--- a/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
+++ b/target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts
@@ -58,7 +58,7 @@
 };
 
 &partitions {
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -74,6 +74,10 @@
 				#nvmem-cell-cells = <1>;
 			};
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -106,10 +110,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts b/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
index 62c1124cb6..8b31a01f57 100644
--- a/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
+++ b/target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts
@@ -93,7 +93,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
index c81d17d20a..c8bbd044c9 100644
--- a/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
+++ b/target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts
@@ -64,7 +64,7 @@
 };
 
 &partitions {
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
index 097e1a87be..bdba469383 100644
--- a/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
+++ b/target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi
@@ -138,7 +138,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
index 33fc3f1a07..4372a07d51 100644
--- a/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
+++ b/target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts
@@ -86,7 +86,7 @@
 				reg = <0x030000 0x010000>;
 			};
 
-			art: partition@40000 {
+			partition@40000 {
 				label = "art";
 				reg = <0x040000 0x010000>;
 				read-only;
@@ -96,6 +96,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
diff --git a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
index c6620969d1..5aaaacef6c 100644
--- a/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
+++ b/target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts
@@ -82,7 +82,7 @@
 };
 
 &partitions {
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -98,6 +98,10 @@
 				#nvmem-cell-cells = <1>;
 			};
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -108,9 +112,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
index 3906b82776..fb2187be1f 100644
--- a/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
+++ b/target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts
@@ -58,7 +58,7 @@
 };
 
 &partitions {
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -74,6 +74,10 @@
 				#nvmem-cell-cells = <1>;
 			};
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -106,9 +110,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi b/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
index 9048fd3e2f..cd84e568d9 100644
--- a/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
+++ b/target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi
@@ -152,7 +152,7 @@
 				reg = <0xe80000 0x170000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 
@@ -166,6 +166,10 @@
 						reg = <0x0 0x6>;
 						#nvmem-cell-cells = <1>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -230,5 +234,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
index 703eead178..afe97df6d4 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-e380ac-v2.dts
@@ -63,12 +63,6 @@
 	};
 };
 
-&eth0 {
-	status = "okay";
-	mtd-mac-address = <&art 0x0>;
-};
-
-
 &spi {
 	status = "okay";
 
@@ -88,7 +82,7 @@
 				read-only;
 			};
 
-			art: partition@40000 {
+			partition@40000 {
 				label = "art";
 				reg = <0x040000 0x010000>;
 				read-only;
@@ -104,6 +98,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -157,7 +155,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 10>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 10>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
index 2e6f86b0b2..d00c4f7e98 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts
@@ -35,7 +35,7 @@
 				read-only;
 			};
 
-			art: partition@20000 {
+			partition@20000 {
 				label = "art";
 				reg = <0x020000 0x010000>;
 				read-only;
@@ -57,6 +57,10 @@
 						reg = <0x18 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -89,8 +93,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_art_18>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_18>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
index a4aa4118fa..fb46f4db50 100644
--- a/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts
@@ -37,7 +37,7 @@
 				read-only;
 			};
 
-			art: partition@40000 {
+			partition@40000 {
 				label = "art";
 				reg = <0x040000 0x010000>;
 				read-only;
@@ -59,6 +59,10 @@
 						reg = <0x18 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -91,8 +95,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_art_18>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_18>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_compex_wpj558-16m.dts b/target/linux/ath79/dts/qca9558_compex_wpj558-16m.dts
index d6ecc7728f..e63c3e842d 100644
--- a/target/linux/ath79/dts/qca9558_compex_wpj558-16m.dts
+++ b/target/linux/ath79/dts/qca9558_compex_wpj558-16m.dts
@@ -94,10 +94,20 @@
 				reg = <0x030000 0xfc0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -135,7 +145,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
index 9fea258970..63d4a75e61 100644
--- a/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
+++ b/target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi
@@ -72,7 +72,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -88,6 +88,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -136,7 +140,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 (-2)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
index 765cfafe15..7b1ccf410d 100644
--- a/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
+++ b/target/linux/ath79/dts/qca9558_domywifi_dw33d.dts
@@ -120,7 +120,7 @@
 				reg = <0x50000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
@@ -146,6 +146,10 @@
 						reg = <0x12 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -219,7 +223,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_c>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi b/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi
new file mode 100644
index 0000000000..1f8a4a2364
--- /dev/null
+++ b/target/linux/ath79/dts/qca9558_engenius_dual_ap.dtsi
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x_senao_loader.dtsi"
+
+&partitions {
+	partition@ff0000 {
+		label = "art";
+		reg = <0xff0000 0x010000>;
+		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			macaddr_art_0: macaddr@0 {
+				compatible = "mac-base";
+				reg = <0x0 0x6>;
+				#nvmem-cell-cells = <1>;
+			};
+
+			calibration_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
+			calibration_art_5000: calibration@5000 {
+				reg = <0x5000 0x844>;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+		eee-broken-100tx;
+		eee-broken-1000t;
+	};
+
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+		eee-broken-100tx;
+		eee-broken-1000t;
+		at803x-override-sgmii-link-check;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_art_0 0>;
+	nvmem-cell-names = "mac-address";
+
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+
+	pll-data = <0x82000000 0x80000101 0x80001313>;
+};
+
+&eth1 {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_art_0 1>;
+	nvmem-cell-names = "mac-address";
+
+	phy-handle = <&phy2>;
+
+	pll-data = <0x03000000 0x00000101 0x00001313>;
+
+	qca955x-sgmii-fixup;
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
+};
+
+&ath10k_1 {
+	nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>;
+	nvmem-cell-names = "mac-address", "calibration";
+};
+
+&pcie1 {
+	status = "okay";
+};
diff --git a/target/linux/ath79/dts/qca9558_engenius_ens1750.dts b/target/linux/ath79/dts/qca9558_engenius_ens1750.dts
new file mode 100644
index 0000000000..45215d31b5
--- /dev/null
+++ b/target/linux/ath79/dts/qca9558_engenius_ens1750.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9558_engenius_dual_ap.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "engenius,ens1750", "qca,qca9558";
+	model = "EnGenius ENS1750";
+
+	aliases {
+		label-mac-device = &eth0;
+		led-boot = &led_wifi5g;
+		led-failsafe = &led_wifi5g;
+		led-upgrade = &led_wifi5g;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi2g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_wifi5g: wifi5g {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_5GHZ;
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+};
diff --git a/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts b/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts
index 9fa1927c1d..01a3804fcb 100644
--- a/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts
+++ b/target/linux/ath79/dts/qca9558_engenius_ews660ap.dts
@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "qca955x_senao_loader.dtsi"
+#include "qca9558_engenius_dual_ap.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	compatible = "engenius,ews660ap", "qca,qca9558";
@@ -31,103 +32,17 @@
 		compatible = "gpio-leds";
 
 		wifi2g {
-			label = "green:wifi2g";
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_2GHZ;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
 
 		led_wifi5g: wifi5g {
-			label = "green:wifi5g";
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_5GHZ;
 			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 	};
 };
-
-&partitions {
-	partition@ff0000 {
-		label = "art";
-		reg = <0xff0000 0x010000>;
-		read-only;
-
-		nvmem-layout {
-			compatible = "fixed-layout";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			macaddr_art_0: macaddr@0 {
-				compatible = "mac-base";
-				reg = <0x0 0x6>;
-				#nvmem-cell-cells = <1>;
-			};
-
-			calibration_art_1000: calibration@1000 {
-				reg = <0x1000 0x440>;
-			};
-
-			calibration_art_5000: calibration@5000 {
-				reg = <0x5000 0x844>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-		eee-broken-100tx;
-		eee-broken-1000t;
-	};
-
-	phy2: ethernet-phy@2 {
-		reg = <2>;
-		eee-broken-100tx;
-		eee-broken-1000t;
-		at803x-override-sgmii-link-check;
-	};
-};
-
-&eth0 {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_0 0>;
-	nvmem-cell-names = "mac-address";
-
-	phy-handle = <&phy1>;
-	phy-mode = "rgmii-id";
-
-	pll-data = <0x82000000 0x80000101 0x80001313>;
-};
-
-&eth1 {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
-
-	phy-handle = <&phy2>;
-
-	pll-data = <0x03000000 0x00000101 0x00001313>;
-
-	qca955x-sgmii-fixup;
-};
-
-&wmac {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>;
-	nvmem-cell-names = "mac-address", "calibration";
-};
-
-&ath10k_1 {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>;
-	nvmem-cell-names = "mac-address", "calibration";
-};
-
-&pcie1 {
-	status = "okay";
-};
diff --git a/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts b/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
index 0f3c23d474..199098fd60 100644
--- a/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
+++ b/target/linux/ath79/dts/qca9558_jjplus_jwap230.dts
@@ -78,7 +78,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts b/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
index 333b52f4d9..a8c1e75d8d 100644
--- a/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
+++ b/target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts
@@ -137,7 +137,7 @@
 				reg = <0xfd0000 0x20000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -158,6 +158,10 @@
 					macaddr_art_c: macaddr@c {
 						reg = <0xc 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 		};
@@ -209,7 +213,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_c>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_ocedo_koala.dts b/target/linux/ath79/dts/qca9558_ocedo_koala.dts
index 891bdd95c4..1341593117 100644
--- a/target/linux/ath79/dts/qca9558_ocedo_koala.dts
+++ b/target/linux/ath79/dts/qca9558_ocedo_koala.dts
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -133,6 +133,10 @@
 						reg = <0xc 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -145,9 +149,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_6>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &mdio0 {
diff --git a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
index 8ddeccefb7..5cdf22ac7b 100644
--- a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
+++ b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
@@ -80,7 +80,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -106,6 +106,10 @@
 						reg = <0x12 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -118,9 +122,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_6>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &mdio0 {
diff --git a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
index e908c26c0d..8cd27e01cc 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
+++ b/target/linux/ath79/dts/qca9558_openmesh_a60.dtsi
@@ -110,7 +110,7 @@
 				reg = <0x850000 0x7a0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "ART";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -130,6 +130,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -193,9 +197,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
index 03f2999083..d4087d511f 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
+++ b/target/linux/ath79/dts/qca9558_openmesh_mr.dtsi
@@ -119,7 +119,7 @@
 				reg = <0x850000 0x7a0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "ART";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -135,6 +135,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -174,9 +178,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
index 8fd35a99d4..838aa1f0b8 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts
@@ -129,7 +129,7 @@
 				reg = <0x850000 0x7a0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "ART";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -149,6 +149,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -212,9 +216,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie1 {
diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
index 2e27d3d6ee..9c5b70a606 100644
--- a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
+++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
@@ -164,7 +164,7 @@
 				reg = <0x850000 0x7a0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "ART";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -184,6 +184,10 @@
 						reg = <0x6 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -251,7 +255,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 2>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 2>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
index 9cbdca234d..16308395e4 100644
--- a/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
+++ b/target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi
@@ -105,10 +105,20 @@
 				};
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
 				reg = <0x060000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -178,5 +188,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
index 2a57eeec77..1c8d88c20d 100644
--- a/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
+++ b/target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
index 92e89ff3aa..744871a931 100644
--- a/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
+++ b/target/linux/ath79/dts/qca9558_sophos_ap.dtsi
@@ -107,7 +107,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -117,13 +117,17 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
 				};
 			};
 
-			config: partition@60000 {
+			partition@60000 {
 				label = "config";
 				reg = <0x060000 0x010000>;
 				read-only;
@@ -184,7 +188,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &usb0 {
diff --git a/target/linux/ath79/dts/qca9558_sophos_ap15.dts b/target/linux/ath79/dts/qca9558_sophos_ap15.dts
index 5801303040..7949d3e88f 100644
--- a/target/linux/ath79/dts/qca9558_sophos_ap15.dts
+++ b/target/linux/ath79/dts/qca9558_sophos_ap15.dts
@@ -75,7 +75,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -85,13 +85,17 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
 				};
 			};
 
-			config: partition@60000 {
+			partition@60000 {
 				label = "config";
 				reg = <0x060000 0x010000>;
 				read-only;
@@ -154,5 +158,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
index 584a66ba52..17af5cb27e 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts
@@ -29,7 +29,7 @@
 };
 
 &mtdparts {
-	uboot: partition@0 {
+	partition@0 {
 		label = "u-boot";
 		reg = <0x000000 0x020000>;
 		read-only;
@@ -53,7 +53,7 @@
 		compatible = "tplink,firmware";
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -63,6 +63,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -90,8 +94,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-c7-v2.dts b/target/linux/ath79/dts/qca9558_tplink_archer-c7-v2.dts
index c722caeb55..398fd7906d 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-c7-v2.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-c7-v2.dts
@@ -54,7 +54,7 @@
 		compatible = "tplink,firmware";
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
index 20cefe0b79..0ddf23f354 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts
@@ -57,7 +57,7 @@
 				read-only;
 			};
 
-			romfs: partition@fd0000 {
+			partition@fd0000 {
 				label = "romfs";
 				reg = <0xfd0000 0x010000>;
 				read-only;
@@ -81,7 +81,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -91,6 +91,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -111,7 +115,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_romfs_f100 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_romfs_f100 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
index 3418601c41..fd47f7fee3 100644
--- a/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts
@@ -51,7 +51,7 @@
 				read-only;
 			};
 
-			romfs: partition@fd0000 {
+			partition@fd0000 {
 				label = "romfs";
 				reg = <0xfd0000 0x010000>;
 				read-only;
@@ -75,7 +75,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -85,6 +85,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -105,7 +109,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_romfs_f100 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_romfs_f100 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
index a3fb9b22d2..becd5cc44b 100644
--- a/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts
@@ -157,7 +157,7 @@
 				read-only;
 			};
 
-			info: partition@da0000 {
+			partition@da0000 {
 				label = "info";
 				reg = <0xda0000 0x020000>;
 				read-only;
@@ -181,7 +181,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -191,6 +191,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -203,7 +207,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
index 3061ae07c7..3857635672 100644
--- a/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
+++ b/target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi
@@ -142,7 +142,7 @@
 				read-only;
 			};
 
-			info: partition@610000 {
+			partition@610000 {
 				label = "info";
 				reg = <0x610000 0x020000>;
 				read-only;
@@ -166,7 +166,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -176,6 +176,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -198,7 +202,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 (-1)>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 (-1)>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wdr4900-v2.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wdr4900-v2.dts
index 0edba24040..e5da140364 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wdr4900-v2.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wdr4900-v2.dts
@@ -156,7 +156,7 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
index 33697d3b83..0e09b5aa09 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts
@@ -29,7 +29,7 @@
 };
 
 &mtdparts {
-	uboot: partition@0 {
+	partition@0 {
 		label = "u-boot";
 		reg = <0x000000 0x020000>;
 		read-only;
@@ -53,7 +53,7 @@
 		reg = <0x020000 0x7d0000>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -63,6 +63,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -90,8 +94,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi b/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
index a72b6e6050..49af23bf02 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi
@@ -121,10 +121,20 @@
 				reg = <0x020000 0x7d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -175,7 +185,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts b/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
index f51b89206d..3f8256ba17 100644
--- a/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
+++ b/target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts
@@ -94,10 +94,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -125,7 +135,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00>;
-	nvmem-cell-names = "mac-address";
+
+	nvmem-cells = <&macaddr_uboot_1fc00>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts b/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
index 23b484cdf5..d2e381eb4b 100644
--- a/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
+++ b/target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts
@@ -135,10 +135,20 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -185,5 +195,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
index e3431330de..043f8dd262 100644
--- a/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
+++ b/target/linux/ath79/dts/qca9558_watchguard_ap300.dts
@@ -102,7 +102,7 @@
 		reg = <0xff0000 0x1000000>;
 	};
 
-	art: partition@1ff0000 {
+	partition@1ff0000 {
 		label = "art";
 		reg = <0x1ff0000 0x010000>;
 		read-only;
@@ -118,6 +118,10 @@
 				#nvmem-cell-cells = <1>;
 			};
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -132,10 +136,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &pcie0 {
diff --git a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
index 76ae8a99a6..19f1245022 100644
--- a/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
+++ b/target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
@@ -96,18 +96,18 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x000000 0x040000>;
 				read-only;
 			};
 
-			uboot_env: partition@40000 {
+			partition@40000 {
 				label = "u-boot-env";
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -117,6 +117,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
diff --git a/target/linux/ath79/dts/qca955x_senao_loader.dtsi b/target/linux/ath79/dts/qca955x_senao_loader.dtsi
index 31e00ce063..7cf64bd965 100644
--- a/target/linux/ath79/dts/qca955x_senao_loader.dtsi
+++ b/target/linux/ath79/dts/qca955x_senao_loader.dtsi
@@ -59,6 +59,7 @@
 			};
 
 			partition@40000 {
+				compatible = "u-boot,env";
 				label = "u-boot-env";
 				reg = <0x040000 0x010000>;
 			};
diff --git a/target/linux/ath79/dts/qca955x_senao_router-dual.dtsi b/target/linux/ath79/dts/qca955x_senao_router-dual.dtsi
index 8f62cf442c..ece2f5d6fb 100644
--- a/target/linux/ath79/dts/qca955x_senao_router-dual.dtsi
+++ b/target/linux/ath79/dts/qca955x_senao_router-dual.dtsi
@@ -98,7 +98,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
index 7c1870d714..c803a4d66d 100644
--- a/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
+++ b/target/linux/ath79/dts/qca955x_ubnt_xc.dtsi
@@ -53,7 +53,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca955x_zyxel_nbg6x16.dtsi b/target/linux/ath79/dts/qca955x_zyxel_nbg6x16.dtsi
index 7de1c4fa69..3cbb305aad 100644
--- a/target/linux/ath79/dts/qca955x_zyxel_nbg6x16.dtsi
+++ b/target/linux/ath79/dts/qca955x_zyxel_nbg6x16.dtsi
@@ -103,7 +103,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &usb_phy0 {
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
index 97e9ebf0b6..e4d9b99a60 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts
@@ -147,13 +147,13 @@
 				reg = <0x030000 0x7a0000>;
 			};
 
-			config: partition@7d0000 {
+			partition@7d0000 {
 				label = "config";
 				reg = <0x7d0000 0x010000>;
 				read-only;
 			};
 
-			info: partition@7e0000 {
+			partition@7e0000 {
 				label = "info";
 				reg = <0x7e0000 0x010000>;
 				read-only;
@@ -171,7 +171,7 @@
 				};
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -181,6 +181,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -220,7 +224,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
index 95af751784..33ef672f45 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts
@@ -39,7 +39,7 @@
 				read-only;
 			};
 
-			info: partition@10000 {
+			partition@10000 {
 				label = "info";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -69,7 +69,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -79,6 +79,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -99,8 +103,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
index e8b282b9c2..4e6e90a8c3 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts
@@ -59,7 +59,7 @@
 				read-only;
 			};
 
-			info: partition@10000 {
+			partition@10000 {
 				label = "info";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -89,7 +89,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -99,6 +99,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -119,8 +123,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
index 8a93d2b3b1..094ef7090f 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts
@@ -62,7 +62,7 @@
 				read-only;
 			};
 
-			info: partition@30000 {
+			partition@30000 {
 				label = "info";
 				reg = <0x030000 0x010000>;
 				read-only;
@@ -92,7 +92,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -102,6 +102,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -122,8 +126,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
index eb21394d04..b64f8c7cec 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
@@ -55,7 +55,7 @@
 				read-only;
 			};
 
-			info: partition@10000 {
+			partition@10000 {
 				label = "info";
 				reg = <0x010000 0x010000>;
 				read-only;
@@ -85,7 +85,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -95,6 +95,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -115,8 +119,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
index aa4a7da10c..34fe10cb51 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
@@ -55,7 +55,7 @@
 				read-only;
 			};
 
-			info: partition@1fb00 {
+			partition@1fb00 {
 				label = "info";
 				reg = <0x01fb00 0x000500>;
 				read-only;
@@ -91,7 +91,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -101,6 +101,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -121,8 +125,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
index ede6878d5c..d50b3af018 100644
--- a/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts
@@ -49,7 +49,7 @@
 				read-only;
 			};
 
-			info: partition@1fb00 {
+			partition@1fb00 {
 				label = "info";
 				reg = <0x01fb00 0x000500>;
 				read-only;
@@ -85,7 +85,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -95,6 +95,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -115,8 +119,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts b/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
index 0e5c1fdc43..aa476ef536 100644
--- a/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
+++ b/target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts
@@ -139,7 +139,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9561_xiaomi_mi-router-4q.dts b/target/linux/ath79/dts/qca9561_xiaomi_mi-router-4q.dts
index 5f9f575b44..b9aee571c9 100644
--- a/target/linux/ath79/dts/qca9561_xiaomi_mi-router-4q.dts
+++ b/target/linux/ath79/dts/qca9561_xiaomi_mi-router-4q.dts
@@ -89,7 +89,7 @@
 				read-only;
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
 				reg = <0x60000 0x10000>;
 				read-only;
@@ -108,6 +108,10 @@
 					macaddr_art_6: macaddr@6 {
 						reg = <0x6 0x6>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -150,7 +154,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 1>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 1>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
index 752ecb2798..a48d14b1d7 100644
--- a/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
+++ b/target/linux/ath79/dts/qca9563_asus_pl-ac56.dts
@@ -96,7 +96,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
index 763ba431ef..1b8f5acadf 100644
--- a/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
+++ b/target/linux/ath79/dts/qca9563_asus_rp-ac66.dts
@@ -117,7 +117,7 @@
 				read-only;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
index ebcaeb6ddc..9fca52bf33 100644
--- a/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
+++ b/target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts
@@ -90,7 +90,7 @@
 				read-only;
 			};
 
-			art: partition@40000 {
+			partition@40000 {
 				label = "art";
 				reg = <0x040000 0x010000>;
 				read-only;
@@ -106,6 +106,10 @@
 						#nvmem-cell-cells = <1>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -156,7 +160,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_art_0 10>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_art_0 10>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_compex_wpj563.dts b/target/linux/ath79/dts/qca9563_compex_wpj563.dts
index 95ca900398..dc449d8214 100644
--- a/target/linux/ath79/dts/qca9563_compex_wpj563.dts
+++ b/target/linux/ath79/dts/qca9563_compex_wpj563.dts
@@ -97,10 +97,20 @@
 				reg = <0x030000 0xfc0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -151,5 +161,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_dlink_covr.dtsi b/target/linux/ath79/dts/qca9563_dlink_covr.dtsi
index 5138cbc796..640de11d34 100644
--- a/target/linux/ath79/dts/qca9563_dlink_covr.dtsi
+++ b/target/linux/ath79/dts/qca9563_dlink_covr.dtsi
@@ -85,7 +85,7 @@
 				reg = <0xe90000 0x160000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
index 34961c94c4..1e0c208505 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
@@ -107,7 +107,7 @@
 				reg = <0x080000 0xf50000>;
 			};
 
-			art: partition@fd0000 {
+			partition@fd0000 {
 				label = "art";
 				reg = <0xfd0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts b/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
index e7cdcad9c3..cf447d782e 100644
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts
@@ -43,7 +43,7 @@
 		read-only;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
index 8b64d8d2ff..343ff8b729 100644
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
@@ -37,7 +37,7 @@
 		read-only;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
diff --git a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
index 0624d88d8a..3244b499c4 100644
--- a/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
+++ b/target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi
@@ -93,7 +93,7 @@
 				reg = <0x040000 0x010000>;
 			};
 
-			art: partition@50000 {
+			partition@50000 {
 				label = "art";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -112,6 +112,10 @@
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
 				};
 			};
 
@@ -197,5 +201,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
index fdcca64a0c..d2621fa304 100644
--- a/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
+++ b/target/linux/ath79/dts/qca9563_nec_wg800hp.dts
@@ -150,7 +150,7 @@
 				};
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
index 614d88d383..e3d20df5f6 100644
--- a/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
+++ b/target/linux/ath79/dts/qca9563_phicomm_k2t.dts
@@ -98,7 +98,7 @@
 				reg = <0x090000 0xf60000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -108,6 +108,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -147,5 +151,7 @@
 
 &wmac {
 	status = "okay";
-	mtd-cal-data = <&art 0x1000>;
+
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
index a0e6489918..90f6d1a494 100644
--- a/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
+++ b/target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi
@@ -87,7 +87,7 @@
 				read-only;
 			};
 
-			pridata: partition@50000 {
+			partition@50000 {
 				label = "pri-data";
 				reg = <0x050000 0x010000>;
 				read-only;
@@ -103,7 +103,7 @@
 				};
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
 				reg = <0x060000 0x010000>;
 				read-only;
@@ -113,6 +113,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -168,5 +172,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_rosinson_wr818.dts b/target/linux/ath79/dts/qca9563_rosinson_wr818.dts
index 6e45a20aae..0f07613d1f 100644
--- a/target/linux/ath79/dts/qca9563_rosinson_wr818.dts
+++ b/target/linux/ath79/dts/qca9563_rosinson_wr818.dts
@@ -90,10 +90,20 @@
 				reg = <0x060000 0xf80000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -125,7 +135,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &usb_phy0 {
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
index 50996e06c7..80874b143f 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts
@@ -27,7 +27,7 @@
 		read-only;
 	};
 
-	uboot: partition@20000 {
+	partition@20000 {
 		label = "u-boot";
 		reg = <0x020000 0x020000>;
 		read-only;
@@ -39,7 +39,7 @@
 		compatible = "denx,uimage";
 	};
 
-	info: partition@f40000 {
+	partition@f40000 {
 		label = "info";
 		reg = <0xf40000 0x020000>;
 		read-only;
@@ -57,7 +57,7 @@
 		};
 	};
 
-	config: partition@f60000 {
+	partition@f60000 {
 		label = "config";
 		reg = <0xf60000 0x050000>;
 		read-only;
@@ -69,7 +69,7 @@
 		read-only;
 	};
 
-	art: partition@ff0000 {
+	partition@ff0000 {
 		label = "art";
 		reg = <0xff0000 0x010000>;
 		read-only;
@@ -79,6 +79,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -101,8 +105,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
index 907eda9400..4006a0231c 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts
@@ -127,7 +127,7 @@
 				compatible = "denx,uimage";
 			};
 
-			info: partition@7e0000 {
+			partition@7e0000 {
 				label = "info";
 				reg = <0x7e0000 0x010000>;
 				read-only;
@@ -145,7 +145,7 @@
 				};
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -155,6 +155,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -202,7 +206,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
index f78a52a120..74ac0f745a 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			info: partition@20000 {
+			partition@20000 {
 				label = "info";
 				reg = <0x020000 0x010000>;
 				read-only;
@@ -147,7 +147,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -157,6 +157,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -172,8 +176,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
index fc7814a97e..66ae2d1ffd 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			info: partition@20000 {
+			partition@20000 {
 				label = "info";
 				reg = <0x020000 0x010000>;
 				read-only;
@@ -141,7 +141,7 @@
 				read-only;
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
@@ -151,6 +151,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -166,8 +170,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
index 611cb8953e..05dd95474e 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts
@@ -205,7 +205,7 @@
 				compatible = "denx,uimage";
 			};
 
-			info: partition@f00000 {
+			partition@f00000 {
 				label = "info";
 				reg = <0xf00000 0x0f0000>;
 				read-only;
@@ -223,7 +223,7 @@
 				};
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -233,6 +233,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -272,7 +276,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
index d37fc14b11..89b2244ca8 100644
--- a/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts
@@ -39,7 +39,7 @@
 		read-only;
 	};
 
-	art: partition@50000 {
+	partition@50000 {
 		label = "art";
 		reg = <0x050000 0x010000>;
 		read-only;
@@ -49,13 +49,17 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
 		};
 	};
 
-	info: partition@60000 {
+	partition@60000 {
 		label = "info";
 		reg = <0x060000 0x020000>;
 		read-only;
@@ -109,8 +113,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
index 3a0c16d4a3..6d1b58f95f 100644
--- a/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts
@@ -114,7 +114,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
index 7968bdbf6d..088ef7b63c 100644
--- a/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts
@@ -93,7 +93,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			uboot: partition@0 {
+			partition@0 {
 				label = "u-boot";
 				reg = <0x000000 0x080000>;
 				read-only;
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			config: partition@e85000 {
+			partition@e85000 {
 				label = "config";
 				reg = <0xe85000 0x16b000>;
 				read-only;
@@ -129,7 +129,7 @@
 				};
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -139,6 +139,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -161,7 +165,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_config_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_config_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
index 29d0d8868d..7cbc77f64b 100644
--- a/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_deco-s4-v2.dts
@@ -111,7 +111,7 @@
 				read-only;
 			};
 
-			art: partition@1f0000 {
+			partition@1f0000 {
 				label = "art";
 				reg = <0x1f0000 0x10000>;
 				read-only;
diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
index 25a7b8229b..43f9106a49 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
@@ -30,7 +30,7 @@
 		read-only;
 	};
 
-	info: partition@610000 {
+	partition@610000 {
 		label = "info";
 		reg = <0x610000 0x020000>;
 		read-only;
@@ -54,7 +54,7 @@
 		read-only;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -64,6 +64,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -86,8 +90,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
index 2572901def..5d23a1d972 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re450-v3.dts
@@ -18,7 +18,7 @@
 		read-only;
 	};
 
-	info: partition@20000 {
+	partition@20000 {
 		label = "info";
 		reg = <0x020000 0x002000>;
 		read-only;
@@ -60,7 +60,7 @@
 		reg = <0x050000 0x7a0000>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -70,6 +70,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -92,8 +96,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
index 7caa356861..b22d2bfa35 100644
--- a/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_re455-v1.dts
@@ -18,7 +18,7 @@
 		read-only;
 	};
 
-	info: partition@20000 {
+	partition@20000 {
 		label = "info";
 		reg = <0x020000 0x002000>;
 		read-only;
@@ -60,7 +60,7 @@
 		reg = <0x050000 0x7a0000>;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -70,6 +70,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -92,8 +96,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
index b1d564be15..50e4445707 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts
@@ -108,10 +108,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
 
 &spi {
@@ -133,7 +131,7 @@
 				read-only;
 			};
 
-			info: partition@20000 {
+			partition@20000 {
 				label = "info";
 				reg = <0x020000 0x010000>;
 				read-only;
@@ -163,7 +161,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -173,6 +171,10 @@
 					#address-cells = <1>;
 					#size-cells = <1>;
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
index a44caa0b6b..fd0d7af328 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts
@@ -12,7 +12,7 @@
 };
 
 &partitions {
-	uboot: partition@0 {
+	partition@0 {
 		label = "u-boot";
 		reg = <0x000000 0x010000>;
 		read-only;
@@ -42,7 +42,7 @@
 		read-only;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -52,6 +52,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			cal_art_5000: calibration@5000 {
 				reg = <0x5000 0x844>;
 			};
@@ -74,8 +78,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_uboot_fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
index 1e62094c12..cf83407932 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts
@@ -42,7 +42,7 @@
 		read-only;
 	};
 
-	info: partition@7e0000 {
+	partition@7e0000 {
 		label = "info";
 		reg = <0x7e0000 0x010000>;
 		read-only;
@@ -60,7 +60,7 @@
 		};
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -70,6 +70,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			precal_art_5000: pre-calibration@5000 {
 				reg = <0x5000 0x2f20>;
 			};
@@ -92,8 +96,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
index 5f834542f2..25ad244eea 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts
@@ -36,7 +36,7 @@
 		read-only;
 	};
 
-	info: partition@630000 {
+	partition@630000 {
 		label = "info";
 		reg = <0x630000 0x010000>;
 		read-only;
@@ -60,7 +60,7 @@
 		read-only;
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -70,6 +70,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			precal_art_5000: pre-calibration@5000 {
 				reg = <0x5000 0x2f20>;
 			};
@@ -92,8 +96,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
index 7be23423df..cb9b9f0fa9 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts
@@ -38,7 +38,7 @@
 		read-only;
 	};
 
-	info: partition@7e0000 {
+	partition@7e0000 {
 		label = "info";
 		reg = <0x7e0000 0x010000>;
 		read-only;
@@ -56,7 +56,7 @@
 		};
 	};
 
-	art: partition@7f0000 {
+	partition@7f0000 {
 		label = "art";
 		reg = <0x7f0000 0x010000>;
 		read-only;
@@ -66,6 +66,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			cal_art_1000: calibration@1000 {
+				reg = <0x1000 0x440>;
+			};
+
 			precal_art_5000: pre-calibration@5000 {
 				reg = <0x5000 0x2f20>;
 			};
@@ -88,8 +92,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n-v5.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n-v5.dts
index dac0da9fdc..895bd0fc0f 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n-v5.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043n-v5.dts
@@ -76,10 +76,20 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -91,8 +101,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
index 6db4653f69..39956c5a06 100644
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts
@@ -83,10 +83,20 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -116,8 +126,6 @@
 };
 
 &wmac {
-	mtd-cal-data = <&art 0x1000>;
-
-	nvmem-cells = <&macaddr_info_8>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_info_8>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts
new file mode 100644
index 0000000000..a322323899
--- /dev/null
+++ b/target/linux/ath79/dts/qca9563_ubnt_amplifi-router-hd.dts
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca956x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "ubnt,amplifi-router-hd", "qca,qca9563";
+	model = "Ubiquiti AmpliFi Router HD";
+
+	aliases {
+		label-mac-device = &eth0;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_art_5000>;
+		nvmem-cell-names = "calibration";
+	};
+};
+
+&spi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x000000 0x060000>;
+				read-only;
+			};
+
+			partition@60000 {
+				compatible = "u-boot,env";
+				label = "u-boot-env";
+				reg = <0x060000 0x010000>;
+			};
+
+			partition@70000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x070000 0xb00000>;
+			};
+
+			partition@b70000 {
+				label = "cfg";
+				reg = <0xb70000 0x0c0000>;
+				read-only;
+			};
+
+			partition@c30000 {
+				label = "recovery";
+				reg = <0xc30000 0x3b0000>;
+				read-only;
+			};
+
+			partition@fe0000 {
+				label = "prst";
+				reg = <0xfe0000 0x010000>;
+				read-only;
+			};
+
+			partition@ff0000 {
+				/* eeprom */
+				label = "art";
+				reg = <0xff0000 0x010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_art_0: macaddr@0 {
+						compatible = "mac-base";
+						reg = <0x0 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
+					cal_art_5000: calibration@5000 {
+						reg = <0x5000 0x844>;
+					};
+				};
+			};
+
+			partition@1000000 {
+				label = "bs1";
+				reg = <0x1000000 0x010000>;
+			};
+
+			partition@1010000 {
+				label = "bs2";
+				reg = <0x1010000 0x010000>;
+				read-only;
+			};
+
+			partition@1020000 {
+				label = "stats";
+				reg = <0x1020000 0x400000>;
+				read-only;
+			};
+
+			partition@1420000 {
+				label = "fw_inactive";
+				reg = <0x1420000 0xb00000>;
+				read-only;
+			};
+
+			partition@1f20000 {
+				label = "reserved";
+				reg = <0x1f20000 0x0e0000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		phy-mode = "sgmii";
+
+		qca,ar8327-initvals = <
+			0x04 0x00000080 /* AR8327_REG_PAD0_MODE */
+			0x08 0x00000000 /* PORT5 PAD MODE CTRL */
+			0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
+			0x10 0x602613a0 /* AR8327_REG_POWER_ON_STRAP */
+			0x50 0xcc35cc35 /* AR8327_REG_LED_CTRL0 */
+			0x54 0xca35ca35 /* AR8327_REG_LED_CTRL1 */
+			0x58 0xc935c935 /* AR8327_REG_LED_CTRL2 */
+			0x5c 0x03ffff00 /* AR8327_REG_LED_CTRL3 */
+			0x7c 0x0000007e /* AR8327_REG_PORT_STATUS(0) */
+			0x94 0x00001080 /* AR8327_REG_PORT_STATUS(6) */
+		>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	
+	pll-data = <0x03000101 0x00000101 0x00001919>;
+
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+
+	nvmem-cells = <&macaddr_art_0 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
diff --git a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
index 48d8d9c83e..961b9faf9f 100644
--- a/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
+++ b/target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi
@@ -93,7 +93,7 @@
 				read-only;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -107,6 +107,10 @@
 						reg = <0x0 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -119,5 +123,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
index 27e3436f8f..cff567e497 100644
--- a/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
+++ b/target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts
@@ -108,7 +108,7 @@
 				read-only;
 			};
 
-			art: partition@60000 {
+			partition@60000 {
 				label = "art";
 				reg = <0x60000 0x10000>;
 				read-only;
@@ -122,6 +122,10 @@
 						reg = <0x0 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					precal_art_5000: pre-calibration@5000 {
 						reg = <0x5000 0x2f20>;
 					};
@@ -185,7 +189,8 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
 
 &pcie {
diff --git a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
index 2cc227a2da..82a22ca5dc 100644
--- a/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
+++ b/target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi
@@ -92,7 +92,7 @@
 				reg = <0x050000 0xfa0000>;
 			};
 
-			art: partition@ff0000 {
+			partition@ff0000 {
 				label = "art";
 				reg = <0xff0000 0x010000>;
 				read-only;
@@ -106,6 +106,10 @@
 						reg = <0x0 0x6>;
 					};
 
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+
 					cal_art_5000: calibration@5000 {
 						reg = <0x5000 0x844>;
 					};
@@ -122,5 +126,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
+	nvmem-cells = <&cal_art_1000>;
+	nvmem-cell-names = "calibration";
 };
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
index aaca7fa531..04aa4bc5f9 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts
@@ -140,10 +140,20 @@
 				};
 			};
 
-			art: partition@7f0000 {
+			partition@7f0000 {
 				label = "art";
 				reg = <0x7f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -168,7 +178,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_config_8 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_config_8 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi b/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi
index 89dff43405..77c4a88c9f 100644
--- a/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi
+++ b/target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi
@@ -48,10 +48,20 @@
 				reg = <0x020000 0x3d0000>;
 			};
 
-			art: partition@3f0000 {
+			partition@3f0000 {
 				label = "art";
 				reg = <0x3f0000 0x010000>;
 				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					cal_art_1000: calibration@1000 {
+						reg = <0x1000 0x440>;
+					};
+				};
 			};
 		};
 	};
@@ -73,7 +83,6 @@
 &wmac {
 	status = "okay";
 
-	mtd-cal-data = <&art 0x1000>;
-	nvmem-cells = <&macaddr_uboot_1fc00 0>;
-	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_uboot_1fc00 0>, <&cal_art_1000>;
+	nvmem-cell-names = "mac-address", "calibration";
 };
diff --git a/target/linux/ath79/files/drivers/gpio/gpio-latch-mikrotik.c b/target/linux/ath79/files/drivers/gpio/gpio-latch-mikrotik.c
new file mode 100644
index 0000000000..8f53974e46
--- /dev/null
+++ b/target/linux/ath79/files/drivers/gpio/gpio-latch-mikrotik.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ *  GPIO latch driver
+ *
+ *  Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/gpio/consumer.h>
+#include <linux/gpio/driver.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+
+#define GPIO_LATCH_DRIVER_NAME  "gpio-latch-mikrotik"
+#define GPIO_LATCH_LINES 9
+
+struct gpio_latch_chip {
+	struct gpio_chip gc;
+	struct mutex mutex;
+	struct mutex latch_mutex;
+	bool latch_enabled;
+	int le_gpio;
+	bool le_active_low;
+	struct gpio_desc *gpios[GPIO_LATCH_LINES];
+};
+
+static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
+{
+	return container_of(gc, struct gpio_latch_chip, gc);
+}
+
+static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
+{
+	mutex_lock(&glc->mutex);
+
+	if (enable)
+		glc->latch_enabled = true;
+
+	if (glc->latch_enabled)
+		mutex_lock(&glc->latch_mutex);
+}
+
+static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
+{
+	if (glc->latch_enabled)
+		mutex_unlock(&glc->latch_mutex);
+
+	if (disable)
+		glc->latch_enabled = true;
+
+	mutex_unlock(&glc->mutex);
+}
+
+static int
+gpio_latch_get(struct gpio_chip *gc, unsigned offset)
+{
+	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+	int ret;
+
+	gpio_latch_lock(glc, false);
+	ret = gpiod_get_raw_value_cansleep(glc->gpios[offset]);
+	gpio_latch_unlock(glc, false);
+
+	return ret;
+}
+
+static void
+gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+	bool enable_latch = false;
+	bool disable_latch = false;
+
+	if (offset == glc->le_gpio) {
+		enable_latch = value ^ glc->le_active_low;
+		disable_latch = !enable_latch;
+	}
+
+	gpio_latch_lock(glc, enable_latch);
+	gpiod_set_raw_value_cansleep(glc->gpios[offset], value);
+	gpio_latch_unlock(glc, disable_latch);
+}
+
+static int
+gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
+{
+	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+	bool enable_latch = false;
+	bool disable_latch = false;
+	int ret;
+
+	if (offset == glc->le_gpio) {
+		enable_latch = value ^ glc->le_active_low;
+		disable_latch = !enable_latch;
+	}
+
+	gpio_latch_lock(glc, enable_latch);
+	ret = gpiod_direction_output_raw(glc->gpios[offset], value);
+	gpio_latch_unlock(glc, disable_latch);
+
+	return ret;
+}
+
+static int gpio_latch_probe(struct platform_device *pdev)
+{
+	struct gpio_latch_chip *glc;
+	struct gpio_chip *gc;
+	struct device *dev = &pdev->dev;
+	struct fwnode_handle *fwnode = dev->fwnode;
+	int i, n;
+
+	glc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);
+	if (!glc)
+		return -ENOMEM;
+
+	mutex_init(&glc->mutex);
+	mutex_init(&glc->latch_mutex);
+
+	n = gpiod_count(dev, NULL);
+	if (n <= 0) {
+		dev_err(dev, "failed to get gpios: %d\n", n);
+		return n;
+	} else if (n != GPIO_LATCH_LINES) {
+		dev_err(dev, "expected %d gpios\n", GPIO_LATCH_LINES);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < n; i++) {
+		glc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,
+			GPIOD_OUT_LOW);
+		if (IS_ERR(glc->gpios[i])) {
+			if (PTR_ERR(glc->gpios[i]) != -EPROBE_DEFER) {
+				dev_err(dev, "failed to get gpio %d: %ld\n", i,
+					PTR_ERR(glc->gpios[i]));
+			}
+			return PTR_ERR(glc->gpios[i]);
+		}
+	}
+
+	glc->le_gpio = 8;
+	glc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);
+
+	if (!glc->gpios[glc->le_gpio]) {
+		dev_err(dev, "missing required latch-enable gpio %d\n",
+			glc->le_gpio);
+		return -EINVAL;
+	}
+
+	gc = &glc->gc;
+	gc->label = GPIO_LATCH_DRIVER_NAME;
+	gc->can_sleep = true;
+	gc->base = -1;
+	gc->ngpio = GPIO_LATCH_LINES;
+	gc->get = gpio_latch_get;
+	gc->set = gpio_latch_set;
+	gc->direction_output = gpio_latch_direction_output;
+	gc->fwnode = fwnode;
+
+	platform_set_drvdata(pdev, glc);
+
+	i = gpiochip_add(&glc->gc);
+	if (i) {
+		dev_err(dev, "gpiochip_add() failed: %d\n", i);
+		return i;
+	}
+
+	return 0;
+}
+
+static int gpio_latch_remove(struct platform_device *pdev)
+{
+	struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
+
+	gpiochip_remove(&glc->gc);
+	return 0;
+}
+
+static const struct of_device_id gpio_latch_match[] = {
+	{ .compatible = GPIO_LATCH_DRIVER_NAME },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, gpio_latch_match);
+
+static struct platform_driver gpio_latch_driver = {
+	.probe = gpio_latch_probe,
+	.remove = gpio_latch_remove,
+	.driver = {
+		.name = GPIO_LATCH_DRIVER_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = gpio_latch_match,
+	},
+};
+
+module_platform_driver(gpio_latch_driver);
+
+MODULE_DESCRIPTION("GPIO latch driver");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);
diff --git a/target/linux/ath79/files/drivers/gpio/gpio-latch.c b/target/linux/ath79/files/drivers/gpio/gpio-latch.c
deleted file mode 100644
index 68f9290b2a..0000000000
--- a/target/linux/ath79/files/drivers/gpio/gpio-latch.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- *  GPIO latch driver
- *
- *  Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/gpio/consumer.h>
-#include <linux/gpio/driver.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
-
-#define GPIO_LATCH_DRIVER_NAME  "gpio-latch"
-#define GPIO_LATCH_LINES 9
-
-struct gpio_latch_chip {
-	struct gpio_chip gc;
-	struct mutex mutex;
-	struct mutex latch_mutex;
-	bool latch_enabled;
-	int le_gpio;
-	bool le_active_low;
-	struct gpio_desc *gpios[GPIO_LATCH_LINES];
-};
-
-static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
-{
-	return container_of(gc, struct gpio_latch_chip, gc);
-}
-
-static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
-{
-	mutex_lock(&glc->mutex);
-
-	if (enable)
-		glc->latch_enabled = true;
-
-	if (glc->latch_enabled)
-		mutex_lock(&glc->latch_mutex);
-}
-
-static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
-{
-	if (glc->latch_enabled)
-		mutex_unlock(&glc->latch_mutex);
-
-	if (disable)
-		glc->latch_enabled = true;
-
-	mutex_unlock(&glc->mutex);
-}
-
-static int
-gpio_latch_get(struct gpio_chip *gc, unsigned offset)
-{
-	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
-	int ret;
-
-	gpio_latch_lock(glc, false);
-	ret = gpiod_get_raw_value_cansleep(glc->gpios[offset]);
-	gpio_latch_unlock(glc, false);
-
-	return ret;
-}
-
-static void
-gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
-{
-	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
-	bool enable_latch = false;
-	bool disable_latch = false;
-
-	if (offset == glc->le_gpio) {
-		enable_latch = value ^ glc->le_active_low;
-		disable_latch = !enable_latch;
-	}
-
-	gpio_latch_lock(glc, enable_latch);
-	gpiod_set_raw_value_cansleep(glc->gpios[offset], value);
-	gpio_latch_unlock(glc, disable_latch);
-}
-
-static int
-gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
-{
-	struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
-	bool enable_latch = false;
-	bool disable_latch = false;
-	int ret;
-
-	if (offset == glc->le_gpio) {
-		enable_latch = value ^ glc->le_active_low;
-		disable_latch = !enable_latch;
-	}
-
-	gpio_latch_lock(glc, enable_latch);
-	ret = gpiod_direction_output_raw(glc->gpios[offset], value);
-	gpio_latch_unlock(glc, disable_latch);
-
-	return ret;
-}
-
-static int gpio_latch_probe(struct platform_device *pdev)
-{
-	struct gpio_latch_chip *glc;
-	struct gpio_chip *gc;
-	struct device *dev = &pdev->dev;
-	struct device_node *of_node = dev->of_node;
-	int i, n;
-
-	glc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);
-	if (!glc)
-		return -ENOMEM;
-
-	mutex_init(&glc->mutex);
-	mutex_init(&glc->latch_mutex);
-
-	n = gpiod_count(dev, NULL);
-	if (n <= 0) {
-		dev_err(dev, "failed to get gpios: %d\n", n);
-		return n;
-	} else if (n != GPIO_LATCH_LINES) {
-		dev_err(dev, "expected %d gpios\n", GPIO_LATCH_LINES);
-		return -EINVAL;
-	}
-
-	for (i = 0; i < n; i++) {
-		glc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,
-			GPIOD_OUT_LOW);
-		if (IS_ERR(glc->gpios[i])) {
-			if (PTR_ERR(glc->gpios[i]) != -EPROBE_DEFER) {
-				dev_err(dev, "failed to get gpio %d: %ld\n", i,
-					PTR_ERR(glc->gpios[i]));
-			}
-			return PTR_ERR(glc->gpios[i]);
-		}
-	}
-
-	glc->le_gpio = 8;
-	glc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);
-
-	if (!glc->gpios[glc->le_gpio]) {
-		dev_err(dev, "missing required latch-enable gpio %d\n",
-			glc->le_gpio);
-		return -EINVAL;
-	}
-
-	gc = &glc->gc;
-	gc->label = GPIO_LATCH_DRIVER_NAME;
-	gc->can_sleep = true;
-	gc->base = -1;
-	gc->ngpio = GPIO_LATCH_LINES;
-	gc->get = gpio_latch_get;
-	gc->set = gpio_latch_set;
-	gc->direction_output = gpio_latch_direction_output;
-	gc->of_node = of_node;
-
-	platform_set_drvdata(pdev, glc);
-
-	i = gpiochip_add(&glc->gc);
-	if (i) {
-		dev_err(dev, "gpiochip_add() failed: %d\n", i);
-		return i;
-	}
-
-	return 0;
-}
-
-static int gpio_latch_remove(struct platform_device *pdev)
-{
-	struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
-
-	gpiochip_remove(&glc->gc);
-	return 0;
-}
-
-static const struct of_device_id gpio_latch_match[] = {
-	{ .compatible = GPIO_LATCH_DRIVER_NAME },
-	{},
-};
-
-MODULE_DEVICE_TABLE(of, gpio_latch_match);
-
-static struct platform_driver gpio_latch_driver = {
-	.probe = gpio_latch_probe,
-	.remove = gpio_latch_remove,
-	.driver = {
-		.name = GPIO_LATCH_DRIVER_NAME,
-		.owner = THIS_MODULE,
-		.of_match_table = gpio_latch_match,
-	},
-};
-
-module_platform_driver(gpio_latch_driver);
-
-MODULE_DESCRIPTION("GPIO latch driver");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);
diff --git a/target/linux/ath79/files/drivers/gpio/gpio-rb91x-key.c b/target/linux/ath79/files/drivers/gpio/gpio-rb91x-key.c
index ee8359e774..8996b2a906 100644
--- a/target/linux/ath79/files/drivers/gpio/gpio-rb91x-key.c
+++ b/target/linux/ath79/files/drivers/gpio/gpio-rb91x-key.c
@@ -144,7 +144,7 @@ static int gpio_rb91x_key_probe(struct platform_device *pdev)
 	struct gpio_rb91x_key *drvdata;
 	struct gpio_chip *gc;
 	struct device *dev = &pdev->dev;
-	struct device_node *of_node = dev->of_node;
+	struct fwnode_handle *fwnode = dev->fwnode;
 	int r;
 
 	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
@@ -172,7 +172,7 @@ static int gpio_rb91x_key_probe(struct platform_device *pdev)
 	gc->set = gpio_rb91x_key_set;
 	gc->direction_output = gpio_rb91x_key_direction_output;
 	gc->direction_input = gpio_rb91x_key_direction_input;
-	gc->of_node = of_node;
+	gc->fwnode = fwnode;
 
 	platform_set_drvdata(pdev, drvdata);
 
diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 8132849a9a..8f2a9c7723 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -1319,7 +1319,6 @@ static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 	int ring_mask = BIT(ring->order) - 1;
 	int ring_size = BIT(ring->order);
 	struct list_head rx_list;
-	struct sk_buff *next;
 	struct sk_buff *skb;
 	int done = 0;
 
@@ -1379,7 +1378,7 @@ next:
 
 	ag71xx_ring_rx_refill(ag);
 
-	list_for_each_entry_safe(skb, next, &rx_list, list)
+	list_for_each_entry(skb, &rx_list, list)
 		skb->protocol = eth_type_trans(skb, dev);
 	netif_receive_skb_list(&rx_list);
 
diff --git a/target/linux/ath79/generic/base-files/etc/board.d/01_leds b/target/linux/ath79/generic/base-files/etc/board.d/01_leds
index 18fe436dbc..143309a8b2 100644
--- a/target/linux/ath79/generic/base-files/etc/board.d/01_leds
+++ b/target/linux/ath79/generic/base-files/etc/board.d/01_leds
@@ -10,6 +10,10 @@ case "$board" in
 	ucidef_set_led_netdev "lan" "LAN" "orange:eth0" "eth0"
 	ucidef_set_led_switch "wan" "WAN" "orange:eth1" "switch0" "0x04"
 	;;
+8dev,carambola3)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" "link"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" "link"
+	;;
 alcatel,hh40v)
 	ucidef_set_led_netdev "lan_data" "LAN Data" "green:lan" "eth1" "tx rx"
 	ucidef_set_led_netdev "lan_link" "LAN Link" "orange:lan" "eth1" "link"
@@ -228,6 +232,10 @@ compex,wpj531-16m)
 	ucidef_set_led_rssi "sig3" "SIG3" "green:sig3" "wlan0" "65" "100"
 	ucidef_set_led_rssi "sig4" "SIG4" "green:sig4" "wlan0" "50" "100"
 	;;
+dell,apl26-0ae)
+	ucidef_set_led_switch "lan1" "LAN1" "amber:lan-1" "switch0" "0x04"
+	ucidef_set_led_switch "lan2" "LAN2" "amber:lan-2" "switch0" "0x08"
+	;;
 devolo,dlan-pro-1200plus-ac|\
 devolo,magic-2-wifi)
 	ucidef_set_led_netdev "plcw" "dLAN" "white:dlan" "eth0.1" "rx"
diff --git a/target/linux/ath79/generic/base-files/etc/board.d/02_network b/target/linux/ath79/generic/base-files/etc/board.d/02_network
index 6823c333b6..7905d6e496 100644
--- a/target/linux/ath79/generic/base-files/etc/board.d/02_network
+++ b/target/linux/ath79/generic/base-files/etc/board.d/02_network
@@ -146,6 +146,7 @@ ath79_setup_interfaces()
 	elecom,wab-i1750-ps|\
 	elecom,wab-s1167-ps|\
 	elecom,wab-s600-ps|\
+	engenius,ens1750|\
 	engenius,enstationac-v1|\
 	engenius,ews511ap|\
 	engenius,ews660ap|\
@@ -287,6 +288,10 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"1:wan" "5:lan" "6@eth0"
 		;;
+	dell,apl26-0ae)
+		ucidef_add_switch "switch0" \
+			"0@eth0" "2:lan:1" "3:lan:2" "6@eth1"
+		;;
 	devolo,dlan-pro-1200plus-ac|\
 	devolo,magic-2-wifi)
 		ucidef_add_switch "switch0" \
@@ -553,6 +558,10 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "2:lan:1" "3:lan:3" "4:lan:2"
 		;;
+	ubnt,amplifi-router-hd)
+		ucidef_add_switch "switch0" \
+			"0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" "5:lan:4" "1:wan"
+		;;
 	ubnt,edgeswitch-5xp)
 		ucidef_set_interface_wan "eth1"
 		ucidef_add_switch "switch0" \
diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index e5f4870e6f..ddcef7b685 100644
--- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -9,9 +9,6 @@ board=$(board_name)
 case "$FIRMWARE" in
 "ath9k-eeprom-ahb-18100000.wmac.bin")
 	case $board in
-	8dev,lima)
-		caldata_extract "art" 0x1000 0x800
-		;;
 	aruba,ap-115)
 		caldata_extract "oemdata" 0x1000 0x440
 		;;
@@ -92,8 +89,7 @@ case "$FIRMWARE" in
 	avm,fritz300e)
 		caldata_extract_reverse "urloader" 0x1541 0x440
 		;;
-	buffalo,wzr-hp-g450h|\
-	pcs,cap324)
+	buffalo,wzr-hp-g450h)
 		caldata_extract "art" 0x1000 0x440
 		;;
 	dlink,dir-825-c1|\
diff --git a/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh b/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh
index cb93c1b5ab..076a785cbf 100644
--- a/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ath79/generic/base-files/lib/upgrade/platform.sh
@@ -40,6 +40,7 @@ platform_do_upgrade() {
 	engenius,eap300-v2|\
 	engenius,eap600|\
 	engenius,ecb600|\
+	engenius,ens1750|\
 	engenius,ens202ext-v1|\
 	engenius,enstationac-v1|\
 	engenius,ews660ap|\
diff --git a/target/linux/ath79/image/common-mikrotik.mk b/target/linux/ath79/image/common-mikrotik.mk
index b37c8b7197..94c29d8cb6 100644
--- a/target/linux/ath79/image/common-mikrotik.mk
+++ b/target/linux/ath79/image/common-mikrotik.mk
@@ -10,7 +10,7 @@ endef
 define Device/mikrotik_nor
   $(Device/mikrotik)
   DEVICE_PACKAGES := -yafut
-  IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \
+  IMAGE/sysupgrade.bin := append-kernel | yaffs-filesystem -M | \
 	pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
 	check-size | append-metadata
 endef
diff --git a/target/linux/ath79/image/generic-ubnt.mk b/target/linux/ath79/image/generic-ubnt.mk
index a4d118456f..f7bab4b697 100644
--- a/target/linux/ath79/image/generic-ubnt.mk
+++ b/target/linux/ath79/image/generic-ubnt.mk
@@ -18,6 +18,18 @@ define Device/ubnt_aircube-isp
 endef
 TARGET_DEVICES += ubnt_aircube-isp
 
+define Device/ubnt_amplifi-router-hd
+  IMAGE_SIZE := 11264k
+  UBNT_BOARD := AFi-R-HD
+  UBNT_TYPE := AFi-R
+  UBNT_VERSION := 3.6.3
+  SOC := qca9563
+  DEVICE_MODEL := AmpliFi Router HD
+  UBNT_CHIP := qca956x
+  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct kmod-usb2
+endef
+TARGET_DEVICES += ubnt_amplifi-router-hd
+
 define Device/ubnt_bullet-ac
   $(Device/ubnt-2wa)
   DEVICE_MODEL := Bullet AC
diff --git a/target/linux/ath79/image/generic.mk b/target/linux/ath79/image/generic.mk
index bf300dd18d..0da5a0ef8d 100644
--- a/target/linux/ath79/image/generic.mk
+++ b/target/linux/ath79/image/generic.mk
@@ -204,6 +204,16 @@ define Device/8dev_carambola2
 endef
 TARGET_DEVICES += 8dev_carambola2
 
+define Device/8dev_carambola3
+  SOC := qca9531
+  DEVICE_VENDOR := 8devices
+  DEVICE_MODEL := Carambola3
+  DEVICE_PACKAGES := kmod-usb2
+  IMAGE_SIZE := 32768k
+  SUPPORTED_DEVICES += carambola3
+endef
+TARGET_DEVICES += 8dev_carambola3
+
 define Device/8dev_lima
   SOC := qca9531
   DEVICE_VENDOR := 8devices
@@ -934,6 +944,22 @@ define Device/compex_wpj563
 endef
 TARGET_DEVICES += compex_wpj563
 
+define Device/dell_apl26-0ae
+  SOC := qca9550
+  DEVICE_VENDOR := Dell
+  DEVICE_MODEL := SonicPoint
+  DEVICE_VARIANT := ACe (APL26-0AE)
+  DEVICE_ALT0_VENDOR := SonicWall
+  DEVICE_ALT0_MODEL := SonicPoint
+  DEVICE_ALT0_VARIANT := ACe (APL26-0AE)
+  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2
+  KERNEL_SIZE := 5952k
+  IMAGE_SIZE := 31680k
+  IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \
+	append-rootfs | pad-rootfs | check-size | append-metadata
+endef
+TARGET_DEVICES += dell_apl26-0ae
+
 define Device/devolo_dlan-pro-1200plus-ac
   SOC := ar9344
   DEVICE_VENDOR := devolo
@@ -1528,18 +1554,29 @@ define Device/engenius_ews511ap
 endef
 TARGET_DEVICES += engenius_ews511ap
 
-define Device/engenius_ews660ap
+define Device/engenius_ews_dual_ap
   $(Device/senao_loader_okli)
   SOC := qca9558
   DEVICE_VENDOR := EnGenius
-  DEVICE_MODEL := EWS660AP
   DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct
   IMAGE_SIZE := 11584k
   LOADER_FLASH_OFFS := 0x220000
+endef
+
+define Device/engenius_ews660ap
+  $(Device/engenius_ews_dual_ap)
+  DEVICE_MODEL := EWS660AP
   SENAO_IMGNAME := ar71xx-generic-ews660ap
 endef
 TARGET_DEVICES += engenius_ews660ap
 
+define Device/engenius_ens1750
+  $(Device/engenius_ews_dual_ap)
+  DEVICE_MODEL := ENS1750
+  SENAO_IMGNAME := ar71xx-generic-ens1750
+endef
+TARGET_DEVICES += engenius_ens1750
+
 define Device/enterasys_ws-ap3705i
   SOC := ar9344
   DEVICE_VENDOR := Enterasys
diff --git a/target/linux/ath79/mikrotik/config-default b/target/linux/ath79/mikrotik/config-default
index a231188c83..3fe5cd4979 100644
--- a/target/linux/ath79/mikrotik/config-default
+++ b/target/linux/ath79/mikrotik/config-default
@@ -3,7 +3,7 @@ CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_ZSTD=y
-CONFIG_GPIO_LATCH=y
+CONFIG_GPIO_LATCH_MIKROTIK=y
 CONFIG_GPIO_RB4XX=y
 CONFIG_GPIO_RB91X_KEY=y
 CONFIG_GPIO_WATCHDOG=y
diff --git a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
index c4ccb04f5b..ca722040f6 100644
--- a/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
+++ b/target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
@@ -9,9 +9,6 @@ board=$(board_name)
 case "$FIRMWARE" in
 "ath9k-eeprom-ahb-18100000.wmac.bin")
 	case $board in
-	8dev,rambutan)
-		caldata_extract "caldata" 0x1000 0x800
-		;;
 	meraki,mr18)
 		. /lib/upgrade/nand.sh
 
diff --git a/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch b/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
index e1c6835afd..6c97bc307c 100644
--- a/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
+++ b/target/linux/ath79/patches-6.1/900-unaligned_access_hacks.patch
@@ -579,7 +579,7 @@ SVN-Revision: 35130
  			goto next_ht;
 --- a/net/ipv6/ip6_offload.c
 +++ b/net/ipv6/ip6_offload.c
-@@ -259,7 +259,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+@@ -290,7 +290,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
  			continue;
  
  		iph2 = (struct ipv6hdr *)(p->data + off);
@@ -858,16 +858,25 @@ SVN-Revision: 35130
  
 --- a/net/ipv4/tcp_offload.c
 +++ b/net/ipv4/tcp_offload.c
-@@ -220,7 +220,7 @@ struct sk_buff *tcp_gro_receive(struct l
+@@ -62,7 +62,7 @@ static struct sk_buff *__tcpv4_gso_segme
+ 	th2 = tcp_hdr(seg->next);
+ 	iph2 = ip_hdr(seg->next);
  
- 		th2 = tcp_hdr(p);
+-	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	if (!(net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) &&
+ 	    iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
+ 		return segs;
+ 
+@@ -254,7 +254,7 @@ struct sk_buff *tcp_gro_lookup(struct li
+ 			continue;
  
+ 		th2 = tcp_hdr(p);
 -		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
 +		if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
  			NAPI_GRO_CB(p)->same_flow = 0;
  			continue;
  		}
-@@ -238,8 +238,8 @@ found:
+@@ -320,8 +320,8 @@ struct sk_buff *tcp_gro_receive(struct l
  		  ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
  	flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
  	for (i = sizeof(*th); i < thlen; i += 4)
diff --git a/target/linux/ath79/patches-6.1/911-mikrotik-rb91x.patch b/target/linux/ath79/patches-6.1/911-mikrotik-rb91x.patch
index 768ab6fb49..677428fa65 100644
--- a/target/linux/ath79/patches-6.1/911-mikrotik-rb91x.patch
+++ b/target/linux/ath79/patches-6.1/911-mikrotik-rb91x.patch
@@ -33,7 +33,7 @@ Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
  
  	  If unsure, say N.
  
-+config GPIO_LATCH
++config GPIO_LATCH_MIKROTIK
 +	tristate "MikroTik RouterBOARD GPIO latch support"
 +	depends on ATH79
 +	help
@@ -59,7 +59,7 @@ Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
  obj-$(CONFIG_GPIO_IXP4XX)		+= gpio-ixp4xx.o
  obj-$(CONFIG_GPIO_JANZ_TTL)		+= gpio-janz-ttl.o
  obj-$(CONFIG_GPIO_KEMPLD)		+= gpio-kempld.o
-+obj-$(CONFIG_GPIO_LATCH)		+= gpio-latch.o
++obj-$(CONFIG_GPIO_LATCH_MIKROTIK)	+= gpio-latch-mikrotik.o
  obj-$(CONFIG_GPIO_LOGICVC)		+= gpio-logicvc.o
  obj-$(CONFIG_GPIO_LOONGSON1)		+= gpio-loongson1.o
  obj-$(CONFIG_GPIO_LOONGSON)		+= gpio-loongson.o
diff --git a/target/linux/ath79/patches-6.6/100-reset-ath79-read-back-reset-register.patch b/target/linux/ath79/patches-6.6/100-reset-ath79-read-back-reset-register.patch
new file mode 100644
index 0000000000..7aa501514d
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/100-reset-ath79-read-back-reset-register.patch
@@ -0,0 +1,33 @@
+From 661edfc3dab943a67c8821353b63cc23057f7ce9 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Tue, 9 Jan 2024 20:48:46 +0100
+Subject: [PATCH] reset: ath79: read back reset register
+
+Read back the reset register in order to flush the cache. This fixes
+spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
+DRAM chips.
+
+This issue was fixed in the past, but switching to the reset-driver
+specific implementation removed the old fix.
+
+Link: https://github.com/freifunk-gluon/gluon/issues/2904
+Link: https://github.com/openwrt/openwrt/issues/13043
+Link: https://dev.archive.openwrt.org/ticket/17839
+Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/reset/reset-ath79.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/reset/reset-ath79.c
++++ b/drivers/reset/reset-ath79.c
+@@ -37,6 +37,8 @@ static int ath79_reset_update(struct res
+ 	else
+ 		val &= ~BIT(id);
+ 	writel(val, ath79_reset->base);
++	/* Flush cache */
++	readl(ath79_reset->base);
+ 	spin_unlock_irqrestore(&ath79_reset->lock, flags);
+ 
+ 	return 0;
diff --git a/target/linux/ath79/patches-6.6/300-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch b/target/linux/ath79/patches-6.6/300-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch
new file mode 100644
index 0000000000..ceda511c21
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/300-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch
@@ -0,0 +1,168 @@
+From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 09:55:13 +0100
+Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
+ QCA9556 SoCs
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/irqchip/Makefile         |   1 +
+ drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 143 insertions(+)
+ create mode 100644 drivers/irqchip/irq-ath79-intc.c
+
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
+ obj-$(CONFIG_AL_FIC)			+= irq-al-fic.o
+ obj-$(CONFIG_ALPINE_MSI)		+= irq-alpine-msi.o
+ obj-$(CONFIG_ATH79)			+= irq-ath79-cpu.o
++obj-$(CONFIG_ATH79)			+= irq-ath79-intc.o
+ obj-$(CONFIG_ATH79)			+= irq-ath79-misc.o
+ obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
+ obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
+--- /dev/null
++++ b/drivers/irqchip/irq-ath79-intc.c
+@@ -0,0 +1,142 @@
++/*
++ *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
++ *
++ *  Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/irqchip.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++
++#include <asm/irq_cpu.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#define ATH79_MAX_INTC_CASCADE	3
++
++struct ath79_intc {
++	struct irq_chip chip;
++	u32 irq;
++	u32 pending_mask;
++	u32 int_status;
++	u32 irq_mask[ATH79_MAX_INTC_CASCADE];
++	u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];
++};
++
++static void ath79_intc_irq_handler(struct irq_desc *desc)
++{
++	struct irq_domain *domain = irq_desc_get_handler_data(desc);
++	struct ath79_intc *intc = domain->host_data;
++	u32 pending;
++
++	pending = ath79_reset_rr(intc->int_status);
++	pending &= intc->pending_mask;
++
++	if (pending) {
++		int i;
++
++		for (i = 0; i < domain->hwirq_max; i++)
++			if (pending & intc->irq_mask[i]) {
++				if (intc->irq_wb_chan[i] != 0xffffffff)
++					ath79_ddr_wb_flush(intc->irq_wb_chan[i]);
++				generic_handle_irq(irq_find_mapping(domain, i));
++			}
++	} else {
++		spurious_interrupt();
++	}
++}
++
++static void ath79_intc_irq_enable(struct irq_data *d)
++{
++	struct ath79_intc *intc = d->domain->host_data;
++	enable_irq(intc->irq);
++}
++
++static void ath79_intc_irq_disable(struct irq_data *d)
++{
++	struct ath79_intc *intc = d->domain->host_data;
++	disable_irq(intc->irq);
++}
++
++static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++	struct ath79_intc *intc = d->host_data;
++
++	irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ath79_irq_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = ath79_intc_map,
++};
++
++static int __init ath79_intc_of_init(
++	struct device_node *node, struct device_node *parent)
++{
++	struct irq_domain *domain;
++	struct ath79_intc *intc;
++	int cnt, cntwb, i, err;
++
++	cnt = of_property_count_u32_elems(node, "qca,pending-bits");
++	if (cnt > ATH79_MAX_INTC_CASCADE)
++		panic("Too many INTC pending bits\n");
++
++	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
++	if (!intc)
++		panic("Failed to allocate INTC memory\n");
++	intc->chip = dummy_irq_chip;
++	intc->chip.name = "INTC";
++	intc->chip.irq_disable = ath79_intc_irq_disable;
++	intc->chip.irq_enable = ath79_intc_irq_enable;
++
++	if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) {
++		panic("Missing address of interrupt status register\n");
++	}
++
++	of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt);
++	for (i = 0; i < cnt; i++) {
++		intc->pending_mask |= intc->irq_mask[i];
++		intc->irq_wb_chan[i] = 0xffffffff;
++	}
++
++	cntwb = of_count_phandle_with_args(
++		node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
++
++	for (i = 0; i < cntwb; i++) {
++		struct of_phandle_args args;
++		u32 irq = i;
++
++		of_property_read_u32_index(
++			node, "qca,ddr-wb-channel-interrupts", i, &irq);
++		if (irq >= ATH79_MAX_INTC_CASCADE)
++			continue;
++
++		err = of_parse_phandle_with_args(
++			node, "qca,ddr-wb-channels",
++			"#qca,ddr-wb-channel-cells",
++			i, &args);
++		if (err)
++			return err;
++
++		intc->irq_wb_chan[irq] = args.args[0];
++	}
++
++	intc->irq = irq_of_parse_and_map(node, 0);
++	if (!intc->irq)
++		panic("Failed to get INTC IRQ");
++
++	domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
++	irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
++
++	return 0;
++}
++IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc",
++		ath79_intc_of_init);
diff --git a/target/linux/ath79/patches-6.6/301-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch b/target/linux/ath79/patches-6.6/301-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch
new file mode 100644
index 0000000000..13117d9a8e
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/301-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch
@@ -0,0 +1,23 @@
+From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 09:58:19 +0100
+Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/irqchip/irq-ath79-cpu.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/irqchip/irq-ath79-cpu.c
++++ b/drivers/irqchip/irq-ath79-cpu.c
+@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init(
+ }
+ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
+ 		ar79_cpu_intc_of_init);
+-
+-void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
+-{
+-	irq_wb_chan[2] = irq_wb_chan2;
+-	irq_wb_chan[3] = irq_wb_chan3;
+-	mips_cpu_irq_init();
+-}
diff --git a/target/linux/ath79/patches-6.6/310-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch b/target/linux/ath79/patches-6.6/310-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch
new file mode 100644
index 0000000000..cf0a75c791
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/310-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch
@@ -0,0 +1,57 @@
+From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:10 +0200
+Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7100-pci.txt    | 38 ++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+@@ -0,0 +1,38 @@
++* Qualcomm Atheros AR7100 PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7100-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++	- "cfg_base"	IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++	properties to define the mapping of the PCIe interface to interrupt
++	numbers.
++- #interrupt-cells: set to <1>
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++Optional properties:
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++* Example for ar7100
++	pcie@180c0000 {
++		compatible = "qca,ar7100-pci";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x0 0x0>;
++		reg = <0x17010000 0x100>;
++		reg-names = "cfg_base";
++		ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
++			  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++		interrupt-parent = <&cpuintc>;
++		interrupts = <2>;
++
++		interrupt-controller;
++		#interrupt-cells = <1>;
++
++		interrupt-map-mask = <0 0 0 1>;
++		interrupt-map = <0 0 0 0 &pcie0 0>;
++	};
diff --git a/target/linux/ath79/patches-6.6/311-MIPS-pci-ar71xx-convert-to-OF.patch b/target/linux/ath79/patches-6.6/311-MIPS-pci-ar71xx-convert-to-OF.patch
new file mode 100644
index 0000000000..9a315aed0b
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/311-MIPS-pci-ar71xx-convert-to-OF.patch
@@ -0,0 +1,206 @@
+From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:23 +0200
+Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
+ 1 file changed, 41 insertions(+), 41 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -15,8 +15,11 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+ 
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -46,12 +49,13 @@
+ #define AR71XX_PCI_IRQ_COUNT		5
+ 
+ struct ar71xx_pci_controller {
++	struct device_node *np;
+ 	void __iomem *cfg_base;
+ 	int irq;
+-	int irq_base;
+ 	struct pci_controller pci_ctrl;
+ 	struct resource io_res;
+ 	struct resource mem_res;
++	struct irq_domain *domain;
+ };
+ 
+ /* Byte lane enable bits */
+@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = {
+ 
+ static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+ {
+-	struct ar71xx_pci_controller *apc;
+ 	void __iomem *base = ath79_reset_base;
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
+ 	u32 pending;
+ 
+-	apc = irq_desc_get_handler_data(desc);
+-
++	chained_irq_enter(chip, desc);
+ 	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ 		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 
+ 	if (pending & AR71XX_PCI_INT_DEV0)
+-		generic_handle_irq(apc->irq_base + 0);
++		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV1)
+-		generic_handle_irq(apc->irq_base + 1);
++		generic_handle_irq(irq_linear_revmap(apc->domain, 2));
+ 
+ 	else if (pending & AR71XX_PCI_INT_DEV2)
+-		generic_handle_irq(apc->irq_base + 2);
++		generic_handle_irq(irq_linear_revmap(apc->domain, 3));
+ 
+ 	else if (pending & AR71XX_PCI_INT_CORE)
+-		generic_handle_irq(apc->irq_base + 4);
++		generic_handle_irq(irq_linear_revmap(apc->domain, 4));
+ 
+ 	else
+ 		spurious_interrupt();
++	chained_irq_exit(chip, desc);
+ }
+ 
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+-	irq = d->irq - apc->irq_base;
++	irq = irq_linear_revmap(apc->domain, d->irq);
+ 
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+-	irq = d->irq - apc->irq_base;
++	irq = irq_linear_revmap(apc->domain, d->irq);
+ 
+ 	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch
+ 	.irq_mask_ack	= ar71xx_pci_irq_mask,
+ };
+ 
++static int ar71xx_pci_irq_map(struct irq_domain *d,
++			      unsigned int irq, irq_hw_number_t hw)
++{
++	struct ar71xx_pci_controller *apc = d->host_data;
++
++	irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
++	irq_set_chip_data(irq, apc);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ar71xx_pci_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = ar71xx_pci_irq_map,
++};
++
+ static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ 	void __iomem *base = ath79_reset_base;
+-	int i;
+ 
+ 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+ 
+-	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+-
+-	apc->irq_base = ATH79_PCI_IRQ_BASE;
+-	for (i = apc->irq_base;
+-	     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+-		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+-					 handle_level_irq);
+-		irq_set_chip_data(i, apc);
+-	}
+-
++	apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
++					    &ar71xx_pci_domain_ops, apc);
+ 	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
+ 					 apc);
+ }
+@@ -325,10 +337,14 @@ static void ar71xx_pci_reset(void)
+ 	mdelay(100);
+ }
+ 
++static const struct of_device_id ar71xx_pci_ids[] = {
++	{ .compatible = "qca,ar7100-pci" },
++	{},
++};
++
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ 	struct ar71xx_pci_controller *apc;
+-	struct resource *res;
+ 	u32 t;
+ 
+ 	apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
+@@ -345,26 +361,6 @@ static int ar71xx_pci_probe(struct platf
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+-	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+-	if (!res)
+-		return -EINVAL;
+-
+-	apc->io_res.parent = res;
+-	apc->io_res.name = "PCI IO space";
+-	apc->io_res.start = res->start;
+-	apc->io_res.end = res->end;
+-	apc->io_res.flags = IORESOURCE_IO;
+-
+-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+-	if (!res)
+-		return -EINVAL;
+-
+-	apc->mem_res.parent = res;
+-	apc->mem_res.name = "PCI memory space";
+-	apc->mem_res.start = res->start;
+-	apc->mem_res.end = res->end;
+-	apc->mem_res.flags = IORESOURCE_MEM;
+-
+ 	ar71xx_pci_reset();
+ 
+ 	/* setup COMMAND register */
+@@ -377,9 +373,11 @@ static int ar71xx_pci_probe(struct platf
+ 
+ 	ar71xx_pci_irq_init(apc);
+ 
++	apc->np = pdev->dev.of_node;
+ 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+ 	apc->pci_ctrl.mem_resource = &apc->mem_res;
+ 	apc->pci_ctrl.io_resource = &apc->io_res;
++	pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
+ 
+ 	register_pci_controller(&apc->pci_ctrl);
+ 
+@@ -390,6 +388,7 @@ static struct platform_driver ar71xx_pci
+ 	.probe = ar71xx_pci_probe,
+ 	.driver = {
+ 		.name = "ar71xx-pci",
++		.of_match_table = of_match_ptr(ar71xx_pci_ids),
+ 	},
+ };
+ 
diff --git a/target/linux/ath79/patches-6.6/312-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch b/target/linux/ath79/patches-6.6/312-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch
new file mode 100644
index 0000000000..a32c9bdcde
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/312-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch
@@ -0,0 +1,61 @@
+From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:02 +0200
+Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7240-pci.txt    | 42 ++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+@@ -0,0 +1,42 @@
++* Qualcomm Atheros AR724X PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7240-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++	- "crp_base"	Configuration registers
++	- "ctrl_base"	Control registers
++	- "cfg_base"	IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++	properties to define the mapping of the PCIe interface to interrupt
++	numbers.
++- #interrupt-cells: set to <1>
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++Optional properties:
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++* Example for qca9557
++	pcie@180c0000 {
++		compatible = "qcom,ar7240-pci";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x0 0x0>;
++		reg = <0x180c0000 0x1000>,
++		      <0x180f0000 0x100>,
++		      <0x14000000 0x1000>;
++		reg-names = "crp_base", "ctrl_base", "cfg_base";
++		ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
++			  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++		interrupt-parent = <&intc2>;
++		interrupts = <1>;
++
++		interrupt-controller;
++		#interrupt-cells = <1>;
++
++		interrupt-map-mask = <0 0 0 1>;
++		interrupt-map = <0 0 0 0 &pcie0 0>;
++	};
diff --git a/target/linux/ath79/patches-6.6/313-MIPS-pci-ar724x-convert-to-OF.patch b/target/linux/ath79/patches-6.6/313-MIPS-pci-ar724x-convert-to-OF.patch
new file mode 100644
index 0000000000..7927c1cbf5
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/313-MIPS-pci-ar724x-convert-to-OF.patch
@@ -0,0 +1,213 @@
+From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:37 +0200
+Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
+ 1 file changed, 42 insertions(+), 46 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,8 +11,11 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+ 
+ #define AR724X_PCI_REG_APP		0x00
+ #define AR724X_PCI_REG_RESET		0x18
+@@ -42,17 +45,20 @@ struct ar724x_pci_controller {
+ 	void __iomem *crp_base;
+ 
+ 	int irq;
+-	int irq_base;
+ 
+ 	bool link_up;
+ 	bool bar0_is_cached;
+ 	u32  bar0_value;
+ 
++	struct device_node *np;
+ 	struct pci_controller pci_controller;
++	struct irq_domain *domain;
+ 	struct resource io_res;
+ 	struct resource mem_res;
+ };
+ 
++static struct irq_chip ar724x_pci_irq_chip;
++
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ 	u32 reset;
+@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = {
+ 
+ static void ar724x_pci_irq_handler(struct irq_desc *desc)
+ {
+-	struct ar724x_pci_controller *apc;
+-	void __iomem *base;
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
+ 	u32 pending;
+ 
+-	apc = irq_desc_get_handler_data(desc);
+-	base = apc->ctrl_base;
+-
+-	pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+-		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++	chained_irq_enter(chip, desc);
++	pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
++		  __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
+ 
+ 	if (pending & AR724X_PCI_INT_DEV0)
+-		generic_handle_irq(apc->irq_base + 0);
+-
++		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+ 	else
+ 		spurious_interrupt();
++	chained_irq_exit(chip, desc);
+ }
+ 
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+-	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
+-	offset = apc->irq_base - d->irq;
+ 
+-	switch (offset) {
++	switch (irq_linear_revmap(apc->domain, d->irq)) {
+ 	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t | AR724X_PCI_INT_DEV0,
+@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ 	struct ar724x_pci_controller *apc;
+ 	void __iomem *base;
+-	int offset;
+ 	u32 t;
+ 
+ 	apc = irq_data_get_irq_chip_data(d);
+ 	base = apc->ctrl_base;
+-	offset = apc->irq_base - d->irq;
+ 
+-	switch (offset) {
++	switch (irq_linear_revmap(apc->domain, d->irq)) {
+ 	case 0:
+ 		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ 		__raw_writel(t & ~AR724X_PCI_INT_DEV0,
+@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch
+ 	.irq_mask_ack	= ar724x_pci_irq_mask,
+ };
+ 
++static int ar724x_pci_irq_map(struct irq_domain *d,
++			      unsigned int irq, irq_hw_number_t hw)
++{
++	struct ar724x_pci_controller *apc = d->host_data;
++
++	irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
++	irq_set_chip_data(irq, apc);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ar724x_pci_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = ar724x_pci_irq_map,
++};
++
+ static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
+ 				int id)
+ {
+ 	void __iomem *base;
+-	int i;
+ 
+ 	base = apc->ctrl_base;
+ 
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ 	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+ 
+-	apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+-
+-	for (i = apc->irq_base;
+-	     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+-		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+-					 handle_level_irq);
+-		irq_set_chip_data(i, apc);
+-	}
+-
++	apc->domain = irq_domain_add_linear(apc->np, 2,
++					    &ar724x_pci_domain_ops, apc);
+ 	irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
+ 					 apc);
+ }
+@@ -360,7 +368,6 @@ static void ar724x_pci_hw_init(struct ar
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ 	struct ar724x_pci_controller *apc;
+-	struct resource *res;
+ 	int id;
+ 
+ 	id = pdev->id;
+@@ -388,29 +395,11 @@ static int ar724x_pci_probe(struct platf
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
+-	res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+-	if (!res)
+-		return -EINVAL;
+-
+-	apc->io_res.parent = res;
+-	apc->io_res.name = "PCI IO space";
+-	apc->io_res.start = res->start;
+-	apc->io_res.end = res->end;
+-	apc->io_res.flags = IORESOURCE_IO;
+-
+-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+-	if (!res)
+-		return -EINVAL;
+-
+-	apc->mem_res.parent = res;
+-	apc->mem_res.name = "PCI memory space";
+-	apc->mem_res.start = res->start;
+-	apc->mem_res.end = res->end;
+-	apc->mem_res.flags = IORESOURCE_MEM;
+-
++	apc->np = pdev->dev.of_node;
+ 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
+ 	apc->pci_controller.io_resource = &apc->io_res;
+ 	apc->pci_controller.mem_resource = &apc->mem_res;
++	pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
+ 
+ 	/*
+ 	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+@@ -432,10 +421,16 @@ static int ar724x_pci_probe(struct platf
+ 	return 0;
+ }
+ 
++static const struct of_device_id ar724x_pci_ids[] = {
++	{ .compatible = "qcom,ar7240-pci" },
++	{},
++};
++
+ static struct platform_driver ar724x_pci_driver = {
+ 	.probe = ar724x_pci_probe,
+ 	.driver = {
+ 		.name = "ar724x-pci",
++		.of_match_table = of_match_ptr(ar724x_pci_ids),
+ 	},
+ };
+ 
diff --git a/target/linux/ath79/patches-6.6/314-MIPS-ath79-remove-irq-code-from-pci.patch b/target/linux/ath79/patches-6.6/314-MIPS-ath79-remove-irq-code-from-pci.patch
new file mode 100644
index 0000000000..01549eec68
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/314-MIPS-ath79-remove-irq-code-from-pci.patch
@@ -0,0 +1,149 @@
+From: John Crispin <john@phrozen.org>
+Subject: ath79: fix remove irq code from pci driver patch
+
+This patch got mangled in the void while rebasing it.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar71xx.c                    | 107 ------------------
+ 1 file changed, 141 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -51,11 +51,9 @@
+ struct ar71xx_pci_controller {
+ 	struct device_node *np;
+ 	void __iomem *cfg_base;
+-	int irq;
+ 	struct pci_controller pci_ctrl;
+ 	struct resource io_res;
+ 	struct resource mem_res;
+-	struct irq_domain *domain;
+ };
+ 
+ /* Byte lane enable bits */
+@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ 	.write	= ar71xx_pci_write_config,
+ };
+ 
+-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+-{
+-	void __iomem *base = ath79_reset_base;
+-	struct irq_chip *chip = irq_desc_get_chip(desc);
+-	struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
+-	u32 pending;
+-
+-	chained_irq_enter(chip, desc);
+-	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+-		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+-	if (pending & AR71XX_PCI_INT_DEV0)
+-		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+-
+-	else if (pending & AR71XX_PCI_INT_DEV1)
+-		generic_handle_irq(irq_linear_revmap(apc->domain, 2));
+-
+-	else if (pending & AR71XX_PCI_INT_DEV2)
+-		generic_handle_irq(irq_linear_revmap(apc->domain, 3));
+-
+-	else if (pending & AR71XX_PCI_INT_CORE)
+-		generic_handle_irq(irq_linear_revmap(apc->domain, 4));
+-
+-	else
+-		spurious_interrupt();
+-	chained_irq_exit(chip, desc);
+-}
+-
+-static void ar71xx_pci_irq_unmask(struct irq_data *d)
+-{
+-	struct ar71xx_pci_controller *apc;
+-	unsigned int irq;
+-	void __iomem *base = ath79_reset_base;
+-	u32 t;
+-
+-	apc = irq_data_get_irq_chip_data(d);
+-	irq = irq_linear_revmap(apc->domain, d->irq);
+-
+-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+-	/* flush write */
+-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-}
+-
+-static void ar71xx_pci_irq_mask(struct irq_data *d)
+-{
+-	struct ar71xx_pci_controller *apc;
+-	unsigned int irq;
+-	void __iomem *base = ath79_reset_base;
+-	u32 t;
+-
+-	apc = irq_data_get_irq_chip_data(d);
+-	irq = irq_linear_revmap(apc->domain, d->irq);
+-
+-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+-	/* flush write */
+-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-}
+-
+-static struct irq_chip ar71xx_pci_irq_chip = {
+-	.name		= "AR71XX PCI",
+-	.irq_mask	= ar71xx_pci_irq_mask,
+-	.irq_unmask	= ar71xx_pci_irq_unmask,
+-	.irq_mask_ack	= ar71xx_pci_irq_mask,
+-};
+-
+-static int ar71xx_pci_irq_map(struct irq_domain *d,
+-			      unsigned int irq, irq_hw_number_t hw)
+-{
+-	struct ar71xx_pci_controller *apc = d->host_data;
+-
+-	irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
+-	irq_set_chip_data(irq, apc);
+-
+-	return 0;
+-}
+-
+-static const struct irq_domain_ops ar71xx_pci_domain_ops = {
+-	.xlate = irq_domain_xlate_onecell,
+-	.map = ar71xx_pci_irq_map,
+-};
+-
+-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+-{
+-	void __iomem *base = ath79_reset_base;
+-
+-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+-
+-	apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
+-					    &ar71xx_pci_domain_ops, apc);
+-	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
+-					 apc);
+-}
+-
+ static void ar71xx_pci_reset(void)
+ {
+ 	ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
+@@ -357,10 +257,6 @@ static int ar71xx_pci_probe(struct platf
+ 	if (IS_ERR(apc->cfg_base))
+ 		return PTR_ERR(apc->cfg_base);
+ 
+-	apc->irq = platform_get_irq(pdev, 0);
+-	if (apc->irq < 0)
+-		return -EINVAL;
+-
+ 	ar71xx_pci_reset();
+ 
+ 	/* setup COMMAND register */
+@@ -371,8 +267,6 @@ static int ar71xx_pci_probe(struct platf
+ 	/* clear bus errors */
+ 	ar71xx_pci_check_error(apc, 1);
+ 
+-	ar71xx_pci_irq_init(apc);
+-
+ 	apc->np = pdev->dev.of_node;
+ 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+ 	apc->pci_ctrl.mem_resource = &apc->mem_res;
diff --git a/target/linux/ath79/patches-6.6/315-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch b/target/linux/ath79/patches-6.6/315-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch
new file mode 100644
index 0000000000..375dec8ba2
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/315-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch
@@ -0,0 +1,130 @@
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 11 Apr 2020 14:03:12 +0200
+Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
+
+The QCA9550 family of SoCs have a slightly different reset
+sequence compared to older chips.
+
+Normally the bootloader performs this sequence, however
+some bootloader implementation expect the operating system
+to clear the reset.
+
+Also get the resets from OF to support handling of the second
+PCIe root-complex on the QCA9558.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -390,6 +390,7 @@
+ #define QCA955X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG		0x04
+ #define QCA955X_PLL_CLK_CTRL_REG		0x08
++#define QCA955X_PLL_PCIE_CONFIG_REG		0x0c
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+ #define QCA955X_PLL_ETH_SGMII_SERDES_REG	0x4c
+@@ -475,6 +476,9 @@
+ #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
+ #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
+ 
++#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD			BIT(30)
++#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS		BIT(16)
++
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB		BIT(5)
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1		BIT(6)
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL		BIT(7)
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -8,6 +8,7 @@
+ 
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/reset.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
+@@ -55,6 +56,9 @@ struct ar724x_pci_controller {
+ 	struct irq_domain *domain;
+ 	struct resource io_res;
+ 	struct resource mem_res;
++
++	struct reset_control *hc_reset;
++	struct reset_control *phy_reset;
+ };
+ 
+ static struct irq_chip ar724x_pci_irq_chip;
+@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar
+ 	int wait = 0;
+ 
+ 	/* deassert PCIe host controller and PCIe PHY reset */
+-	ath79_device_reset_clear(AR724X_RESET_PCIE);
+-	ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++	reset_control_deassert(apc->hc_reset);
++	reset_control_deassert(apc->phy_reset);
+ 
+-	/* remove the reset of the PCIE PLL */
+-	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+-	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+-	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+-
+-	/* deassert bypass for the PCIE PLL */
+-	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+-	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+-	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
++		/* remove the reset of the PCIE PLL */
++		ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
++		ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
++		ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
++
++		/* deassert bypass for the PCIE PLL */
++		ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
++		ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
++		ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
++	} else {
++		/* remove the reset of the PCIE PLL */
++		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
++		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++		/* deassert bypass for the PCIE PLL */
++		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	}
+ 
+ 	/* set PCIE Application Control to ready */
+ 	app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
+@@ -395,6 +411,14 @@ static int ar724x_pci_probe(struct platf
+ 	if (apc->irq < 0)
+ 		return -EINVAL;
+ 
++	apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
++	if (IS_ERR(apc->hc_reset))
++		return PTR_ERR(apc->hc_reset);
++
++	apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
++	if (IS_ERR(apc->phy_reset))
++		return PTR_ERR(apc->phy_reset);
++
+ 	apc->np = pdev->dev.of_node;
+ 	apc->pci_controller.pci_ops = &ar724x_pci_ops;
+ 	apc->pci_controller.io_resource = &apc->io_res;
+@@ -405,7 +429,7 @@ static int ar724x_pci_probe(struct platf
+ 	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+ 	 * host controller is in reset.
+ 	 */
+-	if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
++	if (reset_control_status(apc->hc_reset))
+ 		ar724x_pci_hw_init(apc);
+ 
+ 	apc->link_up = ar724x_pci_check_link(apc);
+@@ -423,6 +447,7 @@ static int ar724x_pci_probe(struct platf
+ 
+ static const struct of_device_id ar724x_pci_ids[] = {
+ 	{ .compatible = "qcom,ar7240-pci" },
++	{ .compatible = "qcom,qca9550-pci" },
+ 	{},
+ };
+ 
diff --git a/target/linux/ath79/patches-6.6/316-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ath79/patches-6.6/316-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
new file mode 100644
index 0000000000..1e2715b84c
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/316-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
@@ -0,0 +1,109 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: [PATCH] ar71xx: swizzle address for PCI byte/word access on AR71xx
+
+Closes #11683.
+
+SVN-Revision: 32639
+---
+ .../mips/include/asm/mach-ath79/mangle-port.h | 111 ++++++++++++++++++
+ 1 file changed, 111 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ath79/mangle-port.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
++/*
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
++ *      Copyright (C) 2003, 2004 Ralf Baechle
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
++#define __ASM_MACH_ATH79_MANGLE_PORT_H
++
++#ifdef CONFIG_PCI_AR71XX
++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
++#else
++#define ath79_pci_swizzle_b(port) (port)
++#define ath79_pci_swizzle_w(port) (port)
++#endif
++
++#define __swizzle_addr_b(port)	ath79_pci_swizzle_b(port)
++#define __swizzle_addr_w(port)	ath79_pci_swizzle_w(port)
++#define __swizzle_addr_l(port)	(port)
++#define __swizzle_addr_q(port)	(port)
++
++# define ioswabb(a, x)           (x)
++# define __mem_ioswabb(a, x)     (x)
++# define ioswabw(a, x)           (x)
++# define __mem_ioswabw(a, x)     cpu_to_le16(x)
++# define ioswabl(a, x)           (x)
++# define __mem_ioswabl(a, x)     cpu_to_le32(x)
++# define ioswabq(a, x)           (x)
++# define __mem_ioswabq(a, x)     cpu_to_le64(x)
++
++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]
+ 	0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
+ };
+ 
++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
++
++static inline bool ar71xx_is_pci_addr(unsigned long port)
++{
++	unsigned long phys = CPHYSADDR(port);
++
++	return (phys >= AR71XX_PCI_MEM_BASE &&
++		phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
++}
++
++static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
++}
++
++static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
++{
++	return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
++}
++
++unsigned long ath79_pci_swizzle_b(unsigned long port)
++{
++	if (__ath79_pci_swizzle_b)
++		return __ath79_pci_swizzle_b(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_b);
++
++unsigned long ath79_pci_swizzle_w(unsigned long port)
++{
++	if (__ath79_pci_swizzle_w)
++		return __ath79_pci_swizzle_w(port);
++
++	return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_w);
++
+ static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
+ {
+ 	u32 t;
+@@ -275,6 +314,9 @@ static int ar71xx_pci_probe(struct platf
+ 
+ 	register_pci_controller(&apc->pci_ctrl);
+ 
++	__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
++	__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/ath79/patches-6.6/330-missing-registers.patch b/target/linux/ath79/patches-6.6/330-missing-registers.patch
new file mode 100644
index 0000000000..74789437ec
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/330-missing-registers.patch
@@ -0,0 +1,20 @@
+From: Christian Lamparter <chunkeey@gmail.com>
+Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for
+
+    ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
+
+    Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1231,6 +1231,10 @@
+ #define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
+ #define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
++#define AR934X_ETH_CFG_TXD_DELAY_MASK   0x3
++#define AR934X_ETH_CFG_TXD_DELAY_SHIFT  18
++#define AR934X_ETH_CFG_TXE_DELAY_MASK   0x3
++#define AR934X_ETH_CFG_TXE_DELAY_SHIFT  20
+ 
+ /*
+  * QCA953X GMAC Interface
diff --git a/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch
new file mode 100644
index 0000000000..c2f228dfe1
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/331-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch
@@ -0,0 +1,90 @@
+From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Mon, 18 Mar 2019 00:54:06 +0100
+Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
+
+This adds missing GMAC register definitions for the Qualcomm Atheros
+QCA955X series MIPS SoCs.
+
+They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
+Repeater 450E's GPL tarball.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1251,7 +1251,12 @@
+  */
+ 
+ #define QCA955X_GMAC_REG_ETH_CFG	0x00
++#define QCA955X_GMAC_REG_SGMII_RESET	0x14
+ #define QCA955X_GMAC_REG_SGMII_SERDES	0x18
++#define QCA955X_GMAC_REG_MR_AN_CONTROL	0x1c
++#define QCA955X_GMAC_REG_MR_AN_STATUS	0x20
++#define QCA955X_GMAC_REG_SGMII_CONFIG	0x34
++#define QCA955X_GMAC_REG_SGMII_DEBUG	0x58
+ 
+ #define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
+ #define QCA955X_ETH_CFG_MII_GE0		BIT(1)
+@@ -1273,9 +1278,58 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK	0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT	20
+ 
++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET	0
++#define QCA955X_SGMII_RESET_RX_CLK_N		BIT(0)
++#define QCA955X_SGMII_RESET_TX_CLK_N		BIT(1)
++#define QCA955X_SGMII_RESET_RX_125M_N		BIT(2)
++#define QCA955X_SGMII_RESET_TX_125M_N		BIT(3)
++#define QCA955X_SGMII_RESET_HW_RX_125M_N	BIT(4)
++
+ #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++
++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1	BIT(6)
++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE	BIT(8)
++#define QCA955X_MR_AN_CONTROL_RESTART_AN	BIT(9)
++#define QCA955X_MR_AN_CONTROL_POWER_DOWN	BIT(11)
++#define QCA955X_MR_AN_CONTROL_AN_ENABLE		BIT(12)
++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0	BIT(13)
++#define QCA955X_MR_AN_CONTROL_LOOPBACK		BIT(14)
++#define QCA955X_MR_AN_CONTROL_PHY_RESET		BIT(15)
++
++#define QCA955X_MR_AN_STATUS_EXT_CAP		BIT(0)
++#define QCA955X_MR_AN_STATUS_LINK_UP		BIT(2)
++#define QCA955X_MR_AN_STATUS_AN_ABILITY		BIT(3)
++#define QCA955X_MR_AN_STATUS_REMOTE_FAULT	BIT(4)
++#define QCA955X_MR_AN_STATUS_AN_COMPLETE	BIT(5)
++#define QCA955X_MR_AN_STATUS_NO_PREAMBLE	BIT(6)
++#define QCA955X_MR_AN_STATUS_BASE_PAGE		BIT(7)
++
++#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT		0
++#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK		0x7
++#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE	BIT(3)
++#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED		BIT(4)
++#define QCA955X_SGMII_CONFIG_FORCE_SPEED		BIT(5)
++#define QCA955X_SGMII_CONFIG_SPEED_SHIFT		6
++#define QCA955X_SGMII_CONFIG_SPEED_MASK			0xc0
++#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK	BIT(8)
++#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED		BIT(9)
++#define QCA955X_SGMII_CONFIG_MDIO_ENABLE		BIT(10)
++#define QCA955X_SGMII_CONFIG_MDIO_PULSE			BIT(11)
++#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE		BIT(12)
++#define QCA955X_SGMII_CONFIG_PRBS_ENABLE		BIT(13)
++#define QCA955X_SGMII_CONFIG_BERT_ENABLE		BIT(14)
++
++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK	0xff
++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT	0
++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK	0xff00
++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT	8
++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK	0xff0000
++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT	16
++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK	0xf000000
++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT	24
++
+ /*
+  * QCA956X GMAC Interface
+  */
diff --git a/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch b/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch
new file mode 100644
index 0000000000..a6a50e4a8a
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/332-ath79-sgmii-config.patch
@@ -0,0 +1,30 @@
+From: David Bauer <mail@david-bauer.net>
+Subject: [PATCH] ath79: force SGMII SerDes mode to MAC operation
+
+The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default.
+This only allows for 1000 Mbit/s links, however when used with an SGMII
+PHY in 100 Mbit/s link mode, the link remains dead.
+
+This strictly has nothing to do with the SerDes calibration, however it
+is done at the same point in the QCA reference U-Boot which is the
+blueprint for everything happening here. As the current state is more or
+less a hack, this should be fine.
+
+This fixes the issues outlined above on a TP-Link EAP-225 Outdoor.
+
+Reported-by: Tom Herbers <freifunk@tomherbers.de>
+Tested-by: Tom Herbers <freifunk@tomherbers.de>
+Submitted-by: David Bauer <mail@david-bauer.net>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h           | 1 +
+ 1 files changed, 1 insertion(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1380,5 +1380,6 @@
+ 
+ #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT	0
+ #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK	0x7
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC	0x2
+ 
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ath79/patches-6.6/340-register_gpio_driver_earlier.patch b/target/linux/ath79/patches-6.6/340-register_gpio_driver_earlier.patch
new file mode 100644
index 0000000000..32c90ef2fc
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/340-register_gpio_driver_earlier.patch
@@ -0,0 +1,26 @@
+From: John Crispin <john@phrozen.org>
+Subject: ath79: Register GPIO driver earlier
+
+HACK: register the GPIO driver earlier to ensure that gpio_request calls
+from mach files succeed.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ drivers/gpio/gpio-ath79.c                     | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ath79.c
++++ b/drivers/gpio/gpio-ath79.c
+@@ -302,7 +302,11 @@ static struct platform_driver ath79_gpio
+ 	.probe = ath79_gpio_probe,
+ };
+ 
+-module_platform_driver(ath79_gpio_driver);
++static int __init ath79_gpio_init(void)
++{
++	return platform_driver_register(&ath79_gpio_driver);
++}
++postcore_initcall(ath79_gpio_init);
+ 
+ MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
+ MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ath79/patches-6.6/350-MIPS-ath79-ath9k-exports.patch b/target/linux/ath79/patches-6.6/350-MIPS-ath79-ath9k-exports.patch
new file mode 100644
index 0000000000..e460fe58f3
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/350-MIPS-ath79-ath9k-exports.patch
@@ -0,0 +1,36 @@
+From: John Crispin <john@phrozen.org>
+Subject: [PATCH] ath79: make ahb wifi work
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/common.c                      | 3 +++
+ mips/include/asm/mach-ath79/ath79.h           | 1+
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);
+ 
+ enum ath79_soc_type ath79_soc;
+ unsigned int ath79_soc_rev;
++EXPORT_SYMBOL_GPL(ath79_soc_rev);
+ 
+ void __iomem *ath79_pll_base;
+ void __iomem *ath79_reset_base;
+ EXPORT_SYMBOL_GPL(ath79_reset_base);
+-static void __iomem *ath79_ddr_base;
++void __iomem *ath79_ddr_base;
++EXPORT_SYMBOL_GPL(ath79_ddr_base);
+ static void __iomem *ath79_ddr_wb_flush_base;
+ static void __iomem *ath79_ddr_pci_win_base;
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_ddr_set_pci_windows(void);
+ 
+ extern void __iomem *ath79_pll_base;
++extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_reset_base;
+ 
+ static inline void ath79_pll_wr(unsigned reg, u32 val)
diff --git a/target/linux/ath79/patches-6.6/351-MIPS-ath79-common-exports.patch b/target/linux/ath79/patches-6.6/351-MIPS-ath79-common-exports.patch
new file mode 100644
index 0000000000..befcf2d50f
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/351-MIPS-ath79-common-exports.patch
@@ -0,0 +1,26 @@
+From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
+Subject: [PATCH] ath79: export ath79_pll_base
+
+This symbol is declared as extern but nobody exported it.
+Any module including arch/mips/include/asm/mach-ath79/ath79.h
+will not build. Without this export, ag71xx.ko will not build
+as a module and the build will fail like this:
+
+ERROR: modpost: "ath79_pll_base" [drivers/net/ethernet/atheros/ag71xx/ag71xx.ko] undefined!
+
+The ath79_pll_base symbol is accessed in the ath79_pll_wr() inline function.
+
+---
+ arch/mips/ath79/common.c                      | 1 +
+ 1 file changed, 1 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -34,6 +34,7 @@ unsigned int ath79_soc_rev;
+ EXPORT_SYMBOL_GPL(ath79_soc_rev);
+ 
+ void __iomem *ath79_pll_base;
++EXPORT_SYMBOL_GPL(ath79_pll_base);
+ void __iomem *ath79_reset_base;
+ EXPORT_SYMBOL_GPL(ath79_reset_base);
+ void __iomem *ath79_ddr_base;
diff --git a/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch
new file mode 100644
index 0000000000..b24ff21692
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/360-MIPS-ath79-export-UART1-reference-clock.patch
@@ -0,0 +1,67 @@
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: [PATCH] ath79: add support for Atheros AR934x HS UART
+
+AR934x chips also got the 'old' qca,ar9330-uart in addition to the
+'new' ns16550a compatible one. Add support for UART1 clock selector as
+well as device-tree bindings in ar934x.dtsi to make use of that uart.
+
+Reported-by: Piotr Dymacz <pepe2k@gmail.com>
+Submitted-by: Daniel Golle <daniel@makrotopia.org>
+---
+ arch/mips/ath79/clock.c                       | 7 +++++++
+ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ include/dt-bindings/clock/ath79-clk.h         | 3 ++-
+ 3 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
+ 	[ATH79_CLK_AHB] = "ahb",
+ 	[ATH79_CLK_REF] = "ref",
+ 	[ATH79_CLK_MDIO] = "mdio",
++	[ATH79_CLK_UART1] = "uart1",
+ };
+ 
+ static const char * __init ath79_clk_name(int type)
+@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
+ 	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
+ 		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+ 
++	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
++		ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
++
+ 	iounmap(dpll_base);
+ }
+ 
+@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
+ 	if (!clks[ATH79_CLK_MDIO])
+ 		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+ 
++	if (!clks[ATH79_CLK_UART1])
++		clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
++
+ 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+ 		pr_err("%pOF: could not register clk provider\n", np);
+ 		goto err_iounmap;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -348,6 +348,7 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
+ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL	BIT(7)
+ 
+ #define QCA953X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA953X_PLL_DDR_CONFIG_REG		0x04
+--- a/include/dt-bindings/clock/ath79-clk.h
++++ b/include/dt-bindings/clock/ath79-clk.h
+@@ -11,7 +11,8 @@
+ #define ATH79_CLK_AHB		2
+ #define ATH79_CLK_REF		3
+ #define ATH79_CLK_MDIO		4
++#define ATH79_CLK_UART1		5
+ 
+-#define ATH79_CLK_END		5
++#define ATH79_CLK_END		6
+ 
+ #endif /* __DT_BINDINGS_ATH79_CLK_H */
diff --git a/target/linux/ath79/patches-6.6/370-MIPS-ath79-sanitize-symbols.patch b/target/linux/ath79/patches-6.6/370-MIPS-ath79-sanitize-symbols.patch
new file mode 100644
index 0000000000..e6aeef5115
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/370-MIPS-ath79-sanitize-symbols.patch
@@ -0,0 +1,77 @@
+From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:16:55 +0200
+Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols
+
+We no longer need to select which SoCs are supported as the whole arch
+code is always built. So lets drop all the SoC symbols
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/Kconfig       |  2 ++
+ arch/mips/ath79/Kconfig | 44 +++++---------------------------------------
+ arch/mips/pci/Makefile  |  2 +-
+ 3 files changed, 8 insertions(+), 40 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -255,6 +255,8 @@ config ATH79
+ 	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_SUPPORTS_MIPS16
+ 	select SYS_SUPPORTS_ZBOOT_UART_PROM
++	select HAVE_PCI
++	select USB_ARCH_HAS_EHCI
+ 	select USE_OF
+ 	select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
+ 	help
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -1,32 +1,14 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if ATH79
+ 
+-config SOC_AR71XX
+-	select HAVE_PCI
+-	def_bool n
+-
+-config SOC_AR724X
+-	select HAVE_PCI
+-	select PCI_AR724X if PCI
+-	def_bool n
+-
+-config SOC_AR913X
+-	def_bool n
+-
+-config SOC_AR933X
+-	def_bool n
+-
+-config SOC_AR934X
+-	select HAVE_PCI
+-	select PCI_AR724X if PCI
+-	def_bool n
+-
+-config SOC_QCA955X
+-	select HAVE_PCI
+-	select PCI_AR724X if PCI
++config PCI_AR71XX
++	bool "PCI support for AR7100 type SoCs"
++	depends on PCI
+ 	def_bool n
+ 
+ config PCI_AR724X
++	bool "PCI support for AR724x type SoCs"
++	depends on PCI
+ 	def_bool n
+ 
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o
+ 					ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY)	+= pci-alchemy.o
+ obj-$(CONFIG_PCI_AR2315)	+= pci-ar2315.o
+-obj-$(CONFIG_SOC_AR71XX)	+= pci-ar71xx.o
++obj-$(CONFIG_PCI_AR71XX)	+= pci-ar71xx.o
+ obj-$(CONFIG_PCI_AR724X)	+= pci-ar724x.o
+ obj-$(CONFIG_PCI_XTALK_BRIDGE)	+= pci-xtalk-bridge.o
+ #
diff --git a/target/linux/ath79/patches-6.6/400-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/ath79/patches-6.6/400-mtd-nor-support-mtd-name-from-device-tree.patch
new file mode 100644
index 0000000000..62d402625d
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/400-mtd-nor-support-mtd-name-from-device-tree.patch
@@ -0,0 +1,53 @@
+From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
+Date: Sat, 25 Feb 2017 16:42:50 +0000
+Subject: mtd: nor: support mtd name from device tree
+
+Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -3420,12 +3420,19 @@ static void spi_nor_set_mtd_info(struct
+ {
+ 	struct mtd_info *mtd = &nor->mtd;
+ 	struct device *dev = nor->dev;
++	struct device_node *np = spi_nor_get_flash_node(nor);
++	const char __maybe_unused *of_mtd_name = NULL;
+ 
+ 	spi_nor_set_mtd_locking_ops(nor);
+ 	spi_nor_set_mtd_otp_ops(nor);
+ 
+ 	mtd->dev.parent = dev;
+-	if (!mtd->name)
++#ifdef CONFIG_MTD_OF_PARTS
++	of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
++#endif
++	if (of_mtd_name)
++		mtd->name = of_mtd_name;
++	else if (!mtd->name)
+ 		mtd->name = dev_name(dev);
+ 	mtd->type = MTD_NORFLASH;
+ 	mtd->flags = MTD_CAP_NORFLASH;
+--- a/drivers/mtd/mtdcore.c
++++ b/drivers/mtd/mtdcore.c
+@@ -870,6 +870,17 @@ out_error:
+  */
+ static void mtd_set_dev_defaults(struct mtd_info *mtd)
+ {
++#ifdef CONFIG_MTD_OF_PARTS
++	const char __maybe_unused *of_mtd_name = NULL;
++	struct device_node *np;
++
++	np = mtd_get_of_node(mtd);
++	if (np && !mtd->name) {
++		of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
++		if (of_mtd_name)
++			mtd->name = of_mtd_name;
++	} else
++#endif
+ 	if (mtd->dev.parent) {
+ 		if (!mtd->owner && mtd->dev.parent->driver)
+ 			mtd->owner = mtd->dev.parent->driver->owner;
diff --git a/target/linux/ath79/patches-6.6/410-mtd-cybertan-trx-parser.patch b/target/linux/ath79/patches-6.6/410-mtd-cybertan-trx-parser.patch
new file mode 100644
index 0000000000..d0e8aec0d5
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/410-mtd-cybertan-trx-parser.patch
@@ -0,0 +1,45 @@
+From: Christian Lamparter <chunkeey@gmail.com>
+Subject: [PATCH] ath79: port cybertan_part from ar71xx
+
+This patch ports the cybertan_part code from ar71xx and converts the
+driver to a DT-supported mtd parser. As a result, it will no longer
+add the u-boot, nvram and art partitions, which were never part of
+the special Cybertan header.
+
+Instead these partitions have to be specified in the DT, which has the
+upside of making it possible to add properties (i.e.: read-only), labels
+and references to these important partitions.
+
+Submitted-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/parsers/Makefile                  | 1 +
+ drivers/mtd/parsers/Kconfig                   | 8 ++++++++
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_MTD_OF_PARTS)		+= ofpart.o
+ ofpart-y				+= ofpart_core.o
+ ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)	+= ofpart_bcm4908.o
+ ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o
++obj-$(CONFIG_MTD_PARSER_CYBERTAN)	+= parser_cybertan.o
+ obj-$(CONFIG_MTD_PARSER_IMAGETAG)	+= parser_imagetag.o
+ obj-$(CONFIG_MTD_AFS_PARTS)		+= afs.o
+ obj-$(CONFIG_MTD_PARSER_TPLINK_SAFELOADER)	+= tplink_safeloader.o
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -112,6 +112,14 @@ config MTD_OF_PARTS_LINKSYS_NS
+ 	  two "firmware" partitions. Currently used firmware has to be detected
+ 	  using CFE environment variable.
+ 
++config MTD_PARSER_CYBERTAN
++	tristate "Parser for Cybertan format partitions"
++	depends on MTD && (ATH79 || COMPILE_TEST)
++	help
++	  Cybertan has a proprietory header than encompasses a Broadcom trx
++	  header. This driver will parse the header and take care of the
++	  special offsets that result in the extra headers.
++
+ config MTD_PARSER_IMAGETAG
+ 	tristate "Parser for BCM963XX Image Tag format partitions"
+ 	depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
diff --git a/target/linux/ath79/patches-6.6/420-drivers-link-spi-before-mtd.patch b/target/linux/ath79/patches-6.6/420-drivers-link-spi-before-mtd.patch
new file mode 100644
index 0000000000..2e9d3c3e94
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/420-drivers-link-spi-before-mtd.patch
@@ -0,0 +1,20 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: [PATCH] ar71xx: Link SPI before MTD
+
+SVN-Revision: 22863
+---
+ drivers/Makefile                              |   2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -87,8 +87,8 @@ obj-y				+= scsi/
+ obj-y				+= nvme/
+ obj-$(CONFIG_ATA)		+= ata/
+ obj-$(CONFIG_TARGET_CORE)	+= target/
+-obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPI)		+= spi/
++obj-$(CONFIG_MTD)		+= mtd/
+ obj-$(CONFIG_SPMI)		+= spmi/
+ obj-$(CONFIG_HSI)		+= hsi/
+ obj-$(CONFIG_SLIMBUS)		+= slimbus/
diff --git a/target/linux/ath79/patches-6.6/430-mtd-ar934x-nand-driver.patch b/target/linux/ath79/patches-6.6/430-mtd-ar934x-nand-driver.patch
new file mode 100644
index 0000000000..603750cbe9
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/430-mtd-ar934x-nand-driver.patch
@@ -0,0 +1,34 @@
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: ar71xx: ar934x_nfc: experimental NAND Flash Controller driver for AR934x
+
+SVN-Revision: 33385
+---
+ drivers/mtd/nand/raw/Kconfig                  | 8 ++++++++
+ drivers/mtd/nand/raw/Makefile                 | 1 +
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -543,4 +543,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
+ 	  load time (assuming you build diskonchip as a module) with the module
+ 	  parameter "inftl_bbt_write=1".
+ 
++config MTD_NAND_AR934X
++	tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs"
++	depends on ATH79 || COMPILE_TEST
++	depends on HAS_IOMEM
++	help
++	  Enables support for NAND controller on Qualcomm Atheros SoCs.
++	  This controller is found on AR934x and QCA955x SoCs.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM)	+= inte
+ obj-$(CONFIG_MTD_NAND_ROCKCHIP)		+= rockchip-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_PL35X)		+= pl35x-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_RENESAS)		+= renesas-nand-controller.o
++obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nand.o
+ 
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
diff --git a/target/linux/ath79/patches-6.6/700-phy-add-ath79-usb-phys.patch b/target/linux/ath79/patches-6.6/700-phy-add-ath79-usb-phys.patch
new file mode 100644
index 0000000000..0a9de68a39
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/700-phy-add-ath79-usb-phys.patch
@@ -0,0 +1,333 @@
+From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:04:05 +0100
+Subject: [PATCH 04/27] phy: add ath79 usb phys
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/phy/Kconfig          |  16 ++++++
+ drivers/phy/Makefile         |   2 +
+ drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++
+ drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++
+ 4 files changed, 250 insertions(+)
+ create mode 100644 drivers/phy/phy-ar7100-usb.c
+ create mode 100644 drivers/phy/phy-ar7200-usb.c
+
+--- a/drivers/phy/Kconfig
++++ b/drivers/phy/Kconfig
+@@ -25,6 +25,22 @@ config GENERIC_PHY_MIPI_DPHY
+ 	  Provides a number of helpers a core functions for MIPI D-PHY
+ 	  drivers to us.
+ 
++config PHY_AR7100_USB
++	tristate "Atheros AR7100 USB PHY driver"
++	depends on ATH79 || COMPILE_TEST
++	default y if USB_EHCI_HCD_PLATFORM
++	select GENERIC_PHY
++	help
++	  Enable this to support the USB PHY on Atheros AR7100 SoCs.
++
++config PHY_AR7200_USB
++	tristate "Atheros AR7200 USB PHY driver"
++	depends on ATH79 || COMPILE_TEST
++	default y if USB_EHCI_HCD_PLATFORM
++	select GENERIC_PHY
++	help
++	  Enable this to support the USB PHY on Atheros AR7200 SoCs.
++
+ config PHY_LPC18XX_USB_OTG
+ 	tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
+ 	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+--- a/drivers/phy/Makefile
++++ b/drivers/phy/Makefile
+@@ -4,6 +4,8 @@
+ #
+ 
+ obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
++obj-$(CONFIG_PHY_AR7100_USB)		+= phy-ar7100-usb.o
++obj-$(CONFIG_PHY_AR7200_USB)		+= phy-ar7200-usb.o
+ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)	+= phy-core-mipi-dphy.o
+ obj-$(CONFIG_PHY_CAN_TRANSCEIVER)	+= phy-can-transceiver.o
+ obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
+--- /dev/null
++++ b/drivers/phy/phy-ar7100-usb.c
+@@ -0,0 +1,140 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/phy/phy.h>
++#include <linux/delay.h>
++#include <linux/reset.h>
++#include <linux/of_gpio.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++struct ar7100_usb_phy {
++	struct reset_control	*rst_phy;
++	struct reset_control	*rst_host;
++	struct reset_control	*rst_ohci_dll;
++	void __iomem		*io_base;
++	struct phy		*phy;
++	int			gpio;
++};
++
++static int ar7100_usb_phy_power_off(struct phy *phy)
++{
++	struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
++	int err = 0;
++
++	err |= reset_control_assert(priv->rst_host);
++	err |= reset_control_assert(priv->rst_phy);
++	err |= reset_control_assert(priv->rst_ohci_dll);
++
++	return err;
++}
++
++static int ar7100_usb_phy_power_on(struct phy *phy)
++{
++	struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
++	int err = 0;
++
++	err |= ar7100_usb_phy_power_off(phy);
++	mdelay(100);
++	err |= reset_control_deassert(priv->rst_ohci_dll);
++	err |= reset_control_deassert(priv->rst_phy);
++	err |= reset_control_deassert(priv->rst_host);
++	mdelay(500);
++	iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);
++	iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);
++
++	return err;
++}
++
++static const struct phy_ops ar7100_usb_phy_ops = {
++	.power_on	= ar7100_usb_phy_power_on,
++	.power_off	= ar7100_usb_phy_power_off,
++	.owner		= THIS_MODULE,
++};
++
++static int ar7100_usb_phy_probe(struct platform_device *pdev)
++{
++	struct phy_provider *phy_provider;
++	struct resource *res;
++	struct ar7100_usb_phy *priv;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
++	if (IS_ERR(priv->io_base))
++		return PTR_ERR(priv->io_base);
++
++	priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
++	if (IS_ERR(priv->rst_phy)) {
++		dev_err(&pdev->dev, "phy reset is missing\n");
++		return PTR_ERR(priv->rst_phy);
++	}
++
++	priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host");
++	if (IS_ERR(priv->rst_host)) {
++		dev_err(&pdev->dev, "host reset is missing\n");
++		return PTR_ERR(priv->rst_host);
++	}
++
++	priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll");
++	if (IS_ERR(priv->rst_ohci_dll)) {
++		dev_err(&pdev->dev, "ohci-dll reset is missing\n");
++		return PTR_ERR(priv->rst_host);
++	}
++
++	priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);
++	if (IS_ERR(priv->phy)) {
++		dev_err(&pdev->dev, "failed to create PHY\n");
++		return PTR_ERR(priv->phy);
++	}
++
++	priv->gpio = of_get_named_gpio(pdev->dev.of_node, "gpios", 0);
++	if (gpio_is_valid(priv->gpio)) {
++		int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
++
++		if (ret) {
++			dev_err(&pdev->dev, "failed to request gpio\n");
++			return ret;
++		}
++		gpio_export_with_name(gpio_to_desc(priv->gpio), 0, dev_name(&pdev->dev));
++		gpio_set_value(priv->gpio, 1);
++	}
++
++	phy_set_drvdata(priv->phy, priv);
++
++	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
++
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id ar7100_usb_phy_of_match[] = {
++	{ .compatible = "qca,ar7100-usb-phy" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);
++
++static struct platform_driver ar7100_usb_phy_driver = {
++	.probe	= ar7100_usb_phy_probe,
++	.driver = {
++		.of_match_table	= ar7100_usb_phy_of_match,
++		.name		= "ar7100-usb-phy",
++	}
++};
++module_platform_driver(ar7100_usb_phy_driver);
++
++MODULE_DESCRIPTION("ATH79 USB PHY driver");
++MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/phy/phy-ar7200-usb.c
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/phy/phy.h>
++#include <linux/reset.h>
++#include <linux/of_gpio.h>
++
++struct ar7200_usb_phy {
++	struct reset_control	*rst_phy;
++	struct reset_control	*rst_phy_analog;
++	struct reset_control	*suspend_override;
++	struct phy		*phy;
++	int			gpio;
++};
++
++static int ar7200_usb_phy_power_on(struct phy *phy)
++{
++	struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
++	int err = 0;
++
++	if (priv->suspend_override)
++		err = reset_control_assert(priv->suspend_override);
++	if (priv->rst_phy)
++		err |= reset_control_deassert(priv->rst_phy);
++	if (priv->rst_phy_analog)
++		err |= reset_control_deassert(priv->rst_phy_analog);
++
++	return err;
++}
++
++static int ar7200_usb_phy_power_off(struct phy *phy)
++{
++	struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
++	int err = 0;
++
++	if (priv->suspend_override)
++		err = reset_control_deassert(priv->suspend_override);
++	if (priv->rst_phy)
++		err |= reset_control_assert(priv->rst_phy);
++	if (priv->rst_phy_analog)
++		err |= reset_control_assert(priv->rst_phy_analog);
++
++	return err;
++}
++
++static const struct phy_ops ar7200_usb_phy_ops = {
++	.power_on	= ar7200_usb_phy_power_on,
++	.power_off	= ar7200_usb_phy_power_off,
++	.owner		= THIS_MODULE,
++};
++
++static int ar7200_usb_phy_probe(struct platform_device *pdev)
++{
++	struct phy_provider *phy_provider;
++	struct ar7200_usb_phy *priv;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
++	if (IS_ERR(priv->rst_phy)) {
++		if (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)
++			dev_err(&pdev->dev, "phy reset is missing\n");
++		return PTR_ERR(priv->rst_phy);
++	}
++
++	priv->rst_phy_analog = devm_reset_control_get_optional(
++		&pdev->dev, "usb-phy-analog");
++	if (IS_ERR(priv->rst_phy_analog)) {
++		if (PTR_ERR(priv->rst_phy_analog) == -ENOENT)
++			priv->rst_phy_analog = NULL;
++		else
++			return PTR_ERR(priv->rst_phy_analog);
++	}
++
++	priv->suspend_override = devm_reset_control_get_optional(
++		&pdev->dev, "usb-suspend-override");
++	if (IS_ERR(priv->suspend_override)) {
++		if (PTR_ERR(priv->suspend_override) == -ENOENT)
++			priv->suspend_override = NULL;
++		else
++			return PTR_ERR(priv->suspend_override);
++	}
++
++	priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);
++	if (IS_ERR(priv->phy)) {
++		dev_err(&pdev->dev, "failed to create PHY\n");
++		return PTR_ERR(priv->phy);
++	}
++
++	priv->gpio = of_get_named_gpio(pdev->dev.of_node, "gpios", 0);
++	if (gpio_is_valid(priv->gpio)) {
++		int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
++
++		if (ret) {
++			dev_err(&pdev->dev, "failed to request gpio\n");
++			return ret;
++		}
++		gpio_export_with_name(gpio_to_desc(priv->gpio), 0, dev_name(&pdev->dev));
++		gpio_set_value(priv->gpio, 1);
++	}
++
++	phy_set_drvdata(priv->phy, priv);
++
++	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id ar7200_usb_phy_of_match[] = {
++	{ .compatible = "qca,ar7200-usb-phy" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);
++
++static struct platform_driver ar7200_usb_phy_driver = {
++	.probe	= ar7200_usb_phy_probe,
++	.driver = {
++		.of_match_table	= ar7200_usb_phy_of_match,
++		.name		= "ar7200-usb-phy",
++	}
++};
++module_platform_driver(ar7200_usb_phy_driver);
++
++MODULE_DESCRIPTION("ATH79 USB PHY driver");
++MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/ath79/patches-6.6/701-usb-add-more-OF-quirk-properties.patch b/target/linux/ath79/patches-6.6/701-usb-add-more-OF-quirk-properties.patch
new file mode 100644
index 0000000000..293a359884
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/701-usb-add-more-OF-quirk-properties.patch
@@ -0,0 +1,24 @@
+From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:01:43 +0100
+Subject: [PATCH 05/27] usb: add more OF/quirk properties
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/usb/host/ehci-platform.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -274,6 +274,11 @@ static int ehci_platform_probe(struct pl
+ 	ehci = hcd_to_ehci(hcd);
+ 
+ 	if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
++		of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset);
++
++		if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug"))
++			pdata->has_synopsys_hc_bug = 1;
++
+ 		if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
+ 			ehci->big_endian_mmio = 1;
+ 
diff --git a/target/linux/ath79/patches-6.6/710-net-use-downstream-ag71xx.patch b/target/linux/ath79/patches-6.6/710-net-use-downstream-ag71xx.patch
new file mode 100644
index 0000000000..54e64fb11c
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/710-net-use-downstream-ag71xx.patch
@@ -0,0 +1,42 @@
+From: John Crispin <john@phrozen.org>
+Subject: [PATCH] ath79: add new OF only target for QCA MIPS silicon
+
+This target aims to replace ar71xx mid-term. The big part that is still
+missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
+subtargets will follow.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/atheros/Kconfig          | 8 +-------
+ drivers/net/ethernet/atheros/Makefile         | 2 +-
+ 2 files changed, 2 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -17,14 +17,7 @@ config NET_VENDOR_ATHEROS
+ 
+ if NET_VENDOR_ATHEROS
+ 
+-config AG71XX
+-	tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
+-	depends on ATH79
+-	select PHYLINK
+-	imply NET_SELFTESTS
+-	help
+-	  If you wish to compile a kernel for AR7XXX/91XXX and enable
+-	  ethernet support, then you should always answer Y to this.
++source "drivers/net/ethernet/atheros/ag71xx/Kconfig"
+ 
+ config ATL2
+ 	tristate "Atheros L2 Fast Ethernet support"
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -3,7 +3,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+ 
+-obj-$(CONFIG_AG71XX) += ag71xx.o
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
diff --git a/target/linux/ath79/patches-6.6/720-mdio_bitbang_ignore_ta_value.patch b/target/linux/ath79/patches-6.6/720-mdio_bitbang_ignore_ta_value.patch
new file mode 100644
index 0000000000..ce6b16c34e
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/720-mdio_bitbang_ignore_ta_value.patch
@@ -0,0 +1,40 @@
+From: Jonas Gorski <jogo@openwrt.org>
+Subject: ar71xx: add a workaround for ar8316 not always driving the TA bit to low
+
+AR8316 behind a GPIO bitbanged MDIO bus fails to drive the turnaround bit
+to low despite returning a valid value. Ignore it and just use the
+returned value anyway.
+
+SVN-Revision: 28422
+---
+ drivers/net/mdio/mdio-bitbang.c               | 16 ++-----------------
+ 1 file changed, 2 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/mdio/mdio-bitbang.c
++++ b/drivers/net/mdio/mdio-bitbang.c
+@@ -148,23 +148,11 @@ static void mdiobb_cmd_addr(struct mdiob
+ static int mdiobb_read_common(struct mii_bus *bus, int phy)
+ {
+ 	struct mdiobb_ctrl *ctrl = bus->priv;
+-	int ret, i;
++	int ret;
+ 
+ 	ctrl->ops->set_mdio_dir(ctrl, 0);
+ 
+-	/* check the turnaround bit: the PHY should be driving it to zero, if this
+-	 * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
+-	 */
+-	if (mdiobb_get_bit(ctrl) != 0 &&
+-	    !(bus->phy_ignore_ta_mask & (1 << phy))) {
+-		/* PHY didn't drive TA low -- flush any bits it
+-		 * may be trying to send.
+-		 */
+-		for (i = 0; i < 32; i++)
+-			mdiobb_get_bit(ctrl);
+-
+-		return 0xffff;
+-	}
++	mdiobb_get_bit(ctrl);
+ 
+ 	ret = mdiobb_get_num(ctrl, 16);
+ 	mdiobb_get_bit(ctrl);
diff --git a/target/linux/ath79/patches-6.6/721-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ath79/patches-6.6/721-phy-mdio-bitbang-prevent-rescheduling-during-command.patch
new file mode 100644
index 0000000000..26c40e132b
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/721-phy-mdio-bitbang-prevent-rescheduling-during-command.patch
@@ -0,0 +1,94 @@
+From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 16 Jun 2015 13:15:08 +0200
+Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command
+
+It seems some phys have some maximum timings for accessing the MDIO line,
+resulting in bit errors under cpu stress. Prevent this from happening by
+disabling interrupts when sending commands.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/mdio/mdio-bitbang.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/net/mdio/mdio-bitbang.c
++++ b/drivers/net/mdio/mdio-bitbang.c
+@@ -14,6 +14,7 @@
+  * Vitaly Bordug <vbordug@ru.mvista.com>
+  */
+ 
++#include <linux/irqflags.h>
+ #include <linux/delay.h>
+ #include <linux/mdio-bitbang.h>
+ #include <linux/module.h>
+@@ -161,22 +162,32 @@ static int mdiobb_read_common(struct mii
+ 
+ int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg)
+ {
++	int ret;
++	unsigned long flags;
+ 	struct mdiobb_ctrl *ctrl = bus->priv;
+ 
++	local_irq_save(flags);
+ 	mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg);
+ 
+-	return mdiobb_read_common(bus, phy);
++	ret = mdiobb_read_common(bus, phy);
++	local_irq_restore(flags);
++	return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_read_c22);
+ 
+ int mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg)
+ {
++	int ret;
++	unsigned long flags;
+ 	struct mdiobb_ctrl *ctrl = bus->priv;
+ 
++	local_irq_save(flags);
+ 	mdiobb_cmd_addr(ctrl, phy, devad, reg);
+ 	mdiobb_cmd(ctrl, MDIO_C45_READ, phy, devad);
+ 
+-	return mdiobb_read_common(bus, phy);
++	ret = mdiobb_read_common(bus, phy);
++	local_irq_restore(flags);
++	return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_read_c45);
+ 
+@@ -197,22 +208,32 @@ static int mdiobb_write_common(struct mi
+ 
+ int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val)
+ {
++	int ret;
++	unsigned long flags;
+ 	struct mdiobb_ctrl *ctrl = bus->priv;
+ 
++	local_irq_save(flags);
+ 	mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg);
+ 
+-	return mdiobb_write_common(bus, val);
++	ret = mdiobb_write_common(bus, val);
++	local_irq_restore(flags);
++	return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_write_c22);
+ 
+ int mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, int reg, u16 val)
+ {
++	int ret;
++	unsigned long flags;
+ 	struct mdiobb_ctrl *ctrl = bus->priv;
+ 
++	local_irq_save(flags);
+ 	mdiobb_cmd_addr(ctrl, phy, devad, reg);
+ 	mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, devad);
+ 
+-	return mdiobb_write_common(bus, val);
++	ret = mdiobb_write_common(bus, val);
++	local_irq_restore(flags);
++	return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_write_c45);
+ 
diff --git a/target/linux/ath79/patches-6.6/730-ar8216-make-reg-access-atomic.patch b/target/linux/ath79/patches-6.6/730-ar8216-make-reg-access-atomic.patch
new file mode 100644
index 0000000000..02f763534e
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/730-ar8216-make-reg-access-atomic.patch
@@ -0,0 +1,59 @@
+From b3797d1a92afe97c173b00fdb7824cedba24eef0 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Sun, 20 Sep 2020 01:00:45 +0800
+Subject: [PATCH] ath79: ar8216: make switch register access atomic
+
+due to some unknown reason these register accesses sometimes fail
+on the integrated switch without this patch.
+
+THIS ONLY WORKS ON ATH79 AND MAY BREAK THE DRIVER ON OTHER PLATFORMS!
+The mdio bus on ath79 works in polling mode and doesn't rely on
+any interrupt. This patch breaks the driver on any mdio master
+with interrupts used.
+
+---
+--- a/drivers/net/phy/ar8216.c
++++ b/drivers/net/phy/ar8216.c
+@@ -252,6 +252,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p
+ u32
+ ar8xxx_read(struct ar8xxx_priv *priv, int reg)
+ {
++	unsigned long flags;
+ 	struct mii_bus *bus = priv->mii_bus;
+ 	u16 r1, r2, page;
+ 	u32 val;
+@@ -259,11 +260,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
+ 	split_addr((u32) reg, &r1, &r2, &page);
+ 
+ 	mutex_lock(&bus->mdio_lock);
++	local_irq_save(flags);
+ 
+ 	bus->write(bus, 0x18, 0, page);
+ 	wait_for_page_switch();
+ 	val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
+ 
++	local_irq_restore(flags);
+ 	mutex_unlock(&bus->mdio_lock);
+ 
+ 	return val;
+@@ -272,17 +275,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
+ void
+ ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
+ {
++	unsigned long flags;
+ 	struct mii_bus *bus = priv->mii_bus;
+ 	u16 r1, r2, page;
+ 
+ 	split_addr((u32) reg, &r1, &r2, &page);
+ 
+ 	mutex_lock(&bus->mdio_lock);
++	local_irq_save(flags);
+ 
+ 	bus->write(bus, 0x18, 0, page);
+ 	wait_for_page_switch();
+ 	ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
+ 
++	local_irq_restore(flags);
+ 	mutex_unlock(&bus->mdio_lock);
+ }
+ 
diff --git a/target/linux/ath79/patches-6.6/800-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-6.6/800-leds-add-reset-controller-based-driver.patch
new file mode 100644
index 0000000000..fa958e767b
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/800-leds-add-reset-controller-based-driver.patch
@@ -0,0 +1,186 @@
+From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:03:03 +0100
+Subject: [PATCH 03/27] leds: add reset-controller based driver
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/leds/Kconfig      |  11 ++++
+ drivers/leds/Makefile     |   1 +
+ drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 149 insertions(+)
+ create mode 100644 drivers/leds/leds-reset.c
+
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -901,6 +901,17 @@ source "drivers/leds/flash/Kconfig"
+ comment "RGB LED drivers"
+ source "drivers/leds/rgb/Kconfig"
+ 
++config LEDS_RESET
++	tristate "LED support for reset-controller API"
++	depends on LEDS_CLASS
++	depends on RESET_CONTROLLER
++	help
++	  This option enables support for LEDs connected to pins driven by reset
++	  controllers. Yes, DNI actual built HW like that.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called leds-reset.
++
+ comment "LED Triggers"
+ source "drivers/leds/trigger/Kconfig"
+ 
+--- /dev/null
++++ b/drivers/leds/leds-reset.c
+@@ -0,0 +1,140 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/err.h>
++#include <linux/reset.h>
++#include <linux/kernel.h>
++#include <linux/leds.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++
++struct reset_led_data {
++	struct led_classdev cdev;
++	struct reset_control *rst;
++};
++
++static inline struct reset_led_data *
++			cdev_to_reset_led_data(struct led_classdev *led_cdev)
++{
++	return container_of(led_cdev, struct reset_led_data, cdev);
++}
++
++static void reset_led_set(struct led_classdev *led_cdev,
++	enum led_brightness value)
++{
++	struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);
++
++	if (value == LED_OFF)
++		reset_control_assert(led_dat->rst);
++	else
++		reset_control_deassert(led_dat->rst);
++}
++
++struct reset_leds_priv {
++	int num_leds;
++	struct reset_led_data leds[];
++};
++
++static inline int sizeof_reset_leds_priv(int num_leds)
++{
++	return sizeof(struct reset_leds_priv) +
++		(sizeof(struct reset_led_data) * num_leds);
++}
++
++static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct fwnode_handle *child;
++	struct reset_leds_priv *priv;
++	int count, ret;
++
++	count = device_get_child_node_count(dev);
++	if (!count)
++		return ERR_PTR(-ENODEV);
++
++	priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);
++	if (!priv)
++		return ERR_PTR(-ENOMEM);
++
++	device_for_each_child_node(dev, child) {
++		struct reset_led_data *led = &priv->leds[priv->num_leds];
++		struct device_node *np = to_of_node(child);
++
++		ret = fwnode_property_read_string(child, "label", &led->cdev.name);
++		if (!led->cdev.name) {
++			fwnode_handle_put(child);
++			return ERR_PTR(-EINVAL);
++		}
++		led->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true);
++		if (IS_ERR(led->rst))
++			return ERR_PTR(-EINVAL);
++
++		fwnode_property_read_string(child, "linux,default-trigger",
++						&led->cdev.default_trigger);
++
++		led->cdev.brightness_set = reset_led_set;
++		ret = devm_led_classdev_register(&pdev->dev, &led->cdev);
++		if (ret < 0)
++			return ERR_PTR(ret);
++		led->cdev.dev->of_node = np;
++		priv->num_leds++;
++	}
++
++	return priv;
++}
++
++static const struct of_device_id of_reset_leds_match[] = {
++	{ .compatible = "reset-leds", },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, of_reset_leds_match);
++
++static int reset_led_probe(struct platform_device *pdev)
++{
++	struct reset_leds_priv *priv;
++
++	priv = reset_leds_create(pdev);
++	if (IS_ERR(priv))
++		return PTR_ERR(priv);
++
++	platform_set_drvdata(pdev, priv);
++
++	return 0;
++}
++
++static void reset_led_shutdown(struct platform_device *pdev)
++{
++	struct reset_leds_priv *priv = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; i < priv->num_leds; i++) {
++		struct reset_led_data *led = &priv->leds[i];
++
++		if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))
++			reset_led_set(&led->cdev, LED_OFF);
++	}
++}
++
++static struct platform_driver reset_led_driver = {
++	.probe		= reset_led_probe,
++	.shutdown	= reset_led_shutdown,
++	.driver		= {
++		.name	= "leds-reset",
++		.of_match_table = of_reset_leds_match,
++	},
++};
++
++module_platform_driver(reset_led_driver);
++
++MODULE_AUTHOR("John Crispin <john@phrozen.org>");
++MODULE_DESCRIPTION("reset controller LED driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:leds-reset");
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -88,6 +88,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)		+= leds
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
++obj-$(CONFIG_LEDS_RESET)		+= leds-reset.o
+ 
+ # LED SPI Drivers
+ obj-$(CONFIG_LEDS_CR0014114)		+= leds-cr0014114.o
diff --git a/target/linux/ath79/patches-6.6/810-ath79-ignore-the-abused-interrupt-map-on-pcie-node.patch b/target/linux/ath79/patches-6.6/810-ath79-ignore-the-abused-interrupt-map-on-pcie-node.patch
new file mode 100644
index 0000000000..980c265fe6
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/810-ath79-ignore-the-abused-interrupt-map-on-pcie-node.patch
@@ -0,0 +1,33 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 31 May 2023 00:15:23 +0000
+Subject: [PATCH] ath79: ignore the abused interrupt-map on pcie node
+
+ath79 PCIe interrupt controller has stopped working correctly. This
+is because the DT exposing a non-sensical interrupt-map property,
+and their drivers relying on the kernel ignoring this property[1].
+
+This patch fix the pcie init error:
+ath9k 0000:00:00.0: of_irq_parse_pci: failed with rc=-14
+
+Notice:
+This is just a workaround, not a fix. PCIe driver and related dts
+node need to be rewritten.
+
+[1] https://lore.kernel.org/all/20211201114102.13446-1-maz@kernel.org/
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/of/irq.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/of/irq.c
++++ b/drivers/of/irq.c
+@@ -86,6 +86,8 @@ EXPORT_SYMBOL_GPL(of_irq_find_parent);
+  * drawing board.
+  */
+ static const char * const of_irq_imap_abusers[] = {
++	"qca,ar7100-pci",
++	"qcom,ar7240-pci",
+ 	"CBEA,platform-spider-pic",
+ 	"sti,platform-spider-pic",
+ 	"realtek,rtl-intc",
diff --git a/target/linux/ath79/patches-6.6/820-mfd-syscon-support-skip-reset-control-for-syscon-devices.patch b/target/linux/ath79/patches-6.6/820-mfd-syscon-support-skip-reset-control-for-syscon-devices.patch
new file mode 100644
index 0000000000..c73c8443b9
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/820-mfd-syscon-support-skip-reset-control-for-syscon-devices.patch
@@ -0,0 +1,37 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 13 Mar 2024 22:36:31 +0800
+Subject: [PATCH] mfd: syscon: support skip reset control for syscon devices
+
+Some platform device drivers(e.g. ag71xx) expect exclusive reset
+control. Fetching reset controller for syscon[1] will break these
+drivers. This patch introduces a new property 'syscon-no-reset'
+to skip it.
+
+[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit?id=7d1e3bd94828ad9fc86f55253cd6fec8edd65394
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/mfd/syscon.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/mfd/syscon.c
++++ b/drivers/mfd/syscon.c
+@@ -52,7 +52,7 @@ static struct syscon *of_syscon_register
+ 	int ret;
+ 	struct regmap_config syscon_config = syscon_regmap_config;
+ 	struct resource res;
+-	struct reset_control *reset;
++	struct reset_control *reset = NULL;
+ 
+ 	syscon = kzalloc(sizeof(*syscon), GFP_KERNEL);
+ 	if (!syscon)
+@@ -134,7 +134,8 @@ static struct syscon *of_syscon_register
+ 				goto err_attach_clk;
+ 		}
+ 
+-		reset = of_reset_control_get_optional_exclusive(np, NULL);
++		if (!of_property_read_bool(np, "syscon-no-reset"))
++			reset = of_reset_control_get_optional_exclusive(np, NULL);
+ 		if (IS_ERR(reset)) {
+ 			ret = PTR_ERR(reset);
+ 			goto err_attach_clk;
diff --git a/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch b/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch
new file mode 100644
index 0000000000..0190da85de
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/900-unaligned_access_hacks.patch
@@ -0,0 +1,909 @@
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] ar71xx: fix unaligned access in a few more places
+
+SVN-Revision: 35130
+---
+ arch/mips/include/asm/checksum.h              | 83 +++---------------
+ include/uapi/linux/ip.h                       |  2 +-
+ include/uapi/linux/ipv6.h                     |  2 +-
+ include/uapi/linux/tcp.h                      |  4 ++--
+ include/uapi/linux/udp.h                      |  2 +-
+ net/netfilter/nf_conntrack_core.c             |  4 ++--
+ include/uapi/linux/icmp.h                     |  2 +-
+ include/uapi/linux/in6.h                      |  2 +-
+ net/ipv6/tcp_ipv6.c                           |  9 +++--
+ net/ipv6/datagram.c                           |  6 ++--
+ net/ipv6/exthdrs.c                            |  2 +-
+ include/linux/types.h                         |  5 +++
+ net/ipv4/af_inet.c                            |  4 ++--
+ net/ipv4/tcp_output.c                         | 69 +++++++++--------
+ include/uapi/linux/igmp.h                     |  8 +++---
+ net/core/flow_dissector.c                     |  2 +-
+ include/uapi/linux/icmpv6.h                   |  2 +-
+ include/net/ndisc.h                           | 10 ++++----
+ net/sched/cls_u32.c                           |  6 +++---
+ net/ipv6/ip6_offload.c                        |  2 +-
+ include/net/addrconf.h                        |  2 +-
+ include/net/inet_ecn.h                        |  4 ++--
+ include/net/ipv6.h                            | 23 +++++----
+ include/net/secure_seq.h                      |  1 +
+ include/uapi/linux/in.h                       |  2 +-
+ net/ipv6/ip6_fib.h                            |  2 +-
+ net/netfilter/nf_conntrack_proto_tcp.c        |  2 +-
+ net/xfrm/xfrm_input.c                         |  4 ++--
+ net/ipv4/tcp_input.c                          | 12 ++++---
+ include/uapi/linux/if_pppox.h                 |  1 +
+ net/ipv6/netfilter/nf_log_ipv6.c              |  4 ++--
+ include/net/neighbour.h                       |  6 +++--
+ include/uapi/linux/netfilter_arp/arp_tables.h |  2 +-
+ net/core/utils.c                              | 10 +++++--
+ include/linux/etherdevice.h                   | 11 ++++---
+ net/ipv4/tcp_offload.c                        |  6 +++---
+ net/ipv6/netfilter/ip6table_mangle.c          |  4 ++--
+ 37 file changed, 171 insertions(+), 141 deletions(-)
+
+--- a/arch/mips/include/asm/checksum.h
++++ b/arch/mips/include/asm/checksum.h
+@@ -100,26 +100,30 @@ static inline __sum16 ip_fast_csum(const
+ 	const unsigned int *stop = word + ihl;
+ 	unsigned int csum;
+ 	int carry;
++	unsigned int w;
+ 
+-	csum = word[0];
+-	csum += word[1];
+-	carry = (csum < word[1]);
++	csum = net_hdr_word(word++);
++
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[2];
+-	carry = (csum < word[2]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	csum += word[3];
+-	carry = (csum < word[3]);
++	w = net_hdr_word(word++);
++	csum += w;
++	carry = (csum < w);
+ 	csum += carry;
+ 
+-	word += 4;
+ 	do {
+-		csum += *word;
+-		carry = (csum < *word);
++		w = net_hdr_word(word++);
++		csum += w;
++		carry = (csum < w);
+ 		csum += carry;
+-		word++;
+ 	} while (word != stop);
+ 
+ 	return csum_fold(csum);
+@@ -179,74 +183,6 @@ static inline __sum16 ip_compute_csum(co
+ 	return csum_fold(csum_partial(buff, len, 0));
+ }
+ 
+-#define _HAVE_ARCH_IPV6_CSUM
+-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+-					  const struct in6_addr *daddr,
+-					  __u32 len, __u8 proto,
+-					  __wsum sum)
+-{
+-	__wsum tmp;
+-
+-	__asm__(
+-	"	.set	push		# csum_ipv6_magic\n"
+-	"	.set	noreorder	\n"
+-	"	.set	noat		\n"
+-	"	addu	%0, %5		# proto (long in network byte order)\n"
+-	"	sltu	$1, %0, %5	\n"
+-	"	addu	%0, $1		\n"
+-
+-	"	addu	%0, %6		# csum\n"
+-	"	sltu	$1, %0, %6	\n"
+-	"	lw	%1, 0(%2)	# four words source address\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%2)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 0(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 4(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 8(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	lw	%1, 12(%3)	\n"
+-	"	addu	%0, $1		\n"
+-	"	addu	%0, %1		\n"
+-	"	sltu	$1, %0, %1	\n"
+-
+-	"	addu	%0, $1		# Add final carry\n"
+-	"	.set	pop"
+-	: "=&r" (sum), "=&r" (tmp)
+-	: "r" (saddr), "r" (daddr),
+-	  "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)
+-	: "memory");
+-
+-	return csum_fold(sum);
+-}
+-
+ #include <asm-generic/checksum.h>
+ #endif /* CONFIG_GENERIC_CSUM */
+ 
+--- a/include/uapi/linux/ip.h
++++ b/include/uapi/linux/ip.h
+@@ -106,7 +106,7 @@ struct iphdr {
+ 		__be32	daddr;
+ 	);
+ 	/*The options start here. */
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ struct ip_auth_hdr {
+--- a/include/uapi/linux/ipv6.h
++++ b/include/uapi/linux/ipv6.h
+@@ -135,7 +135,7 @@ struct ipv6hdr {
+ 		struct	in6_addr	saddr;
+ 		struct	in6_addr	daddr;
+ 	);
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /* index values for the variables in ipv6_devconf */
+--- a/include/uapi/linux/tcp.h
++++ b/include/uapi/linux/tcp.h
+@@ -55,7 +55,7 @@ struct tcphdr {
+ 	__be16	window;
+ 	__sum16	check;
+ 	__be16	urg_ptr;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /*
+  *	The union cast uses a gcc extension to avoid aliasing problems
+@@ -65,7 +65,7 @@ struct tcphdr {
+ union tcp_word_hdr {
+ 	struct tcphdr hdr;
+ 	__be32        words[5];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ #define tcp_flag_word(tp) (((union tcp_word_hdr *)(tp))->words[3])
+ 
+--- a/include/uapi/linux/udp.h
++++ b/include/uapi/linux/udp.h
+@@ -25,7 +25,7 @@ struct udphdr {
+ 	__be16	dest;
+ 	__be16	len;
+ 	__sum16	check;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* UDP socket options */
+ #define UDP_CORK	1	/* Never send partially complete segments */
+--- a/net/netfilter/nf_conntrack_core.c
++++ b/net/netfilter/nf_conntrack_core.c
+@@ -298,8 +298,8 @@ nf_ct_get_tuple(const struct sk_buff *sk
+ 
+ 	switch (l3num) {
+ 	case NFPROTO_IPV4:
+-		tuple->src.u3.ip = ap[0];
+-		tuple->dst.u3.ip = ap[1];
++		tuple->src.u3.ip = net_hdr_word(ap++);
++		tuple->dst.u3.ip = net_hdr_word(ap);
+ 		break;
+ 	case NFPROTO_IPV6:
+ 		memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));
+--- a/include/uapi/linux/icmp.h
++++ b/include/uapi/linux/icmp.h
+@@ -102,7 +102,7 @@ struct icmphdr {
+ 	} frag;
+ 	__u8	reserved[4];
+   } un;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ /*
+--- a/include/uapi/linux/in6.h
++++ b/include/uapi/linux/in6.h
+@@ -43,7 +43,7 @@ struct in6_addr {
+ #define s6_addr16		in6_u.u6_addr16
+ #define s6_addr32		in6_u.u6_addr32
+ #endif
+-};
++} __attribute__((packed, aligned(2)));
+ #endif /* __UAPI_DEF_IN6_ADDR */
+ 
+ #if __UAPI_DEF_SOCKADDR_IN6
+--- a/net/ipv6/tcp_ipv6.c
++++ b/net/ipv6/tcp_ipv6.c
+@@ -35,6 +35,7 @@
+ #include <linux/ipsec.h>
+ #include <linux/times.h>
+ #include <linux/slab.h>
++#include <asm/unaligned.h>
+ #include <linux/uaccess.h>
+ #include <linux/ipv6.h>
+ #include <linux/icmpv6.h>
+@@ -897,10 +898,10 @@ static void tcp_v6_send_response(const s
+ 	topt = (__be32 *)(t1 + 1);
+ 
+ 	if (tsecr) {
+-		*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+-				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
+-		*topt++ = htonl(tsval);
+-		*topt++ = htonl(tsecr);
++		put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++				(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
++		put_unaligned_be32(tsval, topt++);
++		put_unaligned_be32(tsecr, topt++);
+ 	}
+ 
+ 	if (mrst)
+--- a/include/linux/ipv6.h
++++ b/include/linux/ipv6.h
+@@ -6,6 +6,7 @@
+ 
+ #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)
+ #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
++
+ /*
+  * This structure contains configuration options per IPv6 link.
+  */
+--- a/net/ipv6/datagram.c
++++ b/net/ipv6/datagram.c
+@@ -499,7 +499,7 @@ int ipv6_recv_error(struct sock *sk, str
+ 				ipv6_iface_scope_id(&sin->sin6_addr,
+ 						    IP6CB(skb)->iif);
+ 		} else {
+-			ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
++			ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
+ 					       &sin->sin6_addr);
+ 			sin->sin6_scope_id = 0;
+ 		}
+@@ -853,12 +853,12 @@ int ip6_datagram_send_ctl(struct net *ne
+ 			}
+ 
+ 			if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
+-				if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
++				if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
+ 					err = -EINVAL;
+ 					goto exit_f;
+ 				}
+ 			}
+-			fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
++			fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
+ 			break;
+ 
+ 		case IPV6_2292HOPOPTS:
+--- a/net/ipv6/exthdrs.c
++++ b/net/ipv6/exthdrs.c
+@@ -982,7 +982,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
+ 		goto drop;
+ 	}
+ 
+-	pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
++	pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
+ 	if (pkt_len <= IPV6_MAXPLEN) {
+ 		icmpv6_param_prob_reason(skb, ICMPV6_HDR_FIELD, optoff + 2,
+ 					 SKB_DROP_REASON_IP_INHDR);
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -244,5 +244,11 @@ typedef void (*swap_func_t)(void *a, voi
+ typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv);
+ typedef int (*cmp_func_t)(const void *a, const void *b);
+ 
++struct net_hdr_word {
++       u32 words[1];
++} __attribute__((packed, aligned(2)));
++
++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
++
+ #endif /*  __ASSEMBLY__ */
+ #endif /* _LINUX_TYPES_H */
+--- a/net/ipv4/af_inet.c
++++ b/net/ipv4/af_inet.c
+@@ -1506,8 +1506,8 @@ struct sk_buff *inet_gro_receive(struct
+ 		goto out;
+ 
+ 	NAPI_GRO_CB(skb)->proto = proto;
+-	id = ntohl(*(__be32 *)&iph->id);
+-	flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
++	id = ntohl(net_hdr_word(&iph->id));
++	flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
+ 	id >>= 16;
+ 
+ 	list_for_each_entry(p, head, list) {
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -620,48 +620,53 @@ static void tcp_options_write(struct tcp
+ 	u16 options = opts->options;	/* mungable copy */
+ 
+ 	if (unlikely(OPTION_MD5 & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+-			       (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++			      (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
+ 		/* overload cookie hash location */
+ 		opts->hash_location = (__u8 *)ptr;
+ 		ptr += 4;
+ 	}
+ 
+ 	if (unlikely(opts->mss)) {
+-		*ptr++ = htonl((TCPOPT_MSS << 24) |
+-			       (TCPOLEN_MSS << 16) |
+-			       opts->mss);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
++			      opts->mss);
+ 	}
+ 
+ 	if (likely(OPTION_TS & options)) {
+ 		if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-			*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
+-				       (TCPOLEN_SACK_PERM << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_SACK_PERM << 24) |
++				      (TCPOLEN_SACK_PERM << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 			options &= ~OPTION_SACK_ADVERTISE;
+ 		} else {
+-			*ptr++ = htonl((TCPOPT_NOP << 24) |
+-				       (TCPOPT_NOP << 16) |
+-				       (TCPOPT_TIMESTAMP << 8) |
+-				       TCPOLEN_TIMESTAMP);
++			net_hdr_word(ptr++) =
++				htonl((TCPOPT_NOP << 24) |
++				      (TCPOPT_NOP << 16) |
++				      (TCPOPT_TIMESTAMP << 8) |
++				      TCPOLEN_TIMESTAMP);
+ 		}
+-		*ptr++ = htonl(opts->tsval);
+-		*ptr++ = htonl(opts->tsecr);
++		net_hdr_word(ptr++) = htonl(opts->tsval);
++		net_hdr_word(ptr++) = htonl(opts->tsecr);
+ 	}
+ 
+ 	if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_NOP << 16) |
+-			       (TCPOPT_SACK_PERM << 8) |
+-			       TCPOLEN_SACK_PERM);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK_PERM << 8) |
++			      TCPOLEN_SACK_PERM);
+ 	}
+ 
+ 	if (unlikely(OPTION_WSCALE & options)) {
+-		*ptr++ = htonl((TCPOPT_NOP << 24) |
+-			       (TCPOPT_WINDOW << 16) |
+-			       (TCPOLEN_WINDOW << 8) |
+-			       opts->ws);
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_WINDOW << 16) |
++			      (TCPOLEN_WINDOW << 8) |
++			      opts->ws);
+ 	}
+ 
+ 	if (unlikely(opts->num_sack_blocks)) {
+@@ -669,16 +674,17 @@ static void tcp_options_write(struct tcp
+ 			tp->duplicate_sack : tp->selective_acks;
+ 		int this_sack;
+ 
+-		*ptr++ = htonl((TCPOPT_NOP  << 24) |
+-			       (TCPOPT_NOP  << 16) |
+-			       (TCPOPT_SACK <<  8) |
+-			       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
++		net_hdr_word(ptr++) =
++			htonl((TCPOPT_NOP << 24) |
++			      (TCPOPT_NOP << 16) |
++			      (TCPOPT_SACK << 8) |
++			      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
+ 						     TCPOLEN_SACK_PERBLOCK)));
+ 
+ 		for (this_sack = 0; this_sack < opts->num_sack_blocks;
+ 		     ++this_sack) {
+-			*ptr++ = htonl(sp[this_sack].start_seq);
+-			*ptr++ = htonl(sp[this_sack].end_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
++			net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
+ 		}
+ 
+ 		tp->rx_opt.dsack = 0;
+@@ -691,13 +697,14 @@ static void tcp_options_write(struct tcp
+ 
+ 		if (foc->exp) {
+ 			len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
+-			*ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
++			net_hdr_word(ptr) =
++				htonl((TCPOPT_EXP << 24) | (len << 16) |
+ 				     TCPOPT_FASTOPEN_MAGIC);
+ 			p += TCPOLEN_EXP_FASTOPEN_BASE;
+ 		} else {
+ 			len = TCPOLEN_FASTOPEN_BASE + foc->len;
+-			*p++ = TCPOPT_FASTOPEN;
+-			*p++ = len;
++			net_hdr_word(p++) = TCPOPT_FASTOPEN;
++			net_hdr_word(p++) = len;
+ 		}
+ 
+ 		memcpy(p, foc->val, foc->len);
+--- a/include/uapi/linux/igmp.h
++++ b/include/uapi/linux/igmp.h
+@@ -33,7 +33,7 @@ struct igmphdr {
+ 	__u8 code;		/* For newer IGMP */
+ 	__sum16 csum;
+ 	__be32 group;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* V3 group record types [grec_type] */
+ #define IGMPV3_MODE_IS_INCLUDE		1
+@@ -49,7 +49,7 @@ struct igmpv3_grec {
+ 	__be16	grec_nsrcs;
+ 	__be32	grec_mca;
+ 	__be32	grec_src[];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_report {
+ 	__u8 type;
+@@ -58,7 +58,7 @@ struct igmpv3_report {
+ 	__be16 resv2;
+ 	__be16 ngrec;
+ 	struct igmpv3_grec grec[];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct igmpv3_query {
+ 	__u8 type;
+@@ -79,7 +79,7 @@ struct igmpv3_query {
+ 	__u8 qqic;
+ 	__be16 nsrcs;
+ 	__be32 srcs[];
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ #define IGMP_HOST_MEMBERSHIP_QUERY	0x11	/* From RFC1112 */
+ #define IGMP_HOST_MEMBERSHIP_REPORT	0x12	/* Ditto */
+--- a/net/core/flow_dissector.c
++++ b/net/core/flow_dissector.c
+@@ -132,7 +132,7 @@ __be32 __skb_flow_get_ports(const struct
+ 		ports = __skb_header_pointer(skb, thoff + poff,
+ 					     sizeof(_ports), data, hlen, &_ports);
+ 		if (ports)
+-			return *ports;
++			return (__be32)net_hdr_word(ports);
+ 	}
+ 
+ 	return 0;
+--- a/include/uapi/linux/icmpv6.h
++++ b/include/uapi/linux/icmpv6.h
+@@ -78,7 +78,7 @@ struct icmp6hdr {
+ #define icmp6_addrconf_other	icmp6_dataun.u_nd_ra.other
+ #define icmp6_rt_lifetime	icmp6_dataun.u_nd_ra.rt_lifetime
+ #define icmp6_router_pref	icmp6_dataun.u_nd_ra.router_pref
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ 
+ #define ICMPV6_ROUTER_PREF_LOW		0x3
+--- a/include/net/ndisc.h
++++ b/include/net/ndisc.h
+@@ -93,7 +93,7 @@ struct ra_msg {
+         struct icmp6hdr		icmph;
+ 	__be32			reachable_time;
+ 	__be32			retrans_timer;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ struct rd_msg {
+ 	struct icmp6hdr icmph;
+@@ -372,10 +372,10 @@ static inline u32 ndisc_hashfn(const voi
+ {
+ 	const u32 *p32 = pkey;
+ 
+-	return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
+-		(p32[1] * hash_rnd[1]) +
+-		(p32[2] * hash_rnd[2]) +
+-		(p32[3] * hash_rnd[3]));
++	return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
++		(net_hdr_word(&p32[1]) * hash_rnd[1]) +
++		(net_hdr_word(&p32[2]) * hash_rnd[2]) +
++		(net_hdr_word(&p32[3]) * hash_rnd[3]));
+ }
+ 
+ static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
+--- a/net/sched/cls_u32.c
++++ b/net/sched/cls_u32.c
+@@ -157,7 +157,7 @@ next_knode:
+ 			data = skb_header_pointer(skb, toff, 4, &hdata);
+ 			if (!data)
+ 				goto out;
+-			if ((*data ^ key->val) & key->mask) {
++			if ((net_hdr_word(data) ^ key->val) & key->mask) {
+ 				n = rcu_dereference_bh(n->next);
+ 				goto next_knode;
+ 			}
+@@ -208,8 +208,8 @@ check_terminal:
+ 						  &hdata);
+ 			if (!data)
+ 				goto out;
+-			sel = ht->divisor & u32_hash_fold(*data, &n->sel,
+-							  n->fshift);
++			sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
++							  &n->sel, n->fshift);
+ 		}
+ 		if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
+ 			goto next_ht;
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -273,7 +273,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ 			continue;
+ 
+ 		iph2 = (struct ipv6hdr *)(p->data + off);
+-		first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
++		first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
+ 
+ 		/* All fields must match except length and Traffic Class.
+ 		 * XXX skbs on the gro_list have all been parsed and pulled
+--- a/include/net/addrconf.h
++++ b/include/net/addrconf.h
+@@ -52,7 +52,7 @@ struct prefix_info {
+ 	__be32			reserved2;
+ 
+ 	struct in6_addr		prefix;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /* rfc4861 4.6.2: IPv6 PIO is 32 bytes in size */
+ static_assert(sizeof(struct prefix_info) == 32);
+--- a/include/net/inet_ecn.h
++++ b/include/net/inet_ecn.h
+@@ -138,9 +138,9 @@ static inline int IP6_ECN_set_ce(struct
+ 	if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))
+ 		return 0;
+ 
+-	from = *(__be32 *)iph;
++	from = net_hdr_word(iph);
+ 	to = from | htonl(INET_ECN_CE << 20);
+-	*(__be32 *)iph = to;
++	net_hdr_word(iph) = to;
+ 	if (skb->ip_summed == CHECKSUM_COMPLETE)
+ 		skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),
+ 				     (__force __wsum)to);
+--- a/include/net/ipv6.h
++++ b/include/net/ipv6.h
+@@ -149,7 +149,7 @@ struct frag_hdr {
+ 	__u8	reserved;
+ 	__be16	frag_off;
+ 	__be32	identification;
+-};
++} __attribute__((packed, aligned(2)));
+ 
+ /*
+  * Jumbo payload option, as described in RFC 2675 2.
+@@ -649,8 +649,8 @@ static inline void __ipv6_addr_set_half(
+ 	}
+ #endif
+ #endif
+-	addr[0] = wh;
+-	addr[1] = wl;
++	net_hdr_word(&addr[0]) = wh;
++	net_hdr_word(&addr[1]) = wl;
+ }
+ 
+ static inline void ipv6_addr_set(struct in6_addr *addr,
+@@ -709,6 +709,8 @@ static inline bool ipv6_prefix_equal(con
+ 	const __be32 *a1 = addr1->s6_addr32;
+ 	const __be32 *a2 = addr2->s6_addr32;
+ 	unsigned int pdw, pbi;
++	/* Used for last <32-bit fraction of prefix */
++	u32 pbia1, pbia2;
+ 
+ 	/* check complete u32 in prefix */
+ 	pdw = prefixlen >> 5;
+@@ -717,7 +719,9 @@ static inline bool ipv6_prefix_equal(con
+ 
+ 	/* check incomplete u32 in prefix */
+ 	pbi = prefixlen & 0x1f;
+-	if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))
++	pbia1 = net_hdr_word(&a1[pdw]);
++	pbia2 = net_hdr_word(&a2[pdw]);
++	if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))
+ 		return false;
+ 
+ 	return true;
+@@ -839,13 +843,13 @@ static inline void ipv6_addr_set_v4mappe
+  */
+ static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
+ {
+-	const __be32 *a1 = token1, *a2 = token2;
++	const struct in6_addr *a1 = token1, *a2 = token2;
+ 	int i;
+ 
+ 	addrlen >>= 2;
+ 
+ 	for (i = 0; i < addrlen; i++) {
+-		__be32 xb = a1[i] ^ a2[i];
++		__be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];
+ 		if (xb)
+ 			return i * 32 + 31 - __fls(ntohl(xb));
+ 	}
+@@ -1040,17 +1044,18 @@ static inline u32 ip6_multipath_hash_fie
+ static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
+ 				__be32 flowlabel)
+ {
+-	*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;
++	net_hdr_word((__be32 *)hdr) =
++		htonl(0x60000000 | (tclass << 20)) | flowlabel;
+ }
+ 
+ static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)
+ {
+-	return *(__be32 *)hdr & IPV6_FLOWINFO_MASK;
++	return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;
+ }
+ 
+ static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)
+ {
+-	return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;
++	return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;
+ }
+ 
+ static inline u8 ip6_tclass(__be32 flowinfo)
+--- a/include/net/secure_seq.h
++++ b/include/net/secure_seq.h
+@@ -3,6 +3,7 @@
+ #define _NET_SECURE_SEQ
+ 
+ #include <linux/types.h>
++#include <linux/in6.h>
+ 
+ struct net;
+ 
+--- a/include/uapi/linux/in.h
++++ b/include/uapi/linux/in.h
+@@ -91,7 +91,7 @@ enum {
+ /* Internet address. */
+ struct in_addr {
+ 	__be32	s_addr;
+-};
++} __attribute__((packed, aligned(2)));
+ #endif
+ 
+ #define IP_TOS		1
+--- a/net/ipv6/ip6_fib.c
++++ b/net/ipv6/ip6_fib.c
+@@ -141,7 +141,7 @@ static __be32 addr_bit_set(const void *t
+ 	 * See include/asm-generic/bitops/le.h.
+ 	 */
+ 	return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &
+-	       addr[fn_bit >> 5];
++	       net_hdr_word(&addr[fn_bit >> 5]);
+ }
+ 
+ struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh)
+--- a/net/netfilter/nf_conntrack_proto_tcp.c
++++ b/net/netfilter/nf_conntrack_proto_tcp.c
+@@ -406,7 +406,7 @@ static void tcp_sack(const struct sk_buf
+ 
+ 	/* Fast path for timestamp-only option */
+ 	if (length == TCPOLEN_TSTAMP_ALIGNED
+-	    && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)
++	    && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)
+ 				       | (TCPOPT_NOP << 16)
+ 				       | (TCPOPT_TIMESTAMP << 8)
+ 				       | TCPOLEN_TIMESTAMP))
+--- a/net/xfrm/xfrm_input.c
++++ b/net/xfrm/xfrm_input.c
+@@ -168,8 +168,8 @@ int xfrm_parse_spi(struct sk_buff *skb,
+ 	if (!pskb_may_pull(skb, hlen))
+ 		return -EINVAL;
+ 
+-	*spi = *(__be32 *)(skb_transport_header(skb) + offset);
+-	*seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);
++	*spi = net_hdr_word(skb_transport_header(skb) + offset);
++	*seq = net_hdr_word(skb_transport_header(skb) + offset_seq);
+ 	return 0;
+ }
+ EXPORT_SYMBOL(xfrm_parse_spi);
+--- a/net/ipv4/tcp_input.c
++++ b/net/ipv4/tcp_input.c
+@@ -4188,14 +4188,16 @@ static bool tcp_parse_aligned_timestamp(
+ {
+ 	const __be32 *ptr = (const __be32 *)(th + 1);
+ 
+-	if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
+-			  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
++	if (net_hdr_word(ptr) ==
++	    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++		  (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ 		tp->rx_opt.saw_tstamp = 1;
+ 		++ptr;
+-		tp->rx_opt.rcv_tsval = ntohl(*ptr);
++		tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
+ 		++ptr;
+-		if (*ptr)
+-			tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;
++		if (net_hdr_word(ptr))
++			tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -
++					       tp->tsoffset;
+ 		else
+ 			tp->rx_opt.rcv_tsecr = 0;
+ 		return true;
+--- a/include/uapi/linux/if_pppox.h
++++ b/include/uapi/linux/if_pppox.h
+@@ -51,6 +51,7 @@ struct pppoe_addr {
+  */
+ struct pptp_addr {
+ 	__u16		call_id;
++	__u16		pad;
+ 	struct in_addr	sin_addr;
+ };
+ 
+--- a/include/net/neighbour.h
++++ b/include/net/neighbour.h
+@@ -286,8 +286,10 @@ static inline bool neigh_key_eq128(const
+ 	const u32 *n32 = (const u32 *)n->primary_key;
+ 	const u32 *p32 = pkey;
+ 
+-	return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |
+-		(n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;
++	return ((n32[0] ^ net_hdr_word(&p32[0])) |
++		(n32[1] ^ net_hdr_word(&p32[1])) |
++		(n32[2] ^ net_hdr_word(&p32[2])) |
++		(n32[3] ^ net_hdr_word(&p32[3]))) == 0;
+ }
+ 
+ static inline struct neighbour *___neigh_lookup_noref(
+--- a/include/uapi/linux/netfilter_arp/arp_tables.h
++++ b/include/uapi/linux/netfilter_arp/arp_tables.h
+@@ -70,7 +70,7 @@ struct arpt_arp {
+ 	__u8 flags;
+ 	/* Inverse flags */
+ 	__u16 invflags;
+-};
++} __attribute__((aligned(4)));
+ 
+ /* Values for "flag" field in struct arpt_ip (general arp structure).
+  * No flags defined yet.
+--- a/net/core/utils.c
++++ b/net/core/utils.c
+@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 *
+ 			       bool pseudohdr)
+ {
+ 	__be32 diff[] = {
+-		~from[0], ~from[1], ~from[2], ~from[3],
+-		to[0], to[1], to[2], to[3],
++		~net_hdr_word(&from[0]),
++		~net_hdr_word(&from[1]),
++		~net_hdr_word(&from[2]),
++		~net_hdr_word(&from[3]),
++		net_hdr_word(&to[0]),
++		net_hdr_word(&to[1]),
++		net_hdr_word(&to[2]),
++		net_hdr_word(&to[3]),
+ 	};
+ 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
+ 		*sum = csum_fold(csum_partial(diff, sizeof(diff),
+--- a/include/linux/etherdevice.h
++++ b/include/linux/etherdevice.h
+@@ -555,7 +555,7 @@ static inline bool is_etherdev_addr(cons
+  * @b: Pointer to Ethernet header
+  *
+  * Compare two Ethernet headers, returns 0 if equal.
+- * This assumes that the network header (i.e., IP header) is 4-byte
++ * This assumes that the network header (i.e., IP header) is 2-byte
+  * aligned OR the platform can handle unaligned access.  This is the
+  * case for all packets coming into netif_receive_skb or similar
+  * entry points.
+@@ -578,11 +578,12 @@ static inline unsigned long compare_ethe
+ 	fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);
+ 	return fold;
+ #else
+-	u32 *a32 = (u32 *)((u8 *)a + 2);
+-	u32 *b32 = (u32 *)((u8 *)b + 2);
++	const u16 *a16 = a;
++	const u16 *b16 = b;
+ 
+-	return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |
+-	       (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);
++	return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |
++	       (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |
++	       (a16[6] ^ b16[6]);
+ #endif
+ }
+ 
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -63,7 +63,7 @@ static struct sk_buff *__tcpv4_gso_segme
+ 	th2 = tcp_hdr(seg->next);
+ 	iph2 = ip_hdr(seg->next);
+ 
+-	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	if (!(net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) &&
+ 	    iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
+ 		return segs;
+ 
+@@ -255,7 +255,7 @@ struct sk_buff *tcp_gro_lookup(struct li
+ 			continue;
+ 
+ 		th2 = tcp_hdr(p);
+-		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++		if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
+ 			NAPI_GRO_CB(p)->same_flow = 0;
+ 			continue;
+ 		}
+@@ -321,8 +321,8 @@ struct sk_buff *tcp_gro_receive(struct l
+ 		  ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
+ 	flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
+ 	for (i = sizeof(*th); i < thlen; i += 4)
+-		flush |= *(u32 *)((u8 *)th + i) ^
+-			 *(u32 *)((u8 *)th2 + i);
++		flush |= net_hdr_word((u8 *)th + i) ^
++			 net_hdr_word((u8 *)th2 + i);
+ 
+ 	/* When we receive our second frame we can made a decision on if we
+ 	 * continue this flow as an atomic flow with a fixed ID or if we use
+--- a/net/ipv6/netfilter/ip6table_mangle.c
++++ b/net/ipv6/netfilter/ip6table_mangle.c
+@@ -44,7 +44,7 @@ ip6t_mangle_out(void *priv, struct sk_bu
+ 	hop_limit = ipv6_hdr(skb)->hop_limit;
+ 
+ 	/* flowlabel and prio (includes version, which shouldn't change either */
+-	flowlabel = *((u_int32_t *)ipv6_hdr(skb));
++	flowlabel = net_hdr_word(ipv6_hdr(skb));
+ 
+ 	ret = ip6t_do_table(priv, skb, state);
+ 
+@@ -53,7 +53,7 @@ ip6t_mangle_out(void *priv, struct sk_bu
+ 	     !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||
+ 	     skb->mark != mark ||
+ 	     ipv6_hdr(skb)->hop_limit != hop_limit ||
+-	     flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {
++	     flowlabel != net_hdr_word(ipv6_hdr(skb)))) {
+ 		err = ip6_route_me_harder(state->net, state->sk, skb);
+ 		if (err < 0)
+ 			ret = NF_DROP_ERR(err);
diff --git a/target/linux/ath79/patches-6.6/910-mikrotik-rb4xx.patch b/target/linux/ath79/patches-6.6/910-mikrotik-rb4xx.patch
new file mode 100644
index 0000000000..980f29eef1
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/910-mikrotik-rb4xx.patch
@@ -0,0 +1,121 @@
+From: Christopher Hill <ch6574@gmail.com>
+Subject: [PATCH] ath79: add Mikrotik rb4xx series drivers
+
+This adds 3 Mikrotik rb4xx series drivers as follows:
+
+rb4xx-cpld: This is in the mfd subsystem, and is the parent CPLD device
+that interfaces between the SoC SPI bus and its two children below.
+rb4xx-gpio: This is the GPIO expander.
+rb4xx-nand: This is the NAND driver.
+
+The history of this code comes in three phases.
+
+1. The first is a May 2015 attempt to push the equivalient ar71xx rb4xx
+drivers upstream. See https://lore.kernel.org/patchwork/patch/940880/.
+
+Module-author: Gabor Juhos <juhosg@openwrt.org>
+Module-author: Imre Kaloz <kaloz@openwrt.org>
+Module-author: Bert Vermeulen <bert@biot.com>
+
+2. Next several ar71xx patches were applied bringing the code current.
+
+commit 7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c
+Submitted-by: Hauke Mehrtens <hauke@hauke-m.de>
+
+commit af79fdbe4af32a287798b579141204bda056b8aa
+commit 889272d92db689fd9c910243635e44c9d8323095
+commit e21cb649a235180563363b8af5ba8296b9ac0baa
+commit 7c09fa4a7492ca436f2c94bd9a465b7c5bbeed6f
+Submitted-by: Felix Fietkau <nbd@nbd.name>
+
+3. Finally a heavy refactor to split the driver into the three new
+subsystems, and updated to work with the device tree configuration, plus
+updates and review feedback incorporated
+
+Reviewed-by: Thibaut VARÈNE <hacks@slashdirt.org>
+Submitted-by: Christopher Hill <ch6574@gmail.com>
+---
+ drivers/mfd/Kconfig                           | 8 ++++++++
+ drivers/mfd/Makefile                          | 1 +
+ drivers/gpio/Kconfig                          | 6 ++++++
+ drivers/gpio/Makefile                         | 1 +
+ drivers/mtd/nand/raw/Kconfig                  | 7 +++++++
+ drivers/mtd/nand/raw/Makefile                 | 1 +
+ 6 files changed, 24 insertions(+)
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -2261,6 +2261,14 @@ config RAVE_SP_CORE
+ 	  Select this to get support for the Supervisory Processor
+ 	  device found on several devices in RAVE line of hardware.
+ 
++config MFD_RB4XX_CPLD
++	tristate "CPLD driver for Mikrotik RB4xx series boards"
++	select MFD_CORE
++	depends on ATH79 || COMPILE_TEST
++	help
++	  Enables support for the CPLD chip (NAND & GPIO) on Mikrotik
++	  Routerboard RB4xx series.
++
+ config SGI_MFD_IOC3
+ 	bool "SGI IOC3 core driver"
+ 	depends on PCI && MIPS && 64BIT
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -269,6 +269,7 @@ obj-$(CONFIG_MFD_KHADAS_MCU) 	+= khadas-
+ obj-$(CONFIG_MFD_ACER_A500_EC)	+= acer-ec-a500.o
+ obj-$(CONFIG_MFD_QCOM_PM8008)	+= qcom-pm8008.o
+ 
++obj-$(CONFIG_MFD_RB4XX_CPLD)	+= rb4xx-cpld.o
+ obj-$(CONFIG_SGI_MFD_IOC3)	+= ioc3.o
+ obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)	+= simple-mfd-i2c.o
+ obj-$(CONFIG_MFD_SMPRO)		+= smpro-core.o
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -1696,6 +1696,12 @@ config GPIO_SODAVILLE
+ 	help
+ 	  Say Y here to support Intel Sodaville GPIO.
+ 
++config GPIO_RB4XX
++	tristate "GPIO expander for Mikrotik RB4xx series boards"
++	depends on MFD_RB4XX_CPLD
++	help
++	  GPIO driver for Mikrotik Routerboard RB4xx series.
++
+ endmenu
+ 
+ menu "SPI GPIO expanders"
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -131,6 +131,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.
+ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
+ obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
++obj-$(CONFIG_GPIO_RB4XX)		+= gpio-rb4xx.o
+ obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
+ obj-$(CONFIG_GPIO_RDA)			+= gpio-rda.o
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -551,4 +551,11 @@ config MTD_NAND_AR934X
+ 	  Enables support for NAND controller on Qualcomm Atheros SoCs.
+ 	  This controller is found on AR934x and QCA955x SoCs.
+ 
++config MTD_NAND_RB4XX
++	tristate "Support for NAND driver for Mikrotik RB4xx series boards"
++	depends on MFD_RB4XX_CPLD
++	help
++	  Enables support for the NAND flash chip on Mikrotik Routerboard
++	  RB4xx series.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_ROCKCHIP)		+= rock
+ obj-$(CONFIG_MTD_NAND_PL35X)		+= pl35x-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_RENESAS)		+= renesas-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX)		+= nand_rb4xx.o
+ 
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
diff --git a/target/linux/ath79/patches-6.6/911-mikrotik-rb91x.patch b/target/linux/ath79/patches-6.6/911-mikrotik-rb91x.patch
new file mode 100644
index 0000000000..e610a4ff14
--- /dev/null
+++ b/target/linux/ath79/patches-6.6/911-mikrotik-rb91x.patch
@@ -0,0 +1,96 @@
+From: Denis Kalashnikov <denis281089@gmail.com>
+Subject: [PATCH] ath79: add support for reset key on MikroTik RB912UAG-2HPnD
+
+On MikroTik RB91x board series a reset key shares SoC gpio
+line #15 with NAND ALE and NAND IO7. So we need a custom
+gpio driver to manage this non-trivial connection schema.
+Also rb91x-nand needs to have an ability to disable a polling
+of the key while it works with NAND.
+
+While we've been integrating rb91x-key into a firmware, we've
+figured out that:
+* In the gpio-latch driver we need to add a "cansleep" suffix to
+several gpiolib calls,
+* When gpio-latch and rb91x-nand fail to get a gpio and an error
+is -EPROBE_DEFER, they shouldn't report about this, since this
+actually is not an error and occurs when the gpio-latch probe
+function is called before the rb91x-key probe.
+We fix these related things here too.
+
+Submitted-by: Denis Kalashnikov <denis281089@gmail.com>
+Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
+Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
+---
+ drivers/gpio/Kconfig                          | 11 +++++++++++
+ drivers/gpio/Makefile                         |  2 ++
+ drivers/mtd/nand/raw/Kconfig                  |  6 ++++++
+ drivers/mtd/nand/raw/Makefile                 |  1 +
+ 7 files changed, 20 insertions(+)
+
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -371,6 +371,12 @@ config GPIO_IXP4XX
+ 
+ 	  If unsure, say N.
+ 
++config GPIO_LATCH_MIKROTIK
++	tristate "MikroTik RouterBOARD GPIO latch support"
++	depends on ATH79
++	help
++	  GPIO driver for latch on some MikroTik RouterBOARDs.
++
+ config GPIO_LOGICVC
+ 	tristate "Xylon LogiCVC GPIO support"
+ 	depends on MFD_SYSCON && OF
+@@ -553,6 +559,10 @@ config GPIO_ROCKCHIP
+ 	help
+ 	  Say yes here to support GPIO on Rockchip SoCs.
+ 
++config GPIO_RB91X_KEY
++	tristate "MikroTik RB91x board series reset key support"
++	depends on ATH79
++
+ config GPIO_SAMA5D2_PIOBU
+ 	tristate "SAMA5D2 PIOBU GPIO support"
+ 	depends on MFD_SYSCON
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -81,6 +81,7 @@ obj-$(CONFIG_GPIO_IXP4XX)		+= gpio-ixp4x
+ obj-$(CONFIG_GPIO_JANZ_TTL)		+= gpio-janz-ttl.o
+ obj-$(CONFIG_GPIO_KEMPLD)		+= gpio-kempld.o
+ obj-$(CONFIG_GPIO_LATCH)		+= gpio-latch.o
++obj-$(CONFIG_GPIO_LATCH_MIKROTIK)	+= gpio-latch-mikrotik.o
+ obj-$(CONFIG_GPIO_LJCA) 		+= gpio-ljca.o
+ obj-$(CONFIG_GPIO_LOGICVC)		+= gpio-logicvc.o
+ obj-$(CONFIG_GPIO_LOONGSON1)		+= gpio-loongson1.o
+@@ -132,6 +133,7 @@ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio
+ obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
+ obj-$(CONFIG_GPIO_RB4XX)		+= gpio-rb4xx.o
++obj-$(CONFIG_GPIO_RB91X_KEY)		+= gpio-rb91x-key.o
+ obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
+ obj-$(CONFIG_GPIO_RDA)			+= gpio-rda.o
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -558,4 +558,10 @@ config MTD_NAND_RB4XX
+ 	  Enables support for the NAND flash chip on Mikrotik Routerboard
+ 	  RB4xx series.
+ 
++config MTD_NAND_RB91X
++	tristate "MikroTik RB91x NAND driver support"
++	depends on ATH79 && MTD_RAW_NAND
++	help
++	  Enables support for the NAND flash chip on MikroTik RB91x series.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_PL35X)		+= pl35x-n
+ obj-$(CONFIG_MTD_NAND_RENESAS)		+= renesas-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_AR934X)		+= ar934x_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)		+= nand_rb4xx.o
++obj-$(CONFIG_MTD_NAND_RB91X)		+= rb91x_nand.o
+ 
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
diff --git a/target/linux/bcm27xx/image/cmdline.txt b/target/linux/bcm27xx/image/cmdline.txt
index 41f76f10af..bdd1e59a09 100644
--- a/target/linux/bcm27xx/image/cmdline.txt
+++ b/target/linux/bcm27xx/image/cmdline.txt
@@ -1 +1 @@
-console=serial0,115200 console=tty1 root=@ROOT@ rootfstype=squashfs,ext4 rootwait
+console=tty1 console=serial0,115200 root=@ROOT@ rootfstype=squashfs,ext4 rootwait
diff --git a/target/linux/bcm27xx/modules/video.mk b/target/linux/bcm27xx/modules/video.mk
index c9b9555b04..b9af0b3e0f 100644
--- a/target/linux/bcm27xx/modules/video.mk
+++ b/target/linux/bcm27xx/modules/video.mk
@@ -27,7 +27,7 @@ define KernelPackage/codec-bcm2835
   FILES:= \
     $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-codec/bcm2835-codec.ko
   AUTOLOAD:=$(call AutoLoad,67,bcm2835-codec)
-  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma +kmod-video-mem2mem)
+  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma-contig +kmod-video-mem2mem)
 endef
 
 define KernelPackage/codec-bcm2835/description
@@ -72,7 +72,7 @@ define KernelPackage/isp-bcm2835
   FILES:= \
     $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp.ko
   AUTOLOAD:=$(call AutoLoad,67,bcm2835-isp)
-  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma)
+  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma-contig)
 endef
 
 define KernelPackage/isp-bcm2835/description
diff --git a/target/linux/bcm27xx/patches-6.1/950-0080-Revert-net-bcmgenet-Request-APD-DLL-disable-and-IDDQ.patch b/target/linux/bcm27xx/patches-6.1/950-0080-Revert-net-bcmgenet-Request-APD-DLL-disable-and-IDDQ.patch
index 9a29d61792..57a59c1ae4 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0080-Revert-net-bcmgenet-Request-APD-DLL-disable-and-IDDQ.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0080-Revert-net-bcmgenet-Request-APD-DLL-disable-and-IDDQ.patch
@@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
-@@ -290,9 +290,7 @@ int bcmgenet_mii_probe(struct net_device
+@@ -303,9 +303,7 @@ int bcmgenet_mii_probe(struct net_device
  	struct device_node *dn = kdev->of_node;
  	phy_interface_t phy_iface = priv->phy_interface;
  	struct phy_device *phydev;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
index ab145eb66f..89ed666567 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch
@@ -1185,7 +1185,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  }
 --- a/drivers/usb/core/hub.c
 +++ b/drivers/usb/core/hub.c
-@@ -5686,7 +5686,7 @@ static void port_event(struct usb_hub *h
+@@ -5698,7 +5698,7 @@ static void port_event(struct usb_hub *h
  		port_dev->over_current_count++;
  		port_over_current_notify(port_dev);
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0179-bcmgenet-Better-coalescing-parameter-defaults.patch b/target/linux/bcm27xx/patches-6.1/950-0179-bcmgenet-Better-coalescing-parameter-defaults.patch
index b805f1df30..41c6199005 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0179-bcmgenet-Better-coalescing-parameter-defaults.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0179-bcmgenet-Better-coalescing-parameter-defaults.patch
@@ -18,7 +18,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
 
 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -2659,7 +2659,7 @@ static void bcmgenet_init_tx_ring(struct
+@@ -2665,7 +2665,7 @@ static void bcmgenet_init_tx_ring(struct
  
  	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
  	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
@@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
  	/* Disable rate control for now */
  	bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
  				  TDMA_FLOW_PERIOD);
-@@ -4140,9 +4140,12 @@ static int bcmgenet_probe(struct platfor
+@@ -4160,9 +4160,12 @@ static int bcmgenet_probe(struct platfor
  	netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
  
  	/* Set default coalescing parameters */
diff --git a/target/linux/bcm27xx/patches-6.1/950-0180-net-genet-enable-link-energy-detect-powerdown-for-ex.patch b/target/linux/bcm27xx/patches-6.1/950-0180-net-genet-enable-link-energy-detect-powerdown-for-ex.patch
index cc76ba5db9..44d8613b5e 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0180-net-genet-enable-link-energy-detect-powerdown-for-ex.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0180-net-genet-enable-link-energy-detect-powerdown-for-ex.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
 
 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c
 +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c
-@@ -296,6 +296,8 @@ int bcmgenet_mii_probe(struct net_device
+@@ -309,6 +309,8 @@ int bcmgenet_mii_probe(struct net_device
  	/* Communicate the integrated PHY revision */
  	if (priv->internal_phy)
  		phy_flags = priv->gphy_rev;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch b/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch
index 34b923fb23..3feabeaf9d 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch
@@ -90,10 +90,10 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
 +		 */
 +	void	(*fixup_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
 +				  struct usb_host_endpoint *ep, int interval);
- 		/* Returns the hardware-chosen device address */
- 	int	(*address_device)(struct usb_hcd *, struct usb_device *udev);
- 		/* prepares the hardware to send commands to the device */
-@@ -435,6 +440,8 @@ extern void usb_hcd_unmap_urb_setup_for_
+ 		/* Set the hardware-chosen device address */
+ 	int	(*address_device)(struct usb_hcd *, struct usb_device *udev,
+ 				  unsigned int timeout_ms);
+@@ -436,6 +441,8 @@ extern void usb_hcd_unmap_urb_setup_for_
  extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *, struct urb *);
  extern void usb_hcd_flush_endpoint(struct usb_device *udev,
  		struct usb_host_endpoint *ep);
diff --git a/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch b/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch
index 3c1e41ba0a..a5e08d4cca 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch
@@ -125,7 +125,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
   * non-error returns are a promise to giveback() the urb later
   * we drop ownership so next owner (or urb unlink) can get it
   */
-@@ -5471,6 +5574,7 @@ static const struct hc_driver xhci_hc_dr
+@@ -5480,6 +5583,7 @@ static const struct hc_driver xhci_hc_dr
  	.endpoint_reset =	xhci_endpoint_reset,
  	.check_bandwidth =	xhci_check_bandwidth,
  	.reset_bandwidth =	xhci_reset_bandwidth,
diff --git a/target/linux/bcm27xx/patches-6.1/950-0189-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch b/target/linux/bcm27xx/patches-6.1/950-0189-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
index da60efe07f..1507baa65b 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0189-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0189-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch
@@ -37,7 +37,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
  
  static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  {
-@@ -2490,6 +2493,11 @@ static void reset_umac(struct bcmgenet_p
+@@ -2494,6 +2497,11 @@ static void reset_umac(struct bcmgenet_p
  	bcmgenet_rbuf_ctrl_set(priv, 0);
  	udelay(10);
  
@@ -47,5 +47,5 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
 +	}
 +
  	/* issue soft reset and disable MAC while updating its registers */
+ 	spin_lock_bh(&priv->reg_lock);
  	bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
- 	udelay(2);
diff --git a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch
index 93f7ffde9c..1188b4dbe4 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch
@@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
 
 --- a/drivers/usb/host/xhci-mem.c
 +++ b/drivers/usb/host/xhci-mem.c
-@@ -2522,9 +2522,11 @@ int xhci_mem_init(struct xhci_hcd *xhci,
+@@ -2524,9 +2524,11 @@ int xhci_mem_init(struct xhci_hcd *xhci,
  	 * Event ring setup: Allocate a normal ring, but also setup
  	 * the event ring segment table (ERST).  Section 4.9.3.
  	 */
@@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  	if (!xhci->event_ring)
  		goto fail;
  	if (xhci_check_trb_in_td_math(xhci) < 0)
-@@ -2537,7 +2539,7 @@ int xhci_mem_init(struct xhci_hcd *xhci,
+@@ -2539,7 +2541,7 @@ int xhci_mem_init(struct xhci_hcd *xhci,
  	/* set ERST count with the number of entries in the segment table */
  	val = readl(&xhci->ir_set->erst_size);
  	val &= ERST_SIZE_MASK;
@@ -47,7 +47,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  			val);
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1672,8 +1672,8 @@ struct urb_priv {
+@@ -1677,8 +1677,8 @@ struct urb_priv {
   * Each segment table entry is 4*32bits long.  1K seems like an ok size:
   * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
   * meaning 64 ring segments.
diff --git a/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch b/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
index ef96ffe86e..2a3e2d781e 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0227-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch
@@ -32,7 +32,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3679,6 +3679,7 @@ static int spi_set_cs_timing(struct spi_
+@@ -3690,6 +3690,7 @@ static int spi_set_cs_timing(struct spi_
   */
  int spi_setup(struct spi_device *spi)
  {
@@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	unsigned	bad_bits, ugly_bits;
  	int		status = 0;
  
-@@ -3699,6 +3700,14 @@ int spi_setup(struct spi_device *spi)
+@@ -3710,6 +3711,14 @@ int spi_setup(struct spi_device *spi)
  		(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
  		 SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
  		return -EINVAL;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0270-net-bcmgenet-Reset-RBUF-on-first-open.patch b/target/linux/bcm27xx/patches-6.1/950-0270-net-bcmgenet-Reset-RBUF-on-first-open.patch
deleted file mode 100644
index e21de6f79f..0000000000
--- a/target/linux/bcm27xx/patches-6.1/950-0270-net-bcmgenet-Reset-RBUF-on-first-open.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From e857a27d5bca6269cea7a0ca0058aa8fffe90a83 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.com>
-Date: Fri, 25 Sep 2020 15:07:23 +0100
-Subject: [PATCH] net: bcmgenet: Reset RBUF on first open
-
-If the RBUF logic is not reset when the kernel starts then there
-may be some data left over from any network boot loader. If the
-64-byte packet headers are enabled then this can be fatal.
-
-Extend bcmgenet_dma_disable to do perform the reset, but not when
-called from bcmgenet_resume in order to preserve a wake packet.
-
-N.B. This different handling of resume is just based on a hunch -
-why else wouldn't one reset the RBUF as well as the TBUF? If this
-isn't the case then it's easy to change the patch to make the RBUF
-reset unconditional.
-
-See: https://github.com/raspberrypi/linux/issues/3850
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.com>
----
- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 16 ++++++++++++----
- 1 file changed, 12 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c
-@@ -3306,7 +3306,7 @@ static void bcmgenet_get_hw_addr(struct
- }
- 
- /* Returns a reusable dma control register value */
--static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
-+static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv, bool flush_rx)
- {
- 	unsigned int i;
- 	u32 reg;
-@@ -3331,6 +3331,14 @@ static u32 bcmgenet_dma_disable(struct b
- 	udelay(10);
- 	bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
- 
-+	if (flush_rx) {
-+	    reg = bcmgenet_rbuf_ctrl_get(priv);
-+	    bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0));
-+	    udelay(10);
-+	    bcmgenet_rbuf_ctrl_set(priv, reg);
-+	    udelay(10);
-+	}
-+
- 	return dma_ctrl;
- }
- 
-@@ -3394,8 +3402,8 @@ static int bcmgenet_open(struct net_devi
- 
- 	bcmgenet_set_hw_addr(priv, dev->dev_addr);
- 
--	/* Disable RX/TX DMA and flush TX queues */
--	dma_ctrl = bcmgenet_dma_disable(priv);
-+	/* Disable RX/TX DMA and flush TX and RX queues */
-+	dma_ctrl = bcmgenet_dma_disable(priv, true);
- 
- 	/* Reinitialize TDMA and RDMA and SW housekeeping */
- 	ret = bcmgenet_init_dma(priv);
-@@ -4269,7 +4277,7 @@ static int bcmgenet_resume(struct device
- 			bcmgenet_hfb_create_rxnfc_filter(priv, rule);
- 
- 	/* Disable RX/TX DMA and flush TX queues */
--	dma_ctrl = bcmgenet_dma_disable(priv);
-+	dma_ctrl = bcmgenet_dma_disable(priv, false);
- 
- 	/* Reinitialize TDMA and RDMA and SW housekeeping */
- 	ret = bcmgenet_init_dma(priv);
diff --git a/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch b/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch
index db15c65809..ed242cbbe4 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch
@@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
 
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -674,9 +674,9 @@ deq_found:
+@@ -675,9 +675,9 @@ deq_found:
  	}
  
  	if ((ep->ep_state & SET_DEQ_PENDING)) {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
index 073bb8be79..0725689bf8 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
@@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -664,6 +664,15 @@ static int xhci_move_dequeue_past_td(str
+@@ -665,6 +665,15 @@ static int xhci_move_dequeue_past_td(str
  	} while (!cycle_found || !td_last_trb_found);
  
  deq_found:
@@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	addr = xhci_trb_virt_to_dma(new_seg, new_deq);
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1902,6 +1902,7 @@ struct xhci_hcd {
+@@ -1907,6 +1907,7 @@ struct xhci_hcd {
  #define XHCI_RESET_TO_DEFAULT	BIT_ULL(44)
  #define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(45)
  #define XHCI_ZHAOXIN_HOST	BIT_ULL(46)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch b/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch
index ab76ad76cd..4147167600 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch
@@ -144,7 +144,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (ret)
  		return -ENOMEM;
  
-@@ -1811,7 +1815,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc
+@@ -1813,7 +1817,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc
  	for (val = 0; val < evt_ring->num_segs; val++) {
  		entry = &erst->entries[val];
  		entry->seg_addr = cpu_to_le64(seg->dma);
@@ -204,7 +204,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  		xhci_err(xhci, "Tried to move enqueue past ring segment\n");
  		return;
  	}
-@@ -3150,7 +3153,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
+@@ -3151,7 +3154,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
  	 * that clears the EHB.
  	 */
  	while (xhci_handle_event(xhci) > 0) {
@@ -213,7 +213,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  			continue;
  		xhci_update_erst_dequeue(xhci, event_ring_deq);
  		event_ring_deq = xhci->event_ring->dequeue;
-@@ -3292,7 +3295,8 @@ static int prepare_ring(struct xhci_hcd
+@@ -3293,7 +3296,8 @@ static int prepare_ring(struct xhci_hcd
  		}
  	}
  
@@ -247,7 +247,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	 * when the cycle bit is set to 1.
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1634,6 +1634,7 @@ struct xhci_ring {
+@@ -1639,6 +1639,7 @@ struct xhci_ring {
  	unsigned int		num_trbs_free;
  	unsigned int		num_trbs_free_temp;
  	unsigned int		bounce_buf_len;
diff --git a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
index 041f98a97d..da0d7cd969 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
@@ -63,7 +63,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1904,6 +1904,7 @@ struct xhci_hcd {
+@@ -1909,6 +1909,7 @@ struct xhci_hcd {
  #define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(45)
  #define XHCI_ZHAOXIN_HOST	BIT_ULL(46)
  #define XHCI_AVOID_DQ_ON_LINK  BIT_ULL(47)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch
index 0dd7b78b30..df13f539bd 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch
@@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3605,14 +3605,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3606,14 +3606,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	unsigned int num_trbs;
  	unsigned int start_cycle, num_sgs = 0;
  	unsigned int enqd_len, block_len, trb_buff_len, full_len;
@@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	full_len = urb->transfer_buffer_length;
  	/* If we have scatter/gather list, we use it. */
  	if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
-@@ -3649,6 +3650,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3650,6 +3651,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	start_cycle = ring->cycle_state;
  	send_addr = addr;
  
@@ -72,7 +72,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	/* Queue the TRBs, even if they are zero-length */
  	for (enqd_len = 0; first_trb || enqd_len < full_len;
  			enqd_len += trb_buff_len) {
-@@ -3661,6 +3673,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3662,6 +3674,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  		if (enqd_len + trb_buff_len > full_len)
  			trb_buff_len = full_len - enqd_len;
  
@@ -86,7 +86,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  			first_trb = false;
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1905,6 +1905,7 @@ struct xhci_hcd {
+@@ -1910,6 +1910,7 @@ struct xhci_hcd {
  #define XHCI_ZHAOXIN_HOST	BIT_ULL(46)
  #define XHCI_AVOID_DQ_ON_LINK  BIT_ULL(47)
  #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch b/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch
index e3f1848ad5..fecee7d952 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch
@@ -13,7 +13,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
 
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3605,7 +3605,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3606,7 +3606,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	unsigned int num_trbs;
  	unsigned int start_cycle, num_sgs = 0;
  	unsigned int enqd_len, block_len, trb_buff_len, full_len;
@@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	u32 field, length_field, remainder, maxpacket;
  	u64 addr, send_addr;
  
-@@ -3651,14 +3651,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3652,14 +3652,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	send_addr = addr;
  
  	if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG &&
@@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	}
  
  	/* Queue the TRBs, even if they are zero-length */
-@@ -3673,7 +3668,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3674,7 +3669,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  		if (enqd_len + trb_buff_len > full_len)
  			trb_buff_len = full_len - enqd_len;
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch b/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch
index f604759c2f..1afe830091 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch
@@ -31,7 +31,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
 
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -1012,11 +1012,13 @@ static int xhci_invalidate_cancelled_tds
+@@ -1013,11 +1013,13 @@ static int xhci_invalidate_cancelled_tds
  						 td->urb->stream_id, td->urb,
  						 cached_td->urb->stream_id, cached_td->urb);
  				cached_td = td;
@@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  		}
  	}
  
-@@ -1264,10 +1266,7 @@ static void update_ring_for_set_deq_comp
+@@ -1265,10 +1267,7 @@ static void update_ring_for_set_deq_comp
  		unsigned int ep_index)
  {
  	union xhci_trb *dequeue_temp;
@@ -56,7 +56,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dequeue_temp = ep_ring->dequeue;
  
  	/* If we get two back-to-back stalls, and the first stalled transfer
-@@ -1282,8 +1281,6 @@ static void update_ring_for_set_deq_comp
+@@ -1283,8 +1282,6 @@ static void update_ring_for_set_deq_comp
  	}
  
  	while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
@@ -65,7 +65,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  		ep_ring->dequeue++;
  		if (trb_is_link(ep_ring->dequeue)) {
  			if (ep_ring->dequeue ==
-@@ -1293,15 +1290,10 @@ static void update_ring_for_set_deq_comp
+@@ -1294,15 +1291,10 @@ static void update_ring_for_set_deq_comp
  			ep_ring->dequeue = ep_ring->deq_seg->trbs;
  		}
  		if (ep_ring->dequeue == dequeue_temp) {
diff --git a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch
index ade55cf337..ab0bae587b 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch
@@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3582,6 +3582,48 @@ static int xhci_align_td(struct xhci_hcd
+@@ -3583,6 +3583,48 @@ static int xhci_align_td(struct xhci_hcd
  	return 1;
  }
  
@@ -89,7 +89,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  /* This is very similar to what ehci-q.c qtd_fill() does */
  int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
  		struct urb *urb, int slot_id, unsigned int ep_index)
-@@ -3750,6 +3792,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3751,6 +3793,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	}
  
  	check_trb_math(urb, enqd_len);
@@ -98,7 +98,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
  			start_cycle, start_trb);
  	return 0;
-@@ -3885,6 +3929,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3886,6 +3930,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
  			/* Event on completion */
  			field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
  
@@ -109,7 +109,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	return 0;
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1906,6 +1906,7 @@ struct xhci_hcd {
+@@ -1911,6 +1911,7 @@ struct xhci_hcd {
  #define XHCI_AVOID_DQ_ON_LINK  BIT_ULL(47)
  #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48)
  #define XHCI_VLI_SS_BULK_OUT_BUG       BIT_ULL(49)
diff --git a/target/linux/bcm27xx/patches-6.1/950-0513-net-bcmgenet-Add-eee-module-parameter.patch b/target/linux/bcm27xx/patches-6.1/950-0513-net-bcmgenet-Add-eee-module-parameter.patch
index cd9820fc9d..1d035c105c 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0513-net-bcmgenet-Add-eee-module-parameter.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0513-net-bcmgenet-Add-eee-module-parameter.patch
@@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  
  static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  {
-@@ -3440,6 +3443,17 @@ static int bcmgenet_open(struct net_devi
+@@ -3448,6 +3451,17 @@ static int bcmgenet_open(struct net_devi
  
  	bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
  
diff --git a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
index e67cb66880..cf92da67a8 100644
--- a/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
+++ b/target/linux/bcm27xx/patches-6.1/950-0865-usb-dwc3-Set-DMA-and-coherent-masks-early.patch
@@ -212,7 +212,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	},
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -1179,6 +1179,24 @@ static void dwc3_config_threshold(struct
+@@ -1180,6 +1180,24 @@ static void dwc3_config_threshold(struct
  	}
  }
  
@@ -237,7 +237,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  /**
   * dwc3_core_init - Low-level initialization of DWC3 Core
   * @dwc: Pointer to our controller context structure
-@@ -1271,6 +1289,8 @@ static int dwc3_core_init(struct dwc3 *d
+@@ -1257,6 +1275,8 @@ static int dwc3_core_init(struct dwc3 *d
  
  	dwc3_set_incr_burst_type(dwc);
  
@@ -246,7 +246,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	usb_phy_set_suspend(dwc->usb2_phy, 0);
  	usb_phy_set_suspend(dwc->usb3_phy, 0);
  	ret = phy_power_on(dwc->usb2_generic_phy);
-@@ -1504,6 +1524,7 @@ static void dwc3_get_properties(struct d
+@@ -1490,6 +1510,7 @@ static void dwc3_get_properties(struct d
  	u8			tx_thr_num_pkt_prd = 0;
  	u8			tx_max_burst_prd = 0;
  	u8			tx_fifo_resize_max_num;
@@ -254,7 +254,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	const char		*usb_psy_name;
  	int			ret;
  
-@@ -1526,6 +1547,9 @@ static void dwc3_get_properties(struct d
+@@ -1512,6 +1533,9 @@ static void dwc3_get_properties(struct d
  	 */
  	tx_fifo_resize_max_num = 6;
  
@@ -264,7 +264,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->maximum_speed = usb_get_maximum_speed(dev);
  	dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
  	dwc->dr_mode = usb_get_dr_mode(dev);
-@@ -1641,6 +1665,9 @@ static void dwc3_get_properties(struct d
+@@ -1627,6 +1651,9 @@ static void dwc3_get_properties(struct d
  	dwc->dis_split_quirk = device_property_read_bool(dev,
  				"snps,dis-split-quirk");
  
@@ -274,7 +274,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  	dwc->tx_de_emphasis = tx_de_emphasis;
  
-@@ -1658,6 +1685,8 @@ static void dwc3_get_properties(struct d
+@@ -1644,6 +1671,8 @@ static void dwc3_get_properties(struct d
  	dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
  	dwc->tx_max_burst_prd = tx_max_burst_prd;
  
@@ -283,7 +283,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	dwc->imod_interval = 0;
  
  	dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
-@@ -1866,6 +1895,12 @@ static int dwc3_probe(struct platform_de
+@@ -1852,6 +1881,12 @@ static int dwc3_probe(struct platform_de
  
  	dwc3_get_properties(dwc);
  
@@ -326,7 +326,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  
 --- a/drivers/usb/dwc3/host.c
 +++ b/drivers/usb/dwc3/host.c
-@@ -30,10 +30,10 @@ static void dwc3_host_fill_xhci_irq_res(
+@@ -51,10 +51,10 @@ static void dwc3_host_fill_xhci_irq_res(
  
  static int dwc3_host_get_irq(struct dwc3 *dwc)
  {
@@ -339,7 +339,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (irq > 0) {
  		dwc3_host_fill_xhci_irq_res(dwc, irq, "host");
  		goto out;
-@@ -42,7 +42,7 @@ static int dwc3_host_get_irq(struct dwc3
+@@ -63,7 +63,7 @@ static int dwc3_host_get_irq(struct dwc3
  	if (irq == -EPROBE_DEFER)
  		goto out;
  
@@ -348,7 +348,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (irq > 0) {
  		dwc3_host_fill_xhci_irq_res(dwc, irq, "dwc_usb3");
  		goto out;
-@@ -51,7 +51,7 @@ static int dwc3_host_get_irq(struct dwc3
+@@ -72,7 +72,7 @@ static int dwc3_host_get_irq(struct dwc3
  	if (irq == -EPROBE_DEFER)
  		goto out;
  
@@ -357,7 +357,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  	if (irq > 0) {
  		dwc3_host_fill_xhci_irq_res(dwc, irq, NULL);
  		goto out;
-@@ -66,16 +66,23 @@ out:
+@@ -87,16 +87,23 @@ out:
  
  int dwc3_host_init(struct dwc3 *dwc)
  {
diff --git a/target/linux/bcm47xx/Makefile b/target/linux/bcm47xx/Makefile
index 22fc36e9b1..325a207d08 100644
--- a/target/linux/bcm47xx/Makefile
+++ b/target/linux/bcm47xx/Makefile
@@ -10,8 +10,8 @@ BOARDNAME:=Broadcom BCM47xx/53xx (MIPS)
 FEATURES:=squashfs usb
 SUBTARGETS:=generic mips74k legacy
 
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM.
diff --git a/target/linux/bcm47xx/config-5.15 b/target/linux/bcm47xx/config-5.15
deleted file mode 100644
index 6f091c0e7f..0000000000
--- a/target/linux/bcm47xx/config-5.15
+++ /dev/null
@@ -1,176 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BCM47XX=y
-CONFIG_BCM47XX_BCMA=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM47XX_SPROM=y
-CONFIG_BCM47XX_SSB=y
-CONFIG_BCM47XX_WDT=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-CONFIG_BCMA_DRIVER_MIPS=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_NFLASH=y
-CONFIG_BCMA_PFLASH=y
-CONFIG_BCMA_SFLASH=y
-# CONFIG_BGMAC_BCMA is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-# CONFIG_COMMON_CLK is not set
-CONFIG_COMPAT_32BIT_TIME=y
-# CONFIG_CPU_BMIPS is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_EARLY_PRINTK is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WDT=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BCM47XXSFLASH=y
-CONFIG_MTD_BCM47XX_PARTS=y
-CONFIG_MTD_NAND_BCM47XXNFLASH=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_BRCMNAND_BCMA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_OF is not set
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SRCU=y
-CONFIG_SSB=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_DRIVER_EXTIF=y
-CONFIG_SSB_DRIVER_GIGE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_SSB_DRIVER_MIPS=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_EMBEDDED=y
-CONFIG_SSB_HOST_SOC=y
-CONFIG_SSB_PCICORE_HOSTMODE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_SERIAL=y
-CONFIG_SSB_SFLASH=y
-CONFIG_SSB_SPROM=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_B53=y
-CONFIG_SWCONFIG_B53_PHY_DRIVER=y
-CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_BMIPS=y
-CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
-CONFIG_WATCHDOG_CORE=y
diff --git a/target/linux/bcm47xx/config-6.6 b/target/linux/bcm47xx/config-6.6
new file mode 100644
index 0000000000..3b795941f3
--- /dev/null
+++ b/target/linux/bcm47xx/config-6.6
@@ -0,0 +1,196 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BCM47XX=y
+CONFIG_BCM47XX_BCMA=y
+CONFIG_BCM47XX_NVRAM=y
+CONFIG_BCM47XX_SPROM=y
+CONFIG_BCM47XX_SSB=y
+CONFIG_BCM47XX_WDT=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_MIPS=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
+CONFIG_BCMA_FALLBACK_SPROM=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_NFLASH=y
+CONFIG_BCMA_PFLASH=y
+CONFIG_BCMA_SFLASH=y
+# CONFIG_BGMAC_BCMA is not set
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_COMMON_CLK is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_CPU_BMIPS is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_WDT=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO_REGISTER=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BCM47XXSFLASH=y
+CONFIG_MTD_BCM47XX_PARTS=y
+CONFIG_MTD_NAND_BCM47XXNFLASH=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_BRCMNAND_BCMA=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_OF is not set
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_EXTIF=y
+CONFIG_SSB_DRIVER_GIGE=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_EMBEDDED=y
+CONFIG_SSB_FALLBACK_SPROM=y
+CONFIG_SSB_HOST_SOC=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SERIAL=y
+CONFIG_SSB_SFLASH=y
+CONFIG_SSB_SPROM=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_B53=y
+CONFIG_SWCONFIG_B53_PHY_DRIVER=y
+CONFIG_SWCONFIG_B53_PHY_FIXUP=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0xffffffff80400000
diff --git a/target/linux/bcm47xx/patches-5.15/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch b/target/linux/bcm47xx/patches-5.15/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch
deleted file mode 100644
index 921825be5c..0000000000
--- a/target/linux/bcm47xx/patches-5.15/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From eea175eedf3e2f71b9538d21e643e7a1be4923df Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:37 -0800
-Subject: [PATCH] MIPS: BCM47XX: Define Linksys WRT310N V2 buttons
-
-Update the buttons registration code to register the two buttons (WPS,
-system rester) using the existing BCM47XX_BOARD_LINKSYS_WRT310NV2 board
-entry.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -277,6 +277,12 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {
-+	BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
- 	BCM47XX_GPIO_KEY(5, KEY_WIMAX),
- 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -608,6 +614,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT310NV2:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
- 		break;
diff --git a/target/linux/bcm47xx/patches-5.15/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch b/target/linux/bcm47xx/patches-5.15/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch
deleted file mode 100644
index 3fb013a585..0000000000
--- a/target/linux/bcm47xx/patches-5.15/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 3829e4f10a232964cc728c0479c8097922e5e073 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:38 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add board entry for Linksys WRT320N v1
-
-This router is based on a Broadcom BCM4717A1 chipset and supports
-802.11n Wi-Fi. Add a board entry for that router and register LEDs and
-buttons accordingly.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c                          |  1 +
- arch/mips/bcm47xx/buttons.c                        |  9 +++++++++
- arch/mips/bcm47xx/leds.c                           | 10 ++++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h |  1 +
- 4 files changed, 21 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
- 	{{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
-+	{{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -283,6 +283,12 @@ bcm47xx_buttons_linksys_wrt310n_v2[] __i
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(8, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
- 	BCM47XX_GPIO_KEY(5, KEY_WIMAX),
- 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_LINKSYS_WRT310NV2:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
- 		break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -314,6 +314,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc
- };
- 
- static const struct gpio_led
-+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {
-+	BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-+	BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
- 	BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
- 	BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-@@ -689,6 +696,9 @@ void __init bcm47xx_leds_register(void)
- 	case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- 		bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -72,6 +72,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_LINKSYS_WRT300NV11,
- 	BCM47XX_BOARD_LINKSYS_WRT310NV1,
- 	BCM47XX_BOARD_LINKSYS_WRT310NV2,
-+	BCM47XX_BOARD_LINKSYS_WRT320N_V1,
- 	BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
- 	BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
- 	BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
diff --git a/target/linux/bcm47xx/patches-5.15/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch b/target/linux/bcm47xx/patches-5.15/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch
deleted file mode 100644
index c09140e99d..0000000000
--- a/target/linux/bcm47xx/patches-5.15/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From aecf89f2f8e8a604c33085c230a1f04ea325de64 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:39 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U
-
-Add the definitions for the buttons and LEDs used on the Asus RTN-10U
-router.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/buttons.c |  9 +++++++++
- arch/mips/bcm47xx/leds.c    | 11 +++++++++++
- 2 files changed, 20 insertions(+)
-
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -27,6 +27,12 @@
- /* Asus */
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_asus_rtn10u[] __initconst = {
-+	BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(21, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_asus_rtn12[] __initconst = {
- 	BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
- 	BCM47XX_GPIO_KEY(1, KEY_RESTART),
-@@ -490,6 +496,9 @@ int __init bcm47xx_buttons_register(void
- 	int err;
- 
- 	switch (board) {
-+	case BCM47XX_BOARD_ASUS_RTN10U:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u);
-+		break;
- 	case BCM47XX_BOARD_ASUS_RTN12:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
- 		break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -30,6 +30,14 @@
- /* Asus */
- 
- static const struct gpio_led
-+bcm47xx_leds_asus_rtn10u[] __initconst = {
-+	BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
-+	BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_asus_rtn12[] __initconst = {
- 	BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
- 	BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-@@ -563,6 +571,9 @@ void __init bcm47xx_leds_register(void)
- 	enum bcm47xx_board board = bcm47xx_board_get();
- 
- 	switch (board) {
-+	case BCM47XX_BOARD_ASUS_RTN10U:
-+		bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u);
-+		break;
- 	case BCM47XX_BOARD_ASUS_RTN12:
- 		bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
- 		break;
diff --git a/target/linux/bcm47xx/patches-5.15/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch b/target/linux/bcm47xx/patches-5.15/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch
deleted file mode 100644
index 8740942d6f..0000000000
--- a/target/linux/bcm47xx/patches-5.15/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 15e690af5cc3cd8f5d14ee2aa3a093f80196110e Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:40 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear R6300 v1
-
-Add support for the Netgear R6300 v1 Wi-Fi router using a Broadcom
-BCM4706 chipset and supporting 802.11n and 802.11ac.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c                          | 1 +
- arch/mips/bcm47xx/buttons.c                        | 8 ++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 10 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -162,6 +162,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- 	{{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
- 	{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
- 	{{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -410,6 +410,11 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_r6300_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- 	BCM47XX_GPIO_KEY(4, KEY_RESTART),
- 	BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -701,6 +706,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_NETGEAR_R6200_V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_R6300_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -100,6 +100,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
- 
- 	BCM47XX_BOARD_NETGEAR_R6200_V1,
-+	BCM47XX_BOARD_NETGEAR_R6300_V1,
- 	BCM47XX_BOARD_NETGEAR_WGR614V8,
- 	BCM47XX_BOARD_NETGEAR_WGR614V9,
- 	BCM47XX_BOARD_NETGEAR_WGR614_V10,
diff --git a/target/linux/bcm47xx/patches-5.15/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch b/target/linux/bcm47xx/patches-5.15/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch
deleted file mode 100644
index 6975bce952..0000000000
--- a/target/linux/bcm47xx/patches-5.15/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 4da27b6d550427a0560a15df36de99cb17629216 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:41 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2
-
-Add support for the Netgear WN2500 RP v1 and v2 Wi-Fi range extenders
-based on the BCM5357 chipset and supporting 802.11n and 802.11ac.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c                          | 2 ++
- arch/mips/bcm47xx/buttons.c                        | 9 +++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 2 ++
- 3 files changed, 13 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -166,6 +166,8 @@ struct bcm47xx_board_type_list1 bcm47xx_
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -415,6 +415,12 @@ bcm47xx_buttons_netgear_r6300_v1[] __ini
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = {
-+	BCM47XX_GPIO_KEY(12, KEY_RESTART),
-+	BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- 	BCM47XX_GPIO_KEY(4, KEY_RESTART),
- 	BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -709,6 +715,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_NETGEAR_R6300_V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_WN2500RP_V1:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -104,6 +104,8 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_NETGEAR_WGR614V8,
- 	BCM47XX_BOARD_NETGEAR_WGR614V9,
- 	BCM47XX_BOARD_NETGEAR_WGR614_V10,
-+	BCM47XX_BOARD_NETGEAR_WN2500RP_V1,
-+	BCM47XX_BOARD_NETGEAR_WN2500RP_V2,
- 	BCM47XX_BOARD_NETGEAR_WNDR3300,
- 	BCM47XX_BOARD_NETGEAR_WNDR3400V1,
- 	BCM47XX_BOARD_NETGEAR_WNDR3400V2,
diff --git a/target/linux/bcm47xx/patches-5.15/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch b/target/linux/bcm47xx/patches-5.15/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch
deleted file mode 100644
index 8c2233c804..0000000000
--- a/target/linux/bcm47xx/patches-5.15/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From c022e87162219d67d687df22c977d1c2fc95fb42 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 14 Jul 2022 14:13:01 -0700
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WNR3500L v2
-
-Add support for the Netgear WNR3500L v2 router based on the BCM47186
-chipset and supporting 802.11n Wi-Fi.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c                          |  2 ++
- arch/mips/bcm47xx/buttons.c                        | 10 ++++++++++
- arch/mips/bcm47xx/leds.c                           | 11 +++++++++++
- arch/mips/bcm47xx/workarounds.c                    |  1 +
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h |  1 +
- 5 files changed, 25 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -181,6 +181,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- 	{{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"},
-+	{{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "U12H172T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
-@@ -195,6 +196,7 @@ struct bcm47xx_board_type_list3 bcm47xx_
- 	{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
- 	{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
- 	{{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
-+	{{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "0x052b", "3500L", "02"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
- 	{{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -460,6 +460,13 @@ bcm47xx_buttons_netgear_wnr3500lv1[] __i
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_wnr3500lv2[] __initconst = {
-+	BCM47XX_GPIO_KEY(4, KEY_RESTART),
-+	BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(8, KEY_RFKILL),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wnr834bv2[] __initconst = {
- 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
- };
-@@ -736,6 +743,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_NETGEAR_WNR3500L:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv2);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNR834BV2:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2);
- 		break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -528,6 +528,14 @@ bcm47xx_leds_netgear_wnr3500lv1[] __init
- };
- 
- static const struct gpio_led
-+bcm47xx_leds_netgear_wnr3500lv2[] __initconst = {
-+	BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(1, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
-+	BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-+	BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
- 	BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
- 	BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
-@@ -791,6 +799,9 @@ void __init bcm47xx_leds_register(void)
- 	case BCM47XX_BOARD_NETGEAR_WNR3500L:
- 		bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1);
- 		break;
-+	case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
-+		bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv2);
-+		break;
- 	case BCM47XX_BOARD_NETGEAR_WNR834BV2:
- 		bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
- 		break;
---- a/arch/mips/bcm47xx/workarounds.c
-+++ b/arch/mips/bcm47xx/workarounds.c
-@@ -22,6 +22,7 @@ void __init bcm47xx_workarounds(void)
- 
- 	switch (board) {
- 	case BCM47XX_BOARD_NETGEAR_WNR3500L:
-+	case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
- 		bcm47xx_workarounds_enable_usb_power(12);
- 		break;
- 	case BCM47XX_BOARD_NETGEAR_WNDR3400V2:
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -118,6 +118,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_NETGEAR_WNR1000_V3,
- 	BCM47XX_BOARD_NETGEAR_WNR2000,
- 	BCM47XX_BOARD_NETGEAR_WNR3500L,
-+	BCM47XX_BOARD_NETGEAR_WNR3500L_V2,
- 	BCM47XX_BOARD_NETGEAR_WNR3500U,
- 	BCM47XX_BOARD_NETGEAR_WNR3500V2,
- 	BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
diff --git a/target/linux/bcm47xx/patches-5.15/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch b/target/linux/bcm47xx/patches-5.15/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch
deleted file mode 100644
index 4faecdc7d5..0000000000
--- a/target/linux/bcm47xx/patches-5.15/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From fc605b914167de75432c3b5aae239fb191e84a31 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 8 Feb 2023 08:03:01 +0100
-Subject: [PATCH] MIPS: BCM47XX: Add support for Linksys E2500 V3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's a BCM5358 based home WiFi router. 16 MiB flash, 64 MiB RAM, BCM5325
-switch, on-SoC 802.11n radio.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c                          | 1 +
- arch/mips/bcm47xx/buttons.c                        | 9 +++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 11 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -130,6 +130,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
- 	{{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"},
- 	{{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"},
- 	{{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
-+	{{BCM47XX_BOARD_LINKSYS_E2500V3, "Linksys E2500 V3"}, "E2500", "1.0"},
- 	/* like WRT610N v2.0 */
- 	{{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"},
- 	{{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -223,6 +223,12 @@ bcm47xx_buttons_linksys_e2000v1[] __init
- };
- 
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_e2500v3[] __initconst = {
-+	BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON),
-+	BCM47XX_GPIO_KEY(10, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_e3000v1[] __initconst = {
- 	BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
- 	BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void
- 	case BCM47XX_BOARD_LINKSYS_E2000V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1);
- 		break;
-+	case BCM47XX_BOARD_LINKSYS_E2500V3:
-+		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2500v3);
-+		break;
- 	case BCM47XX_BOARD_LINKSYS_E3000V1:
- 		err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -61,6 +61,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_LINKSYS_E1000V21,
- 	BCM47XX_BOARD_LINKSYS_E1200V2,
- 	BCM47XX_BOARD_LINKSYS_E2000V1,
-+	BCM47XX_BOARD_LINKSYS_E2500V3,
- 	BCM47XX_BOARD_LINKSYS_E3000V1,
- 	BCM47XX_BOARD_LINKSYS_E3200V1,
- 	BCM47XX_BOARD_LINKSYS_E4200V1,
diff --git a/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch b/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch
deleted file mode 100644
index f6f90a8165..0000000000
--- a/target/linux/bcm47xx/patches-5.15/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 1/9] mtd: rawnand: brcmnand: Assign soc as early as possible
-Date: Fri, 07 Jan 2022 10:46:06 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In order to key off the brcmnand_probe() code in subsequent changes
-depending upon ctrl->soc, assign that variable as early as possible,
-instead of much later when we have checked that it is non-NULL.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -3059,6 +3059,7 @@ int brcmnand_probe(struct platform_devic
- 
- 	dev_set_drvdata(dev, ctrl);
- 	ctrl->dev = dev;
-+	ctrl->soc = soc;
- 
- 	/* Enable the static key if the soc provides I/O operations indicating
- 	 * that a non-memory mapped IO access path must be used
-@@ -3209,8 +3210,6 @@ int brcmnand_probe(struct platform_devic
- 	 * interesting ways
- 	 */
- 	if (soc) {
--		ctrl->soc = soc;
--
- 		ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
- 				       DRV_NAME, ctrl);
- 
diff --git a/target/linux/bcm47xx/patches-5.15/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.15/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch
deleted file mode 100644
index 46cd377406..0000000000
--- a/target/linux/bcm47xx/patches-5.15/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 3/9] mtd: rawnand: brcmnand: Avoid pdev in brcmnand_init_cs()
-Date: Fri, 07 Jan 2022 10:46:08 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In preparation for encapsulating more of what the loop calling
-brcmnand_init_cs() does, avoid using platform_device when it is the
-device behind platform_device that we are using for printing errors.
-
-No functional changes introduced.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2814,7 +2814,7 @@ static const struct nand_controller_ops
- static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
- {
- 	struct brcmnand_controller *ctrl = host->ctrl;
--	struct platform_device *pdev = host->pdev;
-+	struct device *dev = ctrl->dev;
- 	struct mtd_info *mtd;
- 	struct nand_chip *chip;
- 	int ret;
-@@ -2822,7 +2822,7 @@ static int brcmnand_init_cs(struct brcmn
- 
- 	ret = of_property_read_u32(dn, "reg", &host->cs);
- 	if (ret) {
--		dev_err(&pdev->dev, "can't get chip-select\n");
-+		dev_err(dev, "can't get chip-select\n");
- 		return -ENXIO;
- 	}
- 
-@@ -2831,13 +2831,13 @@ static int brcmnand_init_cs(struct brcmn
- 
- 	nand_set_flash_node(chip, dn);
- 	nand_set_controller_data(chip, host);
--	mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
-+	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
- 				   host->cs);
- 	if (!mtd->name)
- 		return -ENOMEM;
- 
- 	mtd->owner = THIS_MODULE;
--	mtd->dev.parent = &pdev->dev;
-+	mtd->dev.parent = dev;
- 
- 	chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
- 	chip->legacy.cmdfunc = brcmnand_cmdfunc;
diff --git a/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch
deleted file mode 100644
index fdfd35a44f..0000000000
--- a/target/linux/bcm47xx/patches-5.15/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 4/9] mtd: rawnand: brcmnand: Move OF operations out of brcmnand_init_cs()
-Date: Fri, 07 Jan 2022 10:46:09 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In order to initialize a given chip select object for use by the
-brcmnand driver, move all of the Device Tree specific routines outside
-of brcmnand_init_cs() in order to make it usable in a platform data
-configuration which will be necessary for supporting BCMA chips.
-
-No functional changes introduced.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +++++++++++---------
- 1 file changed, 11 insertions(+), 9 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2811,7 +2811,7 @@ static const struct nand_controller_ops
- 	.attach_chip = brcmnand_attach_chip,
- };
- 
--static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
-+static int brcmnand_init_cs(struct brcmnand_host *host)
- {
- 	struct brcmnand_controller *ctrl = host->ctrl;
- 	struct device *dev = ctrl->dev;
-@@ -2820,16 +2820,9 @@ static int brcmnand_init_cs(struct brcmn
- 	int ret;
- 	u16 cfg_offs;
- 
--	ret = of_property_read_u32(dn, "reg", &host->cs);
--	if (ret) {
--		dev_err(dev, "can't get chip-select\n");
--		return -ENXIO;
--	}
--
- 	mtd = nand_to_mtd(&host->chip);
- 	chip = &host->chip;
- 
--	nand_set_flash_node(chip, dn);
- 	nand_set_controller_data(chip, host);
- 	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
- 				   host->cs);
-@@ -3240,7 +3233,16 @@ int brcmnand_probe(struct platform_devic
- 			host->pdev = pdev;
- 			host->ctrl = ctrl;
- 
--			ret = brcmnand_init_cs(host, child);
-+			ret = of_property_read_u32(child, "reg", &host->cs);
-+			if (ret) {
-+				dev_err(dev, "can't get chip-select\n");
-+				devm_kfree(dev, host);
-+				continue;
-+			}
-+
-+			nand_set_flash_node(&host->chip, child);
-+
-+			ret = brcmnand_init_cs(host);
- 			if (ret) {
- 				devm_kfree(dev, host);
- 				continue; /* Try all chip-selects */
diff --git a/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch b/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch
deleted file mode 100644
index 08cecf3d4a..0000000000
--- a/target/linux/bcm47xx/patches-5.15/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 5/9] mtd: rawnand: brcmnand: Allow working without interrupts
-Date: Fri, 07 Jan 2022 10:46:10 -0800
-Content-Type: text/plain; charset="utf-8"
-
-The BCMA devices include the brcmnand controller but they do not wire up
-any interrupt line, allow the main interrupt to be optional and update
-the completion path to also check for the lack of an interrupt line.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 52 +++++++++++-------------
- 1 file changed, 24 insertions(+), 28 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -216,7 +216,7 @@ struct brcmnand_controller {
- 	void __iomem		*nand_base;
- 	void __iomem		*nand_fc; /* flash cache */
- 	void __iomem		*flash_dma_base;
--	unsigned int		irq;
-+	int			irq;
- 	unsigned int		dma_irq;
- 	int			nand_version;
- 
-@@ -1650,7 +1650,7 @@ static bool brcmstb_nand_wait_for_comple
- 	bool err = false;
- 	int sts;
- 
--	if (mtd->oops_panic_write) {
-+	if (mtd->oops_panic_write || ctrl->irq < 0) {
- 		/* switch to interrupt polling and PIO mode */
- 		disable_ctrl_irqs(ctrl);
- 		sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
-@@ -3191,33 +3191,29 @@ int brcmnand_probe(struct platform_devic
- 	}
- 
- 	/* IRQ */
--	ctrl->irq = platform_get_irq(pdev, 0);
--	if ((int)ctrl->irq < 0) {
--		dev_err(dev, "no IRQ defined\n");
--		ret = -ENODEV;
--		goto err;
--	}
--
--	/*
--	 * Some SoCs integrate this controller (e.g., its interrupt bits) in
--	 * interesting ways
--	 */
--	if (soc) {
--		ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
--				       DRV_NAME, ctrl);
--
--		/* Enable interrupt */
--		ctrl->soc->ctlrdy_ack(ctrl->soc);
--		ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
--	} else {
--		/* Use standard interrupt infrastructure */
--		ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
--				       DRV_NAME, ctrl);
--	}
--	if (ret < 0) {
--		dev_err(dev, "can't allocate IRQ %d: error %d\n",
--			ctrl->irq, ret);
--		goto err;
-+	ctrl->irq = platform_get_irq_optional(pdev, 0);
-+	if (ctrl->irq > 0) {
-+		/*
-+		 * Some SoCs integrate this controller (e.g., its interrupt bits) in
-+		 * interesting ways
-+		 */
-+		if (soc) {
-+			ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
-+					       DRV_NAME, ctrl);
-+
-+			/* Enable interrupt */
-+			ctrl->soc->ctlrdy_ack(ctrl->soc);
-+			ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
-+		} else {
-+			/* Use standard interrupt infrastructure */
-+			ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
-+					       DRV_NAME, ctrl);
-+		}
-+		if (ret < 0) {
-+			dev_err(dev, "can't allocate IRQ %d: error %d\n",
-+				ctrl->irq, ret);
-+			goto err;
-+		}
- 	}
- 
- 	for_each_available_child_of_node(dn, child) {
diff --git a/target/linux/bcm47xx/patches-5.15/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch b/target/linux/bcm47xx/patches-5.15/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch
deleted file mode 100644
index 56c686f308..0000000000
--- a/target/linux/bcm47xx/patches-5.15/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 6/9] mtd: rawnand: brcmnand: Add platform data structure for BCMA
-Date: Fri, 07 Jan 2022 10:46:11 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Update the BCMA's chipcommon nand flash driver to detect which
-chip-select is used and pass that information via platform data to the
-brcmnand driver. Make sure that the brcmnand platform data structure is
-always at the beginning of the platform data of the "nflash" device
-created by BCMA to allow brcmnand to safely de-reference it.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- MAINTAINERS                                 |  1 +
- drivers/bcma/driver_chipcommon_nflash.c     | 20 +++++++++++++++++++-
- include/linux/bcma/bcma_driver_chipcommon.h |  5 +++++
- include/linux/platform_data/brcmnand.h      | 12 ++++++++++++
- 4 files changed, 37 insertions(+), 1 deletion(-)
- create mode 100644 include/linux/platform_data/brcmnand.h
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3901,6 +3901,7 @@ L:	linux-mtd@lists.infradead.org
- L:	bcm-kernel-feedback-list@broadcom.com
- S:	Maintained
- F:	drivers/mtd/nand/raw/brcmnand/
-+F:	include/linux/platform_data/brcmnand.h
- 
- BROADCOM STB PCIE DRIVER
- M:	Jim Quinlan <jim2101024@gmail.com>
---- a/drivers/bcma/driver_chipcommon_nflash.c
-+++ b/drivers/bcma/driver_chipcommon_nflash.c
-@@ -7,18 +7,28 @@
- 
- #include "bcma_private.h"
- 
-+#include <linux/bitops.h>
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/bcma/bcma.h>
- 
-+/* Alternate NAND controller driver name in order to allow both bcm47xxnflash
-+ * and bcma_brcmnand to be built into the same kernel image.
-+ */
-+static const char *bcma_nflash_alt_name = "bcma_brcmnand";
-+
- struct platform_device bcma_nflash_dev = {
- 	.name		= "bcma_nflash",
- 	.num_resources	= 0,
- };
- 
-+static const char *probes[] = { "bcm47xxpart", NULL };
-+
- /* Initialize NAND flash access */
- int bcma_nflash_init(struct bcma_drv_cc *cc)
- {
- 	struct bcma_bus *bus = cc->core->bus;
-+	u32 reg;
- 
- 	if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
- 	    cc->core->id.rev != 38) {
-@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc
- 
- 	cc->nflash.present = true;
- 	if (cc->core->id.rev == 38 &&
--	    (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
-+	    (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {
- 		cc->nflash.boot = true;
-+		/* Determine the chip select that is being used */
-+		reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;
-+		cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;
-+		cc->nflash.brcmnand_info.part_probe_types = probes;
-+		cc->nflash.brcmnand_info.ecc_stepsize = 512;
-+		cc->nflash.brcmnand_info.ecc_strength = 1;
-+		bcma_nflash_dev.name = bcma_nflash_alt_name;
-+	}
- 
- 	/* Prepare platform device, but don't register it yet. It's too early,
- 	 * malloc (required by device_private_init) is not available yet. */
---- a/include/linux/bcma/bcma_driver_chipcommon.h
-+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -3,6 +3,7 @@
- #define LINUX_BCMA_DRIVER_CC_H_
- 
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/gpio.h>
- 
- /** ChipCommon core registers. **/
-@@ -599,6 +600,10 @@ struct bcma_sflash {
- 
- #ifdef CONFIG_BCMA_NFLASH
- struct bcma_nflash {
-+	/* Must be the fist member for the brcmnand driver to
-+	 * de-reference that structure.
-+	 */
-+	struct brcmnand_platform_data brcmnand_info;
- 	bool present;
- 	bool boot;		/* This is the flash the SoC boots from */
- };
---- /dev/null
-+++ b/include/linux/platform_data/brcmnand.h
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+#ifndef BRCMNAND_PLAT_DATA_H
-+#define BRCMNAND_PLAT_DATA_H
-+
-+struct brcmnand_platform_data {
-+	int	chip_select;
-+	const char * const *part_probe_types;
-+	unsigned int ecc_stepsize;
-+	unsigned int ecc_strength;
-+};
-+
-+#endif /* BRCMNAND_PLAT_DATA_H */
diff --git a/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch b/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch
deleted file mode 100644
index 4942389b5a..0000000000
--- a/target/linux/bcm47xx/patches-5.15/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 7/9] mtd: rawnand: brcmnand: Allow platform data instantation
-Date: Fri, 07 Jan 2022 10:46:12 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Make use of the recently refactored code in brcmnand_init_cs() and
-derive the chip-select from the platform data that is supplied. Update
-the various code paths to avoid relying on possibly non-existent
-resources, too.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 45 ++++++++++++++++++------
- 1 file changed, 35 insertions(+), 10 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -9,6 +9,7 @@
- #include <linux/delay.h>
- #include <linux/device.h>
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/err.h>
- #include <linux/completion.h>
- #include <linux/interrupt.h>
-@@ -2811,7 +2812,8 @@ static const struct nand_controller_ops
- 	.attach_chip = brcmnand_attach_chip,
- };
- 
--static int brcmnand_init_cs(struct brcmnand_host *host)
-+static int brcmnand_init_cs(struct brcmnand_host *host,
-+			    const char * const *part_probe_types)
- {
- 	struct brcmnand_controller *ctrl = host->ctrl;
- 	struct device *dev = ctrl->dev;
-@@ -2864,7 +2866,7 @@ static int brcmnand_init_cs(struct brcmn
- 	if (ret)
- 		return ret;
- 
--	ret = mtd_device_register(mtd, NULL, 0);
-+	ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
- 	if (ret)
- 		nand_cleanup(chip);
- 
-@@ -3033,17 +3035,15 @@ static int brcmnand_edu_setup(struct pla
- 
- int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
- {
-+	struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
- 	struct device *dev = &pdev->dev;
- 	struct device_node *dn = dev->of_node, *child;
- 	struct brcmnand_controller *ctrl;
-+	struct brcmnand_host *host;
- 	struct resource *res;
- 	int ret;
- 
--	/* We only support device-tree instantiation */
--	if (!dn)
--		return -ENODEV;
--
--	if (!of_match_node(brcmnand_of_match, dn))
-+	if (dn && !of_match_node(brcmnand_of_match, dn))
- 		return -ENODEV;
- 
- 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-@@ -3070,7 +3070,7 @@ int brcmnand_probe(struct platform_devic
- 	/* NAND register range */
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	ctrl->nand_base = devm_ioremap_resource(dev, res);
--	if (IS_ERR(ctrl->nand_base))
-+	if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
- 		return PTR_ERR(ctrl->nand_base);
- 
- 	/* Enable clock before using NAND registers */
-@@ -3218,7 +3218,6 @@ int brcmnand_probe(struct platform_devic
- 
- 	for_each_available_child_of_node(dn, child) {
- 		if (of_device_is_compatible(child, "brcm,nandcs")) {
--			struct brcmnand_host *host;
- 
- 			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- 			if (!host) {
-@@ -3238,7 +3237,7 @@ int brcmnand_probe(struct platform_devic
- 
- 			nand_set_flash_node(&host->chip, child);
- 
--			ret = brcmnand_init_cs(host);
-+			ret = brcmnand_init_cs(host, NULL);
- 			if (ret) {
- 				devm_kfree(dev, host);
- 				continue; /* Try all chip-selects */
-@@ -3248,6 +3247,32 @@ int brcmnand_probe(struct platform_devic
- 		}
- 	}
- 
-+	if (!list_empty(&ctrl->host_list))
-+		return 0;
-+
-+	if (!pd) {
-+		ret = -ENODEV;
-+		goto err;
-+	}
-+
-+	/* If we got there we must have been probing via platform data */
-+	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-+	if (!host) {
-+		ret = -ENOMEM;
-+		goto err;
-+	}
-+	host->pdev = pdev;
-+	host->ctrl = ctrl;
-+	host->cs = pd->chip_select;
-+	host->chip.ecc.size = pd->ecc_stepsize;
-+	host->chip.ecc.strength = pd->ecc_strength;
-+
-+	ret = brcmnand_init_cs(host, pd->part_probe_types);
-+	if (ret)
-+		goto err;
-+
-+	list_add_tail(&host->node, &ctrl->host_list);
-+
- 	/* No chip-selects could initialize properly */
- 	if (list_empty(&ctrl->host_list)) {
- 		ret = -ENODEV;
diff --git a/target/linux/bcm47xx/patches-5.15/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch b/target/linux/bcm47xx/patches-5.15/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch
deleted file mode 100644
index 50cc4a6b22..0000000000
--- a/target/linux/bcm47xx/patches-5.15/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 8/9] mtd: rawnand: brcmnand: BCMA controller uses command shift of 0
-Date: Fri, 07 Jan 2022 10:46:13 -0800
-Content-Type: text/plain; charset="utf-8"
-
-For some odd and unexplained reason the BCMA NAND controller, albeit
-revision 3.4 uses a command shift of 0 instead of 24 as it should be,
-quirk that.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -951,6 +951,12 @@ static void brcmnand_wr_corr_thresh(stru
- 
- static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
- {
-+	/* Kludge for the BCMA-based NAND controller which does not actually
-+	 * shift the command
-+	 */
-+	if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
-+		return 0;
-+
- 	if (ctrl->nand_version < 0x0602)
- 		return 24;
- 	return 0;
diff --git a/target/linux/bcm47xx/patches-5.15/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch b/target/linux/bcm47xx/patches-5.15/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch
deleted file mode 100644
index 38fd3a30a6..0000000000
--- a/target/linux/bcm47xx/patches-5.15/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 9/9] mtd: rawnand: brcmnand: Add BCMA shim
-Date: Fri, 07 Jan 2022 10:46:14 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Add a BCMA shim to allow us to register the brcmnand driver using the
-BCMA bus which provides indirect memory mapped access to SoC registers.
-
-There are a number of registers that need to be byte swapped because
-they are natively big endian, coming directly from the NAND chip, and
-there is no bus interface unlike the iProc or STB platforms that
-performs the byte swapping for us.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/Kconfig              |  13 +++
- drivers/mtd/nand/raw/brcmnand/Makefile    |   2 +
- drivers/mtd/nand/raw/brcmnand/bcma_nand.c | 132 ++++++++++++++++++++++
- drivers/mtd/nand/raw/brcmnand/brcmnand.c  |   4 +
- 4 files changed, 151 insertions(+)
- create mode 100644 drivers/mtd/nand/raw/brcmnand/bcma_nand.c
-
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -208,6 +208,19 @@ config MTD_NAND_BRCMNAND
- 	  originally designed for Set-Top Box but is used on various BCM7xxx,
- 	  BCM3xxx, BCM63xxx, iProc/Cygnus and more.
- 
-+if MTD_NAND_BRCMNAND
-+
-+config MTD_NAND_BRCMNAND_BCMA
-+	tristate "Broadcom BCMA NAND controller"
-+	depends on BCMA_NFLASH
-+	depends on BCMA
-+	help
-+	  Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.
-+	  The glue driver will take care of performing the low-level I/O
-+	  operations to interface the BRCMNAND controller over the BCMA bus.
-+
-+endif # MTD_NAND_BRCMNAND
-+
- config MTD_NAND_BCM47XXNFLASH
- 	tristate "BCM4706 BCMA NAND controller"
- 	depends on BCMA_NFLASH
---- a/drivers/mtd/nand/raw/brcmnand/Makefile
-+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
-@@ -6,3 +6,5 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= bcm6
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= bcm6368_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmstb_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand.o
-+
-+obj-$(CONFIG_MTD_NAND_BRCMNAND_BCMA)	+= bcma_nand.o
---- /dev/null
-+++ b/drivers/mtd/nand/raw/brcmnand/bcma_nand.c
-@@ -0,0 +1,132 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright © 2021 Broadcom
-+ */
-+#include <linux/bcma/bcma.h>
-+#include <linux/bcma/bcma_driver_chipcommon.h>
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include "brcmnand.h"
-+
-+struct brcmnand_bcma_soc {
-+	struct brcmnand_soc soc;
-+	struct bcma_drv_cc *cc;
-+};
-+
-+static inline bool brcmnand_bcma_needs_swapping(u32 offset)
-+{
-+	switch (offset) {
-+	case BCMA_CC_NAND_SPARE_RD0:
-+	case BCMA_CC_NAND_SPARE_RD4:
-+	case BCMA_CC_NAND_SPARE_RD8:
-+	case BCMA_CC_NAND_SPARE_RD12:
-+	case BCMA_CC_NAND_SPARE_WR0:
-+	case BCMA_CC_NAND_SPARE_WR4:
-+	case BCMA_CC_NAND_SPARE_WR8:
-+	case BCMA_CC_NAND_SPARE_WR12:
-+	case BCMA_CC_NAND_DEVID:
-+	case BCMA_CC_NAND_DEVID_X:
-+	case BCMA_CC_NAND_SPARE_RD16:
-+	case BCMA_CC_NAND_SPARE_RD20:
-+	case BCMA_CC_NAND_SPARE_RD24:
-+	case BCMA_CC_NAND_SPARE_RD28:
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc)
-+{
-+	return container_of(soc, struct brcmnand_bcma_soc, soc);
-+}
-+
-+static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset)
-+{
-+	struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+	u32 val;
-+
-+	/* Offset into the NAND block and deal with the flash cache separately */
-+	if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
-+		offset = BCMA_CC_NAND_CACHE_DATA;
-+	else
-+		offset += BCMA_CC_NAND_REVISION;
-+
-+	val = bcma_cc_read32(sc->cc, offset);
-+
-+	/* Swap if necessary */
-+	if (brcmnand_bcma_needs_swapping(offset))
-+		val = be32_to_cpu(val);
-+	return val;
-+}
-+
-+static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val,
-+				    u32 offset)
-+{
-+	struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+
-+	/* Offset into the NAND block */
-+	if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
-+		offset = BCMA_CC_NAND_CACHE_DATA;
-+	else
-+		offset += BCMA_CC_NAND_REVISION;
-+
-+	/* Swap if necessary */
-+	if (brcmnand_bcma_needs_swapping(offset))
-+		val = cpu_to_be32(val);
-+
-+	bcma_cc_write32(sc->cc, offset, val);
-+}
-+
-+static struct brcmnand_io_ops brcmnand_bcma_io_ops = {
-+	.read_reg	= brcmnand_bcma_read_reg,
-+	.write_reg	= brcmnand_bcma_write_reg,
-+};
-+
-+static void brcmnand_bcma_prepare_data_bus(struct brcmnand_soc *soc, bool prepare,
-+					   bool is_param)
-+{
-+	struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+
-+	/* Reset the cache address to ensure we are already accessing the
-+	 * beginning of a sub-page.
-+	 */
-+	bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0);
-+}
-+
-+static int brcmnand_bcma_nand_probe(struct platform_device *pdev)
-+{
-+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
-+	struct brcmnand_bcma_soc *soc;
-+
-+	soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
-+	if (!soc)
-+		return -ENOMEM;
-+
-+	soc->cc = container_of(nflash, struct bcma_drv_cc, nflash);
-+	soc->soc.prepare_data_bus = brcmnand_bcma_prepare_data_bus;
-+	soc->soc.ops = &brcmnand_bcma_io_ops;
-+
-+	if (soc->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
-+		dev_err(&pdev->dev, "Use bcm47xxnflash for 4706!\n");
-+		return -ENODEV;
-+	}
-+
-+	return brcmnand_probe(pdev, &soc->soc);
-+}
-+
-+static struct platform_driver brcmnand_bcma_nand_driver = {
-+	.probe			= brcmnand_bcma_nand_probe,
-+	.remove			= brcmnand_remove,
-+	.driver = {
-+		.name		= "bcma_brcmnand",
-+		.pm		= &brcmnand_pm_ops,
-+	}
-+};
-+module_platform_driver(brcmnand_bcma_nand_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Broadcom");
-+MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips");
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -627,7 +627,11 @@ enum {
- 
- static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
- {
-+#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
- 	return static_branch_unlikely(&brcmnand_soc_has_ops_key);
-+#else
-+	return false;
-+#endif
- }
- 
- static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
diff --git a/target/linux/bcm47xx/patches-5.15/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch b/target/linux/bcm47xx/patches-5.15/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch
deleted file mode 100644
index 333c3d7b87..0000000000
--- a/target/linux/bcm47xx/patches-5.15/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 27 Feb 2023 07:44:38 +0100
-Subject: [PATCH] MIPS: BCM47XX: Add support for Huawei B593u-12
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's a BCM5358 based home router. One of very few bcm47xx devices with
-cellular modems (here: LTE).
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- arch/mips/bcm47xx/board.c                          | 1 +
- arch/mips/bcm47xx/leds.c                           | 8 ++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 10 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- /* boardtype, boardnum, boardrev */
- static const
- struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
-+	{{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"},
- 	{{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
- 	{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
- 	{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -223,6 +223,11 @@ bcm47xx_leds_dlink_dir330[] __initconst
- /* Huawei */
- 
- static const struct gpio_led
-+bcm47xx_leds_huawei_b593u_12[] __initconst = {
-+	BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_huawei_e970[] __initconst = {
- 	BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
- };
-@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void)
- 		bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
- 		break;
- 
-+	case BCM47XX_BOARD_HUAWEI_B593U_12:
-+		bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12);
-+		break;
- 	case BCM47XX_BOARD_HUAWEI_E970:
- 		bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
- 		break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -53,6 +53,7 @@ enum bcm47xx_board {
- 	BCM47XX_BOARD_DLINK_DIR130,
- 	BCM47XX_BOARD_DLINK_DIR330,
- 
-+	BCM47XX_BOARD_HUAWEI_B593U_12,
- 	BCM47XX_BOARD_HUAWEI_E970,
- 
- 	BCM47XX_BOARD_LINKSYS_E900V1,
diff --git a/target/linux/bcm47xx/patches-5.15/159-cpu_fixes.patch b/target/linux/bcm47xx/patches-5.15/159-cpu_fixes.patch
deleted file mode 100644
index fe7eff1911..0000000000
--- a/target/linux/bcm47xx/patches-5.15/159-cpu_fixes.patch
+++ /dev/null
@@ -1,484 +0,0 @@
---- a/arch/mips/include/asm/r4kcache.h
-+++ b/arch/mips/include/asm/r4kcache.h
-@@ -27,6 +27,38 @@
- extern void (*r4k_blast_dcache)(void);
- extern void (*r4k_blast_icache)(void);
- 
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
-+
-+static inline unsigned long bcm4710_dummy_rreg(void)
-+{
-+      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
-+}
-+
-+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
-+
-+static inline unsigned long bcm4710_fill_tlb(void *addr)
-+{
-+      return *(unsigned long *)addr;
-+}
-+
-+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
-+
-+static inline void bcm4710_protected_fill_tlb(void *addr)
-+{
-+      unsigned long x;
-+      get_dbe(x, (unsigned long *)addr);;
-+}
-+
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
-  * This macro return a properly sign-extended address suitable as base address
-  * for indexed cache operations.  Two issues here:
-@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
- 
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Index_Writeback_Inv_D, addr);
- }
- 
-@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
- 
- static inline void flush_dcache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Writeback_Inv_D, addr);
- }
- 
- static inline void invalidate_dcache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	cache_op(Hit_Invalidate_D, addr);
- }
- 
-@@ -160,6 +195,7 @@ static inline int protected_flush_icache
- 		return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
- 
- 	default:
-+		BCM4710_DUMMY_RREG();
- 		return protected_cache_op(Hit_Invalidate_I, addr);
- 	}
- }
-@@ -172,6 +208,7 @@ static inline int protected_flush_icache
-  */
- static inline int protected_writeback_dcache_line(unsigned long addr)
- {
-+	BCM4710_DUMMY_RREG();
- 	return protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
- 
-@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
- 	unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));	\
- } while (0)
- 
-+static inline void blast_dcache(void)
-+{
-+	unsigned long start = KSEG0;
-+	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+	unsigned long end = (start + dcache_size);
-+
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Index_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+
-+	BCM4710_FILL_TLB(start);
-+	do {
-+		BCM4710_DUMMY_RREG();
-+		cache_op(Hit_Writeback_Inv_D, start);
-+		start += current_cpu_data.dcache.linesz;
-+	} while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+	unsigned long start = page;
-+	unsigned long end = start + PAGE_SIZE;
-+	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+	unsigned long ws_end = current_cpu_data.dcache.ways <<
-+	                       current_cpu_data.dcache.waybit;
-+	unsigned long ws, addr;
-+	for (ws = 0; ws < ws_end; ws += ws_inc) {
-+		start = page + ws;
-+		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+			BCM4710_DUMMY_RREG();
-+			cache_op(Index_Writeback_Inv_D, addr);
-+		}
-+	}
-+}
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
- static inline void extra##blast_##pfx##cache##lsize(void)		\
- {									\
- 	unsigned long start = INDEX_BASE;				\
-@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
- 			       current_cpu_data.desc.waybit;		\
- 	unsigned long ws, addr;						\
- 									\
-+	war								\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
- 		for (addr = start; addr < end; addr += lsize * 32)	\
- 			cache_unroll(32, kernel_cache, indexop,		\
-@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
- 	unsigned long start = page;					\
- 	unsigned long end = page + PAGE_SIZE;				\
- 									\
-+	war								\
- 	do {								\
- 		cache_unroll(32, kernel_cache, hitop, start, lsize);	\
- 		start += lsize * 32;					\
-@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
- 			       current_cpu_data.desc.waybit;		\
- 	unsigned long ws, addr;						\
- 									\
-+	war								\
- 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
- 		for (addr = start; addr < end; addr += lsize * 32)	\
- 			cache_unroll(32, kernel_cache, indexop,		\
- 				     addr | ws, lsize);			\
- }
- 
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
- 
- #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
- static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
-@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
- __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
- 
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)	\
- static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
- 						    unsigned long end)	\
- {									\
- 	unsigned long lsize = cpu_##desc##_line_size();			\
--	unsigned long lsize_2 = lsize * 2;				\
--	unsigned long lsize_3 = lsize * 3;				\
--	unsigned long lsize_4 = lsize * 4;				\
--	unsigned long lsize_5 = lsize * 5;				\
--	unsigned long lsize_6 = lsize * 6;				\
--	unsigned long lsize_7 = lsize * 7;				\
--	unsigned long lsize_8 = lsize * 8;				\
- 	unsigned long addr = start & ~(lsize - 1);			\
--	unsigned long aend = (end + lsize - 1) & ~(lsize - 1);		\
--	int lines = (aend - addr) / lsize;				\
--									\
--	while (lines >= 8) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		prot##cache_op(hitop, addr + lsize_2);			\
--		prot##cache_op(hitop, addr + lsize_3);			\
--		prot##cache_op(hitop, addr + lsize_4);			\
--		prot##cache_op(hitop, addr + lsize_5);			\
--		prot##cache_op(hitop, addr + lsize_6);			\
--		prot##cache_op(hitop, addr + lsize_7);			\
--		addr += lsize_8;					\
--		lines -= 8;						\
--	}								\
-+	unsigned long aend = (end - 1) & ~(lsize - 1);			\
- 									\
--	if (lines & 0x4) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		prot##cache_op(hitop, addr + lsize_2);			\
--		prot##cache_op(hitop, addr + lsize_3);			\
--		addr += lsize_4;					\
--	}								\
--									\
--	if (lines & 0x2) {						\
--		prot##cache_op(hitop, addr);				\
--		prot##cache_op(hitop, addr + lsize);			\
--		addr += lsize_2;					\
--	}								\
-+	war								\
- 									\
--	if (lines & 0x1) {						\
-+	while (1) {							\
-+		war2							\
- 		prot##cache_op(hitop, addr);				\
-+		if (addr == aend)					\
-+			break;						\
-+		addr += lsize;						\
- 	}								\
- }
- 
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
- __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
--	protected_, loongson2_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
-+	protected_, loongson2_, , )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
- 
- /* Currently, this is very specific to Loongson-3 */
- #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
---- a/arch/mips/include/asm/stackframe.h
-+++ b/arch/mips/include/asm/stackframe.h
-@@ -429,6 +429,10 @@
- #else
- 		.set	push
- 		.set	arch=r4000
-+#ifdef CONFIG_BCM47XX
-+		nop
-+		nop
-+#endif
- 		eret
- 		.set	pop
- #endif
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -22,6 +22,19 @@
- #include <asm/war.h>
- #include <asm/thread_info.h>
- 
-+#ifdef CONFIG_BCM47XX
-+# ifdef eret
-+#  undef eret
-+# endif
-+# define eret 					\
-+	.set push;				\
-+	.set noreorder;				\
-+	 nop; 					\
-+	 nop;					\
-+	 eret;					\
-+	.set pop;
-+#endif
-+
- 	__INIT
- 
- /*
-@@ -33,6 +46,9 @@
- NESTED(except_vec3_generic, 0, sp)
- 	.set	push
- 	.set	noat
-+#ifdef CONFIG_BCM47XX
-+	nop
-+#endif
- 	mfc0	k1, CP0_CAUSE
- 	andi	k1, k1, 0x7c
- #ifdef CONFIG_64BIT
-@@ -53,6 +69,9 @@ NESTED(except_vec3_r4000, 0, sp)
- 	.set	push
- 	.set	arch=r4000
- 	.set	noat
-+#ifdef CONFIG_BCM47XX
-+	nop
-+#endif
- 	mfc0	k1, CP0_CAUSE
- 	li	k0, 31<<2
- 	andi	k1, k1, 0x7c
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -38,6 +38,9 @@
- #include <asm/traps.h>
- #include <asm/mips-cps.h>
- 
-+/* For enabling BCM4710 cache workarounds */
-+static int bcm4710 = 0;
-+
- /*
-  * Bits describing what cache ops an SMP callback function may perform.
-  *
-@@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
- {
- 	unsigned long  dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page = blast_dcache_page;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_user_page = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache_page_indexed = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
- {
- 	unsigned long dc_lsize = cpu_dcache_line_size();
- 
-+	if (bcm4710)
-+		r4k_blast_dcache = blast_dcache;
-+	else
- 	if (dc_lsize == 0)
- 		r4k_blast_dcache = (void *)cache_noop;
- 	else if (dc_lsize == 16)
-@@ -1826,6 +1838,17 @@ static void coherency_setup(void)
- 	 * silly idea of putting something else there ...
- 	 */
- 	switch (current_cpu_type()) {
-+	case CPU_BMIPS3300:
-+		{
-+			u32 cm;
-+			cm = read_c0_diag();
-+			/* Enable icache */
-+			cm |= (1 << 31);
-+			/* Enable dcache */
-+			cm |= (1 << 30);
-+			write_c0_diag(cm);
-+		}
-+		break;
- 	case CPU_R4000PC:
- 	case CPU_R4000SC:
- 	case CPU_R4000MC:
-@@ -1872,6 +1895,15 @@ void r4k_cache_init(void)
- 	extern void build_copy_page(void);
- 	struct cpuinfo_mips *c = &current_cpu_data;
- 
-+	/* Check if special workarounds are required */
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+	if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
-+		printk("Enabling BCM4710A0 cache workarounds.\n");
-+		bcm4710 = 1;
-+	} else
-+#endif
-+		bcm4710 = 0;
-+
- 	probe_pcache();
- 	probe_vcache();
- 	setup_scache();
-@@ -1944,7 +1976,15 @@ void r4k_cache_init(void)
- 	 */
- 	local_r4k___flush_cache_all(NULL);
- 
-+#ifdef CONFIG_BCM47XX
-+	{
-+		static void (*_coherency_setup)(void);
-+		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+		_coherency_setup();
-+	}
-+#else
- 	coherency_setup();
-+#endif
- 	board_cache_error_setup = r4k_cache_error_setup;
- 
- 	/*
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -985,6 +985,9 @@ void build_get_pgde32(u32 **p, unsigned
- 		uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
- 		uasm_i_addu(p, ptr, tmp, ptr);
- #else
-+#ifdef CONFIG_BCM47XX
-+		uasm_i_nop(p);
-+#endif
- 		UASM_i_LA_mostly(p, ptr, pgdc);
- #endif
- 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1347,6 +1350,9 @@ static void build_r4000_tlb_refill_handl
- #ifdef CONFIG_64BIT
- 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-+# ifdef CONFIG_BCM47XX
-+		uasm_i_nop(&p);
-+# endif
- 		build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
- #endif
- 
-@@ -1358,6 +1364,9 @@ static void build_r4000_tlb_refill_handl
- 		build_update_entries(&p, K0, K1);
- 		build_tlb_write_entry(&p, &l, &r, tlb_random);
- 		uasm_l_leave(&l, p);
-+#ifdef CONFIG_BCM47XX
-+		uasm_i_nop(&p);
-+#endif
- 		uasm_i_eret(&p); /* return from trap */
- 	}
- #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2059,6 +2068,9 @@ build_r4000_tlbchange_handler_head(u32 *
- #ifdef CONFIG_64BIT
- 	build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
- #else
-+# ifdef CONFIG_BCM47XX
-+	uasm_i_nop(p);
-+# endif
- 	build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
- #endif
- 
-@@ -2105,6 +2117,9 @@ build_r4000_tlbchange_handler_tail(u32 *
- 	build_tlb_write_entry(p, l, r, tlb_indexed);
- 	uasm_l_leave(l, *p);
- 	build_restore_work_registers(p);
-+#ifdef CONFIG_BCM47XX
-+	uasm_i_nop(p);
-+#endif
- 	uasm_i_eret(p); /* return from trap */
- 
- #ifdef CONFIG_64BIT
diff --git a/target/linux/bcm47xx/patches-5.15/160-kmap_coherent.patch b/target/linux/bcm47xx/patches-5.15/160-kmap_coherent.patch
deleted file mode 100644
index c2a0db8ab7..0000000000
--- a/target/linux/bcm47xx/patches-5.15/160-kmap_coherent.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From: Jeff Hansen <jhansen@cardaccess-inc.com>
-Subject: [PATCH] kmap_coherent
-
-On ASUS WL-500gP there are some "Data bus error"s when executing simple
-commands liks "ps" or "cat /proc/1/cmdline".
-
-This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485
----
---- a/arch/mips/include/asm/cpu-features.h
-+++ b/arch/mips/include/asm/cpu-features.h
-@@ -257,6 +257,9 @@
- #ifndef cpu_has_pindexed_dcache
- #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
- #endif
-+#ifndef cpu_use_kmap_coherent
-+#define cpu_use_kmap_coherent 1
-+#endif
- 
- /*
-  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
---- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-@@ -80,4 +80,6 @@
- #define cpu_scache_line_size()		0
- #define cpu_has_vz			0
- 
-+#define cpu_use_kmap_coherent		0
-+
- #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -702,7 +702,7 @@ static inline void local_r4k_flush_cache
- 		map_coherent = (cpu_has_dc_aliases &&
- 				page_mapcount(page) &&
- 				!Page_dcache_dirty(page));
--		if (map_coherent)
-+		if (map_coherent && cpu_use_kmap_coherent)
- 			vaddr = kmap_coherent(page, addr);
- 		else
- 			vaddr = kmap_atomic(page);
-@@ -729,7 +729,7 @@ static inline void local_r4k_flush_cache
- 	}
- 
- 	if (vaddr) {
--		if (map_coherent)
-+		if (map_coherent && cpu_use_kmap_coherent)
- 			kunmap_coherent();
- 		else
- 			kunmap_atomic(vaddr);
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -172,7 +172,7 @@ void copy_user_highpage(struct page *to,
- 	void *vfrom, *vto;
- 
- 	vto = kmap_atomic(to);
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(from) && !Page_dcache_dirty(from)) {
- 		vfrom = kmap_coherent(from, vaddr);
- 		copy_page(vto, vfrom);
-@@ -194,7 +194,7 @@ void copy_to_user_page(struct vm_area_st
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(page) && !Page_dcache_dirty(page)) {
- 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(vto, src, len);
-@@ -212,7 +212,7 @@ void copy_from_user_page(struct vm_area_
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
- {
--	if (cpu_has_dc_aliases &&
-+	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- 	    page_mapcount(page) && !Page_dcache_dirty(page)) {
- 		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- 		memcpy(dst, vfrom, len);
diff --git a/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch
deleted file mode 100644
index 772e905ecb..0000000000
--- a/target/linux/bcm47xx/patches-5.15/209-b44-register-adm-switch.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 9 Nov 2013 17:03:59 +0100
-Subject: [PATCH 210/210] b44: register adm switch
-
----
- drivers/net/ethernet/broadcom/b44.c |   57 +++++++++++++++++++++++++++++++++++
- drivers/net/ethernet/broadcom/b44.h |    3 ++
- 2 files changed, 60 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -31,6 +31,8 @@
- #include <linux/ssb/ssb.h>
- #include <linux/slab.h>
- #include <linux/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/adm6996-gpio.h>
- 
- #include <linux/uaccess.h>
- #include <asm/io.h>
-@@ -2245,6 +2247,69 @@ static void b44_adjust_link(struct net_d
- 	}
- }
- 
-+#ifdef CONFIG_BCM47XX
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+	int gpio;
-+	struct platform_device *pdev;
-+	struct adm6996_gpio_platform_data adm_data = {0};
-+	struct platform_device_info info = {0};
-+
-+	adm_data.model = ADM6996L;
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
-+	if (gpio >= 0)
-+		adm_data.eecs = gpio;
-+	else
-+		adm_data.eecs = 2;
-+
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
-+	if (gpio >= 0)
-+		adm_data.eesk = gpio;
-+	else
-+		adm_data.eesk = 3;
-+
-+	gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
-+	if (gpio >= 0)
-+		adm_data.eedi = gpio;
-+	else
-+		adm_data.eedi = 4;
-+
-+	/*
-+	 * We ignore the "adm_rc" GPIO here. The driver does not use it,
-+	 * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.
-+	 */
-+
-+	info.parent = bp->sdev->dev;
-+	info.name = "adm6996_gpio";
-+	info.id = -1;
-+	info.data = &adm_data;
-+	info.size_data = sizeof(adm_data);
-+
-+	if (!bp->adm_switch) {
-+		pdev = platform_device_register_full(&info);
-+		if (IS_ERR(pdev))
-+			return PTR_ERR(pdev);
-+
-+		bp->adm_switch = pdev;
-+	}
-+	return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+	if (bp->adm_switch)
-+		platform_device_unregister(bp->adm_switch);
-+}
-+#else
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+	return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+
-+}
-+#endif /* CONFIG_BCM47XX */
-+
- static int b44_register_phy_one(struct b44 *bp)
- {
- 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-@@ -2281,6 +2346,9 @@ static int b44_register_phy_one(struct b
- 	if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
- 	    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
- 
-+		if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
-+			b44_register_adm_switch(bp);
-+
- 		dev_info(sdev->dev,
- 			 "could not find PHY at %i, use fixed one\n",
- 			 bp->phy_addr);
-@@ -2475,6 +2543,7 @@ static void b44_remove_one(struct ssb_de
- 	unregister_netdev(dev);
- 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- 		b44_unregister_phy_one(bp);
-+	b44_unregister_adm_switch(bp);
- 	ssb_device_disable(sdev, 0);
- 	ssb_bus_may_powerdown(sdev->bus);
- 	netif_napi_del(&bp->napi);
---- a/drivers/net/ethernet/broadcom/b44.h
-+++ b/drivers/net/ethernet/broadcom/b44.h
-@@ -408,6 +408,9 @@ struct b44 {
- 	struct mii_bus		*mii_bus;
- 	int			old_link;
- 	struct mii_if_info	mii_if;
-+
-+	/* platform device for associated switch */
-+	struct platform_device *adm_switch;
- };
- 
- #endif /* _B44_H */
diff --git a/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch
deleted file mode 100644
index ca7123f2a3..0000000000
--- a/target/linux/bcm47xx/patches-5.15/210-b44_phy_fix.patch
+++ /dev/null
@@ -1,54 +0,0 @@
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -430,10 +430,34 @@ static void b44_wap54g10_workaround(stru
- error:
- 	pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
- }
-+
-+static void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+	char buf[20];
-+	struct ssb_device *sdev = bp->sdev;
-+
-+	/* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
-+	if (sdev->bus->sprom.board_num == 100) {
-+		bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+	} else {
-+		/* WL-HDD */
-+		if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
-+		    !strncmp(buf, "WL300-", strlen("WL300-"))) {
-+			if (sdev->bus->sprom.et0phyaddr == 0 &&
-+			    sdev->bus->sprom.et1phyaddr == 1)
-+				bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+		}
-+	}
-+	return;
-+}
- #else
- static inline void b44_wap54g10_workaround(struct b44 *bp)
- {
- }
-+
-+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+}
- #endif
- 
- static int b44_setup_phy(struct b44 *bp)
-@@ -442,6 +466,7 @@ static int b44_setup_phy(struct b44 *bp)
- 	int err;
- 
- 	b44_wap54g10_workaround(bp);
-+	b44_bcm47xx_workarounds(bp);
- 
- 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- 		return 0;
-@@ -2175,6 +2200,8 @@ static int b44_get_invariants(struct b44
- 	 * valid PHY address. */
- 	bp->phy_addr &= 0x1F;
- 
-+	b44_bcm47xx_workarounds(bp);
-+
- 	memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
- 
- 	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
diff --git a/target/linux/bcm47xx/patches-5.15/310-no_highpage.patch b/target/linux/bcm47xx/patches-5.15/310-no_highpage.patch
deleted file mode 100644
index 8f368e3e9e..0000000000
--- a/target/linux/bcm47xx/patches-5.15/310-no_highpage.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From: Jeff Hansen <jhansen@cardaccess-inc.com>
-Subject: [PATCH] no highpage
-
-On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
-seem to be caused by a kernel. They can be avoided by:
-1) Disabling highpage
-2) Using flush_cache_mm in flush_cache_dup_mm
-
-For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
----
---- a/arch/mips/include/asm/page.h
-+++ b/arch/mips/include/asm/page.h
-@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
- #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
- 
- #include <linux/pfn.h>
-+#include <asm/cpu-features.h>
- 
- extern void build_clear_page(void);
- extern void build_copy_page(void);
-@@ -110,11 +111,16 @@ static inline void clear_user_page(void
- 		flush_data_cache_page((unsigned long)addr);
- }
- 
--struct vm_area_struct;
--extern void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma);
-+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-+	struct page *to)
-+{
-+	extern void (*flush_data_cache_page)(unsigned long addr);
- 
--#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-+	copy_page(vto, vfrom);
-+	if (!cpu_has_ic_fills_f_dc ||
-+	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-+		flush_data_cache_page((unsigned long)vto);
-+}
- 
- /*
-  * These are used to make use of C type-checking..
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -166,30 +166,6 @@ void kunmap_coherent(void)
- 	preempt_enable();
- }
- 
--void copy_user_highpage(struct page *to, struct page *from,
--	unsigned long vaddr, struct vm_area_struct *vma)
--{
--	void *vfrom, *vto;
--
--	vto = kmap_atomic(to);
--	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
--	    page_mapcount(from) && !Page_dcache_dirty(from)) {
--		vfrom = kmap_coherent(from, vaddr);
--		copy_page(vto, vfrom);
--		kunmap_coherent();
--	} else {
--		vfrom = kmap_atomic(from);
--		copy_page(vto, vfrom);
--		kunmap_atomic(vfrom);
--	}
--	if ((!cpu_has_ic_fills_f_dc) ||
--	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
--		flush_data_cache_page((unsigned long)vto);
--	kunmap_atomic(vto);
--	/* Make sure this page is cleared on other CPU's too before using it */
--	smp_wmb();
--}
--
- void copy_to_user_page(struct vm_area_struct *vma,
- 	struct page *page, unsigned long vaddr, void *dst, const void *src,
- 	unsigned long len)
diff --git a/target/linux/bcm47xx/patches-5.15/791-tg3-no-pci-sleep.patch b/target/linux/bcm47xx/patches-5.15/791-tg3-no-pci-sleep.patch
deleted file mode 100644
index fb78dca758..0000000000
--- a/target/linux/bcm47xx/patches-5.15/791-tg3-no-pci-sleep.patch
+++ /dev/null
@@ -1,17 +0,0 @@
-When the Ethernet controller is powered down and someone wants to 
-access the mdio bus like the witch driver (b53) the system crashed if 
-PCI_D3hot was set before. This patch deactivates this power sawing mode 
-when a switch driver is in use.
-
---- a/drivers/net/ethernet/broadcom/tg3.c
-+++ b/drivers/net/ethernet/broadcom/tg3.c
-@@ -4268,7 +4268,8 @@ static int tg3_power_down_prepare(struct
- static void tg3_power_down(struct tg3 *tp)
- {
- 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
--	pci_set_power_state(tp->pdev, PCI_D3hot);
-+	if (!tg3_flag(tp, ROBOSWITCH))
-+		pci_set_power_state(tp->pdev, PCI_D3hot);
- }
- 
- static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
diff --git a/target/linux/bcm47xx/patches-5.15/830-huawei_e970_support.patch b/target/linux/bcm47xx/patches-5.15/830-huawei_e970_support.patch
deleted file mode 100644
index 1746fee592..0000000000
--- a/target/linux/bcm47xx/patches-5.15/830-huawei_e970_support.patch
+++ /dev/null
@@ -1,101 +0,0 @@
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -37,6 +37,7 @@
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
- #include <linux/bcma/bcma_soc.h>
-+#include <linux/old_gpio_wdt.h>
- #include <asm/bootinfo.h>
- #include <asm/idle.h>
- #include <asm/prom.h>
-@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f
- 	.duplex	= DUPLEX_FULL,
- };
- 
-+static struct gpio_wdt_platform_data gpio_wdt_data;
-+
-+static struct platform_device gpio_wdt_device = {
-+	.name			= "gpio-wdt",
-+	.id			= 0,
-+	.dev			= {
-+		.platform_data	= &gpio_wdt_data,
-+	},
-+};
-+
-+static int __init bcm47xx_register_gpio_watchdog(void)
-+{
-+	enum bcm47xx_board board = bcm47xx_board_get();
-+
-+	switch (board) {
-+	case BCM47XX_BOARD_HUAWEI_E970:
-+		pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
-+		gpio_wdt_data.gpio = 7;
-+		gpio_wdt_data.interval = HZ;
-+		gpio_wdt_data.first_interval = HZ / 5;
-+		return platform_device_register(&gpio_wdt_device);
-+	default:
-+		/* Nothing to do */
-+		return 0;
-+	}
-+}
-+
- static int __init bcm47xx_register_bus_complete(void)
- {
- 	switch (bcm47xx_bus_type) {
-@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c
- 	bcm47xx_workarounds();
- 
- 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
-+	bcm47xx_register_gpio_watchdog();
- 	return 0;
- }
- device_initcall(bcm47xx_register_bus_complete);
---- a/arch/mips/configs/bcm47xx_defconfig
-+++ b/arch/mips/configs/bcm47xx_defconfig
-@@ -63,6 +63,7 @@ CONFIG_HW_RANDOM=y
- CONFIG_GPIO_SYSFS=y
- CONFIG_WATCHDOG=y
- CONFIG_BCM47XX_WDT=y
-+CONFIG_GPIO_WDT=y
- CONFIG_SSB_DRIVER_GIGE=y
- CONFIG_BCMA_DRIVER_GMAC_CMN=y
- CONFIG_USB=y
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
- }
- EXPORT_SYMBOL(ssb_watchdog_timer_set);
- 
-+#ifdef CONFIG_BCM47XX
-+#include <bcm47xx_board.h>
-+
-+static bool ssb_watchdog_supported(void)
-+{
-+	enum bcm47xx_board board = bcm47xx_board_get();
-+
-+	/* The Huawei E970 has a hardware watchdog using a GPIO */
-+	switch (board) {
-+	case BCM47XX_BOARD_HUAWEI_E970:
-+		return false;
-+	default:
-+		return true;
-+	}
-+}
-+#else
-+static bool ssb_watchdog_supported(void)
-+{
-+	return true;
-+}
-+#endif
-+
- int ssb_watchdog_register(struct ssb_bus *bus)
- {
- 	struct bcm47xx_wdt wdt = {};
- 	struct platform_device *pdev;
- 
-+	if (!ssb_watchdog_supported())
-+		return 0;
-+
- 	if (ssb_chipco_available(&bus->chipco)) {
- 		wdt.driver_data = &bus->chipco;
- 		wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
diff --git a/target/linux/bcm47xx/patches-5.15/831-old_gpio_wdt.patch b/target/linux/bcm47xx/patches-5.15/831-old_gpio_wdt.patch
deleted file mode 100644
index cb3bd0f263..0000000000
--- a/target/linux/bcm47xx/patches-5.15/831-old_gpio_wdt.patch
+++ /dev/null
@@ -1,360 +0,0 @@
-This generic GPIO watchdog is used on Huawei E970 (bcm47xx)
-
-Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1664,6 +1664,15 @@ config WDT_MTX1
- 	  Hardware driver for the MTX-1 boards. This is a watchdog timer that
- 	  will reboot the machine after a 100 seconds timer expired.
- 
-+config GPIO_WDT
-+	tristate "GPIO Hardware Watchdog"
-+ 	help
-+	  Hardware driver for GPIO-controlled watchdogs. GPIO pin and
-+	  toggle interval settings are platform-specific. The driver
-+	  will stop toggling the GPIO (i.e. machine reboots) after a
-+	  100 second timer expired and no process has written to
-+	  /dev/watchdog during that time.
-+
- config SIBYTE_WDOG
- 	tristate "Sibyte SoC hardware watchdog"
- 	depends on CPU_SB1
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -159,6 +159,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
- obj-$(CONFIG_INDYDOG) += indydog.o
- obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
- obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
-+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
---- /dev/null
-+++ b/drivers/watchdog/old_gpio_wdt.c
-@@ -0,0 +1,301 @@
-+/*
-+ *      Driver for GPIO-controlled Hardware Watchdogs.
-+ *
-+ *      Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
-+ *
-+ *      Replaces mtx1_wdt (driver for the MTX-1 Watchdog):
-+ *
-+ *      (C) Copyright 2005 4G Systems <info@4g-systems.biz>,
-+ *                              All Rights Reserved.
-+ *                              http://www.4g-systems.biz
-+ *
-+ *      (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org>
-+ *
-+ *      This program is free software; you can redistribute it and/or
-+ *      modify it under the terms of the GNU General Public License
-+ *      as published by the Free Software Foundation; either version
-+ *      2 of the License, or (at your option) any later version.
-+ *
-+ *      Neither Michael Stickel nor 4G Systems admit liability nor provide
-+ *      warranty for any of this software. This material is provided
-+ *      "AS-IS" and at no charge.
-+ *
-+ *      (c) Copyright 2005    4G Systems <info@4g-systems.biz>
-+ *
-+ *      Release 0.01.
-+ *      Author: Michael Stickel  michael.stickel@4g-systems.biz
-+ *
-+ *      Release 0.02.
-+ *      Author: Florian Fainelli florian@openwrt.org
-+ *              use the Linux watchdog/timer APIs
-+ *
-+ *      Release 0.03.
-+ *      Author: Mathias Adam <m.adam--linux@adamis.de>
-+ *              make it a generic gpio watchdog driver
-+ *
-+ *      The Watchdog is configured to reset the MTX-1
-+ *      if it is not triggered for 100 seconds.
-+ *      It should not be triggered more often than 1.6 seconds.
-+ *
-+ *      A timer triggers the watchdog every 5 seconds, until
-+ *      it is opened for the first time. After the first open
-+ *      it MUST be triggered every 2..95 seconds.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/timer.h>
-+#include <linux/completion.h>
-+#include <linux/jiffies.h>
-+#include <linux/watchdog.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <linux/gpio.h>
-+#include <linux/old_gpio_wdt.h>
-+
-+static int ticks = 100 * HZ;
-+
-+static struct {
-+	struct completion stop;
-+	spinlock_t lock;
-+	int running;
-+	struct timer_list timer;
-+	int queue;
-+	int default_ticks;
-+	unsigned long inuse;
-+	unsigned gpio;
-+	unsigned int gstate;
-+	int interval;
-+	int first_interval;
-+} gpio_wdt_device;
-+
-+static void gpio_wdt_trigger(struct timer_list *unused)
-+{
-+	spin_lock(&gpio_wdt_device.lock);
-+	if (gpio_wdt_device.running && ticks > 0)
-+		ticks -= gpio_wdt_device.interval;
-+
-+	/* toggle wdt gpio */
-+	gpio_wdt_device.gstate = !gpio_wdt_device.gstate;
-+	gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);
-+
-+	if (gpio_wdt_device.queue && ticks > 0)
-+		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);
-+	else
-+		complete(&gpio_wdt_device.stop);
-+	spin_unlock(&gpio_wdt_device.lock);
-+}
-+
-+static void gpio_wdt_reset(void)
-+{
-+	ticks = gpio_wdt_device.default_ticks;
-+}
-+
-+
-+static void gpio_wdt_start(void)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+	if (!gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 1;
-+		gpio_wdt_device.gstate = 1;
-+		gpio_set_value(gpio_wdt_device.gpio, 1);
-+		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);
-+	}
-+	gpio_wdt_device.running++;
-+	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+}
-+
-+static int gpio_wdt_stop(void)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+	if (gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 0;
-+		gpio_wdt_device.gstate = 0;
-+		gpio_set_value(gpio_wdt_device.gpio, 0);
-+	}
-+	ticks = gpio_wdt_device.default_ticks;
-+	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+	return 0;
-+}
-+
-+/* Filesystem functions */
-+
-+static int gpio_wdt_open(struct inode *inode, struct file *file)
-+{
-+	if (test_and_set_bit(0, &gpio_wdt_device.inuse))
-+		return -EBUSY;
-+	return nonseekable_open(inode, file);
-+}
-+
-+
-+static int gpio_wdt_release(struct inode *inode, struct file *file)
-+{
-+	clear_bit(0, &gpio_wdt_device.inuse);
-+	return 0;
-+}
-+
-+static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,
-+							unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	int __user *p = (int __user *)argp;
-+	unsigned int value;
-+	static const struct watchdog_info ident = {
-+		.options = WDIOF_CARDRESET,
-+		.identity = "GPIO WDT",
-+	};
-+
-+	switch (cmd) {
-+	case WDIOC_GETSUPPORT:
-+		if (copy_to_user(argp, &ident, sizeof(ident)))
-+			return -EFAULT;
-+		break;
-+	case WDIOC_GETSTATUS:
-+	case WDIOC_GETBOOTSTATUS:
-+		put_user(0, p);
-+		break;
-+	case WDIOC_SETOPTIONS:
-+		if (get_user(value, p))
-+			return -EFAULT;
-+		if (value & WDIOS_ENABLECARD)
-+			gpio_wdt_start();
-+		else if (value & WDIOS_DISABLECARD)
-+			gpio_wdt_stop();
-+		else
-+			return -EINVAL;
-+		return 0;
-+	case WDIOC_KEEPALIVE:
-+		gpio_wdt_reset();
-+		break;
-+	default:
-+		return -ENOTTY;
-+	}
-+	return 0;
-+}
-+
-+
-+static ssize_t gpio_wdt_write(struct file *file, const char *buf,
-+						size_t count, loff_t *ppos)
-+{
-+	if (!count)
-+		return -EIO;
-+	gpio_wdt_reset();
-+	return count;
-+}
-+
-+static const struct file_operations gpio_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.llseek		= no_llseek,
-+	.unlocked_ioctl	= gpio_wdt_ioctl,
-+	.open		= gpio_wdt_open,
-+	.write		= gpio_wdt_write,
-+	.release	= gpio_wdt_release,
-+};
-+
-+
-+static struct miscdevice gpio_wdt_misc = {
-+	.minor	= WATCHDOG_MINOR,
-+	.name	= "watchdog",
-+	.fops	= &gpio_wdt_fops,
-+};
-+
-+
-+static int gpio_wdt_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;
-+
-+	gpio_wdt_device.gpio = gpio_wdt_data->gpio;
-+	gpio_wdt_device.interval = gpio_wdt_data->interval;
-+	gpio_wdt_device.first_interval = gpio_wdt_data->first_interval;
-+	if (gpio_wdt_device.first_interval <= 0) {
-+		gpio_wdt_device.first_interval = gpio_wdt_device.interval;
-+	}
-+
-+	ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt");
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to request gpio");
-+		return ret;
-+	}
-+
-+	spin_lock_init(&gpio_wdt_device.lock);
-+	init_completion(&gpio_wdt_device.stop);
-+	gpio_wdt_device.queue = 0;
-+	clear_bit(0, &gpio_wdt_device.inuse);
-+	timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);
-+	gpio_wdt_device.default_ticks = ticks;
-+
-+	gpio_wdt_start();
-+	dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n",
-+		gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);
-+	return 0;
-+}
-+
-+static int gpio_wdt_remove(struct platform_device *pdev)
-+{
-+	/* FIXME: do we need to lock this test ? */
-+	if (gpio_wdt_device.queue) {
-+		gpio_wdt_device.queue = 0;
-+		wait_for_completion(&gpio_wdt_device.stop);
-+	}
-+
-+	gpio_free(gpio_wdt_device.gpio);
-+	misc_deregister(&gpio_wdt_misc);
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_wdt_driver = {
-+	.probe = gpio_wdt_probe,
-+	.remove = gpio_wdt_remove,
-+	.driver.name = "gpio-wdt",
-+	.driver.owner = THIS_MODULE,
-+};
-+
-+static int __init gpio_wdt_init(void)
-+{
-+	return platform_driver_register(&gpio_wdt_driver);
-+}
-+arch_initcall(gpio_wdt_init);
-+
-+/*
-+ * We do wdt initialization in two steps: arch_initcall probes the wdt
-+ * very early to start pinging the watchdog (misc devices are not yet
-+ * available), and later module_init() just registers the misc device.
-+ */
-+static int gpio_wdt_init_late(void)
-+{
-+	int ret;
-+
-+	ret = misc_register(&gpio_wdt_misc);
-+	if (ret < 0) {
-+		pr_err("GPIO_WDT: failed to register misc device\n");
-+		return ret;
-+	}
-+	return 0;
-+}
-+#ifndef MODULE
-+module_init(gpio_wdt_init_late);
-+#endif
-+
-+static void __exit gpio_wdt_exit(void)
-+{
-+	platform_driver_unregister(&gpio_wdt_driver);
-+}
-+module_exit(gpio_wdt_exit);
-+
-+MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam");
-+MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS("platform:gpio-wdt");
---- /dev/null
-+++ b/include/linux/old_gpio_wdt.h
-@@ -0,0 +1,21 @@
-+/*
-+ *  Definitions for the GPIO watchdog driver
-+ *
-+ *  Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License version 2 as
-+ *  published by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef _GPIO_WDT_H_
-+#define _GPIO_WDT_H_
-+
-+struct gpio_wdt_platform_data {
-+	int	gpio;		/* GPIO line number */
-+	int	interval;	/* watchdog reset interval in system ticks */
-+	int	first_interval;	/* first wd reset interval in system ticks */
-+};
-+
-+#endif /* _GPIO_WDT_H_ */
diff --git a/target/linux/bcm47xx/patches-5.15/940-bcm47xx-yenta.patch b/target/linux/bcm47xx/patches-5.15/940-bcm47xx-yenta.patch
deleted file mode 100644
index 1a5b98b8b2..0000000000
--- a/target/linux/bcm47xx/patches-5.15/940-bcm47xx-yenta.patch
+++ /dev/null
@@ -1,48 +0,0 @@
---- a/drivers/pcmcia/yenta_socket.c
-+++ b/drivers/pcmcia/yenta_socket.c
-@@ -923,6 +923,8 @@ static struct cardbus_type cardbus_type[
- 
- static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
- {
-+/* WRT54G3G does not like this */
-+#ifndef CONFIG_BCM47XX
- 	int i;
- 	unsigned long val;
- 	u32 mask;
-@@ -951,6 +953,9 @@ static unsigned int yenta_probe_irq(stru
- 	mask = probe_irq_mask(val) & 0xffff;
- 
- 	return mask;
-+#else
-+	return 0;
-+#endif
- }
- 
- 
-@@ -1031,6 +1036,10 @@ static void yenta_get_socket_capabilitie
- 	else
- 		socket->socket.irq_mask = 0;
- 
-+	/* irq mask probing is broken for the WRT54G3G */
-+	if (socket->socket.irq_mask == 0)
-+		socket->socket.irq_mask = 0x6f8;
-+
- 	dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
- 		 socket->socket.irq_mask, socket->cb_irq);
- }
-@@ -1262,6 +1271,15 @@ static int yenta_probe(struct pci_dev *d
- 	dev_info(&dev->dev, "Socket status: %08x\n",
- 		 cb_readl(socket, CB_SOCKET_STATE));
- 
-+	/* Generate an interrupt on card insert/remove */
-+	config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
-+
-+	/* Set up Multifunction Routing Status Register */
-+	config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
-+
-+	/* Switch interrupts to parallelized */
-+	config_writeb(socket, 0x92, 0x64);
-+
- 	yenta_fixup_parent_bridge(dev->subordinate);
- 
- 	/* Register it with the pcmcia layer.. */
diff --git a/target/linux/bcm47xx/patches-5.15/999-wl_exports.patch b/target/linux/bcm47xx/patches-5.15/999-wl_exports.patch
deleted file mode 100644
index b47913af70..0000000000
--- a/target/linux/bcm47xx/patches-5.15/999-wl_exports.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/drivers/firmware/broadcom/bcm47xx_nvram.c
-+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
-@@ -30,7 +30,8 @@ struct nvram_header {
- 	u32 config_ncdl;	/* ncdl values for memc */
- };
- 
--static char nvram_buf[NVRAM_SPACE];
-+char nvram_buf[NVRAM_SPACE];
-+EXPORT_SYMBOL(nvram_buf);
- static size_t nvram_len;
- static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
- static int cfe_env;
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -63,6 +63,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
- void (*_dma_cache_wback)(unsigned long start, unsigned long size);
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
- 
-+EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_inv);
-+
- #endif /* CONFIG_DMA_NONCOHERENT */
- 
- /*
diff --git a/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch
index af4e218f9e..1b9dcb3adc 100644
--- a/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch
+++ b/target/linux/bcm47xx/patches-6.1/209-b44-register-adm-switch.patch
@@ -19,7 +19,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  
  #include <linux/uaccess.h>
  #include <asm/io.h>
-@@ -2249,6 +2251,69 @@ static void b44_adjust_link(struct net_d
+@@ -2251,6 +2253,69 @@ static void b44_adjust_link(struct net_d
  	}
  }
  
@@ -89,7 +89,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  static int b44_register_phy_one(struct b44 *bp)
  {
  	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-@@ -2285,6 +2350,9 @@ static int b44_register_phy_one(struct b
+@@ -2287,6 +2352,9 @@ static int b44_register_phy_one(struct b
  	if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
  	    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
  
@@ -99,7 +99,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  		dev_info(sdev->dev,
  			 "could not find PHY at %i, use fixed one\n",
  			 bp->phy_addr);
-@@ -2479,6 +2547,7 @@ static void b44_remove_one(struct ssb_de
+@@ -2481,6 +2549,7 @@ static void b44_remove_one(struct ssb_de
  	unregister_netdev(dev);
  	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
  		b44_unregister_phy_one(bp);
diff --git a/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch
index ffe029b9fe..af9736518b 100644
--- a/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch
+++ b/target/linux/bcm47xx/patches-6.1/210-b44_phy_fix.patch
@@ -43,7 +43,7 @@
  
  	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
  		return 0;
-@@ -2179,6 +2204,8 @@ static int b44_get_invariants(struct b44
+@@ -2181,6 +2206,8 @@ static int b44_get_invariants(struct b44
  	 * valid PHY address. */
  	bp->phy_addr &= 0x1F;
  
diff --git a/target/linux/bcm47xx/patches-6.6/159-cpu_fixes.patch b/target/linux/bcm47xx/patches-6.6/159-cpu_fixes.patch
new file mode 100644
index 0000000000..f4360664c5
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/159-cpu_fixes.patch
@@ -0,0 +1,484 @@
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -27,6 +27,38 @@
+ extern void (*r4k_blast_dcache)(void);
+ extern void (*r4k_blast_icache)(void);
+ 
++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
++
++static inline unsigned long bcm4710_dummy_rreg(void)
++{
++      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
++}
++
++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
++
++static inline unsigned long bcm4710_fill_tlb(void *addr)
++{
++      return *(unsigned long *)addr;
++}
++
++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
++
++static inline void bcm4710_protected_fill_tlb(void *addr)
++{
++      unsigned long x;
++      get_dbe(x, (unsigned long *)addr);;
++}
++
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+  * This macro return a properly sign-extended address suitable as base address
+  * for indexed cache operations.  Two issues here:
+@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
+ 
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Index_Writeback_Inv_D, addr);
+ }
+ 
+@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
+ 
+ static inline void flush_dcache_line(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Writeback_Inv_D, addr);
+ }
+ 
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	cache_op(Hit_Invalidate_D, addr);
+ }
+ 
+@@ -160,6 +195,7 @@ static inline int protected_flush_icache
+ 		return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+ 
+ 	default:
++		BCM4710_DUMMY_RREG();
+ 		return protected_cache_op(Hit_Invalidate_I, addr);
+ 	}
+ }
+@@ -172,6 +208,7 @@ static inline int protected_flush_icache
+  */
+ static inline int protected_writeback_dcache_line(unsigned long addr)
+ {
++	BCM4710_DUMMY_RREG();
+ 	return protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+ 
+@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
+ 	unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));	\
+ } while (0)
+ 
++static inline void blast_dcache(void)
++{
++	unsigned long start = KSEG0;
++	unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++	unsigned long end = (start + dcache_size);
++
++	do {
++		BCM4710_DUMMY_RREG();
++		cache_op(Index_Writeback_Inv_D, start);
++		start += current_cpu_data.dcache.linesz;
++	} while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++	unsigned long start = page;
++	unsigned long end = start + PAGE_SIZE;
++
++	BCM4710_FILL_TLB(start);
++	do {
++		BCM4710_DUMMY_RREG();
++		cache_op(Hit_Writeback_Inv_D, start);
++		start += current_cpu_data.dcache.linesz;
++	} while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++	unsigned long start = page;
++	unsigned long end = start + PAGE_SIZE;
++	unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++	unsigned long ws_end = current_cpu_data.dcache.ways <<
++	                       current_cpu_data.dcache.waybit;
++	unsigned long ws, addr;
++	for (ws = 0; ws < ws_end; ws += ws_inc) {
++		start = page + ws;
++		for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++			BCM4710_DUMMY_RREG();
++			cache_op(Index_Writeback_Inv_D, addr);
++		}
++	}
++}
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)	\
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
+ static inline void extra##blast_##pfx##cache##lsize(void)		\
+ {									\
+ 	unsigned long start = INDEX_BASE;				\
+@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
+ 			       current_cpu_data.desc.waybit;		\
+ 	unsigned long ws, addr;						\
+ 									\
++	war								\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+ 		for (addr = start; addr < end; addr += lsize * 32)	\
+ 			cache_unroll(32, kernel_cache, indexop,		\
+@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
+ 	unsigned long start = page;					\
+ 	unsigned long end = page + PAGE_SIZE;				\
+ 									\
++	war								\
+ 	do {								\
+ 		cache_unroll(32, kernel_cache, hitop, start, lsize);	\
+ 		start += lsize * 32;					\
+@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
+ 			       current_cpu_data.desc.waybit;		\
+ 	unsigned long ws, addr;						\
+ 									\
++	war								\
+ 	for (ws = 0; ws < ws_end; ws += ws_inc)				\
+ 		for (addr = start; addr < end; addr += lsize * 32)	\
+ 			cache_unroll(32, kernel_cache, indexop,		\
+ 				     addr | ws, lsize);			\
+ }
+ 
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
+ 
+ #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
+ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
+@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
+ __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+ 
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)	\
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)	\
+ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
+ 						    unsigned long end)	\
+ {									\
+ 	unsigned long lsize = cpu_##desc##_line_size();			\
+-	unsigned long lsize_2 = lsize * 2;				\
+-	unsigned long lsize_3 = lsize * 3;				\
+-	unsigned long lsize_4 = lsize * 4;				\
+-	unsigned long lsize_5 = lsize * 5;				\
+-	unsigned long lsize_6 = lsize * 6;				\
+-	unsigned long lsize_7 = lsize * 7;				\
+-	unsigned long lsize_8 = lsize * 8;				\
+ 	unsigned long addr = start & ~(lsize - 1);			\
+-	unsigned long aend = (end + lsize - 1) & ~(lsize - 1);		\
+-	int lines = (aend - addr) / lsize;				\
+-									\
+-	while (lines >= 8) {						\
+-		prot##cache_op(hitop, addr);				\
+-		prot##cache_op(hitop, addr + lsize);			\
+-		prot##cache_op(hitop, addr + lsize_2);			\
+-		prot##cache_op(hitop, addr + lsize_3);			\
+-		prot##cache_op(hitop, addr + lsize_4);			\
+-		prot##cache_op(hitop, addr + lsize_5);			\
+-		prot##cache_op(hitop, addr + lsize_6);			\
+-		prot##cache_op(hitop, addr + lsize_7);			\
+-		addr += lsize_8;					\
+-		lines -= 8;						\
+-	}								\
++	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+ 									\
+-	if (lines & 0x4) {						\
+-		prot##cache_op(hitop, addr);				\
+-		prot##cache_op(hitop, addr + lsize);			\
+-		prot##cache_op(hitop, addr + lsize_2);			\
+-		prot##cache_op(hitop, addr + lsize_3);			\
+-		addr += lsize_4;					\
+-	}								\
+-									\
+-	if (lines & 0x2) {						\
+-		prot##cache_op(hitop, addr);				\
+-		prot##cache_op(hitop, addr + lsize);			\
+-		addr += lsize_2;					\
+-	}								\
++	war								\
+ 									\
+-	if (lines & 0x1) {						\
++	while (1) {							\
++		war2							\
+ 		prot##cache_op(hitop, addr);				\
++		if (addr == aend)					\
++			break;						\
++		addr += lsize;						\
+ 	}								\
+ }
+ 
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
+ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+-	protected_, loongson2_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
++	protected_, loongson2_, , )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
+ 
+ /* Currently, this is very specific to Loongson-3 */
+ #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)	\
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -429,6 +429,10 @@
+ #else
+ 		.set	push
+ 		.set	arch=r4000
++#ifdef CONFIG_BCM47XX
++		nop
++		nop
++#endif
+ 		eret
+ 		.set	pop
+ #endif
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -21,6 +21,19 @@
+ #include <asm/sync.h>
+ #include <asm/thread_info.h>
+ 
++#ifdef CONFIG_BCM47XX
++# ifdef eret
++#  undef eret
++# endif
++# define eret 					\
++	.set push;				\
++	.set noreorder;				\
++	 nop; 					\
++	 nop;					\
++	 eret;					\
++	.set pop;
++#endif
++
+ 	__INIT
+ 
+ /*
+@@ -32,6 +45,9 @@
+ NESTED(except_vec3_generic, 0, sp)
+ 	.set	push
+ 	.set	noat
++#ifdef CONFIG_BCM47XX
++	nop
++#endif
+ 	mfc0	k1, CP0_CAUSE
+ 	andi	k1, k1, 0x7c
+ #ifdef CONFIG_64BIT
+@@ -52,6 +68,9 @@ NESTED(except_vec3_r4000, 0, sp)
+ 	.set	push
+ 	.set	arch=r4000
+ 	.set	noat
++#ifdef CONFIG_BCM47XX
++	nop
++#endif
+ 	mfc0	k1, CP0_CAUSE
+ 	li	k0, 31<<2
+ 	andi	k1, k1, 0x7c
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -37,6 +37,9 @@
+ #include <asm/traps.h>
+ #include <asm/mips-cps.h>
+ 
++/* For enabling BCM4710 cache workarounds */
++static int bcm4710 = 0;
++
+ /*
+  * Bits describing what cache ops an SMP callback function may perform.
+  *
+@@ -144,6 +147,9 @@ static void r4k_blast_dcache_page_setup(
+ {
+ 	unsigned long  dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache_page = blast_dcache_page;
++	else
+ 	switch (dc_lsize) {
+ 	case 0:
+ 		r4k_blast_dcache_page = (void *)cache_noop;
+@@ -175,6 +181,9 @@ static void r4k_blast_dcache_user_page_s
+ {
+ 	unsigned long  dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache_user_page = blast_dcache_user_page;
++	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache_user_page = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -194,6 +203,9 @@ static void r4k_blast_dcache_setup(void)
+ {
+ 	unsigned long dc_lsize = cpu_dcache_line_size();
+ 
++	if (bcm4710)
++		r4k_blast_dcache = blast_dcache;
++	else
+ 	if (dc_lsize == 0)
+ 		r4k_blast_dcache = (void *)cache_noop;
+ 	else if (dc_lsize == 16)
+@@ -1669,6 +1681,17 @@ static void coherency_setup(void)
+ 	 * silly idea of putting something else there ...
+ 	 */
+ 	switch (current_cpu_type()) {
++	case CPU_BMIPS3300:
++		{
++			u32 cm;
++			cm = read_c0_diag();
++			/* Enable icache */
++			cm |= (1 << 31);
++			/* Enable dcache */
++			cm |= (1 << 30);
++			write_c0_diag(cm);
++		}
++		break;
+ 	case CPU_R4000PC:
+ 	case CPU_R4000SC:
+ 	case CPU_R4000MC:
+@@ -1715,6 +1738,15 @@ void r4k_cache_init(void)
+ 	extern void build_copy_page(void);
+ 	struct cpuinfo_mips *c = &current_cpu_data;
+ 
++	/* Check if special workarounds are required */
++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
++	if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
++		printk("Enabling BCM4710A0 cache workarounds.\n");
++		bcm4710 = 1;
++	} else
++#endif
++		bcm4710 = 0;
++
+ 	probe_pcache();
+ 	probe_vcache();
+ 	setup_scache();
+@@ -1777,7 +1809,15 @@ void r4k_cache_init(void)
+ 	 */
+ 	local_r4k___flush_cache_all(NULL);
+ 
++#ifdef CONFIG_BCM47XX
++	{
++		static void (*_coherency_setup)(void);
++		_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++		_coherency_setup();
++	}
++#else
+ 	coherency_setup();
++#endif
+ 	board_cache_error_setup = r4k_cache_error_setup;
+ 
+ 	/*
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -958,6 +958,9 @@ void build_get_pgde32(u32 **p, unsigned
+ 		uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
+ 		uasm_i_addu(p, ptr, tmp, ptr);
+ #else
++#ifdef CONFIG_BCM47XX
++		uasm_i_nop(p);
++#endif
+ 		UASM_i_LA_mostly(p, ptr, pgdc);
+ #endif
+ 		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+@@ -1304,6 +1307,9 @@ static void build_r4000_tlb_refill_handl
+ #ifdef CONFIG_64BIT
+ 		build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
++# ifdef CONFIG_BCM47XX
++		uasm_i_nop(&p);
++# endif
+ 		build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
+ #endif
+ 
+@@ -1315,6 +1321,9 @@ static void build_r4000_tlb_refill_handl
+ 		build_update_entries(&p, K0, K1);
+ 		build_tlb_write_entry(&p, &l, &r, tlb_random);
+ 		uasm_l_leave(&l, p);
++#ifdef CONFIG_BCM47XX
++		uasm_i_nop(&p);
++#endif
+ 		uasm_i_eret(&p); /* return from trap */
+ 	}
+ #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+@@ -2016,6 +2025,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ #ifdef CONFIG_64BIT
+ 	build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
++# ifdef CONFIG_BCM47XX
++	uasm_i_nop(p);
++# endif
+ 	build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
+ #endif
+ 
+@@ -2062,6 +2074,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+ 	build_tlb_write_entry(p, l, r, tlb_indexed);
+ 	uasm_l_leave(l, *p);
+ 	build_restore_work_registers(p);
++#ifdef CONFIG_BCM47XX
++	uasm_i_nop(p);
++#endif
+ 	uasm_i_eret(p); /* return from trap */
+ 
+ #ifdef CONFIG_64BIT
diff --git a/target/linux/bcm47xx/patches-6.6/160-kmap_coherent.patch b/target/linux/bcm47xx/patches-6.6/160-kmap_coherent.patch
new file mode 100644
index 0000000000..19ab8df7c4
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/160-kmap_coherent.patch
@@ -0,0 +1,69 @@
+From: Jeff Hansen <jhansen@cardaccess-inc.com>
+Subject: [PATCH] kmap_coherent
+
+On ASUS WL-500gP there are some "Data bus error"s when executing simple
+commands liks "ps" or "cat /proc/1/cmdline".
+
+This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485
+---
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -257,6 +257,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+ 
+ /*
+  * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
+--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
+@@ -79,4 +79,6 @@
+ #define cpu_scache_line_size()		0
+ #define cpu_has_vz			0
+ 
++#define cpu_use_kmap_coherent		0
++
+ #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -618,7 +618,7 @@ static inline void local_r4k_flush_cache
+ 	}
+ 
+ 	if (vaddr) {
+-		if (map_coherent)
++		if (map_coherent && cpu_use_kmap_coherent)
+ 			kunmap_coherent();
+ 		else
+ 			kunmap_atomic(vaddr);
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -173,7 +173,7 @@ void copy_user_highpage(struct page *to,
+ 	void *vfrom, *vto;
+ 
+ 	vto = kmap_atomic(to);
+-	if (cpu_has_dc_aliases &&
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    folio_mapped(src) && !folio_test_dcache_dirty(src)) {
+ 		vfrom = kmap_coherent(from, vaddr);
+ 		copy_page(vto, vfrom);
+@@ -197,7 +197,7 @@ void copy_to_user_page(struct vm_area_st
+ {
+ 	struct folio *folio = page_folio(page);
+ 
+-	if (cpu_has_dc_aliases &&
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
+ 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(vto, src, len);
+@@ -217,7 +217,7 @@ void copy_from_user_page(struct vm_area_
+ {
+ 	struct folio *folio = page_folio(page);
+ 
+-	if (cpu_has_dc_aliases &&
++	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ 	    folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
+ 		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ 		memcpy(dst, vfrom, len);
diff --git a/target/linux/bcm47xx/patches-6.6/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-6.6/209-b44-register-adm-switch.patch
new file mode 100644
index 0000000000..bb7637cb01
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/209-b44-register-adm-switch.patch
@@ -0,0 +1,121 @@
+From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sat, 9 Nov 2013 17:03:59 +0100
+Subject: [PATCH 210/210] b44: register adm switch
+
+---
+ drivers/net/ethernet/broadcom/b44.c |   57 +++++++++++++++++++++++++++++++++++
+ drivers/net/ethernet/broadcom/b44.h |    3 ++
+ 2 files changed, 60 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -31,6 +31,8 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/slab.h>
+ #include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/platform_data/adm6996-gpio.h>
+ 
+ #include <linux/uaccess.h>
+ #include <asm/io.h>
+@@ -2227,6 +2229,69 @@ static void b44_adjust_link(struct net_d
+ 	}
+ }
+ 
++#ifdef CONFIG_BCM47XX
++static int b44_register_adm_switch(struct b44 *bp)
++{
++	int gpio;
++	struct platform_device *pdev;
++	struct adm6996_gpio_platform_data adm_data = {0};
++	struct platform_device_info info = {0};
++
++	adm_data.model = ADM6996L;
++	gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
++	if (gpio >= 0)
++		adm_data.eecs = gpio;
++	else
++		adm_data.eecs = 2;
++
++	gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
++	if (gpio >= 0)
++		adm_data.eesk = gpio;
++	else
++		adm_data.eesk = 3;
++
++	gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
++	if (gpio >= 0)
++		adm_data.eedi = gpio;
++	else
++		adm_data.eedi = 4;
++
++	/*
++	 * We ignore the "adm_rc" GPIO here. The driver does not use it,
++	 * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.
++	 */
++
++	info.parent = bp->sdev->dev;
++	info.name = "adm6996_gpio";
++	info.id = -1;
++	info.data = &adm_data;
++	info.size_data = sizeof(adm_data);
++
++	if (!bp->adm_switch) {
++		pdev = platform_device_register_full(&info);
++		if (IS_ERR(pdev))
++			return PTR_ERR(pdev);
++
++		bp->adm_switch = pdev;
++	}
++	return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++	if (bp->adm_switch)
++		platform_device_unregister(bp->adm_switch);
++}
++#else
++static int b44_register_adm_switch(struct b44 *bp)
++{
++	return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++
++}
++#endif /* CONFIG_BCM47XX */
++
+ static int b44_register_phy_one(struct b44 *bp)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+@@ -2263,6 +2328,9 @@ static int b44_register_phy_one(struct b
+ 	if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
+ 	    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
+ 
++		if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
++			b44_register_adm_switch(bp);
++
+ 		dev_info(sdev->dev,
+ 			 "could not find PHY at %i, use fixed one\n",
+ 			 bp->phy_addr);
+@@ -2457,6 +2525,7 @@ static void b44_remove_one(struct ssb_de
+ 	unregister_netdev(dev);
+ 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ 		b44_unregister_phy_one(bp);
++	b44_unregister_adm_switch(bp);
+ 	ssb_device_disable(sdev, 0);
+ 	ssb_bus_may_powerdown(sdev->bus);
+ 	netif_napi_del(&bp->napi);
+--- a/drivers/net/ethernet/broadcom/b44.h
++++ b/drivers/net/ethernet/broadcom/b44.h
+@@ -408,6 +408,9 @@ struct b44 {
+ 	struct mii_bus		*mii_bus;
+ 	int			old_link;
+ 	struct mii_if_info	mii_if;
++
++	/* platform device for associated switch */
++	struct platform_device *adm_switch;
+ };
+ 
+ #endif /* _B44_H */
diff --git a/target/linux/bcm47xx/patches-6.6/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-6.6/210-b44_phy_fix.patch
new file mode 100644
index 0000000000..e26f91d12a
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/210-b44_phy_fix.patch
@@ -0,0 +1,54 @@
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -408,10 +408,34 @@ static void b44_wap54g10_workaround(stru
+ error:
+ 	pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
+ }
++
++static void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++	char buf[20];
++	struct ssb_device *sdev = bp->sdev;
++
++	/* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
++	if (sdev->bus->sprom.board_num == 100) {
++		bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++	} else {
++		/* WL-HDD */
++		if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
++		    !strncmp(buf, "WL300-", strlen("WL300-"))) {
++			if (sdev->bus->sprom.et0phyaddr == 0 &&
++			    sdev->bus->sprom.et1phyaddr == 1)
++				bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++		}
++	}
++	return;
++}
+ #else
+ static inline void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ }
++
++static inline void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++}
+ #endif
+ 
+ static int b44_setup_phy(struct b44 *bp)
+@@ -420,6 +444,7 @@ static int b44_setup_phy(struct b44 *bp)
+ 	int err;
+ 
+ 	b44_wap54g10_workaround(bp);
++	b44_bcm47xx_workarounds(bp);
+ 
+ 	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ 		return 0;
+@@ -2157,6 +2182,8 @@ static int b44_get_invariants(struct b44
+ 	 * valid PHY address. */
+ 	bp->phy_addr &= 0x1F;
+ 
++	b44_bcm47xx_workarounds(bp);
++
+ 	eth_hw_addr_set(bp->dev, addr);
+ 
+ 	if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
diff --git a/target/linux/bcm47xx/patches-5.15/280-activate_ssb_support_in_usb.patch b/target/linux/bcm47xx/patches-6.6/280-activate_ssb_support_in_usb.patch
index f6e9e6d30a..f6e9e6d30a 100644
--- a/target/linux/bcm47xx/patches-5.15/280-activate_ssb_support_in_usb.patch
+++ b/target/linux/bcm47xx/patches-6.6/280-activate_ssb_support_in_usb.patch
diff --git a/target/linux/bcm47xx/patches-5.15/300-fork_cacheflush.patch b/target/linux/bcm47xx/patches-6.6/300-fork_cacheflush.patch
index daa2c1adf0..daa2c1adf0 100644
--- a/target/linux/bcm47xx/patches-5.15/300-fork_cacheflush.patch
+++ b/target/linux/bcm47xx/patches-6.6/300-fork_cacheflush.patch
diff --git a/target/linux/bcm47xx/patches-6.6/310-no_highpage.patch b/target/linux/bcm47xx/patches-6.6/310-no_highpage.patch
new file mode 100644
index 0000000000..7a4cd6ed90
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/310-no_highpage.patch
@@ -0,0 +1,75 @@
+From: Jeff Hansen <jhansen@cardaccess-inc.com>
+Subject: [PATCH] no highpage
+
+On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
+seem to be caused by a kernel. They can be avoided by:
+1) Disabling highpage
+2) Using flush_cache_mm in flush_cache_dup_mm
+
+For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
+---
+--- a/arch/mips/include/asm/page.h
++++ b/arch/mips/include/asm/page.h
+@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
+ #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+ 
+ #include <linux/pfn.h>
++#include <asm/cpu-features.h>
+ 
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+@@ -110,11 +111,16 @@ static inline void clear_user_page(void
+ 		flush_data_cache_page((unsigned long)addr);
+ }
+ 
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+-	unsigned long vaddr, struct vm_area_struct *vma);
++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
++	struct page *to)
++{
++	extern void (*flush_data_cache_page)(unsigned long addr);
+ 
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
++	copy_page(vto, vfrom);
++	if (!cpu_has_ic_fills_f_dc ||
++	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
++		flush_data_cache_page((unsigned long)vto);
++}
+ 
+ /*
+  * These are used to make use of C type-checking..
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -166,31 +166,6 @@ void kunmap_coherent(void)
+ 	preempt_enable();
+ }
+ 
+-void copy_user_highpage(struct page *to, struct page *from,
+-	unsigned long vaddr, struct vm_area_struct *vma)
+-{
+-	struct folio *src = page_folio(from);
+-	void *vfrom, *vto;
+-
+-	vto = kmap_atomic(to);
+-	if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+-	    folio_mapped(src) && !folio_test_dcache_dirty(src)) {
+-		vfrom = kmap_coherent(from, vaddr);
+-		copy_page(vto, vfrom);
+-		kunmap_coherent();
+-	} else {
+-		vfrom = kmap_atomic(from);
+-		copy_page(vto, vfrom);
+-		kunmap_atomic(vfrom);
+-	}
+-	if ((!cpu_has_ic_fills_f_dc) ||
+-	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+-		flush_data_cache_page((unsigned long)vto);
+-	kunmap_atomic(vto);
+-	/* Make sure this page is cleared on other CPU's too before using it */
+-	smp_wmb();
+-}
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ 	struct page *page, unsigned long vaddr, void *dst, const void *src,
+ 	unsigned long len)
diff --git a/target/linux/bcm47xx/patches-5.15/400-mtd-bcm47xxpart-get-nvram.patch b/target/linux/bcm47xx/patches-6.6/400-mtd-bcm47xxpart-get-nvram.patch
index 17abe89d1d..17abe89d1d 100644
--- a/target/linux/bcm47xx/patches-5.15/400-mtd-bcm47xxpart-get-nvram.patch
+++ b/target/linux/bcm47xx/patches-6.6/400-mtd-bcm47xxpart-get-nvram.patch
diff --git a/target/linux/bcm47xx/patches-5.15/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-6.6/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch
index 2fcfbb7438..2fcfbb7438 100644
--- a/target/linux/bcm47xx/patches-5.15/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch
+++ b/target/linux/bcm47xx/patches-6.6/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch
diff --git a/target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch b/target/linux/bcm47xx/patches-6.6/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch
index 3a2f4b06ed..3a2f4b06ed 100644
--- a/target/linux/bcm47xx/patches-5.15/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch
+++ b/target/linux/bcm47xx/patches-6.6/701-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch
diff --git a/target/linux/bcm47xx/patches-6.6/791-tg3-no-pci-sleep.patch b/target/linux/bcm47xx/patches-6.6/791-tg3-no-pci-sleep.patch
new file mode 100644
index 0000000000..76e979ad58
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/791-tg3-no-pci-sleep.patch
@@ -0,0 +1,17 @@
+When the Ethernet controller is powered down and someone wants to 
+access the mdio bus like the witch driver (b53) the system crashed if 
+PCI_D3hot was set before. This patch deactivates this power sawing mode 
+when a switch driver is in use.
+
+--- a/drivers/net/ethernet/broadcom/tg3.c
++++ b/drivers/net/ethernet/broadcom/tg3.c
+@@ -4269,7 +4269,8 @@ static int tg3_power_down_prepare(struct
+ static void tg3_power_down(struct tg3 *tp)
+ {
+ 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
+-	pci_set_power_state(tp->pdev, PCI_D3hot);
++	if (!tg3_flag(tp, ROBOSWITCH))
++		pci_set_power_state(tp->pdev, PCI_D3hot);
+ }
+ 
+ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
diff --git a/target/linux/bcm47xx/patches-5.15/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch b/target/linux/bcm47xx/patches-6.6/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch
index 318dc55810..318dc55810 100644
--- a/target/linux/bcm47xx/patches-5.15/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch
+++ b/target/linux/bcm47xx/patches-6.6/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch
diff --git a/target/linux/bcm47xx/patches-5.15/820-wgt634u-nvram-fix.patch b/target/linux/bcm47xx/patches-6.6/820-wgt634u-nvram-fix.patch
index 82997ca65a..82997ca65a 100644
--- a/target/linux/bcm47xx/patches-5.15/820-wgt634u-nvram-fix.patch
+++ b/target/linux/bcm47xx/patches-6.6/820-wgt634u-nvram-fix.patch
diff --git a/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch b/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch
new file mode 100644
index 0000000000..21ab40206f
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/830-huawei_e970_support.patch
@@ -0,0 +1,101 @@
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -37,6 +37,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <linux/old_gpio_wdt.h>
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+ #include <asm/prom.h>
+@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f
+ 	.duplex	= DUPLEX_FULL,
+ };
+ 
++static struct gpio_wdt_platform_data gpio_wdt_data;
++
++static struct platform_device gpio_wdt_device = {
++	.name			= "gpio-wdt",
++	.id			= 0,
++	.dev			= {
++		.platform_data	= &gpio_wdt_data,
++	},
++};
++
++static int __init bcm47xx_register_gpio_watchdog(void)
++{
++	enum bcm47xx_board board = bcm47xx_board_get();
++
++	switch (board) {
++	case BCM47XX_BOARD_HUAWEI_E970:
++		pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
++		gpio_wdt_data.gpio = 7;
++		gpio_wdt_data.interval = HZ;
++		gpio_wdt_data.first_interval = HZ / 5;
++		return platform_device_register(&gpio_wdt_device);
++	default:
++		/* Nothing to do */
++		return 0;
++	}
++}
++
+ static int __init bcm47xx_register_bus_complete(void)
+ {
+ 	switch (bcm47xx_bus_type) {
+@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c
+ 	bcm47xx_workarounds();
+ 
+ 	fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
++	bcm47xx_register_gpio_watchdog();
+ 	return 0;
+ }
+ device_initcall(bcm47xx_register_bus_complete);
+--- a/arch/mips/configs/bcm47xx_defconfig
++++ b/arch/mips/configs/bcm47xx_defconfig
+@@ -62,6 +62,7 @@ CONFIG_HW_RANDOM=y
+ CONFIG_GPIO_SYSFS=y
+ CONFIG_WATCHDOG=y
+ CONFIG_BCM47XX_WDT=y
++CONFIG_GPIO_WDT=y
+ CONFIG_SSB_DRIVER_GIGE=y
+ CONFIG_BCMA_DRIVER_GMAC_CMN=y
+ CONFIG_USB=y
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+ 
++#ifdef CONFIG_BCM47XX
++#include <bcm47xx_board.h>
++
++static bool ssb_watchdog_supported(void)
++{
++	enum bcm47xx_board board = bcm47xx_board_get();
++
++	/* The Huawei E970 has a hardware watchdog using a GPIO */
++	switch (board) {
++	case BCM47XX_BOARD_HUAWEI_E970:
++		return false;
++	default:
++		return true;
++	}
++}
++#else
++static bool ssb_watchdog_supported(void)
++{
++	return true;
++}
++#endif
++
+ int ssb_watchdog_register(struct ssb_bus *bus)
+ {
+ 	struct bcm47xx_wdt wdt = {};
+ 	struct platform_device *pdev;
+ 
++	if (!ssb_watchdog_supported())
++		return 0;
++
+ 	if (ssb_chipco_available(&bus->chipco)) {
+ 		wdt.driver_data = &bus->chipco;
+ 		wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
diff --git a/target/linux/bcm47xx/patches-6.6/831-old_gpio_wdt.patch b/target/linux/bcm47xx/patches-6.6/831-old_gpio_wdt.patch
new file mode 100644
index 0000000000..6c76cbeee7
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/831-old_gpio_wdt.patch
@@ -0,0 +1,360 @@
+This generic GPIO watchdog is used on Huawei E970 (bcm47xx)
+
+Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1755,6 +1755,15 @@ config WDT_MTX1
+ 	  Hardware driver for the MTX-1 boards. This is a watchdog timer that
+ 	  will reboot the machine after a 100 seconds timer expired.
+ 
++config GPIO_WDT
++	tristate "GPIO Hardware Watchdog"
++ 	help
++	  Hardware driver for GPIO-controlled watchdogs. GPIO pin and
++	  toggle interval settings are platform-specific. The driver
++	  will stop toggling the GPIO (i.e. machine reboots) after a
++	  100 second timer expired and no process has written to
++	  /dev/watchdog during that time.
++
+ config SIBYTE_WDOG
+ 	tristate "Sibyte SoC hardware watchdog"
+ 	depends on CPU_SB1
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -167,6 +167,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
+ obj-$(CONFIG_INDYDOG) += indydog.o
+ obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
+ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+--- /dev/null
++++ b/drivers/watchdog/old_gpio_wdt.c
+@@ -0,0 +1,301 @@
++/*
++ *      Driver for GPIO-controlled Hardware Watchdogs.
++ *
++ *      Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
++ *
++ *      Replaces mtx1_wdt (driver for the MTX-1 Watchdog):
++ *
++ *      (C) Copyright 2005 4G Systems <info@4g-systems.biz>,
++ *                              All Rights Reserved.
++ *                              http://www.4g-systems.biz
++ *
++ *      (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org>
++ *
++ *      This program is free software; you can redistribute it and/or
++ *      modify it under the terms of the GNU General Public License
++ *      as published by the Free Software Foundation; either version
++ *      2 of the License, or (at your option) any later version.
++ *
++ *      Neither Michael Stickel nor 4G Systems admit liability nor provide
++ *      warranty for any of this software. This material is provided
++ *      "AS-IS" and at no charge.
++ *
++ *      (c) Copyright 2005    4G Systems <info@4g-systems.biz>
++ *
++ *      Release 0.01.
++ *      Author: Michael Stickel  michael.stickel@4g-systems.biz
++ *
++ *      Release 0.02.
++ *      Author: Florian Fainelli florian@openwrt.org
++ *              use the Linux watchdog/timer APIs
++ *
++ *      Release 0.03.
++ *      Author: Mathias Adam <m.adam--linux@adamis.de>
++ *              make it a generic gpio watchdog driver
++ *
++ *      The Watchdog is configured to reset the MTX-1
++ *      if it is not triggered for 100 seconds.
++ *      It should not be triggered more often than 1.6 seconds.
++ *
++ *      A timer triggers the watchdog every 5 seconds, until
++ *      it is opened for the first time. After the first open
++ *      it MUST be triggered every 2..95 seconds.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/miscdevice.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/timer.h>
++#include <linux/completion.h>
++#include <linux/jiffies.h>
++#include <linux/watchdog.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++#include <linux/gpio.h>
++#include <linux/old_gpio_wdt.h>
++
++static int ticks = 100 * HZ;
++
++static struct {
++	struct completion stop;
++	spinlock_t lock;
++	int running;
++	struct timer_list timer;
++	int queue;
++	int default_ticks;
++	unsigned long inuse;
++	unsigned gpio;
++	unsigned int gstate;
++	int interval;
++	int first_interval;
++} gpio_wdt_device;
++
++static void gpio_wdt_trigger(struct timer_list *unused)
++{
++	spin_lock(&gpio_wdt_device.lock);
++	if (gpio_wdt_device.running && ticks > 0)
++		ticks -= gpio_wdt_device.interval;
++
++	/* toggle wdt gpio */
++	gpio_wdt_device.gstate = !gpio_wdt_device.gstate;
++	gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);
++
++	if (gpio_wdt_device.queue && ticks > 0)
++		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);
++	else
++		complete(&gpio_wdt_device.stop);
++	spin_unlock(&gpio_wdt_device.lock);
++}
++
++static void gpio_wdt_reset(void)
++{
++	ticks = gpio_wdt_device.default_ticks;
++}
++
++
++static void gpio_wdt_start(void)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
++	if (!gpio_wdt_device.queue) {
++		gpio_wdt_device.queue = 1;
++		gpio_wdt_device.gstate = 1;
++		gpio_set_value(gpio_wdt_device.gpio, 1);
++		mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);
++	}
++	gpio_wdt_device.running++;
++	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
++}
++
++static int gpio_wdt_stop(void)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&gpio_wdt_device.lock, flags);
++	if (gpio_wdt_device.queue) {
++		gpio_wdt_device.queue = 0;
++		gpio_wdt_device.gstate = 0;
++		gpio_set_value(gpio_wdt_device.gpio, 0);
++	}
++	ticks = gpio_wdt_device.default_ticks;
++	spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
++	return 0;
++}
++
++/* Filesystem functions */
++
++static int gpio_wdt_open(struct inode *inode, struct file *file)
++{
++	if (test_and_set_bit(0, &gpio_wdt_device.inuse))
++		return -EBUSY;
++	return nonseekable_open(inode, file);
++}
++
++
++static int gpio_wdt_release(struct inode *inode, struct file *file)
++{
++	clear_bit(0, &gpio_wdt_device.inuse);
++	return 0;
++}
++
++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,
++							unsigned long arg)
++{
++	void __user *argp = (void __user *)arg;
++	int __user *p = (int __user *)argp;
++	unsigned int value;
++	static const struct watchdog_info ident = {
++		.options = WDIOF_CARDRESET,
++		.identity = "GPIO WDT",
++	};
++
++	switch (cmd) {
++	case WDIOC_GETSUPPORT:
++		if (copy_to_user(argp, &ident, sizeof(ident)))
++			return -EFAULT;
++		break;
++	case WDIOC_GETSTATUS:
++	case WDIOC_GETBOOTSTATUS:
++		put_user(0, p);
++		break;
++	case WDIOC_SETOPTIONS:
++		if (get_user(value, p))
++			return -EFAULT;
++		if (value & WDIOS_ENABLECARD)
++			gpio_wdt_start();
++		else if (value & WDIOS_DISABLECARD)
++			gpio_wdt_stop();
++		else
++			return -EINVAL;
++		return 0;
++	case WDIOC_KEEPALIVE:
++		gpio_wdt_reset();
++		break;
++	default:
++		return -ENOTTY;
++	}
++	return 0;
++}
++
++
++static ssize_t gpio_wdt_write(struct file *file, const char *buf,
++						size_t count, loff_t *ppos)
++{
++	if (!count)
++		return -EIO;
++	gpio_wdt_reset();
++	return count;
++}
++
++static const struct file_operations gpio_wdt_fops = {
++	.owner		= THIS_MODULE,
++	.llseek		= no_llseek,
++	.unlocked_ioctl	= gpio_wdt_ioctl,
++	.open		= gpio_wdt_open,
++	.write		= gpio_wdt_write,
++	.release	= gpio_wdt_release,
++};
++
++
++static struct miscdevice gpio_wdt_misc = {
++	.minor	= WATCHDOG_MINOR,
++	.name	= "watchdog",
++	.fops	= &gpio_wdt_fops,
++};
++
++
++static int gpio_wdt_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;
++
++	gpio_wdt_device.gpio = gpio_wdt_data->gpio;
++	gpio_wdt_device.interval = gpio_wdt_data->interval;
++	gpio_wdt_device.first_interval = gpio_wdt_data->first_interval;
++	if (gpio_wdt_device.first_interval <= 0) {
++		gpio_wdt_device.first_interval = gpio_wdt_device.interval;
++	}
++
++	ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt");
++	if (ret < 0) {
++		dev_err(&pdev->dev, "failed to request gpio");
++		return ret;
++	}
++
++	spin_lock_init(&gpio_wdt_device.lock);
++	init_completion(&gpio_wdt_device.stop);
++	gpio_wdt_device.queue = 0;
++	clear_bit(0, &gpio_wdt_device.inuse);
++	timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);
++	gpio_wdt_device.default_ticks = ticks;
++
++	gpio_wdt_start();
++	dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n",
++		gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);
++	return 0;
++}
++
++static int gpio_wdt_remove(struct platform_device *pdev)
++{
++	/* FIXME: do we need to lock this test ? */
++	if (gpio_wdt_device.queue) {
++		gpio_wdt_device.queue = 0;
++		wait_for_completion(&gpio_wdt_device.stop);
++	}
++
++	gpio_free(gpio_wdt_device.gpio);
++	misc_deregister(&gpio_wdt_misc);
++	return 0;
++}
++
++static struct platform_driver gpio_wdt_driver = {
++	.probe = gpio_wdt_probe,
++	.remove = gpio_wdt_remove,
++	.driver.name = "gpio-wdt",
++	.driver.owner = THIS_MODULE,
++};
++
++static int __init gpio_wdt_init(void)
++{
++	return platform_driver_register(&gpio_wdt_driver);
++}
++arch_initcall(gpio_wdt_init);
++
++/*
++ * We do wdt initialization in two steps: arch_initcall probes the wdt
++ * very early to start pinging the watchdog (misc devices are not yet
++ * available), and later module_init() just registers the misc device.
++ */
++static int gpio_wdt_init_late(void)
++{
++	int ret;
++
++	ret = misc_register(&gpio_wdt_misc);
++	if (ret < 0) {
++		pr_err("GPIO_WDT: failed to register misc device\n");
++		return ret;
++	}
++	return 0;
++}
++#ifndef MODULE
++module_init(gpio_wdt_init_late);
++#endif
++
++static void __exit gpio_wdt_exit(void)
++{
++	platform_driver_unregister(&gpio_wdt_driver);
++}
++module_exit(gpio_wdt_exit);
++
++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam");
++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
++MODULE_ALIAS("platform:gpio-wdt");
+--- /dev/null
++++ b/include/linux/old_gpio_wdt.h
+@@ -0,0 +1,21 @@
++/*
++ *  Definitions for the GPIO watchdog driver
++ *
++ *  Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License version 2 as
++ *  published by the Free Software Foundation.
++ *
++ */
++
++#ifndef _GPIO_WDT_H_
++#define _GPIO_WDT_H_
++
++struct gpio_wdt_platform_data {
++	int	gpio;		/* GPIO line number */
++	int	interval;	/* watchdog reset interval in system ticks */
++	int	first_interval;	/* first wd reset interval in system ticks */
++};
++
++#endif /* _GPIO_WDT_H_ */
diff --git a/target/linux/bcm47xx/patches-5.15/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch b/target/linux/bcm47xx/patches-6.6/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch
index 970e36eb68..970e36eb68 100644
--- a/target/linux/bcm47xx/patches-5.15/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch
+++ b/target/linux/bcm47xx/patches-6.6/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch
diff --git a/target/linux/bcm47xx/patches-6.6/940-bcm47xx-yenta.patch b/target/linux/bcm47xx/patches-6.6/940-bcm47xx-yenta.patch
new file mode 100644
index 0000000000..f1b46c2ce4
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/940-bcm47xx-yenta.patch
@@ -0,0 +1,48 @@
+--- a/drivers/pcmcia/yenta_socket.c
++++ b/drivers/pcmcia/yenta_socket.c
+@@ -925,6 +925,8 @@ static struct cardbus_type cardbus_type[
+ 
+ static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
+ {
++/* WRT54G3G does not like this */
++#ifndef CONFIG_BCM47XX
+ 	int i;
+ 	unsigned long val;
+ 	u32 mask;
+@@ -953,6 +955,9 @@ static unsigned int yenta_probe_irq(stru
+ 	mask = probe_irq_mask(val) & 0xffff;
+ 
+ 	return mask;
++#else
++	return 0;
++#endif
+ }
+ 
+ 
+@@ -1033,6 +1038,10 @@ static void yenta_get_socket_capabilitie
+ 	else
+ 		socket->socket.irq_mask = 0;
+ 
++	/* irq mask probing is broken for the WRT54G3G */
++	if (socket->socket.irq_mask == 0)
++		socket->socket.irq_mask = 0x6f8;
++
+ 	dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
+ 		 socket->socket.irq_mask, socket->cb_irq);
+ }
+@@ -1264,6 +1273,15 @@ static int yenta_probe(struct pci_dev *d
+ 	dev_info(&dev->dev, "Socket status: %08x\n",
+ 		 cb_readl(socket, CB_SOCKET_STATE));
+ 
++	/* Generate an interrupt on card insert/remove */
++	config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
++
++	/* Set up Multifunction Routing Status Register */
++	config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
++
++	/* Switch interrupts to parallelized */
++	config_writeb(socket, 0x92, 0x64);
++
+ 	yenta_fixup_parent_bridge(dev->subordinate);
+ 
+ 	/* Register it with the pcmcia layer.. */
diff --git a/target/linux/bcm47xx/patches-5.15/976-ssb_increase_pci_delay.patch b/target/linux/bcm47xx/patches-6.6/976-ssb_increase_pci_delay.patch
index 201be1b187..201be1b187 100644
--- a/target/linux/bcm47xx/patches-5.15/976-ssb_increase_pci_delay.patch
+++ b/target/linux/bcm47xx/patches-6.6/976-ssb_increase_pci_delay.patch
diff --git a/target/linux/bcm47xx/patches-6.6/999-wl_exports.patch b/target/linux/bcm47xx/patches-6.6/999-wl_exports.patch
new file mode 100644
index 0000000000..72be498776
--- /dev/null
+++ b/target/linux/bcm47xx/patches-6.6/999-wl_exports.patch
@@ -0,0 +1,24 @@
+--- a/drivers/firmware/broadcom/bcm47xx_nvram.c
++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
+@@ -30,7 +30,8 @@ struct nvram_header {
+ 	u32 config_ncdl;	/* ncdl values for memc */
+ };
+ 
+-static char nvram_buf[NVRAM_SPACE];
++char nvram_buf[NVRAM_SPACE];
++EXPORT_SYMBOL(nvram_buf);
+ static size_t nvram_len;
+ static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
+ static int cfe_env;
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -80,6 +80,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+ /*
diff --git a/target/linux/bcm4908/Makefile b/target/linux/bcm4908/Makefile
index d515912829..b4d238eff6 100644
--- a/target/linux/bcm4908/Makefile
+++ b/target/linux/bcm4908/Makefile
@@ -10,6 +10,7 @@ CPU_TYPE:=cortex-a53
 SUBTARGETS:=generic
 
 KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for Broadcom BCM4908 SoC family routers.
diff --git a/target/linux/bcm4908/config-5.15 b/target/linux/bcm4908/config-5.15
deleted file mode 100644
index b1594ea8d8..0000000000
--- a/target/linux/bcm4908/config-5.15
+++ /dev/null
@@ -1,242 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_BCM4908=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_B53=y
-CONFIG_BCM4908_ENET=y
-CONFIG_BCM7038_WDT=y
-CONFIG_BCM7XXX_PHY=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BCM_PMB=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_PM=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_BRCMSTB=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_BCM63138=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BCM_UNIMAC=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_BRCM_U_BOOT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_OF_PARTS_BCM4908=y
-# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPLIT_CFE_BOOTFS=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_BCM_SF2=y
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_BRCM_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM4908=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELOCATABLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_BCM63XX=y
-CONFIG_SERIAL_BCM63XX_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/bcm4908/patches-5.15/030-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch b/target/linux/bcm4908/patches-5.15/030-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch
deleted file mode 100644
index cb0525507f..0000000000
--- a/target/linux/bcm4908/patches-5.15/030-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 19 Aug 2021 14:11:08 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches nand-controller.yaml requirements.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -295,7 +295,7 @@
- 			status = "okay";
- 		};
- 
--		nand@1800 {
-+		nand-controller@1800 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
diff --git a/target/linux/bcm4908/patches-5.15/031-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch b/target/linux/bcm4908/patches-5.15/031-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch
deleted file mode 100644
index 4d5ffcb9e3..0000000000
--- a/target/linux/bcm4908/patches-5.15/031-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 5 Nov 2021 11:14:12 +0100
-Subject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-One more BCM4908 based device.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-@@ -29,6 +29,7 @@ properties:
-         items:
-           - enum:
-               - asus,gt-ac5300
-+              - netgear,raxe500
-           - const: brcm,bcm4908
- 
-       - description: BCM49408 based boards
diff --git a/target/linux/bcm4908/patches-5.15/032-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch b/target/linux/bcm4908/patches-5.15/032-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch
deleted file mode 100644
index 69ab0e9e63..0000000000
--- a/target/linux/bcm4908/patches-5.15/032-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch
+++ /dev/null
@@ -1,160 +0,0 @@
-From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 30 Dec 2021 12:05:35 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Describe pinmux block with its maps.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi    | 135 ++++++++++++++++++
- 1 file changed, 135 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -286,6 +286,141 @@
- 			gpio-controller;
- 		};
- 
-+		pinctrl@560 {
-+			compatible = "brcm,bcm4908-pinctrl";
-+			reg = <0x560 0x10>;
-+
-+			pins_led_0_a: led_0-a-pins {
-+				function = "led_0";
-+				groups = "led_0_grp_a";
-+			};
-+
-+			pins_led_1_a: led_1-a-pins {
-+				function = "led_1";
-+				groups = "led_1_grp_a";
-+			};
-+
-+			pins_led_2_a: led_2-a-pins {
-+				function = "led_2";
-+				groups = "led_2_grp_a";
-+			};
-+
-+			pins_led_3_a: led_3-a-pins {
-+				function = "led_3";
-+				groups = "led_3_grp_a";
-+			};
-+
-+			pins_led_4_a: led_4-a-pins {
-+				function = "led_4";
-+				groups = "led_4_grp_a";
-+			};
-+
-+			pins_led_5_a: led_5-a-pins {
-+				function = "led_5";
-+				groups = "led_5_grp_a";
-+			};
-+
-+			pins_led_6_a: led_6-a-pins {
-+				function = "led_6";
-+				groups = "led_6_grp_a";
-+			};
-+
-+			pins_led_7_a: led_7-a-pins {
-+				function = "led_7";
-+				groups = "led_7_grp_a";
-+			};
-+
-+			pins_led_8_a: led_8-a-pins {
-+				function = "led_8";
-+				groups = "led_8_grp_a";
-+			};
-+
-+			pins_led_9_a: led_9-a-pins {
-+				function = "led_9";
-+				groups = "led_9_grp_a";
-+			};
-+
-+			pins_led_21_a: led_21-a-pins {
-+				function = "led_21";
-+				groups = "led_21_grp_a";
-+			};
-+
-+			pins_led_22_a: led_22-a-pins {
-+				function = "led_22";
-+				groups = "led_22_grp_a";
-+			};
-+
-+			pins_led_26_a: led_26-a-pins {
-+				function = "led_26";
-+				groups = "led_26_grp_a";
-+			};
-+
-+			pins_led_27_a: led_27-a-pins {
-+				function = "led_27";
-+				groups = "led_27_grp_a";
-+			};
-+
-+			pins_led_28_a: led_28-a-pins {
-+				function = "led_28";
-+				groups = "led_28_grp_a";
-+			};
-+
-+			pins_led_29_a: led_29-a-pins {
-+				function = "led_29";
-+				groups = "led_29_grp_a";
-+			};
-+
-+			pins_led_30_a: led_30-a-pins {
-+				function = "led_30";
-+				groups = "led_30_grp_a";
-+			};
-+
-+			pins_hs_uart: hs_uart-pins {
-+				function = "hs_uart";
-+				groups = "hs_uart_grp";
-+			};
-+
-+			pins_i2c_a: i2c-a-pins {
-+				function = "i2c";
-+				groups = "i2c_grp_a";
-+			};
-+
-+			pins_i2c_b: i2c-b-pins {
-+				function = "i2c";
-+				groups = "i2c_grp_b";
-+			};
-+
-+			pins_i2s: i2s-pins {
-+				function = "i2s";
-+				groups = "i2s_grp";
-+			};
-+
-+			pins_nand_ctrl: nand_ctrl-pins {
-+				function = "nand_ctrl";
-+				groups = "nand_ctrl_grp";
-+			};
-+
-+			pins_nand_data: nand_data-pins {
-+				function = "nand_data";
-+				groups = "nand_data_grp";
-+			};
-+
-+			pins_emmc_ctrl: emmc_ctrl-pins {
-+				function = "emmc_ctrl";
-+				groups = "emmc_ctrl_grp";
-+			};
-+
-+			pins_usb0_pwr: usb0_pwr-pins {
-+				function = "usb0_pwr";
-+				groups = "usb0_pwr_grp";
-+			};
-+
-+			pins_usb1_pwr: usb1_pwr-pins {
-+				function = "usb1_pwr";
-+				groups = "usb1_pwr_grp";
-+			};
-+		};
-+
- 		uart0: serial@640 {
- 			compatible = "brcm,bcm6345-uart";
- 			reg = <0x640 0x18>;
diff --git a/target/linux/bcm4908/patches-5.15/032-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch b/target/linux/bcm4908/patches-5.15/032-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch
deleted file mode 100644
index 6b2a3890c2..0000000000
--- a/target/linux/bcm4908/patches-5.15/032-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:14:17 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt"
-binding which matches the first SoC with that block.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -275,6 +275,15 @@
- 		twd: timer-mfd@400 {
- 			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
- 			reg = <0x400 0x4c>;
-+			ranges = <0x0 0x400 0x4c>;
-+
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			watchdog@28 {
-+				compatible = "brcm,bcm6345-wdt";
-+				reg = <0x28 0x8>;
-+			};
- 		};
- 
- 		gpio0: gpio-controller@500 {
diff --git a/target/linux/bcm4908/patches-5.15/032-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch b/target/linux/bcm4908/patches-5.15/032-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch
deleted file mode 100644
index e59eb3f728..0000000000
--- a/target/linux/bcm4908/patches-5.15/032-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 15 Feb 2022 07:36:39 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -455,6 +455,15 @@
- 			};
- 		};
- 
-+		i2c@2100 {
-+			compatible = "brcm,brcmper-i2c";
-+			reg = <0x2100 0x58>;
-+			clock-frequency = <97500>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pins_i2c_a>;
-+			status = "disabled";
-+		};
-+
- 		misc@2600 {
- 			compatible = "brcm,misc", "simple-mfd";
- 			reg = <0x2600 0xe4>;
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patchgit b/target/linux/bcm4908/patches-5.15/033-v6.0-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patchgit
deleted file mode 100644
index 7cd13e5c22..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patchgit
+++ /dev/null
@@ -1,174 +0,0 @@
-From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:00:59 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
-
-Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
-SoC description DTS header and bcm963146.dts is a simple DTS file for
-Broadcom BCM963146 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi    | 110 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts    |  30 +++++
- 3 files changed, 142 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- 				bcm4912-asus-gt-ax6000.dtb \
- 				bcm94912.dtb \
- 				bcm963158.dtb \
--				bcm96858.dtb
-+				bcm96858.dtb \
-+				bcm963146.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -0,0 +1,110 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+	compatible = "brcm,bcm63146", "brcm,bcmbca";
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	interrupt-parent = <&gic>;
-+
-+	cpus {
-+		#address-cells = <2>;
-+		#size-cells = <0>;
-+
-+		B53_0: cpu@0 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x0>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		B53_1: cpu@1 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x1>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		L2_0: l2-cache0 {
-+			compatible = "cache";
-+		};
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+	};
-+
-+	pmu: pmu {
-+		compatible = "arm,cortex-a53-pmu";
-+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-affinity = <&B53_0>, <&B53_1>;
-+	};
-+
-+	clocks: clocks {
-+		periph_clk: periph-clk {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
-+		uart_clk: uart-clk {
-+			compatible = "fixed-factor-clock";
-+			#clock-cells = <0>;
-+			clocks = <&periph_clk>;
-+			clock-div = <4>;
-+			clock-mult = <1>;
-+		};
-+	};
-+
-+	psci {
-+		compatible = "arm,psci-0.2";
-+		method = "smc";
-+	};
-+
-+	axi@81000000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+		gic: interrupt-controller@1000 {
-+			compatible = "arm,gic-400";
-+			#interrupt-cells = <3>;
-+			interrupt-controller;
-+			reg = <0x1000 0x1000>,
-+				<0x2000 0x2000>,
-+				<0x4000 0x2000>,
-+				<0x6000 0x2000>;
-+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+					IRQ_TYPE_LEVEL_HIGH)>;
-+		};
-+	};
-+
-+	bus@ff800000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+		uart0: serial@12000 {
-+			compatible = "arm,pl011", "arm,primecell";
-+			reg = <0x12000 0x1000>;
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&uart_clk>, <&uart_clk>;
-+			clock-names = "uartclk", "apb_pclk";
-+			status = "disabled";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm63146.dtsi"
-+
-+/ {
-+	model = "Broadcom BCM963146 Reference Board";
-+	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
-+
-+	aliases {
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x08000000>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patchgit b/target/linux/bcm4908/patches-5.15/033-v6.0-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patchgit
deleted file mode 100644
index 2e0da2e54a..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patchgit
+++ /dev/null
@@ -1,167 +0,0 @@
-From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:04:36 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
-
-Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
-SoC description DTS header and bcm96856.dts is a simple DTS file for
-Broadcom BCM96956 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi     | 103 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts     |  30 +++++
- 3 files changed, 135 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- 				bcm94912.dtb \
- 				bcm963158.dtb \
- 				bcm96858.dtb \
--				bcm963146.dtb
-+				bcm963146.dtb \
-+				bcm96856.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -0,0 +1,103 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+	compatible = "brcm,bcm6856", "brcm,bcmbca";
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	interrupt-parent = <&gic>;
-+
-+	cpus {
-+		#address-cells = <2>;
-+		#size-cells = <0>;
-+
-+		B53_0: cpu@0 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x0>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		B53_1: cpu@1 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x1>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		L2_0: l2-cache0 {
-+			compatible = "cache";
-+		};
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+	};
-+
-+	pmu: pmu {
-+		compatible = "arm,cortex-a53-pmu";
-+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-affinity = <&B53_0>, <&B53_1>;
-+	};
-+
-+	clocks: clocks {
-+		periph_clk:periph-clk {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
-+	};
-+
-+	psci {
-+		compatible = "arm,psci-0.2";
-+		method = "smc";
-+	};
-+
-+	axi@81000000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+		gic: interrupt-controller@1000 {
-+			compatible = "arm,gic-400";
-+			#interrupt-cells = <3>;
-+			interrupt-controller;
-+			reg = <0x1000 0x1000>, /* GICD */
-+				<0x2000 0x2000>, /* GICC */
-+				<0x4000 0x2000>, /* GICH */
-+				<0x6000 0x2000>; /* GICV */
-+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+					IRQ_TYPE_LEVEL_HIGH)>;
-+		};
-+	};
-+
-+	bus@ff800000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+		uart0: serial@640 {
-+			compatible = "brcm,bcm6345-uart";
-+			reg = <0x640 0x18>;
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&periph_clk>;
-+			clock-names = "refclk";
-+			status = "disabled";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6856.dtsi"
-+
-+/ {
-+	model = "Broadcom BCM96856 Reference Board";
-+	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
-+
-+	aliases {
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x08000000>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patchgit b/target/linux/bcm4908/patches-5.15/033-v6.0-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patchgit
deleted file mode 100644
index 6be8ab8ee4..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patchgit
+++ /dev/null
@@ -1,192 +0,0 @@
-From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Thu, 9 Jun 2022 17:15:33 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813
-
-Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the
-SoC description DTS header and bcm96813.dts is a simple DTS file for
-Broadcom BCM96813 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi     | 128 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts     |  30 ++++
- 3 files changed, 160 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -9,4 +9,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- 				bcm963158.dtb \
- 				bcm96858.dtb \
- 				bcm963146.dtb \
--				bcm96856.dtb
-+				bcm96856.dtb \
-+				bcm96813.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -0,0 +1,128 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+	compatible = "brcm,bcm6813", "brcm,bcmbca";
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	interrupt-parent = <&gic>;
-+
-+	cpus {
-+		#address-cells = <2>;
-+		#size-cells = <0>;
-+
-+		B53_0: cpu@0 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x0>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		B53_1: cpu@1 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x1>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		B53_2: cpu@2 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x2>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		B53_3: cpu@3 {
-+			compatible = "brcm,brahma-b53";
-+			device_type = "cpu";
-+			reg = <0x0 0x3>;
-+			next-level-cache = <&L2_0>;
-+			enable-method = "psci";
-+		};
-+
-+		L2_0: l2-cache0 {
-+			compatible = "cache";
-+		};
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+	};
-+
-+	pmu: pmu {
-+		compatible = "arm,cortex-a53-pmu";
-+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-affinity = <&B53_0>, <&B53_1>,
-+			<&B53_2>, <&B53_3>;
-+	};
-+
-+	clocks: clocks {
-+		periph_clk: periph-clk {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
-+		uart_clk: uart-clk {
-+			compatible = "fixed-factor-clock";
-+			#clock-cells = <0>;
-+			clocks = <&periph_clk>;
-+			clock-div = <4>;
-+			clock-mult = <1>;
-+		};
-+	};
-+
-+	psci {
-+		compatible = "arm,psci-0.2";
-+		method = "smc";
-+	};
-+
-+	axi@81000000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+		gic: interrupt-controller@1000 {
-+			compatible = "arm,gic-400";
-+			#interrupt-cells = <3>;
-+			interrupt-controller;
-+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-+			reg = <0x1000 0x1000>,
-+				<0x2000 0x2000>,
-+				<0x4000 0x2000>,
-+				<0x6000 0x2000>;
-+		};
-+	};
-+
-+	bus@ff800000 {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+		uart0: serial@12000 {
-+			compatible = "arm,pl011", "arm,primecell";
-+			reg = <0x12000 0x1000>;
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&uart_clk>, <&uart_clk>;
-+			clock-names = "uartclk", "apb_pclk";
-+			status = "disabled";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6813.dtsi"
-+
-+/ {
-+	model = "Broadcom BCM96813 Reference Board";
-+	compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
-+
-+	aliases {
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x08000000>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patchgit b/target/linux/bcm4908/patches-5.15/033-v6.0-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patchgit
deleted file mode 100644
index 987da135d7..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patchgit
+++ /dev/null
@@ -1,79 +0,0 @@
-From ea559c81b61603d4044df6f826f10a832c42c98c Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 15 Jun 2022 17:52:59 -0700
-Subject: [PATCH] arm64: dts: broadcom: align gpio-key node names with dtschema
-
-The node names should be generic and DT schema expects certain pattern
-(e.g. with key/button/switch).
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220616005333.18491-6-krzysztof.kozlowski@linaro.org
----
- .../broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts   | 8 ++++----
- .../boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts  | 8 ++++----
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -83,25 +83,25 @@
- 		compatible = "gpio-keys-polled";
- 		poll-interval = <100>;
- 
--		brightness {
-+		key-brightness {
- 			label = "LEDs";
- 			linux,code = <KEY_BRIGHTNESS_ZERO>;
- 			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- 		};
- 
--		wps {
-+		key-wps {
- 			label = "WPS";
- 			linux,code = <KEY_WPS_BUTTON>;
- 			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- 		};
- 
--		wifi {
-+		key-wifi {
- 			label = "WiFi";
- 			linux,code = <KEY_RFKILL>;
- 			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- 		};
- 
--		restart {
-+		key-restart {
- 			label = "Reset";
- 			linux,code = <KEY_RESTART>;
- 			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -18,25 +18,25 @@
- 		compatible = "gpio-keys-polled";
- 		poll-interval = <100>;
- 
--		wifi {
-+		key-wifi {
- 			label = "WiFi";
- 			linux,code = <KEY_RFKILL>;
- 			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- 		};
- 
--		wps {
-+		key-wps {
- 			label = "WPS";
- 			linux,code = <KEY_WPS_BUTTON>;
- 			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- 		};
- 
--		restart {
-+		key-restart {
- 			label = "Reset";
- 			linux,code = <KEY_RESTART>;
- 			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- 		};
- 
--		brightness {
-+		key-brightness {
- 			label = "LEDs";
- 			linux,code = <KEY_BRIGHTNESS_ZERO>;
- 			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patchgit b/target/linux/bcm4908/patches-5.15/033-v6.0-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patchgit
deleted file mode 100644
index 95540d3aab..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patchgit
+++ /dev/null
@@ -1,33 +0,0 @@
-From b4a544e415e9be33b37d9bfa9d9f9f4d13f553d6 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Fri, 8 Jul 2022 11:25:06 -0700
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix timer node for BCM4906 SoC
-
-The cpu mask value in interrupt property inherits from bcm4908.dtsi
-which sets to four cpus. Correct the value to two cpus for dual core
-BCM4906 SoC.
-
-Fixes: c8b404fb05dc ("arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files")
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-@@ -17,6 +17,14 @@
- 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- 	};
- 
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+	};
-+
- 	pmu {
- 		compatible = "arm,cortex-a53-pmu";
- 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/target/linux/bcm4908/patches-5.15/033-v6.0-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch b/target/linux/bcm4908/patches-5.15/033-v6.0-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch
deleted file mode 100644
index 603e30cb8a..0000000000
--- a/target/linux/bcm4908/patches-5.15/033-v6.0-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 1 Jun 2022 15:56:50 -0700
-Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry
-
-Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/Kconfig.platforms | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -65,6 +65,15 @@ config ARCH_BCM_IPROC
- 	help
- 	  This enables support for Broadcom iProc based SoCs
- 
-+config ARCH_BCMBCA
-+	bool "Broadcom Broadband SoC"
-+	help
-+	  Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
-+	  BCA chipset.
-+
-+	  This enables support for Broadcom BCA ARM-based broadband chipsets,
-+	  including the DSL, PON and Wireless family of chips.
-+
- config ARCH_BERLIN
- 	bool "Marvell Berlin SoC Family"
- 	select DW_APB_ICTL
diff --git a/target/linux/bcm4908/patches-5.15/034-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch b/target/linux/bcm4908/patches-5.15/034-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch
deleted file mode 100644
index 54e515cc5e..0000000000
--- a/target/linux/bcm4908/patches-5.15/034-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:58 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Include all 32 pins.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi    | 75 +++++++++++++++++++
- 1 file changed, 75 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -349,6 +349,61 @@
- 				groups = "led_9_grp_a";
- 			};
- 
-+			pins_led_10_a: led_10-a-pins {
-+				function = "led_10";
-+				groups = "led_10_grp_a";
-+			};
-+
-+			pins_led_11_a: led_11-a-pins {
-+				function = "led_11";
-+				groups = "led_11_grp_a";
-+			};
-+
-+			pins_led_12_a: led_12-a-pins {
-+				function = "led_12";
-+				groups = "led_12_grp_a";
-+			};
-+
-+			pins_led_13_a: led_13-a-pins {
-+				function = "led_13";
-+				groups = "led_13_grp_a";
-+			};
-+
-+			pins_led_14_a: led_14-a-pins {
-+				function = "led_14";
-+				groups = "led_14_grp_a";
-+			};
-+
-+			pins_led_15_a: led_15-a-pins {
-+				function = "led_15";
-+				groups = "led_15_grp_a";
-+			};
-+
-+			pins_led_16_a: led_16-a-pins {
-+				function = "led_16";
-+				groups = "led_16_grp_a";
-+			};
-+
-+			pins_led_17_a: led_17-a-pins {
-+				function = "led_17";
-+				groups = "led_17_grp_a";
-+			};
-+
-+			pins_led_18_a: led_18-a-pins {
-+				function = "led_18";
-+				groups = "led_18_grp_a";
-+			};
-+
-+			pins_led_19_a: led_19-a-pins {
-+				function = "led_19";
-+				groups = "led_19_grp_a";
-+			};
-+
-+			pins_led_20_a: led_20-a-pins {
-+				function = "led_20";
-+				groups = "led_20_grp_a";
-+			};
-+
- 			pins_led_21_a: led_21-a-pins {
- 				function = "led_21";
- 				groups = "led_21_grp_a";
-@@ -359,6 +414,21 @@
- 				groups = "led_22_grp_a";
- 			};
- 
-+			pins_led_23_a: led_23-a-pins {
-+				function = "led_23";
-+				groups = "led_23_grp_a";
-+			};
-+
-+			pins_led_24_a: led_24-a-pins {
-+				function = "led_24";
-+				groups = "led_24_grp_a";
-+			};
-+
-+			pins_led_25_a: led_25-a-pins {
-+				function = "led_25";
-+				groups = "led_25_grp_a";
-+			};
-+
- 			pins_led_26_a: led_26-a-pins {
- 				function = "led_26";
- 				groups = "led_26_grp_a";
-@@ -384,6 +454,11 @@
- 				groups = "led_30_grp_a";
- 			};
- 
-+			pins_led_31_a: led_31-a-pins {
-+				function = "led_31";
-+				groups = "led_31_grp_a";
-+			};
-+
- 			pins_hs_uart: hs_uart-pins {
- 				function = "hs_uart";
- 				groups = "hs_uart_grp";
diff --git a/target/linux/bcm4908/patches-5.15/034-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch b/target/linux/bcm4908/patches-5.15/034-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch
deleted file mode 100644
index 90be8bec0a..0000000000
--- a/target/linux/bcm4908/patches-5.15/034-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:59 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 includes LEDs controller that supports multiple brightness
-levels & hardware blinking.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -514,6 +514,14 @@
- 			status = "okay";
- 		};
- 
-+		leds: leds@800 {
-+			compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
-+			reg = <0x800 0xdc>;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		nand-controller@1800 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
diff --git a/target/linux/bcm4908/patches-5.15/034-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch b/target/linux/bcm4908/patches-5.15/034-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch
deleted file mode 100644
index f4c7d8c489..0000000000
--- a/target/linux/bcm4908/patches-5.15/034-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:21:00 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are 5 software-controllable LEDs on PCB.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../bcmbca/bcm4908-asus-gt-ac5300.dts        | 48 +++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -2,6 +2,7 @@
- 
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
- 
- #include "bcm4908.dtsi"
- 
-@@ -118,6 +119,53 @@
- 	};
- };
- 
-+&leds {
-+	led-power@11 {
-+		reg = <0x11>;
-+		function = LED_FUNCTION_POWER;
-+		color = <LED_COLOR_ID_WHITE>;
-+		default-state = "on";
-+		active-low;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pins_led_17_a>;
-+	};
-+
-+	led-wan-red@12 {
-+		reg = <0x12>;
-+		function = LED_FUNCTION_WAN;
-+		color = <LED_COLOR_ID_RED>;
-+		active-low;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pins_led_18_a>;
-+	};
-+
-+	led-wps@14 {
-+		reg = <0x14>;
-+		function = LED_FUNCTION_WPS;
-+		color = <LED_COLOR_ID_WHITE>;
-+		active-low;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pins_led_20_a>;
-+	};
-+
-+	led-wan-white@15 {
-+		reg = <0x15>;
-+		function = LED_FUNCTION_WAN;
-+		color = <LED_COLOR_ID_WHITE>;
-+		active-low;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pins_led_21_a>;
-+	};
-+
-+	led-lan@19 {
-+		reg = <0x19>;
-+		function = LED_FUNCTION_LAN;
-+		color = <LED_COLOR_ID_WHITE>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pins_led_25_a>;
-+	};
-+};
-+
- &nandcs {
- 	nand-ecc-strength = <4>;
- 	nand-ecc-step-size = <512>;
diff --git a/target/linux/bcm4908/patches-5.15/034-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch b/target/linux/bcm4908/patches-5.15/034-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch
deleted file mode 100644
index 8f9d3604cb..0000000000
--- a/target/linux/bcm4908/patches-5.15/034-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 4fdcbde682291fba2c3f45a41decd656d92a314f Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:49 -0700
-Subject: [PATCH] arm64: dts: bcmbca: update BCM4908 board dts files
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Append "brcm,bcmbca" to compatible strings based on the new bcmbca
-binding rule for BCM4908 family based boards.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Acked-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220803175455.47638-4-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 2 +-
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts     | 2 +-
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 2 +-
- .../arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts | 2 +-
- 4 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
- 
- / {
--	compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908";
-+	compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- 	model = "Netgear R8000P";
- 
- 	memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
- 
- / {
--	compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908";
-+	compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- 	model = "TP-Link Archer C2300 V1";
- 
- 	memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -7,7 +7,7 @@
- #include "bcm4908.dtsi"
- 
- / {
--	compatible = "asus,gt-ac5300", "brcm,bcm4908";
-+	compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
- 	model = "Asus GT-AC5300";
- 
- 	memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-@@ -3,7 +3,7 @@
- #include "bcm4908.dtsi"
- 
- / {
--	compatible = "netgear,raxe500", "brcm,bcm4908";
-+	compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";
- 	model = "Netgear RAXE500";
- 
- 	memory@0 {
diff --git a/target/linux/bcm4908/patches-5.15/034-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch b/target/linux/bcm4908/patches-5.15/034-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch
deleted file mode 100644
index b19c5d33b4..0000000000
--- a/target/linux/bcm4908/patches-5.15/034-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 72e0bdb6d7edb1785d58f2e8e7c80e1d2f93a319 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:51 -0700
-Subject: [PATCH] arm64: dts: Add BCM4908 generic board dts
-
-Add generic bare bone bcm94908.dts file to support any 4908 based
-design. It supports cpu subsystem, memory and an uart console. This can
-be useful for board bring-up and cpu subsystem and memory related kernel
-test as well.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20220803175455.47638-6-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |  1 +
- .../boot/dts/broadcom/bcmbca/bcm94908.dts     | 30 +++++++++++++++++++
- 2 files changed, 31 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- 				bcm4906-tplink-archer-c2300-v1.dtb \
- 				bcm4908-asus-gt-ac5300.dtb \
- 				bcm4908-netgear-raxe500.dtb \
-+				bcm94908.dtb \
- 				bcm4912-asus-gt-ax6000.dtb \
- 				bcm94912.dtb \
- 				bcm963158.dtb \
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm4908.dtsi"
-+
-+/ {
-+	model = "Broadcom BCM94908 Reference Board";
-+	compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
-+
-+	aliases {
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x08000000>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
diff --git a/target/linux/bcm4908/patches-5.15/035-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch b/target/linux/bcm4908/patches-5.15/035-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch
deleted file mode 100644
index e175f27891..0000000000
--- a/target/linux/bcm4908/patches-5.15/035-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 11:53:16 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 TWD contains block with 4 timers. Add binding for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -280,6 +280,11 @@
- 			#address-cells = <1>;
- 			#size-cells = <1>;
- 
-+			timer@0 {
-+				compatible = "brcm,bcm63138-timer";
-+				reg = <0x0 0x28>;
-+			};
-+
- 			watchdog@28 {
- 				compatible = "brcm,bcm6345-wdt";
- 				reg = <0x28 0x8>;
diff --git a/target/linux/bcm4908/patches-5.15/035-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch b/target/linux/bcm4908/patches-5.15/035-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch
deleted file mode 100644
index e8e81ae544..0000000000
--- a/target/linux/bcm4908/patches-5.15/035-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 12:00:15 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM6858 contains TWD block with timers, watchdog, and reset subblocks.
-Describe it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi     | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -109,6 +109,25 @@
- 		#size-cells = <1>;
- 		ranges = <0x0 0x0 0xff800000 0x62000>;
- 
-+		twd: timer-mfd@400 {
-+			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
-+			reg = <0x400 0x4c>;
-+			ranges = <0x0 0x400 0x4c>;
-+
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			timer@0 {
-+				compatible = "brcm,bcm63138-timer";
-+				reg = <0x0 0x28>;
-+			};
-+
-+			watchdog@28 {
-+				compatible = "brcm,bcm6345-wdt";
-+				reg = <0x28 0x8>;
-+			};
-+		};
-+
- 		uart0: serial@640 {
- 			compatible = "brcm,bcm6345-uart";
- 			reg = <0x640 0x18>;
diff --git a/target/linux/bcm4908/patches-5.15/035-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch b/target/linux/bcm4908/patches-5.15/035-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch
deleted file mode 100644
index a19ab8cf8f..0000000000
--- a/target/linux/bcm4908/patches-5.15/035-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From e567e58d6819adc002c57b81e16b88da24d3b4aa Mon Sep 17 00:00:00 2001
-From: Pierre Gondois <pierre.gondois@arm.com>
-Date: Tue, 22 Nov 2022 17:32:07 +0100
-Subject: [PATCH] arm64: dts: Update cache properties for broadcom
-
-The DeviceTree Specification v0.3 specifies that the cache node
-'compatible' and 'cache-level' properties are 'required'. Cf.
-s3.8 Multi-level and Shared Cache Nodes
-The 'cache-unified' property should be present if one of the
-properties for unified cache is present ('cache-size', ...).
-
-Update the Device Trees accordingly.
-
-Acked-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
-Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi   | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi   | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi    | 1 +
- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
- 9 files changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -63,6 +63,7 @@
- 
- 		l2: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -51,6 +51,7 @@
- 
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -35,6 +35,7 @@
- 
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -51,6 +51,7 @@
- 
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -51,6 +51,7 @@
- 
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -35,6 +35,7 @@
- 
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -50,6 +50,7 @@
- 		};
- 		L2_0: l2-cache0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-@@ -79,6 +79,7 @@
- 
- 		CLUSTER0_L2: l2-cache@0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
---- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-@@ -108,18 +108,22 @@
- 
- 		CLUSTER0_L2: l2-cache@0 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 
- 		CLUSTER1_L2: l2-cache@100 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 
- 		CLUSTER2_L2: l2-cache@200 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 
- 		CLUSTER3_L2: l2-cache@300 {
- 			compatible = "cache";
-+			cache-level = <2>;
- 		};
- 	};
- 
diff --git a/target/linux/bcm4908/patches-5.15/036-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch b/target/linux/bcm4908/patches-5.15/036-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch
deleted file mode 100644
index 7476aed05b..0000000000
--- a/target/linux/bcm4908/patches-5.15/036-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch
+++ /dev/null
@@ -1,367 +0,0 @@
-From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Mon, 6 Feb 2023 22:58:15 -0800
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
-
-Add support for HSSPI controller in ARMv8 chip dts files.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi     | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm4912.dtsi     | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi    | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63158.dtsi    | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi     | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi     | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi     | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm94908.dts     |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm94912.dts     |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts    |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963158.dts    |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts     |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts     |  4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96858.dts     |  4 ++++
- 14 files changed, 160 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -107,6 +107,12 @@
- 			clock-frequency = <50000000>;
- 			clock-output-names = "periph";
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <400000000>;
-+		};
- 	};
- 
- 	soc {
-@@ -528,6 +534,18 @@
- 			#size-cells = <0>;
- 		};
- 
-+		hsspi: spi@1000{
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+			reg = <0x1000 0x600>;
-+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
-+
- 		nand-controller@1800 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -79,6 +79,7 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
- 		uart_clk: uart-clk {
- 			compatible = "fixed-factor-clock";
- 			#clock-cells = <0>;
-@@ -86,6 +87,12 @@
- 			clock-div = <4>;
- 			clock-mult = <1>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -117,6 +124,19 @@
- 		#size-cells = <1>;
- 		ranges = <0x0 0x0 0xff800000 0x800000>;
- 
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+			reg = <0x1000 0x600>, <0x2610 0x4>;
-+			reg-names = "hsspi", "spim-ctrl";
-+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@12000 {
- 			compatible = "arm,pl011", "arm,primecell";
- 			reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -60,6 +60,7 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
- 		uart_clk: uart-clk {
- 			compatible = "fixed-factor-clock";
- 			#clock-cells = <0>;
-@@ -67,6 +68,12 @@
- 			clock-div = <4>;
- 			clock-mult = <1>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -99,6 +106,18 @@
- 		#size-cells = <1>;
- 		ranges = <0x0 0x0 0xff800000 0x800000>;
- 
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+			reg = <0x1000 0x600>;
-+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@12000 {
- 			compatible = "arm,pl011", "arm,primecell";
- 			reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -79,6 +79,7 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
- 		uart_clk: uart-clk {
- 			compatible = "fixed-factor-clock";
- 			#clock-cells = <0>;
-@@ -86,6 +87,12 @@
- 			clock-div = <4>;
- 			clock-mult = <1>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <400000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -117,6 +124,18 @@
- 		#size-cells = <1>;
- 		ranges = <0x0 0x0 0xff800000 0x800000>;
- 
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+			reg = <0x1000 0x600>;
-+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@12000 {
- 			compatible = "arm,pl011", "arm,primecell";
- 			reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -79,6 +79,7 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
- 		uart_clk: uart-clk {
- 			compatible = "fixed-factor-clock";
- 			#clock-cells = <0>;
-@@ -86,6 +87,12 @@
- 			clock-div = <4>;
- 			clock-mult = <1>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <200000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -117,6 +124,19 @@
- 		#size-cells = <1>;
- 		ranges = <0x0 0x0 0xff800000 0x800000>;
- 
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+			reg = <0x1000 0x600>, <0x2610 0x4>;
-+			reg-names = "hsspi", "spim-ctrl";
-+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@12000 {
- 			compatible = "arm,pl011", "arm,primecell";
- 			reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -60,6 +60,12 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <400000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -100,5 +106,17 @@
- 			clock-names = "refclk";
- 			status = "disabled";
- 		};
-+
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+			reg = <0x1000 0x600>;
-+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
- 	};
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -78,6 +78,12 @@
- 			#clock-cells = <0>;
- 			clock-frequency = <200000000>;
- 		};
-+
-+		hsspi_pll: hsspi-pll {
-+			compatible = "fixed-clock";
-+			#clock-cells = <0>;
-+			clock-frequency = <400000000>;
-+		};
- 	};
- 
- 	psci {
-@@ -137,5 +143,17 @@
- 			clock-names = "refclk";
- 			status = "disabled";
- 		};
-+
-+		hsspi: spi@1000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+			reg = <0x1000 0x600>;
-+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&hsspi_pll &hsspi_pll>;
-+			clock-names = "hsspi", "pll";
-+			num-cs = <8>;
-+			status = "disabled";
-+		};
- 	};
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- 	status = "okay";
- };
-+
-+&hsspi {
-+	status = "okay";
-+};
diff --git a/target/linux/bcm4908/patches-5.15/036-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch b/target/linux/bcm4908/patches-5.15/036-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch
deleted file mode 100644
index 7ce17c1870..0000000000
--- a/target/linux/bcm4908/patches-5.15/036-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 23be9f68f933adee8163b8efc9c6bff71410cc7c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:43:59 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This fixes:
-arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: leds@800: 'led-lan@19', 'led-power@11', 'led-wan-red@12', 'led-wan-white@15', 'led-wps@14' do not match any of the regexes: '^led@[a-f0-9]+$', 'pinctrl-[0-9]+'
-        From schema: Documentation/devicetree/bindings/leds/leds-bcm63138.yaml
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144400.21689-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts     | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -120,7 +120,7 @@
- };
- 
- &leds {
--	led-power@11 {
-+	led@11 {
- 		reg = <0x11>;
- 		function = LED_FUNCTION_POWER;
- 		color = <LED_COLOR_ID_WHITE>;
-@@ -130,7 +130,7 @@
- 		pinctrl-0 = <&pins_led_17_a>;
- 	};
- 
--	led-wan-red@12 {
-+	led@12 {
- 		reg = <0x12>;
- 		function = LED_FUNCTION_WAN;
- 		color = <LED_COLOR_ID_RED>;
-@@ -139,7 +139,7 @@
- 		pinctrl-0 = <&pins_led_18_a>;
- 	};
- 
--	led-wps@14 {
-+	led@14 {
- 		reg = <0x14>;
- 		function = LED_FUNCTION_WPS;
- 		color = <LED_COLOR_ID_WHITE>;
-@@ -148,7 +148,7 @@
- 		pinctrl-0 = <&pins_led_20_a>;
- 	};
- 
--	led-wan-white@15 {
-+	led@15 {
- 		reg = <0x15>;
- 		function = LED_FUNCTION_WAN;
- 		color = <LED_COLOR_ID_WHITE>;
-@@ -157,7 +157,7 @@
- 		pinctrl-0 = <&pins_led_21_a>;
- 	};
- 
--	led-lan@19 {
-+	led@19 {
- 		reg = <0x19>;
- 		function = LED_FUNCTION_LAN;
- 		color = <LED_COLOR_ID_WHITE>;
diff --git a/target/linux/bcm4908/patches-5.15/036-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch b/target/linux/bcm4908/patches-5.15/036-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch
deleted file mode 100644
index 47b2455ae6..0000000000
--- a/target/linux/bcm4908/patches-5.15/036-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:18 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often
-have LEDs indicating state of selected USB ports. Describe those SoC USB
-ports to allow using them as LED trigger sources.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi     | 39 +++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -148,6 +148,19 @@
- 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- 			phys = <&usb_phy PHY_TYPE_USB2>;
- 			status = "disabled";
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			ehci_port1: port@1 {
-+				reg = <1>;
-+				#trigger-source-cells = <0>;
-+			};
-+
-+			ehci_port2: port@2 {
-+				reg = <2>;
-+				#trigger-source-cells = <0>;
-+			};
- 		};
- 
- 		ohci: usb@c400 {
-@@ -156,6 +169,19 @@
- 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- 			phys = <&usb_phy PHY_TYPE_USB2>;
- 			status = "disabled";
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			ohci_port1: port@1 {
-+				reg = <1>;
-+				#trigger-source-cells = <0>;
-+			};
-+
-+			ohci_port2: port@2 {
-+				reg = <2>;
-+				#trigger-source-cells = <0>;
-+			};
- 		};
- 
- 		xhci: usb@d000 {
-@@ -164,6 +190,19 @@
- 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- 			phys = <&usb_phy PHY_TYPE_USB3>;
- 			status = "disabled";
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			xhci_port1: port@1 {
-+				reg = <1>;
-+				#trigger-source-cells = <0>;
-+			};
-+
-+			xhci_port2: port@2 {
-+				reg = <2>;
-+				#trigger-source-cells = <0>;
-+			};
- 		};
- 
- 		bus@80000 {
diff --git a/target/linux/bcm4908/patches-5.15/036-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch b/target/linux/bcm4908/patches-5.15/036-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch
deleted file mode 100644
index 3e210d68e1..0000000000
--- a/target/linux/bcm4908/patches-5.15/036-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:19 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -58,12 +58,16 @@
- 			function = "usb2";
- 			color = <LED_COLOR_ID_WHITE>;
- 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+			trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+			linux,default-trigger = "usbport";
- 		};
- 
- 		led-usb3 {
- 			function = "usb3";
- 			color = <LED_COLOR_ID_WHITE>;
- 			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-+			trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+			linux,default-trigger = "usbport";
- 		};
- 
- 		led-wifi {
diff --git a/target/linux/bcm4908/patches-5.15/036-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch b/target/linux/bcm4908/patches-5.15/036-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch
deleted file mode 100644
index 959ccd4fa3..0000000000
--- a/target/linux/bcm4908/patches-5.15/036-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:20 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-While at it fix typo in USB LED name.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts  | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -64,12 +64,16 @@
- 			function = "usb2";
- 			color = <LED_COLOR_ID_BLUE>;
- 			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-+			trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+			linux,default-trigger = "usbport";
- 		};
- 
- 		led-usb3 {
--			function = "usbd3";
-+			function = "usb3";
- 			color = <LED_COLOR_ID_BLUE>;
- 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+			trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+			linux,default-trigger = "usbport";
- 		};
- 
- 		led-brightness {
diff --git a/target/linux/bcm4908/patches-5.15/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch b/target/linux/bcm4908/patches-5.15/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch
deleted file mode 100644
index 4d4059b17f..0000000000
--- a/target/linux/bcm4908/patches-5.15/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch
+++ /dev/null
@@ -1,137 +0,0 @@
-From 002181f5b150e60c77f21de7ad4dd10e4614cd91 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 11 Jul 2022 17:30:41 +0200
-Subject: [PATCH] mtd: parsers: add Broadcom's U-Boot parser
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom stores environment variables blocks inside U-Boot partition
-itself. This driver finds & registers them.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-2-zajec5@gmail.com
----
- drivers/mtd/parsers/Kconfig       | 10 ++++
- drivers/mtd/parsers/Makefile      |  1 +
- drivers/mtd/parsers/brcm_u-boot.c | 84 +++++++++++++++++++++++++++++++
- 3 files changed, 95 insertions(+)
- create mode 100644 drivers/mtd/parsers/brcm_u-boot.c
-
---- a/drivers/mtd/parsers/Kconfig
-+++ b/drivers/mtd/parsers/Kconfig
-@@ -20,6 +20,16 @@ config MTD_BCM63XX_PARTS
- 	  This provides partition parsing for BCM63xx devices with CFE
- 	  bootloaders.
- 
-+config MTD_BRCM_U_BOOT
-+	tristate "Broadcom's U-Boot partition parser"
-+	depends on ARCH_BCM4908 || COMPILE_TEST
-+	help
-+	  Broadcom uses a custom way of storing U-Boot environment variables.
-+	  They are placed inside U-Boot partition itself at unspecified offset.
-+	  It's possible to locate them by looking for a custom header with a
-+	  magic value. This driver does that and creates subpartitions for
-+	  each found environment variables block.
-+
- config MTD_CMDLINE_PARTS
- 	tristate "Command line partition table parsing"
- 	depends on MTD
---- a/drivers/mtd/parsers/Makefile
-+++ b/drivers/mtd/parsers/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_MTD_AR7_PARTS)		+= ar7part.o
- obj-$(CONFIG_MTD_BCM47XX_PARTS)		+= bcm47xxpart.o
- obj-$(CONFIG_MTD_BCM63XX_PARTS)		+= bcm63xxpart.o
-+obj-$(CONFIG_MTD_BRCM_U_BOOT)		+= brcm_u-boot.o
- obj-$(CONFIG_MTD_CMDLINE_PARTS)		+= cmdlinepart.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS)		+= myloader.o
- obj-$(CONFIG_MTD_OF_PARTS)		+= ofpart.o
---- /dev/null
-+++ b/drivers/mtd/parsers/brcm_u-boot.c
-@@ -0,0 +1,84 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright © 2022 Rafał Miłecki <rafal@milecki.pl>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+
-+#define BRCM_U_BOOT_MAX_OFFSET		0x200000
-+#define BRCM_U_BOOT_STEP		0x1000
-+
-+#define BRCM_U_BOOT_MAX_PARTS		2
-+
-+#define BRCM_U_BOOT_MAGIC		0x75456e76	/* uEnv */
-+
-+struct brcm_u_boot_header {
-+	__le32 magic;
-+	__le32 length;
-+} __packed;
-+
-+static const char *names[BRCM_U_BOOT_MAX_PARTS] = {
-+	"u-boot-env",
-+	"u-boot-env-backup",
-+};
-+
-+static int brcm_u_boot_parse(struct mtd_info *mtd,
-+			     const struct mtd_partition **pparts,
-+			     struct mtd_part_parser_data *data)
-+{
-+	struct brcm_u_boot_header header;
-+	struct mtd_partition *parts;
-+	size_t bytes_read;
-+	size_t offset;
-+	int err;
-+	int i = 0;
-+
-+	parts = kcalloc(BRCM_U_BOOT_MAX_PARTS, sizeof(*parts), GFP_KERNEL);
-+	if (!parts)
-+		return -ENOMEM;
-+
-+	for (offset = 0;
-+	     offset < min_t(size_t, mtd->size, BRCM_U_BOOT_MAX_OFFSET);
-+	     offset += BRCM_U_BOOT_STEP) {
-+		err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header);
-+		if (err && !mtd_is_bitflip(err)) {
-+			pr_err("Failed to read from %s at 0x%zx: %d\n", mtd->name, offset, err);
-+			continue;
-+		}
-+
-+		if (le32_to_cpu(header.magic) != BRCM_U_BOOT_MAGIC)
-+			continue;
-+
-+		parts[i].name = names[i];
-+		parts[i].offset = offset;
-+		parts[i].size = sizeof(header) + le32_to_cpu(header.length);
-+		i++;
-+		pr_info("offset:0x%zx magic:0x%08x BINGO\n", offset, header.magic);
-+
-+		if (i == BRCM_U_BOOT_MAX_PARTS)
-+			break;
-+	}
-+
-+	*pparts = parts;
-+
-+	return i;
-+};
-+
-+static const struct of_device_id brcm_u_boot_of_match_table[] = {
-+	{ .compatible = "brcm,u-boot" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, brcm_u_boot_of_match_table);
-+
-+static struct mtd_part_parser brcm_u_boot_mtd_parser = {
-+	.parse_fn = brcm_u_boot_parse,
-+	.name = "brcm_u-boot",
-+	.of_match_table = brcm_u_boot_of_match_table,
-+};
-+module_mtd_part_parser(brcm_u_boot_mtd_parser);
-+
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/bcm4908/patches-5.15/070-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch b/target/linux/bcm4908/patches-5.15/070-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch
deleted file mode 100644
index e01c1e4728..0000000000
--- a/target/linux/bcm4908/patches-5.15/070-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch
+++ /dev/null
@@ -1,209 +0,0 @@
-From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 29 Dec 2021 18:16:42 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs.
-2. Add helper for handling non-lineral port <-> reg mappings.
-3. Add support for 12 B LED reg blocks on BCM4908 (different layout)
-
-Complete support for LEDs setup will be implemented once Linux receives
-a proper design & implementation for "hardware" LEDs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/dsa/bcm_sf2.c      | 54 ++++++++++++++++++++++++----
- drivers/net/dsa/bcm_sf2.h      | 10 ++++++
- drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++---
- 3 files changed, 119 insertions(+), 10 deletions(-)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -62,6 +62,38 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
- 	return REG_SWITCH_STATUS;
- }
- 
-+static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
-+{
-+	switch (port) {
-+	case 0:
-+		return REG_LED_0_CNTRL;
-+	case 1:
-+		return REG_LED_1_CNTRL;
-+	case 2:
-+		return REG_LED_2_CNTRL;
-+	}
-+
-+	switch (priv->type) {
-+	case BCM4908_DEVICE_ID:
-+		switch (port) {
-+		case 3:
-+			return REG_LED_3_CNTRL;
-+		case 7:
-+			return REG_LED_4_CNTRL;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	WARN_ONCE(1, "Unsupported port %d\n", port);
-+
-+	/* RO fallback reg */
-+	return REG_SWITCH_STATUS;
-+}
-+
- /* Return the number of active ports, not counting the IMP (CPU) port */
- static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
- {
-@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru
- 
- 	/* Use PHY-driven LED signaling */
- 	if (!enable) {
--		reg = reg_readl(priv, REG_LED_CNTRL(0));
--		reg |= SPDLNK_SRC_SEL;
--		reg_writel(priv, reg, REG_LED_CNTRL(0));
-+		u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
-+
-+		if (priv->type == BCM7278_DEVICE_ID ||
-+		    priv->type == BCM7445_DEVICE_ID) {
-+			reg = reg_led_readl(priv, led_ctrl, 0);
-+			reg |= LED_CNTRL_SPDLNK_SRC_SEL;
-+			reg_led_writel(priv, reg, led_ctrl, 0);
-+		}
- 	}
- }
- 
-@@ -1247,9 +1284,14 @@ static const u16 bcm_sf2_4908_reg_offset
- 	[REG_SPHY_CNTRL]	= 0x24,
- 	[REG_CROSSBAR]		= 0xc8,
- 	[REG_RGMII_11_CNTRL]	= 0x014c,
--	[REG_LED_0_CNTRL]	= 0x40,
--	[REG_LED_1_CNTRL]	= 0x4c,
--	[REG_LED_2_CNTRL]	= 0x58,
-+	[REG_LED_0_CNTRL]		= 0x40,
-+	[REG_LED_1_CNTRL]		= 0x4c,
-+	[REG_LED_2_CNTRL]		= 0x58,
-+	[REG_LED_3_CNTRL]		= 0x64,
-+	[REG_LED_4_CNTRL]		= 0x88,
-+	[REG_LED_5_CNTRL]		= 0xa0,
-+	[REG_LED_AGGREGATE_CTRL]	= 0xb8,
-+
- };
- 
- static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
---- a/drivers/net/dsa/bcm_sf2.h
-+++ b/drivers/net/dsa/bcm_sf2.h
-@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);
- SWITCH_INTR_L2(0);
- SWITCH_INTR_L2(1);
- 
-+static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
-+{
-+	return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
-+static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
-+{
-+	writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
- /* RXNFC */
- int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
- 		      struct ethtool_rxnfc *nfc, u32 *rule_locs);
---- a/drivers/net/dsa/bcm_sf2_regs.h
-+++ b/drivers/net/dsa/bcm_sf2_regs.h
-@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {
- 	REG_LED_0_CNTRL,
- 	REG_LED_1_CNTRL,
- 	REG_LED_2_CNTRL,
-+	REG_LED_3_CNTRL,
-+	REG_LED_4_CNTRL,
-+	REG_LED_5_CNTRL,
-+	REG_LED_AGGREGATE_CTRL,
- 	REG_SWITCH_REG_MAX,
- };
- 
-@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {
- #define CROSSBAR_BCM4908_EXT_GPHY4	1
- #define CROSSBAR_BCM4908_EXT_RGMII	2
- 
-+/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
-+#define  LED_CNTRL_NO_LINK_ENCODE_SHIFT		0
-+#define  LED_CNTRL_M10_ENCODE_SHIFT		2
-+#define  LED_CNTRL_M100_ENCODE_SHIFT		4
-+#define  LED_CNTRL_M1000_ENCODE_SHIFT		6
-+#define  LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT	8
-+#define  LED_CNTRL_SEL_10M_ENCODE_SHIFT		10
-+#define  LED_CNTRL_SEL_100M_ENCODE_SHIFT	12
-+#define  LED_CNTRL_SEL_1000M_ENCODE_SHIFT	14
-+#define  LED_CNTRL_RX_DV_EN			(1 << 16)
-+#define  LED_CNTRL_TX_EN_EN			(1 << 17)
-+#define  LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT	18
-+#define  LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT	20
-+#define  LED_CNTRL_ACT_LED_ACT_SEL_SHIFT	22
-+#define  LED_CNTRL_SPDLNK_SRC_SEL		(1 << 24)
-+#define  LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL	(1 << 25)
-+#define  LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL	(1 << 26)
-+#define  LED_CNTRL_ACT_LED_POL_SEL		(1 << 27)
-+#define  LED_CNTRL_MASK				0x3
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_CTRL				0x0
-+#define  LED_CTRL_RX_ACT_EN			0x00000001
-+#define  LED_CTRL_TX_ACT_EN			0x00000002
-+#define  LED_CTRL_SPDLNK_LED0_ACT_SEL		0x00000004
-+#define  LED_CTRL_SPDLNK_LED1_ACT_SEL		0x00000008
-+#define  LED_CTRL_SPDLNK_LED2_ACT_SEL		0x00000010
-+#define  LED_CTRL_ACT_LED_ACT_SEL		0x00000020
-+#define  LED_CTRL_SPDLNK_LED0_ACT_POL_SEL	0x00000040
-+#define  LED_CTRL_SPDLNK_LED1_ACT_POL_SEL	0x00000080
-+#define  LED_CTRL_SPDLNK_LED2_ACT_POL_SEL	0x00000100
-+#define  LED_CTRL_ACT_LED_POL_SEL		0x00000200
-+#define  LED_CTRL_LED_SPD_OVRD			0x00001c00
-+#define  LED_CTRL_LNK_STATUS_OVRD		0x00002000
-+#define  LED_CTRL_SPD_OVRD_EN			0x00004000
-+#define  LED_CTRL_LNK_OVRD_EN			0x00008000
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC_SEL		0x4
-+#define  LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT	0
-+#define  LED_LINK_SPEED_ENC_SEL_10M_SHIFT	3
-+#define  LED_LINK_SPEED_ENC_SEL_100M_SHIFT	6
-+#define  LED_LINK_SPEED_ENC_SEL_1000M_SHIFT	9
-+#define  LED_LINK_SPEED_ENC_SEL_2500M_SHIFT	12
-+#define  LED_LINK_SPEED_ENC_SEL_10G_SHIFT	15
-+#define  LED_LINK_SPEED_ENC_SEL_MASK		0x7
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC			0x8
-+#define  LED_LINK_SPEED_ENC_NO_LINK_SHIFT	0
-+#define  LED_LINK_SPEED_ENC_M10_SHIFT		3
-+#define  LED_LINK_SPEED_ENC_M100_SHIFT		6
-+#define  LED_LINK_SPEED_ENC_M1000_SHIFT		9
-+#define  LED_LINK_SPEED_ENC_M2500_SHIFT		12
-+#define  LED_LINK_SPEED_ENC_M10G_SHIFT		15
-+#define  LED_LINK_SPEED_ENC_MASK		0x7
-+
- /* Relative to REG_RGMII_CNTRL */
- #define  RGMII_MODE_EN			(1 << 0)
- #define  ID_MODE_DIS			(1 << 1)
-@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {
- #define  LPI_COUNT_SHIFT		9
- #define  LPI_COUNT_MASK			0x3F
- 
--#define REG_LED_CNTRL(x)		(REG_LED_0_CNTRL + (x))
--
--#define  SPDLNK_SRC_SEL			(1 << 24)
--
- /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
- #define INTRL2_CPU_STATUS		0x00
- #define INTRL2_CPU_SET			0x04
diff --git a/target/linux/bcm4908/patches-5.15/071-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch b/target/linux/bcm4908/patches-5.15/071-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch
deleted file mode 100644
index 85be40cef4..0000000000
--- a/target/linux/bcm4908/patches-5.15/071-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From e93a766da57fff3273bcb618edf5dfca1fb86b89 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 15 Sep 2022 15:30:13 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: handle -EPROBE_DEFER when
- getting MAC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reading MAC from OF may return -EPROBE_DEFER if underlaying NVMEM device
-isn't ready yet. In such case pass that error code up and "wait" to be
-probed later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220915133013.2243-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -720,6 +720,8 @@ static int bcm4908_enet_probe(struct pla
- 
- 	SET_NETDEV_DEV(netdev, &pdev->dev);
- 	err = of_get_ethdev_address(dev->of_node, netdev);
-+	if (err == -EPROBE_DEFER)
-+		goto err_dma_free;
- 	if (err)
- 		eth_hw_addr_random(netdev);
- 	netdev->netdev_ops = &bcm4908_enet_netdev_ops;
-@@ -730,14 +732,17 @@ static int bcm4908_enet_probe(struct pla
- 	netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
- 
- 	err = register_netdev(netdev);
--	if (err) {
--		bcm4908_enet_dma_free(enet);
--		return err;
--	}
-+	if (err)
-+		goto err_dma_free;
- 
- 	platform_set_drvdata(pdev, enet);
- 
- 	return 0;
-+
-+err_dma_free:
-+	bcm4908_enet_dma_free(enet);
-+
-+	return err;
- }
- 
- static int bcm4908_enet_remove(struct platform_device *pdev)
diff --git a/target/linux/bcm4908/patches-5.15/072-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch b/target/linux/bcm4908/patches-5.15/072-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch
deleted file mode 100644
index 1b4cc9e24c..0000000000
--- a/target/linux/bcm4908/patches-5.15/072-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch
+++ /dev/null
@@ -1,152 +0,0 @@
-From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 25 Oct 2022 15:22:45 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-RX code can be more efficient with the build_skb(). Allocating actual
-SKB around eth packet buffer - right before passing it up - results in
-a better cache usage.
-
-Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps"
-between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This
-change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using
-single stream iperf 2.0.5 traffic).
-
-There are more optimizations to consider. One obvious to try is GRO
-however as BCM4908 doesn't do hw csum is may actually lower performance.
-Sometimes. Some early testing:
-
-┌─────────────────────────────────┬─────────────────────┬────────────────────┐
-│                                 │ netif_receive_skb() │ napi_gro_receive() │
-├─────────────────────────────────┼─────────────────────┼────────────────────┤
-│ netdev_alloc_skb()              │            905 Mb/s │           892 Mb/s │
-│ napi_alloc_frag() + build_skb() │            918 Mb/s │           917 Mb/s │
-└─────────────────────────────────┴─────────────────────┴────────────────────┘
-
-Another ideas:
-1. napi_build_skb()
-2. skb_copy_from_linear_data() for small packets
-
-Those need proper testing first though. That can be done later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++-------
- 1 file changed, 36 insertions(+), 17 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -36,13 +36,24 @@
- #define ENET_MAX_ETH_OVERHEAD			(ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
- 						 ETH_FCS_LEN + 4) /* 32 */
- 
-+#define ENET_RX_SKB_BUF_SIZE			(NET_SKB_PAD + NET_IP_ALIGN + \
-+						 ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
-+						 ENET_MTU_MAX + ETH_FCS_LEN + 4)
-+#define ENET_RX_SKB_BUF_ALLOC_SIZE		(SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \
-+						 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
-+#define ENET_RX_BUF_DMA_OFFSET			(NET_SKB_PAD + NET_IP_ALIGN)
-+#define ENET_RX_BUF_DMA_SIZE			(ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET)
-+
- struct bcm4908_enet_dma_ring_bd {
- 	__le32 ctl;
- 	__le32 addr;
- } __packed;
- 
- struct bcm4908_enet_dma_ring_slot {
--	struct sk_buff *skb;
-+	union {
-+		void *buf;			/* RX */
-+		struct sk_buff *skb;		/* TX */
-+	};
- 	unsigned int len;
- 	dma_addr_t dma_addr;
- };
-@@ -260,22 +271,21 @@ static int bcm4908_enet_dma_alloc_rx_buf
- 	u32 tmp;
- 	int err;
- 
--	slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
--
--	slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
--	if (!slot->skb)
-+	slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE);
-+	if (!slot->buf)
- 		return -ENOMEM;
- 
--	slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
-+	slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET,
-+					ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
- 	err = dma_mapping_error(dev, slot->dma_addr);
- 	if (err) {
- 		dev_err(dev, "Failed to map DMA buffer: %d\n", err);
--		kfree_skb(slot->skb);
--		slot->skb = NULL;
-+		skb_free_frag(slot->buf);
-+		slot->buf = NULL;
- 		return err;
- 	}
- 
--	tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
-+	tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
- 	tmp |= DMA_CTL_STATUS_OWN;
- 	if (idx == enet->rx_ring.length - 1)
- 		tmp |= DMA_CTL_STATUS_WRAP;
-@@ -315,11 +325,11 @@ static void bcm4908_enet_dma_uninit(stru
- 
- 	for (i = rx_ring->length - 1; i >= 0; i--) {
- 		slot = &rx_ring->slots[i];
--		if (!slot->skb)
-+		if (!slot->buf)
- 			continue;
- 		dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
--		kfree_skb(slot->skb);
--		slot->skb = NULL;
-+		skb_free_frag(slot->buf);
-+		slot->buf = NULL;
- 	}
- }
- 
-@@ -575,6 +585,7 @@ static int bcm4908_enet_poll_rx(struct n
- 	while (handled < weight) {
- 		struct bcm4908_enet_dma_ring_bd *buf_desc;
- 		struct bcm4908_enet_dma_ring_slot slot;
-+		struct sk_buff *skb;
- 		u32 ctl;
- 		int len;
- 		int err;
-@@ -598,16 +609,24 @@ static int bcm4908_enet_poll_rx(struct n
- 
- 		if (len < ETH_ZLEN ||
- 		    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
--			kfree_skb(slot.skb);
-+			skb_free_frag(slot.buf);
- 			enet->netdev->stats.rx_dropped++;
- 			break;
- 		}
- 
--		dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
-+		dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
-+
-+		skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE);
-+		if (unlikely(!skb)) {
-+			skb_free_frag(slot.buf);
-+			enet->netdev->stats.rx_dropped++;
-+			break;
-+		}
-+		skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET);
-+		skb_put(skb, len - ETH_FCS_LEN);
-+		skb->protocol = eth_type_trans(skb, enet->netdev);
- 
--		skb_put(slot.skb, len - ETH_FCS_LEN);
--		slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
--		netif_receive_skb(slot.skb);
-+		netif_receive_skb(skb);
- 
- 		enet->netdev->stats.rx_packets++;
- 		enet->netdev->stats.rx_bytes += len;
diff --git a/target/linux/bcm4908/patches-5.15/072-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch b/target/linux/bcm4908/patches-5.15/072-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch
deleted file mode 100644
index fe85aefa7c..0000000000
--- a/target/linux/bcm4908/patches-5.15/072-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 31 Oct 2022 11:48:56 +0100
-Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted
- bytes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows BQL to operate avoiding buffer bloat and reducing latency.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -505,6 +505,7 @@ static int bcm4908_enet_stop(struct net_
- 	netif_carrier_off(netdev);
- 	napi_disable(&rx_ring->napi);
- 	napi_disable(&tx_ring->napi);
-+	netdev_reset_queue(netdev);
- 
- 	bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
- 	bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
-@@ -564,6 +565,8 @@ static int bcm4908_enet_start_xmit(struc
- 	if (ring->write_idx + 1 == ring->length - 1)
- 		tmp |= DMA_CTL_STATUS_WRAP;
- 
-+	netdev_sent_queue(enet->netdev, skb->len);
-+
- 	buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
- 	buf_desc->ctl = cpu_to_le32(tmp);
- 
-@@ -671,6 +674,7 @@ static int bcm4908_enet_poll_tx(struct n
- 			tx_ring->read_idx = 0;
- 	}
- 
-+	netdev_completed_queue(enet->netdev, handled, bytes);
- 	enet->netdev->stats.tx_packets += handled;
- 	enet->netdev->stats.tx_bytes += bytes;
- 
diff --git a/target/linux/bcm4908/patches-5.15/080-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch b/target/linux/bcm4908/patches-5.15/080-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch
deleted file mode 100644
index adc7d6bb0c..0000000000
--- a/target/linux/bcm4908/patches-5.15/080-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:42 +0100
-Subject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's hardware block that is part of every SoC from BCM4908 family.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/brcm,bcm4908-pinctrl.yaml         | 72 +++++++++++++++++++
- MAINTAINERS                                   |  7 ++
- 2 files changed, 79 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-@@ -0,0 +1,72 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Broadcom BCM4908 pin controller
-+
-+maintainers:
-+  - Rafał Miłecki <rafal@milecki.pl>
-+
-+description:
-+  Binding for pin controller present on BCM4908 family SoCs.
-+
-+properties:
-+  compatible:
-+    const: brcm,bcm4908-pinctrl
-+
-+  reg:
-+    maxItems: 1
-+
-+patternProperties:
-+  '-pins$':
-+    type: object
-+    $ref: pinmux-node.yaml#
-+
-+    properties:
-+      function:
-+        enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
-+                led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
-+                led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
-+                led_25, led_26, led_27, led_28, led_29, led_30, led_31,
-+                hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
-+                usb1_pwr ]
-+
-+      groups:
-+        minItems: 1
-+        maxItems: 2
-+        items:
-+          enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
-+                  led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
-+                  led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
-+                  led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
-+                  led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
-+                  led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
-+                  led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
-+                  led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
-+                  led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
-+                  led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
-+                  nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
-+                  usb1_pwr_grp ]
-+
-+allOf:
-+  - $ref: pinctrl.yaml#
-+
-+required:
-+  - compatible
-+  - reg
-+
-+unevaluatedProperties: false
-+
-+examples:
-+  - |
-+    pinctrl@ff800560 {
-+        compatible = "brcm,bcm4908-pinctrl";
-+        reg = <0xff800560 0x10>;
-+
-+        led_0-a-pins {
-+            function = "led_0";
-+            groups = "led_0_grp_a";
-+        };
-+    };
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3573,6 +3573,13 @@ F:	Documentation/devicetree/bindings/net
- F:	drivers/net/ethernet/broadcom/bcm4908_enet.*
- F:	drivers/net/ethernet/broadcom/unimac.h
- 
-+BROADCOM BCM4908 PINMUX DRIVER
-+M:	Rafał Miłecki <rafal@milecki.pl>
-+M:	bcm-kernel-feedback-list@broadcom.com
-+L:	linux-gpio@vger.kernel.org
-+S:	Maintained
-+F:	Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+
- BROADCOM BCM5301X ARM ARCHITECTURE
- M:	Hauke Mehrtens <hauke@hauke-m.de>
- M:	Rafał Miłecki <zajec5@gmail.com>
diff --git a/target/linux/bcm4908/patches-5.15/080-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch b/target/linux/bcm4908/patches-5.15/080-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch
deleted file mode 100644
index 3fd847b97e..0000000000
--- a/target/linux/bcm4908/patches-5.15/080-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch
+++ /dev/null
@@ -1,629 +0,0 @@
-From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:43 +0100
-Subject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has its own pins layout so it needs a custom binding and a Linux
-driver.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- MAINTAINERS                           |   1 +
- drivers/pinctrl/bcm/Kconfig           |  14 +
- drivers/pinctrl/bcm/Makefile          |   1 +
- drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++
- 4 files changed, 579 insertions(+)
- create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3579,6 +3579,7 @@ M:	bcm-kernel-feedback-list@broadcom.com
- L:	linux-gpio@vger.kernel.org
- S:	Maintained
- F:	Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+F:	drivers/pinctrl/bcm/pinctrl-bcm4908.c
- 
- BROADCOM BCM5301X ARM ARCHITECTURE
- M:	Hauke Mehrtens <hauke@hauke-m.de>
---- a/drivers/pinctrl/bcm/Kconfig
-+++ b/drivers/pinctrl/bcm/Kconfig
-@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
- 	help
- 	   Say Y here to enable the Broadcom BCM2835 GPIO driver.
- 
-+config PINCTRL_BCM4908
-+	tristate "Broadcom BCM4908 pinmux driver"
-+	depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
-+	select PINMUX
-+	select PINCONF
-+	select GENERIC_PINCONF
-+	select GENERIC_PINCTRL_GROUPS
-+	select GENERIC_PINMUX_FUNCTIONS
-+	default ARCH_BCM4908
-+	help
-+	  Driver for BCM4908 family SoCs with integrated pin controller.
-+
-+	  If compiled as module it will be called pinctrl-bcm4908.
-+
- config PINCTRL_BCM63XX
- 	bool
- 	select PINMUX
---- a/drivers/pinctrl/bcm/Makefile
-+++ b/drivers/pinctrl/bcm/Makefile
-@@ -3,6 +3,7 @@
- 
- obj-$(CONFIG_PINCTRL_BCM281XX)		+= pinctrl-bcm281xx.o
- obj-$(CONFIG_PINCTRL_BCM2835)		+= pinctrl-bcm2835.o
-+obj-$(CONFIG_PINCTRL_BCM4908)		+= pinctrl-bcm4908.o
- obj-$(CONFIG_PINCTRL_BCM63XX)		+= pinctrl-bcm63xx.o
- obj-$(CONFIG_PINCTRL_BCM6318)		+= pinctrl-bcm6318.o
- obj-$(CONFIG_PINCTRL_BCM6328)		+= pinctrl-bcm6328.o
---- /dev/null
-+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
-@@ -0,0 +1,560 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/pinctrl/pinconf-generic.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/string_helpers.h>
-+
-+#include "../core.h"
-+#include "../pinmux.h"
-+
-+#define BCM4908_NUM_PINS			86
-+
-+#define BCM4908_TEST_PORT_BLOCK_EN_LSB			0x00
-+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB		0x04
-+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB		0x08
-+#define  BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT	12
-+#define BCM4908_TEST_PORT_COMMAND			0x0c
-+#define  BCM4908_TEST_PORT_CMD_LOAD_MUX_REG		0x00000021
-+
-+struct bcm4908_pinctrl {
-+	struct device *dev;
-+	void __iomem *base;
-+	struct mutex mutex;
-+	struct pinctrl_dev *pctldev;
-+	struct pinctrl_desc pctldesc;
-+};
-+
-+/*
-+ * Groups
-+ */
-+
-+struct bcm4908_pinctrl_pin_setup {
-+	unsigned int number;
-+	unsigned int function;
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
-+	{ 0, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
-+	{ 1, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
-+	{ 2, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
-+	{ 3, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
-+	{ 4, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
-+	{ 5, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
-+	{ 6, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
-+	{ 7, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
-+	{ 8, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
-+	{ 9, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
-+	{ 10, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
-+	{ 11, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
-+	{ 12, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
-+	{ 13, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
-+	{ 14, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
-+	{ 15, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
-+	{ 16, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
-+	{ 17, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
-+	{ 18, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
-+	{ 19, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
-+	{ 20, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
-+	{ 21, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
-+	{ 22, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
-+	{ 23, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
-+	{ 24, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
-+	{ 25, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
-+	{ 26, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
-+	{ 27, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
-+	{ 28, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
-+	{ 29, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
-+	{ 30, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
-+	{ 31, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
-+	{ 8, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
-+	{ 9, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
-+	{ 0, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
-+	{ 1, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
-+	{ 30, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
-+	{ 10, 0 },	/* CTS */
-+	{ 11, 0 },	/* RTS */
-+	{ 12, 0 },	/* RXD */
-+	{ 13, 0 },	/* TXD */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
-+	{ 18, 0 },	/* SDA */
-+	{ 19, 0 },	/* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
-+	{ 22, 0 },	/* SDA */
-+	{ 23, 0 },	/* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
-+	{ 27, 0 },	/* MCLK */
-+	{ 28, 0 },	/* LRCK */
-+	{ 29, 0 },	/* SDATA */
-+	{ 30, 0 },	/* SCLK */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
-+	{ 32, 0 },
-+	{ 33, 0 },
-+	{ 34, 0 },
-+	{ 43, 0 },
-+	{ 44, 0 },
-+	{ 45, 0 },
-+	{ 56, 1 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
-+	{ 35, 0 },
-+	{ 36, 0 },
-+	{ 37, 0 },
-+	{ 38, 0 },
-+	{ 39, 0 },
-+	{ 40, 0 },
-+	{ 41, 0 },
-+	{ 42, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
-+	{ 46, 0 },
-+	{ 47, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
-+	{ 63, 0 },
-+	{ 64, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
-+	{ 66, 0 },
-+	{ 67, 0 },
-+};
-+
-+struct bcm4908_pinctrl_grp {
-+	const char *name;
-+	const struct bcm4908_pinctrl_pin_setup *pins;
-+	const unsigned int num_pins;
-+};
-+
-+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
-+	{ "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
-+	{ "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
-+	{ "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
-+	{ "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
-+	{ "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
-+	{ "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
-+	{ "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
-+	{ "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
-+	{ "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
-+	{ "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
-+	{ "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
-+	{ "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
-+	{ "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
-+	{ "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
-+	{ "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
-+	{ "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
-+	{ "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
-+	{ "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
-+	{ "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
-+	{ "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
-+	{ "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
-+	{ "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
-+	{ "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
-+	{ "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
-+	{ "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
-+	{ "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
-+	{ "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
-+	{ "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
-+	{ "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
-+	{ "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
-+	{ "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
-+	{ "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
-+	{ "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
-+	{ "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
-+	{ "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
-+	{ "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
-+	{ "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
-+	{ "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
-+	{ "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
-+	{ "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
-+	{ "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
-+	{ "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
-+	{ "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
-+	{ "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
-+	{ "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
-+	{ "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
-+};
-+
-+/*
-+ * Functions
-+ */
-+
-+struct bcm4908_pinctrl_function {
-+	const char *name;
-+	const char **groups;
-+	const unsigned int num_groups;
-+};
-+
-+static const char *led_0_groups[] = { "led_0_grp_a" };
-+static const char *led_1_groups[] = { "led_1_grp_a" };
-+static const char *led_2_groups[] = { "led_2_grp_a" };
-+static const char *led_3_groups[] = { "led_3_grp_a" };
-+static const char *led_4_groups[] = { "led_4_grp_a" };
-+static const char *led_5_groups[] = { "led_5_grp_a" };
-+static const char *led_6_groups[] = { "led_6_grp_a" };
-+static const char *led_7_groups[] = { "led_7_grp_a" };
-+static const char *led_8_groups[] = { "led_8_grp_a" };
-+static const char *led_9_groups[] = { "led_9_grp_a" };
-+static const char *led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
-+static const char *led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
-+static const char *led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
-+static const char *led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
-+static const char *led_14_groups[] = { "led_14_grp_a" };
-+static const char *led_15_groups[] = { "led_15_grp_a" };
-+static const char *led_16_groups[] = { "led_16_grp_a" };
-+static const char *led_17_groups[] = { "led_17_grp_a" };
-+static const char *led_18_groups[] = { "led_18_grp_a" };
-+static const char *led_19_groups[] = { "led_19_grp_a" };
-+static const char *led_20_groups[] = { "led_20_grp_a" };
-+static const char *led_21_groups[] = { "led_21_grp_a" };
-+static const char *led_22_groups[] = { "led_22_grp_a" };
-+static const char *led_23_groups[] = { "led_23_grp_a" };
-+static const char *led_24_groups[] = { "led_24_grp_a" };
-+static const char *led_25_groups[] = { "led_25_grp_a" };
-+static const char *led_26_groups[] = { "led_26_grp_a" };
-+static const char *led_27_groups[] = { "led_27_grp_a" };
-+static const char *led_28_groups[] = { "led_28_grp_a" };
-+static const char *led_29_groups[] = { "led_29_grp_a" };
-+static const char *led_30_groups[] = { "led_30_grp_a" };
-+static const char *led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
-+static const char *hs_uart_groups[] = { "hs_uart_grp" };
-+static const char *i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
-+static const char *i2s_groups[] = { "i2s_grp" };
-+static const char *nand_ctrl_groups[] = { "nand_ctrl_grp" };
-+static const char *nand_data_groups[] = { "nand_data_grp" };
-+static const char *emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
-+static const char *usb0_pwr_groups[] = { "usb0_pwr_grp" };
-+static const char *usb1_pwr_groups[] = { "usb1_pwr_grp" };
-+
-+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
-+	{ "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
-+	{ "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
-+	{ "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
-+	{ "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
-+	{ "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
-+	{ "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
-+	{ "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
-+	{ "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
-+	{ "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
-+	{ "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
-+	{ "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
-+	{ "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
-+	{ "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
-+	{ "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
-+	{ "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
-+	{ "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
-+	{ "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
-+	{ "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
-+	{ "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
-+	{ "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
-+	{ "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
-+	{ "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
-+	{ "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
-+	{ "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
-+	{ "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
-+	{ "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
-+	{ "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
-+	{ "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
-+	{ "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
-+	{ "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
-+	{ "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
-+	{ "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
-+	{ "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
-+	{ "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
-+	{ "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
-+	{ "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
-+	{ "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
-+	{ "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
-+	{ "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
-+	{ "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
-+};
-+
-+/*
-+ * Groups code
-+ */
-+
-+static const struct pinctrl_ops bcm4908_pinctrl_ops = {
-+	.get_groups_count = pinctrl_generic_get_group_count,
-+	.get_group_name = pinctrl_generic_get_group_name,
-+	.get_group_pins = pinctrl_generic_get_group_pins,
-+	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
-+	.dt_free_map = pinconf_generic_dt_free_map,
-+};
-+
-+/*
-+ * Functions code
-+ */
-+
-+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
-+			      unsigned int func_selector,
-+			      unsigned int group_selector)
-+{
-+	struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-+	const struct bcm4908_pinctrl_grp *group;
-+	struct group_desc *group_desc;
-+	int i;
-+
-+	group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
-+	if (!group_desc)
-+		return -EINVAL;
-+	group = group_desc->data;
-+
-+	mutex_lock(&bcm4908_pinctrl->mutex);
-+	for (i = 0; i < group->num_pins; i++) {
-+		u32 lsb = 0;
-+
-+		lsb |= group->pins[i].number;
-+		lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
-+
-+		writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
-+		writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
-+		writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
-+		       bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
-+	}
-+	mutex_unlock(&bcm4908_pinctrl->mutex);
-+
-+	return 0;
-+}
-+
-+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
-+	.get_functions_count = pinmux_generic_get_function_count,
-+	.get_function_name = pinmux_generic_get_function_name,
-+	.get_function_groups = pinmux_generic_get_function_groups,
-+	.set_mux = bcm4908_pinctrl_set_mux,
-+};
-+
-+/*
-+ * Controller code
-+ */
-+
-+static struct pinctrl_desc bcm4908_pinctrl_desc = {
-+	.name = "bcm4908-pinctrl",
-+	.pctlops = &bcm4908_pinctrl_ops,
-+	.pmxops = &bcm4908_pinctrl_pmxops,
-+};
-+
-+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
-+	{ .compatible = "brcm,bcm4908-pinctrl", },
-+	{ }
-+};
-+
-+static int bcm4908_pinctrl_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct bcm4908_pinctrl *bcm4908_pinctrl;
-+	struct pinctrl_desc *pctldesc;
-+	struct pinctrl_pin_desc *pins;
-+	int i;
-+
-+	bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
-+	if (!bcm4908_pinctrl)
-+		return -ENOMEM;
-+	pctldesc = &bcm4908_pinctrl->pctldesc;
-+	platform_set_drvdata(pdev, bcm4908_pinctrl);
-+
-+	/* Set basic properties */
-+
-+	bcm4908_pinctrl->dev = dev;
-+
-+	bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(bcm4908_pinctrl->base))
-+		return PTR_ERR(bcm4908_pinctrl->base);
-+
-+	mutex_init(&bcm4908_pinctrl->mutex);
-+
-+	memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
-+
-+	/* Set pinctrl properties */
-+
-+	pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
-+	if (!pins)
-+		return -ENOMEM;
-+	for (i = 0; i < BCM4908_NUM_PINS; i++) {
-+		pins[i].number = i;
-+		pins[i].name = devm_kasprintf(dev, GFP_KERNEL, "pin-%d", i);
-+		if (!pins[i].name)
-+			return -ENOMEM;
-+	}
-+	pctldesc->pins = pins;
-+	pctldesc->npins = BCM4908_NUM_PINS;
-+
-+	/* Register */
-+
-+	bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
-+	if (IS_ERR(bcm4908_pinctrl->pctldev))
-+		return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
-+				     "Failed to register pinctrl\n");
-+
-+	/* Groups */
-+
-+	for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
-+		const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
-+		int *pins;
-+		int j;
-+
-+		pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
-+		if (!pins)
-+			return -ENOMEM;
-+		for (j = 0; j < group->num_pins; j++)
-+			pins[j] = group->pins[j].number;
-+
-+		pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
-+					  pins, group->num_pins, (void *)group);
-+	}
-+
-+	/* Functions */
-+
-+	for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
-+		const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
-+
-+		pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
-+					    function->name,
-+					    function->groups,
-+					    function->num_groups, NULL);
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver bcm4908_pinctrl_driver = {
-+	.probe = bcm4908_pinctrl_probe,
-+	.driver = {
-+		.name = "bcm4908-pinctrl",
-+		.of_match_table = bcm4908_pinctrl_of_match_table,
-+	},
-+};
-+
-+module_platform_driver(bcm4908_pinctrl_driver);
-+
-+MODULE_AUTHOR("Rafał Miłecki");
-+MODULE_LICENSE("GPL v2");
-+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
diff --git a/target/linux/bcm4908/patches-5.15/081-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch b/target/linux/bcm4908/patches-5.15/081-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch
deleted file mode 100644
index 246f249413..0000000000
--- a/target/linux/bcm4908/patches-5.15/081-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 11 Feb 2022 11:58:06 +0100
-Subject: [PATCH] i2c: brcmstb: allow compiling on BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -477,8 +477,8 @@ config I2C_BCM_KONA
- 
- config I2C_BRCMSTB
- 	tristate "BRCM Settop/DSL I2C controller"
--	depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
--		   ARCH_BCM_63XX || COMPILE_TEST
-+	depends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \
-+		   ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- 	default y
- 	help
- 	  If you say yes to this option, support will be included for the
diff --git a/target/linux/bcm4908/patches-5.15/082-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch b/target/linux/bcm4908/patches-5.15/082-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch
deleted file mode 100644
index 0717436ffa..0000000000
--- a/target/linux/bcm4908/patches-5.15/082-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From cd91fb2776967b2b2dea27307a3f23ba3d9bbb32 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:32:02 +0100
-Subject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 is a SoCs family that shares a lot of hardware with BCM63xx
-including the watchdog block. Allow building this driver for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220209203202.26395-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1756,7 +1756,7 @@ config BCM7038_WDT
- 	tristate "BCM7038 Watchdog"
- 	select WATCHDOG_CORE
- 	depends on HAS_IOMEM
--	depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
-+	depends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- 	help
- 	 Watchdog driver for the built-in hardware in Broadcom 7038 and
- 	 later SoCs used in set-top boxes.  BCM7038 was made public
diff --git a/target/linux/bcm4908/patches-5.15/083-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch b/target/linux/bcm4908/patches-5.15/083-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch
deleted file mode 100644
index 14b6c61bac..0000000000
--- a/target/linux/bcm4908/patches-5.15/083-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 2dd441f16d6ad6104d85c4e5dfeb6dde4df26869 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 16 Feb 2022 07:34:08 +0100
-Subject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-A new "compatible" value has been added in the commit 17fffe91ba36
-("dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding").
-It's meant to be used for BCM63xx SoCs family but hardware block can be
-programmed just like the 7038 one.
-
-Cc: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220216063408.23168-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/bcm7038_wdt.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/watchdog/bcm7038_wdt.c
-+++ b/drivers/watchdog/bcm7038_wdt.c
-@@ -212,6 +212,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_
- 			 bcm7038_wdt_resume);
- 
- static const struct of_device_id bcm7038_wdt_match[] = {
-+	{ .compatible = "brcm,bcm6345-wdt" },
- 	{ .compatible = "brcm,bcm7038-wdt" },
- 	{},
- };
diff --git a/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch b/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch
deleted file mode 100644
index 46d632e95d..0000000000
--- a/target/linux/bcm4908/patches-5.15/130-arm64-dts-broadcom-bcmbca-bcm4908-set-brcm-wp-not-co.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 28 Mar 2024 10:24:34 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set
- brcm,wp-not-connected
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Every described BCM4908 board has WP pin not connected. This caused
-problems for drivers since day 0 but there was no property to describe
-that properly. Projects like OpenWrt were modifying Linux driver to deal
-with it.
-
-It's not clear if that is hardware limitation or just reference design
-being copied over and over but this applies to all known / supported
-BCM4908 boards. Handle it by marking WP as not connected by default.
-
-Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -593,6 +593,7 @@
- 			reg-names = "nand", "nand-int-base";
- 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- 			interrupt-names = "nand_ctlrdy";
-+			brcm,wp-not-connected;
- 			status = "okay";
- 
- 			nandcs: nand@0 {
diff --git a/target/linux/bcm4908/patches-5.15/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch b/target/linux/bcm4908/patches-5.15/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch
deleted file mode 100644
index 4adeef8319..0000000000
--- a/target/linux/bcm4908/patches-5.15/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 22:01:03 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Linux driver can't handle more than 64 GPIOs
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -340,7 +340,7 @@
- 		gpio0: gpio-controller@500 {
- 			compatible = "brcm,bcm6345-gpio";
- 			reg-names = "dirout", "dat";
--			reg = <0x500 0x28>, <0x528 0x28>;
-+			reg = <0x500 0x8>, <0x528 0x8>;
- 
- 			#gpio-cells = <2>;
- 			gpio-controller;
diff --git a/target/linux/bcm4908/patches-5.15/301-arm64-don-t-issue-HVC-on-boot.patch b/target/linux/bcm4908/patches-5.15/301-arm64-don-t-issue-HVC-on-boot.patch
deleted file mode 100644
index d167c2ed00..0000000000
--- a/target/linux/bcm4908/patches-5.15/301-arm64-don-t-issue-HVC-on-boot.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 12 Aug 2021 11:52:42 +0200
-Subject: [PATCH] arm64: don't issue HVC on boot
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom's CFE loader seems to miss setting SCR_EL3.HCE which results in
-generating an UNDEF and kernel panic on the first HVC.
-
-HVC gets issued by kernels 5.12+ while booting, by kexec and KVM. Until
-someone finds a workaround we have to avoid all above.
-
-Workarounds: 0c93df9622d4 ("arm64: Initialise as nVHE before switching to VHE")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- arch/arm64/kernel/hyp-stub.S | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/kernel/hyp-stub.S
-+++ b/arch/arm64/kernel/hyp-stub.S
-@@ -238,7 +238,7 @@ SYM_FUNC_START(switch_to_vhe)
- 
- 	// Turn the world upside down
- 	mov	x0, #HVC_VHE_RESTART
--	hvc	#0
-+//	hvc	#0
- 1:
- 	ret
- SYM_FUNC_END(switch_to_vhe)
diff --git a/target/linux/bcm4908/patches-5.15/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch b/target/linux/bcm4908/patches-5.15/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch
deleted file mode 100644
index 165b02da0f..0000000000
--- a/target/linux/bcm4908/patches-5.15/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 23:59:26 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-GPHY needs to be enabled to succesfully probe & setup switch port
-connected to it. Otherwise hardcoding PHY OUI would be required.
-
-Before:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
-
-After:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1548,10 +1548,14 @@ static int bcm_sf2_sw_probe(struct platf
- 	rev = reg_readl(priv, REG_PHY_REVISION);
- 	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
- 
-+	bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- 	ret = b53_switch_register(dev);
- 	if (ret)
- 		goto out_mdio;
- 
-+	bcm_sf2_gphy_enable_set(priv->dev->ds, false);
-+
- 	dev_info(&pdev->dev,
- 		 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
- 		 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
diff --git a/target/linux/bcm4908/patches-5.15/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch b/target/linux/bcm4908/patches-5.15/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch
deleted file mode 100644
index ea0adca26f..0000000000
--- a/target/linux/bcm4908/patches-5.15/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 16 Feb 2021 00:06:35 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
-
-Trying to access disabled PHY results in MDIO_READ_FAIL and:
-[   11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
-[   11.972500] 8021q: adding VLAN 0 to HW filter on device wan
-[   11.980205] ------------[ cut here ]------------
-[   11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1562,6 +1562,12 @@ static int bcm_sf2_sw_probe(struct platf
- 		 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
- 		 priv->irq0, priv->irq1);
- 
-+	/* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
-+	 * GPHY when needed. Leave it enabled here.
-+	 */
-+	if (priv->type == BCM4908_DEVICE_ID)
-+		bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- 	return 0;
- 
- out_mdio:
diff --git a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
index edae77ccd1..9c769880a0 100644
--- a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
+++ b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
@@ -108,7 +108,7 @@ it on BCM4708 family.
  	if (xhci->quirks & XHCI_NEC_HOST)
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1902,6 +1902,7 @@ struct xhci_hcd {
+@@ -1907,6 +1907,7 @@ struct xhci_hcd {
  #define XHCI_RESET_TO_DEFAULT	BIT_ULL(44)
  #define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(45)
  #define XHCI_ZHAOXIN_HOST	BIT_ULL(46)
diff --git a/target/linux/bcm53xx/patches-6.1/600-net-disable-GRO-by-default.patch b/target/linux/bcm53xx/patches-6.1/600-net-disable-GRO-by-default.patch
index 9f6343c791..9fa41a4b7e 100644
--- a/target/linux/bcm53xx/patches-6.1/600-net-disable-GRO-by-default.patch
+++ b/target/linux/bcm53xx/patches-6.1/600-net-disable-GRO-by-default.patch
@@ -25,12 +25,12 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  #define NETIF_F_UPPER_DISABLES	NETIF_F_LRO
  
  /* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
 +#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO)
  
  /* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
  
  #define NETIF_F_VLAN_FEATURES	(NETIF_F_HW_VLAN_CTAG_FILTER | \
  				 NETIF_F_HW_VLAN_CTAG_RX | \
diff --git a/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
index 3b2a7a476a..8b2f86de01 100644
--- a/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
+++ b/target/linux/bcm53xx/patches-6.6/180-usb-xhci-add-support-for-performing-fake-doorbell.patch
@@ -103,7 +103,7 @@ it on BCM4708 family.
  	if (xhci->quirks & XHCI_NEC_HOST)
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1907,6 +1907,7 @@ struct xhci_hcd {
+@@ -1912,6 +1912,7 @@ struct xhci_hcd {
  #define XHCI_RESET_TO_DEFAULT	BIT_ULL(44)
  #define XHCI_ZHAOXIN_TRB_FETCH	BIT_ULL(45)
  #define XHCI_ZHAOXIN_HOST	BIT_ULL(46)
diff --git a/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch b/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch
index 9f6343c791..9fa41a4b7e 100644
--- a/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch
+++ b/target/linux/bcm53xx/patches-6.6/600-net-disable-GRO-by-default.patch
@@ -25,12 +25,12 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  #define NETIF_F_UPPER_DISABLES	NETIF_F_LRO
  
  /* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
 +#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO)
  
  /* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
  
  #define NETIF_F_VLAN_FEATURES	(NETIF_F_HW_VLAN_CTAG_FILTER | \
  				 NETIF_F_HW_VLAN_CTAG_RX | \
diff --git a/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network b/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network
index 104f20ef0e..78c0794f23 100644
--- a/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network
+++ b/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network
@@ -9,6 +9,9 @@ arcadyan,ar7516)
 	ucidef_set_bridge_device switch
 	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
 	;;
+inteno,xg6846)
+	ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan ext1"
+	;;
 comtrend,ar-5381u |\
 comtrend,ar-5387un |\
 innacomm,w3400v6 |\
diff --git a/target/linux/bmips/bcm6328/config-6.1 b/target/linux/bmips/bcm6328/config-6.1
index 5b33e93236..de7784e80a 100644
--- a/target/linux/bmips/bcm6328/config-6.1
+++ b/target/linux/bmips/bcm6328/config-6.1
@@ -170,6 +170,7 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_BCM63XX_FW=y
 CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
diff --git a/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts b/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts
new file mode 100644
index 0000000000..72f85a53ca
--- /dev/null
+++ b/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/*
+ * Devicetree for the Inteno XG6846 router, mostly used as a
+ * media converter from fiber to twisted pair ethernet
+ * "fiber modem" in many households in Sweden. The Marvell
+ * switch has one of its ports connected to an SFP (Small Form
+ * Factor pluggable) optical fiber receiver, which is bridged
+ * to the twisted pair connector LAN1.
+ *
+ * This device tree is inspired by research from the OpenWrt
+ * and Sweclockers forums, including contributions from
+ * NPeca75, mrhaav and csom.
+ *
+ * Some devices have a USB type A host receptacle mounted,
+ * some do not.
+ */
+#include "bcm6328.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Inteno XG6846";
+	compatible = "inteno,xg6846", "brcm,bcm6328";
+
+	/* OpenWrt-specific aliases */
+	aliases {
+		led-boot = &led_pwr_red;
+		led-failsafe = &led_pwr_red;
+		led-running = &led_pwr_green;
+		led-upgrade = &led_pwr_red;
+		led-usb = &led_usb_green;
+	};
+
+	chosen {
+		bootargs = "rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
+	};
+
+	/*
+	 * This I2C port is connected to the SFP and reflects the EEPROM etc
+	 * inside the SFP module. If the module is not plugged in, consequently
+	 * nothing will be found on the bus.
+	 */
+	i2c0: i2c-sfp {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	/* This I2C bus is used for the external CATV connector (usually unused) */
+	i2c1: i2c-catv {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	sfp0: sfp0 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c0>;
+		los-gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		/*
+		 * HW 1.0-1.1: Spansion S25FL128S1
+		 * HW 1.3: Winbond W25Q128
+		 *
+		 * Fast Read Data max speed is 50MHz, see the Winbond W25Q128
+		 * datasheet table 9.5 "AC Electrical Characteristics", we can
+		 * use this speed because the chip supports fast reads. Older
+		 * HW has different NOR chips, I assume they can all do fast
+		 * reads.
+		 */
+		spi-max-frequency = <104000000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+		m25p,fast-read;
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cfe: partition@0 {
+				label = "cfe";
+				reg = <0x0000000 0x0010000>;
+				read-only;
+			};
+
+			partition@10000 {
+				compatible = "openwrt,uimage", "denx,uimage";
+				reg = <0x010000 0xfe0000>;
+				label = "firmware";
+				openwrt,offset = <0x30000>;
+			};
+
+			partition@ff0000 {
+				reg = <0xff0000 0x010000>;
+				label = "nvram";
+			};
+		};
+	};
+};
+
+&cfe {
+	compatible = "nvmem-cells";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	macaddr_cfe_6a0: macaddr@6a0 {
+		reg = <0x6a0 0x6>;
+	};
+};
+
+&ethernet {
+	status = "okay";
+
+	nvmem-cells = <&macaddr_cfe_6a0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&switch0 {
+	dsa,member = <0 0>;
+
+	ports {
+		switch0port4: port@4 {
+			reg = <4>;
+			label = "extsw";
+
+			phy-mode = "rgmii";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&mdio_ext {
+	switch1: switch@0 {
+		/* The switch is not using any external IRQ, sadly */
+		compatible = "marvell,mv88e6085";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		dsa,member = <1 0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan1";
+				phy-handle = <&lan1phy>;
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan2";
+				phy-handle = <&lan2phy>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+				phy-handle = <&lan3phy>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan4";
+				phy-handle = <&lan4phy>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "ext1";
+				phy-handle = <&ext1phy>;
+			};
+
+			port@5 {
+				reg = <5>;
+				phy-mode = "rgmii-id";
+				label = "wan";
+				sfp = <&sfp0>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				phy-mode = "rgmii-id";
+				label = "cpu";
+				ethernet = <&switch0port4>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lan1phy: ethernet-phy@0 {
+				reg = <0>;
+				interrupt-parent = <&switch1>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan2phy: ethernet-phy@1 {
+				reg = <1>;
+				interrupt-parent = <&switch1>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan3phy: ethernet-phy@2 {
+				reg = <2>;
+				interrupt-parent = <&switch1>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			lan4phy: ethernet-phy@3 {
+				reg = <3>;
+				interrupt-parent = <&switch1>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+			ext1phy: ethernet-phy@4 {
+				reg = <4>;
+				interrupt-parent = <&switch1>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl_xg6846_usb_spd_led: xg6846_usb_spd_led-pins {
+		function = "led";
+		pins = "gpio17";
+	};
+};
+
+&leds {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_xg6846_usb_spd_led>, /* GPIO16 LED USB */
+		    <&pinctrl_ephy1_spd_led>, /* GPIO18 LED PWR red */
+		    <&pinctrl_ephy3_spd_led>; /* GPIO20 LED PWR green */
+
+	/* On board variants without USB this LED is not mounted */
+	led_usb_green: led@16 {
+		reg = <16>;
+		active-low;
+		label = "green:usb";
+		default-state = "off";
+	};
+
+	/*
+	 * LED 18 and 20 drive the same physical LED, the PWR
+	 * LED that can be both red and green.
+	 */
+	led_pwr_red: led@18 {
+		reg = <18>;
+		active-low;
+		label = "red:pwr";
+		default-state = "off";
+	};
+
+	led_pwr_green: led@20 {
+		reg = <20>;
+		active-low;
+		label = "green:pwr";
+		default-state = "off";
+	};
+
+};
diff --git a/target/linux/bmips/image/Makefile b/target/linux/bmips/image/Makefile
index 9311e2df09..b79974931d 100644
--- a/target/linux/bmips/image/Makefile
+++ b/target/linux/bmips/image/Makefile
@@ -4,6 +4,7 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/image.mk
 
 KERNEL_LOADADDR := 0x80010000		# RAM start + 64K
+UBOOT_ENTRY := 0x81c00000
 LOADER_ENTRY := 0x81000000		# RAM start + 16M, for relocate
 LZMA_TEXT_START := 0x82000000		# RAM start + 32M
 
@@ -94,6 +95,21 @@ define Build/cfe-bin
 		$(CFE_EXTRAS) $(1)
 endef
 
+# Build a CFE image with just U-Boot
+define Build/cfe-bin-uboot
+	cp $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.bin $@
+	$(call Build/lzma)
+	mv $@ $@.uboot.lzma
+	echo "dummy" > $@.dummyfs
+	$(STAGING_DIR_HOST)/bin/imagetag -i $@.uboot.lzma -f $@.dummyfs \
+		--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \
+		--entry $(UBOOT_ENTRY) --load-addr $(UBOOT_ENTRY) \
+		--info1 "$(call ModelNameLimit16,$(DEVICE_NAME))" \
+		$(CFE_EXTRAS) $(1)
+	rm $@.uboot.lzma
+	rm $@.dummyfs
+endef
+
 define Build/cfe-jffs2
 	$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
 		--big-endian \
@@ -284,6 +300,21 @@ define Device/bcm63xx-cfe-legacy
   KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe
 endef
 
+# CFE images with U-Boot in front of the kernel, these will execute
+# U-Boot instead of the kernel and U-Boot will then proceed to load
+# the kernel. The reason to do this is that CFE is sometimes unable to
+# load big kernels even with the lzma loader tricks.
+define Device/bcm63xx-cfe-uboot
+  $(Device/bcm63xx-cfe)
+  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma
+  IMAGE/cfe.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-rootfs $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2))
+  IMAGE/sysupgrade.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+    append-rootfs | append-metadata
+endef
+
 # CFE expects a single JFFS2 partition with cferam and kernel. However,
 # it's possible to fool CFE into properly loading both cferam and kernel
 # from two different JFFS2 partitions by adding dummy files (see
diff --git a/target/linux/bmips/image/bcm6328.mk b/target/linux/bmips/image/bcm6328.mk
index b28926b1e7..b85b6ac7a8 100644
--- a/target/linux/bmips/image/bcm6328.mk
+++ b/target/linux/bmips/image/bcm6328.mk
@@ -51,6 +51,20 @@ define Device/innacomm_w3400v6
 endef
 TARGET_DEVICES += innacomm_w3400v6
 
+define Device/inteno_xg6846
+  $(Device/bcm63xx-cfe-uboot)
+  DEVICE_VENDOR := Inteno
+  DEVICE_MODEL := XG6846
+  CHIP_ID := 6328
+  CFE_BOARD_ID := 96328avng
+  FLASH_MB := 16
+  DEVICE_PACKAGES := $(USB2_PACKAGES) \
+    kmod-i2c-core kmod-i2c-gpio \
+    kmod-leds-bcm6328 kmod-dsa-mv88e6xxx \
+    kmod-sfp
+endef
+TARGET_DEVICES += inteno_xg6846
+
 define Device/nucom_r5010unv2
   $(Device/bcm63xx-cfe)
   DEVICE_VENDOR := NuCom
diff --git a/target/linux/d1/Makefile b/target/linux/d1/Makefile
index 69e28d4811..a60af57afa 100644
--- a/target/linux/d1/Makefile
+++ b/target/linux/d1/Makefile
@@ -11,7 +11,7 @@ FEATURES:=ext4 squashfs
 KERNELNAME:=Image dtbs
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/d1/config-6.1 b/target/linux/d1/config-6.1
deleted file mode 100644
index ef2112f706..0000000000
--- a/target/linux/d1/config-6.1
+++ /dev/null
@@ -1,396 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMODEL_MEDANY=y
-# CONFIG_CMODEL_MEDLOW is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_DWMAC_SUNXI=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_ELF_CORE=y
-# CONFIG_ERRATA_SIFIVE is not set
-CONFIG_ERRATA_THEAD=y
-CONFIG_ERRATA_THEAD_CMO=y
-CONFIG_ERRATA_THEAD_PBMT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FAILOVER=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_OCORES=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-# CONFIG_LEDS_PWM_MULTICOLOR is not set
-# CONFIG_LEDS_SUN50I_A100 is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_SUN4I is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_AXP20X_I2C=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_SUN4I_GPADC is not set
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MMIOWB=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-# CONFIG_NONPORTABLE is not set
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SUNXI_SID=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DMA_DEFAULT_COHERENT=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xff60000000000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PAGE_TABLE_CHECK is not set
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_PGTABLE_LEVELS=5
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN50I_USB3=y
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SUN20I_D1=y
-# CONFIG_PINCTRL_SUN4I_A10 is not set
-# CONFIG_PINCTRL_SUN50I_A100 is not set
-# CONFIG_PINCTRL_SUN50I_A100_R is not set
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H616 is not set
-# CONFIG_PINCTRL_SUN50I_H616_R is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-# CONFIG_PINCTRL_SUN5I is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_H3_R is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PORTABLE=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-# CONFIG_PWM_CLK is not set
-# CONFIG_PWM_SIFIVE is not set
-# CONFIG_PWM_SUN4I is not set
-# CONFIG_PWM_SUN8I_V536 is not set
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_XILINX is not set
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_AXP20X is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_SUN20I=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RISCV=y
-CONFIG_RISCV_ALTERNATIVE=y
-CONFIG_RISCV_ALTERNATIVE_EARLY=y
-CONFIG_RISCV_BOOT_SPINWAIT=y
-CONFIG_RISCV_DMA_NONCOHERENT=y
-CONFIG_RISCV_INTC=y
-CONFIG_RISCV_ISA_C=y
-CONFIG_RISCV_ISA_SVPBMT=y
-CONFIG_RISCV_ISA_ZICBOM=y
-CONFIG_RISCV_SBI=y
-CONFIG_RISCV_SBI_V01=y
-CONFIG_RISCV_TIMER=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_EFI is not set
-CONFIG_RTC_DRV_GOLDFISH=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SMP=y
-# CONFIG_SND_SUN20I_CODEC is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
-# CONFIG_SOC_SIFIVE is not set
-# CONFIG_SOC_STARFIVE is not set
-# CONFIG_SOC_VIRT is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_SUN4I is not set
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SUN20I_D1_CCU=y
-CONFIG_SUN20I_D1_R_CCU=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_SUN6I_MSGBOX=y
-CONFIG_SUN6I_RTC_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-# CONFIG_SUN8I_R_CCU is not set
-# CONFIG_SUN8I_THERMAL is not set
-CONFIG_SUNXI_CCU=y
-# CONFIG_SUNXI_RSB is not set
-CONFIG_SUNXI_SRAM=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOOLCHAIN_HAS_ZICBOM=y
-CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
-CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TUNE_GENERIC=y
-# CONFIG_UACCE is not set
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_HID=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-# CONFIG_VHOST_MENU is not set
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/d1/config-6.6 b/target/linux/d1/config-6.6
new file mode 100644
index 0000000000..957c3fba4d
--- /dev/null
+++ b/target/linux/d1/config-6.6
@@ -0,0 +1,417 @@
+CONFIG_64BIT=y
+# CONFIG_ACPI is not set
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUNXI=y
+# CONFIG_ARCH_THEAD is not set
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+# CONFIG_AX45MP_L2_CACHE is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMODEL_MEDANY=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_DWMAC_SUNXI=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ERRATA_ANDES is not set
+# CONFIG_ERRATA_SIFIVE is not set
+CONFIG_ERRATA_THEAD=y
+CONFIG_ERRATA_THEAD_CMO=y
+CONFIG_ERRATA_THEAD_PBMT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FAILOVER=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPU=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_OCORES=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_STACKS=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+# CONFIG_LEDS_PWM_MULTICOLOR is not set
+# CONFIG_LEDS_SUN50I_A100 is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_SUN4I is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_SUN4I_GPADC is not set
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMIOWB=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+# CONFIG_NONPORTABLE is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+# CONFIG_PHY_SUN9I_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SUN20I_D1=y
+# CONFIG_PINCTRL_SUN4I_A10 is not set
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+# CONFIG_PINCTRL_SUN5I is not set
+# CONFIG_PINCTRL_SUN6I_A31 is not set
+# CONFIG_PINCTRL_SUN6I_A31_R is not set
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN8I_A33 is not set
+# CONFIG_PINCTRL_SUN8I_A83T is not set
+# CONFIG_PINCTRL_SUN8I_A83T_R is not set
+# CONFIG_PINCTRL_SUN8I_H3 is not set
+# CONFIG_PINCTRL_SUN8I_H3_R is not set
+# CONFIG_PINCTRL_SUN8I_V3S is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+# CONFIG_PINCTRL_SUN9I_A80_R is not set
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_SIFIVE is not set
+# CONFIG_PWM_SUN4I is not set
+# CONFIG_PWM_SUN8I_V536 is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_XILINX is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AXP20X is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_SUN20I=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RISCV=y
+CONFIG_RISCV_ALTERNATIVE=y
+CONFIG_RISCV_ALTERNATIVE_EARLY=y
+CONFIG_RISCV_BOOT_SPINWAIT=y
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_FALLBACK=y
+CONFIG_RISCV_ISA_SVNAPOT=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_V=y
+CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
+CONFIG_RISCV_ISA_ZBB=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_ISA_ZICBOZ=y
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_SBI_V01=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+# CONFIG_SND_SUN20I_CODEC is not set
+# CONFIG_SND_SUN20I_D1_CODEC_ANALOG is not set
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
+# CONFIG_SOC_SIFIVE is not set
+# CONFIG_SOC_STARFIVE is not set
+# CONFIG_SOC_VIRT is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_SUN4I is not set
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_SUN20I_GPADC=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+# CONFIG_SUN8I_R_CCU is not set
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUNXI_CCU=y
+# CONFIG_SUNXI_RSB is not set
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SIZE_ORDER=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_HAS_ZICBOM=y
+CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUNE_GENERIC=y
+# CONFIG_UACCE is not set
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_HID=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VHOST_MENU is not set
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch b/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch
deleted file mode 100644
index 6636cddde6..0000000000
--- a/target/linux/d1/patches-6.1/0001-dt-bindings-net-bluetooth-realtek-Add-RTL8723DS.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 24 Jul 2022 17:12:07 -0500
-Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS
-
-RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is
-already supported by the hci_uart/btrtl driver. Document the compatible.
-
-Series-to: Marcel Holtmann <marcel@holtmann.org>
-Series-to: Johan Hedberg <johan.hedberg@gmail.com>
-Series-to: Luiz Augusto von Dentz <luiz.dentz@gmail.com>
-Series-to: David S. Miller <davem@davemloft.net>
-Series-to: Eric Dumazet <edumazet@google.com>
-Series-to: Jakub Kicinski <kuba@kernel.org>
-Series-to: Paolo Abeni <pabeni@redhat.com>
-Series-cc: linux-bluetooth@vger.kernel.org
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
-+++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
-@@ -20,6 +20,7 @@ properties:
-     enum:
-       - realtek,rtl8723bs-bt
-       - realtek,rtl8723cs-bt
-+      - realtek,rtl8723ds-bt
-       - realtek,rtl8822cs-bt
- 
-   device-wake-gpios:
diff --git a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch b/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch
deleted file mode 100644
index 22d4885e29..0000000000
--- a/target/linux/d1/patches-6.1/0002-clk-sunxi-ng-mp-Avoid-computing-the-rate-twice.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 20:08:49 -0500
-Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice
-
-ccu_mp_find_best() already computes a best_rate at the same time as the
-best m and p factors. Return it so the caller does not need to duplicate
-the division.
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++-----
- 1 file changed, 6 insertions(+), 5 deletions(-)
-
---- a/drivers/clk/sunxi-ng/ccu_mp.c
-+++ b/drivers/clk/sunxi-ng/ccu_mp.c
-@@ -10,9 +10,9 @@
- #include "ccu_gate.h"
- #include "ccu_mp.h"
- 
--static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
--			     unsigned int max_m, unsigned int max_p,
--			     unsigned int *m, unsigned int *p)
-+static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
-+				      unsigned int max_m, unsigned int max_p,
-+				      unsigned int *m, unsigned int *p)
- {
- 	unsigned long best_rate = 0;
- 	unsigned int best_m = 0, best_p = 0;
-@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo
- 
- 	*m = best_m;
- 	*p = best_p;
-+
-+	return best_rate;
- }
- 
- static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
-@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s
- 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
- 
- 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
--		ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
--		rate = *parent_rate / p / m;
-+		rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
- 	} else {
- 		rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
- 							max_m, max_p);
diff --git a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch b/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch
deleted file mode 100644
index ec3f553b51..0000000000
--- a/target/linux/d1/patches-6.1/0003-dt-bindings-net-sun8i-emac-Add-phy-supply-property.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 5 Sep 2022 16:45:44 -0500
-Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml     | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-@@ -40,6 +40,9 @@ properties:
-   clock-names:
-     const: stmmaceth
- 
-+  phy-supply:
-+    description: PHY regulator
-+
-   syscon:
-     $ref: /schemas/types.yaml#/definitions/phandle
-     description:
diff --git a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch b/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch
deleted file mode 100644
index 9ac335ae3e..0000000000
--- a/target/linux/d1/patches-6.1/0004-dt-bindings-net-sun8i-emac-Add-properties-from-dwmac.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 5 Sep 2022 16:46:34 -0500
-Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from
- dwmac binding
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml   | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-@@ -40,6 +40,9 @@ properties:
-   clock-names:
-     const: stmmaceth
- 
-+  resets: true
-+  reset-names: true
-+
-   phy-supply:
-     description: PHY regulator
- 
-@@ -49,6 +52,8 @@ properties:
-       Phandle to the device containing the EMAC or GMAC clock
-       register
- 
-+  mdio: true
-+
- required:
-   - compatible
-   - reg
diff --git a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch b/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch
deleted file mode 100644
index 402f291674..0000000000
--- a/target/linux/d1/patches-6.1/0005-dt-bindings-display-sun8i-a83t-dw-hdmi-Remove-phy-ce.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Aug 2022 10:45:59 -0500
-Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove
- #phy-cells
-
-This device is not a PHY, and none of the nodes using this schema
-contain a #phy-cells property. Likely this was a copy/paste error
-introduced during the YAML conversion.
-
-Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml         | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-@@ -20,9 +20,6 @@ maintainers:
-   - Maxime Ripard <mripard@kernel.org>
- 
- properties:
--  "#phy-cells":
--    const: 0
--
-   compatible:
-     oneOf:
-       - const: allwinner,sun8i-a83t-dw-hdmi
diff --git a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch b/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch
deleted file mode 100644
index b62e45c09f..0000000000
--- a/target/linux/d1/patches-6.1/0006-dt-bindings-display-Add-D1-HDMI-compatibles.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 31 Mar 2022 23:43:15 -0500
-Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles
-
-Allwinner D1 contains a DesignWare HDMI controller with some changes in
-platform integration, and a new HDMI PHY. Add their compatibles.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml           | 1 +
- .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml          | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-@@ -29,6 +29,7 @@ properties:
-           - enum:
-               - allwinner,sun8i-h3-dw-hdmi
-               - allwinner,sun8i-r40-dw-hdmi
-+              - allwinner,sun20i-d1-dw-hdmi
-               - allwinner,sun50i-a64-dw-hdmi
-           - const: allwinner,sun8i-a83t-dw-hdmi
- 
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
-@@ -19,6 +19,7 @@ properties:
-       - allwinner,sun8i-a83t-hdmi-phy
-       - allwinner,sun8i-h3-hdmi-phy
-       - allwinner,sun8i-r40-hdmi-phy
-+      - allwinner,sun20i-d1-hdmi-phy
-       - allwinner,sun50i-a64-hdmi-phy
-       - allwinner,sun50i-h6-hdmi-phy
- 
diff --git a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch b/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch
deleted file mode 100644
index b55c3a3f20..0000000000
--- a/target/linux/d1/patches-6.1/0007-drm-sun4i-Add-support-for-D1-HDMI.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 30 Mar 2022 21:24:21 -0500
-Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI
-
-D1's HDMI controller contains some platform integration changes.
-It now has no external TMDS clock. The controller also supports HDCP
-without an external clock or reset.
-
-While the maximum HDMI frequency is not explicity stated, the BSP PHY
-driver provides PLL configurations only up to 297 MHz, so use that as
-the max frequency.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
-@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev
- 		return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
- 				     "Could not get ctrl reset control\n");
- 
--	hdmi->clk_tmds = devm_clk_get(dev, "tmds");
-+	hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds");
- 	if (IS_ERR(hdmi->clk_tmds))
- 		return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
- 				     "Couldn't get the tmds clock\n");
-@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks
- 	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
- };
- 
-+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = {
-+	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
-+	.use_drm_infoframe = true,
-+};
-+
- static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
- 	.mode_valid = sun8i_dw_hdmi_mode_valid_h6,
- 	.use_drm_infoframe = true,
-@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d
- 		.data = &sun8i_a83t_quirks,
- 	},
- 	{
-+		.compatible = "allwinner,sun20i-d1-dw-hdmi",
-+		.data = &sun20i_d1_quirks,
-+	},
-+	{
- 		.compatible = "allwinner,sun50i-h6-dw-hdmi",
- 		.data = &sun50i_h6_quirks,
- 	},
diff --git a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch b/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch
deleted file mode 100644
index e8007cc5c4..0000000000
--- a/target/linux/d1/patches-6.1/0008-drm-sun4i-sun8i-hdmi-phy-Add-support-for-D1-PHY.patch
+++ /dev/null
@@ -1,251 +0,0 @@
-From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 3 Apr 2022 15:15:41 -0500
-Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  | 169 +++++++++++++++++++++++++
- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c |  32 +++++
- 2 files changed, 201 insertions(+)
-
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-@@ -145,6 +145,175 @@
- 
- #define SUN8I_HDMI_PHY_CEC_REG		0x003c
- 
-+#define SUN20I_HDMI_PHY_CTL0_REG	0x0040
-+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN	BIT(31)
-+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE	BIT(30)
-+#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN	BIT(29)
-+#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS	BIT(28)
-+#define SUN20I_HDMI_PHY_CTL0_ENTX		GENMASK(27, 24)
-+#define SUN20I_HDMI_PHY_CTL0_ENBI		GENMASK(23, 20)
-+#define SUN20I_HDMI_PHY_CTL0_ENLDO		BIT(18)
-+#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS		BIT(17)
-+#define SUN20I_HDMI_PHY_CTL0_ENCK		BIT(16)
-+#define SUN20I_HDMI_PHY_CTL0_REG_PLR		GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL0_REG_DEN		GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS		GENMASK(7, 6)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL	BIT(5)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL		BIT(4)
-+#define SUN20I_HDMI_PHY_CTL0_HPD_EN		BIT(2)
-+#define SUN20I_HDMI_PHY_CTL0_SCL_EN		BIT(1)
-+#define SUN20I_HDMI_PHY_CTL0_SDA_EN		BIT(0)
-+
-+#define SUN20I_HDMI_PHY_CTL1_REG	0x0044
-+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN	BIT(31)
-+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE	BIT(30)
-+#define SUN20I_HDMI_PHY_CTL1_RES_S		GENMASK(29, 28)
-+#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS	BIT(27)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SWI		BIT(26)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SVR		GENMASK(25, 24)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST2		GENMASK(21, 20)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST1		GENMASK(19, 18)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST0		GENMASK(17, 16)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3		GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2		GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1		GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0		GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL2_REG	0x0048
-+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN	BIT(31)
-+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE		BIT(30)
-+#define SUN20I_HDMI_PHY_CTL2_REG_RESDI		GENMASK(29, 24)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3		GENMASK(23, 19)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2		GENMASK(18, 14)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1		GENMASK(13, 9)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0		GENMASK(8, 4)
-+#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT		GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL3_REG	0x004c
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_3		GENMASK(31, 28)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_2		GENMASK(27, 24)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_1		GENMASK(23, 20)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_0		GENMASK(19, 16)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC3		GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC2		GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC1		GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC0		GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL4_REG	0x0050
-+#define SUN20I_HDMI_PHY_CTL4_REG_SLV		GENMASK(31, 29)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_3		GENMASK(28, 24)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_2		GENMASK(20, 16)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_1		GENMASK(12, 8)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_0		GENMASK(4, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL5_REG	0x0054
-+#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT		GENMASK(19, 16)
-+#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT	BIT(12)
-+#define SUN20I_HDMI_PHY_CTL5_REG_CALSW		BIT(11)
-+#define SUN20I_HDMI_PHY_CTL5_ENRESCK		BIT(10)
-+#define SUN20I_HDMI_PHY_CTL5_ENRES		BIT(9)
-+#define SUN20I_HDMI_PHY_CTL5_ENRCAL		BIT(8)
-+#define SUN20I_HDMI_PHY_CTL5_ENP2S		GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL5_ENIB		BIT(1)
-+#define SUN20I_HDMI_PHY_CTL5_ENCALOG		BIT(0)
-+
-+#define SUN20I_HDMI_PLL_CTL0_REG	0x0058
-+#define SUN20I_HDMI_PLL_CTL0_CKO_SEL		GENMASK(31, 30)
-+#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL	BIT(29)
-+#define SUN20I_HDMI_PLL_CTL0_ENVBS		BIT(28)
-+#define SUN20I_HDMI_PLL_CTL0_SLV		GENMASK(26, 24)
-+#define SUN20I_HDMI_PLL_CTL0_BCR		BIT(23)
-+#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH	BIT(22)
-+#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH		GENMASK(21, 20)
-+#define SUN20I_HDMI_PLL_CTL0_CUTFB		BIT(18)
-+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT		BIT(17)
-+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS	BIT(16)
-+#define SUN20I_HDMI_PLL_CTL0_DIV_PRE		GENMASK(15, 12)
-+#define SUN20I_HDMI_PLL_CTL0_DIVX1		BIT(10)
-+#define SUN20I_HDMI_PLL_CTL0_SDRVEN		BIT(9)
-+#define SUN20I_HDMI_PLL_CTL0_VCORANGE		BIT(8)
-+#define SUN20I_HDMI_PLL_CTL0_N_CNTRL		GENMASK(7, 6)
-+#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL		GENMASK(5, 4)
-+#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL		GENMASK(2, 0)
-+
-+#define SUN20I_HDMI_PLL_CTL1_REG	0x005c
-+#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC	BIT(31)
-+#define SUN20I_HDMI_PLL_CTL1_PCNT_N		GENMASK(27, 20)
-+#define SUN20I_HDMI_PLL_CTL1_PCNT_EN		BIT(19)
-+#define SUN20I_HDMI_PLL_CTL1_SDM_EN		BIT(18)
-+#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP		GENMASK(17, 16)
-+#define SUN20I_HDMI_PLL_CTL1_PWRON		BIT(12)
-+#define SUN20I_HDMI_PLL_CTL1_RESET		BIT(11)
-+#define SUN20I_HDMI_PLL_CTL1_SCKREF		BIT(10)
-+#define SUN20I_HDMI_PLL_CTL1_SCKFB		BIT(9)
-+#define SUN20I_HDMI_PLL_CTL1_DRV_ANA		BIT(8)
-+#define SUN20I_HDMI_PLL_CTL1_FAST_TECH		BIT(7)
-+#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT		BIT(6)
-+#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL		GENMASK(5, 4)
-+#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL		GENMASK(2, 0)
-+
-+#define SUN20I_HDMI_AFIFO_CFG_REG	0x0060
-+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR	BIT(0)
-+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET	BIT(1)
-+
-+#define SUN20I_HDMI_MODULATOR_CFG0_REG	0x0064
-+#define SUN20I_HDMI_MODULATOR_CFG1_REG	0x0068
-+
-+#define SUN20I_HDMI_INDEB_CTRL_REG	0x006c
-+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE	BIT(29)
-+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG	BIT(28)
-+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE	BIT(25)
-+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG	BIT(24)
-+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE	BIT(21)
-+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG	BIT(20)
-+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE	BIT(17)
-+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG	BIT(16)
-+#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE	GENMASK(1, 0)
-+
-+#define SUN20I_HDMI_INDBG_TXD0_REG	0x0070
-+#define SUN20I_HDMI_INDBG_TXD1_REG	0x0074
-+#define SUN20I_HDMI_INDBG_TXD2_REG	0x0078
-+#define SUN20I_HDMI_INDBG_TXD3_REG	0x007c
-+
-+#define SUN20I_HDMI_PLL_STS_REG		0x0080
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS	BIT(31)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS	GENMASK(30, 28)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS	BIT(27)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS	GENMASK(26, 24)
-+#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS	BIT(23)
-+#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS	BIT(22)
-+#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS	BIT(21)
-+#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS	BIT(20)
-+#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS	BIT(17)
-+#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS	BIT(16)
-+#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS	GENMASK(13, 8)
-+#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS	BIT(4)
-+#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS	BIT(1)
-+#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS	BIT(0)
-+
-+#define SUN20I_HDMI_PRBS_CTL_REG	0x0084
-+#define SUN20I_HDMI_PRBS_SEED_GEN_REG	0x0088
-+#define SUN20I_HDMI_PRBS_SEED_CHK_REG	0x008c
-+#define SUN20I_HDMI_PRBS_SEED_NUM_REG	0x0090
-+#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG	0x0094
-+
-+#define SUN20I_HDMI_PLL_ODLY_REG	0x0098
-+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET	BIT(31)
-+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT	GENMASK(30, 16)
-+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET	BIT(15)
-+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT	GENMASK(14, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL6_REG	0x009c
-+#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA	BIT(31)
-+#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT		BIT(30)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M	GENMASK(29, 20)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M	GENMASK(19, 10)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M	GENMASK(9, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL7_REG	0x00a0
-+#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M	GENMASK(21, 12)
-+#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M	GENMASK(9, 0)
-+
- struct sun8i_hdmi_phy;
- 
- struct sun8i_hdmi_phy_variant {
---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8
- 	.setup_hpd	= dw_hdmi_phy_setup_hpd,
- };
- 
-+static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
-+				     const struct drm_display_info *display,
-+				     const struct drm_display_mode *mode)
-+{
-+	struct sun8i_hdmi_phy *phy = data;
-+
-+	return 0;
-+}
-+
-+static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
-+{
-+	struct sun8i_hdmi_phy *phy = data;
-+}
-+
-+static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = {
-+	.init		= sun20i_d1_hdmi_phy_config,
-+	.disable	= sun20i_d1_hdmi_phy_disable,
-+	.read_hpd	= dw_hdmi_phy_read_hpd,
-+	.update_hpd	= dw_hdmi_phy_update_hpd,
-+	.setup_hpd	= dw_hdmi_phy_setup_hpd,
-+};
-+
- static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
- {
- 	/* enable read access to HDMI controller */
-@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i
- 	const struct sun8i_hdmi_phy_variant *variant = phy->variant;
- 
- 	if (variant->phy_ops) {
-+		plat_data->phy_force_vendor = true;
- 		plat_data->phy_ops = variant->phy_ops;
- 		plat_data->phy_name = "sun8i_dw_hdmi_phy";
- 		plat_data->phy_data = phy;
-@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia
- 	.phy_init = &sun8i_hdmi_phy_init_h3,
- };
- 
-+static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = {
-+	.phy_ops = &sun20i_d1_hdmi_phy_ops,
-+	.phy_init = &sun50i_hdmi_phy_init_h6,
-+};
-+
- static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
- 	.has_phy_clk = true,
- 	.phy_ops = &sun8i_h3_hdmi_phy_ops,
-@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h
- 		.data = &sun8i_r40_hdmi_phy,
- 	},
- 	{
-+		.compatible = "allwinner,sun20i-d1-hdmi-phy",
-+		.data = &sun20i_d1_hdmi_phy,
-+	},
-+	{
- 		.compatible = "allwinner,sun50i-a64-hdmi-phy",
- 		.data = &sun50i_a64_hdmi_phy,
- 	},
diff --git a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch b/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch
deleted file mode 100644
index 85c81d5057..0000000000
--- a/target/linux/d1/patches-6.1/0009-drm-sun4i-Copy-in-BSP-code-for-D1-HDMI-PHY.patch
+++ /dev/null
@@ -1,621 +0,0 @@
-From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 30 Mar 2022 00:46:07 -0500
-Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/aw_phy.h         | 411 +++++++++++++++++++++++++
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h  |   1 +
- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++
- 3 files changed, 568 insertions(+)
- create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h
-
---- /dev/null
-+++ b/drivers/gpu/drm/sun4i/aw_phy.h
-@@ -0,0 +1,411 @@
-+/*
-+ * Allwinner SoCs hdmi2.0 driver.
-+ *
-+ * Copyright (C) 2016 Allwinner.
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2.  This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef AW_PHY_H_
-+#define AW_PHY_H_
-+
-+#define AW_PHY_TIMEOUT	1000
-+#define LOCK_TIMEOUT	100
-+
-+/* allwinner phy register offset */
-+#define HDMI_PHY_CTL0				0x40
-+#define HDMI_PHY_CTL1				0x44
-+#define HDMI_PHY_CTL2				0x48
-+#define HDMI_PHY_CTL3				0x4C
-+#define HDMI_PHY_CTL4				0x50
-+#define HDMI_PHY_CTL5				0x54
-+#define HDMI_PLL_CTL0				0x58
-+#define HDMI_PLL_CTL1				0x5C
-+#define HDMI_AFIFO_CFG				0x60
-+#define HDMI_MODULATOR_CFG0			0x64
-+#define HDMI_MODULATOR_CFG1			0x68
-+#define HDMI_PHY_INDEB_CTRL			0x6C
-+#define HDMI_PHY_INDBG_TXD0			0x70
-+#define HDMI_PHY_INDBG_TXD1			0x74
-+#define HDMI_PHY_INDBG_TXD2			0x78
-+#define HDMI_PHY_INDBG_TXD3			0x7C
-+#define HDMI_PHY_PLL_STS			0x80
-+#define HDMI_PRBS_CTL				0x84
-+#define HDMI_PRBS_SEED_GEN			0x88
-+#define HDMI_PRBS_SEED_CHK			0x8C
-+#define HDMI_PRBS_SEED_NUM			0x90
-+#define HDMI_PRBS_CYCLE_NUM			0x94
-+#define HDMI_PHY_PLL_ODLY_CFG			0x98
-+#define HDMI_PHY_CTL6				0x9C
-+#define HDMI_PHY_CTL7				0xA0
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 sda_en		:1;    // Default: 0;
-+		u32 scl_en		:1;    // Default: 0;
-+		u32 hpd_en		:1;    // Default: 0;
-+		u32 res0		:1;    // Default: 0;
-+		u32 reg_ck_sel		:1;    // Default: 1;
-+		u32 reg_ck_test_sel	:1;    // Default: 1;
-+		u32 reg_csmps		:2;    // Default: 0;
-+		u32 reg_den		:4;    // Default: F;
-+		u32 reg_plr		:4;    // Default: 0;
-+		u32 enck		:1;    // Default: 1;
-+		u32 enldo_fs		:1;    // Default: 1;
-+		u32 enldo		:1;    // Default: 1;
-+		u32 res1		:1;    // Default: 1;
-+		u32 enbi		:4;    // Default: F;
-+		u32 entx		:4;    // Default: F;
-+		u32 async_fifo_autosync_disable	:1;    // Default: 0;
-+		u32 async_fifo_workc_enable	:1;    // Default: 1;
-+		u32 phy_pll_lock_mode		:1;    // Default: 1;
-+		u32 phy_pll_lock_mode_man	:1;    // Default: 1;
-+	} bits;
-+} HDMI_PHY_CTL0_t;      //===========================    0x0040
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 reg_sp2_0				:   4  ;    // Default: 0;
-+		u32 reg_sp2_1				:   4  ;    // Default: 0;
-+		u32 reg_sp2_2				:   4  ;    // Default: 0;
-+		u32 reg_sp2_3				:   4  ;    // Default: 0;
-+		u32 reg_bst0				:   2  ;    // Default: 3;
-+		u32 reg_bst1				:   2  ;    // Default: 3;
-+		u32 reg_bst2				:   2  ;    // Default: 3;
-+		u32 res0				:   2  ;    // Default: 0;
-+		u32 reg_svr				:   2  ;    // Default: 2;
-+		u32 reg_swi				:   1  ;    // Default: 0;
-+		u32 res_scktmds				:   1  ;    // Default: 0;
-+		u32 res_res_s				:   2  ;    // Default: 3;
-+		u32 phy_rxsense_mode			:   1  ;    // Default: 0;
-+		u32 res_rxsense_mode_man		:   1  ;    // Default: 0;
-+	} bits;
-+} HDMI_PHY_CTL1_t;      //=====================================================    0x0044
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 reg_p2opt				:   4  ;    // Default: 0;
-+		u32 reg_sp1_0				:   5  ;    // Default: 0;
-+		u32 reg_sp1_1				:   5  ;    // Default: 0;
-+		u32 reg_sp1_2				:   5  ;    // Default: 0;
-+		u32 reg_sp1_3				:   5  ;    // Default: 0;
-+		u32 reg_resdi				:   6  ;    // Default: 18;
-+		u32 phy_hpdo_mode			:   1  ;    // Default: 0;
-+		u32 phy_hpdo_mode_man			:   1  ;    // Default: 0;
-+	} bits;
-+} HDMI_PHY_CTL2_t;      //=====================================================    0x0048
-+
-+
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 reg_mc0				:   4  ;    // Default: F;
-+		u32 reg_mc1				:   4  ;    // Default: F;
-+		u32 reg_mc2				:   4  ;    // Default: F;
-+		u32 reg_mc3				:   4  ;    // Default: F;
-+		u32 reg_p2_0				:   4  ;    // Default: F;
-+		u32 reg_p2_1				:   4  ;    // Default: F;
-+		u32 reg_p2_2				:   4  ;    // Default: F;
-+		u32 reg_p2_3				:   4  ;    // Default: F;
-+	} bits;
-+} HDMI_PHY_CTL3_t;      //=====================================================    0x004C
-+
-+
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 reg_p1_0				:   5  ;    // Default: 0x10;
-+		u32 res0				:   3  ;    // Default: 0;
-+		u32 reg_p1_1				:   5  ;    // Default: 0x10;
-+		u32 res1				:   3  ;    // Default: 0;
-+		u32 reg_p1_2				:   5  ;    // Default: 0x10;
-+		u32 res2				:   3  ;    // Default: 0;
-+		u32 reg_p1_3				:   5  ;    // Default: 0x10;
-+		u32 reg_slv				:   3  ;    // Default: 0;
-+	} bits;
-+} HDMI_PHY_CTL4_t;      //=====================================================    0x0050
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 encalog				:   1  ;    // Default: 0x1;
-+		u32 enib				:   1  ;    // Default: 0x1;
-+		u32 res0				:   2  ;    // Default: 0;
-+		u32 enp2s				:   4  ;    // Default: 0xF;
-+		u32 enrcal				:   1  ;    // Default: 0x1;
-+		u32 enres				:   1  ;    // Default: 1;
-+		u32 enresck				:   1  ;    // Default: 1;
-+		u32 reg_calsw				:   1  ;    // Default: 0;
-+		u32 reg_ckpdlyopt			:   1  ;    // Default: 0;
-+		u32 res1				:   3  ;    // Default: 0;
-+		u32 reg_p1opt				:   4  ;    // Default: 0;
-+		u32 res2				:  12  ;    // Default: 0;
-+	} bits;
-+} HDMI_PHY_CTL5_t;      //=====================================================    0x0054
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prop_cntrl				:   3  ;    // Default: 0x7;
-+		u32 res0				:   1  ;    // Default: 0;
-+		u32 gmp_cntrl				:   2  ;    // Default: 1;
-+		u32 n_cntrl				:   2  ;    // Default: 0;
-+		u32 vcorange				:   1  ;    // Default: 0;
-+		u32 sdrven				:   1  ;    // Default: 0;
-+		u32 divx1				:   1  ;    // Default: 0;
-+		u32 res1				:   1  ;    // Default: 0;
-+		u32 div_pre				:   4  ;    // Default: 0;
-+		u32 div2_cktmds				:   1  ;    // Default: 1;
-+		u32 div2_ckbit				:   1  ;    // Default: 1;
-+		u32 cutfb				:   1  ;    // Default: 0;
-+		u32 res2				:   1  ;    // Default: 0;
-+		u32 clr_dpth				:   2  ;    // Default: 0;
-+		u32 bypass_clrdpth			:   1  ;    // Default: 0;
-+		u32 bcr					:   1  ;    // Default: 0;
-+		u32 slv					:   3  ;    // Default: 4;
-+		u32 res3				:   1  ;    // Default: 0;
-+		u32 envbs				:   1  ;    // Default: 0;
-+		u32 bypass_ppll				:   1  ;    // Default: 0;
-+		u32 cko_sel				:   2  ;    // Default: 0;
-+	} bits;
-+} HDMI_PLL_CTL0_t;      //=====================================================    0x0058
-+
-+
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 int_cntrl				:   3  ;    // Default: 0x0;
-+		u32 res0				:   1  ;    // Default: 0;
-+		u32 ref_cntrl				:   2  ;    // Default: 3;
-+		u32 gear_shift				:   1  ;    // Default: 0;
-+		u32 fast_tech				:   1  ;    // Default: 0;
-+		u32 drv_ana				:   1  ;    // Default: 1;
-+		u32 sckfb				:   1  ;    // Default: 0;
-+		u32 sckref				:   1  ;    // Default: 0;
-+		u32 reset				:   1  ;    // Default: 0;
-+		u32 pwron				:   1  ;    // Default: 0;
-+		u32 res1				:   3  ;    // Default: 0;
-+		u32 pixel_rep				:   2  ;    // Default: 0;
-+		u32 sdm_en				:   1  ;    // Default: 0;
-+		u32 pcnt_en				:   1  ;    // Default: 0;
-+		u32 pcnt_n				:   8  ;    // Default: 0xE;
-+		u32 res2				:   3  ;    // Default: 0;
-+		u32 ctrl_modle_clksrc			:   1  ;    // Default: 0;
-+	} bits;
-+} HDMI_PLL_CTL1_t;      //=====================================================    0x005C
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 hdmi_afifo_error	:   1  ;    // Default: 0x0;
-+		u32 hdmi_afifo_error_det	:   1  ;    // Default: 0x0;
-+		u32 res0			:  30  ;    // Default: 0;
-+	} bits;
-+} HDMI_AFIFO_CFG_t;      //=====================================================    0x0060
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 fnpll_mash_en		:   1  ;    // Default: 0x0;
-+		u32 fnpll_mash_mod		:   2  ;    // Default: 0x0;
-+		u32 fnpll_mash_stp		:   9  ;    // Default: 0x0;
-+		u32 fnpll_mash_m12		:   1  ;    // Default: 0x0;
-+		u32 fnpll_mash_frq		:   2  ;    // Default: 0x0;
-+		u32 fnpll_mash_bot		:  17  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_MODULATOR_CFG0_t;      //=====================================================    0x0064
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 fnpll_mash_dth		:   1  ;    // Default: 0x0;
-+		u32 fnpll_mash_fen		:   1  ;    // Default: 0x0;
-+		u32 fnpll_mash_frc		:  17  ;    // Default: 0x0;
-+		u32 fnpll_mash_fnv		:   8  ;    // Default: 0x0;
-+		u32 res0			:   5  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_MODULATOR_CFG1_t;      //=====================================================    0x0068
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 txdata_debugmode		:   2  ;    // Default: 0x0;
-+		u32 res0			:  14  ;    // Default: 0x0;
-+		u32 ceci_debug			:   1  ;    // Default: 0x0;
-+		u32 ceci_debugmode		:   1  ;    // Default: 0x0;
-+		u32 res1			:   2  ;    // Default: 0x0;
-+		u32 sdai_debug			:   1  ;    // Default: 0x0;
-+		u32 sdai_debugmode		:   1  ;    // Default: 0x0;
-+		u32 res2			:   2  ;    // Default: 0x0;
-+		u32 scli_debug			:   1  ;    // Default: 0x0;
-+		u32 scli_debugmode		:   1  ;    // Default: 0x0;
-+		u32 res3			:   2  ;    // Default: 0x0;
-+		u32 hpdi_debug			:   1  ;    // Default: 0x0;
-+		u32 hpdi_debugmode		:   1  ;    // Default: 0x0;
-+		u32 res4			:   2  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_INDBG_CTRL_t;      //==================================================    0x006C
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 txdata0_debug_data	    :  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_INDBG_TXD0_t;      //==================================================    0x0070
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 txdata1_debug_data	    :  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_INDBG_TXD1_t;      //==================================================    0x0074
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 txdata2_debug_data	    :  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_INDBG_TXD2_t;      //==================================================    0x0078
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 txdata3_debug_data	    :  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_INDBG_TXD3_t;      //==================================================    0x007C
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 tx_ready_dly_status	:   1  ;    // Default: 0x0;
-+		u32 rxsense_dly_status		:   1  ;    // Default: 0x0;
-+		u32 res0			:   2  ;    // Default: 0x0;
-+		u32 pll_lock_status		:   1  ;    // Default: 0x0;
-+		u32 res1			:   3  ;    // Default: 0x0;
-+		u32 phy_resdo2d_status		:   6  ;    // Default: 0x0;
-+		u32 res2			:   2  ;    // Default: 0x0;
-+		u32 phy_rcalend2d_status	:   1  ;    // Default: 0x0;
-+		u32 phy_cout2d_status		:   1  ;    // Default: 0x0;
-+		u32 res3			:   2  ;    // Default: 0x0;
-+		u32 phy_ceco_status		:   1  ;    // Default: 0x0;
-+		u32 phy_sdao_status		:   1  ;    // Default: 0x0;
-+		u32 phy_sclo_status		:   1  ;    // Default: 0x0;
-+		u32 phy_hpdo_status		:   1  ;    // Default: 0x0;
-+		u32 phy_cdetn_status		:   3  ;    // Default: 0x0;
-+		u32 phy_cdetnck_status		:   1  ;    // Default: 0x0;
-+		u32 phy_cdetp_status		:   3  ;    // Default: 0x0;
-+		u32 phy_cdetpck_status		:   1  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_PLL_STS_t;      //=====================================================    0x0080
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prbs_en				:   1  ;    // Default: 0x0;
-+		u32 prbs_start				:   1  ;    // Default: 0x0;
-+		u32 prbs_seq_gen			:   1  ;    // Default: 0x0;
-+		u32 prbs_seq_chk			:   1  ;    // Default: 0x0;
-+		u32 prbs_mode				:   4  ;    // Default: 0x0;
-+		u32 prbs_type				:   2  ;    // Default: 0x0;
-+		u32 prbs_clk_pol			:   1  ;    // Default: 0x0;
-+		u32 res0				:  21  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PRBS_CTL_t;      //=====================================================    0x0084
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prbs_seed_gen			:  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PRBS_SEED_GEN_t;      //=================================================    0x0088
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prbs_seed_chk			:  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PRBS_SEED_CHK_t;      //=================================================    0x008C
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prbs_seed_num			:  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PRBS_SEED_NUM_t;      //=================================================    0x0090
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32 prbs_cycle_num			:  32  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PRBS_CYCLE_NUM_t;      //=================================================    0x0094
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32	tx_ready_dly_count		:  15  ;    // Default: 0x0;
-+		u32	tx_ready_dly_reset		:   1  ;    // Default: 0x0;
-+		u32	rxsense_dly_count		:  15  ;    // Default: 0x0;
-+		u32	rxsense_dly_reset		:   1  ;    // Default: 0x0;
-+	} bits;
-+} HDMI_PHY_PLL_ODLY_CFG_t;      //=================================================    0x0098
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32	clk_greate0_340m		:  10  ;    // Default: 0x3FF;
-+		u32	clk_greate1_340m		:  10  ;    // Default: 0x3FF;
-+		u32	clk_greate2_340m		:  10  ;    // Default: 0x3FF;
-+		u32	en_ckdat				:   1  ;    // Default: 0x3FF;
-+		u32	switch_clkch_data_corresponding	:   1  ;    // Default: 0x3FF;
-+	} bits;
-+} HDMI_PHY_CTL6_t;      //=========================================================    0x009C
-+
-+typedef union {
-+	u32 dwval;
-+	struct {
-+		u32	clk_greate3_340m		:  10  ;    // Default: 0x0;
-+		u32	res0				:   2  ;    // Default: 0x3FF;
-+		u32	clk_low_340m			:  10  ;    // Default: 0x3FF;
-+		u32	res1				:  10  ;    // Default: 0x3FF;
-+	} bits;
-+} HDMI_PHY_CTL7_t;      //=========================================================    0x00A0
-+
-+struct __aw_phy_reg_t {
-+	u32 res[16];		/* 0x0 ~ 0x3c */
-+	HDMI_PHY_CTL0_t		phy_ctl0; /* 0x0040 */
-+	HDMI_PHY_CTL1_t		phy_ctl1; /* 0x0044 */
-+	HDMI_PHY_CTL2_t		phy_ctl2; /* 0x0048 */
-+	HDMI_PHY_CTL3_t		phy_ctl3; /* 0x004c */
-+	HDMI_PHY_CTL4_t		phy_ctl4; /* 0x0050 */
-+	HDMI_PHY_CTL5_t		phy_ctl5; /* 0x0054 */
-+	HDMI_PLL_CTL0_t		pll_ctl0; /* 0x0058 */
-+	HDMI_PLL_CTL1_t		pll_ctl1; /* 0x005c */
-+	HDMI_AFIFO_CFG_t	afifo_cfg; /* 0x0060 */
-+	HDMI_MODULATOR_CFG0_t	modulator_cfg0; /* 0x0064 */
-+	HDMI_MODULATOR_CFG1_t	modulator_cfg1; /* 0x0068 */
-+	HDMI_PHY_INDBG_CTRL_t	phy_indbg_ctrl;	/* 0x006c */
-+	HDMI_PHY_INDBG_TXD0_t	phy_indbg_txd0; /* 0x0070 */
-+	HDMI_PHY_INDBG_TXD1_t	phy_indbg_txd1; /* 0x0074 */
-+	HDMI_PHY_INDBG_TXD2_t	phy_indbg_txd2; /* 0x0078 */
-+	HDMI_PHY_INDBG_TXD3_t	phy_indbg_txd3; /* 0x007c */
-+	HDMI_PHY_PLL_STS_t	phy_pll_sts; /* 0x0080 */
-+	HDMI_PRBS_CTL_t		prbs_ctl;	/* 0x0084 */
-+	HDMI_PRBS_SEED_GEN_t	prbs_seed_gen;	/* 0x0088 */
-+	HDMI_PRBS_SEED_CHK_t	prbs_seed_chk;	/* 0x008c */
-+	HDMI_PRBS_SEED_NUM_t	prbs_seed_num;	/* 0x0090 */
-+	HDMI_PRBS_CYCLE_NUM_t	prbs_cycle_num;	/* 0x0094 */
-+	HDMI_PHY_PLL_ODLY_CFG_t	phy_pll_odly_cfg; /* 0x0098 */
-+	HDMI_PHY_CTL6_t		phy_ctl6;	/* 0x009c */
-+	HDMI_PHY_CTL7_t		phy_ctl7;	/* 0x00A0 */
-+};
-+
-+#endif	/* AW_PHY_H_ */
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy {
- 	struct clk			*clk_pll1;
- 	struct device			*dev;
- 	unsigned int			rcal;
-+	void __iomem			*base;
- 	struct regmap			*regs;
- 	struct reset_control		*rst_phy;
- 	const struct sun8i_hdmi_phy_variant *variant;
---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-@@ -9,6 +9,8 @@
- 
- #include "sun8i_dw_hdmi.h"
- 
-+#include "aw_phy.h"
-+
- /*
-  * Address can be actually any value. Here is set to same value as
-  * it is set in BSP driver.
-@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8
- 	.setup_hpd	= dw_hdmi_phy_setup_hpd,
- };
- 
-+static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base)
-+{
-+	int i = 0, status = 0;
-+
-+	pr_info("enter %s\n", __func__);
-+
-+	//enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0]
-+	phy_base->phy_ctl4.bits.reg_slv = 4;     //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26]
-+	phy_base->phy_ctl5.bits.enib = 1;
-+	phy_base->phy_ctl0.bits.enldo = 1;
-+	phy_base->phy_ctl0.bits.enldo_fs = 1;
-+	phy_base->phy_ctl5.bits.enrcal = 1;
-+
-+	phy_base->phy_ctl5.bits.encalog = 1;
-+
-+	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+		udelay(5);
-+		status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status;
-+		if (status & 0x1) {
-+			pr_info("[%s]:phy_rcalend2d_status\n", __func__);
-+			break;
-+		}
-+	}
-+	if ((i == AW_PHY_TIMEOUT) && !status) {
-+		pr_err("phy_rcalend2d_status Timeout !\n");
-+		return -1;
-+	}
-+
-+	phy_base->phy_ctl0.bits.enbi = 0xF;
-+	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+		udelay(5);
-+		status = phy_base->phy_pll_sts.bits.pll_lock_status;
-+		if (status & 0x1) {
-+			pr_info("[%s]:pll_lock_status\n", __func__);
-+			break;
-+		}
-+	}
-+	if ((i == AW_PHY_TIMEOUT) && !status) {
-+		pr_err("pll_lock_status Timeout! status = 0x%x\n", status);
-+		return -1;
-+	}
-+
-+	phy_base->phy_ctl0.bits.enck = 1;
-+	phy_base->phy_ctl5.bits.enp2s = 0xF;
-+	phy_base->phy_ctl5.bits.enres = 1;
-+	phy_base->phy_ctl5.bits.enresck = 1;
-+	phy_base->phy_ctl0.bits.entx = 0xF;
-+
-+	for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+		udelay(5);
-+		status = phy_base->phy_pll_sts.bits.tx_ready_dly_status;
-+		if (status & 0x1) {
-+			pr_info("[%s]:tx_ready_status\n", __func__);
-+			break;
-+		}
-+	}
-+	if ((i == AW_PHY_TIMEOUT) && !status) {
-+		pr_err("tx_ready_status Timeout ! status = 0x%x\n", status);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
- static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
- 				     const struct drm_display_info *display,
- 				     const struct drm_display_mode *mode)
- {
- 	struct sun8i_hdmi_phy *phy = data;
-+	volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base;
-+	int ret;
-+
-+	pr_info("enter %s\n", __func__);
-+
-+	/* enable all channel */
-+	phy_base->phy_ctl5.bits.reg_p1opt = 0xF;
-+
-+	// phy_reset
-+	phy_base->phy_ctl0.bits.entx = 0;
-+	phy_base->phy_ctl5.bits.enresck = 0;
-+	phy_base->phy_ctl5.bits.enres = 0;
-+	phy_base->phy_ctl5.bits.enp2s = 0;
-+	phy_base->phy_ctl0.bits.enck = 0;
-+	phy_base->phy_ctl0.bits.enbi = 0;
-+	phy_base->phy_ctl5.bits.encalog = 0;
-+	phy_base->phy_ctl5.bits.enrcal = 0;
-+	phy_base->phy_ctl0.bits.enldo_fs = 0;
-+	phy_base->phy_ctl0.bits.enldo = 0;
-+	phy_base->phy_ctl5.bits.enib = 0;
-+	phy_base->pll_ctl1.bits.reset = 1;
-+	phy_base->pll_ctl1.bits.pwron = 0;
-+	phy_base->pll_ctl0.bits.envbs = 0;
-+
-+	// phy_set_mpll
-+	phy_base->pll_ctl0.bits.cko_sel = 0x3;
-+	phy_base->pll_ctl0.bits.bypass_ppll = 0x1;
-+	phy_base->pll_ctl1.bits.drv_ana = 1;
-+	phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video   1: MPLL
-+	phy_base->pll_ctl1.bits.sdm_en = 0x0;            //mpll sdm jitter is very large, not used for the time being
-+	phy_base->pll_ctl1.bits.sckref = 0;        //default value is 1
-+	phy_base->pll_ctl0.bits.slv = 4;
-+	phy_base->pll_ctl0.bits.prop_cntrl = 7;   //default value 7
-+	phy_base->pll_ctl0.bits.gmp_cntrl = 3;    //default value 1
-+	phy_base->pll_ctl1.bits.ref_cntrl = 0;
-+	phy_base->pll_ctl0.bits.vcorange = 1;
-+
-+	// phy_set_div
-+	phy_base->pll_ctl0.bits.div_pre = 0;      //div7 = n+1
-+	phy_base->pll_ctl1.bits.pcnt_en = 0;
-+	phy_base->pll_ctl1.bits.pcnt_n = 1;       //div6 = 1 (pcnt_en=0)    [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256
-+	phy_base->pll_ctl1.bits.pixel_rep = 0;    //div5 = n+1
-+	phy_base->pll_ctl0.bits.bypass_clrdpth = 0;
-+	phy_base->pll_ctl0.bits.clr_dpth = 0;     //div4 = 1 (bypass_clrdpth = 0)
-+	//00: 2    01: 2.5  10: 3   11: 4
-+	phy_base->pll_ctl0.bits.n_cntrl = 1;      //div
-+	phy_base->pll_ctl0.bits.div2_ckbit = 0;   //div1 = n+1
-+	phy_base->pll_ctl0.bits.div2_cktmds = 0;  //div2 = n+1
-+	phy_base->pll_ctl0.bits.bcr = 0;          //div3    0: [1:10]  1: [1:40]
-+	phy_base->pll_ctl1.bits.pwron = 1;
-+	phy_base->pll_ctl1.bits.reset = 0;
-+
-+	// configure phy
-+	/* config values taken from table */
-+	phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0);
-+	phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0);
-+	phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF);
-+	phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D);
-+	//phy_base->pll_ctl0.dwval |= config->pll_ctl0;
-+	//phy_base->pll_ctl1.dwval |= config->pll_ctl1;
-+
-+	// phy_set_clk
-+	phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0;
-+	phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF;
-+	phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF;
-+	phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0;
-+	phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0;
-+	phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0;
-+	phy_base->phy_ctl6.bits.en_ckdat = 1;       //default value is 0
-+
-+	// phy_base->phy_ctl2.bits.reg_resdi = 0x18;
-+	// phy_base->phy_ctl4.bits.reg_slv = 3;         //low power voltage 1.08V, default value is 3
-+
-+	phy_base->phy_ctl1.bits.res_scktmds = 0;  //
-+	phy_base->phy_ctl0.bits.reg_csmps = 2;
-+	phy_base->phy_ctl0.bits.reg_ck_test_sel = 0;  //?
-+	phy_base->phy_ctl0.bits.reg_ck_sel = 1;
-+	phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0;
-+
-+	// phy_enable
-+	ret = sun20i_d1_hdmi_phy_enable(phy_base);
-+	if (ret)
-+		return ret;
-+
-+	phy_base->phy_ctl0.bits.sda_en = 1;
-+	phy_base->phy_ctl0.bits.scl_en = 1;
-+	phy_base->phy_ctl0.bits.hpd_en = 1;
-+	phy_base->phy_ctl0.bits.reg_den = 0xF;
-+	phy_base->pll_ctl0.bits.envbs = 1;
- 
- 	return 0;
- }
-@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p
- 		return dev_err_probe(dev, PTR_ERR(regs),
- 				     "Couldn't map the HDMI PHY registers\n");
- 
-+	phy->base = regs;
- 	phy->regs = devm_regmap_init_mmio(dev, regs,
- 					  &sun8i_hdmi_phy_regmap_config);
- 	if (IS_ERR(phy->regs))
diff --git a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch b/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch
deleted file mode 100644
index 18dfa573e3..0000000000
--- a/target/linux/d1/patches-6.1/0010-riscv-mm-Use-IOMMU-for-DMA-when-available.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 18:47:53 -0500
-Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/mm/dma-noncoherent.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/riscv/mm/dma-noncoherent.c
-+++ b/arch/riscv/mm/dma-noncoherent.c
-@@ -7,6 +7,7 @@
- 
- #include <linux/dma-direct.h>
- #include <linux/dma-map-ops.h>
-+#include <linux/iommu.h>
- #include <linux/mm.h>
- #include <asm/cacheflush.h>
- 
-@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d
- 		   dev_driver_string(dev), dev_name(dev));
- 
- 	dev->dma_coherent = coherent;
-+
-+	if (iommu)
-+		iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
- }
- 
- void riscv_noncoherent_supported(void)
diff --git a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch b/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch
deleted file mode 100644
index d8dd2878d1..0000000000
--- a/target/linux/d1/patches-6.1/0011-genirq-Add-support-for-oneshot-safe-threaded-EOIs.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 7 May 2022 18:34:25 -0500
-Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs
-
-irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE |
-IRQCHIP_EOI_THREADED to elide mask operations.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- kernel/irq/chip.c      | 36 +++++++++++++++++-------------------
- kernel/irq/internals.h |  2 +-
- kernel/irq/manage.c    | 12 ++++++------
- 3 files changed, 24 insertions(+), 26 deletions(-)
-
---- a/kernel/irq/chip.c
-+++ b/kernel/irq/chip.c
-@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc)
- 	}
- }
- 
--void unmask_threaded_irq(struct irq_desc *desc)
--{
--	struct irq_chip *chip = desc->irq_data.chip;
--
--	if (chip->flags & IRQCHIP_EOI_THREADED)
--		chip->irq_eoi(&desc->irq_data);
--
--	unmask_irq(desc);
--}
--
- /*
-  *	handle_nested_irq - Handle a nested irq from a irq thread
-  *	@irq:	the interrupt number
-@@ -656,25 +646,33 @@ out_unlock:
- }
- EXPORT_SYMBOL_GPL(handle_level_irq);
- 
--static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
-+void unmask_eoi_threaded_irq(struct irq_desc *desc)
- {
--	if (!(desc->istate & IRQS_ONESHOT)) {
-+	struct irq_chip *chip = desc->irq_data.chip;
-+
-+	if (desc->istate & IRQS_ONESHOT)
-+		unmask_irq(desc);
-+
-+	if (chip->flags & IRQCHIP_EOI_THREADED)
- 		chip->irq_eoi(&desc->irq_data);
-+}
-+
-+static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
-+{
-+	/* Do not send EOI if the thread will do it for us. */
-+	if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot)
- 		return;
--	}
-+
- 	/*
- 	 * We need to unmask in the following cases:
- 	 * - Oneshot irq which did not wake the thread (caused by a
- 	 *   spurious interrupt or a primary handler handling it
- 	 *   completely).
- 	 */
--	if (!irqd_irq_disabled(&desc->irq_data) &&
--	    irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
--		chip->irq_eoi(&desc->irq_data);
-+	if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot)
- 		unmask_irq(desc);
--	} else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
--		chip->irq_eoi(&desc->irq_data);
--	}
-+
-+	chip->irq_eoi(&desc->irq_data);
- }
- 
- /**
---- a/kernel/irq/internals.h
-+++ b/kernel/irq/internals.h
-@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq
- extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu);
- extern void mask_irq(struct irq_desc *desc);
- extern void unmask_irq(struct irq_desc *desc);
--extern void unmask_threaded_irq(struct irq_desc *desc);
-+extern void unmask_eoi_threaded_irq(struct irq_desc *desc);
- 
- #ifdef CONFIG_SPARSE_IRQ
- static inline void irq_mark_irq(unsigned int irq) { }
---- a/kernel/irq/manage.c
-+++ b/kernel/irq/manage.c
-@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct
- static void irq_finalize_oneshot(struct irq_desc *desc,
- 				 struct irqaction *action)
- {
--	if (!(desc->istate & IRQS_ONESHOT) ||
--	    action->handler == irq_forced_secondary_handler)
-+	if (action->handler == irq_forced_secondary_handler)
- 		return;
-+
- again:
- 	chip_bus_lock(desc);
- 	raw_spin_lock_irq(&desc->lock);
-@@ -1112,9 +1112,8 @@ again:
- 
- 	desc->threads_oneshot &= ~action->thread_mask;
- 
--	if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) &&
--	    irqd_irq_masked(&desc->irq_data))
--		unmask_threaded_irq(desc);
-+	if (!desc->threads_oneshot)
-+		unmask_eoi_threaded_irq(desc);
- 
- out_unlock:
- 	raw_spin_unlock_irq(&desc->lock);
-@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq
- 	 * !ONESHOT irqs the thread mask is 0 so we can avoid a
- 	 * conditional in irq_wake_thread().
- 	 */
--	if (new->flags & IRQF_ONESHOT) {
-+	if ((new->flags & IRQF_ONESHOT) ||
-+	    (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) {
- 		/*
- 		 * Unlikely to have 32 resp 64 irqs sharing one line,
- 		 * but who knows.
diff --git a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch b/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch
deleted file mode 100644
index 8cb949f186..0000000000
--- a/target/linux/d1/patches-6.1/0012-irqchip-sifive-plic-Enable-oneshot-safe-threaded-EOI.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 7 May 2022 18:38:34 -0500
-Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded
- EOIs
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/irqchip/irq-sifive-plic.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/irqchip/irq-sifive-plic.c
-+++ b/drivers/irqchip/irq-sifive-plic.c
-@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = {
- 	.irq_set_affinity = plic_set_affinity,
- #endif
- 	.irq_set_type	= plic_irq_set_type,
--	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
-+	.flags		= IRQCHIP_ONESHOT_SAFE |
-+			  IRQCHIP_EOI_THREADED |
-+			  IRQCHIP_AFFINITY_PRE_STARTUP,
- };
- 
- static int plic_irq_set_type(struct irq_data *d, unsigned int type)
diff --git a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch b/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch
deleted file mode 100644
index 209d97597c..0000000000
--- a/target/linux/d1/patches-6.1/0013-irqchip-sifive-plic-Support-wake-IRQs.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 28 May 2022 19:04:56 -0500
-Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/irqchip/irq-sifive-plic.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/irqchip/irq-sifive-plic.c
-+++ b/drivers/irqchip/irq-sifive-plic.c
-@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip =
- 	.irq_set_affinity = plic_set_affinity,
- #endif
- 	.irq_set_type	= plic_irq_set_type,
--	.flags		= IRQCHIP_AFFINITY_PRE_STARTUP,
-+	.flags		= IRQCHIP_SKIP_SET_WAKE |
-+			  IRQCHIP_AFFINITY_PRE_STARTUP,
- };
- 
- static struct irq_chip plic_chip = {
-@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = {
- 	.irq_set_affinity = plic_set_affinity,
- #endif
- 	.irq_set_type	= plic_irq_set_type,
--	.flags		= IRQCHIP_ONESHOT_SAFE |
-+	.flags		= IRQCHIP_SKIP_SET_WAKE |
-+			  IRQCHIP_ONESHOT_SAFE |
- 			  IRQCHIP_EOI_THREADED |
- 			  IRQCHIP_AFFINITY_PRE_STARTUP,
- };
diff --git a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch b/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch
deleted file mode 100644
index 7e8098a2cf..0000000000
--- a/target/linux/d1/patches-6.1/0014-mmc-sunxi-mmc-Correct-the-maximum-segment-size.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:15:56 -0500
-Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size
-
-According to the DMA descriptor documentation, the lowest two bits of
-the size field are ignored, so the size must be rounded up to a multiple
-of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size
-to 0 will cause that DMA descriptor to be ignored.
-
-Together, these restrictions limit the maximum DMA segment size to 4
-less than the power-of-two width of the size field.
-
-Series-to: Ulf Hansson <ulf.hansson@linaro.org>
-Series-to: linux-mmc@vger.kernel.org
-
-Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -214,6 +214,9 @@
- #define SDXC_IDMAC_DES0_CES	BIT(30) /* card error summary */
- #define SDXC_IDMAC_DES0_OWN	BIT(31) /* 1-idma owns it, 0-host owns it */
- 
-+/* Buffer size must be a multiple of 4 bytes. */
-+#define SDXC_IDMAC_SIZE_ALIGN	4
-+
- #define SDXC_CLK_400K		0
- #define SDXC_CLK_25M		1
- #define SDXC_CLK_50M		2
-@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru
- {
- 	struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
- 	dma_addr_t next_desc = host->sg_dma;
--	int i, max_len = (1 << host->cfg->idma_des_size_bits);
-+	int i;
- 
- 	for (i = 0; i < data->sg_len; i++) {
- 		pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
- 					     SDXC_IDMAC_DES0_OWN |
- 					     SDXC_IDMAC_DES0_DIC);
- 
--		if (data->sg[i].length == max_len)
--			pdes[i].buf_size = 0; /* 0 == max_len */
--		else
--			pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
-+		pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length,
-+						     SDXC_IDMAC_SIZE_ALIGN));
- 
- 		next_desc += sizeof(struct sunxi_idma_des);
- 		pdes[i].buf_addr_ptr1 =
-@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo
- 	mmc->max_blk_count	= 8192;
- 	mmc->max_blk_size	= 4096;
- 	mmc->max_segs		= PAGE_SIZE / sizeof(struct sunxi_idma_des);
--	mmc->max_seg_size	= (1 << host->cfg->idma_des_size_bits);
-+	mmc->max_seg_size	= (1 << host->cfg->idma_des_size_bits) -
-+				  SDXC_IDMAC_SIZE_ALIGN;
- 	mmc->max_req_size	= mmc->max_seg_size * mmc->max_segs;
- 	/* 400kHz ~ 52MHz */
- 	mmc->f_min		=   400000;
diff --git a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch b/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch
deleted file mode 100644
index 665c55058c..0000000000
--- a/target/linux/d1/patches-6.1/0015-dt-bindings-display-Add-bindings-for-ClockworkPi-CWD.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001
-From: Max Fierke <max@maxfierke.com>
-Date: Wed, 1 Jun 2022 00:17:47 -0500
-Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi
- CWD686
-
-The CWD686 is a 6.86" IPS LCD panel used as the primary
-display in the ClockworkPi DevTerm portable (all cores)
-
-Signed-off-by: Max Fierke <max@maxfierke.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/panel/clockwork,cwd686.yaml       | 62 +++++++++++++++++++
- 1 file changed, 62 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
-@@ -0,0 +1,62 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Clockwork CWD686 6.86" IPS LCD panel
-+
-+maintainers:
-+  - Max Fierke <max@maxfierke.com>
-+
-+description: |
-+  The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the
-+  Clockwork DevTerm series of portable devices. The panel has a 480x1280
-+  resolution and uses 24 bit RGB per pixel.
-+
-+allOf:
-+  - $ref: panel-common.yaml#
-+
-+properties:
-+  compatible:
-+    const: clockwork,cwd686
-+
-+  reg:
-+    description: DSI virtual channel used by that screen
-+    maxItems: 1
-+
-+  reset-gpios: true
-+  rotation: true
-+  backlight: true
-+  iovcc-supply: true
-+  vci-supply: true
-+
-+required:
-+  - compatible
-+  - reg
-+  - backlight
-+  - reset-gpios
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/gpio/gpio.h>
-+
-+    backlight: backlight {
-+        compatible = "gpio-backlight";
-+        gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-+    };
-+
-+    dsi {
-+        #address-cells = <1>;
-+        #size-cells = <0>;
-+
-+        panel@0 {
-+            compatible = "clockwork,cwd686";
-+            reg = <0>;
-+            backlight = <&backlight>;
-+            reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
-+            rotation = <90>;
-+        };
-+    };
diff --git a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch b/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch
deleted file mode 100644
index 85d8421f62..0000000000
--- a/target/linux/d1/patches-6.1/0016-dt-bindings-display-Add-Sitronix-ST7701s-panel-bindi.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 01:59:35 -0500
-Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel
- binding
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/panel/sitronix,st7701s.yaml       | 32 +++++++++++++++++++
- 1 file changed, 32 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
-@@ -0,0 +1,32 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Sitronix ST7701 based LCD panels
-+
-+maintainers:
-+  - Samuel Holland <samuel@sholland.org>
-+
-+description: |
-+  Panel used on Lichee RV 86 Panel
-+
-+allOf:
-+  - $ref: panel-common.yaml#
-+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
-+
-+properties:
-+  compatible:
-+    items:
-+      - const: sitronix,st7701s
-+
-+  backlight: true
-+
-+  reset-gpios: true
-+
-+required:
-+  - compatible
-+  - reset-gpios
-+
-+unevaluatedProperties: false
diff --git a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch b/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch
deleted file mode 100644
index 535478cf9e..0000000000
--- a/target/linux/d1/patches-6.1/0017-drm-panel-Add-driver-for-ST7701s-DPI-LCD-panel.patch
+++ /dev/null
@@ -1,487 +0,0 @@
-From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 29 Mar 2022 22:47:57 -0500
-Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/Kconfig                 |   8 +
- drivers/gpu/drm/panel/Makefile                |   1 +
- .../gpu/drm/panel/panel-sitronix-st7701s.c    | 444 ++++++++++++++++++
- 3 files changed, 453 insertions(+)
- create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c
-
---- a/drivers/gpu/drm/panel/Kconfig
-+++ b/drivers/gpu/drm/panel/Kconfig
-@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701
- 	  ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI
- 	  system interfaces.
- 
-+config DRM_PANEL_SITRONIX_ST7701S
-+	tristate "Sitronix ST7701s panel driver"
-+	depends on OF
-+	depends on BACKLIGHT_CLASS_DEVICE
-+	help
-+	  Say Y here if you want to enable support for the Sitronix
-+	  ST7701s controller with a SPI interface.
-+
- config DRM_PANEL_SITRONIX_ST7703
- 	tristate "Sitronix ST7703 based MIPI touchscreen panels"
- 	depends on OF
---- a/drivers/gpu/drm/panel/Makefile
-+++ b/drivers/gpu/drm/panel/Makefile
-@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01
- obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
- obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
-+obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
- obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o
---- /dev/null
-+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c
-@@ -0,0 +1,444 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2017 Free Electrons
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/module.h>
-+#include <linux/spi/spi.h>
-+
-+#include <video/mipi_display.h>
-+
-+#include <drm/drm_device.h>
-+#include <drm/drm_modes.h>
-+#include <drm/drm_panel.h>
-+
-+struct st7701s {
-+	struct drm_panel	panel;
-+	struct gpio_desc	*reset;
-+	struct spi_device	*spi;
-+};
-+
-+enum {
-+	ST7789V_COMMAND	= 0 << 8,
-+	ST7789V_DATA	= 1 << 8,
-+};
-+
-+#define LCD_WRITE_COMMAND(x)	(ST7789V_COMMAND | (x))
-+#define LCD_WRITE_DATA(x)	(ST7789V_DATA | (x))
-+
-+static const u16 st7701s_init_sequence_1[] = {
-+	LCD_WRITE_COMMAND(0xFF),
-+	LCD_WRITE_DATA(0x77),
-+	LCD_WRITE_DATA(0x01),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x10),
-+
-+	LCD_WRITE_COMMAND(0xC0),
-+	LCD_WRITE_DATA(0x3B),
-+	LCD_WRITE_DATA(0x00),
-+
-+	LCD_WRITE_COMMAND(0xC1),
-+	LCD_WRITE_DATA(0x0D),
-+	LCD_WRITE_DATA(0x02),
-+
-+	LCD_WRITE_COMMAND(0xC2),
-+	LCD_WRITE_DATA(0x21),
-+	LCD_WRITE_DATA(0x08),
-+
-+	// RGB Interface Setting
-+	// LCD_WRITE_COMMAND(0xC3),
-+	// LCD_WRITE_DATA(0x02),
-+
-+	LCD_WRITE_COMMAND(0xCD),
-+	LCD_WRITE_DATA(0x18),//0F 08-OK  D0-D18
-+
-+	LCD_WRITE_COMMAND(0xB0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x18),
-+	LCD_WRITE_DATA(0x0E),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x06),
-+	LCD_WRITE_DATA(0x07),
-+	LCD_WRITE_DATA(0x08),
-+	LCD_WRITE_DATA(0x07),
-+	LCD_WRITE_DATA(0x22),
-+	LCD_WRITE_DATA(0x04),
-+	LCD_WRITE_DATA(0x12),
-+	LCD_WRITE_DATA(0x0F),
-+	LCD_WRITE_DATA(0xAA),
-+	LCD_WRITE_DATA(0x31),
-+	LCD_WRITE_DATA(0x18),
-+
-+	LCD_WRITE_COMMAND(0xB1),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x19),
-+	LCD_WRITE_DATA(0x0E),
-+	LCD_WRITE_DATA(0x12),
-+	LCD_WRITE_DATA(0x07),
-+	LCD_WRITE_DATA(0x08),
-+	LCD_WRITE_DATA(0x08),
-+	LCD_WRITE_DATA(0x08),
-+	LCD_WRITE_DATA(0x22),
-+	LCD_WRITE_DATA(0x04),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0xA9),
-+	LCD_WRITE_DATA(0x32),
-+	LCD_WRITE_DATA(0x18),
-+
-+	LCD_WRITE_COMMAND(0xFF),
-+	LCD_WRITE_DATA(0x77),
-+	LCD_WRITE_DATA(0x01),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x11),
-+
-+	LCD_WRITE_COMMAND(0xB0),
-+	LCD_WRITE_DATA(0x60),
-+
-+	LCD_WRITE_COMMAND(0xB1),
-+	LCD_WRITE_DATA(0x30),
-+
-+	LCD_WRITE_COMMAND(0xB2),
-+	LCD_WRITE_DATA(0x87),
-+
-+	LCD_WRITE_COMMAND(0xB3),
-+	LCD_WRITE_DATA(0x80),
-+
-+	LCD_WRITE_COMMAND(0xB5),
-+	LCD_WRITE_DATA(0x49),
-+
-+	LCD_WRITE_COMMAND(0xB7),
-+	LCD_WRITE_DATA(0x85),
-+
-+	LCD_WRITE_COMMAND(0xB8),
-+	LCD_WRITE_DATA(0x21),
-+
-+	LCD_WRITE_COMMAND(0xC1),
-+	LCD_WRITE_DATA(0x78),
-+
-+	LCD_WRITE_COMMAND(0xC2),
-+	LCD_WRITE_DATA(0x78),
-+};
-+
-+static const u16 st7701s_init_sequence_2[] = {
-+	LCD_WRITE_COMMAND(0xE0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x1B),
-+	LCD_WRITE_DATA(0x02),
-+
-+	LCD_WRITE_COMMAND(0xE1),
-+	LCD_WRITE_DATA(0x08),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x07),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x44),
-+	LCD_WRITE_DATA(0x44),
-+
-+	LCD_WRITE_COMMAND(0xE2),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x44),
-+	LCD_WRITE_DATA(0x44),
-+	LCD_WRITE_DATA(0xED),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0xEC),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+
-+	LCD_WRITE_COMMAND(0xE3),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x11),
-+
-+	LCD_WRITE_COMMAND(0xE4),
-+	LCD_WRITE_DATA(0x44),
-+	LCD_WRITE_DATA(0x44),
-+
-+	LCD_WRITE_COMMAND(0xE5),
-+	LCD_WRITE_DATA(0x0A),
-+	LCD_WRITE_DATA(0xE9),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x0C),
-+	LCD_WRITE_DATA(0xEB),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x0E),
-+	LCD_WRITE_DATA(0xED),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x10),
-+	LCD_WRITE_DATA(0xEF),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+
-+	LCD_WRITE_COMMAND(0xE6),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x11),
-+	LCD_WRITE_DATA(0x11),
-+
-+	LCD_WRITE_COMMAND(0xE7),
-+	LCD_WRITE_DATA(0x44),
-+	LCD_WRITE_DATA(0x44),
-+
-+	LCD_WRITE_COMMAND(0xE8),
-+	LCD_WRITE_DATA(0x09),
-+	LCD_WRITE_DATA(0xE8),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x0B),
-+	LCD_WRITE_DATA(0xEA),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x0D),
-+	LCD_WRITE_DATA(0xEC),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+	LCD_WRITE_DATA(0x0F),
-+	LCD_WRITE_DATA(0xEE),
-+	LCD_WRITE_DATA(0xD8),
-+	LCD_WRITE_DATA(0xA0),
-+
-+	LCD_WRITE_COMMAND(0xEB),
-+	LCD_WRITE_DATA(0x02),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0xE4),
-+	LCD_WRITE_DATA(0xE4),
-+	LCD_WRITE_DATA(0x88),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x40),
-+
-+	LCD_WRITE_COMMAND(0xEC),
-+	LCD_WRITE_DATA(0x3C),
-+	LCD_WRITE_DATA(0x00),
-+
-+	LCD_WRITE_COMMAND(0xED),
-+	LCD_WRITE_DATA(0xAB),
-+	LCD_WRITE_DATA(0x89),
-+	LCD_WRITE_DATA(0x76),
-+	LCD_WRITE_DATA(0x54),
-+	LCD_WRITE_DATA(0x02),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0xFF),
-+	LCD_WRITE_DATA(0x20),
-+	LCD_WRITE_DATA(0x45),
-+	LCD_WRITE_DATA(0x67),
-+	LCD_WRITE_DATA(0x98),
-+	LCD_WRITE_DATA(0xBA),
-+
-+	LCD_WRITE_COMMAND(0xFF),
-+	LCD_WRITE_DATA(0x77),
-+	LCD_WRITE_DATA(0x01),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+	LCD_WRITE_DATA(0x00),
-+
-+	LCD_WRITE_COMMAND(MIPI_DCS_SET_PIXEL_FORMAT),
-+	LCD_WRITE_DATA(0x66),
-+
-+	LCD_WRITE_COMMAND(MIPI_DCS_SET_ADDRESS_MODE),
-+	LCD_WRITE_DATA(0x00),
-+
-+	LCD_WRITE_COMMAND(MIPI_DCS_ENTER_INVERT_MODE),
-+
-+	LCD_WRITE_COMMAND(MIPI_DCS_EXIT_SLEEP_MODE),
-+};
-+
-+static const u16 st7701s_enable_sequence[] = {
-+	LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_ON),
-+};
-+
-+static const u16 st7701s_disable_sequence[] = {
-+	LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_OFF),
-+};
-+
-+static inline struct st7701s *panel_to_st7701s(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct st7701s, panel);
-+}
-+
-+static int st7701s_spi_write(struct st7701s *ctx, const u16 *data, size_t size)
-+{
-+	struct spi_transfer xfer = { };
-+	struct spi_message msg;
-+
-+	spi_message_init(&msg);
-+
-+	xfer.tx_buf = data;
-+	xfer.bits_per_word = 9;
-+	xfer.len = size;
-+
-+	spi_message_add_tail(&xfer, &msg);
-+	return spi_sync(ctx->spi, &msg);
-+}
-+
-+static const struct drm_display_mode default_mode = {
-+	.clock		= 19800,
-+	.hdisplay	= 480,
-+	.hsync_start	= 480 + 60,
-+	.hsync_end	= 480 + 60 + 12,
-+	.htotal		= 480 + 60 + 12 + 60,
-+	.vdisplay	= 480,
-+	.vsync_start	= 480 + 18,
-+	.vsync_end	= 480 + 18 + 4,
-+	.vtotal		= 480 + 18 + 4 + 18,
-+};
-+
-+static int st7701s_get_modes(struct drm_panel *panel,
-+			     struct drm_connector *connector)
-+{
-+	struct drm_display_mode *mode;
-+
-+	mode = drm_mode_duplicate(connector->dev, &default_mode);
-+	if (!mode)
-+		return -ENOMEM;
-+
-+	drm_mode_set_name(mode);
-+
-+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+	drm_mode_probed_add(connector, mode);
-+
-+	connector->display_info.width_mm = 70;
-+	connector->display_info.height_mm = 72;
-+
-+	return 1;
-+}
-+
-+static int st7701s_prepare(struct drm_panel *panel)
-+{
-+	struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+	gpiod_set_value_cansleep(ctx->reset, 1);
-+	msleep(20);
-+
-+	gpiod_set_value_cansleep(ctx->reset, 0);
-+	msleep(20);
-+
-+	st7701s_spi_write(ctx, st7701s_init_sequence_1,
-+			  sizeof(st7701s_init_sequence_1));
-+	msleep(20);
-+
-+	st7701s_spi_write(ctx, st7701s_init_sequence_2,
-+			  sizeof(st7701s_init_sequence_2));
-+	msleep(120);
-+
-+	return 0;
-+}
-+
-+static int st7701s_enable(struct drm_panel *panel)
-+{
-+	struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+	st7701s_spi_write(ctx, st7701s_enable_sequence,
-+			  sizeof(st7701s_enable_sequence));
-+	msleep(20);
-+
-+	return 0;
-+}
-+
-+static int st7701s_disable(struct drm_panel *panel)
-+{
-+	struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+	st7701s_spi_write(ctx, st7701s_disable_sequence,
-+			  sizeof(st7701s_disable_sequence));
-+
-+	return 0;
-+}
-+
-+static int st7701s_unprepare(struct drm_panel *panel)
-+{
-+	return 0;
-+}
-+
-+static const struct drm_panel_funcs st7701s_drm_funcs = {
-+	.disable	= st7701s_disable,
-+	.enable		= st7701s_enable,
-+	.get_modes	= st7701s_get_modes,
-+	.prepare	= st7701s_prepare,
-+	.unprepare	= st7701s_unprepare,
-+};
-+
-+static int st7701s_probe(struct spi_device *spi)
-+{
-+	struct device *dev = &spi->dev;
-+	struct st7701s *ctx;
-+	int ret;
-+
-+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	spi_set_drvdata(spi, ctx);
-+	ctx->spi = spi;
-+
-+	ctx->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
-+	if (IS_ERR(ctx->reset)) {
-+		dev_err(&spi->dev, "Couldn't get our reset line\n");
-+		return PTR_ERR(ctx->reset);
-+	}
-+
-+	drm_panel_init(&ctx->panel, dev, &st7701s_drm_funcs,
-+		       DRM_MODE_CONNECTOR_DPI);
-+
-+	ret = drm_panel_of_backlight(&ctx->panel);
-+	if (ret)
-+		return ret;
-+
-+	drm_panel_add(&ctx->panel);
-+
-+	return 0;
-+}
-+
-+static void st7701s_remove(struct spi_device *spi)
-+{
-+	struct st7701s *ctx = spi_get_drvdata(spi);
-+
-+	drm_panel_remove(&ctx->panel);
-+}
-+
-+static const struct of_device_id st7701s_of_match[] = {
-+	{ .compatible = "sitronix,st7701s" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, st7701s_of_match);
-+
-+static const struct spi_device_id st7701s_ids[] = {
-+	{ "st7701s" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(spi, st7701s_ids);
-+
-+static struct spi_driver st7701s_driver = {
-+	.probe = st7701s_probe,
-+	.remove = st7701s_remove,
-+	.driver = {
-+		.name = "st7701s",
-+		.of_match_table = st7701s_of_match,
-+	},
-+};
-+module_spi_driver(st7701s_driver);
-+
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Sitronix ST7701s LCD Driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch b/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch
deleted file mode 100644
index 1db6899a19..0000000000
--- a/target/linux/d1/patches-6.1/0018-nvmem-sunxi_sid-Drop-the-workaround-on-A64.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From db71abf941d25b92b2117780d3771197417d1c81 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 31 Jul 2022 20:34:20 -0500
-Subject: [PATCH 018/117] nvmem: sunxi_sid: Drop the workaround on A64
-
-Now that the SRAM readout code is fixed by using 32-bit accesses, it
-always returns the same values as register readout, so the A64 variant
-no longer needs the workaround. This makes the D1 variant structure
-redundant, so remove it.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/nvmem/sunxi_sid.c | 8 +-------
- 1 file changed, 1 insertion(+), 7 deletions(-)
-
---- a/drivers/nvmem/sunxi_sid.c
-+++ b/drivers/nvmem/sunxi_sid.c
-@@ -196,15 +196,9 @@ static const struct sunxi_sid_cfg sun8i_
- 	.need_register_readout = true,
- };
- 
--static const struct sunxi_sid_cfg sun20i_d1_cfg = {
--	.value_offset = 0x200,
--	.size = 0x100,
--};
--
- static const struct sunxi_sid_cfg sun50i_a64_cfg = {
- 	.value_offset = 0x200,
- 	.size = 0x100,
--	.need_register_readout = true,
- };
- 
- static const struct sunxi_sid_cfg sun50i_h6_cfg = {
-@@ -217,7 +211,7 @@ static const struct of_device_id sunxi_s
- 	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
- 	{ .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
- 	{ .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
--	{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg },
-+	{ .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg },
- 	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
- 	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
- 	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
diff --git a/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch b/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch
deleted file mode 100644
index ee4a7f742b..0000000000
--- a/target/linux/d1/patches-6.1/0019-dt-bindings-nvmem-Allow-bit-offsets-greater-than-a-b.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From d03341ef7acb64803ade6b173d24f49ffa6149a3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 2 Aug 2022 00:29:32 -0500
-Subject: [PATCH 019/117] dt-bindings: nvmem: Allow bit offsets greater than a
- byte
-
-Some NVMEM devices contain cells which do not start at a multiple of the
-device's stride. However, the "reg" property of a cell must be aligned
-to its provider device's stride.
-
-These cells can be represented in the DT using the "bits" property if
-that property allows offsets up to the full stride. 63 is chosen
-assuming that NVMEM devices will not have strides larger than 8 bytes.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/nvmem/nvmem.yaml | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
-+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
-@@ -53,7 +53,7 @@ patternProperties:
-         $ref: /schemas/types.yaml#/definitions/uint32-array
-         items:
-           - minimum: 0
--            maximum: 7
-+            maximum: 63
-             description:
-               Offset in bit within the address range specified by reg.
-           - minimum: 1
diff --git a/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch b/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch
deleted file mode 100644
index 0e59af2f38..0000000000
--- a/target/linux/d1/patches-6.1/0020-regulator-dt-bindings-Add-Allwinner-D1-LDOs.patch
+++ /dev/null
@@ -1,156 +0,0 @@
-From f666d95c1443854555044d3d4b52c463cf845ccc Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 20:33:40 -0500
-Subject: [PATCH 020/117] regulator: dt-bindings: Add Allwinner D1 LDOs
-
-The Allwinner D1 SoC contains two pairs of in-package LDOs. One pair is
-for general purpose use. LDOA generally powers the board's 1.8 V rail.
-LDOB generally powers the in-package DRAM, where applicable.
-
-The other pair of LDOs powers the analog power domains inside the SoC,
-including the audio codec, thermal sensor, and ADCs. These LDOs require
-a 0.9 V bandgap voltage reference. The calibration value for the voltage
-reference is stored in an eFuse, accessed via an NVMEM cell.
-
-Neither LDO control register is in its own MMIO range; instead, each
-regulator device relies on a regmap/syscon exported by its parent.
-
-Series-changes: 2
- - Remove syscon property from bindings
- - Update binding examples to fix warnings and provide context
-
-Series-changes: 3
- - Add "reg" property to bindings
- - Add "unevaluatedProperties: true" to regulator nodes
- - Minor changes to regulator node name patterns
- - Remove system-ldos example (now added in patch 3)
-
-Series-changes: 4
- - Fix the order of the maintainer/description sections
- - Replace unevaluatedProperties with "additionalProperties: false"
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner,sun20i-d1-analog-ldos.yaml      | 74 +++++++++++++++++++
- .../allwinner,sun20i-d1-system-ldos.yaml      | 37 ++++++++++
- 2 files changed, 111 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
- create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
-@@ -0,0 +1,74 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-analog-ldos.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner D1 Analog LDOs
-+
-+maintainers:
-+  - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+  Allwinner D1 contains a set of LDOs which are designed to supply analog power
-+  inside and outside the SoC. They are controlled by a register within the audio
-+  codec MMIO space, but which is not part of the audio codec clock/reset domain.
-+
-+properties:
-+  compatible:
-+    enum:
-+      - allwinner,sun20i-d1-analog-ldos
-+
-+  reg:
-+    maxItems: 1
-+
-+  nvmem-cells:
-+    items:
-+      - description: NVMEM cell for the calibrated bandgap reference trim value
-+
-+  nvmem-cell-names:
-+    items:
-+      - const: bg_trim
-+
-+patternProperties:
-+  "^(a|hp)ldo$":
-+    type: object
-+    $ref: regulator.yaml#
-+    unevaluatedProperties: false
-+
-+required:
-+  - compatible
-+  - reg
-+  - nvmem-cells
-+  - nvmem-cell-names
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    audio-codec@2030000 {
-+        compatible = "simple-mfd", "syscon";
-+        reg = <0x2030000 0x1000>;
-+        ranges;
-+        #address-cells = <1>;
-+        #size-cells = <1>;
-+
-+        regulators@2030348 {
-+            compatible = "allwinner,sun20i-d1-analog-ldos";
-+            reg = <0x2030348 0x4>;
-+            nvmem-cells = <&bg_trim>;
-+            nvmem-cell-names = "bg_trim";
-+
-+            reg_aldo: aldo {
-+                regulator-min-microvolt = <1800000>;
-+                regulator-max-microvolt = <1800000>;
-+            };
-+
-+            reg_hpldo: hpldo {
-+                regulator-min-microvolt = <1800000>;
-+                regulator-max-microvolt = <1800000>;
-+            };
-+        };
-+    };
-+
-+...
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
-@@ -0,0 +1,37 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner D1 System LDOs
-+
-+maintainers:
-+  - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+  Allwinner D1 contains a pair of general-purpose LDOs which are designed to
-+  supply power inside and outside the SoC. They are controlled by a register
-+  within the system control MMIO space.
-+
-+properties:
-+  compatible:
-+    enum:
-+      - allwinner,sun20i-d1-system-ldos
-+
-+  reg:
-+    maxItems: 1
-+
-+patternProperties:
-+  "^ldo[ab]$":
-+    type: object
-+    $ref: regulator.yaml#
-+    unevaluatedProperties: false
-+
-+required:
-+  - compatible
-+  - reg
-+
-+additionalProperties: false
-+
-+...
diff --git a/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch b/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch
deleted file mode 100644
index 7a5b2a0e74..0000000000
--- a/target/linux/d1/patches-6.1/0021-regulator-sun20i-Add-support-for-Allwinner-D1-LDOs.patch
+++ /dev/null
@@ -1,294 +0,0 @@
-From ad842bfb2eb10a75050dd69145ca59de982eb0e9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 11:46:52 -0500
-Subject: [PATCH 021/117] regulator: sun20i: Add support for Allwinner D1 LDOs
-
-D1 contains two pairs of LDOs. Since they have similar bindings, and
-they always exist together, put them in a single driver.
-
-The analog LDOs are relatively boring, with a single linear range. Their
-one quirk is that a bandgap reference must be calibrated for them to
-produce the correct voltage.
-
-The system LDOs have the complication that their voltage step is not an
-integer, so a custom .list_voltage is needed to get the rounding right.
-
-Series-changes: 2
- - Use decimal numbers for .n_voltages instead of field widths
- - Get the regmap from the parent device instead of a property/phandle
-
-Series-changes: 3
- - Adjust control flow in sun20i_regulator_get_regmap() for clarity
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/regulator/Kconfig            |   8 +
- drivers/regulator/Makefile           |   1 +
- drivers/regulator/sun20i-regulator.c | 232 +++++++++++++++++++++++++++
- 3 files changed, 241 insertions(+)
- create mode 100644 drivers/regulator/sun20i-regulator.c
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1280,6 +1280,14 @@ config REGULATOR_STW481X_VMMC
- 	  This driver supports the internal VMMC regulator in the STw481x
- 	  PMIC chips.
- 
-+config REGULATOR_SUN20I
-+	tristate "Allwinner D1 internal LDOs"
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	depends on MFD_SYSCON && NVMEM
-+	default ARCH_SUNXI
-+	help
-+	  This driver supports the internal LDOs in the Allwinner D1 SoC.
-+
- config REGULATOR_SY7636A
- 	tristate "Silergy SY7636A voltage regulator"
- 	depends on MFD_SY7636A
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -150,6 +150,7 @@ obj-$(CONFIG_REGULATOR_STM32_VREFBUF) +=
- obj-$(CONFIG_REGULATOR_STM32_PWR) += stm32-pwr.o
- obj-$(CONFIG_REGULATOR_STPMIC1) += stpmic1_regulator.o
- obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
-+obj-$(CONFIG_REGULATOR_SUN20I) += sun20i-regulator.o
- obj-$(CONFIG_REGULATOR_SY7636A) += sy7636a-regulator.o
- obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
- obj-$(CONFIG_REGULATOR_SY8824X) += sy8824x.o
---- /dev/null
-+++ b/drivers/regulator/sun20i-regulator.c
-@@ -0,0 +1,232 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+//
-+// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
-+//
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/driver.h>
-+
-+#define SUN20I_POWER_REG		0x348
-+
-+#define SUN20I_SYS_LDO_CTRL_REG		0x150
-+
-+struct sun20i_regulator_data {
-+	int				(*init)(struct device *dev,
-+						struct regmap *regmap);
-+	const struct regulator_desc	*descs;
-+	unsigned int			ndescs;
-+};
-+
-+static int sun20i_d1_analog_ldos_init(struct device *dev, struct regmap *regmap)
-+{
-+	u8 bg_trim;
-+	int ret;
-+
-+	ret = nvmem_cell_read_u8(dev, "bg_trim", &bg_trim);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to get bg_trim value\n");
-+
-+	/* The default value corresponds to 900 mV. */
-+	if (!bg_trim)
-+		bg_trim = 0x19;
-+
-+	return regmap_update_bits(regmap, SUN20I_POWER_REG,
-+				  GENMASK(7, 0), bg_trim);
-+}
-+
-+static const struct regulator_ops sun20i_d1_analog_ldo_ops = {
-+	.list_voltage		= regulator_list_voltage_linear,
-+	.map_voltage		= regulator_map_voltage_linear,
-+	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
-+	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
-+	.enable			= regulator_enable_regmap,
-+	.disable		= regulator_disable_regmap,
-+	.is_enabled		= regulator_is_enabled_regmap,
-+};
-+
-+static const struct regulator_desc sun20i_d1_analog_ldo_descs[] = {
-+	{
-+		.name		= "aldo",
-+		.supply_name	= "vdd33",
-+		.of_match	= "aldo",
-+		.ops		= &sun20i_d1_analog_ldo_ops,
-+		.type		= REGULATOR_VOLTAGE,
-+		.owner		= THIS_MODULE,
-+		.n_voltages	= 8,
-+		.min_uV		= 1650000,
-+		.uV_step	= 50000,
-+		.vsel_reg	= SUN20I_POWER_REG,
-+		.vsel_mask	= GENMASK(14, 12),
-+		.enable_reg	= SUN20I_POWER_REG,
-+		.enable_mask	= BIT(31),
-+	},
-+	{
-+		.name		= "hpldo",
-+		.supply_name	= "hpldoin",
-+		.of_match	= "hpldo",
-+		.ops		= &sun20i_d1_analog_ldo_ops,
-+		.type		= REGULATOR_VOLTAGE,
-+		.owner		= THIS_MODULE,
-+		.n_voltages	= 8,
-+		.min_uV		= 1650000,
-+		.uV_step	= 50000,
-+		.vsel_reg	= SUN20I_POWER_REG,
-+		.vsel_mask	= GENMASK(10, 8),
-+		.enable_reg	= SUN20I_POWER_REG,
-+		.enable_mask	= BIT(30),
-+	},
-+};
-+
-+static const struct sun20i_regulator_data sun20i_d1_analog_ldos = {
-+	.init	= sun20i_d1_analog_ldos_init,
-+	.descs	= sun20i_d1_analog_ldo_descs,
-+	.ndescs	= ARRAY_SIZE(sun20i_d1_analog_ldo_descs),
-+};
-+
-+/* regulator_list_voltage_linear() modified for the non-integral uV_step. */
-+static int sun20i_d1_system_ldo_list_voltage(struct regulator_dev *rdev,
-+					     unsigned int selector)
-+{
-+	const struct regulator_desc *desc = rdev->desc;
-+	unsigned int uV;
-+
-+	if (selector >= desc->n_voltages)
-+		return -EINVAL;
-+
-+	uV = desc->min_uV + (desc->uV_step * selector);
-+
-+	/* Produce correctly-rounded absolute voltages. */
-+	return uV + ((selector + 1 + (desc->min_uV % 4)) / 3);
-+}
-+
-+static const struct regulator_ops sun20i_d1_system_ldo_ops = {
-+	.list_voltage		= sun20i_d1_system_ldo_list_voltage,
-+	.map_voltage		= regulator_map_voltage_ascend,
-+	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
-+	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
-+};
-+
-+static const struct regulator_desc sun20i_d1_system_ldo_descs[] = {
-+	{
-+		.name		= "ldoa",
-+		.supply_name	= "ldo-in",
-+		.of_match	= "ldoa",
-+		.ops		= &sun20i_d1_system_ldo_ops,
-+		.type		= REGULATOR_VOLTAGE,
-+		.owner		= THIS_MODULE,
-+		.n_voltages	= 32,
-+		.min_uV		= 1600000,
-+		.uV_step	= 13333, /* repeating */
-+		.vsel_reg	= SUN20I_SYS_LDO_CTRL_REG,
-+		.vsel_mask	= GENMASK(7, 0),
-+	},
-+	{
-+		.name		= "ldob",
-+		.supply_name	= "ldo-in",
-+		.of_match	= "ldob",
-+		.ops		= &sun20i_d1_system_ldo_ops,
-+		.type		= REGULATOR_VOLTAGE,
-+		.owner		= THIS_MODULE,
-+		.n_voltages	= 64,
-+		.min_uV		= 1166666,
-+		.uV_step	= 13333, /* repeating */
-+		.vsel_reg	= SUN20I_SYS_LDO_CTRL_REG,
-+		.vsel_mask	= GENMASK(15, 8),
-+	},
-+};
-+
-+static const struct sun20i_regulator_data sun20i_d1_system_ldos = {
-+	.descs	= sun20i_d1_system_ldo_descs,
-+	.ndescs	= ARRAY_SIZE(sun20i_d1_system_ldo_descs),
-+};
-+
-+static const struct of_device_id sun20i_regulator_of_match[] = {
-+	{
-+		.compatible = "allwinner,sun20i-d1-analog-ldos",
-+		.data = &sun20i_d1_analog_ldos,
-+	},
-+	{
-+		.compatible = "allwinner,sun20i-d1-system-ldos",
-+		.data = &sun20i_d1_system_ldos,
-+	},
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, sun20i_regulator_of_match);
-+
-+static struct regmap *sun20i_regulator_get_regmap(struct device *dev)
-+{
-+	struct regmap *regmap;
-+
-+	/*
-+	 * First try the syscon interface. The system control device is not
-+	 * compatible with "syscon", so fall back to getting the regmap from
-+	 * its platform device. This is ugly, but required for devicetree
-+	 * backward compatibility.
-+	 */
-+	regmap = syscon_node_to_regmap(dev->parent->of_node);
-+	if (!IS_ERR(regmap))
-+		return regmap;
-+
-+	regmap = dev_get_regmap(dev->parent, NULL);
-+	if (regmap)
-+		return regmap;
-+
-+	return ERR_PTR(-EPROBE_DEFER);
-+}
-+
-+static int sun20i_regulator_probe(struct platform_device *pdev)
-+{
-+	const struct sun20i_regulator_data *data;
-+	struct device *dev = &pdev->dev;
-+	struct regulator_config config;
-+	struct regmap *regmap;
-+	int ret;
-+
-+	data = of_device_get_match_data(dev);
-+	if (!data)
-+		return -EINVAL;
-+
-+	regmap = sun20i_regulator_get_regmap(dev);
-+	if (IS_ERR(regmap))
-+		return dev_err_probe(dev, PTR_ERR(regmap), "Failed to get regmap\n");
-+
-+	if (data->init) {
-+		ret = data->init(dev, regmap);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	config = (struct regulator_config) {
-+		.dev	= dev,
-+		.regmap	= regmap,
-+	};
-+
-+	for (unsigned int i = 0; i < data->ndescs; ++i) {
-+		const struct regulator_desc *desc = &data->descs[i];
-+		struct regulator_dev *rdev;
-+
-+		rdev = devm_regulator_register(dev, desc, &config);
-+		if (IS_ERR(rdev))
-+			return PTR_ERR(rdev);
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver sun20i_regulator_driver = {
-+	.probe	= sun20i_regulator_probe,
-+	.driver	= {
-+		.name		= "sun20i-regulator",
-+		.of_match_table	= sun20i_regulator_of_match,
-+	},
-+};
-+module_platform_driver(sun20i_regulator_driver);
-+
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_DESCRIPTION("Allwinner D1 internal LDO driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch b/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch
deleted file mode 100644
index 9e24a75927..0000000000
--- a/target/linux/d1/patches-6.1/0022-dt-bindings-sram-sunxi-sram-Add-optional-regulators-.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 52c6979628d596018e9259767bff4def25e449dc Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 1 Aug 2022 23:57:19 -0500
-Subject: [PATCH 022/117] dt-bindings: sram: sunxi-sram: Add optional
- regulators child
-
-Some sunxi SoCs have in-package regulators controlled by a register in
-the system control MMIO block. Allow a child node for these regulators
-in addition to SRAM child nodes.
-
-Commit-changes: 2
- - New patch for v2
-
-Series-changes: 3
- - Require the regulators node to have a unit address
- - Reference the regulator schema from the SRAM controller schema
- - Move the system LDOs example to the SRAM controller schema
- - Reorder the patches so the example passes validation
-
-Series-changes: 4
- - Remove unevaluatedProperties from regulators schema reference
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner,sun4i-a10-system-control.yaml   | 28 +++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
-+++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
-@@ -56,6 +56,9 @@ properties:
-   ranges: true
- 
- patternProperties:
-+  "^regulators@[0-9a-f]+$":
-+    $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
-+
-   "^sram@[a-z0-9]+":
-     type: object
- 
-@@ -130,3 +133,28 @@ examples:
-         };
-       };
-     };
-+
-+  - |
-+    syscon@3000000 {
-+      compatible = "allwinner,sun20i-d1-system-control";
-+      reg = <0x3000000 0x1000>;
-+      ranges;
-+      #address-cells = <1>;
-+      #size-cells = <1>;
-+
-+      regulators@3000150 {
-+        compatible = "allwinner,sun20i-d1-system-ldos";
-+        reg = <0x3000150 0x4>;
-+
-+        reg_ldoa: ldoa {
-+          regulator-min-microvolt = <1800000>;
-+          regulator-max-microvolt = <1800000>;
-+        };
-+
-+        reg_ldob: ldob {
-+          regulator-name = "vcc-dram";
-+          regulator-min-microvolt = <1500000>;
-+          regulator-max-microvolt = <1500000>;
-+        };
-+      };
-+    };
diff --git a/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch b/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch
deleted file mode 100644
index 4544cb3c38..0000000000
--- a/target/linux/d1/patches-6.1/0023-soc-sunxi-sram-Only-iterate-over-SRAM-children.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 1946ff7ee38c994ae3eb9968c5b51695c0df2cf7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 2 Aug 2022 00:01:21 -0500
-Subject: [PATCH 023/117] soc: sunxi: sram: Only iterate over SRAM children
-
-Now that a "regulators" child is accepted by the controller binding, the
-debugfs show routine must be explicitly limited to "sram" children.
-
-Series-to: Liam Girdwood <lgirdwood@gmail.com>
-Series-to: Mark Brown <broonie@kernel.org>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-to: Rob Herring <robh+dt@kernel.org>
-
-Commit-changes: 2
- - New patch for v2
-
-Series-version: 4
-
-Cover-letter:
-regulator: Add support for Allwinner D1 LDOs
-This series adds bindings and a driver for the two pairs of LDOs
-inside the Allwinner D1 SoC.
-
-A binding and driver change is required for the SRAM controller, to
-accept the regulators device as its child node. The new example in the
-SRAM controller binding uses the compatible string added in this series:
-https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
-END
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/soc/sunxi/sunxi_sram.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/soc/sunxi/sunxi_sram.c
-+++ b/drivers/soc/sunxi/sunxi_sram.c
-@@ -120,6 +120,9 @@ static int sunxi_sram_show(struct seq_fi
- 	seq_puts(s, "--------------------\n\n");
- 
- 	for_each_child_of_node(sram_dev->of_node, sram_node) {
-+		if (!of_node_name_eq(sram_node, "sram"))
-+			continue;
-+
- 		sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
- 
- 		seq_printf(s, "sram@%08x\n",
diff --git a/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch b/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch
deleted file mode 100644
index 442e9865b6..0000000000
--- a/target/linux/d1/patches-6.1/0024-MAINTAINERS-Match-the-sun20i-family-of-Allwinner-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 25727569379b42593b55cfb743b7eff4cfa1cce2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 23:45:50 -0500
-Subject: [PATCH 024/117] MAINTAINERS: Match the sun20i family of Allwinner
- SoCs
-
-Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
-that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- MAINTAINERS | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -1828,7 +1828,7 @@ F:	drivers/pinctrl/sunxi/
- F:	drivers/soc/sunxi/
- N:	allwinner
- N:	sun[x456789]i
--N:	sun50i
-+N:	sun[25]0i
- 
- ARM/Amlogic Meson SoC CLOCK FRAMEWORK
- M:	Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch b/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch
deleted file mode 100644
index 357cc1e419..0000000000
--- a/target/linux/d1/patches-6.1/0025-dt-bindings-riscv-Add-T-HEAD-C906-and-C910-compatibl.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 16 May 2021 14:05:17 -0500
-Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
- compatibles
-
-The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
-Notably, the C906 core is used in the Allwinner D1 SoC.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/riscv/cpus.yaml
-+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
-@@ -39,6 +39,8 @@ properties:
-               - sifive,u5
-               - sifive,u7
-               - canaan,k210
-+              - thead,c906
-+              - thead,c910
-           - const: riscv
-       - items:
-           - enum:
diff --git a/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch b/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch
deleted file mode 100644
index ca4d7c4295..0000000000
--- a/target/linux/d1/patches-6.1/0026-dt-bindings-vendor-prefixes-Add-Allwinner-D1-board-v.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From d0c24deb787a95515d355eea68e0402bfec77f75 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 14:42:05 -0500
-Subject: [PATCH 026/117] dt-bindings: vendor-prefixes: Add Allwinner D1 board
- vendors
-
-Some boards using the Allwinner D1 SoC are made by vendors not
-previously documented.
-
-Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
-ClockworkPi and DevTerm boards.
-
-Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
-the MangoPi family of boards.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -260,6 +260,8 @@ patternProperties:
-     description: Cirrus Logic, Inc.
-   "^cisco,.*":
-     description: Cisco Systems, Inc.
-+  "^clockwork,.*":
-+    description: Clockwork Tech LLC
-   "^cloudengines,.*":
-     description: Cloud Engines, Inc.
-   "^cnm,.*":
-@@ -1424,6 +1426,8 @@ patternProperties:
-     description: Shenzhen whwave Electronics, Inc.
-   "^wi2wi,.*":
-     description: Wi2Wi, Inc.
-+  "^widora,.*":
-+    description: Beijing Widora Technology Co., Ltd.
-   "^wiligear,.*":
-     description: Wiligear, Ltd.
-   "^willsemi,.*":
diff --git a/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch b/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch
deleted file mode 100644
index 6fd802e68b..0000000000
--- a/target/linux/d1/patches-6.1/0027-dt-bindings-riscv-Add-Allwinner-D1-board-compatibles.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 4d7c04f210dd401f3560a7f53c78d6e058d182e2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 29 Jun 2022 00:26:39 -0500
-Subject: [PATCH 027/117] dt-bindings: riscv: Add Allwinner D1 board
- compatibles
-
-Several SoMs and boards are available that feature the Allwinner D1 SoC.
-Document their compatible strings.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/riscv/sunxi.yaml      | 64 +++++++++++++++++++
- 1 file changed, 64 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner RISC-V SoC-based boards
-+
-+maintainers:
-+  - Chen-Yu Tsai <wens@csie.org>
-+  - Jernej Skrabec <jernej.skrabec@gmail.com>
-+  - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+  Allwinner RISC-V SoC-based boards
-+
-+properties:
-+  $nodename:
-+    const: '/'
-+  compatible:
-+    oneOf:
-+      - description: Dongshan Nezha STU SoM
-+        items:
-+          - const: 100ask,dongshan-nezha-stu
-+          - const: allwinner,sun20i-d1
-+
-+      - description: D1 Nezha board
-+        items:
-+          - const: allwinner,d1-nezha
-+          - const: allwinner,sun20i-d1
-+
-+      - description: ClockworkPi R-01 SoM and v3.14 board
-+        items:
-+          - const: clockwork,r-01-clockworkpi-v3.14
-+          - const: allwinner,sun20i-d1
-+
-+      - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
-+        items:
-+          - const: clockwork,r-01-devterm-v3.14
-+          - const: clockwork,r-01-clockworkpi-v3.14
-+          - const: allwinner,sun20i-d1
-+
-+      - description: Lichee RV SoM
-+        items:
-+          - const: sipeed,lichee-rv
-+          - const: allwinner,sun20i-d1
-+
-+      - description: Carrier boards for the Lichee RV SoM
-+        items:
-+          - enum:
-+              - sipeed,lichee-rv-86-panel-480p
-+              - sipeed,lichee-rv-86-panel-720p
-+              - sipeed,lichee-rv-dock
-+          - const: sipeed,lichee-rv
-+          - const: allwinner,sun20i-d1
-+
-+      - description: MangoPi MQ Pro board
-+        items:
-+          - const: widora,mangopi-mq-pro
-+          - const: allwinner,sun20i-d1
-+
-+additionalProperties: true
-+
-+...
diff --git a/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch b/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch
deleted file mode 100644
index 6f41449594..0000000000
--- a/target/linux/d1/patches-6.1/0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch
+++ /dev/null
@@ -1,936 +0,0 @@
-From 20d565fb9324b0d2791d10cb65560eddd2ef526e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 28 Jun 2022 23:20:33 -0500
-Subject: [PATCH 028/117] riscv: dts: allwinner: Add the D1 SoC base devicetree
-
-D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
-one HiFi 4 DSP. The SoC is based on a design that additionally contained
-a pair of Cortex A7's. For that reason, some peripherals are duplicated.
-
-This devicetree includes all of the peripherals that already have a
-documented binding.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/Makefile                 |   1 +
- arch/riscv/boot/dts/allwinner/Makefile       |   1 +
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
- 3 files changed, 902 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-
---- a/arch/riscv/boot/dts/Makefile
-+++ b/arch/riscv/boot/dts/Makefile
-@@ -1,4 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
-+subdir-y += allwinner
- subdir-y += sifive
- subdir-y += starfive
- subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -0,0 +1 @@
-+# SPDX-License-Identifier: GPL-2.0
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -0,0 +1,900 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+#include <dt-bindings/clock/sun6i-rtc.h>
-+#include <dt-bindings/clock/sun8i-de2.h>
-+#include <dt-bindings/clock/sun8i-tcon-top.h>
-+#include <dt-bindings/clock/sun20i-d1-ccu.h>
-+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/reset/sun8i-de2.h>
-+#include <dt-bindings/reset/sun20i-d1-ccu.h>
-+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
-+#include <dt-bindings/thermal/thermal.h>
-+
-+/ {
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	cpus {
-+		timebase-frequency = <24000000>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		cpu0: cpu@0 {
-+			compatible = "thead,c906", "riscv";
-+			device_type = "cpu";
-+			reg = <0>;
-+			clocks = <&ccu CLK_RISCV>;
-+			clock-frequency = <24000000>;
-+			d-cache-block-size = <64>;
-+			d-cache-sets = <256>;
-+			d-cache-size = <32768>;
-+			i-cache-block-size = <64>;
-+			i-cache-sets = <128>;
-+			i-cache-size = <32768>;
-+			mmu-type = "riscv,sv39";
-+			riscv,isa = "rv64imafdc";
-+			#cooling-cells = <2>;
-+
-+			cpu0_intc: interrupt-controller {
-+				compatible = "riscv,cpu-intc";
-+				interrupt-controller;
-+				#address-cells = <0>;
-+				#interrupt-cells = <1>;
-+			};
-+		};
-+	};
-+
-+	de: display-engine {
-+		compatible = "allwinner,sun20i-d1-display-engine";
-+		allwinner,pipelines = <&mixer0>, <&mixer1>;
-+		status = "disabled";
-+	};
-+
-+	osc24M: osc24M-clk {
-+		compatible = "fixed-clock";
-+		clock-frequency = <24000000>;
-+		clock-output-names = "osc24M";
-+		#clock-cells = <0>;
-+	};
-+
-+	soc {
-+		compatible = "simple-bus";
-+		ranges;
-+		interrupt-parent = <&plic>;
-+		dma-noncoherent;
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		dsp_wdt: watchdog@1700400 {
-+			compatible = "allwinner,sun20i-d1-wdt";
-+			reg = <0x1700400 0x20>;
-+			interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+			clock-names = "hosc", "losc";
-+			status = "reserved";
-+		};
-+
-+		pio: pinctrl@2000000 {
-+			compatible = "allwinner,sun20i-d1-pinctrl";
-+			reg = <0x2000000 0x800>;
-+			interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
-+				     <87 IRQ_TYPE_LEVEL_HIGH>,
-+				     <89 IRQ_TYPE_LEVEL_HIGH>,
-+				     <91 IRQ_TYPE_LEVEL_HIGH>,
-+				     <93 IRQ_TYPE_LEVEL_HIGH>,
-+				     <95 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_APB0>,
-+				 <&osc24M>,
-+				 <&rtc CLK_OSC32K>;
-+			clock-names = "apb", "hosc", "losc";
-+			gpio-controller;
-+			interrupt-controller;
-+			#gpio-cells = <3>;
-+			#interrupt-cells = <3>;
-+
-+			/omit-if-no-ref/
-+			i2c0_pb10_pins: i2c0-pb10-pins {
-+				pins = "PB10", "PB11";
-+				function = "i2c0";
-+			};
-+
-+			/omit-if-no-ref/
-+			i2c2_pb0_pins: i2c2-pb0-pins {
-+				pins = "PB0", "PB1";
-+				function = "i2c2";
-+			};
-+
-+			/omit-if-no-ref/
-+			lcd_rgb666_pins: lcd-rgb666-pins {
-+				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
-+				       "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
-+				       "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
-+				       "PD18", "PD19", "PD20", "PD21";
-+				function = "lcd0";
-+			};
-+
-+			/omit-if-no-ref/
-+			mmc0_pins: mmc0-pins {
-+				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
-+				function = "mmc0";
-+			};
-+
-+			/omit-if-no-ref/
-+			mmc1_pins: mmc1-pins {
-+				pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
-+				function = "mmc1";
-+			};
-+
-+			/omit-if-no-ref/
-+			mmc2_pins: mmc2-pins {
-+				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
-+				function = "mmc2";
-+			};
-+
-+			/omit-if-no-ref/
-+			rgmii_pe_pins: rgmii-pe-pins {
-+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
-+				       "PE5", "PE6", "PE7", "PE8", "PE9",
-+				       "PE11", "PE12", "PE13", "PE14", "PE15";
-+				function = "emac";
-+			};
-+
-+			/omit-if-no-ref/
-+			rmii_pe_pins: rmii-pe-pins {
-+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
-+				       "PE5", "PE6", "PE7", "PE8", "PE9";
-+				function = "emac";
-+			};
-+
-+			/omit-if-no-ref/
-+			uart0_pb8_pins: uart0-pb8-pins {
-+				pins = "PB8", "PB9";
-+				function = "uart0";
-+			};
-+
-+			/omit-if-no-ref/
-+			uart1_pg6_pins: uart1-pg6-pins {
-+				pins = "PG6", "PG7";
-+				function = "uart1";
-+			};
-+
-+			/omit-if-no-ref/
-+			uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
-+				pins = "PG8", "PG9";
-+				function = "uart1";
-+			};
-+		};
-+
-+		ccu: clock-controller@2001000 {
-+			compatible = "allwinner,sun20i-d1-ccu";
-+			reg = <0x2001000 0x1000>;
-+			clocks = <&osc24M>,
-+				 <&rtc CLK_OSC32K>,
-+				 <&rtc CLK_IOSC>;
-+			clock-names = "hosc", "losc", "iosc";
-+			#clock-cells = <1>;
-+			#reset-cells = <1>;
-+		};
-+
-+		lradc: keys@2009800 {
-+			compatible = "allwinner,sun20i-d1-lradc",
-+				     "allwinner,sun50i-r329-lradc";
-+			reg = <0x2009800 0x400>;
-+			interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_LRADC>;
-+			resets = <&ccu RST_BUS_LRADC>;
-+			status = "disabled";
-+		};
-+
-+		codec: audio-codec@2030000 {
-+			compatible = "simple-mfd", "syscon";
-+			reg = <0x2030000 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			regulators@2030348 {
-+				compatible = "allwinner,sun20i-d1-analog-ldos";
-+				reg = <0x2030348 0x4>;
-+				nvmem-cells = <&bg_trim>;
-+				nvmem-cell-names = "bg_trim";
-+
-+				reg_aldo: aldo {
-+				};
-+
-+				reg_hpldo: hpldo {
-+				};
-+			};
-+		};
-+
-+		i2s0: i2s@2032000 {
-+			compatible = "allwinner,sun20i-d1-i2s",
-+				     "allwinner,sun50i-r329-i2s";
-+			reg = <0x2032000 0x1000>;
-+			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2S0>,
-+				 <&ccu CLK_I2S0>;
-+			clock-names = "apb", "mod";
-+			resets = <&ccu RST_BUS_I2S0>;
-+			dmas = <&dma 3>, <&dma 3>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#sound-dai-cells = <0>;
-+		};
-+
-+		i2s1: i2s@2033000 {
-+			compatible = "allwinner,sun20i-d1-i2s",
-+				     "allwinner,sun50i-r329-i2s";
-+			reg = <0x2033000 0x1000>;
-+			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2S1>,
-+				 <&ccu CLK_I2S1>;
-+			clock-names = "apb", "mod";
-+			resets = <&ccu RST_BUS_I2S1>;
-+			dmas = <&dma 4>, <&dma 4>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#sound-dai-cells = <0>;
-+		};
-+
-+		i2s2: i2s@2034000 {
-+			compatible = "allwinner,sun20i-d1-i2s",
-+				     "allwinner,sun50i-r329-i2s";
-+			reg = <0x2034000 0x1000>;
-+			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2S2>,
-+				 <&ccu CLK_I2S2>;
-+			clock-names = "apb", "mod";
-+			resets = <&ccu RST_BUS_I2S2>;
-+			dmas = <&dma 5>, <&dma 5>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#sound-dai-cells = <0>;
-+		};
-+
-+		timer: timer@2050000 {
-+			compatible = "allwinner,sun20i-d1-timer",
-+				     "allwinner,sun8i-a23-timer";
-+			reg = <0x2050000 0xa0>;
-+			interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
-+				     <76 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&osc24M>;
-+		};
-+
-+		wdt: watchdog@20500a0 {
-+			compatible = "allwinner,sun20i-d1-wdt-reset",
-+				     "allwinner,sun20i-d1-wdt";
-+			reg = <0x20500a0 0x20>;
-+			interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+			clock-names = "hosc", "losc";
-+			status = "reserved";
-+		};
-+
-+		uart0: serial@2500000 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2500000 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART0>;
-+			resets = <&ccu RST_BUS_UART0>;
-+			dmas = <&dma 14>, <&dma 14>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		uart1: serial@2500400 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2500400 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART1>;
-+			resets = <&ccu RST_BUS_UART1>;
-+			dmas = <&dma 15>, <&dma 15>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		uart2: serial@2500800 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2500800 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART2>;
-+			resets = <&ccu RST_BUS_UART2>;
-+			dmas = <&dma 16>, <&dma 16>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		uart3: serial@2500c00 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2500c00 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART3>;
-+			resets = <&ccu RST_BUS_UART3>;
-+			dmas = <&dma 17>, <&dma 17>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		uart4: serial@2501000 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2501000 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART4>;
-+			resets = <&ccu RST_BUS_UART4>;
-+			dmas = <&dma 18>, <&dma 18>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		uart5: serial@2501400 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x2501400 0x400>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_UART5>;
-+			resets = <&ccu RST_BUS_UART5>;
-+			dmas = <&dma 19>, <&dma 19>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
-+		i2c0: i2c@2502000 {
-+			compatible = "allwinner,sun20i-d1-i2c",
-+				     "allwinner,sun8i-v536-i2c",
-+				     "allwinner,sun6i-a31-i2c";
-+			reg = <0x2502000 0x400>;
-+			interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2C0>;
-+			resets = <&ccu RST_BUS_I2C0>;
-+			dmas = <&dma 43>, <&dma 43>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		i2c1: i2c@2502400 {
-+			compatible = "allwinner,sun20i-d1-i2c",
-+				     "allwinner,sun8i-v536-i2c",
-+				     "allwinner,sun6i-a31-i2c";
-+			reg = <0x2502400 0x400>;
-+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2C1>;
-+			resets = <&ccu RST_BUS_I2C1>;
-+			dmas = <&dma 44>, <&dma 44>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		i2c2: i2c@2502800 {
-+			compatible = "allwinner,sun20i-d1-i2c",
-+				     "allwinner,sun8i-v536-i2c",
-+				     "allwinner,sun6i-a31-i2c";
-+			reg = <0x2502800 0x400>;
-+			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2C2>;
-+			resets = <&ccu RST_BUS_I2C2>;
-+			dmas = <&dma 45>, <&dma 45>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		i2c3: i2c@2502c00 {
-+			compatible = "allwinner,sun20i-d1-i2c",
-+				     "allwinner,sun8i-v536-i2c",
-+				     "allwinner,sun6i-a31-i2c";
-+			reg = <0x2502c00 0x400>;
-+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_I2C3>;
-+			resets = <&ccu RST_BUS_I2C3>;
-+			dmas = <&dma 46>, <&dma 46>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		syscon: syscon@3000000 {
-+			compatible = "allwinner,sun20i-d1-system-control";
-+			reg = <0x3000000 0x1000>;
-+			ranges;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			regulators@3000150 {
-+				compatible = "allwinner,sun20i-d1-system-ldos";
-+				reg = <0x3000150 0x4>;
-+
-+				reg_ldoa: ldoa {
-+				};
-+
-+				reg_ldob: ldob {
-+				};
-+			};
-+		};
-+
-+		dma: dma-controller@3002000 {
-+			compatible = "allwinner,sun20i-d1-dma";
-+			reg = <0x3002000 0x1000>;
-+			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
-+			clock-names = "bus", "mbus";
-+			resets = <&ccu RST_BUS_DMA>;
-+			dma-channels = <16>;
-+			dma-requests = <48>;
-+			#dma-cells = <1>;
-+		};
-+
-+		sid: efuse@3006000 {
-+			compatible = "allwinner,sun20i-d1-sid";
-+			reg = <0x3006000 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			ths_calib: ths-calib@14 {
-+				reg = <0x14 0x4>;
-+			};
-+
-+			bg_trim: bg-trim@28 {
-+				reg = <0x28 0x4>;
-+				bits = <16 8>;
-+			};
-+		};
-+
-+		mbus: dram-controller@3102000 {
-+			compatible = "allwinner,sun20i-d1-mbus";
-+			reg = <0x3102000 0x1000>,
-+			      <0x3103000 0x1000>;
-+			reg-names = "mbus", "dram";
-+			interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_MBUS>,
-+				 <&ccu CLK_DRAM>,
-+				 <&ccu CLK_BUS_DRAM>;
-+			clock-names = "mbus", "dram", "bus";
-+			dma-ranges = <0 0x40000000 0x80000000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			#interconnect-cells = <1>;
-+		};
-+
-+		mmc0: mmc@4020000 {
-+			compatible = "allwinner,sun20i-d1-mmc";
-+			reg = <0x4020000 0x1000>;
-+			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
-+			clock-names = "ahb", "mmc";
-+			resets = <&ccu RST_BUS_MMC0>;
-+			reset-names = "ahb";
-+			cap-sd-highspeed;
-+			max-frequency = <150000000>;
-+			no-mmc;
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		mmc1: mmc@4021000 {
-+			compatible = "allwinner,sun20i-d1-mmc";
-+			reg = <0x4021000 0x1000>;
-+			interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
-+			clock-names = "ahb", "mmc";
-+			resets = <&ccu RST_BUS_MMC1>;
-+			reset-names = "ahb";
-+			cap-sd-highspeed;
-+			max-frequency = <150000000>;
-+			no-mmc;
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		mmc2: mmc@4022000 {
-+			compatible = "allwinner,sun20i-d1-emmc",
-+				     "allwinner,sun50i-a100-emmc";
-+			reg = <0x4022000 0x1000>;
-+			interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
-+			clock-names = "ahb", "mmc";
-+			resets = <&ccu RST_BUS_MMC2>;
-+			reset-names = "ahb";
-+			cap-mmc-highspeed;
-+			max-frequency = <150000000>;
-+			mmc-ddr-1_8v;
-+			mmc-ddr-3_3v;
-+			no-sd;
-+			no-sdio;
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		usb_otg: usb@4100000 {
-+			compatible = "allwinner,sun20i-d1-musb",
-+				     "allwinner,sun8i-a33-musb";
-+			reg = <0x4100000 0x400>;
-+			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "mc";
-+			clocks = <&ccu CLK_BUS_OTG>;
-+			resets = <&ccu RST_BUS_OTG>;
-+			extcon = <&usbphy 0>;
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		usbphy: phy@4100400 {
-+			compatible = "allwinner,sun20i-d1-usb-phy";
-+			reg = <0x4100400 0x100>,
-+			      <0x4101800 0x100>,
-+			      <0x4200800 0x100>;
-+			reg-names = "phy_ctrl",
-+				    "pmu0",
-+				    "pmu1";
-+			clocks = <&osc24M>,
-+				 <&osc24M>;
-+			clock-names = "usb0_phy",
-+				      "usb1_phy";
-+			resets = <&ccu RST_USB_PHY0>,
-+				 <&ccu RST_USB_PHY1>;
-+			reset-names = "usb0_reset",
-+				      "usb1_reset";
-+			status = "disabled";
-+			#phy-cells = <1>;
-+		};
-+
-+		ehci0: usb@4101000 {
-+			compatible = "allwinner,sun20i-d1-ehci",
-+				     "generic-ehci";
-+			reg = <0x4101000 0x100>;
-+			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI0>,
-+				 <&ccu CLK_BUS_EHCI0>,
-+				 <&ccu CLK_USB_OHCI0>;
-+			resets = <&ccu RST_BUS_OHCI0>,
-+				 <&ccu RST_BUS_EHCI0>;
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci0: usb@4101400 {
-+			compatible = "allwinner,sun20i-d1-ohci",
-+				     "generic-ohci";
-+			reg = <0x4101400 0x100>;
-+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI0>,
-+				 <&ccu CLK_USB_OHCI0>;
-+			resets = <&ccu RST_BUS_OHCI0>;
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ehci1: usb@4200000 {
-+			compatible = "allwinner,sun20i-d1-ehci",
-+				     "generic-ehci";
-+			reg = <0x4200000 0x100>;
-+			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI1>,
-+				 <&ccu CLK_BUS_EHCI1>,
-+				 <&ccu CLK_USB_OHCI1>;
-+			resets = <&ccu RST_BUS_OHCI1>,
-+				 <&ccu RST_BUS_EHCI1>;
-+			phys = <&usbphy 1>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci1: usb@4200400 {
-+			compatible = "allwinner,sun20i-d1-ohci",
-+				     "generic-ohci";
-+			reg = <0x4200400 0x100>;
-+			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI1>,
-+				 <&ccu CLK_USB_OHCI1>;
-+			resets = <&ccu RST_BUS_OHCI1>;
-+			phys = <&usbphy 1>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		emac: ethernet@4500000 {
-+			compatible = "allwinner,sun20i-d1-emac",
-+				     "allwinner,sun50i-a64-emac";
-+			reg = <0x4500000 0x10000>;
-+			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "macirq";
-+			clocks = <&ccu CLK_BUS_EMAC>;
-+			clock-names = "stmmaceth";
-+			resets = <&ccu RST_BUS_EMAC>;
-+			reset-names = "stmmaceth";
-+			syscon = <&syscon>;
-+			status = "disabled";
-+
-+			mdio: mdio {
-+				compatible = "snps,dwmac-mdio";
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
-+		};
-+
-+		display_clocks: clock-controller@5000000 {
-+			compatible = "allwinner,sun20i-d1-de2-clk",
-+				     "allwinner,sun50i-h5-de2-clk";
-+			reg = <0x5000000 0x10000>;
-+			clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_DE>;
-+			#clock-cells = <1>;
-+			#reset-cells = <1>;
-+		};
-+
-+		mixer0: mixer@5100000 {
-+			compatible = "allwinner,sun20i-d1-de2-mixer-0";
-+			reg = <0x5100000 0x100000>;
-+			clocks = <&display_clocks CLK_BUS_MIXER0>,
-+				 <&display_clocks CLK_MIXER0>;
-+			clock-names = "bus", "mod";
-+			resets = <&display_clocks RST_MIXER0>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mixer0_out: port@1 {
-+					reg = <1>;
-+
-+					mixer0_out_tcon_top_mixer0: endpoint {
-+						remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
-+					};
-+				};
-+			};
-+		};
-+
-+		mixer1: mixer@5200000 {
-+			compatible = "allwinner,sun20i-d1-de2-mixer-1";
-+			reg = <0x5200000 0x100000>;
-+			clocks = <&display_clocks CLK_BUS_MIXER1>,
-+				 <&display_clocks CLK_MIXER1>;
-+			clock-names = "bus", "mod";
-+			resets = <&display_clocks RST_MIXER1>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mixer1_out: port@1 {
-+					reg = <1>;
-+
-+					mixer1_out_tcon_top_mixer1: endpoint {
-+						remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
-+					};
-+				};
-+			};
-+		};
-+
-+		tcon_top: tcon-top@5460000 {
-+			compatible = "allwinner,sun20i-d1-tcon-top";
-+			reg = <0x5460000 0x1000>;
-+			clocks = <&ccu CLK_BUS_DPSS_TOP>,
-+				 <&ccu CLK_TCON_TV>,
-+				 <&ccu CLK_TVE>,
-+				 <&ccu CLK_TCON_LCD0>;
-+			clock-names = "bus", "tcon-tv0", "tve0", "dsi";
-+			clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
-+			resets = <&ccu RST_BUS_DPSS_TOP>;
-+			#clock-cells = <1>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				tcon_top_mixer0_in: port@0 {
-+					reg = <0>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_top_mixer0_in_mixer0: endpoint@0 {
-+						reg = <0>;
-+						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
-+					};
-+				};
-+
-+				tcon_top_mixer0_out: port@1 {
-+					reg = <1>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
-+						reg = <0>;
-+						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
-+					};
-+
-+					tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
-+						reg = <2>;
-+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
-+					};
-+				};
-+
-+				tcon_top_mixer1_in: port@2 {
-+					reg = <2>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_top_mixer1_in_mixer1: endpoint@1 {
-+						reg = <1>;
-+						remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
-+					};
-+				};
-+
-+				tcon_top_mixer1_out: port@3 {
-+					reg = <3>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
-+						reg = <0>;
-+						remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
-+					};
-+
-+					tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
-+						reg = <2>;
-+						remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
-+					};
-+				};
-+
-+				tcon_top_hdmi_in: port@4 {
-+					reg = <4>;
-+
-+					tcon_top_hdmi_in_tcon_tv0: endpoint {
-+						remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
-+					};
-+				};
-+
-+				tcon_top_hdmi_out: port@5 {
-+					reg = <5>;
-+				};
-+			};
-+		};
-+
-+		tcon_lcd0: lcd-controller@5461000 {
-+			compatible = "allwinner,sun20i-d1-tcon-lcd";
-+			reg = <0x5461000 0x1000>;
-+			interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_TCON_LCD0>,
-+				 <&ccu CLK_TCON_LCD0>;
-+			clock-names = "ahb", "tcon-ch0";
-+			clock-output-names = "tcon-pixel-clock";
-+			resets = <&ccu RST_BUS_TCON_LCD0>,
-+				 <&ccu RST_BUS_LVDS0>;
-+			reset-names = "lcd", "lvds";
-+			#clock-cells = <0>;
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				tcon_lcd0_in: port@0 {
-+					reg = <0>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
-+						reg = <0>;
-+						remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
-+					};
-+
-+					tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
-+						reg = <1>;
-+						remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
-+					};
-+				};
-+
-+				tcon_lcd0_out: port@1 {
-+					reg = <1>;
-+				};
-+			};
-+		};
-+
-+		tcon_tv0: lcd-controller@5470000 {
-+			compatible = "allwinner,sun20i-d1-tcon-tv";
-+			reg = <0x5470000 0x1000>;
-+			interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_TCON_TV>,
-+				 <&tcon_top CLK_TCON_TOP_TV0>;
-+			clock-names = "ahb", "tcon-ch1";
-+			resets = <&ccu RST_BUS_TCON_TV>;
-+			reset-names = "lcd";
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				tcon_tv0_in: port@0 {
-+					reg = <0>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
-+						reg = <0>;
-+						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
-+					};
-+
-+					tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
-+						reg = <1>;
-+						remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
-+					};
-+				};
-+
-+				tcon_tv0_out: port@1 {
-+					reg = <1>;
-+
-+					tcon_tv0_out_tcon_top_hdmi: endpoint {
-+						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
-+					};
-+				};
-+			};
-+		};
-+
-+		riscv_wdt: watchdog@6011000 {
-+			compatible = "allwinner,sun20i-d1-wdt";
-+			reg = <0x6011000 0x20>;
-+			interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+			clock-names = "hosc", "losc";
-+		};
-+
-+		r_ccu: clock-controller@7010000 {
-+			compatible = "allwinner,sun20i-d1-r-ccu";
-+			reg = <0x7010000 0x400>;
-+			clocks = <&osc24M>,
-+				 <&rtc CLK_OSC32K>,
-+				 <&rtc CLK_IOSC>,
-+				 <&ccu CLK_PLL_PERIPH0_DIV3>;
-+			clock-names = "hosc", "losc", "iosc", "pll-periph";
-+			#clock-cells = <1>;
-+			#reset-cells = <1>;
-+		};
-+
-+		rtc: rtc@7090000 {
-+			compatible = "allwinner,sun20i-d1-rtc",
-+				     "allwinner,sun50i-r329-rtc";
-+			reg = <0x7090000 0x400>;
-+			interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&r_ccu CLK_BUS_R_RTC>,
-+				 <&osc24M>,
-+				 <&r_ccu CLK_R_AHB>;
-+			clock-names = "bus", "hosc", "ahb";
-+			#clock-cells = <1>;
-+		};
-+
-+		plic: interrupt-controller@10000000 {
-+			compatible = "allwinner,sun20i-d1-plic",
-+				     "thead,c900-plic";
-+			reg = <0x10000000 0x4000000>;
-+			interrupts-extended = <&cpu0_intc 11>,
-+					      <&cpu0_intc 9>;
-+			interrupt-controller;
-+			riscv,ndev = <176>;
-+			#address-cells = <0>;
-+			#interrupt-cells = <2>;
-+		};
-+	};
-+};
diff --git a/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch b/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch
deleted file mode 100644
index aadc3138d4..0000000000
--- a/target/linux/d1/patches-6.1/0029-riscv-dts-allwinner-Add-Allwinner-D1-Nezha-devicetre.patch
+++ /dev/null
@@ -1,263 +0,0 @@
-From 5da27190c54b7a51062786eb01246f6f4cf2ba98 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 28 Jun 2022 23:31:16 -0500
-Subject: [PATCH 029/117] riscv: dts: allwinner: Add Allwinner D1 Nezha
- devicetree
-
-"D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
-It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
-HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
-plus low-speed I/O from the SoC and a GPIO expander chip.
-
-Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
-powered by the SoCs internal LDOA, analog domains powered by ALDO, and
-the rest of the board powered by always-on fixed regulators. Some (but
-not all) boards also copied the PWM CPU regulator. To avoid duplication,
-factor out the out the regulator references that are common across all
-known boards.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Conor Dooley <conor.dooley@microchip.com>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile        |   1 +
- .../sun20i-d1-common-regulators.dtsi          |  51 ++++++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 171 ++++++++++++++++++
- 3 files changed, 223 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1 +1,2 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -0,0 +1,51 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+/ {
-+	reg_vcc: vcc {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	reg_vcc_3v3: vcc-3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc-3v3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+};
-+
-+&lradc {
-+	vref-supply = <&reg_aldo>;
-+};
-+
-+&pio {
-+	vcc-pb-supply = <&reg_vcc_3v3>;
-+	vcc-pc-supply = <&reg_vcc_3v3>;
-+	vcc-pd-supply = <&reg_vcc_3v3>;
-+	vcc-pe-supply = <&reg_vcc_3v3>;
-+	vcc-pf-supply = <&reg_vcc_3v3>;
-+	vcc-pg-supply = <&reg_vcc_3v3>;
-+};
-+
-+&reg_aldo {
-+	regulator-min-microvolt = <1800000>;
-+	regulator-max-microvolt = <1800000>;
-+	vdd33-supply = <&reg_vcc_3v3>;
-+};
-+
-+&reg_hpldo {
-+	regulator-min-microvolt = <1800000>;
-+	regulator-max-microvolt = <1800000>;
-+	hpldoin-supply = <&reg_vcc_3v3>;
-+};
-+
-+&reg_ldoa {
-+	regulator-always-on;
-+	regulator-min-microvolt = <1800000>;
-+	regulator-max-microvolt = <1800000>;
-+	ldo-in-supply = <&reg_vcc_3v3>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -0,0 +1,171 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+	model = "Allwinner D1 Nezha";
-+	compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
-+
-+	aliases {
-+		ethernet0 = &emac;
-+		ethernet1 = &xr829;
-+		mmc0 = &mmc0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	reg_usbvbus: usbvbus {
-+		compatible = "regulator-fixed";
-+		regulator-name = "usbvbus";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
-+		enable-active-high;
-+		vin-supply = <&reg_vcc>;
-+	};
-+
-+	/*
-+	 * This regulator is PWM-controlled, but the PWM controller is not
-+	 * yet supported, so fix the regulator to its default voltage.
-+	 */
-+	reg_vdd_cpu: vdd-cpu {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd-cpu";
-+		regulator-min-microvolt = <1100000>;
-+		regulator-max-microvolt = <1100000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+	status = "okay";
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&emac {
-+	pinctrl-0 = <&rgmii_pe_pins>;
-+	pinctrl-names = "default";
-+	phy-handle = <&ext_rgmii_phy>;
-+	phy-mode = "rgmii-id";
-+	phy-supply = <&reg_vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&i2c2 {
-+	pinctrl-0 = <&i2c2_pb0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	pcf8574a: gpio@38 {
-+		compatible = "nxp,pcf8574a";
-+		reg = <0x38>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
-+		interrupt-controller;
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		#interrupt-cells = <2>;
-+	};
-+};
-+
-+&lradc {
-+	status = "okay";
-+
-+	button-160 {
-+		label = "OK";
-+		linux,code = <KEY_OK>;
-+		channel = <0>;
-+		voltage = <160000>;
-+	};
-+};
-+
-+&mdio {
-+	ext_rgmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+	};
-+};
-+
-+&mmc0 {
-+	bus-width = <4>;
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+	disable-wp;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&mmc1 {
-+	bus-width = <4>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc1_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	xr829: wifi@1 {
-+		reg = <1>;
-+	};
-+};
-+
-+&ohci0 {
-+	status = "okay";
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0_pb8_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	uart-has-rtscts;
-+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	/* XR829 bluetooth is connected here */
-+};
-+
-+&usb_otg {
-+	dr_mode = "otg";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+	usb0_vbus-supply = <&reg_usbvbus>;
-+	usb1_vbus-supply = <&reg_vcc>;
-+	status = "okay";
-+};
diff --git a/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch b/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch
deleted file mode 100644
index 73c486aed2..0000000000
--- a/target/linux/d1/patches-6.1/0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch
+++ /dev/null
@@ -1,344 +0,0 @@
-From 3bf76e93011425ed64a69c462b9959ed2a8ccf46 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 29 Jun 2022 00:13:50 -0500
-Subject: [PATCH 030/117] riscv: dts: allwinner: Add Sipeed Lichee RV
- devicetrees
-
-Sipeed manufactures a "Lichee RV" system-on-module, which provides a
-minimal working system on its own, as well as a few carrier boards. The
-"Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
-provides 100M Ethernet and a built-in display panel.
-
-The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
-panel interface, since the USB OTG port is inaccessible inside the case.
-
-Co-developed-by: Jisheng Zhang <jszhang@kernel.org>
-Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile        |  4 +
- .../sun20i-d1-lichee-rv-86-panel-480p.dts     | 29 ++++++
- .../sun20i-d1-lichee-rv-86-panel-720p.dts     | 10 ++
- .../sun20i-d1-lichee-rv-86-panel.dtsi         | 92 +++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 74 +++++++++++++++
- .../dts/allwinner/sun20i-d1-lichee-rv.dts     | 84 +++++++++++++++++
- 6 files changed, 293 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,2 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-@@ -0,0 +1,29 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
-+
-+/ {
-+	model = "Sipeed Lichee RV 86 Panel (480p)";
-+	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
-+		     "allwinner,sun20i-d1";
-+};
-+
-+&i2c2 {
-+	pinctrl-0 = <&i2c2_pb0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	touchscreen@48 {
-+		compatible = "focaltech,ft6236";
-+		reg = <0x48>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
-+		iovcc-supply = <&reg_vcc_3v3>;
-+		reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
-+		touchscreen-size-x = <480>;
-+		touchscreen-size-y = <480>;
-+		vcc-supply = <&reg_vcc_3v3>;
-+		wakeup-source;
-+	};
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
-+
-+/ {
-+	model = "Sipeed Lichee RV 86 Panel (720p)";
-+	compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
-+		     "allwinner,sun20i-d1";
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -0,0 +1,92 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv.dts"
-+
-+/ {
-+	aliases {
-+		ethernet0 = &emac;
-+		ethernet1 = &xr829;
-+	};
-+
-+	/* PC1 is repurposed as BT_WAKE_AP */
-+	/delete-node/ leds;
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&ccu CLK_FANOUT1>;
-+		clock-names = "ext_clock";
-+		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+		assigned-clocks = <&ccu CLK_FANOUT1>;
-+		assigned-clock-rates = <32768>;
-+		pinctrl-0 = <&clk_pg11_pin>;
-+		pinctrl-names = "default";
-+	};
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&emac {
-+	pinctrl-0 = <&rmii_pe_pins>;
-+	pinctrl-names = "default";
-+	phy-handle = <&ext_rmii_phy>;
-+	phy-mode = "rmii";
-+	phy-supply = <&reg_vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&mdio {
-+	ext_rmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+		reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
-+	};
-+};
-+
-+&mmc1 {
-+	bus-width = <4>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc1_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	xr829: wifi@1 {
-+		reg = <1>;
-+	};
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&pio {
-+	clk_pg11_pin: clk-pg11-pin {
-+		pins = "PG11";
-+		function = "clk";
-+	};
-+};
-+
-+&uart1 {
-+	uart-has-rtscts;
-+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	/* XR829 bluetooth is connected here */
-+};
-+
-+&usb_otg {
-+	status = "disabled";
-+};
-+
-+&usbphy {
-+	/* PD20 and PD21 are repurposed for the LCD panel */
-+	/delete-property/ usb0_id_det-gpios;
-+	/delete-property/ usb0_vbus_det-gpios;
-+	usb1_vbus-supply = <&reg_vcc>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -0,0 +1,74 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include <dt-bindings/input/input.h>
-+
-+#include "sun20i-d1-lichee-rv.dts"
-+
-+/ {
-+	model = "Sipeed Lichee RV Dock";
-+	compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
-+		     "allwinner,sun20i-d1";
-+
-+	aliases {
-+		ethernet1 = &rtl8723ds;
-+	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+	};
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&lradc {
-+	status = "okay";
-+
-+	button-220 {
-+		label = "OK";
-+		linux,code = <KEY_OK>;
-+		channel = <0>;
-+		voltage = <220000>;
-+	};
-+};
-+
-+&mmc1 {
-+	bus-width = <4>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc1_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	rtl8723ds: wifi@1 {
-+		reg = <1>;
-+	};
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	uart-has-rtscts;
-+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "realtek,rtl8723ds-bt";
-+		device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
-+		enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
-+		host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
-+	};
-+};
-+
-+&usbphy {
-+	usb1_vbus-supply = <&reg_vcc>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-@@ -0,0 +1,84 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+	model = "Sipeed Lichee RV";
-+	compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
-+
-+	aliases {
-+		mmc0 = &mmc0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-0 {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_STATUS;
-+			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
-+		};
-+	};
-+
-+	reg_vdd_cpu: vdd-cpu {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd-cpu";
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+	status = "okay";
-+};
-+
-+&mmc0 {
-+	broken-cd;
-+	bus-width = <4>;
-+	disable-wp;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&ohci0 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0_pb8_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&usb_otg {
-+	dr_mode = "otg";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+	usb0_vbus-supply = <&reg_vcc>;
-+	status = "okay";
-+};
diff --git a/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch b/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch
deleted file mode 100644
index 54073136bf..0000000000
--- a/target/linux/d1/patches-6.1/0031-riscv-dts-allwinner-Add-MangoPi-MQ-Pro-devicetree.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From 3cf55c25453517960d72b56d1ba8f12840b1990e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 9 Jul 2022 17:43:17 -0500
-Subject: [PATCH 031/117] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
-
-The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
-Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
-and an RTL8723DS-based WiFi/Bluetooth module.
-
-The board also exposes GPIO Port E via a connector on the end of the
-board, which can support either a camera or an RMII Ethernet PHY. The
-additional regulators supply that connector.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile        |   1 +
- .../allwinner/sun20i-d1-mangopi-mq-pro.dts    | 128 ++++++++++++++++++
- 2 files changed, 129 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-li
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-@@ -0,0 +1,128 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+	model = "MangoPi MQ Pro";
-+	compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
-+
-+	aliases {
-+		ethernet0 = &rtl8723ds;
-+		mmc0 = &mmc0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	reg_avdd2v8: avdd2v8 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "avdd2v8";
-+		regulator-min-microvolt = <2800000>;
-+		regulator-max-microvolt = <2800000>;
-+		vin-supply = <&reg_vcc_3v3>;
-+	};
-+
-+	reg_dvdd: dvdd {
-+		compatible = "regulator-fixed";
-+		regulator-name = "dvdd";
-+		regulator-min-microvolt = <1200000>;
-+		regulator-max-microvolt = <1200000>;
-+		vin-supply = <&reg_vcc_3v3>;
-+	};
-+
-+	reg_vdd_cpu: vdd-cpu {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd-cpu";
-+		regulator-min-microvolt = <1100000>;
-+		regulator-max-microvolt = <1100000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpu>;
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&mmc0 {
-+	bus-width = <4>;
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+	disable-wp;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&mmc1 {
-+	bus-width = <4>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc1_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	rtl8723ds: wifi@1 {
-+		reg = <1>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
-+		interrupt-names = "host-wake";
-+	};
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&pio {
-+	vcc-pe-supply = <&reg_avdd2v8>;
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0_pb8_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	uart-has-rtscts;
-+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "realtek,rtl8723ds-bt";
-+		device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
-+		enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
-+		host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
-+	};
-+};
-+
-+&usb_otg {
-+	dr_mode = "peripheral";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_vbus-supply = <&reg_vcc>;
-+	status = "okay";
-+};
diff --git a/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch b/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch
deleted file mode 100644
index fe64eabd4e..0000000000
--- a/target/linux/d1/patches-6.1/0032-riscv-dts-allwinner-Add-Dongshan-Nezha-STU-devicetre.patch
+++ /dev/null
@@ -1,146 +0,0 @@
-From 1f26c90ac9cbb60ff315c552368a3bca16562e51 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 10 Jul 2022 11:24:42 -0500
-Subject: [PATCH 032/117] riscv: dts: allwinner: Add Dongshan Nezha STU
- devicetree
-
-The 100ask Dongshan Nezha STU is a system-on-module that can be used
-standalone or with a carrier board. The SoM provides gigabit Ethernet,
-HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
-
-The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
-headers, but contains no digital circuitry, so it does not have its own
-devicetree.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile        |   1 +
- .../sun20i-d1-dongshan-nezha-stu.dts          | 114 ++++++++++++++++++
- 2 files changed, 115 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,4 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-@@ -0,0 +1,114 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+	model = "Dongshan Nezha STU";
-+	compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
-+
-+	aliases {
-+		ethernet0 = &emac;
-+		mmc0 = &mmc0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-0 {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_STATUS;
-+			gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
-+		};
-+	};
-+
-+	reg_usbvbus: usbvbus {
-+		compatible = "regulator-fixed";
-+		regulator-name = "usbvbus";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
-+		enable-active-high;
-+		vin-supply = <&reg_vcc>;
-+	};
-+
-+	/*
-+	 * This regulator is PWM-controlled, but the PWM controller is not
-+	 * yet supported, so fix the regulator to its default voltage.
-+	 */
-+	reg_vdd_cpu: vdd-cpu {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd-cpu";
-+		regulator-min-microvolt = <1100000>;
-+		regulator-max-microvolt = <1100000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+	status = "okay";
-+};
-+
-+&emac {
-+	pinctrl-0 = <&rgmii_pe_pins>;
-+	pinctrl-names = "default";
-+	phy-handle = <&ext_rgmii_phy>;
-+	phy-mode = "rgmii-id";
-+	phy-supply = <&reg_vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&mdio {
-+	ext_rgmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+	};
-+};
-+
-+&mmc0 {
-+	broken-cd;
-+	bus-width = <4>;
-+	disable-wp;
-+	vmmc-supply = <&reg_vcc_3v3>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&ohci0 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0_pb8_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&usb_otg {
-+	dr_mode = "otg";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+	usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+	usb0_vbus-supply = <&reg_usbvbus>;
-+	status = "okay";
-+};
diff --git a/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch b/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch
deleted file mode 100644
index f9fcae026f..0000000000
--- a/target/linux/d1/patches-6.1/0033-riscv-dts-allwinner-Add-ClockworkPi-and-DevTerm-devi.patch
+++ /dev/null
@@ -1,322 +0,0 @@
-From 11f692c6b009f36b9a91d5ceb5998ae15e57f18c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 10 Jul 2022 23:43:49 -0500
-Subject: [PATCH 033/117] riscv: dts: allwinner: Add ClockworkPi and DevTerm
- devicetrees
-
-Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible
-"ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC.
-The R-01 contains only the CPU, DRAM, and always-on voltage regulation;
-it does not merit a separate devicetree.
-
-The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB
-host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an
-X-Powers AXP228 PMIC for managing a Li-ion battery.
-
-The DevTerm is a complete system which extends the ClockworkPi mainboard
-with a pair of expansion boards. These expansion boards provide a fan, a
-keyboard, speakers, and a thermal printer.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile        |   2 +
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 ++++++++++++++++++
- .../dts/allwinner/sun20i-d1-devterm-v3.14.dts |  37 +++
- 3 files changed, 281 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,4 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -0,0 +1,242 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+	model = "ClockworkPi v3.14 (R-01)";
-+	compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
-+
-+	aliases {
-+		ethernet0 = &ap6256;
-+		mmc0 = &mmc0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	/*
-+	 * This regulator is PWM-controlled, but the PWM controller is not
-+	 * yet supported, so fix the regulator to its default voltage.
-+	 */
-+	reg_vdd_cpu: vdd-cpu {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd-cpu";
-+		regulator-min-microvolt = <1100000>;
-+		regulator-max-microvolt = <1100000>;
-+		vin-supply = <&reg_vcc>;
-+	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpu>;
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	pinctrl-0 = <&i2c0_pb10_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	axp221: pmic@34 {
-+		compatible = "x-powers,axp228", "x-powers,axp221";
-+		reg = <0x34>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+
-+		ac_power_supply: ac-power {
-+			compatible = "x-powers,axp221-ac-power-supply";
-+		};
-+
-+		axp_adc: adc {
-+			compatible = "x-powers,axp221-adc";
-+			#io-channel-cells = <1>;
-+		};
-+
-+		battery_power_supply: battery-power {
-+			compatible = "x-powers,axp221-battery-power-supply";
-+		};
-+
-+		regulators {
-+			x-powers,dcdc-freq = <3000>;
-+
-+			reg_dcdc1: dcdc1 {
-+				regulator-name = "sys-3v3";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_dcdc3: dcdc3 {
-+				regulator-name = "sys-1v8";
-+				regulator-always-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+			};
-+
-+			reg_aldo1: aldo1 {
-+				regulator-name = "aud-3v3";
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_aldo2: aldo2 {
-+				regulator-name = "disp-3v3";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_aldo3: aldo3 {
-+				regulator-name = "vdd-wifi";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+			};
-+
-+			/* DLDO1 and ELDO1-3 are connected in parallel. */
-+			reg_dldo1: dldo1 {
-+				regulator-name = "vbat-wifi-a";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			/* DLDO2-DLDO4 are connected in parallel. */
-+			reg_dldo2: dldo2 {
-+				regulator-name = "vcc-3v3-ext-a";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_dldo3: dldo3 {
-+				regulator-name = "vcc-3v3-ext-b";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_dldo4: dldo4 {
-+				regulator-name = "vcc-3v3-ext-c";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_eldo1: eldo1 {
-+				regulator-name = "vbat-wifi-b";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_eldo2: eldo2 {
-+				regulator-name = "vbat-wifi-c";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+
-+			reg_eldo3: eldo3 {
-+				regulator-name = "vbat-wifi-d";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+			};
-+		};
-+
-+		usb_power_supply: usb-power {
-+			compatible = "x-powers,axp221-usb-power-supply";
-+			status = "disabled";
-+		};
-+	};
-+};
-+
-+&mmc0 {
-+	broken-cd;
-+	bus-width = <4>;
-+	disable-wp;
-+	vmmc-supply = <&reg_dcdc1>;
-+	vqmmc-supply = <&reg_vcc_3v3>;
-+	pinctrl-0 = <&mmc0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&mmc1 {
-+	bus-width = <4>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&reg_dldo1>;
-+	vqmmc-supply = <&reg_aldo3>;
-+	pinctrl-0 = <&mmc1_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	ap6256: wifi@1 {
-+		compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
-+		reg = <1>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
-+		interrupt-names = "host-wake";
-+	};
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&pio {
-+	vcc-pg-supply = <&reg_ldoa>;
-+};
-+
-+&uart0 {
-+	pinctrl-0 = <&uart0_pb8_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	uart-has-rtscts;
-+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm4345c5";
-+		interrupt-parent = <&pio>;
-+		interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
-+		device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
-+		shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
-+		max-speed = <1500000>;
-+		vbat-supply = <&reg_dldo1>;
-+		vddio-supply = <&reg_aldo3>;
-+	};
-+};
-+
-+&usb_otg {
-+	dr_mode = "peripheral";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_vbus_power-supply = <&ac_power_supply>;
-+	status = "okay";
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include "sun20i-d1-clockworkpi-v3.14.dts"
-+
-+/ {
-+	model = "Clockwork DevTerm (R-01)";
-+	compatible = "clockwork,r-01-devterm-v3.14",
-+		     "clockwork,r-01-clockworkpi-v3.14",
-+		     "allwinner,sun20i-d1";
-+
-+	fan {
-+		compatible = "gpio-fan";
-+		gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
-+		gpio-fan,speed-map = <0    0>,
-+				     <6000 1>;
-+		#cooling-cells = <2>;
-+	};
-+
-+	i2c-gpio-0 {
-+		compatible = "i2c-gpio";
-+		sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
-+		scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		adc@54 {
-+			compatible = "ti,adc101c";
-+			reg = <0x54>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
-+			vref-supply = <&reg_dldo2>;
-+		};
-+	};
-+};
diff --git a/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch b/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch
deleted file mode 100644
index b31537d150..0000000000
--- a/target/linux/d1/patches-6.1/0034-riscv-Add-the-Allwinner-SoC-family-Kconfig-option.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From f648ec2a040efde432876ee04240cb71e4c24d6e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 16 May 2021 14:17:45 -0500
-Subject: [PATCH 034/117] riscv: Add the Allwinner SoC family Kconfig option
-
-Allwinner manufactures the sunxi family of application processors. This
-includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
-SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
-
-The first SoC in the sun20i series is D1, containing a single T-HEAD
-C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
-
-Most peripherals are shared across the entire chip family. In fact, the
-ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
-with the D1s.
-
-This means many existing device drivers can be reused. To facilitate
-this reuse, name the symbol ARCH_SUNXI, since that is what the existing
-drivers have as their dependency.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/Kconfig.socs | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/riscv/Kconfig.socs
-+++ b/arch/riscv/Kconfig.socs
-@@ -1,5 +1,14 @@
- menu "SoC selection"
- 
-+config ARCH_SUNXI
-+	bool "Allwinner sun20i SoCs"
-+	select ERRATA_THEAD if MMU && !XIP_KERNEL
-+	select SIFIVE_PLIC
-+	select SUN4I_TIMER
-+	help
-+	  This enables support for Allwinner sun20i platform hardware,
-+	  including boards based on the D1 and D1s SoCs.
-+
- config SOC_MICROCHIP_POLARFIRE
- 	bool "Microchip PolarFire SoCs"
- 	select MCHP_CLK_MPFS
diff --git a/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch b/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch
deleted file mode 100644
index 2c172c8ad8..0000000000
--- a/target/linux/d1/patches-6.1/0035-riscv-defconfig-Enable-the-Allwinner-D1-platform-and.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From 73f9cc8568b6b821107d5194fa868e922b159091 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 27 Jun 2022 01:33:05 -0500
-Subject: [PATCH 035/117] riscv: defconfig: Enable the Allwinner D1 platform
- and drivers
-
-Now that several D1-based boards are supported, enable the platform in
-our defconfig. Build in the drivers which are necessary to boot, such as
-the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
-and watchdog (which may be left enabled by the bootloader). Other common
-onboard peripherals are enabled as modules.
-
-Cover-letter:
-riscv: Allwinner D1 platform support
-This series adds the Kconfig/defconfig plumbing and devicetrees for a
-range of Allwinner D1-based boards. Many features are already enabled,
-including USB, Ethernet, and WiFi.
-
-The SoC devicetree uses bindings from the following series which have
-not yet been merged:
-- SRAM controller:
-  https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
-- NVMEM cell bits property change:
-  https://lore.kernel.org/lkml/20220814173656.11856-1-samuel@sholland.org/
-- In-package LDO regulators:
-  https://lore.kernel.org/lkml/20220815043436.20170-1-samuel@sholland.org/
-
-All three of these are required to set the correct I/O domain voltages
-in the pin controller, which I would consider important to have in the
-initial version of the devicetree.
-
-The SoC devicetree does contain one small hack to avoid a dependency on
-the audio codec binding, since that is not ready yet: the codec node
-uses a bare "simple-mfd", "syscon" compatible.
-END
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: linux-sunxi@lists.linux.dev
-Series-to: Palmer Dabbelt <palmer@dabbelt.com>
-Series-to: Paul Walmsley <paul.walmsley@sifive.com>
-Series-to: Albert Ou <aou@eecs.berkeley.edu>
-Series-to: linux-riscv@lists.infradead.org
-Series-cc: Rob Herring <robh+dt@kernel.org>
-Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-cc: devicetree@vger.kernel.org
-Series-cc: linux-kernel@vger.kernel.org
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/configs/defconfig
-+++ b/arch/riscv/configs/defconfig
-@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
- CONFIG_EXPERT=y
- # CONFIG_SYSFS_SYSCALL is not set
- CONFIG_PROFILING=y
-+CONFIG_ARCH_SUNXI=y
- CONFIG_SOC_MICROCHIP_POLARFIRE=y
- CONFIG_SOC_SIFIVE=y
- CONFIG_SOC_STARFIVE=y
-@@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
- CONFIG_MACB=y
- CONFIG_E1000E=y
- CONFIG_R8169=y
-+CONFIG_STMMAC_ETH=m
- CONFIG_MICROSEMI_PHY=y
- CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_KEYBOARD_SUN4I_LRADC=m
- CONFIG_SERIAL_8250=y
- CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_DW=y
- CONFIG_SERIAL_OF_PLATFORM=y
- CONFIG_VIRTIO_CONSOLE=y
- CONFIG_HW_RANDOM=y
- CONFIG_HW_RANDOM_VIRTIO=y
-+CONFIG_I2C_MV64XXX=m
- CONFIG_SPI=y
- CONFIG_SPI_SIFIVE=y
-+CONFIG_SPI_SUN6I=y
- # CONFIG_PTP_1588_CLOCK is not set
--CONFIG_GPIOLIB=y
- CONFIG_GPIO_SIFIVE=y
-+CONFIG_WATCHDOG=y
-+CONFIG_SUNXI_WATCHDOG=y
-+CONFIG_REGULATOR=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
- CONFIG_DRM=m
- CONFIG_DRM_RADEON=m
- CONFIG_DRM_NOUVEAU=m
-+CONFIG_DRM_SUN4I=m
- CONFIG_DRM_VIRTIO_GPU=m
- CONFIG_FB=y
- CONFIG_FRAMEBUFFER_CONSOLE=y
-@@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
- CONFIG_USB_OHCI_HCD_PLATFORM=y
- CONFIG_USB_STORAGE=y
- CONFIG_USB_UAS=y
-+CONFIG_USB_MUSB_HDRC=m
-+CONFIG_USB_MUSB_SUNXI=m
-+CONFIG_NOP_USB_XCEIV=m
- CONFIG_MMC=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_PLTFM=y
- CONFIG_MMC_SDHCI_CADENCE=y
- CONFIG_MMC_SPI=y
-+CONFIG_MMC_SUNXI=y
- CONFIG_RTC_CLASS=y
-+CONFIG_RTC_DRV_SUN6I=y
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_SUN6I=m
- CONFIG_VIRTIO_PCI=y
- CONFIG_VIRTIO_BALLOON=y
- CONFIG_VIRTIO_INPUT=y
- CONFIG_VIRTIO_MMIO=y
-+CONFIG_SUN8I_DE2_CCU=m
-+CONFIG_SUN50I_IOMMU=y
- CONFIG_RPMSG_CHAR=y
- CONFIG_RPMSG_CTRL=y
- CONFIG_RPMSG_VIRTIO=y
-+CONFIG_PHY_SUN4I_USB=m
-+CONFIG_NVMEM_SUNXI_SID=y
- CONFIG_EXT4_FS=y
- CONFIG_EXT4_FS_POSIX_ACL=y
- CONFIG_EXT4_FS_SECURITY=y
diff --git a/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch b/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch
deleted file mode 100644
index 0ef4b3c56b..0000000000
--- a/target/linux/d1/patches-6.1/0036-riscv-dts-allwinner-Add-Bluetooth-PCM-audio.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From bf83f1dc034111aac1f23b98d7205d08c7c83208 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:33:25 -0500
-Subject: [PATCH 036/117] riscv: dts: allwinner: Add Bluetooth PCM audio
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 47 +++++++++++++++++++
- 1 file changed, 47 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -22,6 +22,32 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- 
-+	bt_sco_codec: bt-sco-codec {
-+		#sound-dai-cells = <0>;
-+		compatible = "linux,bt-sco";
-+	};
-+
-+	bt-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "Bluetooth";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		simple-audio-card,dai-link@0 {
-+			format = "dsp_a";
-+			frame-master = <&bt_sound_cpu>;
-+			bitclock-master = <&bt_sound_cpu>;
-+
-+			bt_sound_cpu: cpu {
-+				sound-dai = <&i2s1>;
-+			};
-+
-+			codec {
-+				sound-dai = <&bt_sco_codec>;
-+			};
-+		};
-+	};
-+
- 	/*
- 	 * This regulator is PWM-controlled, but the PWM controller is not
- 	 * yet supported, so fix the regulator to its default voltage.
-@@ -169,6 +195,12 @@
- 	};
- };
- 
-+&i2s1 {
-+	pinctrl-0 = <&i2s1_clk_pins>, <&i2s1_din_pin>, <&i2s1_dout_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &mmc0 {
- 	broken-cd;
- 	bus-width = <4>;
-@@ -205,6 +237,21 @@
- 
- &pio {
- 	vcc-pg-supply = <&reg_ldoa>;
-+
-+	i2s1_clk_pins: i2s1-clk-pins {
-+		pins = "PG12", "PG13";
-+		function = "i2s1";
-+	};
-+
-+	i2s1_din_pin: i2s1-din-pin {
-+		pins = "PG14";
-+		function = "i2s1_din";
-+	};
-+
-+	i2s1_dout_pin: i2s1-dout-pin {
-+		pins = "PG15";
-+		function = "i2s1_dout";
-+	};
- };
- 
- &uart0 {
diff --git a/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch
deleted file mode 100644
index 1aee036b10..0000000000
--- a/target/linux/d1/patches-6.1/0037-dt-bindings-crypto-sun8i-ce-Add-compatible-for-D1.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 690b8d708e0193d50522f70359bcab62a2f99742 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 09:04:29 -0600
-Subject: [PATCH 037/117] dt-bindings: crypto: sun8i-ce: Add compatible for D1
-
-D1 has a crypto engine similar to the one in other Allwinner SoCs.
-Like H6, it has a separate MBUS clock gate.
-
-It also requires the internal RC oscillator to be enabled for the TRNG
-to return data. This is likely the case for earlier variants as well,
-but the clock drivers for earlier SoCs did not allow disabling the RC
-oscillator.
-
-Series-changes: 2
- - Add TRNG clock
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/crypto/allwinner,sun8i-ce.yaml   | 31 ++++++++++++++-----
- 1 file changed, 23 insertions(+), 8 deletions(-)
-
---- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
-+++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
-@@ -14,6 +14,7 @@ properties:
-     enum:
-       - allwinner,sun8i-h3-crypto
-       - allwinner,sun8i-r40-crypto
-+      - allwinner,sun20i-d1-crypto
-       - allwinner,sun50i-a64-crypto
-       - allwinner,sun50i-h5-crypto
-       - allwinner,sun50i-h6-crypto
-@@ -29,6 +30,7 @@ properties:
-       - description: Bus clock
-       - description: Module clock
-       - description: MBus clock
-+      - description: TRNG clock (RC oscillator)
-     minItems: 2
- 
-   clock-names:
-@@ -36,6 +38,7 @@ properties:
-       - const: bus
-       - const: mod
-       - const: ram
-+      - const: trng
-     minItems: 2
- 
-   resets:
-@@ -44,19 +47,31 @@ properties:
- if:
-   properties:
-     compatible:
--      const: allwinner,sun50i-h6-crypto
-+      enum:
-+        - allwinner,sun20i-d1-crypto
- then:
-   properties:
-     clocks:
--      minItems: 3
-+      minItems: 4
-     clock-names:
--      minItems: 3
-+      minItems: 4
- else:
--  properties:
--    clocks:
--      maxItems: 2
--    clock-names:
--      maxItems: 2
-+  if:
-+    properties:
-+      compatible:
-+        const: allwinner,sun50i-h6-crypto
-+  then:
-+    properties:
-+      clocks:
-+        minItems: 3
-+      clock-names:
-+        minItems: 3
-+  else:
-+    properties:
-+      clocks:
-+        maxItems: 2
-+      clock-names:
-+        maxItems: 2
- 
- required:
-   - compatible
diff --git a/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch b/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch
deleted file mode 100644
index b8344ce5ce..0000000000
--- a/target/linux/d1/patches-6.1/0038-crypto-sun8i-ce-Add-TRNG-clock-to-D1-variant.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 1 Feb 2022 21:50:16 -0600
-Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant
-
-At least the D1 variant requires a separate clock for the TRNG.
-Without this clock enabled, reading from /dev/hwrng reports:
-
-   sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3
-
-Experimentation shows that the necessary clock is the SoC's internal
-RC oscillator. This makes sense, as the oscillator's frequency
-variations can be used as a source of randomness.
-
-Since D1 does not yet have a device tree, we can update this variant
-without breaking anything.
-
-Series-changes: 2
- - New patch
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
- drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h      | 2 +-
- 2 files changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
-+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
-@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
- 		{ "bus", 0, 200000000 },
- 		{ "mod", 300000000, 0 },
- 		{ "ram", 0, 400000000 },
-+		{ "trng", 0, 0 },
- 		},
- 	.esr = ESR_D1,
- 	.prng = CE_ALG_PRNG,
---- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
-+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
-@@ -105,7 +105,7 @@
- 
- #define MAX_SG 8
- 
--#define CE_MAX_CLOCKS 3
-+#define CE_MAX_CLOCKS 4
- 
- #define MAXFLOW 4
- 
diff --git a/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch b/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch
deleted file mode 100644
index 05289b737c..0000000000
--- a/target/linux/d1/patches-6.1/0039-riscv-dts-allwinner-d1-Add-crypto-engine-support.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 5dae72bf0e0fabb3164dbc4b5eee310c63f1975c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:20:31 -0500
-Subject: [PATCH 039/117] riscv: dts: allwinner: d1: Add crypto engine support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -457,6 +457,18 @@
- 			};
- 		};
- 
-+		crypto: crypto@3040000 {
-+			compatible = "allwinner,sun20i-d1-crypto";
-+			reg = <0x3040000 0x800>;
-+			interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_CE>,
-+				 <&ccu CLK_CE>,
-+				 <&ccu CLK_MBUS_CE>,
-+				 <&rtc CLK_IOSC>;
-+			clock-names = "bus", "mod", "ram", "trng";
-+			resets = <&ccu RST_BUS_CE>;
-+		};
-+
- 		mbus: dram-controller@3102000 {
- 			compatible = "allwinner,sun20i-d1-mbus";
- 			reg = <0x3102000 0x1000>,
diff --git a/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch b/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch
deleted file mode 100644
index abc4608e19..0000000000
--- a/target/linux/d1/patches-6.1/0040-ASoC-sun50i-dmic-dt-bindings-Add-D1-compatible-strin.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 7a24e5ee94e0163801c8ab4c131ae1d530a420ea Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:08:36 -0500
-Subject: [PATCH 040/117] ASoC: sun50i-dmic: dt-bindings: Add D1 compatible
- string
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/sound/allwinner,sun50i-h6-dmic.yaml           | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
-@@ -11,7 +11,12 @@ maintainers:
- 
- properties:
-   compatible:
--    const: allwinner,sun50i-h6-dmic
-+    oneOf:
-+      - items:
-+          - enum:
-+              - allwinner,sun20i-d1-dmic
-+          - const: allwinner,sun50i-h6-dmic
-+      - const: allwinner,sun50i-h6-dmic
- 
-   "#sound-dai-cells":
-     const: 0
diff --git a/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch b/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch
deleted file mode 100644
index 1d838c92bf..0000000000
--- a/target/linux/d1/patches-6.1/0041-riscv-dts-allwinner-d1-Add-DMIC-node.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From d73f2176958e405e55c4e782c6d0f888e20080e5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:08:58 -0500
-Subject: [PATCH 041/117] riscv: dts: allwinner: d1: Add DMIC node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -208,6 +208,21 @@
- 			};
- 		};
- 
-+		dmic: dmic@2031000 {
-+			compatible = "allwinner,sun20i-d1-dmic",
-+				     "allwinner,sun50i-h6-dmic";
-+			reg = <0x2031000 0x400>;
-+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_DMIC>,
-+				 <&ccu CLK_DMIC>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_DMIC>;
-+			dmas = <&dma 8>;
-+			dma-names = "rx";
-+			status = "disabled";
-+			#sound-dai-cells = <0>;
-+		};
-+
- 		i2s0: i2s@2032000 {
- 			compatible = "allwinner,sun20i-d1-i2s",
- 				     "allwinner,sun50i-r329-i2s";
diff --git a/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch b/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch
deleted file mode 100644
index 1aec73b70f..0000000000
--- a/target/linux/d1/patches-6.1/0042-riscv-dts-allwinner-Add-DMIC-sound-cards.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From 500a3fc1ce1b216ef4f4df73e4e048170764189e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:20:49 -0500
-Subject: [PATCH 042/117] riscv: dts: allwinner: Add DMIC sound cards
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-lichee-rv-86-panel.dtsi         | 43 ++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 45 +++++++++++++++++++
- 2 files changed, 88 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -9,6 +9,33 @@
- 		ethernet1 = &xr829;
- 	};
- 
-+	dmic_codec: dmic-codec {
-+		compatible = "dmic-codec";
-+		num-channels = <2>;
-+		#sound-dai-cells = <0>;
-+	};
-+
-+	dmic-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "DMIC";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		simple-audio-card,dai-link@0 {
-+			format = "pdm";
-+			frame-master = <&link0_cpu>;
-+			bitclock-master = <&link0_cpu>;
-+
-+			link0_cpu: cpu {
-+				sound-dai = <&dmic>;
-+			};
-+
-+			link0_codec: codec {
-+				sound-dai = <&dmic_codec>;
-+			};
-+		};
-+	};
-+
- 	/* PC1 is repurposed as BT_WAKE_AP */
- 	/delete-node/ leds;
- 
-@@ -24,6 +51,12 @@
- 	};
- };
- 
-+&dmic {
-+	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &ehci1 {
- 	status = "okay";
- };
-@@ -69,6 +102,16 @@
- 		pins = "PG11";
- 		function = "clk";
- 	};
-+
-+	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
-+		pins = "PB11";
-+		function = "dmic";
-+	};
-+
-+	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
-+		pins = "PE17";
-+		function = "dmic";
-+	};
- };
- 
- &uart1 {
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -15,12 +15,45 @@
- 		ethernet1 = &rtl8723ds;
- 	};
- 
-+	dmic_codec: dmic-codec {
-+		compatible = "dmic-codec";
-+		num-channels = <2>;
-+		#sound-dai-cells = <0>;
-+	};
-+
-+	dmic-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "DMIC";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		simple-audio-card,dai-link@0 {
-+			format = "pdm";
-+			frame-master = <&link0_cpu>;
-+			bitclock-master = <&link0_cpu>;
-+
-+			link0_cpu: cpu {
-+				sound-dai = <&dmic>;
-+			};
-+
-+			link0_codec: codec {
-+				sound-dai = <&dmic_codec>;
-+			};
-+		};
-+	};
-+
- 	wifi_pwrseq: wifi-pwrseq {
- 		compatible = "mmc-pwrseq-simple";
- 		reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
- 	};
- };
- 
-+&dmic {
-+	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &ehci1 {
- 	status = "okay";
- };
-@@ -55,6 +88,18 @@
- 	status = "okay";
- };
- 
-+&pio {
-+	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
-+		pins = "PB11";
-+		function = "dmic";
-+	};
-+
-+	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
-+		pins = "PE17";
-+		function = "dmic";
-+	};
-+};
-+
- &uart1 {
- 	uart-has-rtscts;
- 	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
diff --git a/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch b/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch
deleted file mode 100644
index e7fb887772..0000000000
--- a/target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 7708f7471ab45039e08237b42121d0372f9216a7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:42:19 -0500
-Subject: [PATCH 043/117] hwspinlock: sun6i: Clarify bank counting logic
-
-In some of the most recent datasheets, the register definition was
-updated in a way that resolves the conflict here: the field is only two
-bits wide, and a value of "4" really means a bit pattern of "0". Correct
-the code to reflect this, but leave an updated comment because some
-datasheets still have incorrect information in them.
-
-Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/hwspinlock/sun6i_hwspinlock.c | 36 +++++++++++----------------
- 1 file changed, 14 insertions(+), 22 deletions(-)
-
---- a/drivers/hwspinlock/sun6i_hwspinlock.c
-+++ b/drivers/hwspinlock/sun6i_hwspinlock.c
-@@ -129,30 +129,22 @@ static int sun6i_hwspinlock_probe(struct
- 	}
- 
- 	/*
--	 * bit 28 and 29 represents the hwspinlock setup
-+	 * Bits 28 and 29 represent the number of available locks.
- 	 *
--	 * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1
--	 * to 0x4 represent 32, 64, 128 and 256 locks
--	 * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,
--	 * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks
--	 * all the time, not a single mentioning of 64 locks
--	 * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not
--	 * correct
--	 * one thing have all in common, default value of the sysstatus register is 0x10000000,
--	 * which results in bit 28 being set
--	 * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account
--	 * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)
-+	 * The datasheets have two conflicting interpretations for these bits:
-+	 *   |  00 | 01 |  10 |  11 |
-+	 *   +-----+----+-----+-----+
-+	 *   | 256 | 32 |  64 | 128 | A80, A83T, H3, A64, A50, D1
-+	 *   |  32 | 64 | 128 | 256 | H5, H6, R329
-+	 * where some datasheets use "4" instead of "0" for the first column.
-+	 *
-+	 * Experiments shows that the first interpretation is correct, as all
-+	 * known implementations report the value "1" and have 32 spinlocks.
- 	 */
--	num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
--	switch (num_banks) {
--	case 1 ... 4:
--		priv->nlocks = 1 << (4 + num_banks);
--		break;
--	default:
--		err = -EINVAL;
--		dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
--		goto bank_fail;
--	}
-+	num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28 & 0x3;
-+	if (!num_banks)
-+		num_banks = 4;
-+	priv->nlocks = 1 << (4 + num_banks);
- 
- 	priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
- 				  GFP_KERNEL);
diff --git a/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch b/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch
deleted file mode 100644
index 23adcd3af3..0000000000
--- a/target/linux/d1/patches-6.1/0044-hwspinlock-sun6i-Fix-driver-to-match-binding.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From a19b55088945ce86051ea4eab22df27805a30c71 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:41:44 -0500
-Subject: [PATCH 044/117] hwspinlock: sun6i: Fix driver to match binding
-
-The binding for this device does not allow using the clock-names and
-reset-names properties, so the driver should not reference the clock or
-reset by name.
-
-Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/hwspinlock/sun6i_hwspinlock.c | 12 +++++-------
- 1 file changed, 5 insertions(+), 7 deletions(-)
-
---- a/drivers/hwspinlock/sun6i_hwspinlock.c
-+++ b/drivers/hwspinlock/sun6i_hwspinlock.c
-@@ -104,14 +104,12 @@ static int sun6i_hwspinlock_probe(struct
- 	if (!priv)
- 		return -ENOMEM;
- 
--	priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
--	if (IS_ERR(priv->ahb_clk)) {
--		err = PTR_ERR(priv->ahb_clk);
--		dev_err(&pdev->dev, "unable to get AHB clock (%d)\n", err);
--		return err;
--	}
-+	priv->ahb_clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(priv->ahb_clk))
-+		return dev_err_probe(&pdev->dev, PTR_ERR(priv->ahb_clk),
-+				     "unable to get AHB clock\n");
- 
--	priv->reset = devm_reset_control_get(&pdev->dev, "ahb");
-+	priv->reset = devm_reset_control_get(&pdev->dev, NULL);
- 	if (IS_ERR(priv->reset))
- 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset),
- 				     "unable to get reset control\n");
diff --git a/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch b/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch
deleted file mode 100644
index d2c61a54dd..0000000000
--- a/target/linux/d1/patches-6.1/0045-dt-bindings-hwlock-sun6i-Add-interrupts-property.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From f0c29c5d370507ca2106689e7e17b81e8b58f236 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 11:37:34 -0600
-Subject: [PATCH 045/117] dt-bindings: hwlock: sun6i: Add interrupts property
-
-While it was not officially documented until recently (e.g. A50), the
-hwspinlock block can trigger an interrupt when a lock is unlocked. This
-capability is used by Allwinner's ARISC firmware, it has been verified
-to work on A64, and the IRQ numbers are reserved as far back as A31.
-So most likely this feature has always been available.
-
-Even though the Linux hwspinlock framework cannot make use of the IRQ,
-the capability should still be documented in the device tree.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml     | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-+++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-@@ -26,17 +26,22 @@ properties:
-   resets:
-     maxItems: 1
- 
-+  interrupts:
-+    maxItems: 1
-+
- required:
-   - compatible
-   - reg
-   - clocks
-   - resets
-+  - interrupts
- 
- additionalProperties: false
- 
- examples:
-   - |
-     #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-     #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
- 
-     hwlock@1c18000 {
-@@ -44,5 +49,6 @@ examples:
-         reg = <0x01c18000 0x1000>;
-         clocks = <&ccu CLK_BUS_SPINLOCK>;
-         resets = <&ccu RST_BUS_SPINLOCK>;
-+        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-     };
- ...
diff --git a/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch b/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch
deleted file mode 100644
index 120232b51a..0000000000
--- a/target/linux/d1/patches-6.1/0046-dt-bindings-hwlock-sun6i-Add-per-SoC-compatibles.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From e7b8c42c6bf02f4c2e24b015a12cd9edad094644 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 12:36:52 -0600
-Subject: [PATCH 046/117] dt-bindings: hwlock: sun6i: Add per-SoC compatibles
-
-While all implementations of this hardware appear to be indentical, it
-is possible that some difference exists. To be safe, add a compatible
-for each SoC integration, using the A31 compatible only as a fallback.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../hwlock/allwinner,sun6i-a31-hwspinlock.yaml   | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-+++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-@@ -15,7 +15,21 @@ description:
- 
- properties:
-   compatible:
--    const: allwinner,sun6i-a31-hwspinlock
-+    oneOf:
-+      - items:
-+          - enum:
-+              - allwinner,sun8i-a23-hwspinlock
-+              - allwinner,sun8i-a33-hwspinlock
-+              - allwinner,sun8i-a50-hwspinlock
-+              - allwinner,sun8i-a83t-hwspinlock
-+              - allwinner,sun8i-h3-hwspinlock
-+              - allwinner,sun9i-a80-hwspinlock
-+              - allwinner,sun20i-d1-hwspinlock
-+              - allwinner,sun50i-a64-hwspinlock
-+              - allwinner,sun50i-h6-hwspinlock
-+              - allwinner,sun50i-r329-hwspinlock
-+          - const: allwinner,sun6i-a31-hwspinlock
-+      - const: allwinner,sun6i-a31-hwspinlock
- 
-   reg:
-     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch b/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch
deleted file mode 100644
index c0350455c9..0000000000
--- a/target/linux/d1/patches-6.1/0047-ASoC-sun4i-i2s-Also-set-capture-DMA-width.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 419b337ac3e60126f9de0bc98892e54a8ffe3b6e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:50:57 -0500
-Subject: [PATCH 047/117] ASoC: sun4i-i2s: Also set capture DMA width
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-i2s.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/sound/soc/sunxi/sun4i-i2s.c
-+++ b/sound/soc/sunxi/sun4i-i2s.c
-@@ -633,6 +633,7 @@ static int sun4i_i2s_hw_params(struct sn
- 			params_physical_width(params));
- 		return -EINVAL;
- 	}
-+	i2s->capture_dma_data.addr_width = width;
- 	i2s->playback_dma_data.addr_width = width;
- 
- 	sr = i2s->variant->get_sr(word_size);
diff --git a/target/linux/d1/patches-6.1/0048-todo.patch b/target/linux/d1/patches-6.1/0048-todo.patch
deleted file mode 100644
index b06f37ea37..0000000000
--- a/target/linux/d1/patches-6.1/0048-todo.patch
+++ /dev/null
@@ -1,19 +0,0 @@
-From dbad9a1f280b3c3e34cc133407ae057293b8aadf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:34:08 -0500
-Subject: [PATCH 048/117] todo
-
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -253,6 +253,7 @@
- 			#sound-dai-cells = <0>;
- 		};
- 
-+		// TODO: how to integrate ASRC? same or separate node?
- 		i2s2: i2s@2034000 {
- 			compatible = "allwinner,sun20i-d1-i2s",
- 				     "allwinner,sun50i-r329-i2s";
diff --git a/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch b/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch
deleted file mode 100644
index 63ff6234c8..0000000000
--- a/target/linux/d1/patches-6.1/0049-dt-bindings-iommu-sun50i-Add-compatible-for-Allwinne.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 031deed1d755fc9f1e4908ef70969e1458203421 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:20:38 -0500
-Subject: [PATCH 049/117] dt-bindings: iommu: sun50i: Add compatible for
- Allwinner D1
-
-D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
-variant has no external reset signal.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../iommu/allwinner,sun50i-h6-iommu.yaml         | 16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
-+++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
-@@ -17,7 +17,9 @@ properties:
-       The content of the cell is the master ID.
- 
-   compatible:
--    const: allwinner,sun50i-h6-iommu
-+    enum:
-+      - allwinner,sun20i-d1-iommu
-+      - allwinner,sun50i-h6-iommu
- 
-   reg:
-     maxItems: 1
-@@ -37,7 +39,17 @@ required:
-   - reg
-   - interrupts
-   - clocks
--  - resets
-+
-+if:
-+  properties:
-+    compatible:
-+      contains:
-+        enum:
-+          - allwinner,sun50i-h6-iommu
-+
-+then:
-+  required:
-+    - resets
- 
- additionalProperties: false
- 
diff --git a/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch b/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch
deleted file mode 100644
index 483746a11f..0000000000
--- a/target/linux/d1/patches-6.1/0050-iommu-sun50i-Support-variants-without-an-external-re.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 15a0487680cf506bb4b9bfee2c41b2c3176d4efa Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:01:57 -0500
-Subject: [PATCH 050/117] iommu/sun50i: Support variants without an external
- reset
-
-The IOMMU in the Allwinner D1 SoC does not have an external reset line.
-
-Only attempt to get the reset on hardware variants which should have one
-according to the binding. And switch from the deprecated function to the
-explicit "exclusive" variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 18 ++++++++++++++++--
- 1 file changed, 16 insertions(+), 2 deletions(-)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -95,6 +95,10 @@
- 
- #define SPAGE_SIZE			4096
- 
-+struct sun50i_iommu_variant {
-+	bool has_reset;
-+};
-+
- struct sun50i_iommu {
- 	struct iommu_device iommu;
- 
-@@ -979,9 +983,14 @@ static irqreturn_t sun50i_iommu_irq(int
- 
- static int sun50i_iommu_probe(struct platform_device *pdev)
- {
-+	const struct sun50i_iommu_variant *variant;
- 	struct sun50i_iommu *iommu;
- 	int ret, irq;
- 
-+	variant = of_device_get_match_data(&pdev->dev);
-+	if (!variant)
-+		return -EINVAL;
-+
- 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
- 	if (!iommu)
- 		return -ENOMEM;
-@@ -1021,7 +1030,8 @@ static int sun50i_iommu_probe(struct pla
- 		goto err_free_group;
- 	}
- 
--	iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
-+	if (variant->has_reset)
-+		iommu->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- 	if (IS_ERR(iommu->reset)) {
- 		dev_err(&pdev->dev, "Couldn't get our reset line.\n");
- 		ret = PTR_ERR(iommu->reset);
-@@ -1059,8 +1069,12 @@ err_free_cache:
- 	return ret;
- }
- 
-+static const struct sun50i_iommu_variant sun50i_h6_iommu = {
-+	.has_reset = true,
-+};
-+
- static const struct of_device_id sun50i_iommu_dt[] = {
--	{ .compatible = "allwinner,sun50i-h6-iommu", },
-+	{ .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
- 	{ /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, sun50i_iommu_dt);
diff --git a/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch b/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch
deleted file mode 100644
index 3f2db0054e..0000000000
--- a/target/linux/d1/patches-6.1/0051-iommu-sun50i-Ensure-bypass-is-disabled.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 384e2ca3c049fe36f4e679fc76fcc8dfdc9297f9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:06:28 -0500
-Subject: [PATCH 051/117] iommu/sun50i: Ensure bypass is disabled
-
-The H6 variant of the hardware disables bypass by default. The D1
-variant of the hardware enables bypass for all masters by default.
-
-Since the driver expects bypass to be disabled, ensure that is the case.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -445,6 +445,8 @@ static int sun50i_iommu_enable(struct su
- 
- 	spin_lock_irqsave(&iommu->iommu_lock, flags);
- 
-+	iommu_write(iommu, IOMMU_BYPASS_REG, 0);
-+
- 	iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
- 	iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
- 		    IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
diff --git a/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch b/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch
deleted file mode 100644
index d82542a4a2..0000000000
--- a/target/linux/d1/patches-6.1/0052-iommu-sun50i-Add-support-for-the-D1-variant.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 5fdd5231c56d58f16a6cefa2bed4b8f331da2c92 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:20:58 -0500
-Subject: [PATCH 052/117] iommu/sun50i: Add support for the D1 variant
-
-D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
-variant has no external reset signal. It also has some register
-definition changes, but none that affect the current driver.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -1071,11 +1071,15 @@ err_free_cache:
- 	return ret;
- }
- 
-+static const struct sun50i_iommu_variant sun20i_d1_iommu = {
-+};
-+
- static const struct sun50i_iommu_variant sun50i_h6_iommu = {
- 	.has_reset = true,
- };
- 
- static const struct of_device_id sun50i_iommu_dt[] = {
-+	{ .compatible = "allwinner,sun20i-d1-iommu", .data = &sun20i_d1_iommu },
- 	{ .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
- 	{ /* sentinel */ },
- };
diff --git a/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch b/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch
deleted file mode 100644
index b3a2d53c24..0000000000
--- a/target/linux/d1/patches-6.1/0053-riscv-dts-allwinner-d1-Add-IOMMU-node.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 4c37ac95ee354857c8c662b6b7b4bc50eea23206 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 11:20:37 -0500
-Subject: [PATCH 053/117] riscv: dts: allwinner: d1: Add IOMMU node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -188,6 +188,14 @@
- 			status = "disabled";
- 		};
- 
-+		iommu: iommu@2010000 {
-+			compatible = "allwinner,sun20i-d1-iommu";
-+			reg = <0x2010000 0x10000>;
-+			interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_IOMMU>;
-+			#iommu-cells = <1>;
-+		};
-+
- 		codec: audio-codec@2030000 {
- 			compatible = "simple-mfd", "syscon";
- 			reg = <0x2030000 0x1000>;
-@@ -681,6 +689,7 @@
- 				 <&display_clocks CLK_MIXER0>;
- 			clock-names = "bus", "mod";
- 			resets = <&display_clocks RST_MIXER0>;
-+			iommus = <&iommu 2>;
- 
- 			ports {
- 				#address-cells = <1>;
-@@ -703,6 +712,7 @@
- 				 <&display_clocks CLK_MIXER1>;
- 			clock-names = "bus", "mod";
- 			resets = <&display_clocks RST_MIXER1>;
-+			iommus = <&iommu 2>;
- 
- 			ports {
- 				#address-cells = <1>;
diff --git a/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch b/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch
deleted file mode 100644
index 548a92efb5..0000000000
--- a/target/linux/d1/patches-6.1/0054-dt-bindings-leds-Add-Allwinner-A100-LED-controller.patch
+++ /dev/null
@@ -1,179 +0,0 @@
-From 31857adcc9db7244a047a3a3550219f7559d8846 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 4 Aug 2021 21:36:26 -0500
-Subject: [PATCH 054/117] dt-bindings: leds: Add Allwinner A100 LED controller
-
-The Allwinner A100, R329, and D1 SoCs contain an LED controller designed
-to drive a series of RGB LED pixels. It supports PIO and DMA transfers,
-and has configurable timing and pixel format. All three implementations
-appear to be identical, so use the oldest as the fallback compatible.
-
-Series-changes: 2
- - Fixed typo leading to duplicate t1h-ns property
- - Removed "items" layer in definition of dmas/dma-names
- - Replaced uint32 type reference with maxItems in timing properties
-
-Series-changes: 3
- - Removed quotes from enumeration values
- - Added vendor prefix to timing/format properties
- - Renamed "format" property to "pixel-format" for clarity
- - Dropped "vled-supply" as it is unrelated to the controller hardware
-
-Series-changes: 4
- - Use "default" instead of "maxItems" for timing properties
-
-Series-changes: 5
- - A100 contains the original implementation, so use that as the base
-   compatible string, and rename the binding to match
- - Add "unevaluatedProperties: false" to the child multi-led binding
-
-Acked-by: Maxime Ripard <maxime@cerno.tech>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../leds/allwinner,sun50i-a100-ledc.yaml      | 139 ++++++++++++++++++
- 1 file changed, 139 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
-@@ -0,0 +1,139 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner A100 LED Controller Bindings
-+
-+maintainers:
-+  - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+  The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
-+  interface to drive up to 1024 RGB LEDs.
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - const: allwinner,sun50i-a100-ledc
-+      - items:
-+          - enum:
-+              - allwinner,sun20i-d1-ledc
-+              - allwinner,sun50i-r329-ledc
-+          - const: allwinner,sun50i-a100-ledc
-+
-+  reg:
-+    maxItems: 1
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    items:
-+      - description: Bus clock
-+      - description: Module clock
-+
-+  clock-names:
-+    items:
-+      - const: bus
-+      - const: mod
-+
-+  resets:
-+    maxItems: 1
-+
-+  dmas:
-+    maxItems: 1
-+    description: TX DMA channel
-+
-+  dma-names:
-+    const: tx
-+
-+  allwinner,pixel-format:
-+    description: Pixel format (subpixel transmission order), default is "grb"
-+    enum:
-+      - bgr
-+      - brg
-+      - gbr
-+      - grb
-+      - rbg
-+      - rgb
-+
-+  allwinner,t0h-ns:
-+    default: 336
-+    description: Length of high pulse when transmitting a "0" bit
-+
-+  allwinner,t0l-ns:
-+    default: 840
-+    description: Length of low pulse when transmitting a "0" bit
-+
-+  allwinner,t1h-ns:
-+    default: 882
-+    description: Length of high pulse when transmitting a "1" bit
-+
-+  allwinner,t1l-ns:
-+    default: 294
-+    description: Length of low pulse when transmitting a "1" bit
-+
-+  allwinner,treset-ns:
-+    default: 300000
-+    description: Minimum delay between transmission frames
-+
-+patternProperties:
-+  "^multi-led@[0-9a-f]+$":
-+    type: object
-+    $ref: leds-class-multicolor.yaml#
-+    unevaluatedProperties: false
-+    properties:
-+      reg:
-+        minimum: 0
-+        maximum: 1023
-+        description: Index of the LED in the series (must be contiguous)
-+
-+    required:
-+      - reg
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+  - resets
-+  - dmas
-+  - dma-names
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/leds/common.h>
-+
-+    ledc: led-controller@2008000 {
-+      compatible = "allwinner,sun20i-d1-ledc",
-+                   "allwinner,sun50i-a100-ledc";
-+      reg = <0x2008000 0x400>;
-+      interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-+      clocks = <&ccu 12>, <&ccu 34>;
-+      clock-names = "bus", "mod";
-+      resets = <&ccu 12>;
-+      dmas = <&dma 42>;
-+      dma-names = "tx";
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+
-+      multi-led@0 {
-+        reg = <0x0>;
-+        color = <LED_COLOR_ID_RGB>;
-+        function = LED_FUNCTION_INDICATOR;
-+      };
-+    };
-+
-+...
diff --git a/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch b/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch
deleted file mode 100644
index 4c2cab557a..0000000000
--- a/target/linux/d1/patches-6.1/0055-leds-sun50i-a100-New-driver-for-the-A100-LED-control.patch
+++ /dev/null
@@ -1,620 +0,0 @@
-From 352b296d30df06b880d2c7620910cd759dc2609d Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 26 Jun 2021 11:02:49 -0500
-Subject: [PATCH 055/117] leds: sun50i-a100: New driver for the A100 LED
- controller
-
-Some Allwinner sunxi SoCs, starting with the A100, contain an LED
-controller designed to drive RGB LED pixels. Add a driver for it using
-the multicolor LED framework, and with LEDs defined in the device tree.
-
-Series-changes: 2
- - Renamed from sunxi-ledc to sun50i-r329-ledc
- - Added missing "static" to functions/globals as reported by 0day bot
-
-Series-changes: 3
- - Added vendor prefix to timing/format properties
- - Renamed "format" property to "pixel-format" for clarity
- - Dropped "vled-supply" as it is unrelated to the controller hardware
- - Changed "writesl" to "iowrite32_rep" so the driver builds on hppa
-
-Series-changes: 4
- - Depend on LEDS_CLASS_MULTICOLOR
-
-Series-changes: 5
- - Rename the driver R329 -> A100, since that is the actual original
-   implementation
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/leds/Kconfig            |   9 +
- drivers/leds/Makefile           |   1 +
- drivers/leds/leds-sun50i-a100.c | 554 ++++++++++++++++++++++++++++++++
- 3 files changed, 564 insertions(+)
- create mode 100644 drivers/leds/leds-sun50i-a100.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ
- 	help
- 	  This option enables support for the Cobalt Raq series LEDs.
- 
-+config LEDS_SUN50I_A100
-+	tristate "LED support for Allwinner A100 RGB LED controller"
-+	depends on LEDS_CLASS_MULTICOLOR && OF
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	help
-+	  This option enables support for the RGB LED controller found
-+	  in some Allwinner sunxi SoCs, includeing A100, R329, and D1.
-+	  It uses a one-wire interface to control up to 1024 LEDs.
-+
- config LEDS_SUNFIRE
- 	tristate "LED support for SunFire servers."
- 	depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SUN50I_A100)		+= leds-sun50i-a100.o
- obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o
---- /dev/null
-+++ b/drivers/leds/leds-sun50i-a100.c
-@@ -0,0 +1,554 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
-+//
-+// Partly based on drivers/leds/leds-turris-omnia.c, which is:
-+//     Copyright (c) 2020 by Marek Behún <kabel@kernel.org>
-+//
-+
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/led-class-multicolor.h>
-+#include <linux/leds.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm.h>
-+#include <linux/reset.h>
-+#include <linux/spinlock.h>
-+
-+#define LEDC_CTRL_REG			0x0000
-+#define LEDC_CTRL_REG_DATA_LENGTH		(0x1fff << 16)
-+#define LEDC_CTRL_REG_RGB_MODE			(0x7 << 6)
-+#define LEDC_CTRL_REG_LEDC_EN			BIT(0)
-+#define LEDC_T01_TIMING_CTRL_REG	0x0004
-+#define LEDC_T01_TIMING_CTRL_REG_T1H		(0x3f << 21)
-+#define LEDC_T01_TIMING_CTRL_REG_T1L		(0x1f << 16)
-+#define LEDC_T01_TIMING_CTRL_REG_T0H		(0x1f << 6)
-+#define LEDC_T01_TIMING_CTRL_REG_T0L		(0x3f << 0)
-+#define LEDC_RESET_TIMING_CTRL_REG	0x000c
-+#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM	(0x3ff << 0)
-+#define LEDC_DATA_REG			0x0014
-+#define LEDC_DMA_CTRL_REG		0x0018
-+#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL	(0x1f << 0)
-+#define LEDC_INT_CTRL_REG		0x001c
-+#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN		BIT(5)
-+#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN	BIT(1)
-+#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN	BIT(0)
-+#define LEDC_INT_STS_REG		0x0020
-+#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT	BIT(1)
-+#define LEDC_INT_STS_REG_TRANS_FINISH_INT	BIT(0)
-+
-+#define LEDC_FIFO_DEPTH			32
-+#define LEDC_MAX_LEDS			1024
-+
-+#define LEDS_TO_BYTES(n)		((n) * sizeof(u32))
-+
-+struct sun50i_a100_ledc_led {
-+	struct led_classdev_mc mc_cdev;
-+	struct mc_subled subled_info[3];
-+};
-+
-+#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)
-+
-+struct sun50i_a100_ledc_timing {
-+	u32 t0h_ns;
-+	u32 t0l_ns;
-+	u32 t1h_ns;
-+	u32 t1l_ns;
-+	u32 treset_ns;
-+};
-+
-+struct sun50i_a100_ledc {
-+	struct device *dev;
-+	void __iomem *base;
-+	struct clk *bus_clk;
-+	struct clk *mod_clk;
-+	struct reset_control *reset;
-+
-+	u32 *buffer;
-+	struct dma_chan *dma_chan;
-+	dma_addr_t dma_handle;
-+	int pio_length;
-+	int pio_offset;
-+
-+	spinlock_t lock;
-+	int next_length;
-+	bool xfer_active;
-+
-+	u32 format;
-+	struct sun50i_a100_ledc_timing timing;
-+
-+	int num_leds;
-+	struct sun50i_a100_ledc_led leds[];
-+};
-+
-+static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, int length)
-+{
-+	struct dma_async_tx_descriptor *desc;
-+	dma_cookie_t cookie;
-+
-+	desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle,
-+					   LEDS_TO_BYTES(length),
-+					   DMA_MEM_TO_DEV, 0);
-+	if (!desc)
-+		return -ENOMEM;
-+
-+	cookie = dmaengine_submit(desc);
-+	if (dma_submit_error(cookie))
-+		return -EIO;
-+
-+	dma_async_issue_pending(priv->dma_chan);
-+
-+	return 0;
-+}
-+
-+static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, int length)
-+{
-+	u32 burst, offset, val;
-+
-+	if (length) {
-+		/* New transfer (FIFO is empty). */
-+		offset = 0;
-+		burst  = min(length, LEDC_FIFO_DEPTH);
-+	} else {
-+		/* Existing transfer (FIFO is half-full). */
-+		length = priv->pio_length;
-+		offset = priv->pio_offset;
-+		burst  = min(length, LEDC_FIFO_DEPTH / 2);
-+	}
-+
-+	iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst);
-+
-+	if (burst < length) {
-+		priv->pio_length = length - burst;
-+		priv->pio_offset = offset + burst;
-+
-+		if (!offset) {
-+			val = readl(priv->base + LEDC_INT_CTRL_REG);
-+			val |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
-+			writel(val, priv->base + LEDC_INT_CTRL_REG);
-+		}
-+	} else {
-+		/* Disable the request IRQ once all data is written. */
-+		val = readl(priv->base + LEDC_INT_CTRL_REG);
-+		val &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
-+		writel(val, priv->base + LEDC_INT_CTRL_REG);
-+	}
-+}
-+
-+static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv,
-+					int length)
-+{
-+	u32 val;
-+
-+	dev_dbg(priv->dev, "Updating %d LEDs\n", length);
-+
-+	val = readl(priv->base + LEDC_CTRL_REG);
-+	val &= ~LEDC_CTRL_REG_DATA_LENGTH;
-+	val |= length << 16 | LEDC_CTRL_REG_LEDC_EN;
-+	writel(val, priv->base + LEDC_CTRL_REG);
-+
-+	if (length > LEDC_FIFO_DEPTH) {
-+		int ret = sun50i_a100_ledc_dma_xfer(priv, length);
-+
-+		if (!ret)
-+			return;
-+
-+		dev_warn(priv->dev, "Failed to set up DMA: %d\n", ret);
-+	}
-+
-+	sun50i_a100_ledc_pio_xfer(priv, length);
-+}
-+
-+static irqreturn_t sun50i_a100_ledc_irq(int irq, void *dev_id)
-+{
-+	struct sun50i_a100_ledc *priv = dev_id;
-+	u32 val;
-+
-+	val = readl(priv->base + LEDC_INT_STS_REG);
-+
-+	if (val & LEDC_INT_STS_REG_TRANS_FINISH_INT) {
-+		int next_length;
-+
-+		/* Start the next transfer if needed. */
-+		spin_lock(&priv->lock);
-+		next_length = priv->next_length;
-+		if (next_length)
-+			priv->next_length = 0;
-+		else
-+			priv->xfer_active = false;
-+		spin_unlock(&priv->lock);
-+
-+		if (next_length)
-+			sun50i_a100_ledc_start_xfer(priv, next_length);
-+	} else if (val & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {
-+		/* Continue the current transfer. */
-+		sun50i_a100_ledc_pio_xfer(priv, 0);
-+	}
-+
-+	writel(val, priv->base + LEDC_INT_STS_REG);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,
-+					    enum led_brightness brightness)
-+{
-+	struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent);
-+	struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
-+	struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);
-+	int addr = led - priv->leds;
-+	unsigned long flags;
-+	bool xfer_active;
-+	int next_length;
-+
-+	led_mc_calc_color_components(mc_cdev, brightness);
-+
-+	priv->buffer[addr] = led->subled_info[0].brightness << 16 |
-+			     led->subled_info[1].brightness <<  8 |
-+			     led->subled_info[2].brightness;
-+
-+	dev_dbg(priv->dev, "LED %d -> #%06x\n", addr, priv->buffer[addr]);
-+
-+	spin_lock_irqsave(&priv->lock, flags);
-+	next_length = max(priv->next_length, addr + 1);
-+	xfer_active = priv->xfer_active;
-+	if (xfer_active)
-+		priv->next_length = next_length;
-+	else
-+		priv->xfer_active = true;
-+	spin_unlock_irqrestore(&priv->lock, flags);
-+
-+	if (!xfer_active)
-+		sun50i_a100_ledc_start_xfer(priv, next_length);
-+}
-+
-+static const char *const sun50i_a100_ledc_formats[] = {
-+	"rgb",
-+	"rbg",
-+	"grb",
-+	"gbr",
-+	"brg",
-+	"bgr",
-+};
-+
-+static int sun50i_a100_ledc_parse_format(const struct device_node *np,
-+					 struct sun50i_a100_ledc *priv)
-+{
-+	const char *format = "grb";
-+	u32 i;
-+
-+	of_property_read_string(np, "allwinner,pixel-format", &format);
-+
-+	for (i = 0; i < ARRAY_SIZE(sun50i_a100_ledc_formats); ++i) {
-+		if (!strcmp(format, sun50i_a100_ledc_formats[i])) {
-+			priv->format = i;
-+			return 0;
-+		}
-+	}
-+
-+	dev_err(priv->dev, "Bad pixel format '%s'\n", format);
-+
-+	return -EINVAL;
-+}
-+
-+static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)
-+{
-+	u32 val;
-+
-+	val = readl(priv->base + LEDC_CTRL_REG);
-+	val &= ~LEDC_CTRL_REG_RGB_MODE;
-+	val |= priv->format << 6;
-+	writel(val, priv->base + LEDC_CTRL_REG);
-+}
-+
-+static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {
-+	.t0h_ns = 336,
-+	.t0l_ns = 840,
-+	.t1h_ns = 882,
-+	.t1l_ns = 294,
-+	.treset_ns = 300000,
-+};
-+
-+static int sun50i_a100_ledc_parse_timing(const struct device_node *np,
-+					 struct sun50i_a100_ledc *priv)
-+{
-+	struct sun50i_a100_ledc_timing *timing = &priv->timing;
-+
-+	*timing = sun50i_a100_ledc_default_timing;
-+
-+	of_property_read_u32(np, "allwinner,t0h-ns", &timing->t0h_ns);
-+	of_property_read_u32(np, "allwinner,t0l-ns", &timing->t0l_ns);
-+	of_property_read_u32(np, "allwinner,t1h-ns", &timing->t1h_ns);
-+	of_property_read_u32(np, "allwinner,t1l-ns", &timing->t1l_ns);
-+	of_property_read_u32(np, "allwinner,treset-ns", &timing->treset_ns);
-+
-+	return 0;
-+}
-+
-+static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)
-+{
-+	const struct sun50i_a100_ledc_timing *timing = &priv->timing;
-+	unsigned long mod_freq = clk_get_rate(priv->mod_clk);
-+	u32 cycle_ns = NSEC_PER_SEC / mod_freq;
-+	u32 val;
-+
-+	val = (timing->t1h_ns / cycle_ns) << 21 |
-+	      (timing->t1l_ns / cycle_ns) << 16 |
-+	      (timing->t0h_ns / cycle_ns) <<  6 |
-+	      (timing->t0l_ns / cycle_ns);
-+	writel(val, priv->base + LEDC_T01_TIMING_CTRL_REG);
-+
-+	val = (timing->treset_ns / cycle_ns) << 16 |
-+	      (priv->num_leds - 1);
-+	writel(val, priv->base + LEDC_RESET_TIMING_CTRL_REG);
-+}
-+
-+static int sun50i_a100_ledc_resume(struct device *dev)
-+{
-+	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
-+	u32 val;
-+	int ret;
-+
-+	ret = reset_control_deassert(priv->reset);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(priv->bus_clk);
-+	if (ret)
-+		goto err_assert_reset;
-+
-+	ret = clk_prepare_enable(priv->mod_clk);
-+	if (ret)
-+		goto err_disable_bus_clk;
-+
-+	sun50i_a100_ledc_set_format(priv);
-+	sun50i_a100_ledc_set_timing(priv);
-+
-+	/* The trigger level must be at least the burst length. */
-+	val = readl(priv->base + LEDC_DMA_CTRL_REG);
-+	val &= ~LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL;
-+	val |= LEDC_FIFO_DEPTH / 2;
-+	writel(val, priv->base + LEDC_DMA_CTRL_REG);
-+
-+	val = LEDC_INT_CTRL_REG_GLOBAL_INT_EN |
-+	      LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN;
-+	writel(val, priv->base + LEDC_INT_CTRL_REG);
-+
-+	return 0;
-+
-+err_disable_bus_clk:
-+	clk_disable_unprepare(priv->bus_clk);
-+err_assert_reset:
-+	reset_control_assert(priv->reset);
-+
-+	return ret;
-+}
-+
-+static int sun50i_a100_ledc_suspend(struct device *dev)
-+{
-+	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
-+
-+	clk_disable_unprepare(priv->mod_clk);
-+	clk_disable_unprepare(priv->bus_clk);
-+	reset_control_assert(priv->reset);
-+
-+	return 0;
-+}
-+
-+static void sun50i_a100_ledc_dma_cleanup(void *data)
-+{
-+	struct sun50i_a100_ledc *priv = data;
-+	struct device *dma_dev = dmaengine_get_dma_device(priv->dma_chan);
-+
-+	if (priv->buffer)
-+		dma_free_wc(dma_dev, LEDS_TO_BYTES(priv->num_leds),
-+			    priv->buffer, priv->dma_handle);
-+	dma_release_channel(priv->dma_chan);
-+}
-+
-+static int sun50i_a100_ledc_probe(struct platform_device *pdev)
-+{
-+	const struct device_node *np = pdev->dev.of_node;
-+	struct dma_slave_config dma_cfg = {};
-+	struct led_init_data init_data = {};
-+	struct device *dev = &pdev->dev;
-+	struct device_node *child;
-+	struct sun50i_a100_ledc *priv;
-+	struct resource *mem;
-+	int count, irq, ret;
-+
-+	count = of_get_available_child_count(np);
-+	if (!count)
-+		return -ENODEV;
-+	if (count > LEDC_MAX_LEDS) {
-+		dev_err(dev, "Too many LEDs! (max is %d)\n", LEDC_MAX_LEDS);
-+		return -EINVAL;
-+	}
-+
-+	priv = devm_kzalloc(dev, struct_size(priv, leds, count), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->dev = dev;
-+	priv->num_leds = count;
-+	spin_lock_init(&priv->lock);
-+	dev_set_drvdata(dev, priv);
-+
-+	ret = sun50i_a100_ledc_parse_format(np, priv);
-+	if (ret)
-+		return ret;
-+
-+	ret = sun50i_a100_ledc_parse_timing(np, priv);
-+	if (ret)
-+		return ret;
-+
-+	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
-+	if (IS_ERR(priv->base))
-+		return PTR_ERR(priv->base);
-+
-+	priv->bus_clk = devm_clk_get(dev, "bus");
-+	if (IS_ERR(priv->bus_clk))
-+		return PTR_ERR(priv->bus_clk);
-+
-+	priv->mod_clk = devm_clk_get(dev, "mod");
-+	if (IS_ERR(priv->mod_clk))
-+		return PTR_ERR(priv->mod_clk);
-+
-+	priv->reset = devm_reset_control_get_exclusive(dev, NULL);
-+	if (IS_ERR(priv->reset))
-+		return PTR_ERR(priv->reset);
-+
-+	priv->dma_chan = dma_request_chan(dev, "tx");
-+	if (IS_ERR(priv->dma_chan))
-+		return PTR_ERR(priv->dma_chan);
-+
-+	ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);
-+	if (ret)
-+		return ret;
-+
-+	dma_cfg.dst_addr	= mem->start + LEDC_DATA_REG;
-+	dma_cfg.dst_addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES;
-+	dma_cfg.dst_maxburst	= LEDC_FIFO_DEPTH / 2;
-+	ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
-+	if (ret)
-+		return ret;
-+
-+	priv->buffer = dma_alloc_wc(dmaengine_get_dma_device(priv->dma_chan),
-+				    LEDS_TO_BYTES(priv->num_leds),
-+				    &priv->dma_handle, GFP_KERNEL);
-+	if (!priv->buffer)
-+		return -ENOMEM;
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq,
-+			       0, dev_name(dev), priv);
-+	if (ret)
-+		return ret;
-+
-+	ret = sun50i_a100_ledc_resume(dev);
-+	if (ret)
-+		return ret;
-+
-+	for_each_available_child_of_node(np, child) {
-+		struct sun50i_a100_ledc_led *led;
-+		struct led_classdev *cdev;
-+		u32 addr, color;
-+
-+		ret = of_property_read_u32(child, "reg", &addr);
-+		if (ret || addr >= count) {
-+			dev_err(dev, "LED 'reg' values must be from 0 to %d\n",
-+				priv->num_leds - 1);
-+			ret = -EINVAL;
-+			goto err_put_child;
-+		}
-+
-+		ret = of_property_read_u32(child, "color", &color);
-+		if (ret || color != LED_COLOR_ID_RGB) {
-+			dev_err(dev, "LED 'color' must be LED_COLOR_ID_RGB\n");
-+			ret = -EINVAL;
-+			goto err_put_child;
-+		}
-+
-+		led = &priv->leds[addr];
-+
-+		led->subled_info[0].color_index = LED_COLOR_ID_RED;
-+		led->subled_info[0].channel = 0;
-+		led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
-+		led->subled_info[1].channel = 1;
-+		led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
-+		led->subled_info[2].channel = 2;
-+
-+		led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info);
-+		led->mc_cdev.subled_info = led->subled_info;
-+
-+		cdev = &led->mc_cdev.led_cdev;
-+		cdev->max_brightness = U8_MAX;
-+		cdev->brightness_set = sun50i_a100_ledc_brightness_set;
-+
-+		init_data.fwnode = of_fwnode_handle(child);
-+
-+		ret = devm_led_classdev_multicolor_register_ext(dev,
-+								&led->mc_cdev,
-+								&init_data);
-+		if (ret) {
-+			dev_err(dev, "Failed to register LED %u: %d\n",
-+				addr, ret);
-+			goto err_put_child;
-+		}
-+	}
-+
-+	dev_info(dev, "Registered %d LEDs\n", priv->num_leds);
-+
-+	return 0;
-+
-+err_put_child:
-+	of_node_put(child);
-+	sun50i_a100_ledc_suspend(&pdev->dev);
-+
-+	return ret;
-+}
-+
-+static int sun50i_a100_ledc_remove(struct platform_device *pdev)
-+{
-+	sun50i_a100_ledc_suspend(&pdev->dev);
-+
-+	return 0;
-+}
-+
-+static void sun50i_a100_ledc_shutdown(struct platform_device *pdev)
-+{
-+	sun50i_a100_ledc_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id sun50i_a100_ledc_of_match[] = {
-+	{ .compatible = "allwinner,sun50i-a100-ledc" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);
-+
-+static SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,
-+			 sun50i_a100_ledc_suspend, sun50i_a100_ledc_resume);
-+
-+static struct platform_driver sun50i_a100_ledc_driver = {
-+	.probe		= sun50i_a100_ledc_probe,
-+	.remove		= sun50i_a100_ledc_remove,
-+	.shutdown	= sun50i_a100_ledc_shutdown,
-+	.driver		= {
-+		.name		= "sun50i-a100-ledc",
-+		.of_match_table	= sun50i_a100_ledc_of_match,
-+		.pm		= pm_ptr(&sun50i_a100_ledc_pm),
-+	},
-+};
-+module_platform_driver(sun50i_a100_ledc_driver);
-+
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_DESCRIPTION("Allwinner A100 LED controller driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch b/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch
deleted file mode 100644
index 92fa2a31ee..0000000000
--- a/target/linux/d1/patches-6.1/0056-arm64-dts-allwinner-a100-Add-LED-controller-node.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 0040f071ab45d3098b2aad7e28e07593a5740782 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 25 Aug 2022 23:19:40 -0500
-Subject: [PATCH 056/117] arm64: dts: allwinner: a100: Add LED controller node
-
-Allwinner A100 contains an LED controller. Add it to the devicetree.
-
-Commit-changes: 5
- - New patch for v5
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
-@@ -273,6 +273,20 @@
- 			#size-cells = <0>;
- 		};
- 
-+		ledc: led-controller@5018000 {
-+			compatible = "allwinner,sun50i-a100-ledc";
-+			reg = <0x5018000 0x400>;
-+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_LEDC>;
-+			dmas = <&dma 42>;
-+			dma-names = "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		ths: thermal-sensor@5070400 {
- 			compatible = "allwinner,sun50i-a100-ths";
- 			reg = <0x05070400 0x100>;
diff --git a/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch b/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch
deleted file mode 100644
index f6a04113b1..0000000000
--- a/target/linux/d1/patches-6.1/0057-riscv-dts-allwinner-d1-Add-LED-controller-node.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 595f76548e1d51a76b1ab201293ef441233921cf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 23:02:43 -0500
-Subject: [PATCH 057/117] riscv: dts: allwinner: d1: Add LED controller node
-
-Allwinner D1 contains an LED controller. Add its devicetree node, as
-well as the pinmux used by the reference board design.
-
-Commit-changes: 5
- - New patch for v5
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 21 ++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -116,6 +116,12 @@
- 			};
- 
- 			/omit-if-no-ref/
-+			ledc_pc0_pin: ledc-pc0-pin {
-+				pins = "PC0";
-+				function = "ledc";
-+			};
-+
-+			/omit-if-no-ref/
- 			mmc0_pins: mmc0-pins {
- 				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
- 				function = "mmc0";
-@@ -178,6 +184,21 @@
- 			#reset-cells = <1>;
- 		};
- 
-+		ledc: led-controller@2008000 {
-+			compatible = "allwinner,sun20i-d1-ledc",
-+				     "allwinner,sun50i-a100-ledc";
-+			reg = <0x2008000 0x400>;
-+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_LEDC>;
-+			dmas = <&dma 42>;
-+			dma-names = "tx";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		lradc: keys@2009800 {
- 			compatible = "allwinner,sun20i-d1-lradc",
- 				     "allwinner,sun50i-r329-lradc";
diff --git a/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch b/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch
deleted file mode 100644
index 901cb0daf8..0000000000
--- a/target/linux/d1/patches-6.1/0058-riscv-dts-allwinner-d1-Add-RGB-LEDs-to-boards.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From e6eb041b2099ec3d07a4ec391a06e86d7697c9d1 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 23:03:01 -0500
-Subject: [PATCH 058/117] riscv: dts: allwinner: d1: Add RGB LEDs to boards
-
-Some D1-based boards feature an onboard RGB LED. Enable them.
-
-Commit-changes: 5
- - New patch for v5
-
-Series-version: 5
-
-Series-to: Pavel Machek <pavel@ucw.cz>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: linux-leds@vger.kernel.org
-Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-cc: Rob Herring <robh+dt@kernel.org>
-Series-cc: devicetree@vger.kernel.org
-Series-cc: linux-arm-kernel@lists.infradead.org
-Series-cc: linux-kernel@vger.kernel.org
-Series-cc: linux-riscv@lists.infradead.org
-Series-cc: linux-sunxi@lists.linux.dev
-
-Cover-letter:
-leds: Allwinner A100 LED controller support
-This series adds bindings and a driver for the RGB LED controller found
-in some Allwinner SoCs, starting with A100. The hardware in the R329 and
-D1 SoCs appears to be identical.
-
-Patch 3 is included because the LED controller binding requires the DMA
-properties. That patch was sent previously[1], but never got merged.
-
-Patches 5-6 depend on the D1 devicetree series[2], but the rest of this
-series can be merged without them.
-
-This driver was tested on the D1 Nezha board.
-
-[1]: https://lore.kernel.org/linux-arm-kernel/20201110040553.1381-7-frank@allwinnertech.com/
-[2]: https://lore.kernel.org/linux-riscv/20220815050815.22340-1-samuel@sholland.org/
-END
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts   | 13 +++++++++++++
- 2 files changed, 25 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -58,6 +58,18 @@
- 	status = "okay";
- };
- 
-+&ledc {
-+	pinctrl-0 = <&ledc_pc0_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	multi-led@0 {
-+		reg = <0x0>;
-+		color = <LED_COLOR_ID_RGB>;
-+		function = LED_FUNCTION_STATUS;
-+	};
-+};
-+
- &lradc {
- 	status = "okay";
- 
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -5,6 +5,7 @@
- 
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
- 
- #include "sun20i-d1.dtsi"
- #include "sun20i-d1-common-regulators.dtsi"
-@@ -90,6 +91,18 @@
- 	};
- };
- 
-+&ledc {
-+	pinctrl-0 = <&ledc_pc0_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	multi-led@0 {
-+		reg = <0x0>;
-+		color = <LED_COLOR_ID_RGB>;
-+		function = LED_FUNCTION_STATUS;
-+	};
-+};
-+
- &lradc {
- 	status = "okay";
- 
diff --git a/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch b/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch
deleted file mode 100644
index 4ec15bce0c..0000000000
--- a/target/linux/d1/patches-6.1/0059-pwm-sun8i-v536-document-device-tree-bindings.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From effa2ef8717b0390e8fb0648e16df1b43610af53 Mon Sep 17 00:00:00 2001
-From: Ban Tao <fengzheng923@gmail.com>
-Date: Tue, 2 Mar 2021 20:40:23 +0800
-Subject: [PATCH 059/117] pwm: sun8i-v536: document device tree bindings
-
-This adds binding documentation for sun8i-v536 SoC PWM driver.
-
-Signed-off-by: Ban Tao <fengzheng923@gmail.com>
----
- .../bindings/pwm/pwm-sun8i-v536.txt           | 24 +++++++++++++++++++
- 1 file changed, 24 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
-@@ -0,0 +1,24 @@
-+Allwinner sun8i-v536 SoC PWM controller
-+
-+Required properties:
-+ - compatible: should be "allwinner,<name>-pwm"
-+   "allwinner,sun8i-v833-pwm"
-+   "allwinner,sun8i-v536-pwm"
-+   "allwinner,sun50i-r818-pwm"
-+   "allwinner,sun50i-a133-pwm"
-+   "allwinner,sun50i-r329-pwm"
-+ - reg: physical base address and length of the controller's registers
-+ - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
-+   the cells format.
-+ - clocks: From common clock binding, handle to the parent clock.
-+ - resets: From reset clock binding, handle to the parent clock.
-+
-+Example:
-+
-+	pwm: pwm@300a0000 {
-+		compatible = "allwinner,sun50i-r818-pwm";
-+		reg = <0x0300a000 0x3ff>;
-+		clocks = <&ccu CLK_BUS_PWM>;
-+		resets = <&ccu RST_BUS_PWM>;
-+		#pwm-cells = <3>;
-+	};
diff --git a/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch b/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch
deleted file mode 100644
index 8c5d290c49..0000000000
--- a/target/linux/d1/patches-6.1/0060-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-driver.patch
+++ /dev/null
@@ -1,466 +0,0 @@
-From 4919e67557eaebb9f155950e7cac547a507b59e5 Mon Sep 17 00:00:00 2001
-From: Ban Tao <fengzheng923@gmail.com>
-Date: Tue, 2 Mar 2021 20:37:37 +0800
-Subject: [PATCH 060/117] pwm: sunxi: Add Allwinner SoC PWM controller driver
-
-The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
-IP compared to the older Allwinner SoCs.
-
-Signed-off-by: Ban Tao <fengzheng923@gmail.com>
----
- MAINTAINERS                  |   6 +
- drivers/pwm/Kconfig          |  11 +
- drivers/pwm/Makefile         |   1 +
- drivers/pwm/pwm-sun8i-v536.c | 401 +++++++++++++++++++++++++++++++++++
- 4 files changed, 419 insertions(+)
- create mode 100644 drivers/pwm/pwm-sun8i-v536.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -802,6 +802,12 @@ S:	Maintained
- F:	Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
- F:	drivers/hwspinlock/sun6i_hwspinlock.c
- 
-+ALLWINNER PWM DRIVER
-+M:	Ban Tao <fengzheng923@gmail.com>
-+L:	linux-pwm@vger.kernel.org
-+S:	Maintained
-+F:	drivers/pwm/pwm-sun8i-v536.c
-+
- ALLWINNER THERMAL DRIVER
- M:	Vasily Khoruzhick <anarsoul@gmail.com>
- M:	Yangtao Li <tiny.windzz@gmail.com>
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -582,6 +582,17 @@ config PWM_SUN4I
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called pwm-sun4i.
- 
-+config PWM_SUN8I_V536
-+	tristate "Allwinner SUN8I_V536 PWM support"
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	depends on HAS_IOMEM && COMMON_CLK
-+	help
-+	  Enhanced PWM framework driver for Allwinner R818, A133, R329,
-+	  V536 and V833 SoCs.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called pwm-sun8i-v536.
-+
- config PWM_SUNPLUS
- 	tristate "Sunplus PWM support"
- 	depends on ARCH_SUNPLUS || COMPILE_TEST
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
- obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
- obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
- obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
-+obj-$(CONFIG_PWM_SUN8I_V536)	+= pwm-sun8i-v536.o
- obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
- obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
- obj-$(CONFIG_PWM_TIECAP)	+= pwm-tiecap.o
---- /dev/null
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -0,0 +1,401 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Driver for Allwinner sun8i-v536 Pulse Width Modulation Controller
-+ *
-+ * Copyright (C) 2021 Ban Tao <fengzheng923@gmail.com>
-+ *
-+ *
-+ * Limitations:
-+ * - When PWM is disabled, the output is driven to inactive.
-+ * - If the register is reconfigured while PWM is running,
-+ *   it does not complete the currently running period.
-+ * - If the user input duty is beyond acceptible limits,
-+ *   -EINVAL is returned.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/pwm.h>
-+#include <linux/clk.h>
-+#include <linux/reset.h>
-+
-+#define PWM_GET_CLK_OFFSET(chan)	(0x20 + ((chan >> 1) * 0x4))
-+#define PWM_CLK_APB_SCR			BIT(7)
-+#define PWM_DIV_M			0
-+#define PWM_DIV_M_MASK			GENMASK(3, PWM_DIV_M)
-+
-+#define PWM_CLK_REG			0x40
-+#define PWM_CLK_GATING			BIT(0)
-+
-+#define PWM_ENABLE_REG			0x80
-+#define PWM_EN				BIT(0)
-+
-+#define PWM_CTL_REG(chan)		(0x100 + 0x20 * chan)
-+#define PWM_ACT_STA			BIT(8)
-+#define PWM_PRESCAL_K			0
-+#define PWM_PRESCAL_K_MASK		GENMASK(7, PWM_PRESCAL_K)
-+
-+#define PWM_PERIOD_REG(chan)		(0x104 + 0x20 * chan)
-+#define PWM_ENTIRE_CYCLE			16
-+#define PWM_ENTIRE_CYCLE_MASK		GENMASK(31, PWM_ENTIRE_CYCLE)
-+#define PWM_ACT_CYCLE			0
-+#define PWM_ACT_CYCLE_MASK		GENMASK(15, PWM_ACT_CYCLE)
-+
-+#define BIT_CH(bit, chan)		((bit) << (chan))
-+#define SET_BITS(shift, mask, reg, val) \
-+	    (((reg) & ~mask) | (val << (shift)))
-+
-+#define PWM_OSC_CLK			24000000
-+#define PWM_PRESCALER_MAX		256
-+#define PWM_CLK_DIV_M__MAX		9
-+#define PWM_ENTIRE_CYCLE_MAX		65536
-+
-+struct sun8i_pwm_data {
-+	unsigned int npwm;
-+};
-+
-+struct sun8i_pwm_chip {
-+	struct pwm_chip chip;
-+	struct clk *clk;
-+	struct reset_control *rst_clk;
-+	void __iomem *base;
-+	const struct sun8i_pwm_data *data;
-+};
-+
-+static inline struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip)
-+{
-+	return container_of(chip, struct sun8i_pwm_chip, chip);
-+}
-+
-+static inline u32 sun8i_pwm_readl(struct sun8i_pwm_chip *chip,
-+				   unsigned long offset)
-+{
-+	return readl(chip->base + offset);
-+}
-+
-+static inline void sun8i_pwm_writel(struct sun8i_pwm_chip *chip,
-+				     u32 val, unsigned long offset)
-+{
-+	writel(val, chip->base + offset);
-+}
-+
-+static void sun8i_pwm_get_state(struct pwm_chip *chip,
-+				 struct pwm_device *pwm,
-+				 struct pwm_state *state)
-+{
-+	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+	u64 clk_rate;
-+	u32 tmp, entire_cycles, active_cycles;
-+	unsigned int prescaler, div_m;
-+
-+	tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+	if (tmp & PWM_CLK_APB_SCR)
-+		clk_rate = clk_get_rate(pc->clk);
-+	else
-+		clk_rate = PWM_OSC_CLK;
-+
-+	tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+	div_m = 0x1 << (tmp & PWM_DIV_M_MASK);
-+
-+	tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+	prescaler = (tmp & PWM_PRESCAL_K_MASK) + 1;
-+
-+	tmp = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
-+	entire_cycles = (tmp >> PWM_ENTIRE_CYCLE) + 1;
-+	active_cycles = (tmp & PWM_ACT_CYCLE_MASK);
-+
-+	/* (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns. */
-+	state->period = DIV_ROUND_CLOSEST_ULL(entire_cycles * NSEC_PER_SEC,
-+					      clk_rate) * div_m * prescaler;
-+	/* duty_ns / period_ns = active_cycles / entire_cycles. */
-+	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(active_cycles * state->period,
-+						  entire_cycles);
-+
-+	/* parsing polarity */
-+	tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+	if (tmp & PWM_ACT_STA)
-+		state->polarity = PWM_POLARITY_NORMAL;
-+	else
-+		state->polarity = PWM_POLARITY_INVERSED;
-+
-+	/* parsing enabled */
-+	tmp = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
-+	if (tmp & BIT_CH(PWM_EN, pwm->hwpwm))
-+		state->enabled = true;
-+	else
-+		state->enabled = false;
-+
-+	dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld polarity=%s enabled=%s.\n",
-+				state->duty_cycle, state->period,
-+				state->polarity ? "inversed":"normal",
-+				state->enabled ? "true":"false");
-+}
-+
-+static void sun8i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
-+				    enum pwm_polarity polarity)
-+{
-+	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+	u32 temp;
-+
-+	temp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+
-+	if (polarity == PWM_POLARITY_NORMAL)
-+		temp |= PWM_ACT_STA;
-+	else
-+		temp &= ~PWM_ACT_STA;
-+
-+	sun8i_pwm_writel(pc, temp, PWM_CTL_REG(pwm->hwpwm));
-+}
-+
-+static int sun8i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-+			      const struct pwm_state *state)
-+{
-+	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+	unsigned long long c;
-+	unsigned long entire_cycles, active_cycles;
-+	unsigned int div_m, prescaler;
-+	u64 duty_ns = state->duty_cycle, period_ns = state->period;
-+	u32 config;
-+	int ret = 0;
-+
-+	if (period_ns > 334) {
-+		/* if freq < 3M, then select 24M clock */
-+		c = PWM_OSC_CLK;
-+		config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+		config &= ~PWM_CLK_APB_SCR;
-+		sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+	} else {
-+		/* if freq > 3M, then select APB as clock */
-+		c = clk_get_rate(pc->clk);
-+		config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+		config |= PWM_CLK_APB_SCR;
-+		sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+	}
-+
-+	dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld c =%llu.\n",
-+			duty_ns, period_ns, c);
-+
-+	/*
-+	 * (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns.
-+	 * So, entire_cycles = clk * period_ns / NSEC_PER_SEC / div_m / prescaler.
-+	 */
-+	c = c * period_ns;
-+	c = DIV_ROUND_CLOSEST_ULL(c, NSEC_PER_SEC);
-+	for (div_m = 0; div_m < PWM_CLK_DIV_M__MAX; div_m++) {
-+		for (prescaler = 0; prescaler < PWM_PRESCALER_MAX; prescaler++) {
-+			/*
-+			 * actual prescaler = prescaler(reg value) + 1.
-+			 * actual div_m = 0x1 << div_m(reg value).
-+			 */
-+			entire_cycles = ((unsigned long)c >> div_m)/(prescaler + 1);
-+			if (entire_cycles <= PWM_ENTIRE_CYCLE_MAX)
-+				goto calc_end;
-+		}
-+	}
-+	ret = -EINVAL;
-+	goto exit;
-+
-+calc_end:
-+	/*
-+	 * duty_ns / period_ns = active_cycles / entire_cycles.
-+	 * So, active_cycles = entire_cycles * duty_ns / period_ns.
-+	 */
-+	c = (unsigned long long)entire_cycles * duty_ns;
-+	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
-+	active_cycles = c;
-+	if (entire_cycles == 0)
-+		entire_cycles++;
-+
-+	/* config  clk div_m*/
-+	config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+	config = SET_BITS(PWM_DIV_M, PWM_DIV_M_MASK, config, div_m);
-+	sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+
-+	/* config prescaler */
-+	config = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+	config = SET_BITS(PWM_PRESCAL_K, PWM_PRESCAL_K_MASK, config, prescaler);
-+	sun8i_pwm_writel(pc, config, PWM_CTL_REG(pwm->hwpwm));
-+
-+	/* config active and period cycles */
-+	config = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
-+	config = SET_BITS(PWM_ACT_CYCLE, PWM_ACT_CYCLE_MASK, config, active_cycles);
-+	config = SET_BITS(PWM_ENTIRE_CYCLE, PWM_ENTIRE_CYCLE_MASK,
-+			config, (entire_cycles - 1));
-+	sun8i_pwm_writel(pc, config, PWM_PERIOD_REG(pwm->hwpwm));
-+
-+	dev_dbg(chip->dev, "active_cycles=%lu entire_cycles=%lu prescaler=%u div_m=%u\n",
-+			   active_cycles, entire_cycles, prescaler, div_m);
-+
-+exit:
-+	return ret;
-+}
-+
-+static void sun8i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
-+			     bool enable)
-+{
-+	struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+	u32 clk, pwm_en;
-+
-+	clk = sun8i_pwm_readl(pc, PWM_CLK_REG);
-+	pwm_en = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
-+
-+	if (enable) {
-+		clk |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+		sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
-+
-+		pwm_en |= BIT_CH(PWM_EN, pwm->hwpwm);
-+		sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
-+	} else {
-+		pwm_en &= ~BIT_CH(PWM_EN, pwm->hwpwm);
-+		sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
-+
-+		clk &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+		sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
-+	}
-+}
-+
-+static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
-+			      const struct pwm_state *state)
-+{
-+	struct pwm_state curstate;
-+	int ret;
-+
-+	pwm_get_state(pwm, &curstate);
-+
-+	ret = sun8i_pwm_config(chip, pwm, state);
-+
-+	if (state->polarity != curstate.polarity)
-+		sun8i_pwm_set_polarity(chip, pwm, state->polarity);
-+
-+	if (state->enabled != curstate.enabled)
-+		sun8i_pwm_enable(chip, pwm, state->enabled);
-+
-+	return ret;
-+}
-+
-+static const struct pwm_ops sun8i_pwm_ops = {
-+	.get_state = sun8i_pwm_get_state,
-+	.apply = sun8i_pwm_apply,
-+	.owner = THIS_MODULE,
-+};
-+
-+static const struct sun8i_pwm_data sun8i_pwm_data_c9 = {
-+	.npwm = 9,
-+};
-+
-+static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
-+	.npwm = 16,
-+};
-+
-+static const struct of_device_id sun8i_pwm_dt_ids[] = {
-+	{
-+		.compatible = "allwinner,sun8i-v536-pwm",
-+		.data = &sun8i_pwm_data_c9,
-+	}, {
-+		.compatible = "allwinner,sun50i-r818-pwm",
-+		.data = &sun50i_pwm_data_c16,
-+	}, {
-+		/* sentinel */
-+	},
-+};
-+MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids);
-+
-+static int sun8i_pwm_probe(struct platform_device *pdev)
-+{
-+	struct sun8i_pwm_chip *pc;
-+	int ret;
-+
-+	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
-+	if (!pc)
-+		return dev_err_probe(&pdev->dev, -ENOMEM,
-+				     "memory allocation failed\n");
-+
-+	pc->data = of_device_get_match_data(&pdev->dev);
-+	if (!pc->data)
-+		return dev_err_probe(&pdev->dev, -ENODEV,
-+				     "can't get match data\n");
-+
-+	pc->base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(pc->base))
-+		return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
-+				     "can't remap pwm resource\n");
-+
-+	pc->clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(pc->clk))
-+		return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
-+				     "get clock failed\n");
-+
-+	pc->rst_clk = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-+	if (IS_ERR(pc->rst_clk))
-+		return dev_err_probe(&pdev->dev, PTR_ERR(pc->rst_clk),
-+				     "get reset failed\n");
-+
-+	/* Deassert reset */
-+	ret = reset_control_deassert(pc->rst_clk);
-+	if (ret < 0)
-+		return dev_err_probe(&pdev->dev, ret,
-+				     "cannot deassert reset control\n");
-+
-+	ret = clk_prepare_enable(pc->clk);
-+	if (ret) {
-+		dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
-+			ERR_PTR(ret));
-+		goto err_clk;
-+	}
-+
-+	pc->chip.dev = &pdev->dev;
-+	pc->chip.ops = &sun8i_pwm_ops;
-+	pc->chip.npwm = pc->data->npwm;
-+	pc->chip.of_xlate = of_pwm_xlate_with_flags;
-+	pc->chip.base = -1;
-+	pc->chip.of_pwm_n_cells = 3;
-+
-+	ret = pwmchip_add(&pc->chip);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
-+		goto err_pwm_add;
-+	}
-+
-+	platform_set_drvdata(pdev, pc);
-+
-+	return 0;
-+
-+err_pwm_add:
-+	clk_disable_unprepare(pc->clk);
-+err_clk:
-+	reset_control_assert(pc->rst_clk);
-+
-+	return ret;
-+}
-+
-+static int sun8i_pwm_remove(struct platform_device *pdev)
-+{
-+	struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
-+	int ret;
-+
-+	ret = pwmchip_remove(&pc->chip);
-+	if (ret)
-+		return ret;
-+
-+	clk_disable_unprepare(pc->clk);
-+	reset_control_assert(pc->rst_clk);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver sun8i_pwm_driver = {
-+	.driver = {
-+		.name = "sun8i-pwm-v536",
-+		.of_match_table = sun8i_pwm_dt_ids,
-+	},
-+	.probe = sun8i_pwm_probe,
-+	.remove = sun8i_pwm_remove,
-+};
-+module_platform_driver(sun8i_pwm_driver);
-+
-+MODULE_ALIAS("platform:sun8i-v536-pwm");
-+MODULE_AUTHOR("Ban Tao <fengzheng923@gmail.com>");
-+MODULE_DESCRIPTION("Allwinner sun8i-v536 PWM driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch b/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch
deleted file mode 100644
index 0eac89797d..0000000000
--- a/target/linux/d1/patches-6.1/0061-squash-pwm-sunxi-Add-Allwinner-SoC-PWM-controller-dr.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 2f452dd6047126c42a0ad32ef0f10145c6047d66 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 11:05:20 -0500
-Subject: [PATCH 061/117] squash? pwm: sunxi: Add Allwinner SoC PWM controller
- driver
-
----
- drivers/pwm/Kconfig          | 4 ++--
- drivers/pwm/pwm-sun8i-v536.c | 6 +-----
- 2 files changed, 3 insertions(+), 7 deletions(-)
-
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -583,11 +583,11 @@ config PWM_SUN4I
- 	  will be called pwm-sun4i.
- 
- config PWM_SUN8I_V536
--	tristate "Allwinner SUN8I_V536 PWM support"
-+	tristate "Allwinner SUN8I V536 enhanced PWM support"
- 	depends on ARCH_SUNXI || COMPILE_TEST
- 	depends on HAS_IOMEM && COMMON_CLK
- 	help
--	  Enhanced PWM framework driver for Allwinner R818, A133, R329,
-+	  Enhanced PWM framework driver for Allwinner A133, D1, R329, R818,
- 	  V536 and V833 SoCs.
- 
- 	  To compile this driver as a module, choose M here: the module
---- a/drivers/pwm/pwm-sun8i-v536.c
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -373,12 +373,8 @@ err_clk:
- static int sun8i_pwm_remove(struct platform_device *pdev)
- {
- 	struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
--	int ret;
--
--	ret = pwmchip_remove(&pc->chip);
--	if (ret)
--		return ret;
- 
-+	pwmchip_remove(&pc->chip);
- 	clk_disable_unprepare(pc->clk);
- 	reset_control_assert(pc->rst_clk);
- 
diff --git a/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch b/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch
deleted file mode 100644
index d9df6e6681..0000000000
--- a/target/linux/d1/patches-6.1/0062-pwm-sun8i-v536-Add-support-for-the-Allwinner-D1.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 8bb576d8640fdf896650a4d4a1b2e60254d75eb2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:56:25 -0500
-Subject: [PATCH 062/117] pwm: sun8i-v536: Add support for the Allwinner D1
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/pwm/pwm-sun8i-v536.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/pwm/pwm-sun8i-v536.c
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -285,6 +285,10 @@ static const struct sun8i_pwm_data sun8i
- 	.npwm = 9,
- };
- 
-+static const struct sun8i_pwm_data sun20i_pwm_data_c8 = {
-+	.npwm = 8,
-+};
-+
- static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
- 	.npwm = 16,
- };
-@@ -294,6 +298,9 @@ static const struct of_device_id sun8i_p
- 		.compatible = "allwinner,sun8i-v536-pwm",
- 		.data = &sun8i_pwm_data_c9,
- 	}, {
-+		.compatible = "allwinner,sun20i-d1-pwm",
-+		.data = &sun20i_pwm_data_c8,
-+	}, {
- 		.compatible = "allwinner,sun50i-r818-pwm",
- 		.data = &sun50i_pwm_data_c16,
- 	}, {
diff --git a/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch b/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch
deleted file mode 100644
index f353c6f91b..0000000000
--- a/target/linux/d1/patches-6.1/0063-riscv-dts-allwinner-d1-Add-PWM-support.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 2ee8994e4db3978261e6c644e897400c4df5edeb Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:24:52 -0500
-Subject: [PATCH 063/117] riscv: dts: allwinner: d1: Add PWM support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 35 ++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -155,6 +155,30 @@
- 			};
- 
- 			/omit-if-no-ref/
-+			pwm0_pd16_pin: pwm0-pd16-pin {
-+				pins = "PD16";
-+				function = "pwm0";
-+			};
-+
-+			/omit-if-no-ref/
-+			pwm2_pd18_pin: pwm2-pd18-pin {
-+				pins = "PD18";
-+				function = "pwm2";
-+			};
-+
-+			/omit-if-no-ref/
-+			pwm4_pd20_pin: pwm4-pd20-pin {
-+				pins = "PD20";
-+				function = "pwm4";
-+			};
-+
-+			/omit-if-no-ref/
-+			pwm7_pd22_pin: pwm7-pd22-pin {
-+				pins = "PD22";
-+				function = "pwm7";
-+			};
-+
-+			/omit-if-no-ref/
- 			uart0_pb8_pins: uart0-pb8-pins {
- 				pins = "PB8", "PB9";
- 				function = "uart0";
-@@ -173,6 +197,17 @@
- 			};
- 		};
- 
-+		pwm: pwm@2000c00 {
-+			compatible = "allwinner,sun20i-d1-pwm";
-+			reg = <0x2000c00 0x400>;
-+			interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_PWM>, <&osc24M>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_PWM>;
-+			status = "disabled";
-+			#pwm-cells = <3>;
-+		};
-+
- 		ccu: clock-controller@2001000 {
- 			compatible = "allwinner,sun20i-d1-ccu";
- 			reg = <0x2001000 0x1000>;
diff --git a/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch b/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch
deleted file mode 100644
index ff61b07d93..0000000000
--- a/target/linux/d1/patches-6.1/0064-riscv-dts-allwinner-d1-Hook-up-PWM-controlled-CPU-vo.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From 5479c8efb6ffbbc8b7fd1068337037faf9c20a36 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:25:40 -0500
-Subject: [PATCH 064/117] riscv: dts: allwinner: d1: Hook up PWM-controlled CPU
- voltage regulators
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 19 +++++++++++--------
- .../sun20i-d1-dongshan-nezha-stu.dts          | 19 +++++++++++--------
- .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 19 +++++++++++--------
- 3 files changed, 33 insertions(+), 24 deletions(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -48,16 +48,13 @@
- 		};
- 	};
- 
--	/*
--	 * This regulator is PWM-controlled, but the PWM controller is not
--	 * yet supported, so fix the regulator to its default voltage.
--	 */
- 	reg_vdd_cpu: vdd-cpu {
--		compatible = "regulator-fixed";
-+		compatible = "pwm-regulator";
-+		pwms = <&pwm 0 50000 0>;
-+		pwm-supply = <&reg_vcc>;
- 		regulator-name = "vdd-cpu";
--		regulator-min-microvolt = <1100000>;
--		regulator-max-microvolt = <1100000>;
--		vin-supply = <&reg_vcc>;
-+		regulator-min-microvolt = <810000>;
-+		regulator-max-microvolt = <1160000>;
- 	};
- 
- 	wifi_pwrseq: wifi-pwrseq {
-@@ -254,6 +251,12 @@
- 	};
- };
- 
-+&pwm {
-+	pinctrl-0 = <&pwm0_pd16_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-0 = <&uart0_pb8_pins>;
- 	pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-@@ -43,16 +43,13 @@
- 		vin-supply = <&reg_vcc>;
- 	};
- 
--	/*
--	 * This regulator is PWM-controlled, but the PWM controller is not
--	 * yet supported, so fix the regulator to its default voltage.
--	 */
- 	reg_vdd_cpu: vdd-cpu {
--		compatible = "regulator-fixed";
-+		compatible = "pwm-regulator";
-+		pwms = <&pwm 0 50000 0>;
-+		pwm-supply = <&reg_vcc>;
- 		regulator-name = "vdd-cpu";
--		regulator-min-microvolt = <1100000>;
--		regulator-max-microvolt = <1100000>;
--		vin-supply = <&reg_vcc>;
-+		regulator-min-microvolt = <810000>;
-+		regulator-max-microvolt = <1160000>;
- 	};
- };
- 
-@@ -95,6 +92,12 @@
- 	status = "okay";
- };
- 
-+&pwm {
-+	pinctrl-0 = <&pwm0_pd16_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-0 = <&uart0_pb8_pins>;
- 	pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -35,16 +35,13 @@
- 		vin-supply = <&reg_vcc>;
- 	};
- 
--	/*
--	 * This regulator is PWM-controlled, but the PWM controller is not
--	 * yet supported, so fix the regulator to its default voltage.
--	 */
- 	reg_vdd_cpu: vdd-cpu {
--		compatible = "regulator-fixed";
-+		compatible = "pwm-regulator";
-+		pwms = <&pwm 0 50000 0>;
-+		pwm-supply = <&reg_vcc>;
- 		regulator-name = "vdd-cpu";
--		regulator-min-microvolt = <1100000>;
--		regulator-max-microvolt = <1100000>;
--		vin-supply = <&reg_vcc>;
-+		regulator-min-microvolt = <810000>;
-+		regulator-max-microvolt = <1160000>;
- 	};
- 
- 	wifi_pwrseq: wifi-pwrseq {
-@@ -155,6 +152,12 @@
- 	status = "okay";
- };
- 
-+&pwm {
-+	pinctrl-0 = <&pwm0_pd16_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-0 = <&uart0_pb8_pins>;
- 	pinctrl-names = "default";
diff --git a/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch b/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch
deleted file mode 100644
index f184bd2136..0000000000
--- a/target/linux/d1/patches-6.1/0065-riscv-dts-allwinner-mangopi-mq-pro-Add-PWM-LED.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 29360e65c326ea8bbac6e63b42aa91fb8f14d3bf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:57:13 -0500
-Subject: [PATCH 065/117] riscv: dts: allwinner: mangopi-mq-pro: Add PWM LED
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts  | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-@@ -4,6 +4,7 @@
- /dts-v1/;
- 
- #include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
- 
- #include "sun20i-d1.dtsi"
- #include "sun20i-d1-common-regulators.dtsi"
-@@ -22,6 +23,17 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- 
-+	leds {
-+		compatible = "pwm-leds";
-+
-+		led {
-+			color = <LED_COLOR_ID_BLUE>;
-+			function = LED_FUNCTION_STATUS;
-+			max-brightness = <255>;
-+			pwms = <&pwm 2 50000 0>;
-+		};
-+	};
-+
- 	reg_avdd2v8: avdd2v8 {
- 		compatible = "regulator-fixed";
- 		regulator-name = "avdd2v8";
diff --git a/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch b/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch
deleted file mode 100644
index 0d27224ac3..0000000000
--- a/target/linux/d1/patches-6.1/0066-ASoC-dt-bindings-sun4i-spdif-Require-resets-for-H6.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From bccb19038038c7377275d74bb815f5f9363ba2e3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 10:08:41 -0600
-Subject: [PATCH 066/117] ASoC: dt-bindings: sun4i-spdif: Require resets for H6
-
-The H6 variant has a module reset, and it is used by the driver. So the
-resets property should be required in the binding for this variant.
-
-Fixes: b20453031472 ("dt-bindings: sound: sun4i-spdif: Add Allwinner H6 compatible")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml     | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-@@ -61,6 +61,7 @@ allOf:
-             enum:
-               - allwinner,sun6i-a31-spdif
-               - allwinner,sun8i-h3-spdif
-+              - allwinner,sun50i-h6-spdif
- 
-     then:
-       required:
diff --git a/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch
deleted file mode 100644
index 5c7e21954f..0000000000
--- a/target/linux/d1/patches-6.1/0067-ASoC-dt-bindings-sun4i-spdif-Add-compatible-for-D1.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 4e72722bfb7dec028e11278a924bb8bef3e10897 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 10:48:24 -0600
-Subject: [PATCH 067/117] ASoC: dt-bindings: sun4i-spdif: Add compatible for D1
-
-D1 mostly keeps the existing register layout, but it separates the
-module clock into separate clocks for the RX block and the TX block.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sound/allwinner,sun4i-a10-spdif.yaml      | 54 +++++++++++++++----
- 1 file changed, 44 insertions(+), 10 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-@@ -18,10 +18,12 @@ properties:
- 
-   compatible:
-     oneOf:
--      - const: allwinner,sun4i-a10-spdif
--      - const: allwinner,sun6i-a31-spdif
--      - const: allwinner,sun8i-h3-spdif
--      - const: allwinner,sun50i-h6-spdif
-+      - enum:
-+          - allwinner,sun4i-a10-spdif
-+          - allwinner,sun6i-a31-spdif
-+          - allwinner,sun8i-h3-spdif
-+          - allwinner,sun20i-d1-spdif
-+          - allwinner,sun50i-h6-spdif
-       - items:
-           - const: allwinner,sun8i-a83t-spdif
-           - const: allwinner,sun8i-h3-spdif
-@@ -36,14 +38,12 @@ properties:
-     maxItems: 1
- 
-   clocks:
--    items:
--      - description: Bus Clock
--      - description: Module Clock
-+    minItems: 2
-+    maxItems: 3
- 
-   clock-names:
--    items:
--      - const: apb
--      - const: spdif
-+    minItems: 2
-+    maxItems: 3
- 
-   # Even though it only applies to subschemas under the conditionals,
-   # not listing them here will trigger a warning because of the
-@@ -59,8 +59,42 @@ allOf:
-         compatible:
-           contains:
-             enum:
-+              - allwinner,sun20i-d1-spdif
-+
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: Bus Clock
-+            - description: RX Module Clock
-+            - description: TX Module Clock
-+
-+        clock-names:
-+          items:
-+            - const: apb
-+            - const: rx
-+            - const: tx
-+
-+    else:
-+      properties:
-+        clocks:
-+          items:
-+            - description: Bus Clock
-+            - description: Module Clock
-+
-+        clock-names:
-+          items:
-+            - const: apb
-+            - const: spdif
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-               - allwinner,sun6i-a31-spdif
-               - allwinner,sun8i-h3-spdif
-+              - allwinner,sun20i-d1-spdif
-               - allwinner,sun50i-h6-spdif
- 
-     then:
diff --git a/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch b/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch
deleted file mode 100644
index 06d2f4892f..0000000000
--- a/target/linux/d1/patches-6.1/0068-ASoC-sun4i-spdif-Assert-reset-when-removing-the-devi.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 1d85b3609cf4239f7e971b839f1ab985413cd560 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 11:12:14 -0600
-Subject: [PATCH 068/117] ASoC: sun4i-spdif: Assert reset when removing the
- device
-
-This completes reversing the process done in the probe function.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -710,10 +710,14 @@ err_unregister:
- 
- static int sun4i_spdif_remove(struct platform_device *pdev)
- {
-+	struct sun4i_spdif_dev *host = dev_get_drvdata(&pdev->dev);
-+
- 	pm_runtime_disable(&pdev->dev);
- 	if (!pm_runtime_status_suspended(&pdev->dev))
- 		sun4i_spdif_runtime_suspend(&pdev->dev);
- 
-+	reset_control_assert(host->rst);
-+
- 	return 0;
- }
- 
diff --git a/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch b/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch
deleted file mode 100644
index 42d59bc92d..0000000000
--- a/target/linux/d1/patches-6.1/0069-ASoC-sun4i-spdif-Simplify-code-around-optional-reset.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 0efd742482dbe4b17a441eab5c57231d65f9a852 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 11:14:30 -0600
-Subject: [PATCH 069/117] ASoC: sun4i-spdif: Simplify code around optional
- resets
-
-The driver does not need to care about which variants have a reset;
-the devicetree binding already enforces that the necessary resources are
-provided. Simplify the logic by always calling the optional getter,
-which will return NULL if no reset reference is found.
-
-Also clean up the error handling, which should not print a misleading
-error in the EPROBE_DEFER case.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 22 ++++++----------------
- 1 file changed, 6 insertions(+), 16 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -170,12 +170,10 @@
-  * struct sun4i_spdif_quirks - Differences between SoC variants.
-  *
-  * @reg_dac_txdata: TX FIFO offset for DMA config.
-- * @has_reset: SoC needs reset deasserted.
-  * @val_fctl_ftx: TX FIFO flush bitmask.
-  */
- struct sun4i_spdif_quirks {
- 	unsigned int reg_dac_txdata;
--	bool has_reset;
- 	unsigned int val_fctl_ftx;
- };
- 
-@@ -546,19 +544,16 @@ static const struct sun4i_spdif_quirks s
- static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
- 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
--	.has_reset	= true,
- };
- 
- static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
- 	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
--	.has_reset	= true,
- };
- 
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
- 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
--	.has_reset      = true,
- };
- 
- static const struct of_device_id sun4i_spdif_of_match[] = {
-@@ -672,17 +667,12 @@ static int sun4i_spdif_probe(struct plat
- 
- 	platform_set_drvdata(pdev, host);
- 
--	if (quirks->has_reset) {
--		host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
--								      NULL);
--		if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
--			ret = -EPROBE_DEFER;
--			dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
--			return ret;
--		}
--		if (!IS_ERR(host->rst))
--			reset_control_deassert(host->rst);
--	}
-+	host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
-+	if (IS_ERR(host->rst))
-+		return dev_err_probe(&pdev->dev, PTR_ERR(host->rst),
-+				     "Failed to get reset\n");
-+
-+	reset_control_deassert(host->rst);
- 
- 	ret = devm_snd_soc_register_component(&pdev->dev,
- 				&sun4i_spdif_component, &sun4i_spdif_dai, 1);
diff --git a/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch b/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch
deleted file mode 100644
index 91262eca03..0000000000
--- a/target/linux/d1/patches-6.1/0070-ASoC-sun4i-spdif-Add-support-for-separate-RX-TX-cloc.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From b42a9e0cf6b0ca78b4ef5310de967d515a3cca03 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:53:16 -0500
-Subject: [PATCH 070/117] ASoC: sun4i-spdif: Add support for separate RX/TX
- clocks
-
-On older variants of the hardware, the RX and TX blocks share a single
-module clock, named "spdif" in the DT binding. The D1 variant has
-separate RX and TX clocks, so the TX module clock is named "tx" in the
-binding. To support this, supply the clock name in the quirks structure.
-
-Since the driver supports only TX, only the TX clock name is needed.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 24 +++++++++++++++---------
- 1 file changed, 15 insertions(+), 9 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -169,18 +169,20 @@
- /**
-  * struct sun4i_spdif_quirks - Differences between SoC variants.
-  *
-+ * @tx_clk_name: firmware name for the TX clock reference.
-  * @reg_dac_txdata: TX FIFO offset for DMA config.
-  * @val_fctl_ftx: TX FIFO flush bitmask.
-  */
- struct sun4i_spdif_quirks {
-+	const char *tx_clk_name;
- 	unsigned int reg_dac_txdata;
- 	unsigned int val_fctl_ftx;
- };
- 
- struct sun4i_spdif_dev {
- 	struct platform_device *pdev;
--	struct clk *spdif_clk;
- 	struct clk *apb_clk;
-+	struct clk *tx_clk;
- 	struct reset_control *rst;
- 	struct snd_soc_dai_driver cpu_dai_drv;
- 	struct regmap *regmap;
-@@ -313,7 +315,7 @@ static int sun4i_spdif_hw_params(struct
- 		return -EINVAL;
- 	}
- 
--	ret = clk_set_rate(host->spdif_clk, mclk);
-+	ret = clk_set_rate(host->tx_clk, mclk);
- 	if (ret < 0) {
- 		dev_err(&pdev->dev,
- 			"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
-@@ -537,21 +539,25 @@ static struct snd_soc_dai_driver sun4i_s
- };
- 
- static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
-+	.tx_clk_name	= "spdif",
- 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
- };
- 
- static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
-+	.tx_clk_name	= "spdif",
- 	.reg_dac_txdata	= SUN4I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
- };
- 
- static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
-+	.tx_clk_name	= "spdif",
- 	.reg_dac_txdata	= SUN8I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
- };
- 
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
-+	.tx_clk_name	= "spdif",
- 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- 	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
- };
-@@ -591,7 +597,7 @@ static int sun4i_spdif_runtime_suspend(s
- {
- 	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
- 
--	clk_disable_unprepare(host->spdif_clk);
-+	clk_disable_unprepare(host->tx_clk);
- 	clk_disable_unprepare(host->apb_clk);
- 
- 	return 0;
-@@ -602,12 +608,12 @@ static int sun4i_spdif_runtime_resume(st
- 	struct sun4i_spdif_dev *host  = dev_get_drvdata(dev);
- 	int ret;
- 
--	ret = clk_prepare_enable(host->spdif_clk);
-+	ret = clk_prepare_enable(host->tx_clk);
- 	if (ret)
- 		return ret;
- 	ret = clk_prepare_enable(host->apb_clk);
- 	if (ret)
--		clk_disable_unprepare(host->spdif_clk);
-+		clk_disable_unprepare(host->tx_clk);
- 
- 	return ret;
- }
-@@ -655,10 +661,10 @@ static int sun4i_spdif_probe(struct plat
- 		return PTR_ERR(host->apb_clk);
- 	}
- 
--	host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
--	if (IS_ERR(host->spdif_clk)) {
--		dev_err(&pdev->dev, "failed to get a spdif clock.\n");
--		return PTR_ERR(host->spdif_clk);
-+	host->tx_clk = devm_clk_get(&pdev->dev, quirks->tx_clk_name);
-+	if (IS_ERR(host->tx_clk)) {
-+		dev_err(&pdev->dev, "failed to get TX module clock.\n");
-+		return PTR_ERR(host->tx_clk);
- 	}
- 
- 	host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
diff --git a/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch b/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch
deleted file mode 100644
index 022e319ab0..0000000000
--- a/target/linux/d1/patches-6.1/0071-ASoC-sun4i-spdif-Add-support-for-the-D1-variant.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From af01261bf4e334cad158519291e5bc38765c955f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:53:26 -0500
-Subject: [PATCH 071/117] ASoC: sun4i-spdif: Add support for the D1 variant
-
-The D1 variant is similar to the H6 variant, except for its clock setup.
-The clock tree changes impact some register fields on the RX side, but
-those are not yet relevant, because RX is not supported by this driver.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -556,6 +556,12 @@ static const struct sun4i_spdif_quirks s
- 	.val_fctl_ftx   = SUN4I_SPDIF_FCTL_FTX,
- };
- 
-+static const struct sun4i_spdif_quirks sun20i_d1_spdif_quirks = {
-+	.tx_clk_name	= "tx",
-+	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
-+	.val_fctl_ftx   = SUN50I_H6_SPDIF_FCTL_FTX,
-+};
-+
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
- 	.tx_clk_name	= "spdif",
- 	.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
-@@ -576,6 +582,10 @@ static const struct of_device_id sun4i_s
- 		.data = &sun8i_h3_spdif_quirks,
- 	},
- 	{
-+		.compatible = "allwinner,sun20i-d1-spdif",
-+		.data = &sun20i_d1_spdif_quirks,
-+	},
-+	{
- 		.compatible = "allwinner,sun50i-h6-spdif",
- 		.data = &sun50i_h6_spdif_quirks,
- 	},
diff --git a/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch b/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch
deleted file mode 100644
index 72335cab40..0000000000
--- a/target/linux/d1/patches-6.1/0072-riscv-dts-allwinner-d1-Add-SPDIF-support.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 36153e325aa912268a5a5d4574dc7092e67c8008 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 01:54:46 -0500
-Subject: [PATCH 072/117] riscv: dts: allwinner: d1: Add SPDIF support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -333,6 +333,22 @@
- 			#sound-dai-cells = <0>;
- 		};
- 
-+		// TODO: add receive functionality
-+		spdif: spdif@2036000 {
-+			compatible = "allwinner,sun20i-d1-spdif";
-+			reg = <0x2036000 0x400>;
-+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_SPDIF>,
-+				 <&ccu CLK_SPDIF_RX>,
-+				 <&ccu CLK_SPDIF_TX>;
-+			clock-names = "apb", "rx", "tx";
-+			resets = <&ccu RST_BUS_SPDIF>;
-+			dmas = <&dma 2>, <&dma 2>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+			#sound-dai-cells = <0>;
-+		};
-+
- 		timer: timer@2050000 {
- 			compatible = "allwinner,sun20i-d1-timer",
- 				     "allwinner,sun8i-a23-timer";
diff --git a/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch b/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch
deleted file mode 100644
index 37ff3e2a9a..0000000000
--- a/target/linux/d1/patches-6.1/0073-ASoC-sun4i-spdif-Add-support-for-separate-resets.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c2b3f2c723e1b558afe5661bb91669e3b68154f7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:52:47 -0500
-Subject: [PATCH 073/117] ASoC: sun4i-spdif: Add support for separate resets
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -28,10 +28,11 @@
- #include <sound/soc.h>
- 
- #define	SUN4I_SPDIF_CTL		(0x00)
-+	#define SUN4I_SPDIF_CTL_RST_RX			BIT(12)
- 	#define SUN4I_SPDIF_CTL_MCLKDIV(v)		((v) << 4) /* v even */
- 	#define SUN4I_SPDIF_CTL_MCLKOUTEN		BIT(2)
- 	#define SUN4I_SPDIF_CTL_GEN			BIT(1)
--	#define SUN4I_SPDIF_CTL_RESET			BIT(0)
-+	#define SUN4I_SPDIF_CTL_RST_TX			BIT(0)
- 
- #define SUN4I_SPDIF_TXCFG	(0x04)
- 	#define SUN4I_SPDIF_TXCFG_SINGLEMOD		BIT(31)
-@@ -196,7 +197,7 @@ static void sun4i_spdif_configure(struct
- 	const struct sun4i_spdif_quirks *quirks = host->quirks;
- 
- 	/* soft reset SPDIF */
--	regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
-+	regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RST_TX);
- 
- 	/* flush TX FIFO */
- 	regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
diff --git a/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch b/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch
deleted file mode 100644
index 2301fad1cd..0000000000
--- a/target/linux/d1/patches-6.1/0074-dt-bindings-spi-sun6i-Add-R329-variant.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From e8e8a9490b2d4acc8670256dd3ba7d2a77346c4d Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:23:05 -0500
-Subject: [PATCH 074/117] dt-bindings: spi: sun6i: Add R329 variant
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml  | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
-+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
-@@ -21,6 +21,7 @@ properties:
-     oneOf:
-       - const: allwinner,sun6i-a31-spi
-       - const: allwinner,sun8i-h3-spi
-+      - const: allwinner,sun50i-r329-spi
-       - items:
-           - enum:
-               - allwinner,sun8i-r40-spi
-@@ -28,6 +29,13 @@ properties:
-               - allwinner,sun50i-h616-spi
-               - allwinner,suniv-f1c100s-spi
-           - const: allwinner,sun8i-h3-spi
-+      - items:
-+          - const: allwinner,sun20i-d1-spi
-+          - const: allwinner,sun50i-r329-spi
-+      - items:
-+          - const: allwinner,sun20i-d1-spi-dbi
-+          - const: allwinner,sun50i-r329-spi-dbi
-+          - const: allwinner,sun50i-r329-spi
- 
-   reg:
-     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch b/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch
deleted file mode 100644
index b13b7accf7..0000000000
--- a/target/linux/d1/patches-6.1/0075-spi-spi-sun6i-Use-a-struct-for-quirks.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From dbc9e83cefe51d19877a4a7349ebbeafa31c0e06 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 16 Jul 2021 21:33:16 -0500
-Subject: [PATCH 075/117] spi: spi-sun6i: Use a struct for quirks
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 32 ++++++++++++++++++++++----------
- 1 file changed, 22 insertions(+), 10 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -85,7 +85,12 @@
- #define SUN6I_TXDATA_REG		0x200
- #define SUN6I_RXDATA_REG		0x300
- 
-+struct sun6i_spi_quirks {
-+	unsigned long		fifo_depth;
-+};
-+
- struct sun6i_spi {
-+	const struct sun6i_spi_quirks *quirks;
- 	struct spi_master	*master;
- 	void __iomem		*base_addr;
- 	dma_addr_t		dma_addr_rx;
-@@ -100,7 +105,6 @@ struct sun6i_spi {
- 	const u8		*tx_buf;
- 	u8			*rx_buf;
- 	int			len;
--	unsigned long		fifo_depth;
- };
- 
- static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
-@@ -157,7 +161,7 @@ static inline void sun6i_spi_fill_fifo(s
- 	u8 byte;
- 
- 	/* See how much data we can fit */
--	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
-+	cnt = sspi->quirks->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
- 
- 	len = min((int)cnt, sspi->len);
- 
-@@ -300,14 +304,14 @@ static int sun6i_spi_transfer_one(struct
- 		 * the hardcoded value used in old generation of Allwinner
- 		 * SPI controller. (See spi-sun4i.c)
- 		 */
--		trig_level = sspi->fifo_depth / 4 * 3;
-+		trig_level = sspi->quirks->fifo_depth / 4 * 3;
- 	} else {
- 		/*
- 		 * Setup FIFO DMA request trigger level
- 		 * We choose 1/2 of the full fifo depth, that value will
- 		 * be used as DMA burst length.
- 		 */
--		trig_level = sspi->fifo_depth / 2;
-+		trig_level = sspi->quirks->fifo_depth / 2;
- 
- 		if (tfr->tx_buf)
- 			reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
-@@ -421,9 +425,9 @@ static int sun6i_spi_transfer_one(struct
- 	reg = SUN6I_INT_CTL_TC;
- 
- 	if (!use_dma) {
--		if (rx_len > sspi->fifo_depth)
-+		if (rx_len > sspi->quirks->fifo_depth)
- 			reg |= SUN6I_INT_CTL_RF_RDY;
--		if (tx_len > sspi->fifo_depth)
-+		if (tx_len > sspi->quirks->fifo_depth)
- 			reg |= SUN6I_INT_CTL_TF_ERQ;
- 	}
- 
-@@ -569,7 +573,7 @@ static bool sun6i_spi_can_dma(struct spi
- 	 * the fifo length we can just fill the fifo and wait for a single
- 	 * irq, so don't bother setting up dma
- 	 */
--	return xfer->len > sspi->fifo_depth;
-+	return xfer->len > sspi->quirks->fifo_depth;
- }
- 
- static int sun6i_spi_probe(struct platform_device *pdev)
-@@ -608,7 +612,7 @@ static int sun6i_spi_probe(struct platfo
- 	}
- 
- 	sspi->master = master;
--	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
-+	sspi->quirks = of_device_get_match_data(&pdev->dev);
- 
- 	master->max_speed_hz = 100 * 1000 * 1000;
- 	master->min_speed_hz = 3 * 1000;
-@@ -723,9 +727,17 @@ static int sun6i_spi_remove(struct platf
- 	return 0;
- }
- 
-+static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
-+	.fifo_depth		= SUN6I_FIFO_DEPTH,
-+};
-+
-+static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
-+	.fifo_depth		= SUN8I_FIFO_DEPTH,
-+};
-+
- static const struct of_device_id sun6i_spi_match[] = {
--	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
--	{ .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
-+	{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
-+	{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
- 	{}
- };
- MODULE_DEVICE_TABLE(of, sun6i_spi_match);
diff --git a/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch b/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch
deleted file mode 100644
index 04e1c17f66..0000000000
--- a/target/linux/d1/patches-6.1/0076-spi-spi-sun6i-Add-Allwinner-R329-support.patch
+++ /dev/null
@@ -1,146 +0,0 @@
-From ec8dfb455da3822451129257ab21e2f0d03a6ae3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 16 Jul 2021 21:46:31 -0500
-Subject: [PATCH 076/117] spi: spi-sun6i: Add Allwinner R329 support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 78 ++++++++++++++++++++++++++---------------
- 1 file changed, 49 insertions(+), 29 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -30,6 +30,7 @@
- #define SUN6I_GBL_CTL_REG		0x04
- #define SUN6I_GBL_CTL_BUS_ENABLE		BIT(0)
- #define SUN6I_GBL_CTL_MASTER			BIT(1)
-+#define SUN6I_GBL_CTL_SAMPLE_MODE		BIT(2)
- #define SUN6I_GBL_CTL_TP			BIT(7)
- #define SUN6I_GBL_CTL_RST			BIT(31)
- 
-@@ -87,6 +88,8 @@
- 
- struct sun6i_spi_quirks {
- 	unsigned long		fifo_depth;
-+	bool			has_divider : 1;
-+	bool			has_new_sample_mode : 1;
- };
- 
- struct sun6i_spi {
-@@ -362,38 +365,44 @@ static int sun6i_spi_transfer_one(struct
- 	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
- 
- 	/* Ensure that we have a parent clock fast enough */
--	mclk_rate = clk_get_rate(sspi->mclk);
--	if (mclk_rate < (2 * tfr->speed_hz)) {
--		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
-+	if (sspi->quirks->has_divider) {
- 		mclk_rate = clk_get_rate(sspi->mclk);
--	}
-+		if (mclk_rate < (2 * tfr->speed_hz)) {
-+			clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
-+			mclk_rate = clk_get_rate(sspi->mclk);
-+		}
- 
--	/*
--	 * Setup clock divider.
--	 *
--	 * We have two choices there. Either we can use the clock
--	 * divide rate 1, which is calculated thanks to this formula:
--	 * SPI_CLK = MOD_CLK / (2 ^ cdr)
--	 * Or we can use CDR2, which is calculated with the formula:
--	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
--	 * Wether we use the former or the latter is set through the
--	 * DRS bit.
--	 *
--	 * First try CDR2, and if we can't reach the expected
--	 * frequency, fall back to CDR1.
--	 */
--	div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
--	div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
--	if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
--		reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
--		tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
-+		/*
-+		 * Setup clock divider.
-+		 *
-+		 * We have two choices there. Either we can use the clock
-+		 * divide rate 1, which is calculated thanks to this formula:
-+		 * SPI_CLK = MOD_CLK / (2 ^ cdr)
-+		 * Or we can use CDR2, which is calculated with the formula:
-+		 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+		 * Wether we use the former or the latter is set through the
-+		 * DRS bit.
-+		 *
-+		 * First try CDR2, and if we can't reach the expected
-+		 * frequency, fall back to CDR1.
-+		 */
-+		div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
-+		div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
-+		if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
-+			reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
-+			tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
-+		} else {
-+			div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
-+			reg = SUN6I_CLK_CTL_CDR1(div);
-+			tfr->effective_speed_hz = mclk_rate / (1 << div);
-+		}
-+		sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
- 	} else {
--		div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
--		reg = SUN6I_CLK_CTL_CDR1(div);
--		tfr->effective_speed_hz = mclk_rate / (1 << div);
-+		clk_set_rate(sspi->mclk, tfr->speed_hz);
-+		mclk_rate = clk_get_rate(sspi->mclk);
-+		tfr->effective_speed_hz = mclk_rate;
- 	}
- 
--	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
- 	/* Finally enable the bus - doing so before might raise SCK to HIGH */
- 	reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
- 	reg |= SUN6I_GBL_CTL_BUS_ENABLE;
-@@ -518,6 +527,7 @@ static int sun6i_spi_runtime_resume(stru
- 	struct spi_master *master = dev_get_drvdata(dev);
- 	struct sun6i_spi *sspi = spi_master_get_devdata(master);
- 	int ret;
-+	u32 reg;
- 
- 	ret = clk_prepare_enable(sspi->hclk);
- 	if (ret) {
-@@ -537,8 +547,10 @@ static int sun6i_spi_runtime_resume(stru
- 		goto err2;
- 	}
- 
--	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
--			SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
-+	reg = SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP;
-+	if (sspi->quirks->has_new_sample_mode)
-+		reg |= SUN6I_GBL_CTL_SAMPLE_MODE;
-+	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
- 
- 	return 0;
- 
-@@ -729,15 +741,23 @@ static int sun6i_spi_remove(struct platf
- 
- static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
- 	.fifo_depth		= SUN6I_FIFO_DEPTH,
-+	.has_divider		= true,
- };
- 
- static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
- 	.fifo_depth		= SUN8I_FIFO_DEPTH,
-+	.has_divider		= true,
-+};
-+
-+static const struct sun6i_spi_quirks sun50i_r329_spi_quirks = {
-+	.fifo_depth		= SUN8I_FIFO_DEPTH,
-+	.has_new_sample_mode	= true,
- };
- 
- static const struct of_device_id sun6i_spi_match[] = {
- 	{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
- 	{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
-+	{ .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_quirks },
- 	{}
- };
- MODULE_DEVICE_TABLE(of, sun6i_spi_match);
diff --git a/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch b/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch
deleted file mode 100644
index ab7df5fe87..0000000000
--- a/target/linux/d1/patches-6.1/0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From b300b013de16109f833782d9f4e7ee8cc204780f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 17 Jul 2021 11:19:29 -0500
-Subject: [PATCH 077/117] spi: spi-sun6i: Dual/Quad RX Support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 17 +++++++++++++++--
- 1 file changed, 15 insertions(+), 2 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -82,6 +82,8 @@
- #define SUN6I_XMIT_CNT_REG		0x34
- 
- #define SUN6I_BURST_CTL_CNT_REG		0x38
-+#define SUN6I_BURST_CTL_CNT_QUAD_EN		BIT(29)
-+#define SUN6I_BURST_CTL_CNT_DUAL_EN		BIT(28)
- 
- #define SUN6I_TXDATA_REG		0x200
- #define SUN6I_RXDATA_REG		0x300
-@@ -415,7 +417,17 @@ static int sun6i_spi_transfer_one(struct
- 	/* Setup the counters */
- 	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
- 	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
--	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
-+
-+	reg = tx_len;
-+	switch (tfr->rx_nbits) {
-+	case SPI_NBITS_QUAD:
-+		reg |= SUN6I_BURST_CTL_CNT_QUAD_EN;
-+		break;
-+	case SPI_NBITS_DUAL:
-+		reg |= SUN6I_BURST_CTL_CNT_DUAL_EN;
-+		break;
-+	}
-+	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
- 
- 	if (!use_dma) {
- 		/* Fill the TX FIFO */
-@@ -632,7 +644,8 @@ static int sun6i_spi_probe(struct platfo
- 	master->set_cs = sun6i_spi_set_cs;
- 	master->transfer_one = sun6i_spi_transfer_one;
- 	master->num_chipselect = 4;
--	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST
-+			  | SPI_RX_DUAL | SPI_RX_QUAD;
- 	master->bits_per_word_mask = SPI_BPW_MASK(8);
- 	master->dev.of_node = pdev->dev.of_node;
- 	master->auto_runtime_pm = true;
diff --git a/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch b/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch
deleted file mode 100644
index 67a3dfb32b..0000000000
--- a/target/linux/d1/patches-6.1/0078-riscv-dts-allwinner-Add-SPI-support.patch
+++ /dev/null
@@ -1,154 +0,0 @@
-From aaabd3cf8c041b5122ca252f51fa616833e18749 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 00:54:01 -0500
-Subject: [PATCH 078/117] riscv: dts: allwinner: Add SPI support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../dts/allwinner/sun20i-d1-lichee-rv.dts     |  6 +++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 44 ++++++++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 51 +++++++++++++++++++
- 3 files changed, 101 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-@@ -65,6 +65,12 @@
- 	status = "okay";
- };
- 
-+&spi0 {
-+	pinctrl-0 = <&spi0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-0 = <&uart0_pb8_pins>;
- 	pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -19,6 +19,7 @@
- 		ethernet1 = &xr829;
- 		mmc0 = &mmc0;
- 		serial0 = &uart0;
-+		spi0 = &spi0;
- 	};
- 
- 	chosen {
-@@ -157,6 +158,49 @@
- 	pinctrl-names = "default";
- 	status = "okay";
- };
-+
-+&spi0 {
-+	pinctrl-0 = <&spi0_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "boot0";
-+				reg = <0x00000000 0x00100000>;
-+			};
-+
-+			partition@100000 {
-+				label = "uboot";
-+				reg = <0x00100000 0x00300000>;
-+			};
-+
-+			partition@400000 {
-+				label = "secure_storage";
-+				reg = <0x00400000 0x00100000>;
-+			};
-+
-+			partition@500000 {
-+				label = "sys";
-+				reg = <0x00500000 0x0fb00000>;
-+			};
-+		};
-+	};
-+};
-+
-+&spi1 {
-+	pinctrl-0 = <&spi1_pd_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
- 
- &uart0 {
- 	pinctrl-0 = <&uart0_pb8_pins>;
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -179,6 +179,24 @@
- 			};
- 
- 			/omit-if-no-ref/
-+			spi0_pins: spi0-pins {
-+				pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
-+				function = "spi0";
-+			};
-+
-+			/omit-if-no-ref/
-+			spi1_pb_pins: spi1-pb-pins {
-+				pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
-+				function = "spi1";
-+			};
-+
-+			/omit-if-no-ref/
-+			spi1_pd_pins: spi1-pd-pins {
-+				pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
-+				function = "spi1";
-+			};
-+
-+			/omit-if-no-ref/
- 			uart0_pb8_pins: uart0-pb8-pins {
- 				pins = "PB8", "PB9";
- 				function = "uart0";
-@@ -631,6 +649,39 @@
- 			status = "disabled";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-+		};
-+
-+		spi0: spi@4025000 {
-+			compatible = "allwinner,sun20i-d1-spi",
-+				     "allwinner,sun50i-r329-spi";
-+			reg = <0x4025000 0x1000>;
-+			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-+			clock-names = "ahb", "mod";
-+			resets = <&ccu RST_BUS_SPI0>;
-+			dmas = <&dma 22>, <&dma 22>;
-+			dma-names = "rx", "tx";
-+			num-cs = <1>;
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		spi1: spi@4026000 {
-+			compatible = "allwinner,sun20i-d1-spi-dbi",
-+				     "allwinner,sun50i-r329-spi-dbi",
-+				     "allwinner,sun50i-r329-spi";
-+			reg = <0x4026000 0x1000>;
-+			interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
-+			clock-names = "ahb", "mod";
-+			resets = <&ccu RST_BUS_SPI1>;
-+			dmas = <&dma 23>, <&dma 23>;
-+			dma-names = "rx", "tx";
-+			num-cs = <1>;
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
- 		};
- 
- 		usb_otg: usb@4100000 {
diff --git a/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch b/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch
deleted file mode 100644
index 6ba5b3ac75..0000000000
--- a/target/linux/d1/patches-6.1/0079-dt-bindings-thermal-sun8i-Add-compatible-for-D1.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 68c6f452bf42d6c5cbaf40537d8a17a7f3f5481e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:03:12 -0500
-Subject: [PATCH 079/117] dt-bindings: thermal: sun8i: Add compatible for D1
-
-D1 contains a thermal sensor similar to other Allwinner SoCs. Like the
-H3 variant, it contains only one channel.
-
-D1's thermal sensor gets a reference voltage from AVCC. This may always
-have been the case; it is explicitly documented in the SoC user manuals
-since at least H616. However, it was not as important on earlier SoCs,
-because those reference designs foreced AVCC always-on by connecting it
-to the PLL power supply.
-
-Now, since D1 only uses AVCC for other optional peripherals, this supply
-could be turned off at runtime, so it must be made explicit in the DTS.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../thermal/allwinner,sun8i-a83t-ths.yaml     | 21 ++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-+++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-@@ -16,6 +16,7 @@ properties:
-       - allwinner,sun8i-a83t-ths
-       - allwinner,sun8i-h3-ths
-       - allwinner,sun8i-r40-ths
-+      - allwinner,sun20i-d1-ths
-       - allwinner,sun50i-a64-ths
-       - allwinner,sun50i-a100-ths
-       - allwinner,sun50i-h5-ths
-@@ -55,6 +56,10 @@ properties:
-       - 0
-       - 1
- 
-+  vref-supply:
-+    description:
-+      Regulator for the analog reference voltage
-+
- allOf:
-   - if:
-       properties:
-@@ -84,7 +89,9 @@ allOf:
-       properties:
-         compatible:
-           contains:
--            const: allwinner,sun8i-h3-ths
-+            enum:
-+              - allwinner,sun8i-h3-ths
-+              - allwinner,sun20i-d1-ths
- 
-     then:
-       properties:
-@@ -103,6 +110,7 @@ allOf:
-             enum:
-               - allwinner,sun8i-h3-ths
-               - allwinner,sun8i-r40-ths
-+              - allwinner,sun20i-d1-ths
-               - allwinner,sun50i-a64-ths
-               - allwinner,sun50i-a100-ths
-               - allwinner,sun50i-h5-ths
-@@ -114,6 +122,17 @@ allOf:
-         - clock-names
-         - resets
- 
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - allwinner,sun20i-d1-ths
-+
-+    then:
-+      required:
-+        - vref-supply
-+
- required:
-   - compatible
-   - reg
diff --git a/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch b/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch
deleted file mode 100644
index 9bfb74b895..0000000000
--- a/target/linux/d1/patches-6.1/0080-riscv-dts-allwinner-d1-Add-thermal-sensor-and-zone.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From c225b48d2cf5f5a824b5b0a4144511bdc5f65ab5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 11:18:11 -0500
-Subject: [PATCH 080/117] riscv: dts: allwinner: d1: Add thermal sensor and
- zone
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-common-regulators.dtsi          |  4 ++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 41 +++++++++++++++++++
- 2 files changed, 45 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -49,3 +49,7 @@
- 	regulator-max-microvolt = <1800000>;
- 	ldo-in-supply = <&reg_vcc_3v3>;
- };
-+
-+&ths {
-+	vref-supply = <&reg_aldo>;
-+};
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -59,6 +59,35 @@
- 		#clock-cells = <0>;
- 	};
- 
-+	thermal-zones {
-+		cpu-thermal {
-+			polling-delay = <0>;
-+			polling-delay-passive = <0>;
-+			thermal-sensors = <&ths>;
-+
-+			trips {
-+				cpu_target: cpu-target {
-+					hysteresis = <3000>;
-+					temperature = <85000>;
-+					type = "passive";
-+				};
-+
-+				cpu-crit {
-+					hysteresis = <0>;
-+					temperature = <110000>;
-+					type = "critical";
-+				};
-+			};
-+
-+			cooling-maps {
-+				map0 {
-+					trip = <&cpu_target>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+	};
-+
- 	soc {
- 		compatible = "simple-bus";
- 		ranges;
-@@ -252,6 +281,18 @@
- 			#size-cells = <0>;
- 		};
- 
-+		ths: temperature-sensor@2009400 {
-+			compatible = "allwinner,sun20i-d1-ths";
-+			reg = <0x2009400 0x400>;
-+			interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_THS>;
-+			nvmem-cells = <&ths_calib>;
-+			nvmem-cell-names = "calibration";
-+			#thermal-sensor-cells = <0>;
-+		};
-+
- 		lradc: keys@2009800 {
- 			compatible = "allwinner,sun20i-d1-lradc",
- 				     "allwinner,sun50i-r329-lradc";
diff --git a/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch b/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch
deleted file mode 100644
index 6460d84f07..0000000000
--- a/target/linux/d1/patches-6.1/0081-ASoC-sun20i-codec-New-driver-for-D1-internal-codec.patch
+++ /dev/null
@@ -1,927 +0,0 @@
-From 9b6a07cacab9300c261b1f7e25857f96cfeae9cf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 12 Jun 2021 23:42:48 -0500
-Subject: [PATCH 081/117] ASoC: sun20i-codec: New driver for D1 internal codec
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/Kconfig        |   6 +
- sound/soc/sunxi/Makefile       |   1 +
- sound/soc/sunxi/sun20i-codec.c | 886 +++++++++++++++++++++++++++++++++
- 3 files changed, 893 insertions(+)
- create mode 100644 sound/soc/sunxi/sun20i-codec.c
-
---- a/sound/soc/sunxi/Kconfig
-+++ b/sound/soc/sunxi/Kconfig
-@@ -30,6 +30,12 @@ config SND_SUN8I_CODEC_ANALOG
- 	  Say Y or M if you want to add support for the analog controls for
- 	  the codec embedded in newer Allwinner SoCs.
- 
-+config SND_SUN20I_CODEC
-+	tristate "Allwinner D1 (sun20i) Audio Codec"
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	help
-+	  Say Y or M to add support for the audio codec in Allwinner D1 SoC.
-+
- config SND_SUN50I_CODEC_ANALOG
- 	tristate "Allwinner sun50i Codec Analog Controls Support"
- 	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
---- a/sound/soc/sunxi/Makefile
-+++ b/sound/soc/sunxi/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-c
- obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
- obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
- obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
-+obj-$(CONFIG_SND_SUN20I_CODEC) += sun20i-codec.o
- obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
- obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
- obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
---- /dev/null
-+++ b/sound/soc/sunxi/sun20i-codec.c
-@@ -0,0 +1,886 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+
-+#include <sound/dmaengine_pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/simple_card_utils.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dai.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/tlv.h>
-+
-+#define SUN20I_CODEC_DAC_DPC		0x0000
-+#define SUN20I_CODEC_DAC_DPC_EN_DA		31
-+#define SUN20I_CODEC_DAC_DPC_HPF_EN		18
-+#define SUN20I_CODEC_DAC_DPC_DVOL		12
-+#define SUN20I_CODEC_DAC_VOL_CTRL	0x0004
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL	16
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L	8
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R	0
-+#define SUN20I_CODEC_DAC_FIFOC		0x0010
-+#define SUN20I_CODEC_DAC_FIFOC_FS		29
-+#define SUN20I_CODEC_DAC_FIFOC_FIFO_MODE	24
-+#define SUN20I_CODEC_DAC_FIFOC_DRQ_CLR_CNT	21
-+#define SUN20I_CODEC_DAC_FIFOC_TRIG_LEVEL	8
-+#define SUN20I_CODEC_DAC_FIFOC_MONO_EN		6
-+#define SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS	5
-+#define SUN20I_CODEC_DAC_FIFOC_DRQ_EN		4
-+#define SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH	0
-+#define SUN20I_CODEC_DAC_TXDATA		0x0020
-+#define SUN20I_CODEC_DAC_DEBUG		0x0028
-+#define SUN20I_CODEC_DAC_DEBUG_DA_SWP		6
-+#define SUN20I_CODEC_DAC_ADDA_LOOP_MODE		0
-+
-+#define SUN20I_CODEC_ADC_FIFOC		0x0030
-+#define SUN20I_CODEC_ADC_FIFOC_FS		29
-+#define SUN20I_CODEC_ADC_FIFOC_EN_AD		28
-+#define SUN20I_CODEC_ADC_FIFOC_FIFO_MODE	24
-+#define SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS	16
-+#define SUN20I_CODEC_ADC_FIFOC_TRIG_LEVEL	4
-+#define SUN20I_CODEC_ADC_FIFOC_DRQ_EN		3
-+#define SUN20I_CODEC_ADC_FIFOC_FIFO_FLUSH	0
-+#define SUN20I_CODEC_ADC_VOL_CTRL	0x0034
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL	16
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL	8
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL	0
-+#define SUN20I_CODEC_ADC_RXDATA		0x0040
-+#define SUN20I_CODEC_ADC_DEBUG		0x004c
-+#define SUN20I_CODEC_ADC_DEBUG_AD_SWP1		24
-+#define SUN20I_CODEC_ADC_DIG_CTRL	0x0050
-+#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN	16
-+#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN	0
-+
-+#define SUN20I_CODEC_DAC_DAP_CTRL	0x00f0
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_EN	31
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_DRC_EN	29
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_HPF_EN	28
-+
-+#define SUN20I_CODEC_ADC_DAP_CTRL	0x00f8
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_EN	31
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_DRC_EN	29
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_HPF_EN	28
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_EN	27
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_DRC_EN	25
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_HPF_EN	24
-+
-+#define SUN20I_CODEC_ADC1		0x0300
-+#define SUN20I_CODEC_ADC1_ADC1_EN		31
-+#define SUN20I_CODEC_ADC1_MICIN1_PGA_EN		30
-+#define SUN20I_CODEC_ADC1_ADC1_DITHER_EN	29
-+#define SUN20I_CODEC_ADC1_MICIN1_SIN_EN		28
-+#define SUN20I_CODEC_ADC1_FMINL_EN		27
-+#define SUN20I_CODEC_ADC1_FMINL_GAIN		26
-+#define SUN20I_CODEC_ADC1_DITHER_LEVEL		24
-+#define SUN20I_CODEC_ADC1_LINEINL_EN		23
-+#define SUN20I_CODEC_ADC1_LINEINL_GAIN		22
-+#define SUN20I_CODEC_ADC1_ADC1_PGA_GAIN		8
-+#define SUN20I_CODEC_ADC2		0x0304
-+#define SUN20I_CODEC_ADC2_ADC2_EN		31
-+#define SUN20I_CODEC_ADC2_MICIN2_PGA_EN		30
-+#define SUN20I_CODEC_ADC2_ADC2_DITHER_EN	29
-+#define SUN20I_CODEC_ADC2_MICIN2_SIN_EN		28
-+#define SUN20I_CODEC_ADC2_FMINR_EN		27
-+#define SUN20I_CODEC_ADC2_FMINR_GAIN		26
-+#define SUN20I_CODEC_ADC2_DITHER_LEVEL		24
-+#define SUN20I_CODEC_ADC2_LINEINR_EN		23
-+#define SUN20I_CODEC_ADC2_LINEINR_GAIN		22
-+#define SUN20I_CODEC_ADC2_ADC2_PGA_GAIN		8
-+#define SUN20I_CODEC_ADC3		0x0308
-+#define SUN20I_CODEC_ADC3_ADC3_EN		31
-+#define SUN20I_CODEC_ADC3_MICIN3_PGA_EN		30
-+#define SUN20I_CODEC_ADC3_ADC3_DITHER_EN	29
-+#define SUN20I_CODEC_ADC3_MICIN3_SIN_EN		28
-+#define SUN20I_CODEC_ADC3_DITHER_LEVEL		24
-+#define SUN20I_CODEC_ADC3_ADC3_PGA_GAIN		8
-+
-+#define SUN20I_CODEC_DAC		0x0310
-+#define SUN20I_CODEC_DAC_DACL_EN		15
-+#define SUN20I_CODEC_DAC_DACR_EN		14
-+#define SUN20I_CODEC_DAC_LINEOUTL_EN		13
-+#define SUN20I_CODEC_DAC_LMUTE			12
-+#define SUN20I_CODEC_DAC_LINEOUTR_EN		11
-+#define SUN20I_CODEC_DAC_RMUTE			10
-+#define SUN20I_CODEC_DAC_LINEOUTL_DIFFEN	6
-+#define SUN20I_CODEC_DAC_LINEOUTR_DIFFEN	5
-+#define SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL	0
-+
-+#define SUN20I_CODEC_MICBIAS		0x0318
-+#define SUN20I_CODEC_MICBIAS_SELDETADCFS	28
-+#define SUN20I_CODEC_MICBIAS_SELDETADCDB	26
-+#define SUN20I_CODEC_MICBIAS_SELDETADCBF	24
-+#define SUN20I_CODEC_MICBIAS_JACKDETEN		23
-+#define SUN20I_CODEC_MICBIAS_SELDETADCDY	21
-+#define SUN20I_CODEC_MICBIAS_MICADCEN		20
-+#define SUN20I_CODEC_MICBIAS_POPFREE		19
-+#define SUN20I_CODEC_MICBIAS_DET_MODE		18
-+#define SUN20I_CODEC_MICBIAS_AUTOPLEN		17
-+#define SUN20I_CODEC_MICBIAS_MICDETPL		16
-+#define SUN20I_CODEC_MICBIAS_HMICBIASEN		15
-+#define SUN20I_CODEC_MICBIAS_HMICBIASSEL	13
-+#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_EN	12
-+#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_CLK	10
-+#define SUN20I_CODEC_MICBIAS_MMICBIASEN		7
-+#define SUN20I_CODEC_MICBIAS_MMICBIASSEL	5
-+#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_EN	4
-+#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_CLK	2
-+
-+/* TODO */
-+#define SUN20I_CODEC_RAMP		0x031c
-+#define SUN20I_CODEC_RAMP_HP_PULL_OUT_EN	15
-+
-+#define SUN20I_CODEC_HMIC_CTRL		0x0328
-+#define SUN20I_CODEC_HMIC_CTRL_SAMPLE_SELECT	21
-+#define SUN20I_CODEC_HMIC_CTRL_MDATA_THRESHOLD	16
-+#define SUN20I_CODEC_HMIC_CTRL_SF		14
-+#define SUN20I_CODEC_HMIC_CTRL_M		10
-+#define SUN20I_CODEC_HMIC_CTRL_N		6
-+#define SUN20I_CODEC_HMIC_CTRL_THRESH_DEBOUNCE	3
-+#define SUN20I_CODEC_HMIC_CTRL_JACK_OUT_IRQ_EN	2
-+#define SUN20I_CODEC_HMIC_CTRL_JACK_IN_IRQ_EN	1
-+#define SUN20I_CODEC_HMIC_CTRL_MIC_DET_IRQ_EN	0
-+#define SUN20I_CODEC_HMIC_STS		0x032c
-+#define SUN20I_CODEC_HMIC_STS_MDATA_DISCARD	13
-+#define SUN20I_CODEC_HMIC_STS_HMIC_DATA		8
-+#define SUN20I_CODEC_HMIC_STS_JACK_OUT_IRQ	4
-+#define SUN20I_CODEC_HMIC_STS_JACK_IN_IRQ	3
-+#define SUN20I_CODEC_HMIC_STS_MIC_DET_IRQ	0
-+
-+#define SUN20I_CODEC_HP2		0x0340
-+#define SUN20I_CODEC_HP2_HPFB_BUF_EN		31
-+#define SUN20I_CODEC_HP2_HEADPHONE_GAIN		28
-+#define SUN20I_CODEC_HP2_HPFB_RES		26
-+#define SUN20I_CODEC_HP2_HP_DRVEN		21
-+#define SUN20I_CODEC_HP2_HP_DRVOUTEN		20
-+#define SUN20I_CODEC_HP2_RSWITCH		19
-+#define SUN20I_CODEC_HP2_RAMPEN			18
-+#define SUN20I_CODEC_HP2_HPFB_IN_EN		17
-+#define SUN20I_CODEC_HP2_RAMP_FINAL_CONTROL	16
-+#define SUN20I_CODEC_HP2_RAMP_OUT_EN		15
-+#define SUN20I_CODEC_HP2_RAMP_FINAL_STATE_RES	13
-+
-+/* Not affected by codec bus clock/reset */
-+#define SUN20I_CODEC_POWER		0x0348
-+#define SUN20I_CODEC_POWER_ALDO_EN_MASK		BIT(31)
-+#define SUN20I_CODEC_POWER_HPLDO_EN_MASK	BIT(30)
-+#define SUN20I_CODEC_POWER_ALDO_VOLTAGE_MASK	GENMASK(14, 12)
-+#define SUN20I_CODEC_POWER_HPLDO_VOLTAGE_MASK	GENMASK(10, 8)
-+
-+#define SUN20I_CODEC_ADC_CUR		0x034c
-+
-+#define SUN20I_CODEC_PCM_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE|\
-+					 SNDRV_PCM_FMTBIT_S20_LE|\
-+					 SNDRV_PCM_FMTBIT_S32_LE)
-+
-+#define DRIVER_NAME			"sun20i-codec"
-+
-+/* snd_soc_register_card() takes over drvdata, so the card must be first! */
-+struct sun20i_codec {
-+	struct snd_soc_card			card;
-+	struct snd_soc_dai_link			dai_link;
-+	struct snd_soc_dai_link_component	dlcs[3];
-+	struct snd_dmaengine_dai_dma_data	dma_data[2];
-+
-+	struct clk		*bus_clk;
-+	struct clk		*adc_clk;
-+	struct clk		*dac_clk;
-+	struct reset_control	*reset;
-+};
-+
-+static int sun20i_codec_dai_probe(struct snd_soc_dai *dai)
-+{
-+	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+
-+	snd_soc_dai_init_dma_data(dai,
-+				  &codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
-+				  &codec->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
-+
-+	return 0;
-+}
-+
-+static struct clk *sun20i_codec_get_clk(struct snd_pcm_substream *substream,
-+					struct snd_soc_dai *dai)
-+{
-+	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+
-+	return substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
-+		codec->adc_clk : codec->dac_clk;
-+}
-+
-+static const unsigned int sun20i_codec_rates[] = {
-+	 7350,   8000,  11025,  12000,  14700,  16000,  22050,  24000,
-+	29400,  32000,  44100,  48000,  88200,  96000, 176400, 192000,
-+};
-+
-+static const struct snd_pcm_hw_constraint_list sun20i_codec_rate_lists[] = {
-+	[SNDRV_PCM_STREAM_PLAYBACK] = {
-+		.list	= sun20i_codec_rates,
-+		.count	= ARRAY_SIZE(sun20i_codec_rates),
-+	},
-+	[SNDRV_PCM_STREAM_CAPTURE] = {
-+		.list	= sun20i_codec_rates,
-+		.count	= ARRAY_SIZE(sun20i_codec_rates) - 4, /* max 48 kHz */
-+	},
-+};
-+
-+static int sun20i_codec_startup(struct snd_pcm_substream *substream,
-+				struct snd_soc_dai *dai)
-+{
-+	const struct snd_pcm_hw_constraint_list *list;
-+	int ret;
-+
-+	list = &sun20i_codec_rate_lists[substream->stream];
-+	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
-+					 SNDRV_PCM_HW_PARAM_RATE, list);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(sun20i_codec_get_clk(substream, dai));
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static void sun20i_codec_shutdown(struct snd_pcm_substream *substream,
-+				  struct snd_soc_dai *dai)
-+{
-+	clk_disable_unprepare(sun20i_codec_get_clk(substream, dai));
-+}
-+
-+static unsigned int sun20i_codec_get_clk_rate(unsigned int sample_rate)
-+{
-+	return (sample_rate % 4000) ? 22579200 : 24576000;
-+}
-+
-+static const unsigned short sun20i_codec_divisors[] = {
-+	512, 1024, 2048, 128,
-+	768, 1536, 3072, 256,
-+};
-+
-+static int sun20i_codec_get_fs(unsigned int clk_rate, unsigned int sample_rate)
-+{
-+	unsigned int divisor = clk_rate / sample_rate;
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(sun20i_codec_divisors); ++i)
-+		if (sun20i_codec_divisors[i] == divisor)
-+			return i;
-+
-+	return -EINVAL;
-+}
-+
-+static int sun20i_codec_hw_params(struct snd_pcm_substream *substream,
-+				  struct snd_pcm_hw_params *params,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+	struct snd_soc_component *component = dai->component;
-+	unsigned int channels = params_channels(params);
-+	unsigned int sample_bits = params_width(params);
-+	unsigned int sample_rate = params_rate(params);
-+	unsigned int clk_rate = sun20i_codec_get_clk_rate(sample_rate);
-+	enum dma_slave_buswidth dma_width;
-+	unsigned int reg;
-+	int ret, val;
-+
-+	switch (params_physical_width(params)) {
-+	case 16:
-+		dma_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
-+		break;
-+	case 32:
-+		dma_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+		break;
-+	default:
-+		dev_err(dai->dev, "Unsupported physical sample width: %d\n",
-+			params_physical_width(params));
-+		return -EINVAL;
-+	}
-+	codec->dma_data[substream->stream].addr_width = dma_width;
-+
-+	ret = clk_set_rate(sun20i_codec_get_clk(substream, dai),
-+			   sun20i_codec_get_clk_rate(sample_rate));
-+	if (ret)
-+		return ret;
-+
-+	reg = substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
-+		SUN20I_CODEC_ADC_FIFOC : SUN20I_CODEC_DAC_FIFOC;
-+
-+	val = sun20i_codec_get_fs(clk_rate, sample_rate);
-+	if (val < 0)
-+		return val;
-+	snd_soc_component_update_bits(component, reg,
-+				      0x7 << SUN20I_CODEC_DAC_FIFOC_FS,
-+				      val << SUN20I_CODEC_DAC_FIFOC_FS);
-+
-+	/* Data is at MSB for full 4-byte samples, otherwise at LSB. */
-+	val = sample_bits != 32;
-+	snd_soc_component_update_bits(component, reg,
-+				      0x1 << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE,
-+				      val << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE);
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-+		val = sample_bits > 16;
-+		snd_soc_component_update_bits(component, reg,
-+					      0x1 << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS,
-+					      val << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS);
-+
-+		val = BIT(channels) - 1;
-+		snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
-+					      0xf << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN,
-+					      val << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN);
-+	} else {
-+		val = sample_bits > 16;
-+		snd_soc_component_update_bits(component, reg,
-+					      0x1 << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS,
-+					      val << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS);
-+
-+		val = channels == 1;
-+		snd_soc_component_update_bits(component, reg,
-+					      0x1 << SUN20I_CODEC_DAC_FIFOC_MONO_EN,
-+					      val << SUN20I_CODEC_DAC_FIFOC_MONO_EN);
-+	}
-+
-+	return 0;
-+}
-+
-+static int sun20i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
-+				struct snd_soc_dai *dai)
-+{
-+	struct snd_soc_component *component = dai->component;
-+	unsigned int reg, mask;
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-+		reg  = SUN20I_CODEC_ADC_FIFOC;
-+		mask = BIT(SUN20I_CODEC_ADC_FIFOC_DRQ_EN);
-+	} else {
-+		reg  = SUN20I_CODEC_DAC_FIFOC;
-+		mask = BIT(SUN20I_CODEC_DAC_FIFOC_DRQ_EN);
-+	}
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+		mask |= BIT(SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH);
-+		snd_soc_component_update_bits(component, reg, mask, mask);
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+		snd_soc_component_update_bits(component, reg, mask, 0);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops sun20i_codec_dai_ops = {
-+	.startup	= sun20i_codec_startup,
-+	.shutdown	= sun20i_codec_shutdown,
-+	.hw_params	= sun20i_codec_hw_params,
-+	.trigger	= sun20i_codec_trigger,
-+};
-+
-+static struct snd_soc_dai_driver sun20i_codec_dai = {
-+	.name = DRIVER_NAME,
-+	.probe = sun20i_codec_dai_probe,
-+	.ops = &sun20i_codec_dai_ops,
-+	.capture = {
-+		.stream_name	= "Capture",
-+		.channels_min	= 1,
-+		.channels_max	= 3, /* ??? */
-+		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
-+		.formats	= SUN20I_CODEC_PCM_FORMATS,
-+		.sig_bits	= 20,
-+	},
-+	.playback = {
-+		.stream_name	= "Playback",
-+		.channels_min	= 1,
-+		.channels_max	= 2,
-+		.rates		= SNDRV_PCM_RATE_CONTINUOUS,
-+		.formats	= SUN20I_CODEC_PCM_FORMATS,
-+		.sig_bits	= 20,
-+	},
-+};
-+
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_boost_vol_scale, 0, 600, 0);
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_digital_vol_scale, -12000, 75, 1);
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_headphone_vol_scale, -4200, 600, 0);
-+/* FIXME */
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_line_out_vol_scale, -4650, 150, 1);
-+/* FIXME */
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_pga_vol_scale, 500, 100, 0);
-+
-+static const char *const sun20i_codec_line_out_mode_enum_text[] = {
-+	"Single-Ended", "Differential"
-+};
-+
-+static const SOC_ENUM_DOUBLE_DECL(sun20i_codec_line_out_mode_enum,
-+				  SUN20I_CODEC_DAC,
-+				  SUN20I_CODEC_DAC_LINEOUTL_DIFFEN,
-+				  SUN20I_CODEC_DAC_LINEOUTR_DIFFEN,
-+				  sun20i_codec_line_out_mode_enum_text);
-+
-+static const struct snd_kcontrol_new sun20i_codec_controls[] = {
-+	/* Digital Controls */
-+	SOC_DOUBLE_TLV("DAC Playback Volume",
-+		       SUN20I_CODEC_DAC_VOL_CTRL,
-+		       SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L,
-+		       SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R,
-+		       0xc0, 0, sun20i_codec_digital_vol_scale),
-+	SOC_SINGLE_TLV("ADC3 Capture Volume",
-+		       SUN20I_CODEC_ADC_VOL_CTRL,
-+		       SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL,
-+		       0xc0, 0, sun20i_codec_digital_vol_scale),
-+	SOC_SINGLE_TLV("ADC2 Capture Volume",
-+		       SUN20I_CODEC_ADC_VOL_CTRL,
-+		       SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL,
-+		       0xc0, 0, sun20i_codec_digital_vol_scale),
-+	SOC_SINGLE_TLV("ADC1 Capture Volume",
-+		       SUN20I_CODEC_ADC_VOL_CTRL,
-+		       SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL,
-+		       0xc0, 0, sun20i_codec_digital_vol_scale),
-+
-+	/* Analog Controls */
-+	SOC_DOUBLE_R_TLV("FM Capture Volume",
-+			 SUN20I_CODEC_ADC1,
-+			 SUN20I_CODEC_ADC2,
-+			 SUN20I_CODEC_ADC1_FMINL_GAIN,
-+			 0x1, 0, sun20i_codec_boost_vol_scale),
-+	SOC_DOUBLE_R_TLV("Line In Capture Volume",
-+			 SUN20I_CODEC_ADC1,
-+			 SUN20I_CODEC_ADC2,
-+			 SUN20I_CODEC_ADC1_LINEINL_GAIN,
-+			 0x1, 0, sun20i_codec_boost_vol_scale),
-+	SOC_ENUM("Line Out Mode Playback Enum",
-+		 sun20i_codec_line_out_mode_enum),
-+	SOC_SINGLE_TLV("Line Out Playback Volume",
-+		       SUN20I_CODEC_DAC,
-+		       SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL,
-+		       0x1f, 0, sun20i_codec_line_out_vol_scale),
-+	SOC_SINGLE_TLV("Headphone Playback Volume",
-+		       SUN20I_CODEC_HP2,
-+		       SUN20I_CODEC_HP2_HEADPHONE_GAIN,
-+		       0x7, 1, sun20i_codec_headphone_vol_scale),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_line_out_switch =
-+	SOC_DAPM_DOUBLE("Line Out Playback Switch",
-+			SUN20I_CODEC_DAC,
-+			SUN20I_CODEC_DAC_LMUTE,
-+			SUN20I_CODEC_DAC_RMUTE, 1, 1);
-+
-+static const struct snd_kcontrol_new sun20i_codec_hp_switch =
-+	SOC_DAPM_SINGLE("Headphone Playback Switch",
-+			SUN20I_CODEC_HP2,
-+			SUN20I_CODEC_HP2_HP_DRVOUTEN, 1, 0);
-+
-+static const struct snd_kcontrol_new sun20i_codec_adc12_mixer_controls[] = {
-+	/* ADC1 Only */
-+	SOC_DAPM_SINGLE("Mic1 Capture Switch",
-+			SUN20I_CODEC_ADC1,
-+			SUN20I_CODEC_ADC1_MICIN1_SIN_EN, 1, 0),
-+	/* Shared */
-+	SOC_DAPM_DOUBLE_R("FM Capture Switch",
-+			  SUN20I_CODEC_ADC1,
-+			  SUN20I_CODEC_ADC2,
-+			  SUN20I_CODEC_ADC1_FMINL_EN, 1, 0),
-+	/* Shared */
-+	SOC_DAPM_DOUBLE_R("Line In Capture Switch",
-+			  SUN20I_CODEC_ADC1,
-+			  SUN20I_CODEC_ADC2,
-+			  SUN20I_CODEC_ADC1_LINEINL_EN, 1, 0),
-+	/* ADC2 Only */
-+	SOC_DAPM_SINGLE("Mic2 Capture Switch",
-+			SUN20I_CODEC_ADC2,
-+			SUN20I_CODEC_ADC2_MICIN2_SIN_EN, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_adc3_mixer_controls[] = {
-+	SOC_DAPM_SINGLE("Mic3 Capture Switch",
-+			SUN20I_CODEC_ADC3,
-+			SUN20I_CODEC_ADC3_MICIN3_SIN_EN, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic1_volume =
-+	SOC_DAPM_SINGLE_TLV("Capture Volume",
-+			    SUN20I_CODEC_ADC1,
-+			    SUN20I_CODEC_ADC1_ADC1_PGA_GAIN,
-+			    0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic2_volume =
-+	SOC_DAPM_SINGLE_TLV("Capture Volume",
-+			    SUN20I_CODEC_ADC2,
-+			    SUN20I_CODEC_ADC2_ADC2_PGA_GAIN,
-+			    0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic3_volume =
-+	SOC_DAPM_SINGLE_TLV("Capture Volume",
-+			    SUN20I_CODEC_ADC3,
-+			    SUN20I_CODEC_ADC3_ADC3_PGA_GAIN,
-+			    0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_soc_dapm_widget sun20i_codec_widgets[] = {
-+	/* Playback */
-+	SND_SOC_DAPM_OUTPUT("LINEOUTL"),
-+	SND_SOC_DAPM_OUTPUT("LINEOUTR"),
-+
-+	SND_SOC_DAPM_SWITCH("LINEOUTL Switch",
-+			    SUN20I_CODEC_DAC,
-+			    SUN20I_CODEC_DAC_LINEOUTL_EN, 0,
-+			    &sun20i_codec_line_out_switch),
-+	SND_SOC_DAPM_SWITCH("LINEOUTR Switch",
-+			    SUN20I_CODEC_DAC,
-+			    SUN20I_CODEC_DAC_LINEOUTR_EN, 0,
-+			    &sun20i_codec_line_out_switch),
-+
-+	SND_SOC_DAPM_OUTPUT("HPOUTL"),
-+	SND_SOC_DAPM_OUTPUT("HPOUTR"),
-+
-+	SND_SOC_DAPM_SWITCH("HPOUTL Switch",
-+			    SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
-+	SND_SOC_DAPM_SWITCH("HPOUTR Switch",
-+			    SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
-+	SND_SOC_DAPM_SUPPLY("Headphone Driver",
-+			    SUN20I_CODEC_HP2,
-+			    SUN20I_CODEC_HP2_HP_DRVEN, 0, NULL, 0),
-+
-+	SND_SOC_DAPM_DAC("DACL", NULL,
-+			 SUN20I_CODEC_DAC,
-+			 SUN20I_CODEC_DAC_DACL_EN, 0),
-+	SND_SOC_DAPM_DAC("DACR", NULL,
-+			 SUN20I_CODEC_DAC,
-+			 SUN20I_CODEC_DAC_DACR_EN, 0),
-+	SND_SOC_DAPM_SUPPLY("DAC",
-+			    SUN20I_CODEC_DAC_DPC,
-+			    SUN20I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
-+
-+	SND_SOC_DAPM_AIF_IN("DACL FIFO", "Playback", 0,
-+			    SND_SOC_NOPM, 0, 0),
-+	SND_SOC_DAPM_AIF_IN("DACR FIFO", "Playback", 1,
-+			    SND_SOC_NOPM, 0, 0),
-+
-+	/* Capture */
-+	SND_SOC_DAPM_AIF_OUT("ADC1 FIFO", "Capture", 0,
-+			     SND_SOC_NOPM, 0, 0),
-+	SND_SOC_DAPM_AIF_OUT("ADC2 FIFO", "Capture", 1,
-+			     SND_SOC_NOPM, 0, 0),
-+	SND_SOC_DAPM_AIF_OUT("ADC3 FIFO", "Capture", 2,
-+			     SND_SOC_NOPM, 0, 0),
-+
-+	SND_SOC_DAPM_ADC("ADC1", NULL,
-+			 SUN20I_CODEC_ADC1,
-+			 SUN20I_CODEC_ADC1_ADC1_EN, 0),
-+	SND_SOC_DAPM_ADC("ADC2", NULL,
-+			 SUN20I_CODEC_ADC2,
-+			 SUN20I_CODEC_ADC2_ADC2_EN, 0),
-+	SND_SOC_DAPM_ADC("ADC3", NULL,
-+			 SUN20I_CODEC_ADC3,
-+			 SUN20I_CODEC_ADC3_ADC3_EN, 0),
-+	SND_SOC_DAPM_SUPPLY("ADC",
-+			    SUN20I_CODEC_ADC_FIFOC,
-+			    SUN20I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
-+
-+	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC1 Mixer", SND_SOC_NOPM, 0, 0,
-+				     sun20i_codec_adc12_mixer_controls, 3),
-+	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC2 Mixer", SND_SOC_NOPM, 0, 0,
-+				     sun20i_codec_adc12_mixer_controls + 1, 3),
-+	SND_SOC_DAPM_MIXER_NAMED_CTL("ADC3 Mixer", SND_SOC_NOPM, 0, 0,
-+				     sun20i_codec_adc3_mixer_controls,
-+				     ARRAY_SIZE(sun20i_codec_adc3_mixer_controls)),
-+
-+	SND_SOC_DAPM_PGA("Mic1",
-+			 SUN20I_CODEC_ADC1,
-+			 SUN20I_CODEC_ADC1_MICIN1_PGA_EN, 0,
-+			 &sun20i_codec_mic1_volume, 1),
-+	SND_SOC_DAPM_PGA("Mic2",
-+			 SUN20I_CODEC_ADC2,
-+			 SUN20I_CODEC_ADC2_MICIN2_PGA_EN, 0,
-+			 &sun20i_codec_mic2_volume, 1),
-+	SND_SOC_DAPM_PGA("Mic3",
-+			 SUN20I_CODEC_ADC3,
-+			 SUN20I_CODEC_ADC3_MICIN3_PGA_EN, 0,
-+			 &sun20i_codec_mic3_volume, 1),
-+
-+	SND_SOC_DAPM_INPUT("MICIN1"),
-+	SND_SOC_DAPM_INPUT("MICIN2"),
-+	SND_SOC_DAPM_INPUT("MICIN3"),
-+
-+	SND_SOC_DAPM_INPUT("FMINL"),
-+	SND_SOC_DAPM_INPUT("FMINR"),
-+
-+	SND_SOC_DAPM_INPUT("LINEINL"),
-+	SND_SOC_DAPM_INPUT("LINEINR"),
-+
-+	SND_SOC_DAPM_SUPPLY("HBIAS",
-+			    SUN20I_CODEC_MICBIAS,
-+			    SUN20I_CODEC_MICBIAS_HMICBIASEN, 0, NULL, 0),
-+	SND_SOC_DAPM_SUPPLY("MBIAS",
-+			    SUN20I_CODEC_MICBIAS,
-+			    SUN20I_CODEC_MICBIAS_MMICBIASEN, 0, NULL, 0),
-+
-+	SND_SOC_DAPM_REGULATOR_SUPPLY("avcc", 0, 0),
-+	SND_SOC_DAPM_REGULATOR_SUPPLY("hpvcc", 0, 0),
-+	SND_SOC_DAPM_REGULATOR_SUPPLY("vdd33", 0, 0),
-+};
-+
-+static const struct snd_soc_dapm_route sun20i_codec_routes[] = {
-+	/* Playback */
-+	{ "LINEOUTL", NULL, "LINEOUTL Switch" },
-+	{ "LINEOUTR", NULL, "LINEOUTR Switch" },
-+
-+	{ "LINEOUTL Switch", "Line Out Playback Switch", "DACL" },
-+	{ "LINEOUTR Switch", "Line Out Playback Switch", "DACR" },
-+
-+	{ "HPOUTL", NULL, "HPOUTL Switch" },
-+	{ "HPOUTR", NULL, "HPOUTR Switch" },
-+
-+	{ "HPOUTL Switch", "Headphone Playback Switch", "DACL" },
-+	{ "HPOUTR Switch", "Headphone Playback Switch", "DACR" },
-+	{ "HPOUTL Switch", NULL, "Headphone Driver" },
-+	{ "HPOUTR Switch", NULL, "Headphone Driver" },
-+	{ "Headphone Driver", NULL, "hpvcc" },
-+
-+	{ "DACL", NULL, "DACL FIFO" },
-+	{ "DACR", NULL, "DACR FIFO" },
-+	{ "DACL", NULL, "DAC" },
-+	{ "DACR", NULL, "DAC" },
-+	{ "DACL", NULL, "avcc" },
-+	{ "DACR", NULL, "avcc" },
-+
-+	/* Capture */
-+	{ "ADC1 FIFO", NULL, "ADC1" },
-+	{ "ADC2 FIFO", NULL, "ADC2" },
-+	{ "ADC3 FIFO", NULL, "ADC3" },
-+
-+	{ "ADC1", NULL, "ADC1 Mixer" },
-+	{ "ADC2", NULL, "ADC2 Mixer" },
-+	{ "ADC3", NULL, "ADC3 Mixer" },
-+	{ "ADC1", NULL, "ADC" },
-+	{ "ADC2", NULL, "ADC" },
-+	{ "ADC3", NULL, "ADC" },
-+	{ "ADC1", NULL, "avcc" },
-+	{ "ADC2", NULL, "avcc" },
-+	{ "ADC3", NULL, "avcc" },
-+
-+	{ "ADC1 Mixer", "Mic1 Capture Switch", "Mic1" },
-+	{ "ADC2 Mixer", "Mic2 Capture Switch", "Mic2" },
-+	{ "ADC3 Mixer", "Mic3 Capture Switch", "Mic3" },
-+	{ "ADC1 Mixer", "FM Capture Switch", "FMINL" },
-+	{ "ADC2 Mixer", "FM Capture Switch", "FMINR" },
-+	{ "ADC1 Mixer", "Line In Capture Switch", "LINEINL" },
-+	{ "ADC2 Mixer", "Line In Capture Switch", "LINEINR" },
-+
-+	{ "Mic1", NULL, "MICIN1" },
-+	{ "Mic2", NULL, "MICIN2" },
-+	{ "Mic3", NULL, "MICIN3" },
-+
-+	{ "HBIAS", NULL, "vdd33" },
-+	{ "MBIAS", NULL, "vdd33" },
-+};
-+
-+static int sun20i_codec_component_probe(struct snd_soc_component *component)
-+{
-+	struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
-+	int ret;
-+
-+	ret = reset_control_deassert(codec->reset);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(codec->bus_clk);
-+	if (ret)
-+		goto err_assert_reset;
-+
-+	/* Enable digital volume control. */
-+	snd_soc_component_update_bits(component, SUN20I_CODEC_DAC_VOL_CTRL,
-+				      0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL,
-+				      0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL);
-+	snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
-+				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
-+				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
-+
-+	return 0;
-+
-+err_assert_reset:
-+	reset_control_assert(codec->reset);
-+
-+	return ret;
-+}
-+
-+static void sun20i_codec_component_remove(struct snd_soc_component *component)
-+{
-+	struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
-+
-+	clk_disable_unprepare(codec->bus_clk);
-+	reset_control_assert(codec->reset);
-+}
-+
-+static const struct snd_soc_component_driver sun20i_codec_component = {
-+	.controls		= sun20i_codec_controls,
-+	.num_controls		= ARRAY_SIZE(sun20i_codec_controls),
-+	.dapm_widgets		= sun20i_codec_widgets,
-+	.num_dapm_widgets	= ARRAY_SIZE(sun20i_codec_widgets),
-+	.dapm_routes		= sun20i_codec_routes,
-+	.num_dapm_routes	= ARRAY_SIZE(sun20i_codec_routes),
-+	.probe			= sun20i_codec_component_probe,
-+	.remove			= sun20i_codec_component_remove,
-+};
-+
-+static int sun20i_codec_init_card(struct device *dev,
-+				  struct sun20i_codec *codec)
-+{
-+	struct snd_soc_dai_link *dai_link = &codec->dai_link;
-+	struct snd_soc_card *card = &codec->card;
-+	int ret;
-+
-+	codec->dlcs[0].of_node	= dev->of_node;
-+	codec->dlcs[0].dai_name	= DRIVER_NAME;
-+	codec->dlcs[1].name	= "snd-soc-dummy";
-+	codec->dlcs[1].dai_name	= "snd-soc-dummy-dai";
-+	codec->dlcs[2].of_node	= dev->of_node;
-+
-+	dai_link->name		= DRIVER_NAME;
-+	dai_link->stream_name	= DRIVER_NAME;
-+	dai_link->cpus		= &codec->dlcs[0];
-+	dai_link->num_cpus	= 1;
-+	dai_link->codecs	= &codec->dlcs[1];
-+	dai_link->num_codecs	= 1;
-+	dai_link->platforms	= &codec->dlcs[2];
-+	dai_link->num_platforms	= 1;
-+
-+	card->name		= DRIVER_NAME;
-+	card->dev		= dev;
-+	card->owner		= THIS_MODULE;
-+	card->dai_link		= dai_link;
-+	card->num_links		= 1;
-+	card->fully_routed	= true;
-+
-+	ret = snd_soc_of_parse_aux_devs(card, "aux-devs");
-+	if (ret)
-+		return ret;
-+
-+	ret = snd_soc_of_parse_pin_switches(card, "pin-switches");
-+	if (ret)
-+		return ret;
-+
-+	ret = snd_soc_of_parse_audio_routing(card, "routing");
-+	if (ret)
-+		return ret;
-+
-+	ret = snd_soc_of_parse_audio_simple_widgets(card, "widgets");
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static const struct regmap_config sun20i_codec_regmap_config = {
-+	.reg_bits		= 32,
-+	.reg_stride		= 4,
-+	.val_bits		= 32,
-+	.max_register		= SUN20I_CODEC_ADC_CUR,
-+};
-+
-+static int sun20i_codec_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct sun20i_codec *codec;
-+	struct regmap *regmap;
-+	struct resource *res;
-+	void __iomem *base;
-+	int ret;
-+
-+	codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL);
-+	if (!codec)
-+		return -ENOMEM;
-+
-+	dev_set_drvdata(dev, codec);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	base = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(base))
-+		return dev_err_probe(dev, PTR_ERR(base),
-+				     "Failed to map registers\n");
-+
-+	regmap = devm_regmap_init_mmio(dev, base,
-+				       &sun20i_codec_regmap_config);
-+	if (IS_ERR(regmap))
-+		return dev_err_probe(dev, PTR_ERR(regmap),
-+				     "Failed to create regmap\n");
-+
-+	codec->bus_clk = devm_clk_get(dev, "bus");
-+	if (IS_ERR(codec->bus_clk))
-+		return dev_err_probe(dev, PTR_ERR(codec->bus_clk),
-+				     "Failed to get bus clock\n");
-+
-+	codec->adc_clk = devm_clk_get(dev, "adc");
-+	if (IS_ERR(codec->adc_clk))
-+		return dev_err_probe(dev, PTR_ERR(codec->adc_clk),
-+				     "Failed to get ADC clock\n");
-+
-+	codec->dac_clk = devm_clk_get(dev, "dac");
-+	if (IS_ERR(codec->dac_clk))
-+		return dev_err_probe(dev, PTR_ERR(codec->dac_clk),
-+				     "Failed to get DAC clock\n");
-+
-+	codec->reset = devm_reset_control_get_exclusive(dev, NULL);
-+	if (IS_ERR(codec->reset))
-+		return dev_err_probe(dev, PTR_ERR(codec->reset),
-+				     "Failed to get reset\n");
-+
-+	ret = devm_snd_soc_register_component(dev, &sun20i_codec_component,
-+					      &sun20i_codec_dai, 1);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to register component\n");
-+
-+	codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
-+			res->start + SUN20I_CODEC_DAC_TXDATA;
-+	codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 8;
-+	codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
-+			res->start + SUN20I_CODEC_ADC_RXDATA;
-+	codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 8;
-+
-+	ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to register PCM\n");
-+
-+	ret = sun20i_codec_init_card(dev, codec);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to initialize card\n");
-+
-+	ret = devm_snd_soc_register_card(dev, &codec->card);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to register card\n");
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id sun20i_codec_of_match[] = {
-+	{ .compatible = "allwinner,sun20i-d1-codec" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, sun20i_codec_of_match);
-+
-+static struct platform_driver sun20i_codec_driver = {
-+	.driver	= {
-+		.name		= DRIVER_NAME,
-+		.of_match_table	= sun20i_codec_of_match,
-+	},
-+	.probe	= sun20i_codec_probe,
-+};
-+module_platform_driver(sun20i_codec_driver);
-+
-+MODULE_DESCRIPTION("Allwinner D1 (sun20i) codec driver");
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:sun20i-codec");
diff --git a/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch b/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch
deleted file mode 100644
index d837c6afdc..0000000000
--- a/target/linux/d1/patches-6.1/0082-ASoC-sun20i-codec-What-is-this-ramp-thing.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 87a77f803f5038e3fc64f45d5142ea402512029a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 23 Jun 2021 21:18:47 -0500
-Subject: [PATCH 082/117] ASoC: sun20i-codec: What is this ramp thing?
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun20i-codec.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/sound/soc/sunxi/sun20i-codec.c
-+++ b/sound/soc/sunxi/sun20i-codec.c
-@@ -709,6 +709,10 @@ static int sun20i_codec_component_probe(
- 				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
- 				      0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
- 
-+	/* Maaagic... */
-+	snd_soc_component_update_bits(component, SUN20I_CODEC_RAMP,
-+				      BIT(1) | BIT(0), BIT(0));
-+
- 	return 0;
- 
- err_assert_reset:
diff --git a/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch b/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch
deleted file mode 100644
index b0f93c3a48..0000000000
--- a/target/linux/d1/patches-6.1/0083-riscv-dts-allwinner-d1-Add-sound-cards-to-boards.patch
+++ /dev/null
@@ -1,132 +0,0 @@
-From 54b1030c72d74ba6390d62086cbfc6a511f58aa7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 00:39:42 -0500
-Subject: [PATCH 083/117] riscv: dts: allwinner: d1: Add sound cards to boards
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-common-regulators.dtsi          |  5 +++++
- .../sun20i-d1-lichee-rv-86-panel.dtsi         | 21 +++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 12 +++++++++++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 12 +++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi  | 13 +++++++++++-
- 5 files changed, 62 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -18,6 +18,11 @@
- 	};
- };
- 
-+&codec {
-+	avcc-supply = <&reg_aldo>;
-+	hpvcc-supply = <&reg_hpldo>;
-+};
-+
- &lradc {
- 	vref-supply = <&reg_aldo>;
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -9,6 +9,12 @@
- 		ethernet1 = &xr829;
- 	};
- 
-+	audio_amplifier: audio-amplifier {
-+		compatible = "simple-audio-amplifier";
-+		enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
-+		sound-name-prefix = "Amplifier";
-+	};
-+
- 	dmic_codec: dmic-codec {
- 		compatible = "dmic-codec";
- 		num-channels = <2>;
-@@ -51,6 +57,21 @@
- 	};
- };
- 
-+&codec {
-+	aux-devs = <&audio_amplifier>;
-+	routing = "Internal Speaker", "Amplifier OUTL",
-+		  "Internal Speaker", "Amplifier OUTR",
-+		  "Amplifier INL", "HPOUTL",
-+		  "Amplifier INR", "HPOUTR",
-+		  "LINEINL", "HPOUTL",
-+		  "LINEINR", "HPOUTR",
-+		  "MICIN3", "Internal Microphone",
-+		  "Internal Microphone", "HBIAS";
-+	widgets = "Microphone", "Internal Microphone",
-+		  "Speaker", "Internal Speaker";
-+	status = "okay";
-+};
-+
- &dmic {
- 	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
- 	pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -48,6 +48,18 @@
- 	};
- };
- 
-+&codec {
-+	routing = "Internal Speaker", "HPOUTL",
-+		  "Internal Speaker", "HPOUTR",
-+		  "LINEINL", "HPOUTL",
-+		  "LINEINR", "HPOUTR",
-+		  "MICIN3", "Internal Microphone",
-+		  "Internal Microphone", "HBIAS";
-+	widgets = "Microphone", "Internal Microphone",
-+		  "Speaker", "Internal Speaker";
-+	status = "okay";
-+};
-+
- &dmic {
- 	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
- 	pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -51,6 +51,18 @@
- 	};
- };
- 
-+&codec {
-+	routing = "Headphone Jack", "HPOUTL",
-+		  "Headphone Jack", "HPOUTR",
-+		  "LINEINL", "HPOUTL",
-+		  "LINEINR", "HPOUTR",
-+		  "MICIN3", "Headset Microphone",
-+		  "Headset Microphone", "HBIAS";
-+	widgets = "Microphone", "Headset Microphone",
-+		  "Headphone", "Headphone Jack";
-+	status = "okay";
-+};
-+
- &cpu0 {
- 	cpu-supply = <&reg_vdd_cpu>;
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -312,10 +312,21 @@
- 		};
- 
- 		codec: audio-codec@2030000 {
--			compatible = "simple-mfd", "syscon";
-+			compatible = "allwinner,sun20i-d1-codec", "simple-mfd", "syscon";
- 			reg = <0x2030000 0x1000>;
-+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_AUDIO>,
-+				 <&ccu CLK_AUDIO_ADC>,
-+				 <&ccu CLK_AUDIO_DAC>,
-+				 <&osc24M>,
-+				 <&rtc CLK_OSC32K>;
-+			clock-names = "bus", "adc", "dac", "hosc", "losc";
-+			resets = <&ccu RST_BUS_AUDIO>;
-+			dmas = <&dma 7>, <&dma 7>;
-+			dma-names = "rx", "tx";
- 			#address-cells = <1>;
- 			#size-cells = <1>;
-+			#sound-dai-cells = <0>;
- 
- 			regulators@2030348 {
- 				compatible = "allwinner,sun20i-d1-analog-ldos";
diff --git a/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch b/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch
deleted file mode 100644
index e74ea35e5a..0000000000
--- a/target/linux/d1/patches-6.1/0084-drm-sun4i-dsi-Allow-panel-attach-before-card-registr.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From bae2790f627eb30ec3845167341b108e13328f6f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:46:43 -0500
-Subject: [PATCH 084/117] drm/sun4i: dsi: Allow panel attach before card
- registration
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -967,13 +967,12 @@ static int sun6i_dsi_attach(struct mipi_
- 
- 	if (IS_ERR(panel))
- 		return PTR_ERR(panel);
--	if (!dsi->drm || !dsi->drm->registered)
--		return -EPROBE_DEFER;
- 
- 	dsi->panel = panel;
- 	dsi->device = device;
- 
--	drm_kms_helper_hotplug_event(dsi->drm);
-+	if (dsi->drm && dsi->drm->registered)
-+		drm_kms_helper_hotplug_event(dsi->drm);
- 
- 	dev_info(host->dev, "Attached device %s\n", device->name);
- 
-@@ -988,7 +987,8 @@ static int sun6i_dsi_detach(struct mipi_
- 	dsi->panel = NULL;
- 	dsi->device = NULL;
- 
--	drm_kms_helper_hotplug_event(dsi->drm);
-+	if (dsi->drm && dsi->drm->registered)
-+		drm_kms_helper_hotplug_event(dsi->drm);
- 
- 	return 0;
- }
diff --git a/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch b/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch
deleted file mode 100644
index ae47bbed26..0000000000
--- a/target/linux/d1/patches-6.1/0085-drm-sun4i-mixer-Remove-unused-CMA-headers.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 5755bea969adcb00b102271b0cbaa3002acd7a35 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 18:50:01 -0500
-Subject: [PATCH 085/117] drm/sun4i: mixer: Remove unused CMA headers
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
-@@ -17,7 +17,7 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc.h>
- #include <drm/drm_framebuffer.h>
--#include <drm/drm_gem_dma_helper.h>
-+#include <drm/drm_print.h>
- #include <drm/drm_probe_helper.h>
- 
- #include "sun4i_drv.h"
diff --git a/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch b/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch
deleted file mode 100644
index 8a6015bc56..0000000000
--- a/target/linux/d1/patches-6.1/0086-drm-sun4i-decouple-TCON_DCLK_DIV-value-from-pll_mipi.patch
+++ /dev/null
@@ -1,110 +0,0 @@
-From 9a7acb8f03346705d7420a490d95b32309d90e22 Mon Sep 17 00:00:00 2001
-From: Roman Beranek <roman.beranek@prusa3d.com>
-Date: Wed, 25 Nov 2020 13:07:35 +0100
-Subject: [PATCH 086/117] drm/sun4i: decouple TCON_DCLK_DIV value from
- pll_mipi/dotclock ratio
-
-Observations showed that an actual refresh rate differs from the intended.
-Specifically, in case of 4-lane panels it was reduced by 1/3, and in case of
-2-lane panels by 2/3.
-
-BSP code apparently distinguishes between a `dsi_div` and a 'tcon inner div'.
-While this 'inner' divider is under DSI always 4, the `dsi_div` is defined
-as a number of bits per pixel over a number of DSI lanes. This value is then
-involved in setting the rate of PLL_MIPI.
-
-I couldn't really figure out how to fit this into the dotclock driver,
-so I opted for this hack where the requested rate is adjusted in such a way
-that the sun4i_dotclock driver can remain untouched.
-
-Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun4i_tcon.c | 44 +++++++++++++++++-------------
- 1 file changed, 25 insertions(+), 19 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-@@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(cons
- 	return delay;
- }
- 
--static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
--					const struct drm_display_mode *mode)
--{
--	/* Configure the dot clock */
--	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
--
--	/* Set the resolution */
--	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
--		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
--		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
--}
--
- static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
- 					   const struct drm_connector *connector)
- {
-@@ -365,12 +353,18 @@ static void sun4i_tcon0_mode_set_cpu(str
- 	u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
- 	u8 lanes = device->lanes;
- 	u32 block_space, start_delay;
--	u32 tcon_div;
- 
- 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
- 	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
- 
--	sun4i_tcon0_mode_set_common(tcon, mode);
-+	/* Configure the dot clock */
-+	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000
-+				 * bpp / (lanes * SUN6I_DSI_TCON_DIV));
-+
-+        /* Set the resolution */
-+	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
- 
- 	/* Set dithering if needed */
- 	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
-@@ -394,9 +388,7 @@ static void sun4i_tcon0_mode_set_cpu(str
- 	 * The datasheet says that this should be set higher than 20 *
- 	 * pixel cycle, but it's not clear what a pixel cycle is.
- 	 */
--	regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
--	tcon_div &= GENMASK(6, 0);
--	block_space = mode->htotal * bpp / (tcon_div * lanes);
-+	block_space = mode->htotal * bpp / (SUN6I_DSI_TCON_DIV * lanes);
- 	block_space -= mode->hdisplay + 40;
- 
- 	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
-@@ -438,7 +430,14 @@ static void sun4i_tcon0_mode_set_lvds(st
- 
- 	tcon->dclk_min_div = 7;
- 	tcon->dclk_max_div = 7;
--	sun4i_tcon0_mode_set_common(tcon, mode);
-+
-+	/* Configure the dot clock */
-+	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-+
-+        /* Set the resolution */
-+	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
- 
- 	/* Set dithering if needed */
- 	sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
-@@ -515,7 +514,14 @@ static void sun4i_tcon0_mode_set_rgb(str
- 
- 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
- 	tcon->dclk_max_div = 127;
--	sun4i_tcon0_mode_set_common(tcon, mode);
-+
-+	/* Configure the dot clock */
-+	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-+
-+	/* Set the resolution */
-+	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
- 
- 	/* Set dithering if needed */
- 	sun4i_tcon0_mode_set_dithering(tcon, connector);
diff --git a/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch b/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch
deleted file mode 100644
index 7e404eecd1..0000000000
--- a/target/linux/d1/patches-6.1/0087-drm-sun4i-tcon-Always-protect-the-LCD-dotclock-rate.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 9ea0c216d4f85a8ea888a38853e9573bbd9e995a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 21:09:39 -0500
-Subject: [PATCH 087/117] drm/sun4i: tcon: Always protect the LCD dotclock rate
-
-This handles the case where multiple CRTCs get their .mode_set function
-called during the same atomic commit, before rate protection is applied
-by enabling the CRTC.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 4 ++++
- drivers/gpu/drm/sun4i/sun4i_tcon.c     | 6 ++++--
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
-@@ -6,6 +6,7 @@
-  * Maxime Ripard <maxime.ripard@free-electrons.com>
-  */
- 
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/regmap.h>
- 
-@@ -194,12 +195,15 @@ int sun4i_dclk_create(struct device *dev
- 	if (IS_ERR(tcon->dclk))
- 		return PTR_ERR(tcon->dclk);
- 
-+	clk_rate_exclusive_get(tcon->dclk);
-+
- 	return 0;
- }
- EXPORT_SYMBOL(sun4i_dclk_create);
- 
- int sun4i_dclk_free(struct sun4i_tcon *tcon)
- {
-+	clk_rate_exclusive_put(tcon->dclk);
- 	clk_unregister(tcon->dclk);
- 	return 0;
- }
---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_statu
- 
- 	if (enabled) {
- 		clk_prepare_enable(clk);
--		clk_rate_exclusive_get(clk);
-+		if (clk != tcon->dclk)
-+			clk_rate_exclusive_get(clk);
- 	} else {
--		clk_rate_exclusive_put(clk);
-+		if (clk != tcon->dclk)
-+			clk_rate_exclusive_put(clk);
- 		clk_disable_unprepare(clk);
- 	}
- }
diff --git a/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch b/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch
deleted file mode 100644
index fae19b8087..0000000000
--- a/target/linux/d1/patches-6.1/0088-drm-sun4i-tcon_top-Register-reset-clock-gates-in-pro.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From f792492db1f42c43eb4b8bb72ce573418afc933d Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Tue, 31 Dec 2019 18:35:24 +0530
-Subject: [PATCH 088/117] drm/sun4i: tcon_top: Register reset, clock gates in
- probe
-
-TCON TOP is processing clock gates and reset control for
-TV0, TV1 and DSI channels during bind and release the same
-during unbind component ops.
-
-The usual DSI initialization would setup all controller
-clocks along with DPHY clocking during probe.
-
-Since the actual clock gates (along with DSI clock gate)
-are initialized during ton top bind, the DPHY is failed to
-get the DSI clock during that time.
-
-To solve, this circular dependency move the reset control,
-clock gate registration from bind to probe and release the
-same from unbind to remove.
-
-This eventually give a chance DPHY to initialize the DSI
-clock gate.
-
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 42 ++++++++++++++------------
- 1 file changed, 22 insertions(+), 20 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
-@@ -124,14 +124,29 @@ static struct clk_hw *sun8i_tcon_top_reg
- static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
- 			       void *data)
- {
--	struct platform_device *pdev = to_platform_device(dev);
-+	return 0;
-+}
-+
-+static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
-+				  void *data)
-+{
-+}
-+
-+static const struct component_ops sun8i_tcon_top_ops = {
-+	.bind	= sun8i_tcon_top_bind,
-+	.unbind	= sun8i_tcon_top_unbind,
-+};
-+
-+static int sun8i_tcon_top_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
- 	struct clk_hw_onecell_data *clk_data;
- 	struct sun8i_tcon_top *tcon_top;
- 	const struct sun8i_tcon_top_quirks *quirks;
- 	void __iomem *regs;
- 	int ret, i;
- 
--	quirks = of_device_get_match_data(&pdev->dev);
-+	quirks = of_device_get_match_data(dev);
- 
- 	tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
- 	if (!tcon_top)
-@@ -222,7 +237,7 @@ static int sun8i_tcon_top_bind(struct de
- 
- 	dev_set_drvdata(dev, tcon_top);
- 
--	return 0;
-+	return component_add(dev, &sun8i_tcon_top_ops);
- 
- err_unregister_gates:
- 	for (i = 0; i < CLK_NUM; i++)
-@@ -235,13 +250,15 @@ err_assert_reset:
- 	return ret;
- }
- 
--static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
--				  void *data)
-+static int sun8i_tcon_top_remove(struct platform_device *pdev)
- {
-+	struct device *dev = &pdev->dev;
- 	struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
- 	struct clk_hw_onecell_data *clk_data = tcon_top->clk_data;
- 	int i;
- 
-+	component_del(dev, &sun8i_tcon_top_ops);
-+
- 	of_clk_del_provider(dev->of_node);
- 	for (i = 0; i < CLK_NUM; i++)
- 		if (clk_data->hws[i])
-@@ -249,21 +266,6 @@ static void sun8i_tcon_top_unbind(struct
- 
- 	clk_disable_unprepare(tcon_top->bus);
- 	reset_control_assert(tcon_top->rst);
--}
--
--static const struct component_ops sun8i_tcon_top_ops = {
--	.bind	= sun8i_tcon_top_bind,
--	.unbind	= sun8i_tcon_top_unbind,
--};
--
--static int sun8i_tcon_top_probe(struct platform_device *pdev)
--{
--	return component_add(&pdev->dev, &sun8i_tcon_top_ops);
--}
--
--static int sun8i_tcon_top_remove(struct platform_device *pdev)
--{
--	component_del(&pdev->dev, &sun8i_tcon_top_ops);
- 
- 	return 0;
- }
diff --git a/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch b/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch
deleted file mode 100644
index ce7510d156..0000000000
--- a/target/linux/d1/patches-6.1/0089-riscv-dts-allwinner-lichee-rv-86-panel-480p-Add-pane.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 03dbb926f6d65f75af902e421c44aeaaf84be66a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:46:28 -0500
-Subject: [PATCH 089/117] riscv: dts: allwinner: lichee-rv-86-panel-480p: Add
- panel
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-lichee-rv-86-panel-480p.dts     | 51 +++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-@@ -7,6 +7,40 @@
- 	model = "Sipeed Lichee RV 86 Panel (480p)";
- 	compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
- 		     "allwinner,sun20i-d1";
-+
-+	backlight: backlight {
-+		compatible = "pwm-backlight";
-+		power-supply = <&reg_vcc>;
-+		pwms = <&pwm 7 50000 0>;
-+	};
-+
-+	spi {
-+		compatible = "spi-gpio";
-+		cs-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
-+		mosi-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
-+		sck-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
-+		num-chipselects = <1>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		panel@0 {
-+			compatible = "sitronix,st7701s";
-+			reg = <0>;
-+			backlight = <&backlight>;
-+			reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
-+			spi-3wire;
-+
-+			port {
-+				panel_in_tcon_lcd0: endpoint {
-+					remote-endpoint = <&tcon_lcd0_out_panel>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&de {
-+	status = "okay";
- };
- 
- &i2c2 {
-@@ -27,3 +61,20 @@
- 		wakeup-source;
- 	};
- };
-+
-+&pwm {
-+	pinctrl-0 = <&pwm7_pd22_pin>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&tcon_lcd0 {
-+	pinctrl-0 = <&lcd_rgb666_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&tcon_lcd0_out {
-+	tcon_lcd0_out_panel: endpoint {
-+		remote-endpoint = <&panel_in_tcon_lcd0>;
-+	};
-+};
diff --git a/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch b/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch
deleted file mode 100644
index e6e992b9e6..0000000000
--- a/target/linux/d1/patches-6.1/0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:59:29 -0500
-Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
- 1 file changed, 49 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -124,6 +124,14 @@
- 			#interrupt-cells = <3>;
- 
- 			/omit-if-no-ref/
-+			dsi_4lane_pins: dsi-4lane-pins {
-+				pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
-+				       "PD6", "PD7", "PD8", "PD9";
-+				drive-strength = <30>;
-+				function = "dsi";
-+			};
-+
-+			/omit-if-no-ref/
- 			i2c0_pb10_pins: i2c0-pb10-pins {
- 				pins = "PB10", "PB11";
- 				function = "i2c0";
-@@ -903,6 +911,40 @@
- 			};
- 		};
- 
-+		dsi: dsi@5450000 {
-+			compatible = "allwinner,sun20i-d1-mipi-dsi",
-+				     "allwinner,sun50i-a100-mipi-dsi";
-+			reg = <0x5450000 0x1000>;
-+			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
-+				 <&tcon_top CLK_TCON_TOP_DSI>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_MIPI_DSI>;
-+			phys = <&dphy>;
-+			phy-names = "dphy";
-+			status = "disabled";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			port {
-+				dsi_in_tcon_lcd0: endpoint {
-+					remote-endpoint = <&tcon_lcd0_out_dsi>;
-+				};
-+			};
-+		};
-+
-+		dphy: phy@5451000 {
-+			compatible = "allwinner,sun20i-d1-mipi-dphy",
-+				     "allwinner,sun50i-a100-mipi-dphy";
-+			reg = <0x5451000 0x1000>;
-+			interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
-+				 <&ccu CLK_MIPI_DSI>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_MIPI_DSI>;
-+			#phy-cells = <0>;
-+		};
-+
- 		tcon_top: tcon-top@5460000 {
- 			compatible = "allwinner,sun20i-d1-tcon-top";
- 			reg = <0x5460000 0x1000>;
-@@ -1022,6 +1064,13 @@
- 
- 				tcon_lcd0_out: port@1 {
- 					reg = <1>;
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+
-+					tcon_lcd0_out_dsi: endpoint@1 {
-+						reg = <1>;
-+						remote-endpoint = <&dsi_in_tcon_lcd0>;
-+					};
- 				};
- 			};
- 		};
diff --git a/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch b/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch
deleted file mode 100644
index 60855f0f1c..0000000000
--- a/target/linux/d1/patches-6.1/0091-riscv-dts-allwinner-devterm-Add-DSI-panel-and-backli.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 7ac17ab7ea644ec27935865d6d0208ecc7fd4ed9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:29:03 -0500
-Subject: [PATCH 091/117] riscv: dts: allwinner: devterm: Add DSI panel and
- backlight
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts |  8 +++++++-
- .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 20 +++++++++++++++++++
- 2 files changed, 27 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -48,6 +48,12 @@
- 		};
- 	};
- 
-+	backlight: backlight {
-+		compatible = "pwm-backlight";
-+		power-supply = <&reg_vcc>;
-+		pwms = <&pwm 4 50000 0>; /* PD20/GPIO9 */
-+	};
-+
- 	reg_vdd_cpu: vdd-cpu {
- 		compatible = "pwm-regulator";
- 		pwms = <&pwm 0 50000 0>;
-@@ -252,7 +258,7 @@
- };
- 
- &pwm {
--	pinctrl-0 = <&pwm0_pd16_pin>;
-+	pinctrl-0 = <&pwm0_pd16_pin>, <&pwm4_pd20_pin>;
- 	pinctrl-names = "default";
- 	status = "okay";
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-@@ -35,3 +35,23 @@
- 		};
- 	};
- };
-+
-+&de {
-+	status = "okay";
-+};
-+
-+&dsi {
-+	pinctrl-0 = <&dsi_4lane_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+
-+	panel@0 {
-+		compatible = "clockwork,cwd686";
-+		reg = <0>;
-+		backlight = <&backlight>;
-+		reset-gpios = <&pio 3 19 GPIO_ACTIVE_LOW>; /* PD19/GPIO8 */
-+		rotation = <90>;
-+		iovcc-supply = <&reg_dcdc3>;
-+		vci-supply = <&reg_aldo2>;
-+	};
-+};
diff --git a/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch b/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch
deleted file mode 100644
index a8c6b685cd..0000000000
--- a/target/linux/d1/patches-6.1/0092-dt-bindings-display-sun4i-tcon-Add-external-LVDS-PHY.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 822fdc3556b688103cdaf7b4b34e98fbe1676425 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:58:02 -0500
-Subject: [PATCH 092/117] dt-bindings: display: sun4i-tcon: Add external LVDS
- PHY
-
-A100 and D1 use the same "combo" PHY for LVDS0 and DSI.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun4i-a10-tcon.yaml         | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
-@@ -80,6 +80,13 @@ properties:
-   dmas:
-     maxItems: 1
- 
-+  phys:
-+    maxItems: 1
-+
-+  phy-names:
-+    items:
-+      - const: "lvds0"
-+
-   resets:
-     anyOf:
-       - items:
diff --git a/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch b/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch
deleted file mode 100644
index f80b125c67..0000000000
--- a/target/linux/d1/patches-6.1/0093-riscv-dts-allwinner-d1-Add-LVDS0-PHY.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 7d95f6b52ea5f01c9e2414d4984e5a274328c021 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:58:57 -0500
-Subject: [PATCH 093/117] riscv: dts: allwinner: d1: Add LVDS0 PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -1040,6 +1040,8 @@
- 			resets = <&ccu RST_BUS_TCON_LCD0>,
- 				 <&ccu RST_BUS_LVDS0>;
- 			reset-names = "lcd", "lvds";
-+			phys = <&dphy>;
-+			phy-names = "lvds0";
- 			#clock-cells = <0>;
- 
- 			ports {
diff --git a/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch b/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch
deleted file mode 100644
index 6006310298..0000000000
--- a/target/linux/d1/patches-6.1/0094-dt-bindings-display-sun6i-dsi-Fix-clock-conditional.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From d0f7ed9dc803e09fb6c1e895efbd1182c9212483 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:49:30 -0500
-Subject: [PATCH 094/117] dt-bindings: display: sun6i-dsi: Fix clock
- conditional
-
-The A64 case should have limited maxItems, instead of duplicating the
-minItems value from the main binding. While here, simplify the binding
-by making this an "else" case of the two-clock conditional block.
-
-Fixes: fe5040f2843a ("dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controller")
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 10 ++--------
- 1 file changed, 2 insertions(+), 8 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-@@ -78,16 +78,10 @@ allOf:
-       required:
-         - clock-names
- 
--  - if:
--      properties:
--        compatible:
--          contains:
--            const: allwinner,sun50i-a64-mipi-dsi
--
--    then:
-+    else:
-       properties:
-         clocks:
--          minItems: 1
-+          maxItems: 1
- 
- unevaluatedProperties: false
- 
diff --git a/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch b/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch
deleted file mode 100644
index 325c2528a5..0000000000
--- a/target/linux/d1/patches-6.1/0095-dt-bindings-display-sun6i-dsi-Add-the-A100-variant.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 30abd0e5f27bc57fba7084ba51aca671316b6d24 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:50:21 -0500
-Subject: [PATCH 095/117] dt-bindings: display: sun6i-dsi: Add the A100 variant
-
-The "40nm" MIPI DSI controller found in the A100 and D1 SoCs has the
-same register layout as previous SoC integrations. However, its module
-clock now comes from the TCON, which means it no longer runs at a fixed
-rate, so this needs to be distinguished in the driver.
-
-The controller also now uses pins on Port D instead of dedicated pins,
-so it drops the separate power domain.
-
-Commit-notes:
-Removal of the vcc-dsi-supply is maybe a bit questionable. Since there
-is no "VCC-DSI" pin anymore, it's not obvious which pin actually does
-power the DSI controller/PHY. Possibly power comes from VCC-PD or VCC-IO
-or VCC-LVDS. So far, all boards have all of these as always-on supplies,
-so it is hard to test.
-END
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 28 +++++++++++++++----
- 1 file changed, 23 insertions(+), 5 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-@@ -12,9 +12,14 @@ maintainers:
- 
- properties:
-   compatible:
--    enum:
--      - allwinner,sun6i-a31-mipi-dsi
--      - allwinner,sun50i-a64-mipi-dsi
-+    oneOf:
-+      - enum:
-+          - allwinner,sun6i-a31-mipi-dsi
-+          - allwinner,sun50i-a64-mipi-dsi
-+          - allwinner,sun50i-a100-mipi-dsi
-+      - items:
-+          - const: allwinner,sun20i-d1-mipi-dsi
-+          - const: allwinner,sun50i-a100-mipi-dsi
- 
-   reg:
-     maxItems: 1
-@@ -59,7 +64,6 @@ required:
-   - phys
-   - phy-names
-   - resets
--  - vcc-dsi-supply
-   - port
- 
- allOf:
-@@ -68,7 +72,9 @@ allOf:
-       properties:
-         compatible:
-           contains:
--            const: allwinner,sun6i-a31-mipi-dsi
-+            enum:
-+              - allwinner,sun6i-a31-mipi-dsi
-+              - allwinner,sun50i-a100-mipi-dsi
- 
-     then:
-       properties:
-@@ -83,6 +89,18 @@ allOf:
-         clocks:
-           maxItems: 1
- 
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - allwinner,sun6i-a31-mipi-dsi
-+              - allwinner,sun50i-a64-mipi-dsi
-+
-+    then:
-+      required:
-+        - vcc-dsi-supply
-+
- unevaluatedProperties: false
- 
- examples:
diff --git a/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch b/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch
deleted file mode 100644
index afe7a1ed42..0000000000
--- a/target/linux/d1/patches-6.1/0096-drm-sun4i-dsi-Add-a-variant-structure.patch
+++ /dev/null
@@ -1,158 +0,0 @@
-From 28e64e830ef487b400b3b943fa3bda83dfb2a937 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 22:03:42 -0500
-Subject: [PATCH 096/117] drm/sun4i: dsi: Add a variant structure
-
-Replace the ad-hoc calls to of_device_is_compatible() with a structure
-describing the differences between variants. This is in preparation for
-adding more variants to the driver.
-
-Series-changes: 2
- - Add the variant check to the probe error path
-
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 53 +++++++++++++++++---------
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h |  7 ++++
- 2 files changed, 42 insertions(+), 18 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -1101,12 +1101,16 @@ static const struct component_ops sun6i_
- 
- static int sun6i_dsi_probe(struct platform_device *pdev)
- {
-+	const struct sun6i_dsi_variant *variant;
- 	struct device *dev = &pdev->dev;
--	const char *bus_clk_name = NULL;
- 	struct sun6i_dsi *dsi;
- 	void __iomem *base;
- 	int ret;
- 
-+	variant = device_get_match_data(dev);
-+	if (!variant)
-+		return -EINVAL;
-+
- 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
- 	if (!dsi)
- 		return -ENOMEM;
-@@ -1114,10 +1118,7 @@ static int sun6i_dsi_probe(struct platfo
- 	dsi->dev = dev;
- 	dsi->host.ops = &sun6i_dsi_host_ops;
- 	dsi->host.dev = dev;
--
--	if (of_device_is_compatible(dev->of_node,
--				    "allwinner,sun6i-a31-mipi-dsi"))
--		bus_clk_name = "bus";
-+	dsi->variant = variant;
- 
- 	base = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(base)) {
-@@ -1142,7 +1143,7 @@ static int sun6i_dsi_probe(struct platfo
- 		return PTR_ERR(dsi->regs);
- 	}
- 
--	dsi->bus_clk = devm_clk_get(dev, bus_clk_name);
-+	dsi->bus_clk = devm_clk_get(dev, variant->has_mod_clk ? "bus" : NULL);
- 	if (IS_ERR(dsi->bus_clk))
- 		return dev_err_probe(dev, PTR_ERR(dsi->bus_clk),
- 				     "Couldn't get the DSI bus clock\n");
-@@ -1151,21 +1152,21 @@ static int sun6i_dsi_probe(struct platfo
- 	if (ret)
- 		return ret;
- 
--	if (of_device_is_compatible(dev->of_node,
--				    "allwinner,sun6i-a31-mipi-dsi")) {
-+	if (variant->has_mod_clk) {
- 		dsi->mod_clk = devm_clk_get(dev, "mod");
- 		if (IS_ERR(dsi->mod_clk)) {
- 			dev_err(dev, "Couldn't get the DSI mod clock\n");
- 			ret = PTR_ERR(dsi->mod_clk);
- 			goto err_attach_clk;
- 		}
--	}
- 
--	/*
--	 * In order to operate properly, that clock seems to be always
--	 * set to 297MHz.
--	 */
--	clk_set_rate_exclusive(dsi->mod_clk, 297000000);
-+		/*
-+		 * In order to operate properly, the module clock on the
-+		 * A31 variant always seems to be set to 297MHz.
-+		 */
-+		if (variant->set_mod_clk)
-+			clk_set_rate_exclusive(dsi->mod_clk, 297000000);
-+	}
- 
- 	dsi->dphy = devm_phy_get(dev, "dphy");
- 	if (IS_ERR(dsi->dphy)) {
-@@ -1191,7 +1192,8 @@ static int sun6i_dsi_probe(struct platfo
- err_remove_dsi_host:
- 	mipi_dsi_host_unregister(&dsi->host);
- err_unprotect_clk:
--	clk_rate_exclusive_put(dsi->mod_clk);
-+	if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
-+		clk_rate_exclusive_put(dsi->mod_clk);
- err_attach_clk:
- 	regmap_mmio_detach_clk(dsi->regs);
- 
-@@ -1205,16 +1207,31 @@ static int sun6i_dsi_remove(struct platf
- 
- 	component_del(&pdev->dev, &sun6i_dsi_ops);
- 	mipi_dsi_host_unregister(&dsi->host);
--	clk_rate_exclusive_put(dsi->mod_clk);
-+	if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
-+		clk_rate_exclusive_put(dsi->mod_clk);
- 
- 	regmap_mmio_detach_clk(dsi->regs);
- 
- 	return 0;
- }
- 
-+static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi_variant = {
-+	.has_mod_clk	= true,
-+	.set_mod_clk	= true,
-+};
-+
-+static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
-+};
-+
- static const struct of_device_id sun6i_dsi_of_table[] = {
--	{ .compatible = "allwinner,sun6i-a31-mipi-dsi" },
--	{ .compatible = "allwinner,sun50i-a64-mipi-dsi" },
-+	{
-+		.compatible	= "allwinner,sun6i-a31-mipi-dsi",
-+		.data		= &sun6i_a31_mipi_dsi_variant,
-+	},
-+	{
-+		.compatible	= "allwinner,sun50i-a64-mipi-dsi",
-+		.data		= &sun50i_a64_mipi_dsi_variant,
-+	},
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
-@@ -15,6 +15,11 @@
- 
- #define SUN6I_DSI_TCON_DIV	4
- 
-+struct sun6i_dsi_variant {
-+	bool			has_mod_clk;
-+	bool			set_mod_clk;
-+};
-+
- struct sun6i_dsi {
- 	struct drm_connector	connector;
- 	struct drm_encoder	encoder;
-@@ -31,6 +36,8 @@ struct sun6i_dsi {
- 	struct mipi_dsi_device	*device;
- 	struct drm_device	*drm;
- 	struct drm_panel	*panel;
-+
-+	const struct sun6i_dsi_variant *variant;
- };
- 
- static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
diff --git a/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch b/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch
deleted file mode 100644
index 0077e37ed4..0000000000
--- a/target/linux/d1/patches-6.1/0097-drm-sun4i-dsi-Add-the-A100-variant.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 713029c6a33df9218d11593bc5be79420715633f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:06:22 -0500
-Subject: [PATCH 097/117] drm/sun4i: dsi: Add the A100 variant
-
-The A100 variant of the MIPI DSI controller now gets its module clock
-from the TCON via the TCON TOP, so the clock rate cannot be set to a
-fixed value. Otherwise, it appears to be the same as the A31 variant.
-
-Cover-letter:
-drm/sun4i: dsi: Support the A100/D1 controller variant
-This series adds support for the digital part of the DSI controller
-found in the A100 and D1 SoCs (plus T7, which is not supported by
-mainline Linux). There are two changes to the hardware integration:
-  1) the module clock routes through the TCON TOP, and
-  2) the separate I/O domain is removed.
-
-The actual register interface appears to be the same as before. The
-register definitions in the D1 BSP exactly match the A64 BSP.
-
-The BSP describes this as the "40nm" DSI controller variant. There is
-also a "28nm" variant with a different register interface; that one is
-found in a different subset of SoCs (V5 and A50).
-
-A100/D1 also come with an updated DPHY, described by the BSP as a
-"combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI
-share the same pins on Port D.) Since that is a different subsystem,
-I am sending that as a separate series.
-END
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Maxime Ripard <mripard@kernel.org>
-
-Series-version: 2
-
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -1223,6 +1223,10 @@ static const struct sun6i_dsi_variant su
- static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
- };
- 
-+static const struct sun6i_dsi_variant sun50i_a100_mipi_dsi_variant = {
-+	.has_mod_clk	= true,
-+};
-+
- static const struct of_device_id sun6i_dsi_of_table[] = {
- 	{
- 		.compatible	= "allwinner,sun6i-a31-mipi-dsi",
-@@ -1232,6 +1236,10 @@ static const struct of_device_id sun6i_d
- 		.compatible	= "allwinner,sun50i-a64-mipi-dsi",
- 		.data		= &sun50i_a64_mipi_dsi_variant,
- 	},
-+	{
-+		.compatible	= "allwinner,sun50i-a100-mipi-dsi",
-+		.data		= &sun50i_a100_mipi_dsi_variant,
-+	},
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
diff --git a/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch b/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch
deleted file mode 100644
index c4ac271b20..0000000000
--- a/target/linux/d1/patches-6.1/0098-riscv-Move-cast-inside-kernel_mapping_-pv-a_to_-vp-a.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From b6af4b7f6f75904509747c08e87d91c1bb607bd4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 22 Sep 2022 00:39:36 -0500
-Subject: [PATCH 098/117] riscv: Move cast inside kernel_mapping_[pv]a_to_[vp]a
-
-Before commit 44c922572952 ("RISC-V: enable XIP"), these macros cast
-their argument to unsigned long. That commit moved the cast after an
-assignment to an unsigned long variable, rendering it ineffectual.
-Move the cast back, so we can remove the cast at each call site.
-
-Series-to: Palmer Dabbelt <palmer@dabbelt.com>
-Series-to: linux-riscv@lists.infradead.org
-
-Series-version: 2
-
-Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/include/asm/page.h | 18 +++++++++---------
- arch/riscv/mm/init.c          | 16 ++++++++--------
- 2 files changed, 17 insertions(+), 17 deletions(-)
-
---- a/arch/riscv/include/asm/page.h
-+++ b/arch/riscv/include/asm/page.h
-@@ -123,20 +123,20 @@ extern phys_addr_t phys_ram_base;
- 	((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE))
- 
- #define linear_mapping_pa_to_va(x)	((void *)((unsigned long)(x) + kernel_map.va_pa_offset))
--#define kernel_mapping_pa_to_va(y)	({						\
--	unsigned long _y = y;								\
--	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?					\
--		(void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) :		\
--		(void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET);	\
-+#define kernel_mapping_pa_to_va(y)	({					\
-+	unsigned long _y = (unsigned long)(y);					\
-+	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?			\
-+		(void *)(_y + kernel_map.va_kernel_xip_pa_offset) :		\
-+		(void *)(_y + kernel_map.va_kernel_pa_offset + XIP_OFFSET);	\
- 	})
- #define __pa_to_va_nodebug(x)		linear_mapping_pa_to_va(x)
- 
- #define linear_mapping_va_to_pa(x)	((unsigned long)(x) - kernel_map.va_pa_offset)
- #define kernel_mapping_va_to_pa(y) ({						\
--	unsigned long _y = y;							\
--	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ?	\
--		((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) :		\
--		((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET);	\
-+	unsigned long _y = (unsigned long)(y);					\
-+	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
-+		(_y - kernel_map.va_kernel_xip_pa_offset) :			\
-+		(_y - kernel_map.va_kernel_pa_offset - XIP_OFFSET);		\
- 	})
- 
- #define __va_to_pa_nodebug(x)	({						\
---- a/arch/riscv/mm/init.c
-+++ b/arch/riscv/mm/init.c
-@@ -903,15 +903,15 @@ static void __init pt_ops_set_early(void
-  */
- static void __init pt_ops_set_fixmap(void)
- {
--	pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap);
--	pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap);
-+	pt_ops.alloc_pte = kernel_mapping_pa_to_va(alloc_pte_fixmap);
-+	pt_ops.get_pte_virt = kernel_mapping_pa_to_va(get_pte_virt_fixmap);
- #ifndef __PAGETABLE_PMD_FOLDED
--	pt_ops.alloc_pmd = kernel_mapping_pa_to_va((uintptr_t)alloc_pmd_fixmap);
--	pt_ops.get_pmd_virt = kernel_mapping_pa_to_va((uintptr_t)get_pmd_virt_fixmap);
--	pt_ops.alloc_pud = kernel_mapping_pa_to_va((uintptr_t)alloc_pud_fixmap);
--	pt_ops.get_pud_virt = kernel_mapping_pa_to_va((uintptr_t)get_pud_virt_fixmap);
--	pt_ops.alloc_p4d = kernel_mapping_pa_to_va((uintptr_t)alloc_p4d_fixmap);
--	pt_ops.get_p4d_virt = kernel_mapping_pa_to_va((uintptr_t)get_p4d_virt_fixmap);
-+	pt_ops.alloc_pmd = kernel_mapping_pa_to_va(alloc_pmd_fixmap);
-+	pt_ops.get_pmd_virt = kernel_mapping_pa_to_va(get_pmd_virt_fixmap);
-+	pt_ops.alloc_pud = kernel_mapping_pa_to_va(alloc_pud_fixmap);
-+	pt_ops.get_pud_virt = kernel_mapping_pa_to_va(get_pud_virt_fixmap);
-+	pt_ops.alloc_p4d = kernel_mapping_pa_to_va(alloc_p4d_fixmap);
-+	pt_ops.get_p4d_virt = kernel_mapping_pa_to_va(get_p4d_virt_fixmap);
- #endif
- }
- 
diff --git a/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch b/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch
deleted file mode 100644
index 056d92af36..0000000000
--- a/target/linux/d1/patches-6.1/0099-dt-bindings-sun6i-a31-mipi-dphy-Add-the-interrupts-p.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 20a204b31291befcd583f97dafc0a827f3bc7f00 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 01:37:16 -0500
-Subject: [PATCH 099/117] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts
- property
-
-The sun6i DPHY can generate several interrupts, mostly for reporting
-error conditions, but also for detecting BTA and UPLS sequences.
-Document this capability in order to accurately describe the hardware.
-
-The DPHY has no interrupt number provided in the vendor documentation
-because its interrupt line is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-@@ -24,6 +24,9 @@ properties:
-   reg:
-     maxItems: 1
- 
-+  interrupts:
-+    maxItems: 1
-+
-   clocks:
-     items:
-       - description: Bus Clock
-@@ -53,6 +56,7 @@ required:
-   - "#phy-cells"
-   - compatible
-   - reg
-+  - interrupts
-   - clocks
-   - clock-names
-   - resets
diff --git a/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch b/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch
deleted file mode 100644
index 36a4627e00..0000000000
--- a/target/linux/d1/patches-6.1/0100-ARM-dts-sun8i-a33-Add-DPHY-interrupt.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 7d47c62b378a4dbbf3e46a80c7b03966f8964da1 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 02:24:14 -0500
-Subject: [PATCH 100/117] ARM: dts: sun8i: a33: Add DPHY interrupt
-
-The DPHY has an interrupt line which is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/sun8i-a33.dtsi
-+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
-@@ -278,6 +278,7 @@
- 		dphy: d-phy@1ca1000 {
- 			compatible = "allwinner,sun6i-a31-mipi-dphy";
- 			reg = <0x01ca1000 0x1000>;
-+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
- 				 <&ccu CLK_DSI_DPHY>;
- 			clock-names = "bus", "mod";
diff --git a/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch b/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch
deleted file mode 100644
index 5734a84a19..0000000000
--- a/target/linux/d1/patches-6.1/0101-arm64-dts-allwinner-a64-Add-DPHY-interrupt.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 11d78fce09e80ec246016c19ecc28a724e1e5530 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 02:25:55 -0500
-Subject: [PATCH 101/117] arm64: dts: allwinner: a64: Add DPHY interrupt
-
-The DPHY has an interrupt line which is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -1199,6 +1199,7 @@
- 			compatible = "allwinner,sun50i-a64-mipi-dphy",
- 				     "allwinner,sun6i-a31-mipi-dphy";
- 			reg = <0x01ca1000 0x1000>;
-+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&ccu CLK_BUS_MIPI_DSI>,
- 				 <&ccu CLK_DSI_DPHY>;
- 			clock-names = "bus", "mod";
diff --git a/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch b/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch
deleted file mode 100644
index 6c93a60296..0000000000
--- a/target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c7fa1be12bf0ef02f5557dd1d1100d25af4e34f5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:00:12 -0500
-Subject: [PATCH 102/117] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
- variant
-
-A100 features an updated DPHY, which moves PLL control inside the DPHY
-register space. (Previously PLL-MIPI was controlled from the CCU. This
-does not affect the "clocks" property because the link between PLL-MIPI
-and the DPHY was never represented in the devicetree.) It also requires
-a modified analog power-on sequence. Finally, the new DPHY adds support
-for operating as an LVDS PHY. D1 uses this same variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-@@ -17,9 +17,13 @@ properties:
-   compatible:
-     oneOf:
-       - const: allwinner,sun6i-a31-mipi-dphy
-+      - const: allwinner,sun50i-a100-mipi-dphy
-       - items:
-           - const: allwinner,sun50i-a64-mipi-dphy
-           - const: allwinner,sun6i-a31-mipi-dphy
-+      - items:
-+          - const: allwinner,sun20i-d1-mipi-dphy
-+          - const: allwinner,sun50i-a100-mipi-dphy
- 
-   reg:
-     maxItems: 1
diff --git a/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch b/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch
deleted file mode 100644
index 6a1f4f9af9..0000000000
--- a/target/linux/d1/patches-6.1/0103-phy-allwinner-phy-sun6i-mipi-dphy-Make-RX-support-op.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 27c0c2cbe7b30b907b031016d2cd15fe9505cb1b Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 12:11:53 -0500
-Subject: [PATCH 103/117] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support
- optional
-
-While all variants of the DPHY likely support RX mode, the new variant
-in the A100 is not used in this direction by the BSP, and it has some
-analog register changes, so its RX power-on sequence is unknown. To be
-safe, limit RX support to variants where the power-on sequence is known.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
- 1 file changed, 23 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
- 	SUN6I_DPHY_DIRECTION_RX,
- };
- 
-+struct sun6i_dphy_variant {
-+	bool	supports_rx;
-+};
-+
- struct sun6i_dphy {
- 	struct clk				*bus_clk;
- 	struct clk				*mod_clk;
-@@ -123,6 +127,7 @@ struct sun6i_dphy {
- 	struct phy				*phy;
- 	struct phy_configure_opts_mipi_dphy	config;
- 
-+	const struct sun6i_dphy_variant		*variant;
- 	enum sun6i_dphy_direction		direction;
- };
- 
-@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platf
- 	if (!dphy)
- 		return -ENOMEM;
- 
-+	dphy->variant = device_get_match_data(&pdev->dev);
-+	if (!dphy->variant)
-+		return -EINVAL;
-+
- 	regs = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(regs)) {
- 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
-@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platf
- 	ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
- 				      &direction);
- 
--	if (!ret && !strncmp(direction, "rx", 2))
-+	if (!ret && !strncmp(direction, "rx", 2)) {
-+		if (!dphy->variant->supports_rx) {
-+			dev_err(&pdev->dev, "RX not supported on this variant\n");
-+			return -EOPNOTSUPP;
-+		}
- 		dphy->direction = SUN6I_DPHY_DIRECTION_RX;
-+	}
- 
- 	phy_set_drvdata(dphy->phy, dphy);
- 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
-@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platf
- 	return PTR_ERR_OR_ZERO(phy_provider);
- }
- 
-+static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
-+	.supports_rx	= true,
-+};
-+
- static const struct of_device_id sun6i_dphy_of_table[] = {
--	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
-+	{
-+		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
-+		.data		= &sun6i_a31_mipi_dphy_variant,
-+	},
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
diff --git a/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch b/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch
deleted file mode 100644
index e8c6ef8c5a..0000000000
--- a/target/linux/d1/patches-6.1/0104-phy-allwinner-phy-sun6i-mipi-dphy-Set-enable-bit-las.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 16993169c82c2c57e1df1e7f4598a7c2aa565fe2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:12:02 -0500
-Subject: [PATCH 104/117] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit
- last
-
-The A100 variant of the DPHY requires configuring the analog registers
-before setting the global enable bit. Since this order also works on the
-other variants, always use it, to minimize the differences between them.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct
- 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
- 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
- 
--	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
--		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
--		     SUN6I_DPHY_GCTL_EN);
--
- 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
- 		     SUN6I_DPHY_ANA0_REG_PWS |
- 		     SUN6I_DPHY_ANA0_REG_DMPC |
-@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct
- 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
- 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
- 
-+	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-+		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-+		     SUN6I_DPHY_GCTL_EN);
-+
- 	return 0;
- }
- 
diff --git a/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch b/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch
deleted file mode 100644
index 6df659e80d..0000000000
--- a/target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From b953c09bde508c2edd8acd95abba8542b6cebff6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:44:09 -0500
-Subject: [PATCH 105/117] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant
- power-on hook
-
-The A100 variant uses the same values for the timing registers, and it
-uses the same final power-on sequence, but it needs a different analog
-register configuration in the middle. Support this by moving the
-variant-specific parts to a hook provided by the variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
- 1 file changed, 35 insertions(+), 24 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
- 	SUN6I_DPHY_DIRECTION_RX,
- };
- 
-+struct sun6i_dphy;
-+
- struct sun6i_dphy_variant {
-+	void	(*tx_power_on)(struct sun6i_dphy *dphy);
- 	bool	supports_rx;
- };
- 
-@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct p
- 	return 0;
- }
- 
--static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
- {
- 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
- 
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
--		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
--
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
--		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
--		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
--		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
--
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
--		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
--		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
--		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
--		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
--
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
--		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
--
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
--
--	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
--		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
--		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
--
- 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
- 		     SUN6I_DPHY_ANA0_REG_PWS |
- 		     SUN6I_DPHY_ANA0_REG_DMPC |
-@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct
- 		     SUN6I_DPHY_ANA3_EN_LDOC |
- 		     SUN6I_DPHY_ANA3_EN_LDOD);
- 	udelay(1);
-+}
-+
-+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+{
-+	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-+		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-+		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-+		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-+		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-+		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-+		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-+		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-+		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-+		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-+
-+	dphy->variant->tx_power_on(dphy);
- 
- 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
- 			   SUN6I_DPHY_ANA3_EN_VTTC |
-@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platf
- }
- 
- static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
-+	.tx_power_on	= sun6i_a31_mipi_dphy_tx_power_on,
- 	.supports_rx	= true,
- };
- 
diff --git a/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch b/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch
deleted file mode 100644
index 751d382177..0000000000
--- a/target/linux/d1/patches-6.1/0106-phy-allwinner-phy-sun6i-mipi-dphy-Add-the-A100-DPHY-.patch
+++ /dev/null
@@ -1,229 +0,0 @@
-From 474b608dee5e6285dd1981b00ab568a2f7f15fd0 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 10 Aug 2022 23:02:06 -0500
-Subject: [PATCH 106/117] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100
- DPHY variant
-
-A100 features an updated DPHY, which moves PLL control inside the DPHY
-register space (previously the PLL was controlled from the CCU). It also
-requires a modified analog power-on sequence. This "combo PHY" can also
-be used as an LVDS PHY, but that is not yet supported by the driver.
-
-Cover-letter:
-phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY
-This series adds support for the updated DPHY found in a couple of
-recent Allwinner SoCs. The first three patches fix an omission in the
-existing binding. The remaining patches add the new hardware variant.
-END
-
-Series-to: Kishon Vijay Abraham I <kishon@ti.com>
-Series-to: Vinod Koul <vkoul@kernel.org>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Maxime Ripard <mripard@kernel.org>
-Series-cc: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
- 1 file changed, 142 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -70,11 +70,19 @@
- 
- #define SUN6I_DPHY_ANA0_REG		0x4c
- #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
-+#define SUN6I_DPHY_ANA0_REG_PWEND		BIT(30)
-+#define SUN6I_DPHY_ANA0_REG_PWENC		BIT(29)
- #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
- #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
-+#define SUN6I_DPHY_ANA0_REG_SRXDT(n)		(((n) & 0xf) << 20)
-+#define SUN6I_DPHY_ANA0_REG_SRXCK(n)		(((n) & 0xf) << 16)
-+#define SUN6I_DPHY_ANA0_REG_SDIV2		BIT(15)
- #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
- #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
-+#define SUN6I_DPHY_ANA0_REG_PLR(n)		(((n) & 0xf) << 4)
- #define SUN6I_DPHY_ANA0_REG_SFB(n)		(((n) & 3) << 2)
-+#define SUN6I_DPHY_ANA0_REG_RSD			BIT(1)
-+#define SUN6I_DPHY_ANA0_REG_SELSCK		BIT(0)
- 
- #define SUN6I_DPHY_ANA1_REG		0x50
- #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
-@@ -97,8 +105,13 @@
- #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
- 
- #define SUN6I_DPHY_ANA4_REG		0x5c
-+#define SUN6I_DPHY_ANA4_REG_EN_MIPI		BIT(31)
-+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST		BIT(30)
-+#define SUN6I_DPHY_ANA4_REG_COMTEST(n)		(((n) & 3) << 28)
-+#define SUN6I_DPHY_ANA4_REG_IB(n)		(((n) & 3) << 25)
- #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
- #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
-+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n)		(((n) & 0x7) << 17)
- #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
- #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
- #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
-@@ -109,6 +122,56 @@
- 
- #define SUN6I_DPHY_DBG5_REG		0xf4
- 
-+#define SUN50I_DPHY_TX_SLEW_REG0	0xf8
-+#define SUN50I_DPHY_TX_SLEW_REG1	0xfc
-+#define SUN50I_DPHY_TX_SLEW_REG2	0x100
-+
-+#define SUN50I_DPHY_PLL_REG0		0x104
-+#define SUN50I_DPHY_PLL_REG0_CP36_EN		BIT(23)
-+#define SUN50I_DPHY_PLL_REG0_LDO_EN		BIT(22)
-+#define SUN50I_DPHY_PLL_REG0_EN_LVS		BIT(21)
-+#define SUN50I_DPHY_PLL_REG0_PLL_EN		BIT(20)
-+#define SUN50I_DPHY_PLL_REG0_P(n)		(((n) & 0xf) << 16)
-+#define SUN50I_DPHY_PLL_REG0_N(n)		(((n) & 0xff) << 8)
-+#define SUN50I_DPHY_PLL_REG0_NDET		BIT(7)
-+#define SUN50I_DPHY_PLL_REG0_TDIV		BIT(6)
-+#define SUN50I_DPHY_PLL_REG0_M0(n)		(((n) & 3) << 4)
-+#define SUN50I_DPHY_PLL_REG0_M1(n)		((n) & 0xf)
-+
-+#define SUN50I_DPHY_PLL_REG1		0x108
-+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n)	(((n) & 3) << 14)
-+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL		BIT(13)
-+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN		BIT(12)
-+#define SUN50I_DPHY_PLL_REG1_VSETA(n)		(((n) & 0x7) << 9)
-+#define SUN50I_DPHY_PLL_REG1_VSETD(n)		(((n) & 0x7) << 6)
-+#define SUN50I_DPHY_PLL_REG1_LPF_SW		BIT(5)
-+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n)		(((n) & 3) << 3)
-+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n)	(((n) & 3) << 1)
-+#define SUN50I_DPHY_PLL_REG1_TEST_EN		BIT(0)
-+
-+#define SUN50I_DPHY_PLL_REG2		0x10c
-+#define SUN50I_DPHY_PLL_REG2_SDM_EN		BIT(31)
-+#define SUN50I_DPHY_PLL_REG2_FF_EN		BIT(30)
-+#define SUN50I_DPHY_PLL_REG2_SS_EN		BIT(29)
-+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n)		(((n) & 0x1ff) << 20)
-+#define SUN50I_DPHY_PLL_REG2_SS_INT(n)		(((n) & 0xff) << 12)
-+#define SUN50I_DPHY_PLL_REG2_FRAC(n)		((n) & 0xfff)
-+
-+#define SUN50I_COMBO_PHY_REG0		0x110
-+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO	BIT(5)
-+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8	BIT(4)
-+#define SUN50I_COMBO_PHY_REG0_EN_MIPI		BIT(3)
-+#define SUN50I_COMBO_PHY_REG0_EN_LVDS		BIT(2)
-+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO	BIT(1)
-+#define SUN50I_COMBO_PHY_REG0_EN_CP		BIT(0)
-+
-+#define SUN50I_COMBO_PHY_REG1		0x114
-+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n)	(((n) & 0x7) << 4)
-+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n)	((n) & 0x7)
-+
-+#define SUN50I_COMBO_PHY_REG2		0x118
-+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n)	((n) & 0xff)
-+
- enum sun6i_dphy_direction {
- 	SUN6I_DPHY_DIRECTION_TX,
- 	SUN6I_DPHY_DIRECTION_RX,
-@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power
- 	udelay(1);
- }
- 
-+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+{
-+	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
-+	unsigned int div, n;
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
-+		     SUN6I_DPHY_ANA4_REG_IB(2) |
-+		     SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
-+		     SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
-+		     SUN6I_DPHY_ANA4_REG_CKDV(3) |
-+		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
-+		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
-+		     SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
-+		     SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
-+		     SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
-+		     SUN6I_DPHY_ANA4_REG_TXDNSC(3));
-+
-+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
-+			   SUN6I_DPHY_ANA2_EN_CK_CPU,
-+			   SUN6I_DPHY_ANA2_EN_CK_CPU);
-+
-+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
-+			   SUN6I_DPHY_ANA2_REG_ENIB,
-+			   SUN6I_DPHY_ANA2_REG_ENIB);
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
-+		     SUN6I_DPHY_ANA3_EN_LDOR |
-+		     SUN6I_DPHY_ANA3_EN_LDOC |
-+		     SUN6I_DPHY_ANA3_EN_LDOD);
-+
-+	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
-+		     SUN6I_DPHY_ANA0_REG_PLR(4) |
-+		     SUN6I_DPHY_ANA0_REG_SFB(1));
-+
-+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
-+		     SUN50I_COMBO_PHY_REG0_EN_CP);
-+
-+	/* Choose a divider to limit the VCO frequency to around 2 GHz. */
-+	div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
-+	n = mipi_symbol_rate * div / 24000000;
-+
-+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
-+		     SUN50I_DPHY_PLL_REG0_CP36_EN |
-+		     SUN50I_DPHY_PLL_REG0_LDO_EN |
-+		     SUN50I_DPHY_PLL_REG0_EN_LVS |
-+		     SUN50I_DPHY_PLL_REG0_PLL_EN |
-+		     SUN50I_DPHY_PLL_REG0_NDET |
-+		     SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
-+		     SUN50I_DPHY_PLL_REG0_N(n) |
-+		     SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
-+		     SUN50I_DPHY_PLL_REG0_M1(2));
-+
-+	/* Disable sigma-delta modulation. */
-+	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
-+
-+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
-+			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
-+			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
-+
-+	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
-+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
-+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
-+			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
-+			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
-+
-+	regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
-+		     SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
-+	udelay(1);
-+}
-+
- static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
- {
- 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
-@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_
- 	.reg_bits	= 32,
- 	.val_bits	= 32,
- 	.reg_stride	= 4,
--	.max_register	= SUN6I_DPHY_DBG5_REG,
-+	.max_register	= SUN50I_COMBO_PHY_REG2,
- 	.name		= "mipi-dphy",
- };
- 
-@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant s
- 	.supports_rx	= true,
- };
- 
-+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
-+	.tx_power_on	= sun50i_a100_mipi_dphy_tx_power_on,
-+};
-+
- static const struct of_device_id sun6i_dphy_of_table[] = {
- 	{
- 		.compatible	= "allwinner,sun6i-a31-mipi-dphy",
- 		.data		= &sun6i_a31_mipi_dphy_variant,
- 	},
-+	{
-+		.compatible	= "allwinner,sun50i-a100-mipi-dphy",
-+		.data		= &sun50i_a100_mipi_dphy_variant,
-+	},
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
diff --git a/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch b/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch
deleted file mode 100644
index 5dd0273b7e..0000000000
--- a/target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch
+++ /dev/null
@@ -1,518 +0,0 @@
-From 5bf84a1a0a282a18bf9dd2d752537525aefc2e05 Mon Sep 17 00:00:00 2001
-From: Max Fierke <max@maxfierke.com>
-Date: Wed, 1 Jun 2022 00:17:48 -0500
-Subject: [PATCH 107/117] drm: panel: Add driver for Clockwork cwd686 panel
-
-The Clockwork DevTerm (all models) uses a 6.86" IPS display
-of unknown provenance, which uses the Chipone ICNL9707 IC driver.
-
-The display panel I have has two model numbers: TXW686001 and WTL068601G,
-but cannot find any manufacturer associated with either, so opting for the
-Clockwork model number.
-
-This driver is based on the GPL-licensed driver released by Clockwork,
-authored by Pinfan Zhu, with some additional cleanup, rotation support,
-and display sleep re-enabling done by me.
-
-Original driver here for reference: https://github.com/clockworkpi/DevTerm/blob/main/Code/patch/armbian_build_a06/patch/kernel-004-panel.patch
-Display IC datasheet provided here: https://github.com/clockworkpi/DevTerm/blob/main/Schematics/ICNL9707_Datasheet.pdf
-
-Signed-off-by: Max Fierke <max@maxfierke.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/Kconfig                 |  12 +
- drivers/gpu/drm/panel/Makefile                |   1 +
- .../gpu/drm/panel/panel-clockwork-cwd686.c    | 456 ++++++++++++++++++
- 3 files changed, 469 insertions(+)
- create mode 100644 drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-
---- a/drivers/gpu/drm/panel/Kconfig
-+++ b/drivers/gpu/drm/panel/Kconfig
-@@ -68,6 +68,18 @@ config DRM_PANEL_BOE_TV101WUM_NL6
- 	  Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
- 	  45NA WUXGA PANEL DSI Video Mode panel
- 
-+config DRM_PANEL_CLOCKWORK_CWD686
-+	tristate "Clockwork CWD686 panel"
-+	depends on OF
-+	depends on DRM_MIPI_DSI
-+	depends on BACKLIGHT_CLASS_DEVICE
-+	help
-+	  Say Y here if you want to enable support for the Clockwork CWD686
-+	  ICNL9707-based panel, e.g. as used within the Clockwork DevTerm.
-+	  The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
-+
-+	  To compile this driver as a module, choose M here.
-+
- config DRM_PANEL_DSI_CM
- 	tristate "Generic DSI command mode panels"
- 	depends on OF
---- a/drivers/gpu/drm/panel/Makefile
-+++ b/drivers/gpu/drm/panel/Makefile
-@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_N
- obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o
- obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
- obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
-+obj-$(CONFIG_DRM_PANEL_CLOCKWORK_CWD686) += panel-clockwork-cwd686.o
- obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
- obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
- obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
---- /dev/null
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -0,0 +1,456 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (c) 2021 Clockwork Tech LLC
-+ * Copyright (c) 2021-2022 Max Fierke <max@maxfierke.com>
-+ *
-+ * Based on Pinfan Zhu's work on panel-cwd686.c for ClockworkPi's 5.10 BSP
-+ */
-+
-+#include <drm/drm_modes.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+#include <linux/backlight.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/delay.h>
-+#include <linux/of_device.h>
-+#include <linux/module.h>
-+#include <video/mipi_display.h>
-+
-+struct cwd686 {
-+	struct device *dev;
-+	struct drm_panel panel;
-+	struct regulator *supply;
-+	struct gpio_desc *enable_gpio;
-+	struct gpio_desc *reset_gpio;
-+	struct backlight_device *backlight;
-+	enum drm_panel_orientation orientation;
-+	bool prepared;
-+	bool enabled;
-+};
-+
-+static const struct drm_display_mode default_mode = {
-+	.clock = 54465,
-+	.hdisplay = 480,
-+	.hsync_start = 480 + 150,
-+	.hsync_end = 480 + 150 + 24,
-+	.htotal = 480 + 150 + 24 + 40,
-+	.vdisplay = 1280,
-+	.vsync_start = 1280 + 12,
-+	.vsync_end = 1280 + 12 + 6,
-+	.vtotal = 1280 + 12 + 6 + 10,
-+};
-+
-+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct cwd686, panel);
-+}
-+
-+#define ICNL9707_DCS(seq...)                              \
-+({                                                              \
-+	static const u8 d[] = { seq };                          \
-+	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
-+})
-+
-+#define ICNL9707_CMD_CGOUTL 0xB3
-+#define ICNL9707_CMD_CGOUTR 0xB4
-+#define ICNL9707_P_CGOUT_VGL 0x00
-+#define ICNL9707_P_CGOUT_VGH 0x01
-+#define ICNL9707_P_CGOUT_HZ 0x02
-+#define ICNL9707_P_CGOUT_GND 0x03
-+#define ICNL9707_P_CGOUT_GSP1 0x04
-+#define ICNL9707_P_CGOUT_GSP2 0x05
-+#define ICNL9707_P_CGOUT_GSP3 0x06
-+#define ICNL9707_P_CGOUT_GSP4 0x07
-+#define ICNL9707_P_CGOUT_GSP5 0x08
-+#define ICNL9707_P_CGOUT_GSP6 0x09
-+#define ICNL9707_P_CGOUT_GSP7 0x0A
-+#define ICNL9707_P_CGOUT_GSP8 0x0B
-+#define ICNL9707_P_CGOUT_GCK1 0x0C
-+#define ICNL9707_P_CGOUT_GCK2 0x0D
-+#define ICNL9707_P_CGOUT_GCK3 0x0E
-+#define ICNL9707_P_CGOUT_GCK4 0x0F
-+#define ICNL9707_P_CGOUT_GCK5 0x10
-+#define ICNL9707_P_CGOUT_GCK6 0x11
-+#define ICNL9707_P_CGOUT_GCK7 0x12
-+#define ICNL9707_P_CGOUT_GCK8 0x13
-+#define ICNL9707_P_CGOUT_GCK9 0x14
-+#define ICNL9707_P_CGOUT_GCK10 0x15
-+#define ICNL9707_P_CGOUT_GCK11 0x16
-+#define ICNL9707_P_CGOUT_GCK12 0x17
-+#define ICNL9707_P_CGOUT_GCK13 0x18
-+#define ICNL9707_P_CGOUT_GCK14 0x19
-+#define ICNL9707_P_CGOUT_GCK15 0x1A
-+#define ICNL9707_P_CGOUT_GCK16 0x1B
-+#define ICNL9707_P_CGOUT_DIR 0x1C
-+#define ICNL9707_P_CGOUT_DIRB 0x1D
-+#define ICNL9707_P_CGOUT_ECLK_AC 0x1E
-+#define ICNL9707_P_CGOUT_ECLK_ACB 0x1F
-+#define ICNL9707_P_CGOUT_ECLK_AC2 0x20
-+#define ICNL9707_P_CGOUT_ECLK_AC2B 0x21
-+#define ICNL9707_P_CGOUT_GCH 0x22
-+#define ICNL9707_P_CGOUT_GCL 0x23
-+#define ICNL9707_P_CGOUT_XDON 0x24
-+#define ICNL9707_P_CGOUT_XDONB 0x25
-+
-+#define ICNL9707_MADCTL_ML  0x10
-+#define ICNL9707_MADCTL_RGB 0x00
-+#define ICNL9707_MADCTL_BGR 0x08
-+#define ICNL9707_MADCTL_MH  0x04
-+
-+#define ICNL9707_CMD_PWRCON_VCOM 0xB6
-+#define ICNL9707_P_PWRCON_VCOM_0495V 0x0D
-+
-+#define ICNL9707_CMD_PWRCON_SEQ 0xB7
-+#define ICNL9707_CMD_PWRCON_CLK 0xB8
-+#define ICNL9707_CMD_PWRCON_BTA 0xB9
-+#define ICNL9707_CMD_PWRCON_MODE 0xBA
-+#define ICNL9707_CMD_PWRCON_REG 0xBD
-+
-+#define ICNL9707_CMD_TCON 0xC1
-+#define ICNL9707_CMD_TCON2 0xC2
-+#define ICNL9707_CMD_TCON3 0xC3
-+#define ICNL9707_CMD_SRC_TIM 0xC6
-+#define ICNL9707_CMD_SRCCON 0xC7
-+#define ICNL9707_CMD_SET_GAMMA 0xC8
-+
-+#define ICNL9707_CMD_ETC 0xD0
-+
-+#define ICNL9707_CMD_PASSWORD1 0xF0
-+#define ICNL9707_P_PASSWORD1_DEFAULT 0xA5
-+#define ICNL9707_P_PASSWORD1_ENABLE_LVL2 0x5A
-+
-+#define ICNL9707_CMD_PASSWORD2 0xF1
-+#define ICNL9707_P_PASSWORD2_DEFAULT 0x5A
-+#define ICNL9707_P_PASSWORD2_ENABLE_LVL2 0xA5
-+
-+static int cwd686_init_sequence(struct cwd686 *ctx)
-+{
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int err;
-+
-+	/* Enable access to Level 2 registers */
-+	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-+		     ICNL9707_P_PASSWORD1_ENABLE_LVL2,
-+		     ICNL9707_P_PASSWORD1_ENABLE_LVL2);
-+	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-+		     ICNL9707_P_PASSWORD2_ENABLE_LVL2,
-+		     ICNL9707_P_PASSWORD2_ENABLE_LVL2);
-+
-+	/* Set PWRCON_VCOM (-0.495V, -0.495V) */
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
-+		     ICNL9707_P_PWRCON_VCOM_0495V,
-+		     ICNL9707_P_PWRCON_VCOM_0495V);
-+
-+	/* Map ASG output signals */
-+	ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
-+		     ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
-+		     ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
-+		     ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
-+	ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
-+		     ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
-+		     ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
-+		     ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+		     ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
-+
-+	/* Undocumented commands provided by the vendor */
-+	ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
-+	ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
-+	ICNL9707_DCS(0xB2, 0x73);
-+
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
-+		     0x4E, 0x0E, 0x50, 0x50, 0x26,
-+		     0x1D, 0x00, 0x14, 0x42, 0x03);
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
-+		     0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
-+		     0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
-+		     0x00, 0x00, 0x02, 0xFF, 0x3C);
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
-+
-+	/* Disable abnormal power-off flag */
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
-+
-+	ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
-+
-+	/* Set VBP, VFP, VSW, HBP, HFP, HSW */
-+	ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
-+
-+	/* Set resolution */
-+	ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
-+
-+	/* Set frame blanking */
-+	ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
-+
-+	ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
-+
-+	/* Another undocumented command */
-+	ICNL9707_DCS(0xC5, 0x00);
-+
-+	ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
-+
-+	/* Another set of undocumented commands */
-+	ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
-+	ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
-+
-+	/* Set Gamma to 2.2 */
-+	ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
-+		     0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
-+		     0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
-+		     0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
-+		     0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
-+		     0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
-+		     0x3B, 0x2A, 0x06);
-+
-+	ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
-+
-+	/* Another undocumented command */
-+	ICNL9707_DCS(0xF4, 0x08, 0x77);
-+
-+	ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
-+		     ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
-+
-+	/* Enable tearing mode at VBLANK */
-+	err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
-+		return err;
-+	}
-+
-+	/* Disable access to Level 2 registers */
-+	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-+		     ICNL9707_P_PASSWORD2_DEFAULT,
-+		     ICNL9707_P_PASSWORD2_DEFAULT);
-+	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-+		     ICNL9707_P_PASSWORD1_DEFAULT,
-+		     ICNL9707_P_PASSWORD1_DEFAULT);
-+
-+	return 0;
-+}
-+
-+static int cwd686_disable(struct drm_panel *panel)
-+{
-+	struct cwd686 *ctx = panel_to_cwd686(panel);
-+
-+	if (!ctx->enabled)
-+		return 0;
-+
-+	backlight_disable(ctx->backlight);
-+
-+	ctx->enabled = false;
-+
-+	return 0;
-+}
-+
-+static int cwd686_unprepare(struct drm_panel *panel)
-+{
-+	struct cwd686 *ctx = panel_to_cwd686(panel);
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int err;
-+
-+	if (!ctx->prepared)
-+		return 0;
-+
-+	err = mipi_dsi_dcs_set_display_off(dsi);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to turn display off (%d)\n", err);
-+		return err;
-+	}
-+
-+	err = mipi_dsi_dcs_enter_sleep_mode(dsi);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", err);
-+		return err;
-+	}
-+
-+	msleep(120);
-+
-+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+
-+	ctx->prepared = false;
-+
-+	return 0;
-+}
-+
-+static int cwd686_prepare(struct drm_panel *panel)
-+{
-+	struct cwd686 *ctx = panel_to_cwd686(panel);
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int err;
-+
-+	if (ctx->prepared)
-+		return 0;
-+
-+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+	/* T2 */
-+	msleep(10);
-+
-+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
-+	/* T3 */
-+	msleep(20);
-+
-+	/* Exit sleep mode and power on */
-+
-+	err = cwd686_init_sequence(ctx);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to initialize display (%d)\n", err);
-+		return err;
-+	}
-+
-+	err = mipi_dsi_dcs_exit_sleep_mode(dsi);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
-+		return err;
-+	}
-+	/* T6 */
-+	msleep(120);
-+
-+	err = mipi_dsi_dcs_set_display_on(dsi);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
-+		return err;
-+	}
-+	msleep(20);
-+
-+	ctx->prepared = true;
-+
-+	return 0;
-+}
-+
-+static int cwd686_enable(struct drm_panel *panel)
-+{
-+	struct cwd686 *ctx = panel_to_cwd686(panel);
-+
-+	if (ctx->enabled)
-+		return 0;
-+
-+	backlight_enable(ctx->backlight);
-+
-+	ctx->enabled = true;
-+
-+	return 0;
-+}
-+
-+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
-+{
-+	struct cwd686 *ctx = panel_to_cwd686(panel);
-+	struct drm_display_mode *mode;
-+
-+	mode = drm_mode_duplicate(connector->dev, &default_mode);
-+	if (!mode) {
-+		dev_err(panel->dev, "bad mode or failed to add mode\n");
-+		return -EINVAL;
-+	}
-+	drm_mode_set_name(mode);
-+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+
-+	connector->display_info.width_mm = mode->width_mm;
-+	connector->display_info.height_mm = mode->height_mm;
-+
-+	/* set up connector's "panel orientation" property */
-+	drm_connector_set_panel_orientation(connector, ctx->orientation);
-+
-+	drm_mode_probed_add(connector, mode);
-+
-+	return 1; /* Number of modes */
-+}
-+
-+static const struct drm_panel_funcs cwd686_drm_funcs = {
-+	.disable = cwd686_disable,
-+	.unprepare = cwd686_unprepare,
-+	.prepare = cwd686_prepare,
-+	.enable = cwd686_enable,
-+	.get_modes = cwd686_get_modes,
-+};
-+
-+static int cwd686_probe(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct cwd686 *ctx;
-+	int err;
-+
-+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	mipi_dsi_set_drvdata(dsi, ctx);
-+	ctx->dev = dev;
-+
-+	dsi->lanes = 4;
-+	dsi->format = MIPI_DSI_FMT_RGB888;
-+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
-+			  MIPI_DSI_MODE_VIDEO_BURST |
-+			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
-+
-+	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
-+	if (IS_ERR(ctx->reset_gpio)) {
-+		err = PTR_ERR(ctx->reset_gpio);
-+		if (err != -EPROBE_DEFER)
-+			dev_err(dev, "failed to request GPIO (%d)\n", err);
-+		return err;
-+	}
-+
-+	ctx->backlight = devm_of_find_backlight(dev);
-+	if (IS_ERR(ctx->backlight))
-+		return PTR_ERR(ctx->backlight);
-+
-+	err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
-+	if (err) {
-+		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
-+		return err;
-+	}
-+
-+	drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
-+
-+	drm_panel_add(&ctx->panel);
-+
-+	err = mipi_dsi_attach(dsi);
-+	if (err < 0) {
-+		dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
-+		drm_panel_remove(&ctx->panel);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static void cwd686_remove(struct mipi_dsi_device *dsi)
-+{
-+	struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
-+
-+	mipi_dsi_detach(dsi);
-+	drm_panel_remove(&ctx->panel);
-+}
-+
-+static const struct of_device_id cwd686_of_match[] = {
-+	{ .compatible = "clockwork,cwd686" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, cwd686_of_match);
-+
-+static struct mipi_dsi_driver cwd686_driver = {
-+	.probe = cwd686_probe,
-+	.remove = cwd686_remove,
-+	.driver = {
-+		.name = "panel-clockwork-cwd686",
-+		.of_match_table = cwd686_of_match,
-+	},
-+};
-+module_mipi_dsi_driver(cwd686_driver);
-+
-+MODULE_AUTHOR("Pinfan Zhu <zhu@clockworkpi.com>");
-+MODULE_AUTHOR("Max Fierke <max@maxfierke.com>");
-+MODULE_DESCRIPTION("ClockworkPi CWD686 panel driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch b/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch
deleted file mode 100644
index 60b21168b5..0000000000
--- a/target/linux/d1/patches-6.1/0108-drm-panel-cwd686-Add-regulators.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 979271f803c1578087a965a2a4b845c87e7d922f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:14:21 -0500
-Subject: [PATCH 108/117] drm: panel: cwd686: Add regulators
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c    | 26 ++++++++++++++++++-
- 1 file changed, 25 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -20,7 +20,8 @@
- struct cwd686 {
- 	struct device *dev;
- 	struct drm_panel panel;
--	struct regulator *supply;
-+	struct regulator *iovcc;
-+	struct regulator *vci;
- 	struct gpio_desc *enable_gpio;
- 	struct gpio_desc *reset_gpio;
- 	struct backlight_device *backlight;
-@@ -279,6 +280,9 @@ static int cwd686_unprepare(struct drm_p
- 
- 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- 
-+	regulator_disable(ctx->vci);
-+	regulator_disable(ctx->iovcc);
-+
- 	ctx->prepared = false;
- 
- 	return 0;
-@@ -293,6 +297,18 @@ static int cwd686_prepare(struct drm_pan
- 	if (ctx->prepared)
- 		return 0;
- 
-+	err = regulator_enable(ctx->iovcc);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
-+		return err;
-+	}
-+
-+	err = regulator_enable(ctx->vci);
-+	if (err) {
-+		dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
-+		return err;
-+	}
-+
- 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- 	/* T2 */
- 	msleep(10);
-@@ -402,6 +418,14 @@ static int cwd686_probe(struct mipi_dsi_
- 		return err;
- 	}
- 
-+	ctx->iovcc = devm_regulator_get(dev, "iovcc");
-+	if (IS_ERR(ctx->iovcc))
-+		return PTR_ERR(ctx->iovcc);
-+
-+	ctx->vci = devm_regulator_get(dev, "vci");
-+	if (IS_ERR(ctx->vci))
-+		return PTR_ERR(ctx->vci);
-+
- 	ctx->backlight = devm_of_find_backlight(dev);
- 	if (IS_ERR(ctx->backlight))
- 		return PTR_ERR(ctx->backlight);
diff --git a/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch b/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch
deleted file mode 100644
index 786273bcfd..0000000000
--- a/target/linux/d1/patches-6.1/0109-drm-panel-cwd686-Make-reset-gpio-mandatory.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 6112585994a6bdbd882709e7187c8c9289211b3b Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:16:03 -0500
-Subject: [PATCH 109/117] drm: panel: cwd686: Make reset gpio mandatory
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -410,7 +410,7 @@ static int cwd686_probe(struct mipi_dsi_
- 			  MIPI_DSI_MODE_VIDEO_BURST |
- 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
- 
--	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
-+	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
- 	if (IS_ERR(ctx->reset_gpio)) {
- 		err = PTR_ERR(ctx->reset_gpio);
- 		if (err != -EPROBE_DEFER)
diff --git a/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch b/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch
deleted file mode 100644
index 6551348a4f..0000000000
--- a/target/linux/d1/patches-6.1/0110-drm-panel-cwd686-Increase-post-reset-delay.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 8d70f9f4a66522c2720de986623d1130337ff670 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:16:18 -0500
-Subject: [PATCH 110/117] drm: panel: cwd686: Increase post-reset delay
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -315,7 +315,7 @@ static int cwd686_prepare(struct drm_pan
- 
- 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- 	/* T3 */
--	msleep(20);
-+	msleep(120);
- 
- 	/* Exit sleep mode and power on */
- 
diff --git a/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch b/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch
deleted file mode 100644
index df68d18557..0000000000
--- a/target/linux/d1/patches-6.1/0111-drm-panel-cwd686-Use-vendor-panel-init-sequence.patch
+++ /dev/null
@@ -1,171 +0,0 @@
-From 8fc2a02d1d2e98a01a2dad3bf3da8e33366725eb Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:17:35 -0500
-Subject: [PATCH 111/117] drm: panel: cwd686: Use vendor panel init sequence
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c    | 142 ++++--------------
- 1 file changed, 32 insertions(+), 110 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -47,10 +47,12 @@ static inline struct cwd686 *panel_to_cw
- 	return container_of(panel, struct cwd686, panel);
- }
- 
--#define ICNL9707_DCS(seq...)                              \
-+#define dcs_write_seq(seq...)                              \
- ({                                                              \
- 	static const u8 d[] = { seq };                          \
--	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
-+	ssize_t r = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
-+	if (r < 0) \
-+		return r; \
- })
- 
- #define ICNL9707_CMD_CGOUTL 0xB3
-@@ -128,115 +130,35 @@ static inline struct cwd686 *panel_to_cw
- static int cwd686_init_sequence(struct cwd686 *ctx)
- {
- 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
--	int err;
- 
--	/* Enable access to Level 2 registers */
--	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
--		     ICNL9707_P_PASSWORD1_ENABLE_LVL2,
--		     ICNL9707_P_PASSWORD1_ENABLE_LVL2);
--	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
--		     ICNL9707_P_PASSWORD2_ENABLE_LVL2,
--		     ICNL9707_P_PASSWORD2_ENABLE_LVL2);
--
--	/* Set PWRCON_VCOM (-0.495V, -0.495V) */
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
--		     ICNL9707_P_PWRCON_VCOM_0495V,
--		     ICNL9707_P_PWRCON_VCOM_0495V);
--
--	/* Map ASG output signals */
--	ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
--		     ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
--		     ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
--		     ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
--	ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
--		     ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
--		     ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
--		     ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
--		     ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
--
--	/* Undocumented commands provided by the vendor */
--	ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
--	ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
--	ICNL9707_DCS(0xB2, 0x73);
--
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
--		     0x4E, 0x0E, 0x50, 0x50, 0x26,
--		     0x1D, 0x00, 0x14, 0x42, 0x03);
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
--		     0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
--		     0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
--		     0x00, 0x00, 0x02, 0xFF, 0x3C);
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
--
--	/* Disable abnormal power-off flag */
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
--
--	ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
--
--	/* Set VBP, VFP, VSW, HBP, HFP, HSW */
--	ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
--
--	/* Set resolution */
--	ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
--
--	/* Set frame blanking */
--	ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
--
--	ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
--
--	/* Another undocumented command */
--	ICNL9707_DCS(0xC5, 0x00);
--
--	ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
--
--	/* Another set of undocumented commands */
--	ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
--	ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
--
--	/* Set Gamma to 2.2 */
--	ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
--		     0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
--		     0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
--		     0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
--		     0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
--		     0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
--		     0x3B, 0x2A, 0x06);
--
--	ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
--
--	/* Another undocumented command */
--	ICNL9707_DCS(0xF4, 0x08, 0x77);
--
--	ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
--		     ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
--
--	/* Enable tearing mode at VBLANK */
--	err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
--	if (err) {
--		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
--		return err;
--	}
--
--	/* Disable access to Level 2 registers */
--	ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
--		     ICNL9707_P_PASSWORD2_DEFAULT,
--		     ICNL9707_P_PASSWORD2_DEFAULT);
--	ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
--		     ICNL9707_P_PASSWORD1_DEFAULT,
--		     ICNL9707_P_PASSWORD1_DEFAULT);
-+	dcs_write_seq(0xF0,0x5A,0x5A);
-+	dcs_write_seq(0xF1,0xA5,0xA5);
-+	dcs_write_seq(0xB6,0x0D,0x0D);
-+	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
-+	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
-+	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
-+	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
-+	dcs_write_seq(0xB2,0x73);
-+	dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
-+	dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
-+	dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
-+	dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
-+	dcs_write_seq(0xBA,0x12,0x63);
-+	dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
-+	dcs_write_seq(0xC2,0x11,0x41);
-+	dcs_write_seq(0xC3,0x22,0x31,0x04);
-+	dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
-+	dcs_write_seq(0xC5,0x00);
-+	dcs_write_seq(0xD0,0x37,0xFF,0xFF);
-+	dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
-+	dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
-+	dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
-+	dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
-+	dcs_write_seq(0xF4,0x08,0x77);
-+	dcs_write_seq(0x36,0x14);
-+	dcs_write_seq(0x35,0x00);
-+	dcs_write_seq(0xF1,0x5A,0x5A);
-+	dcs_write_seq(0xF0,0xA5,0xA5);
- 
- 	return 0;
- }
diff --git a/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch b/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch
deleted file mode 100644
index 08c0f59eed..0000000000
--- a/target/linux/d1/patches-6.1/0112-drm-panel-cwd686-Fix-timings.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 6ea428297717faa16056076f7dd5a69e49c58fe6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 23:34:35 -0500
-Subject: [PATCH 112/117] drm: panel: cwd686: Fix timings
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 18 +++++++++---------
- 1 file changed, 9 insertions(+), 9 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -31,15 +31,15 @@ struct cwd686 {
- };
- 
- static const struct drm_display_mode default_mode = {
--	.clock = 54465,
--	.hdisplay = 480,
--	.hsync_start = 480 + 150,
--	.hsync_end = 480 + 150 + 24,
--	.htotal = 480 + 150 + 24 + 40,
--	.vdisplay = 1280,
--	.vsync_start = 1280 + 12,
--	.vsync_end = 1280 + 12 + 6,
--	.vtotal = 1280 + 12 + 6 + 10,
-+	.clock		= 54465,
-+	.hdisplay	= 480,
-+	.hsync_start	= 480 + 64,
-+	.hsync_end	= 480 + 64 + 40,
-+	.htotal		= 480 + 64 + 40 + 110,
-+	.vdisplay	= 1280,
-+	.vsync_start	= 1280 + 16,
-+	.vsync_end	= 1280 + 16 + 10,
-+	.vtotal		= 1280 + 16 + 10 + 2,
- };
- 
- static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
diff --git a/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch b/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch
deleted file mode 100644
index 5e732945a9..0000000000
--- a/target/linux/d1/patches-6.1/0113-drm-panel-cwd686-Disable-burst.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 16359ba0c5f5011e4742672454b35ad91a02fabe Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 8 Aug 2022 00:30:17 -0500
-Subject: [PATCH 113/117] drm: panel: cwd686: Disable burst
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -329,7 +329,6 @@ static int cwd686_probe(struct mipi_dsi_
- 	dsi->lanes = 4;
- 	dsi->format = MIPI_DSI_FMT_RGB888;
- 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
--			  MIPI_DSI_MODE_VIDEO_BURST |
- 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
- 
- 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
diff --git a/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch b/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch
deleted file mode 100644
index 334f75c68b..0000000000
--- a/target/linux/d1/patches-6.1/0114-drm-panel-cwd686-Use-the-init-sequence-from-the-R-01.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 02da00f2215f3d755ec806636fe499331870e8d6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:14:59 -0500
-Subject: [PATCH 114/117] drm: panel: cwd686: Use the init sequence from the
- R-01 BSP
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c    | 44 ++++++++-----------
- 1 file changed, 19 insertions(+), 25 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -131,34 +131,28 @@ static int cwd686_init_sequence(struct c
- {
- 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
- 
--	dcs_write_seq(0xF0,0x5A,0x5A);
--	dcs_write_seq(0xF1,0xA5,0xA5);
--	dcs_write_seq(0xB6,0x0D,0x0D);
--	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
--	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
--	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
--	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
-+	dcs_write_seq(0xF0,0x5A,0x59);
-+	dcs_write_seq(0xF1,0xA5,0xA6);
-+	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x9F,0x00,0x01,0x9F,0x00,0x01);
-+	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x29,0x06,0x06,0x72,0x06,0x06);
- 	dcs_write_seq(0xB2,0x73);
--	dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
--	dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
--	dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
--	dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
--	dcs_write_seq(0xBA,0x12,0x63);
--	dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
--	dcs_write_seq(0xC2,0x11,0x41);
--	dcs_write_seq(0xC3,0x22,0x31,0x04);
--	dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
--	dcs_write_seq(0xC5,0x00);
--	dcs_write_seq(0xD0,0x37,0xFF,0xFF);
--	dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
--	dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
--	dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
--	dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
--	dcs_write_seq(0xF4,0x08,0x77);
-+	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
-+	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
-+	dcs_write_seq(0xB6,0x13,0x13);
-+	dcs_write_seq(0xB8,0xB4,0x43,0x02,0xCC);
-+	dcs_write_seq(0xB9,0xA5,0x20,0xFF,0xC8);
-+	dcs_write_seq(0xBA,0x88,0x23);
-+	dcs_write_seq(0xBD,0x43,0x0E,0x0E,0x50,0x50,0x29,0x10,0x03,0x44,0x03);
-+	dcs_write_seq(0xC1,0x00,0x0C,0x16,0x04,0x00,0x30,0x10,0x04);
-+	dcs_write_seq(0xC2,0x21,0x81);
-+	dcs_write_seq(0xC3,0x02,0x30);
-+	dcs_write_seq(0xC7,0x25,0x6A);
-+	dcs_write_seq(0xC8,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06);
-+	dcs_write_seq(0xD4,0x00,0x00,0x00,0x32,0x04,0x51);
-+	dcs_write_seq(0xF1,0x5A,0x59);
-+	dcs_write_seq(0xF0,0xA5,0xA6);
- 	dcs_write_seq(0x36,0x14);
- 	dcs_write_seq(0x35,0x00);
--	dcs_write_seq(0xF1,0x5A,0x5A);
--	dcs_write_seq(0xF0,0xA5,0xA5);
- 
- 	return 0;
- }
diff --git a/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch b/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch
deleted file mode 100644
index 149e42d0cc..0000000000
--- a/target/linux/d1/patches-6.1/0115-drm-panel-cwd686-Power-up-sequence.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 6b438292e6b86a5cb5bffee2e517f1335903e39e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:15:24 -0500
-Subject: [PATCH 115/117] drm: panel: cwd686: Power up sequence
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -218,12 +218,14 @@ static int cwd686_prepare(struct drm_pan
- 		dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
- 		return err;
- 	}
-+	msleep(20);
- 
- 	err = regulator_enable(ctx->vci);
- 	if (err) {
- 		dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
- 		return err;
- 	}
-+	msleep(120);
- 
- 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- 	/* T2 */
diff --git a/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch b/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch
deleted file mode 100644
index b46a58752a..0000000000
--- a/target/linux/d1/patches-6.1/0116-drm-panel-cwd686-Why-is-this-not-getting-called.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From a19565eccfdc0fce7f41cfe70cd67a1a10d2113c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:15:39 -0500
-Subject: [PATCH 116/117] drm: panel: cwd686: Why is this not getting called?
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -373,6 +373,8 @@ static void cwd686_remove(struct mipi_ds
- 
- 	mipi_dsi_detach(dsi);
- 	drm_panel_remove(&ctx->panel);
-+	if (ctx->prepared)
-+		cwd686_unprepare(&ctx->panel);
- }
- 
- static const struct of_device_id cwd686_of_match[] = {
diff --git a/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch b/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch
deleted file mode 100644
index fd25a0af48..0000000000
--- a/target/linux/d1/patches-6.1/0117-riscv-dts-allwinner-d1-Add-video-engine-node.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From d6036571b774437bb3bdd378821033e118a01fe8 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 2 Nov 2022 23:42:52 -0500
-Subject: [PATCH 117/117] riscv: dts: allwinner: d1: Add video engine node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 30 ++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -105,6 +105,21 @@
- 			status = "reserved";
- 		};
- 
-+		ve: video-codec@1c0e000 {
-+			compatible = "allwinner,sun20i-d1-video-engine";
-+			reg = <0x1c0e000 0x2000>;
-+			interrupts = <82 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_VE>,
-+				 <&ccu CLK_VE>,
-+				 <&ccu CLK_MBUS_VE>;
-+			clock-names = "ahb", "mod", "ram";
-+			resets = <&ccu RST_BUS_VE>;
-+			allwinner,sram = <&ve_sram 1>;
-+			interconnects = <&mbus 4>;
-+			interconnect-names = "dma-mem";
-+			iommus = <&iommu 0>;
-+		};
-+
- 		pio: pinctrl@2000000 {
- 			compatible = "allwinner,sun20i-d1-pinctrl";
- 			reg = <0x2000000 0x800>;
-@@ -591,6 +606,21 @@
- 			#address-cells = <1>;
- 			#size-cells = <1>;
- 
-+			// FIXME: Address is not verified. It is copied from A64/H6.
-+			sram@1d00000 {
-+				compatible = "mmio-sram";
-+				reg = <0x1d00000 0x40000>;
-+				ranges = <0 0x1d00000 0x40000>;
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+
-+				ve_sram: sram-section@0 {
-+					compatible = "allwinner,sun20i-d1-sram-c1",
-+						     "allwinner,sun4i-a10-sram-c1";
-+					reg = <0 0x40000>;
-+				};
-+			};
-+
- 			regulators@3000150 {
- 				compatible = "allwinner,sun20i-d1-system-ldos";
- 				reg = <0x3000150 0x4>;
diff --git a/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch
new file mode 100644
index 0000000000..4652b640fe
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0001-riscv-dts-allwinner-d1-Add-PMU-event-node.patch
@@ -0,0 +1,64 @@
+From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001
+From: Inochi Amaoto <inochiama@outlook.com>
+Date: Mon, 28 Aug 2023 12:30:22 +0800
+Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node
+
+D1 has several pmu events supported by opensbi.
+These events can be used by perf for profiling.
+
+Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
+Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
+Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Reviewed-by: Guo Ren <guoren@kernel.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+@@ -72,4 +72,43 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 	};
++
++	pmu {
++		compatible = "riscv,pmu";
++		riscv,event-to-mhpmcounters =
++			<0x00003 0x00003 0x00000008>,
++			<0x00004 0x00004 0x00000010>,
++			<0x00005 0x00005 0x00000200>,
++			<0x00006 0x00006 0x00000100>,
++			<0x10000 0x10000 0x00004000>,
++			<0x10001 0x10001 0x00008000>,
++			<0x10002 0x10002 0x00010000>,
++			<0x10003 0x10003 0x00020000>,
++			<0x10019 0x10019 0x00000040>,
++			<0x10021 0x10021 0x00000020>;
++		riscv,event-to-mhpmevent =
++			<0x00003 0x00000000 0x00000001>,
++			<0x00004 0x00000000 0x00000002>,
++			<0x00005 0x00000000 0x00000007>,
++			<0x00006 0x00000000 0x00000006>,
++			<0x10000 0x00000000 0x0000000c>,
++			<0x10001 0x00000000 0x0000000d>,
++			<0x10002 0x00000000 0x0000000e>,
++			<0x10003 0x00000000 0x0000000f>,
++			<0x10019 0x00000000 0x00000004>,
++			<0x10021 0x00000000 0x00000003>;
++		riscv,raw-event-to-mhpmcounters =
++			<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
++			<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
++			<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
++			<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
++			<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
++			<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
++			<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
++			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
++			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
++			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
++			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
++			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
++	};
+ };
diff --git a/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch
new file mode 100644
index 0000000000..db3ce3dcca
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0002-riscv-dts-allwinner-Update-opp-table-to-allow-CPU-fr.patch
@@ -0,0 +1,59 @@
+From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:39 +0100
+Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU
+ frequency scaling
+
+Two OPPs are currently defined for the D1/D1s; one at 408MHz and
+another at 1.08GHz. Switching between these can be done with the
+"sun50i-cpufreq-nvmem" driver. This patch populates the opp table
+appropriately, inspired by
+https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi
+
+The supply voltages are PWM-controlled, but support for that IP
+is still in the works. So stick to a target vdd-cpu supply of 0.9V,
+which seems to be the default on most D1 boards.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+@@ -36,16 +36,22 @@
+ 	};
+ 
+ 	opp_table_cpu: opp-table-cpu {
+-		compatible = "operating-points-v2";
++		compatible = "allwinner,sun20i-d1-operating-points",
++				 "allwinner,sun50i-h6-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		nvmem-cell-names = "speed";
++		opp-shared;
+ 
+ 		opp-408000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
+ 			opp-hz = /bits/ 64 <408000000>;
+-			opp-microvolt = <900000 900000 1100000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
+ 		};
+ 
+ 		opp-1080000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
+ 			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <900000 900000 1100000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
+ 		};
+ 	};
+ 
+@@ -112,3 +118,9 @@
+ 			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ 	};
+ };
++
++&sid {
++	cpu_speed_grade: cpu-speed-grade@0 {
++		reg = <0x00 0x2>;
++	};
++};
diff --git a/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch
new file mode 100644
index 0000000000..b60551be86
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0003-dt-bindings-opp-sun50i-Add-binding-for-D1-CPUs.patch
@@ -0,0 +1,25 @@
+From e904f32e5fe694ed7b8d1cd914bcf2bfd67e896c Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:40 +0100
+Subject: [PATCH 03/14] dt-bindings: opp: sun50i: Add binding for D1 CPUs
+
+Add binding for D1 CPU OPPs.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml    | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
++++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+@@ -23,7 +23,9 @@ allOf:
+ 
+ properties:
+   compatible:
+-    const: allwinner,sun50i-h6-operating-points
++    enum:
++      - allwinner,sun50i-h6-operating-points
++      - allwinner,sun20i-d1-operating-points
+ 
+   nvmem-cells:
+     description: |
diff --git a/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch
new file mode 100644
index 0000000000..e918156eb1
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0004-cpufreq-sun50i-Add-D1-support.patch
@@ -0,0 +1,23 @@
+From b294def636629cc4d9feff4ed610a0d0c68a58fd Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:41 +0100
+Subject: [PATCH 04/14] cpufreq: sun50i: Add D1 support
+
+Add support for D1 based devices to the Allwinner H6 cpufreq
+driver
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpu
+ 
+ static const struct of_device_id sun50i_cpufreq_match_list[] = {
+ 	{ .compatible = "allwinner,sun50i-h6" },
++	{ .compatible = "allwinner,sun20i-d1" },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
diff --git a/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch
new file mode 100644
index 0000000000..3127a0e9bb
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0005-cpufreq-dt-platdev-Blocklist-allwinner-sun20i-d1-SoC.patch
@@ -0,0 +1,23 @@
+From 9d78aafd278577ef2a9d92127c9d35b00989c057 Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:42 +0100
+Subject: [PATCH 05/14] cpufreq: dt-platdev: Blocklist allwinner,sun20i-d1 SoC
+
+The Allwinner D1 uses H6 cpufreq driver. Add it to blocklist
+so the "cpufreq-dt" device is not created twice.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -104,6 +104,7 @@ static const struct of_device_id allowli
+  */
+ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "allwinner,sun50i-h6", },
++	{ .compatible = "allwinner,sun20i-d1", },
+ 
+ 	{ .compatible = "apple,arm-platform", },
+ 
diff --git a/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch
new file mode 100644
index 0000000000..7ff3095ebc
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0006-cpufreq-Make-sun50i-h6-cpufreq-Kconfig-option-arch-g.patch
@@ -0,0 +1,69 @@
+From e4a8ff817e133d84f8a82f78461e0592e5e9d9cc Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:43 +0100
+Subject: [PATCH 06/14] cpufreq: Make sun50i h6 cpufreq Kconfig option arch
+ generic
+
+Move the Allwinner SUN50I cpufreq driver from Kconfig.arm to the
+main Kconfig file so it supports other architectures, like RISC-V
+in our case, and drop the 'ARM_' prefix.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/Kconfig     | 12 ++++++++++++
+ drivers/cpufreq/Kconfig.arm | 12 ------------
+ drivers/cpufreq/Makefile    |  2 +-
+ 3 files changed, 13 insertions(+), 13 deletions(-)
+
+--- a/drivers/cpufreq/Kconfig
++++ b/drivers/cpufreq/Kconfig
+@@ -312,5 +312,17 @@ config QORIQ_CPUFREQ
+ 	  This adds the CPUFreq driver support for Freescale QorIQ SoCs
+ 	  which are capable of changing the CPU's frequency dynamically.
+ 
++config ALLWINNER_SUN50I_CPUFREQ_NVMEM
++	tristate "Allwinner nvmem based SUN50I CPUFreq driver"
++	depends on ARCH_SUNXI
++	depends on NVMEM_SUNXI_SID
++	select PM_OPP
++	help
++	  This adds the nvmem based CPUFreq driver for Allwinner
++	  h6/D1 SoCs.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called sun50i-cpufreq-nvmem.
++
+ endif
+ endmenu
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -29,18 +29,6 @@ config ACPI_CPPC_CPUFREQ_FIE
+ 
+ 	  If in doubt, say N.
+ 
+-config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
+-	tristate "Allwinner nvmem based SUN50I CPUFreq driver"
+-	depends on ARCH_SUNXI
+-	depends on NVMEM_SUNXI_SID
+-	select PM_OPP
+-	help
+-	  This adds the nvmem based CPUFreq driver for Allwinner
+-	  h6 SoC.
+-
+-	  To compile this driver as a module, choose M here: the
+-	  module will be called sun50i-cpufreq-nvmem.
+-
+ config ARM_APPLE_SOC_CPUFREQ
+ 	tristate "Apple Silicon SoC CPUFreq support"
+ 	depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
+--- a/drivers/cpufreq/Makefile
++++ b/drivers/cpufreq/Makefile
+@@ -78,7 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ)		+= scmi-
+ obj-$(CONFIG_ARM_SCPI_CPUFREQ)		+= scpi-cpufreq.o
+ obj-$(CONFIG_ARM_SPEAR_CPUFREQ)		+= spear-cpufreq.o
+ obj-$(CONFIG_ARM_STI_CPUFREQ)		+= sti-cpufreq.o
+-obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
++obj-$(CONFIG_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
+ obj-$(CONFIG_ARM_TEGRA20_CPUFREQ)	+= tegra20-cpufreq.o
+ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ)	+= tegra124-cpufreq.o
+ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)	+= tegra186-cpufreq.o
diff --git a/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch
new file mode 100644
index 0000000000..ad50d9130c
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0007-ASoC-dt-bindings-sun4i-a10-codec-Add-binding-for-All.patch
@@ -0,0 +1,116 @@
+From 3341f884d75929a009801d4299d219e64c64a33c Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:01 +0300
+Subject: [PATCH 07/14] ASoC: dt-bindings: sun4i-a10-codec: Add binding for
+ Allwinner D1 SoC
+
+The Allwinner D1 SoC has a internal audio codec that similar to previous
+ones, but it contains a three ADC channels instead of two, and also has
+a separate clocks for ADC and DAC modules.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../sound/allwinner,sun4i-a10-codec.yaml      | 64 ++++++++++++++++---
+ 1 file changed, 56 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml
+@@ -22,6 +22,7 @@ properties:
+       - allwinner,sun8i-a23-codec
+       - allwinner,sun8i-h3-codec
+       - allwinner,sun8i-v3s-codec
++      - allwinner,sun20i-d1-codec
+ 
+   reg:
+     maxItems: 1
+@@ -29,15 +30,9 @@ properties:
+   interrupts:
+     maxItems: 1
+ 
+-  clocks:
+-    items:
+-      - description: Bus Clock
+-      - description: Module Clock
++  clocks: true
+ 
+-  clock-names:
+-    items:
+-      - const: apb
+-      - const: codec
++  clock-names: true
+ 
+   dmas:
+     items:
+@@ -106,11 +101,42 @@ allOf:
+   - if:
+       properties:
+         compatible:
++          const: allwinner,sun20i-d1-codec
++    then:
++      properties:
++        clocks:
++          items:
++            - description: Bus Clock
++            - description: ADC Module Clock
++            - description: DAC Module Clock
++
++        clock-names:
++          items:
++            - const: apb
++            - const: adc
++            - const: dac
++
++    else:
++      properties:
++        clocks:
++          items:
++            - description: Bus Clock
++            - description: Module Clock
++
++        clock-names:
++          items:
++            - const: apb
++            - const: codec
++
++  - if:
++      properties:
++        compatible:
+           enum:
+             - allwinner,sun6i-a31-codec
+             - allwinner,sun8i-a23-codec
+             - allwinner,sun8i-h3-codec
+             - allwinner,sun8i-v3s-codec
++            - allwinner,sun20i-d1-codec
+ 
+     then:
+       if:
+@@ -225,6 +251,28 @@ allOf:
+               - Headphone
+               - Headset Mic
+               - Line In
++              - Line Out
++              - Mic
++              - Speaker
++
++  - if:
++      properties:
++        compatible:
++          enum:
++            - allwinner,sun20i-d1-codec
++
++    then:
++      properties:
++        allwinner,audio-routing:
++          items:
++            enum:
++              - HP
++              - LINEIN
++              - MIC3
++              - MBIAS
++              - Headphone
++              - Headset Mic
++              - Line In
+               - Line Out
+               - Mic
+               - Speaker
diff --git a/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch
new file mode 100644
index 0000000000..d25a27de92
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0008-ASoC-dt-bindings-Add-schema-for-allwinner-sun20i-d1-.patch
@@ -0,0 +1,51 @@
+From 64efc9cc704d27c60dc9c96a02d842f22dbdfeae Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:02 +0300
+Subject: [PATCH 08/14] ASoC: dt-bindings: Add schema for
+ "allwinner,sun20i-d1-codec-analog"
+
+Add a DT schema to describe the analog part of the Allwinner D1/T113s
+internal audio codec.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ .../allwinner,sun20i-d1-codec-analog.yaml     | 33 +++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml
+@@ -0,0 +1,33 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/sound/allwinner,sun20i-d1-codec-analog.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner D1 Analog Codec
++
++maintainers:
++  - Maksim Kiselev <bigunclemax@gmail.com>
++
++properties:
++  compatible:
++    const: allwinner,sun20i-d1-codec-analog
++
++  reg:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++
++additionalProperties: false
++
++examples:
++  - |
++    codec_analog: codec-analog@2030300 {
++        compatible = "allwinner,sun20i-d1-codec-analog";
++        reg = <0x02030300 0xd00>;
++    };
++
++...
++
diff --git a/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch
new file mode 100644
index 0000000000..242f8f7a0e
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0009-ASoC-sunxi-sun4i-codec-add-basic-support-for-D1-audi.patch
@@ -0,0 +1,614 @@
+From 0963766bc665769aebf370d44ee3a97facfbca57 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:03 +0300
+Subject: [PATCH 09/14] ASoC: sunxi: sun4i-codec: add basic support for D1
+ audio codec
+
+Allwinner D1 has an audio codec similar to earlier ones, but it comes
+with 3 channel ADC instead of 2, and many registers are moved.
+
+Add basic support for it.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ sound/soc/sunxi/sun4i-codec.c | 364 ++++++++++++++++++++++++++++------
+ 1 file changed, 300 insertions(+), 64 deletions(-)
+
+--- a/sound/soc/sunxi/sun4i-codec.c
++++ b/sound/soc/sunxi/sun4i-codec.c
+@@ -232,15 +232,65 @@
+ 
+ /* TODO H3 DAP (Digital Audio Processing) bits */
+ 
++/*
++ * sun20i D1 and similar codecs specific registers
++ *
++ * Almost all registers moved on D1, including ADC digital controls,
++ * FIFO and RX data registers. Only DAC control are at the same offset.
++ */
++
++#define SUN20I_D1_CODEC_DAC_VOL_CTRL		(0x04)
++#define SUN20I_D1_CODEC_DAC_VOL_SEL			(16)
++#define SUN20I_D1_CODEC_DAC_VOL_L			(8)
++#define SUN20I_D1_CODEC_DAC_VOL_R			(0)
++#define SUN20I_D1_CODEC_DAC_FIFOC		(0x10)
++#define SUN20I_D1_CODEC_ADC_FIFOC		(0x30)
++#define SUN20I_D1_CODEC_ADC_FIFOC_EN_AD			(28)
++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS	(16)
++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL		(4)
++#define SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN		(3)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1		(0x34)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL		(16)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL		(8)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL		(0)
++#define SUN20I_D1_CODEC_ADC_RXDATA		(0x40)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL		(0x50)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN		(2)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN		(1)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN		(0)
++#define SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL	(0x54)
++
++/* TODO D1 DAP (Digital Audio Processing) bits */
++
++struct sun4i_codec;
++
++struct sun4i_codec_quirks {
++	const struct regmap_config *regmap_config;
++	const struct snd_soc_component_driver *codec;
++	struct snd_soc_card * (*create_card)(struct device *dev);
++	struct reg_field reg_dac_fifoc;	/* used for regmap_field */
++	struct reg_field reg_adc_fifoc;	/* used for regmap_field */
++	unsigned int adc_drq_en;
++	unsigned int rx_sample_bits;
++	unsigned int rx_trig_level;
++	unsigned int reg_dac_txdata;	/* TX FIFO offset for DMA config */
++	unsigned int reg_adc_rxdata;	/* RX FIFO offset for DMA config */
++	bool has_reset;
++	bool has_dual_clock;
++};
++
+ struct sun4i_codec {
+ 	struct device	*dev;
+ 	struct regmap	*regmap;
+ 	struct clk	*clk_apb;
+-	struct clk	*clk_module;
++	struct clk	*clk_module; /* used for ADC if clocks are separate */
++	struct clk	*clk_module_dac;
+ 	struct reset_control *rst;
+ 	struct gpio_desc *gpio_pa;
++	const struct sun4i_codec_quirks *quirks;
+ 
+-	/* ADC_FIFOC register is at different offset on different SoCs */
++	/* DAC/ADC FIFOC registers are at different offset on different SoCs */
++	struct regmap_field *reg_dac_fifoc;
+ 	struct regmap_field *reg_adc_fifoc;
+ 
+ 	struct snd_dmaengine_dai_dma_data	capture_dma_data;
+@@ -250,33 +300,33 @@ struct sun4i_codec {
+ static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
+ {
+ 	/* Flush TX FIFO */
+-	regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
++	regmap_field_set_bits(scodec->reg_dac_fifoc,
++			      BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+ 
+ 	/* Enable DAC DRQ */
+-	regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
++	regmap_field_set_bits(scodec->reg_dac_fifoc,
++			      BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+ }
+ 
+ static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
+ {
+ 	/* Disable DAC DRQ */
+-	regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			  BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
++	regmap_field_clear_bits(scodec->reg_dac_fifoc,
++				BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+ }
+ 
+ static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
+ {
+ 	/* Enable ADC DRQ */
+ 	regmap_field_set_bits(scodec->reg_adc_fifoc,
+-			      BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
++			      BIT(scodec->quirks->adc_drq_en));
+ }
+ 
+ static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
+ {
+ 	/* Disable ADC DRQ */
+ 	regmap_field_clear_bits(scodec->reg_adc_fifoc,
+-				 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
++				BIT(scodec->quirks->adc_drq_en));
+ }
+ 
+ static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
+@@ -325,8 +375,8 @@ static int sun4i_codec_prepare_capture(s
+ 
+ 	/* Set RX FIFO trigger level */
+ 	regmap_field_update_bits(scodec->reg_adc_fifoc,
+-				 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+-				 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
++				 0xf << scodec->quirks->rx_trig_level,
++				 0x7 << scodec->quirks->rx_trig_level);
+ 
+ 	/*
+ 	 * FIXME: Undocumented in the datasheet, but
+@@ -360,13 +410,13 @@ static int sun4i_codec_prepare_playback(
+ 	u32 val;
+ 
+ 	/* Flush the TX FIFO */
+-	regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
++	regmap_field_set_bits(scodec->reg_dac_fifoc,
++			      BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+ 
+ 	/* Set TX FIFO Empty Trigger Level */
+-	regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
+-			   0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
++	regmap_field_update_bits(scodec->reg_dac_fifoc,
++				 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
++				 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
+ 
+ 	if (substream->runtime->rate > 32000)
+ 		/* Use 64 bits FIR filter */
+@@ -375,13 +425,12 @@ static int sun4i_codec_prepare_playback(
+ 		/* Use 32 bits FIR filter */
+ 		val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
+ 
+-	regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
+-			   val);
++	regmap_field_update_bits(scodec->reg_dac_fifoc,
++				 BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), val);
+ 
+ 	/* Send zeros when we have an underrun */
+-	regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
++	regmap_field_clear_bits(scodec->reg_dac_fifoc,
++				BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
+ 
+ 	return 0;
+ };
+@@ -476,30 +525,32 @@ static int sun4i_codec_hw_params_capture
+ 				 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
+ 				 hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
+ 
+-	/* Set the number of channels we want to use */
+-	if (params_channels(params) == 1)
+-		regmap_field_set_bits(scodec->reg_adc_fifoc,
+-					 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
+-	else
+-		regmap_field_clear_bits(scodec->reg_adc_fifoc,
+-					 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++	if (!scodec->quirks->has_dual_clock) {
++		/* Set the number of channels we want to use */
++		if (params_channels(params) == 1)
++			regmap_field_set_bits(scodec->reg_adc_fifoc,
++					      BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++		else
++			regmap_field_clear_bits(scodec->reg_adc_fifoc,
++						BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++	}
+ 
+ 	/* Set the number of sample bits to either 16 or 24 bits */
+ 	if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+ 		regmap_field_set_bits(scodec->reg_adc_fifoc,
+-				   BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
++				      BIT(scodec->quirks->rx_sample_bits));
+ 
+ 		regmap_field_clear_bits(scodec->reg_adc_fifoc,
+-				   BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
++					BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+ 
+ 		scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ 	} else {
+ 		regmap_field_clear_bits(scodec->reg_adc_fifoc,
+-				   BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
++					BIT(scodec->quirks->rx_sample_bits));
+ 
+ 		/* Fill most significant bits with valid data MSB */
+ 		regmap_field_set_bits(scodec->reg_adc_fifoc,
+-				   BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
++				      BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+ 
+ 		scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ 	}
+@@ -514,9 +565,9 @@ static int sun4i_codec_hw_params_playbac
+ 	u32 val;
+ 
+ 	/* Set DAC sample rate */
+-	regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
+-			   hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
++	regmap_field_update_bits(scodec->reg_dac_fifoc,
++				 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
++				 hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
+ 
+ 	/* Set the number of channels we want to use */
+ 	if (params_channels(params) == 1)
+@@ -524,27 +575,26 @@ static int sun4i_codec_hw_params_playbac
+ 	else
+ 		val = 0;
+ 
+-	regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
+-			   val);
++	regmap_field_update_bits(scodec->reg_dac_fifoc,
++				 BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), val);
+ 
+ 	/* Set the number of sample bits to either 16 or 24 bits */
+ 	if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+-		regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-				   BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
++		regmap_field_set_bits(scodec->reg_dac_fifoc,
++				      BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+ 
+ 		/* Set TX FIFO mode to padding the LSBs with 0 */
+-		regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-				   BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
++		regmap_field_clear_bits(scodec->reg_dac_fifoc,
++					BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+ 
+ 		scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ 	} else {
+-		regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-				   BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
++		regmap_field_clear_bits(scodec->reg_dac_fifoc,
++					BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+ 
+ 		/* Set TX FIFO mode to repeat the MSB */
+-		regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-				   BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
++		regmap_field_set_bits(scodec->reg_dac_fifoc,
++				      BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+ 
+ 		scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ 	}
+@@ -565,7 +615,11 @@ static int sun4i_codec_hw_params(struct
+ 	if (!clk_freq)
+ 		return -EINVAL;
+ 
+-	ret = clk_set_rate(scodec->clk_module, clk_freq);
++	if (scodec->clk_module_dac &&
++	    substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		ret = clk_set_rate(scodec->clk_module_dac, clk_freq);
++	else
++		ret = clk_set_rate(scodec->clk_module, clk_freq);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -607,10 +661,14 @@ static int sun4i_codec_startup(struct sn
+ 	 * Stop issuing DRQ when we have room for less than 16 samples
+ 	 * in our TX FIFO
+ 	 */
+-	regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+-			   3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
++	regmap_field_set_bits(scodec->reg_dac_fifoc,
++			      3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
+ 
+-	return clk_prepare_enable(scodec->clk_module);
++	if (scodec->clk_module_dac &&
++	    substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		return clk_prepare_enable(scodec->clk_module_dac);
++	else
++		return clk_prepare_enable(scodec->clk_module);
+ }
+ 
+ static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
+@@ -619,7 +677,11 @@ static void sun4i_codec_shutdown(struct
+ 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ 	struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+ 
+-	clk_disable_unprepare(scodec->clk_module);
++	if (scodec->clk_module_dac &&
++	    substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		clk_disable_unprepare(scodec->clk_module_dac);
++	else
++		clk_disable_unprepare(scodec->clk_module);
+ }
+ 
+ static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
+@@ -1229,6 +1291,55 @@ static const struct snd_soc_component_dr
+ 	.endianness		= 1,
+ };
+ 
++/* sun20i D1 codec */
++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_dvol_scale, -12000, 75, 1);
++
++static const struct snd_kcontrol_new sun20i_d1_codec_codec_controls[] = {
++	SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
++		       SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
++		       sun6i_codec_dvol_scale),
++	SOC_DOUBLE_TLV("DAC Front Playback Volume", SUN20I_D1_CODEC_DAC_VOL_CTRL,
++		       SUN20I_D1_CODEC_DAC_VOL_L, SUN20I_D1_CODEC_DAC_VOL_R,
++		       0xFF, 0, sun20i_d1_codec_dvol_scale),
++
++	SOC_SINGLE_TLV("ADC1 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++		       SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL, 0xff, 0,
++		       sun20i_d1_codec_dvol_scale),
++	SOC_SINGLE_TLV("ADC2 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++		       SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL, 0xff, 0,
++		       sun20i_d1_codec_dvol_scale),
++	SOC_SINGLE_TLV("ADC3 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++		       SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL, 0xff, 0,
++		       sun20i_d1_codec_dvol_scale),
++};
++
++static const struct snd_soc_dapm_widget sun20i_d1_codec_codec_widgets[] = {
++	/* Digital parts of the ADCs */
++	SND_SOC_DAPM_SUPPLY("ADC Enable", SUN20I_D1_CODEC_ADC_FIFOC,
++			    SUN20I_D1_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("ADC1 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++			    SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("ADC2 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++			    SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("ADC3 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++			    SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN, 0, NULL, 0),
++	/* Digital parts of the DACs */
++	SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
++			    SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("DAC VOL_SEL Enable", SUN20I_D1_CODEC_DAC_VOL_CTRL,
++			    SUN20I_D1_CODEC_DAC_VOL_SEL, 0, NULL, 0),
++};
++
++static const struct snd_soc_component_driver sun20i_d1_codec_codec = {
++	.controls		= sun20i_d1_codec_codec_controls,
++	.num_controls		= ARRAY_SIZE(sun20i_d1_codec_codec_controls),
++	.dapm_widgets		= sun20i_d1_codec_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(sun20i_d1_codec_codec_widgets),
++	.idle_bias_on		= 1,
++	.use_pmdown_time	= 1,
++	.endianness		= 1,
++};
++
+ static const struct snd_soc_component_driver sun4i_codec_component = {
+ 	.name			= "sun4i-codec",
+ 	.legacy_dai_naming	= 1,
+@@ -1532,6 +1643,66 @@ static struct snd_soc_card *sun8i_v3s_co
+ 	return card;
+ };
+ 
++static const struct snd_soc_dapm_route sun20i_d1_codec_card_routes[] = {
++	/* ADC Routes */
++	{ "ADC1", NULL, "ADC Enable" },
++	{ "ADC2", NULL, "ADC Enable" },
++	{ "ADC3", NULL, "ADC Enable" },
++	{ "ADC1", NULL, "ADC1 CH Enable" },
++	{ "ADC2", NULL, "ADC2 CH Enable" },
++	{ "ADC3", NULL, "ADC3 CH Enable" },
++	{ "Codec Capture", NULL, "ADC1" },
++	{ "Codec Capture", NULL, "ADC2" },
++	{ "Codec Capture", NULL, "ADC3" },
++
++	/* DAC Routes */
++	{ "Left DAC", NULL, "DAC Enable" },
++	{ "Right DAC", NULL, "DAC Enable" },
++	{ "Left DAC", NULL, "DAC VOL_SEL Enable" },
++	{ "Right DAC", NULL, "DAC VOL_SEL Enable" },
++	{ "Left DAC", NULL, "Codec Playback" },
++	{ "Right DAC", NULL, "Codec Playback" },
++};
++
++static struct snd_soc_card *sun20i_d1_codec_create_card(struct device *dev)
++{
++	struct snd_soc_card *card;
++	int ret;
++
++	card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++	if (!card)
++		return ERR_PTR(-ENOMEM);
++
++	aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
++					       "allwinner,codec-analog-controls",
++					       0);
++	if (!aux_dev.dlc.of_node) {
++		dev_err(dev, "Can't find analog controls for codec.\n");
++		return ERR_PTR(-EINVAL);
++	}
++
++	card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
++	if (!card->dai_link)
++		return ERR_PTR(-ENOMEM);
++
++	card->dev		= dev;
++	card->owner		= THIS_MODULE;
++	card->name		= "D1 Audio Codec";
++	card->dapm_widgets	= sun6i_codec_card_dapm_widgets;
++	card->num_dapm_widgets	= ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
++	card->dapm_routes	= sun20i_d1_codec_card_routes;
++	card->num_dapm_routes	= ARRAY_SIZE(sun20i_d1_codec_card_routes);
++	card->aux_dev		= &aux_dev;
++	card->num_aux_devs	= 1;
++	card->fully_routed	= true;
++
++	ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
++	if (ret)
++		dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
++
++	return card;
++};
++
+ static const struct regmap_config sun4i_codec_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.reg_stride	= 4,
+@@ -1574,21 +1745,22 @@ static const struct regmap_config sun8i_
+ 	.max_register	= SUN8I_H3_CODEC_ADC_DBG,
+ };
+ 
+-struct sun4i_codec_quirks {
+-	const struct regmap_config *regmap_config;
+-	const struct snd_soc_component_driver *codec;
+-	struct snd_soc_card * (*create_card)(struct device *dev);
+-	struct reg_field reg_adc_fifoc;	/* used for regmap_field */
+-	unsigned int reg_dac_txdata;	/* TX FIFO offset for DMA config */
+-	unsigned int reg_adc_rxdata;	/* RX FIFO offset for DMA config */
+-	bool has_reset;
++static const struct regmap_config sun20i_d1_codec_regmap_config = {
++	.reg_bits	= 32,
++	.reg_stride	= 4,
++	.val_bits	= 32,
++	.max_register	= SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL,
+ };
+ 
+ static const struct sun4i_codec_quirks sun4i_codec_quirks = {
+ 	.regmap_config	= &sun4i_codec_regmap_config,
+ 	.codec		= &sun4i_codec_codec,
+ 	.create_card	= sun4i_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN4I_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN4I_CODEC_ADC_RXDATA,
+ };
+@@ -1597,7 +1769,11 @@ static const struct sun4i_codec_quirks s
+ 	.regmap_config	= &sun6i_codec_regmap_config,
+ 	.codec		= &sun6i_codec_codec,
+ 	.create_card	= sun6i_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN4I_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN6I_CODEC_ADC_RXDATA,
+ 	.has_reset	= true,
+@@ -1607,7 +1783,11 @@ static const struct sun4i_codec_quirks s
+ 	.regmap_config	= &sun7i_codec_regmap_config,
+ 	.codec		= &sun7i_codec_codec,
+ 	.create_card	= sun4i_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN4I_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN4I_CODEC_ADC_RXDATA,
+ };
+@@ -1616,7 +1796,11 @@ static const struct sun4i_codec_quirks s
+ 	.regmap_config	= &sun8i_a23_codec_regmap_config,
+ 	.codec		= &sun8i_a23_codec_codec,
+ 	.create_card	= sun8i_a23_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN4I_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN6I_CODEC_ADC_RXDATA,
+ 	.has_reset	= true,
+@@ -1631,7 +1815,11 @@ static const struct sun4i_codec_quirks s
+ 	 */
+ 	.codec		= &sun8i_a23_codec_codec,
+ 	.create_card	= sun8i_h3_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN8I_H3_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN6I_CODEC_ADC_RXDATA,
+ 	.has_reset	= true,
+@@ -1645,12 +1833,31 @@ static const struct sun4i_codec_quirks s
+ 	 */
+ 	.codec		= &sun8i_a23_codec_codec,
+ 	.create_card	= sun8i_v3s_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ 	.reg_adc_fifoc	= REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ 	.reg_dac_txdata	= SUN8I_H3_CODEC_DAC_TXDATA,
+ 	.reg_adc_rxdata	= SUN6I_CODEC_ADC_RXDATA,
+ 	.has_reset	= true,
+ };
+ 
++static const struct sun4i_codec_quirks sun20i_d1_codec_quirks = {
++	.regmap_config	= &sun20i_d1_codec_regmap_config,
++	.codec		= &sun20i_d1_codec_codec,
++	.create_card	= sun20i_d1_codec_create_card,
++	.reg_dac_fifoc	= REG_FIELD(SUN20I_D1_CODEC_DAC_FIFOC, 0, 31),
++	.reg_adc_fifoc	= REG_FIELD(SUN20I_D1_CODEC_ADC_FIFOC, 0, 31),
++	.adc_drq_en	= SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++	.rx_sample_bits	= SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++	.rx_trig_level	= SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
++	.reg_dac_txdata	= SUN8I_H3_CODEC_DAC_TXDATA,
++	.reg_adc_rxdata	= SUN20I_D1_CODEC_ADC_RXDATA,
++	.has_reset	= true,
++	.has_dual_clock = true,
++};
++
+ static const struct of_device_id sun4i_codec_of_match[] = {
+ 	{
+ 		.compatible = "allwinner,sun4i-a10-codec",
+@@ -1676,6 +1883,10 @@ static const struct of_device_id sun4i_c
+ 		.compatible = "allwinner,sun8i-v3s-codec",
+ 		.data = &sun8i_v3s_codec_quirks,
+ 	},
++	{
++		.compatible = "allwinner,sun20i-d1-codec",
++		.data = &sun20i_d1_codec_quirks,
++	},
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
+@@ -1704,6 +1915,7 @@ static int sun4i_codec_probe(struct plat
+ 		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ 		return -ENODEV;
+ 	}
++	scodec->quirks = quirks;
+ 
+ 	scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ 					       quirks->regmap_config);
+@@ -1719,10 +1931,24 @@ static int sun4i_codec_probe(struct plat
+ 		return PTR_ERR(scodec->clk_apb);
+ 	}
+ 
+-	scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
+-	if (IS_ERR(scodec->clk_module)) {
+-		dev_err(&pdev->dev, "Failed to get the module clock\n");
+-		return PTR_ERR(scodec->clk_module);
++	if (quirks->has_dual_clock) {
++		scodec->clk_module = devm_clk_get(&pdev->dev, "adc");
++		if (IS_ERR(scodec->clk_module)) {
++			dev_err(&pdev->dev, "Failed to get the ADC module clock\n");
++			return PTR_ERR(scodec->clk_module);
++		}
++
++		scodec->clk_module_dac = devm_clk_get(&pdev->dev, "dac");
++		if (IS_ERR(scodec->clk_module_dac)) {
++			dev_err(&pdev->dev, "Failed to get the DAC module clock\n");
++			return PTR_ERR(scodec->clk_module_dac);
++		}
++	} else {
++		scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
++		if (IS_ERR(scodec->clk_module)) {
++			dev_err(&pdev->dev, "Failed to get the module clock\n");
++			return PTR_ERR(scodec->clk_module);
++		}
+ 	}
+ 
+ 	if (quirks->has_reset) {
+@@ -1751,6 +1977,16 @@ static int sun4i_codec_probe(struct plat
+ 		dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
+ 			ret);
+ 		return ret;
++	}
++
++	scodec->reg_dac_fifoc = devm_regmap_field_alloc(&pdev->dev,
++							scodec->regmap,
++							quirks->reg_dac_fifoc);
++	if (IS_ERR(scodec->reg_dac_fifoc)) {
++		ret = PTR_ERR(scodec->reg_dac_fifoc);
++		dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
++			ret);
++		return ret;
+ 	}
+ 
+ 	/* Enable the bus clock */
diff --git a/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch
new file mode 100644
index 0000000000..345504d321
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0010-ASoC-sunxi-Add-new-driver-for-Allwinner-D1-T113s-cod.patch
@@ -0,0 +1,274 @@
+From c8c3c516ca5c38e7858055ce0137efde17a07190 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:04 +0300
+Subject: [PATCH 10/14] ASoC: sunxi: Add new driver for Allwinner D1/T113s
+ codec's analog path controls
+
+The internal codec on D1/T113s is split into 2 parts like the previous
+ones. But now analog path controls registers are mapped directly
+on the bus, right after the registers of the digital part.
+
+Add an ASoC component driver for it. This should be tied to the codec
+audio card as an auxiliary device.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ sound/soc/sunxi/Kconfig                  |  11 ++
+ sound/soc/sunxi/Makefile                 |   1 +
+ sound/soc/sunxi/sun20i-d1-codec-analog.c | 220 +++++++++++++++++++++++
+ 3 files changed, 232 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun20i-d1-codec-analog.c
+
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -38,6 +38,17 @@ config SND_SUN50I_CODEC_ANALOG
+ 	  Say Y or M if you want to add support for the analog controls for
+ 	  the codec embedded in Allwinner A64 SoC.
+ 
++config SND_SUN20I_D1_CODEC_ANALOG
++	tristate "Allwinner D1 Codec Analog Controls Support"
++	depends on ARCH_SUNXI || COMPILE_TEST
++	select REGMAP_MMIO
++	help
++	  This option enables the analog controls part of the internal audio
++	  codec for Allwinner D1/T113s SoCs family.
++
++	  Say Y or M if you want to add support for the analog part of
++	  the D1/T113s audio codec.
++
+ config SND_SUN4I_I2S
+ 	tristate "Allwinner A10 I2S Support"
+ 	select SND_SOC_GENERIC_DMAENGINE_PCM
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+ obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
++obj-$(CONFIG_SND_SUN20I_D1_CODEC_ANALOG) += sun20i-d1-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+ obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
+--- /dev/null
++++ b/sound/soc/sunxi/sun20i-d1-codec-analog.c
+@@ -0,0 +1,220 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * This driver supports the analog controls for the internal codec
++ * found in Allwinner's D1/T113s SoCs family.
++ *
++ * Based on sun50i-codec-analog.c
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++/* Codec analog control register offsets and bit fields */
++#define SUN20I_D1_ADDA_ADC1			(0x00)
++#define SUN20I_D1_ADDA_ADC2			(0x04)
++#define SUN20I_D1_ADDA_ADC3			(0x08)
++#define SUN20I_D1_ADDA_ADC_EN				(31)
++#define SUN20I_D1_ADDA_ADC_PGA_EN			(30)
++#define SUN20I_D1_ADDA_ADC_MIC_SIN_EN			(28)
++#define SUN20I_D1_ADDA_ADC_LINEINLEN			(23)
++#define SUN20I_D1_ADDA_ADC_PGA_GAIN			(8)
++
++#define SUN20I_D1_ADDA_DAC			(0x10)
++#define SUN20I_D1_ADDA_DAC_DACL_EN			(15)
++#define SUN20I_D1_ADDA_DAC_DACR_EN			(14)
++
++#define SUN20I_D1_ADDA_MICBIAS			(0x18)
++#define SUN20I_D1_ADDA_MICBIAS_MMICBIASEN		(7)
++
++#define SUN20I_D1_ADDA_RAMP			(0x1C)
++#define SUN20I_D1_ADDA_RAMP_RD_EN			(0)
++
++#define SUN20I_D1_ADDA_HP2			(0x40)
++#define SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN		(28)
++
++#define SUN20I_D1_ADDA_ADC_CUR_REG		(0x4C)
++
++static const DECLARE_TLV_DB_RANGE(sun20i_d1_codec_adc_gain_scale,
++	0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
++	1, 3, TLV_DB_SCALE_ITEM(600, 0, 0),
++	4, 4, TLV_DB_SCALE_ITEM(900, 0, 0),
++	5, 31, TLV_DB_SCALE_ITEM(1000, 100, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_hp_vol_scale, -4200, 600, 0);
++
++/* volume controls */
++static const struct snd_kcontrol_new sun20i_d1_codec_controls[] = {
++	SOC_SINGLE_TLV("Headphone Playback Volume",
++		       SUN20I_D1_ADDA_HP2,
++		       SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN, 0x7, 1,
++		       sun20i_d1_codec_hp_vol_scale),
++	SOC_SINGLE_TLV("ADC1 Gain Capture Volume",
++		       SUN20I_D1_ADDA_ADC1,
++		       SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++		       sun20i_d1_codec_adc_gain_scale),
++	SOC_SINGLE_TLV("ADC2 Gain Capture Volume",
++		       SUN20I_D1_ADDA_ADC2,
++		       SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++		       sun20i_d1_codec_adc_gain_scale),
++	SOC_SINGLE_TLV("ADC3 Gain Capture Volume",
++		       SUN20I_D1_ADDA_ADC3,
++		       SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++		       sun20i_d1_codec_adc_gain_scale),
++};
++
++/* ADC mixer controls */
++static const struct snd_kcontrol_new sun20i_d1_codec_mixer_controls[] = {
++	SOC_DAPM_DOUBLE_R("Line In Switch",
++			  SUN20I_D1_ADDA_ADC1,
++			  SUN20I_D1_ADDA_ADC2,
++			  SUN20I_D1_ADDA_ADC_LINEINLEN, 1, 0),
++};
++
++static const char * const sun20i_d1_codec_mic3_src_enum_text[] = {
++	"Differential", "Single",
++};
++
++static SOC_ENUM_SINGLE_DECL(sun20i_d1_codec_mic3_src_enum,
++			    SUN20I_D1_ADDA_ADC3,
++			    SUN20I_D1_ADDA_ADC_MIC_SIN_EN,
++			    sun20i_d1_codec_mic3_src_enum_text);
++
++static const struct snd_kcontrol_new sun20i_d1_codec_mic3_input_src[] = {
++	SOC_DAPM_ENUM("MIC3 Source Capture Route",
++		      sun20i_d1_codec_mic3_src_enum),
++};
++
++static const struct snd_soc_dapm_widget sun20i_d1_codec_widgets[] = {
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", NULL, SUN20I_D1_ADDA_DAC,
++			 SUN20I_D1_ADDA_DAC_DACL_EN, 0),
++	SND_SOC_DAPM_DAC("Right DAC", NULL, SUN20I_D1_ADDA_DAC,
++			 SUN20I_D1_ADDA_DAC_DACR_EN, 0),
++	/* ADC */
++	SND_SOC_DAPM_ADC("ADC1", NULL, SUN20I_D1_ADDA_ADC1,
++			 SUN20I_D1_ADDA_ADC_EN, 0),
++	SND_SOC_DAPM_ADC("ADC2", NULL, SUN20I_D1_ADDA_ADC2,
++			 SUN20I_D1_ADDA_ADC_EN, 0),
++	SND_SOC_DAPM_ADC("ADC3", NULL, SUN20I_D1_ADDA_ADC3,
++			 SUN20I_D1_ADDA_ADC_EN, 0),
++
++	/* ADC Mixers */
++	SND_SOC_DAPM_MIXER("ADC1 Mixer", SND_SOC_NOPM, 0, 0,
++			   sun20i_d1_codec_mixer_controls,
++			   ARRAY_SIZE(sun20i_d1_codec_mixer_controls)),
++	SND_SOC_DAPM_MIXER("ADC2 Mixer", SND_SOC_NOPM, 0, 0,
++			   sun20i_d1_codec_mixer_controls,
++			   ARRAY_SIZE(sun20i_d1_codec_mixer_controls)),
++
++	/* Headphone */
++	SND_SOC_DAPM_OUTPUT("HP"),
++	SND_SOC_DAPM_SUPPLY("RAMP Enable", SUN20I_D1_ADDA_RAMP,
++			    SUN20I_D1_ADDA_RAMP_RD_EN, 0, NULL, 0),
++
++	/* Line input */
++	SND_SOC_DAPM_INPUT("LINEIN"),
++
++	/* Microphone input */
++	SND_SOC_DAPM_INPUT("MIC3"),
++
++	/* Microphone input path */
++	SND_SOC_DAPM_MUX("MIC3 Source Capture Route", SND_SOC_NOPM, 0, 0,
++			 sun20i_d1_codec_mic3_input_src),
++
++	SND_SOC_DAPM_PGA("Mic3 Amplifier", SUN20I_D1_ADDA_ADC3,
++			 SUN20I_D1_ADDA_ADC_PGA_EN, 0, NULL, 0),
++
++	/* Microphone Bias */
++	SND_SOC_DAPM_SUPPLY("MBIAS", SUN20I_D1_ADDA_MICBIAS,
++			    SUN20I_D1_ADDA_MICBIAS_MMICBIASEN, 0, NULL, 0),
++};
++
++static const struct snd_soc_dapm_route sun20i_d1_codec_routes[] = {
++	/* Headphone Routes */
++	{ "HP", NULL, "Left DAC" },
++	{ "HP", NULL, "Right DAC" },
++	{ "HP", NULL, "RAMP Enable" },
++
++	/* Line input Routes */
++	{ "ADC1", NULL, "ADC1 Mixer" },
++	{ "ADC2", NULL, "ADC2 Mixer" },
++	{ "ADC1 Mixer", "Line In Switch", "LINEIN" },
++	{ "ADC2 Mixer", "Line In Switch", "LINEIN" },
++
++	/* Microphone Routes */
++	{ "MIC3 Source Capture Route", "Differential", "MIC3" },
++	{ "MIC3 Source Capture Route", "Single", "MIC3" },
++	{ "Mic3 Amplifier", NULL, "MIC3 Source Capture Route" },
++	{ "ADC3", NULL, "Mic3 Amplifier" },
++};
++
++static const struct snd_soc_component_driver sun20i_d1_codec_analog_cmpnt_drv = {
++	.controls		= sun20i_d1_codec_controls,
++	.num_controls		= ARRAY_SIZE(sun20i_d1_codec_controls),
++	.dapm_widgets		= sun20i_d1_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(sun20i_d1_codec_widgets),
++	.dapm_routes		= sun20i_d1_codec_routes,
++	.num_dapm_routes	= ARRAY_SIZE(sun20i_d1_codec_routes),
++};
++
++static const struct of_device_id sun20i_d1_codec_analog_of_match[] = {
++	{
++		.compatible = "allwinner,sun20i-d1-codec-analog",
++	},
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun20i_d1_codec_analog_of_match);
++
++static const struct regmap_config sun20i_d1_codec_regmap_config = {
++	.reg_bits	= 32,
++	.reg_stride	= 4,
++	.val_bits	= 32,
++	.max_register	= SUN20I_D1_ADDA_ADC_CUR_REG,
++};
++
++static int sun20i_d1_codec_analog_probe(struct platform_device *pdev)
++{
++	struct regmap *regmap;
++	void __iomem *base;
++
++	base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(base)) {
++		dev_err(&pdev->dev, "Failed to map the registers\n");
++		return PTR_ERR(base);
++	}
++
++	regmap = devm_regmap_init_mmio(&pdev->dev, base,
++				       &sun20i_d1_codec_regmap_config);
++	if (IS_ERR(regmap)) {
++		dev_err(&pdev->dev, "Failed to create regmap\n");
++		return PTR_ERR(regmap);
++	}
++
++	return devm_snd_soc_register_component(&pdev->dev,
++					       &sun20i_d1_codec_analog_cmpnt_drv,
++					       NULL, 0);
++}
++
++static struct platform_driver sun20i_d1_codec_analog_driver = {
++	.driver = {
++		.name = "sun20i-d1-codec-analog",
++		.of_match_table = sun20i_d1_codec_analog_of_match,
++	},
++	.probe = sun20i_d1_codec_analog_probe,
++};
++module_platform_driver(sun20i_d1_codec_analog_driver);
++
++MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for D1");
++MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sun20i-d1-codec-analog");
diff --git a/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch
new file mode 100644
index 0000000000..06bd159998
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0011-dt-bindings-thermal-sun8i-Add-binding-for-D1-T113s-T.patch
@@ -0,0 +1,51 @@
+From 16728b748a44f1cea060a6ba57453c03e3745c1d Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:22 +0300
+Subject: [PATCH 11/14] dt-bindings: thermal: sun8i: Add binding for D1/T113s
+ THS controller
+
+Add a binding for D1/T113s thermal sensor controller.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml         | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
++++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+@@ -16,6 +16,7 @@ properties:
+       - allwinner,sun8i-a83t-ths
+       - allwinner,sun8i-h3-ths
+       - allwinner,sun8i-r40-ths
++      - allwinner,sun20i-d1-ths
+       - allwinner,sun50i-a64-ths
+       - allwinner,sun50i-a100-ths
+       - allwinner,sun50i-h5-ths
+@@ -61,6 +62,7 @@ allOf:
+         compatible:
+           contains:
+             enum:
++              - allwinner,sun20i-d1-ths
+               - allwinner,sun50i-a100-ths
+               - allwinner,sun50i-h6-ths
+ 
+@@ -84,7 +86,9 @@ allOf:
+       properties:
+         compatible:
+           contains:
+-            const: allwinner,sun8i-h3-ths
++            enum:
++              - allwinner,sun8i-h3-ths
++              - allwinner,sun20i-d1-ths
+ 
+     then:
+       properties:
+@@ -103,6 +107,7 @@ allOf:
+             enum:
+               - allwinner,sun8i-h3-ths
+               - allwinner,sun8i-r40-ths
++              - allwinner,sun20i-d1-ths
+               - allwinner,sun50i-a64-ths
+               - allwinner,sun50i-a100-ths
+               - allwinner,sun50i-h5-ths
diff --git a/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch
new file mode 100644
index 0000000000..a7ded59868
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0012-thermal-sun8i-Add-D1-T113s-THS-controller-support.patch
@@ -0,0 +1,45 @@
+From eb7e78f9e4bb9133898875afb0e0b9f09663e802 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:23 +0300
+Subject: [PATCH 12/14] thermal: sun8i: Add D1/T113s THS controller support
+
+This patch adds a thermal sensor controller support for the D1/T113s,
+which is similar to the one on H6, but with only one sensor and
+different scale and offset values.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
+ 	.calc_temp = sun8i_ths_calc_temp,
+ };
+ 
++static const struct ths_thermal_chip sun20i_d1_ths = {
++	.sensor_num = 1,
++	.has_bus_clk_reset = true,
++	.offset = 188552,
++	.scale = 673,
++	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++	.calibrate = sun50i_h6_ths_calibrate,
++	.init = sun50i_h6_thermal_init,
++	.irq_ack = sun50i_h6_irq_ack,
++	.calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
+ 	{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
diff --git a/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch
new file mode 100644
index 0000000000..f8318c8207
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0013-riscv-dts-allwinner-d1-Add-thermal-sensor.patch
@@ -0,0 +1,47 @@
+From 196423a17b92ef241766691b42dac0136342bdb5 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:24 +0300
+Subject: [PATCH 13/14] riscv: dts: allwinner: d1: Add thermal sensor
+
+This patch adds a thermal sensor controller node for the D1/T113s.
+Also it adds a THS calibration data cell to efuse node.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi      | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+@@ -166,6 +166,19 @@
+ 			#io-channel-cells = <1>;
+ 		};
+ 
++		ths: thermal-sensor@2009400 {
++			compatible = "allwinner,sun20i-d1-ths";
++			reg = <0x02009400 0x400>;
++			interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_THS>;
++			clock-names = "bus";
++			resets = <&ccu RST_BUS_THS>;
++			nvmem-cells = <&ths_calibration>;
++			nvmem-cell-names = "calibration";
++			status = "disabled";
++			#thermal-sensor-cells = <0>;
++		};
++
+ 		dmic: dmic@2031000 {
+ 			compatible = "allwinner,sun20i-d1-dmic",
+ 				     "allwinner,sun50i-h6-dmic";
+@@ -415,6 +428,10 @@
+ 			reg = <0x3006000 0x1000>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++
++			ths_calibration: thermal-sensor-calibration@14 {
++				reg = <0x14 0x4>;
++			};
+ 		};
+ 
+ 		crypto: crypto@3040000 {
diff --git a/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch
new file mode 100644
index 0000000000..14a4c3c131
--- /dev/null
+++ b/target/linux/d1/patches-6.6/0014-riscv-dts-allwinner-d1-Add-device-nodes-for-internal.patch
@@ -0,0 +1,44 @@
+From edebcc9d47f0bfe9bd769a2c578dda16acbfbef2 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:05 +0300
+Subject: [PATCH 14/14] riscv: dts: allwinner: d1: Add device nodes for
+ internal audio codec
+
+Add DT nodes for the internal D1/T113s audio codec and its analog part.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+@@ -179,6 +179,28 @@
+ 			#thermal-sensor-cells = <0>;
+ 		};
+ 
++		codec: codec@2030000 {
++			#sound-dai-cells = <0>;
++			compatible = "allwinner,sun20i-d1-codec";
++			reg = <0x02030000 0x300>;
++			interrupts = <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_AUDIO>,
++				 <&ccu CLK_AUDIO_ADC>,
++				 <&ccu CLK_AUDIO_DAC>;
++			clock-names = "apb", "adc", "dac";
++			resets = <&ccu RST_BUS_AUDIO>;
++			dmas = <&dma 7>, <&dma 7>;
++			dma-names = "rx", "tx";
++			allwinner,codec-analog-controls = <&codec_analog>;
++			status = "disabled";
++		};
++
++		codec_analog: codec-analog@2030300 {
++			compatible = "allwinner,sun20i-d1-codec-analog";
++			reg = <0x02030300 0xd00>;
++			status = "disabled";
++		};
++
+ 		dmic: dmic@2031000 {
+ 			compatible = "allwinner,sun20i-d1-dmic",
+ 				     "allwinner,sun50i-h6-dmic";
diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile
index b7f1962c9a..b2869ff72e 100644
--- a/target/linux/gemini/Makefile
+++ b/target/linux/gemini/Makefile
@@ -11,7 +11,7 @@ FEATURES:=squashfs pci rtc usb dt gpio display ext4 rootfs-part boot-part
 CPU_TYPE:=fa526
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU
diff --git a/target/linux/gemini/config-6.1 b/target/linux/gemini/config-6.1
deleted file mode 100644
index ae0922f5dc..0000000000
--- a/target/linux/gemini/config-6.1
+++ /dev/null
@@ -1,451 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AMBA_PL08X=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_GEMINI=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MOXART is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-# CONFIG_ARCH_MULTI_V5 is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_PERCENTAGE=10
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-# CONFIG_CMA_SIZE_SEL_MBYTES is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_GEMINI=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4=y
-CONFIG_CPU_CACHE_FA=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_FA=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_FA526=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_NO_EFFICIENT_FFS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_TLB_FA=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_SL3516=y
-# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_DMA_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_NOMODESET=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ILITEK_IL9322=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TVE200=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_93CX6=y
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-# CONFIG_EXPERT is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FARADAY_FTINTC010=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FTTMR010_TIMER=y
-CONFIG_FTWDT010_WATCHDOG=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GEMINI_ETHERNET=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_FTGPIO010=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDMI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KERNEL_LZMA=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_DLINK_DIR685=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-# CONFIG_LDM_DEBUG is not set
-CONFIG_LDM_PARTITION=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_GEMINI=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_REALTEK=y
-# CONFIG_NET_DSA_REALTEK_MDIO is not set
-# CONFIG_NET_DSA_REALTEK_RTL8365MB is not set
-CONFIG_NET_DSA_REALTEK_RTL8366RB=y
-CONFIG_NET_DSA_REALTEK_SMI=y
-CONFIG_NET_DSA_TAG_RTL4_A=y
-CONFIG_NET_NS=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PATA_FTIDE010=y
-CONFIG_PCI=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_FTPCI100=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_GEMINI=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GEMINI_POWEROFF=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_FTRTC010=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_NVMEM=y
-CONFIG_SATA_GEMINI=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SENSORS_DRIVETEMP=y
-CONFIG_SENSORS_GPIO_FAN=y
-CONFIG_SENSORS_LM75=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACKTRACE=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_FOTG210 is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USER_NS=y
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VITESSE_PHY=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/gemini/config-6.6 b/target/linux/gemini/config-6.6
new file mode 100644
index 0000000000..d670279135
--- /dev/null
+++ b/target/linux/gemini/config-6.6
@@ -0,0 +1,468 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMBA_PL08X=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_GEMINI=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MOXART is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+# CONFIG_ARCH_MULTI_V5 is not set
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_PERCENTAGE=10
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+# CONFIG_CMA_SIZE_SEL_MBYTES is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_GEMINI=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_CACHE_FA=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FA=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_FA526=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_FA=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_DEV_JH7110 is not set
+CONFIG_CRYPTO_DEV_SL3516=y
+# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_USER=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ILITEK_IL9322=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_TVE200=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_EXPERT is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FARADAY_FTINTC010=y
+CONFIG_FB=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTTMR010_TIMER=y
+CONFIG_FTWDT010_WATCHDOG=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GEMINI_ETHERNET=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_IO_URING=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_DLINK_DIR685=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_GEMINI=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_REALTEK=y
+# CONFIG_NET_DSA_REALTEK_MDIO is not set
+# CONFIG_NET_DSA_REALTEK_RTL8365MB is not set
+CONFIG_NET_DSA_REALTEK_RTL8366RB=y
+CONFIG_NET_DSA_REALTEK_SMI=y
+CONFIG_NET_DSA_TAG_RTL4_A=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PATA_FTIDE010=y
+CONFIG_PCI=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GEMINI=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GEMINI_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_FTRTC010=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTC_NVMEM=y
+CONFIG_SATA_GEMINI=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SENSORS_DRIVETEMP=y
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKTRACE=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_FOTG210 is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile
index 3fce3172ed..3ddb6e5554 100644
--- a/target/linux/gemini/image/Makefile
+++ b/target/linux/gemini/image/Makefile
@@ -124,6 +124,7 @@ endef
 # All DTB files are prefixed with "gemini-"
 define Device/Default
 	PROFILES := Default
+	DEVICE_DTS_DIR = $$(DTS_DIR)/gemini
 	KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
 	KERNEL_NAME := zImage
 	KERNEL := kernel-bin | append-dtb
diff --git a/target/linux/gemini/patches-6.1/0001-usb-phy-phy-gpio-vbus-usb-Add-device-tree-probing.patch b/target/linux/gemini/patches-6.1/0001-usb-phy-phy-gpio-vbus-usb-Add-device-tree-probing.patch
deleted file mode 100644
index 943b166d7e..0000000000
--- a/target/linux/gemini/patches-6.1/0001-usb-phy-phy-gpio-vbus-usb-Add-device-tree-probing.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From d5a026cc8306ccd3e99e1455c87e38f8e6fa18df Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 7 Nov 2022 00:05:06 +0100
-Subject: [PATCH 01/29] usb: phy: phy-gpio-vbus-usb: Add device tree probing
-
-Make it possible to probe the GPIO VBUS detection driver
-from the device tree compatible for GPIO USB B connectors.
-
-Since this driver is using the "gpio-usb-b-connector"
-compatible, it is important to discern it from the role
-switch connector driver (which does not provide a phy),
-so we add some Kconfig text and depend on !USB_CONN_GPIO.
-
-Cc: Rob Herring <robh@kernel.org>
-Cc: Prashant Malani <pmalani@chromium.org>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221106230506.1646101-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/phy/Kconfig
-+++ b/drivers/usb/phy/Kconfig
-@@ -93,12 +93,16 @@ config USB_GPIO_VBUS
- 	tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
- 	depends on GPIOLIB || COMPILE_TEST
- 	depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
-+	depends on !USB_CONN_GPIO
- 	select USB_PHY
- 	help
- 	  Provides simple GPIO VBUS sensing for controllers with an
- 	  internal transceiver via the usb_phy interface, and
- 	  optionally control of a D+ pullup GPIO as well as a VBUS
--	  current limit regulator.
-+	  current limit regulator. This driver is for devices that do
-+	  NOT support role switch. OTG devices that can do role switch
-+	  (master/peripheral) shall use the USB based connection
-+	  detection driver USB_CONN_GPIO.
- 
- config OMAP_OTG
- 	tristate "OMAP USB OTG controller driver"
---- a/drivers/usb/phy/phy-gpio-vbus-usb.c
-+++ b/drivers/usb/phy/phy-gpio-vbus-usb.c
-@@ -366,12 +366,24 @@ static const struct dev_pm_ops gpio_vbus
- 
- MODULE_ALIAS("platform:gpio-vbus");
- 
-+/*
-+ * NOTE: this driver matches against "gpio-usb-b-connector" for
-+ * devices that do NOT support role switch.
-+ */
-+static const struct of_device_id gpio_vbus_of_match[] = {
-+	{
-+		.compatible = "gpio-usb-b-connector",
-+	},
-+	{},
-+};
-+
- static struct platform_driver gpio_vbus_driver = {
- 	.driver = {
- 		.name  = "gpio-vbus",
- #ifdef CONFIG_PM
- 		.pm = &gpio_vbus_dev_pm_ops,
- #endif
-+		.of_match_table = gpio_vbus_of_match,
- 	},
- 	.probe		= gpio_vbus_probe,
- 	.remove		= gpio_vbus_remove,
diff --git a/target/linux/gemini/patches-6.1/0002-usb-fotg210-Collect-pieces-of-dual-mode-controller.patch b/target/linux/gemini/patches-6.1/0002-usb-fotg210-Collect-pieces-of-dual-mode-controller.patch
deleted file mode 100644
index 1ee4f27c46..0000000000
--- a/target/linux/gemini/patches-6.1/0002-usb-fotg210-Collect-pieces-of-dual-mode-controller.patch
+++ /dev/null
@@ -1,15990 +0,0 @@
-From 30367636930864f71b2bd462adedcf8484313864 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:06 +0200
-Subject: [PATCH 02/29] usb: fotg210: Collect pieces of dual mode controller
-
-The Faraday FOTG210 is a dual-mode OTG USB controller that can
-act as host, peripheral or both. To be able to probe from one
-hardware description and to follow the pattern of other dual-
-mode controllers such as MUSB or MTU3 we need to collect the
-two, currently completely separate drivers in the same
-directory.
-
-After this, users need to select the main symbol USB_FOTG210
-and then each respective subdriver. We pave the road to
-compile both drivers into the same kernel and select the
-one we want to use at probe() time, and possibly add OTG
-support in the end.
-
-This patch doesn't do much more than create the new symbol
-and collect the drivers in one place. We also add a comment
-for the section of dual-mode controllers in the Kconfig
-file so people can see what these selections are about.
-
-Also add myself as maintainer as there has been little
-response on my patches to these drivers.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -111,8 +111,12 @@ source "drivers/usb/usbip/Kconfig"
- 
- endif
- 
-+comment "USB dual-mode controller drivers"
-+
- source "drivers/usb/cdns3/Kconfig"
- 
-+source "drivers/usb/fotg210/Kconfig"
-+
- source "drivers/usb/mtu3/Kconfig"
- 
- source "drivers/usb/musb/Kconfig"
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -17,6 +17,8 @@ obj-$(CONFIG_USB_CDNS_SUPPORT)	+= cdns3/
- obj-$(CONFIG_USB_CDNS3)		+= cdns3/
- obj-$(CONFIG_USB_CDNSP_PCI)	+= cdns3/
- 
-+obj-$(CONFIG_USB_FOTG210)	+= fotg210/
-+
- obj-$(CONFIG_USB_MON)		+= mon/
- obj-$(CONFIG_USB_MTU3)		+= mtu3/
- 
---- /dev/null
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -0,0 +1,36 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+config USB_FOTG210
-+	tristate "Faraday FOTG210 USB2 Dual Role controller"
-+	depends on USB || USB_GADGET
-+	depends on HAS_DMA && HAS_IOMEM
-+	default ARCH_GEMINI
-+	help
-+	  Faraday FOTG210 is a dual-mode USB controller that can act
-+	  in both host controller and peripheral controller mode.
-+
-+if USB_FOTG210
-+
-+config USB_FOTG210_HCD
-+	tristate "Faraday FOTG210 USB Host Controller support"
-+	depends on USB
-+	help
-+	  Faraday FOTG210 is an OTG controller which can be configured as
-+	  an USB2.0 host. It is designed to meet USB2.0 EHCI specification
-+	  with minor modification.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called fotg210-hcd.
-+
-+config USB_FOTG210_UDC
-+	depends on USB_GADGET
-+	tristate "Faraday FOTG210 USB Peripheral Controller support"
-+	help
-+	   Faraday USB2.0 OTG controller which can be configured as
-+	   high speed or full speed USB device. This driver suppports
-+	   Bulk Transfer so far.
-+
-+	   Say "y" to link the driver statically, or "m" to build a
-+	   dynamically linked module called "fotg210-udc".
-+
-+endif
---- /dev/null
-+++ b/drivers/usb/fotg210/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0
-+obj-$(CONFIG_USB_FOTG210_HCD)	+= fotg210-hcd.o
-+obj-$(CONFIG_USB_FOTG210_UDC)	+= fotg210-udc.o
---- a/drivers/usb/host/fotg210-hcd.c
-+++ /dev/null
-@@ -1,5724 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0+
--/* Faraday FOTG210 EHCI-like driver
-- *
-- * Copyright (c) 2013 Faraday Technology Corporation
-- *
-- * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- *	   Feng-Hsin Chiang <john453@faraday-tech.com>
-- *	   Po-Yu Chuang <ratbert.chuang@gmail.com>
-- *
-- * Most of code borrowed from the Linux-3.7 EHCI driver
-- */
--#include <linux/module.h>
--#include <linux/of.h>
--#include <linux/device.h>
--#include <linux/dmapool.h>
--#include <linux/kernel.h>
--#include <linux/delay.h>
--#include <linux/ioport.h>
--#include <linux/sched.h>
--#include <linux/vmalloc.h>
--#include <linux/errno.h>
--#include <linux/init.h>
--#include <linux/hrtimer.h>
--#include <linux/list.h>
--#include <linux/interrupt.h>
--#include <linux/usb.h>
--#include <linux/usb/hcd.h>
--#include <linux/moduleparam.h>
--#include <linux/dma-mapping.h>
--#include <linux/debugfs.h>
--#include <linux/slab.h>
--#include <linux/uaccess.h>
--#include <linux/platform_device.h>
--#include <linux/io.h>
--#include <linux/iopoll.h>
--#include <linux/clk.h>
--
--#include <asm/byteorder.h>
--#include <asm/irq.h>
--#include <asm/unaligned.h>
--
--#define DRIVER_AUTHOR "Yuan-Hsin Chen"
--#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
--static const char hcd_name[] = "fotg210_hcd";
--
--#undef FOTG210_URB_TRACE
--#define FOTG210_STATS
--
--/* magic numbers that can affect system performance */
--#define FOTG210_TUNE_CERR	3 /* 0-3 qtd retries; 0 == don't stop */
--#define FOTG210_TUNE_RL_HS	4 /* nak throttle; see 4.9 */
--#define FOTG210_TUNE_RL_TT	0
--#define FOTG210_TUNE_MULT_HS	1 /* 1-3 transactions/uframe; 4.10.3 */
--#define FOTG210_TUNE_MULT_TT	1
--
--/* Some drivers think it's safe to schedule isochronous transfers more than 256
-- * ms into the future (partly as a result of an old bug in the scheduling
-- * code).  In an attempt to avoid trouble, we will use a minimum scheduling
-- * length of 512 frames instead of 256.
-- */
--#define FOTG210_TUNE_FLS 1 /* (medium) 512-frame schedule */
--
--/* Initial IRQ latency:  faster than hw default */
--static int log2_irq_thresh; /* 0 to 6 */
--module_param(log2_irq_thresh, int, S_IRUGO);
--MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
--
--/* initial park setting:  slower than hw default */
--static unsigned park;
--module_param(park, uint, S_IRUGO);
--MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
--
--/* for link power management(LPM) feature */
--static unsigned int hird;
--module_param(hird, int, S_IRUGO);
--MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
--
--#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
--
--#include "fotg210.h"
--
--#define fotg210_dbg(fotg210, fmt, args...) \
--	dev_dbg(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_err(fotg210, fmt, args...) \
--	dev_err(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_info(fotg210, fmt, args...) \
--	dev_info(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_warn(fotg210, fmt, args...) \
--	dev_warn(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--
--/* check the values in the HCSPARAMS register (host controller _Structural_
-- * parameters) see EHCI spec, Table 2-4 for each value
-- */
--static void dbg_hcs_params(struct fotg210_hcd *fotg210, char *label)
--{
--	u32 params = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
--
--	fotg210_dbg(fotg210, "%s hcs_params 0x%x ports=%d\n", label, params,
--			HCS_N_PORTS(params));
--}
--
--/* check the values in the HCCPARAMS register (host controller _Capability_
-- * parameters) see EHCI Spec, Table 2-5 for each value
-- */
--static void dbg_hcc_params(struct fotg210_hcd *fotg210, char *label)
--{
--	u32 params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
--	fotg210_dbg(fotg210, "%s hcc_params %04x uframes %s%s\n", label,
--			params,
--			HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
--			HCC_CANPARK(params) ? " park" : "");
--}
--
--static void __maybe_unused
--dbg_qtd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd)
--{
--	fotg210_dbg(fotg210, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
--			hc32_to_cpup(fotg210, &qtd->hw_next),
--			hc32_to_cpup(fotg210, &qtd->hw_alt_next),
--			hc32_to_cpup(fotg210, &qtd->hw_token),
--			hc32_to_cpup(fotg210, &qtd->hw_buf[0]));
--	if (qtd->hw_buf[1])
--		fotg210_dbg(fotg210, "  p1=%08x p2=%08x p3=%08x p4=%08x\n",
--				hc32_to_cpup(fotg210, &qtd->hw_buf[1]),
--				hc32_to_cpup(fotg210, &qtd->hw_buf[2]),
--				hc32_to_cpup(fotg210, &qtd->hw_buf[3]),
--				hc32_to_cpup(fotg210, &qtd->hw_buf[4]));
--}
--
--static void __maybe_unused
--dbg_qh(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	struct fotg210_qh_hw *hw = qh->hw;
--
--	fotg210_dbg(fotg210, "%s qh %p n%08x info %x %x qtd %x\n", label, qh,
--			hw->hw_next, hw->hw_info1, hw->hw_info2,
--			hw->hw_current);
--
--	dbg_qtd("overlay", fotg210, (struct fotg210_qtd *) &hw->hw_qtd_next);
--}
--
--static void __maybe_unused
--dbg_itd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
--{
--	fotg210_dbg(fotg210, "%s[%d] itd %p, next %08x, urb %p\n", label,
--			itd->frame, itd, hc32_to_cpu(fotg210, itd->hw_next),
--			itd->urb);
--
--	fotg210_dbg(fotg210,
--			"  trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
--			hc32_to_cpu(fotg210, itd->hw_transaction[0]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[1]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[2]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[3]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[4]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[5]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[6]),
--			hc32_to_cpu(fotg210, itd->hw_transaction[7]));
--
--	fotg210_dbg(fotg210,
--			"  buf:   %08x %08x %08x %08x %08x %08x %08x\n",
--			hc32_to_cpu(fotg210, itd->hw_bufp[0]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[1]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[2]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[3]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[4]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[5]),
--			hc32_to_cpu(fotg210, itd->hw_bufp[6]));
--
--	fotg210_dbg(fotg210, "  index: %d %d %d %d %d %d %d %d\n",
--			itd->index[0], itd->index[1], itd->index[2],
--			itd->index[3], itd->index[4], itd->index[5],
--			itd->index[6], itd->index[7]);
--}
--
--static int __maybe_unused
--dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
--{
--	return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
--			label, label[0] ? " " : "", status,
--			(status & STS_ASS) ? " Async" : "",
--			(status & STS_PSS) ? " Periodic" : "",
--			(status & STS_RECL) ? " Recl" : "",
--			(status & STS_HALT) ? " Halt" : "",
--			(status & STS_IAA) ? " IAA" : "",
--			(status & STS_FATAL) ? " FATAL" : "",
--			(status & STS_FLR) ? " FLR" : "",
--			(status & STS_PCD) ? " PCD" : "",
--			(status & STS_ERR) ? " ERR" : "",
--			(status & STS_INT) ? " INT" : "");
--}
--
--static int __maybe_unused
--dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
--{
--	return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
--			label, label[0] ? " " : "", enable,
--			(enable & STS_IAA) ? " IAA" : "",
--			(enable & STS_FATAL) ? " FATAL" : "",
--			(enable & STS_FLR) ? " FLR" : "",
--			(enable & STS_PCD) ? " PCD" : "",
--			(enable & STS_ERR) ? " ERR" : "",
--			(enable & STS_INT) ? " INT" : "");
--}
--
--static const char *const fls_strings[] = { "1024", "512", "256", "??" };
--
--static int dbg_command_buf(char *buf, unsigned len, const char *label,
--		u32 command)
--{
--	return scnprintf(buf, len,
--			"%s%scommand %07x %s=%d ithresh=%d%s%s%s period=%s%s %s",
--			label, label[0] ? " " : "", command,
--			(command & CMD_PARK) ? " park" : "(park)",
--			CMD_PARK_CNT(command),
--			(command >> 16) & 0x3f,
--			(command & CMD_IAAD) ? " IAAD" : "",
--			(command & CMD_ASE) ? " Async" : "",
--			(command & CMD_PSE) ? " Periodic" : "",
--			fls_strings[(command >> 2) & 0x3],
--			(command & CMD_RESET) ? " Reset" : "",
--			(command & CMD_RUN) ? "RUN" : "HALT");
--}
--
--static char *dbg_port_buf(char *buf, unsigned len, const char *label, int port,
--		u32 status)
--{
--	char *sig;
--
--	/* signaling state */
--	switch (status & (3 << 10)) {
--	case 0 << 10:
--		sig = "se0";
--		break;
--	case 1 << 10:
--		sig = "k";
--		break; /* low speed */
--	case 2 << 10:
--		sig = "j";
--		break;
--	default:
--		sig = "?";
--		break;
--	}
--
--	scnprintf(buf, len, "%s%sport:%d status %06x %d sig=%s%s%s%s%s%s%s%s",
--			label, label[0] ? " " : "", port, status,
--			status >> 25, /*device address */
--			sig,
--			(status & PORT_RESET) ? " RESET" : "",
--			(status & PORT_SUSPEND) ? " SUSPEND" : "",
--			(status & PORT_RESUME) ? " RESUME" : "",
--			(status & PORT_PEC) ? " PEC" : "",
--			(status & PORT_PE) ? " PE" : "",
--			(status & PORT_CSC) ? " CSC" : "",
--			(status & PORT_CONNECT) ? " CONNECT" : "");
--
--	return buf;
--}
--
--/* functions have the "wrong" filename when they're output... */
--#define dbg_status(fotg210, label, status) {			\
--	char _buf[80];						\
--	dbg_status_buf(_buf, sizeof(_buf), label, status);	\
--	fotg210_dbg(fotg210, "%s\n", _buf);			\
--}
--
--#define dbg_cmd(fotg210, label, command) {			\
--	char _buf[80];						\
--	dbg_command_buf(_buf, sizeof(_buf), label, command);	\
--	fotg210_dbg(fotg210, "%s\n", _buf);			\
--}
--
--#define dbg_port(fotg210, label, port, status) {			       \
--	char _buf[80];							       \
--	fotg210_dbg(fotg210, "%s\n",					       \
--			dbg_port_buf(_buf, sizeof(_buf), label, port, status));\
--}
--
--/* troubleshooting help: expose state in debugfs */
--static int debug_async_open(struct inode *, struct file *);
--static int debug_periodic_open(struct inode *, struct file *);
--static int debug_registers_open(struct inode *, struct file *);
--static int debug_async_open(struct inode *, struct file *);
--
--static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
--static int debug_close(struct inode *, struct file *);
--
--static const struct file_operations debug_async_fops = {
--	.owner		= THIS_MODULE,
--	.open		= debug_async_open,
--	.read		= debug_output,
--	.release	= debug_close,
--	.llseek		= default_llseek,
--};
--static const struct file_operations debug_periodic_fops = {
--	.owner		= THIS_MODULE,
--	.open		= debug_periodic_open,
--	.read		= debug_output,
--	.release	= debug_close,
--	.llseek		= default_llseek,
--};
--static const struct file_operations debug_registers_fops = {
--	.owner		= THIS_MODULE,
--	.open		= debug_registers_open,
--	.read		= debug_output,
--	.release	= debug_close,
--	.llseek		= default_llseek,
--};
--
--static struct dentry *fotg210_debug_root;
--
--struct debug_buffer {
--	ssize_t (*fill_func)(struct debug_buffer *);	/* fill method */
--	struct usb_bus *bus;
--	struct mutex mutex;	/* protect filling of buffer */
--	size_t count;		/* number of characters filled into buffer */
--	char *output_buf;
--	size_t alloc_size;
--};
--
--static inline char speed_char(u32 scratch)
--{
--	switch (scratch & (3 << 12)) {
--	case QH_FULL_SPEED:
--		return 'f';
--
--	case QH_LOW_SPEED:
--		return 'l';
--
--	case QH_HIGH_SPEED:
--		return 'h';
--
--	default:
--		return '?';
--	}
--}
--
--static inline char token_mark(struct fotg210_hcd *fotg210, __hc32 token)
--{
--	__u32 v = hc32_to_cpu(fotg210, token);
--
--	if (v & QTD_STS_ACTIVE)
--		return '*';
--	if (v & QTD_STS_HALT)
--		return '-';
--	if (!IS_SHORT_READ(v))
--		return ' ';
--	/* tries to advance through hw_alt_next */
--	return '/';
--}
--
--static void qh_lines(struct fotg210_hcd *fotg210, struct fotg210_qh *qh,
--		char **nextp, unsigned *sizep)
--{
--	u32 scratch;
--	u32 hw_curr;
--	struct fotg210_qtd *td;
--	unsigned temp;
--	unsigned size = *sizep;
--	char *next = *nextp;
--	char mark;
--	__le32 list_end = FOTG210_LIST_END(fotg210);
--	struct fotg210_qh_hw *hw = qh->hw;
--
--	if (hw->hw_qtd_next == list_end) /* NEC does this */
--		mark = '@';
--	else
--		mark = token_mark(fotg210, hw->hw_token);
--	if (mark == '/') { /* qh_alt_next controls qh advance? */
--		if ((hw->hw_alt_next & QTD_MASK(fotg210)) ==
--		    fotg210->async->hw->hw_alt_next)
--			mark = '#'; /* blocked */
--		else if (hw->hw_alt_next == list_end)
--			mark = '.'; /* use hw_qtd_next */
--		/* else alt_next points to some other qtd */
--	}
--	scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
--	hw_curr = (mark == '*') ? hc32_to_cpup(fotg210, &hw->hw_current) : 0;
--	temp = scnprintf(next, size,
--			"qh/%p dev%d %cs ep%d %08x %08x(%08x%c %s nak%d)",
--			qh, scratch & 0x007f,
--			speed_char(scratch),
--			(scratch >> 8) & 0x000f,
--			scratch, hc32_to_cpup(fotg210, &hw->hw_info2),
--			hc32_to_cpup(fotg210, &hw->hw_token), mark,
--			(cpu_to_hc32(fotg210, QTD_TOGGLE) & hw->hw_token)
--				? "data1" : "data0",
--			(hc32_to_cpup(fotg210, &hw->hw_alt_next) >> 1) & 0x0f);
--	size -= temp;
--	next += temp;
--
--	/* hc may be modifying the list as we read it ... */
--	list_for_each_entry(td, &qh->qtd_list, qtd_list) {
--		scratch = hc32_to_cpup(fotg210, &td->hw_token);
--		mark = ' ';
--		if (hw_curr == td->qtd_dma)
--			mark = '*';
--		else if (hw->hw_qtd_next == cpu_to_hc32(fotg210, td->qtd_dma))
--			mark = '+';
--		else if (QTD_LENGTH(scratch)) {
--			if (td->hw_alt_next == fotg210->async->hw->hw_alt_next)
--				mark = '#';
--			else if (td->hw_alt_next != list_end)
--				mark = '/';
--		}
--		temp = snprintf(next, size,
--				"\n\t%p%c%s len=%d %08x urb %p",
--				td, mark, ({ char *tmp;
--				switch ((scratch>>8)&0x03) {
--				case 0:
--					tmp = "out";
--					break;
--				case 1:
--					tmp = "in";
--					break;
--				case 2:
--					tmp = "setup";
--					break;
--				default:
--					tmp = "?";
--					break;
--				 } tmp; }),
--				(scratch >> 16) & 0x7fff,
--				scratch,
--				td->urb);
--		if (size < temp)
--			temp = size;
--		size -= temp;
--		next += temp;
--	}
--
--	temp = snprintf(next, size, "\n");
--	if (size < temp)
--		temp = size;
--
--	size -= temp;
--	next += temp;
--
--	*sizep = size;
--	*nextp = next;
--}
--
--static ssize_t fill_async_buffer(struct debug_buffer *buf)
--{
--	struct usb_hcd *hcd;
--	struct fotg210_hcd *fotg210;
--	unsigned long flags;
--	unsigned temp, size;
--	char *next;
--	struct fotg210_qh *qh;
--
--	hcd = bus_to_hcd(buf->bus);
--	fotg210 = hcd_to_fotg210(hcd);
--	next = buf->output_buf;
--	size = buf->alloc_size;
--
--	*next = 0;
--
--	/* dumps a snapshot of the async schedule.
--	 * usually empty except for long-term bulk reads, or head.
--	 * one QH per line, and TDs we know about
--	 */
--	spin_lock_irqsave(&fotg210->lock, flags);
--	for (qh = fotg210->async->qh_next.qh; size > 0 && qh;
--			qh = qh->qh_next.qh)
--		qh_lines(fotg210, qh, &next, &size);
--	if (fotg210->async_unlink && size > 0) {
--		temp = scnprintf(next, size, "\nunlink =\n");
--		size -= temp;
--		next += temp;
--
--		for (qh = fotg210->async_unlink; size > 0 && qh;
--				qh = qh->unlink_next)
--			qh_lines(fotg210, qh, &next, &size);
--	}
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--
--	return strlen(buf->output_buf);
--}
--
--/* count tds, get ep direction */
--static unsigned output_buf_tds_dir(char *buf, struct fotg210_hcd *fotg210,
--		struct fotg210_qh_hw *hw, struct fotg210_qh *qh, unsigned size)
--{
--	u32 scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
--	struct fotg210_qtd *qtd;
--	char *type = "";
--	unsigned temp = 0;
--
--	/* count tds, get ep direction */
--	list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
--		temp++;
--		switch ((hc32_to_cpu(fotg210, qtd->hw_token) >> 8) & 0x03) {
--		case 0:
--			type = "out";
--			continue;
--		case 1:
--			type = "in";
--			continue;
--		}
--	}
--
--	return scnprintf(buf, size, "(%c%d ep%d%s [%d/%d] q%d p%d)",
--			speed_char(scratch), scratch & 0x007f,
--			(scratch >> 8) & 0x000f, type, qh->usecs,
--			qh->c_usecs, temp, (scratch >> 16) & 0x7ff);
--}
--
--#define DBG_SCHED_LIMIT 64
--static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
--{
--	struct usb_hcd *hcd;
--	struct fotg210_hcd *fotg210;
--	unsigned long flags;
--	union fotg210_shadow p, *seen;
--	unsigned temp, size, seen_count;
--	char *next;
--	unsigned i;
--	__hc32 tag;
--
--	seen = kmalloc_array(DBG_SCHED_LIMIT, sizeof(*seen), GFP_ATOMIC);
--	if (!seen)
--		return 0;
--
--	seen_count = 0;
--
--	hcd = bus_to_hcd(buf->bus);
--	fotg210 = hcd_to_fotg210(hcd);
--	next = buf->output_buf;
--	size = buf->alloc_size;
--
--	temp = scnprintf(next, size, "size = %d\n", fotg210->periodic_size);
--	size -= temp;
--	next += temp;
--
--	/* dump a snapshot of the periodic schedule.
--	 * iso changes, interrupt usually doesn't.
--	 */
--	spin_lock_irqsave(&fotg210->lock, flags);
--	for (i = 0; i < fotg210->periodic_size; i++) {
--		p = fotg210->pshadow[i];
--		if (likely(!p.ptr))
--			continue;
--
--		tag = Q_NEXT_TYPE(fotg210, fotg210->periodic[i]);
--
--		temp = scnprintf(next, size, "%4d: ", i);
--		size -= temp;
--		next += temp;
--
--		do {
--			struct fotg210_qh_hw *hw;
--
--			switch (hc32_to_cpu(fotg210, tag)) {
--			case Q_TYPE_QH:
--				hw = p.qh->hw;
--				temp = scnprintf(next, size, " qh%d-%04x/%p",
--						p.qh->period,
--						hc32_to_cpup(fotg210,
--							&hw->hw_info2)
--							/* uframe masks */
--							& (QH_CMASK | QH_SMASK),
--						p.qh);
--				size -= temp;
--				next += temp;
--				/* don't repeat what follows this qh */
--				for (temp = 0; temp < seen_count; temp++) {
--					if (seen[temp].ptr != p.ptr)
--						continue;
--					if (p.qh->qh_next.ptr) {
--						temp = scnprintf(next, size,
--								" ...");
--						size -= temp;
--						next += temp;
--					}
--					break;
--				}
--				/* show more info the first time around */
--				if (temp == seen_count) {
--					temp = output_buf_tds_dir(next,
--							fotg210, hw,
--							p.qh, size);
--
--					if (seen_count < DBG_SCHED_LIMIT)
--						seen[seen_count++].qh = p.qh;
--				} else
--					temp = 0;
--				tag = Q_NEXT_TYPE(fotg210, hw->hw_next);
--				p = p.qh->qh_next;
--				break;
--			case Q_TYPE_FSTN:
--				temp = scnprintf(next, size,
--						" fstn-%8x/%p",
--						p.fstn->hw_prev, p.fstn);
--				tag = Q_NEXT_TYPE(fotg210, p.fstn->hw_next);
--				p = p.fstn->fstn_next;
--				break;
--			case Q_TYPE_ITD:
--				temp = scnprintf(next, size,
--						" itd/%p", p.itd);
--				tag = Q_NEXT_TYPE(fotg210, p.itd->hw_next);
--				p = p.itd->itd_next;
--				break;
--			}
--			size -= temp;
--			next += temp;
--		} while (p.ptr);
--
--		temp = scnprintf(next, size, "\n");
--		size -= temp;
--		next += temp;
--	}
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	kfree(seen);
--
--	return buf->alloc_size - size;
--}
--#undef DBG_SCHED_LIMIT
--
--static const char *rh_state_string(struct fotg210_hcd *fotg210)
--{
--	switch (fotg210->rh_state) {
--	case FOTG210_RH_HALTED:
--		return "halted";
--	case FOTG210_RH_SUSPENDED:
--		return "suspended";
--	case FOTG210_RH_RUNNING:
--		return "running";
--	case FOTG210_RH_STOPPING:
--		return "stopping";
--	}
--	return "?";
--}
--
--static ssize_t fill_registers_buffer(struct debug_buffer *buf)
--{
--	struct usb_hcd *hcd;
--	struct fotg210_hcd *fotg210;
--	unsigned long flags;
--	unsigned temp, size, i;
--	char *next, scratch[80];
--	static const char fmt[] = "%*s\n";
--	static const char label[] = "";
--
--	hcd = bus_to_hcd(buf->bus);
--	fotg210 = hcd_to_fotg210(hcd);
--	next = buf->output_buf;
--	size = buf->alloc_size;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	if (!HCD_HW_ACCESSIBLE(hcd)) {
--		size = scnprintf(next, size,
--				"bus %s, device %s\n"
--				"%s\n"
--				"SUSPENDED(no register access)\n",
--				hcd->self.controller->bus->name,
--				dev_name(hcd->self.controller),
--				hcd->product_desc);
--		goto done;
--	}
--
--	/* Capability Registers */
--	i = HC_VERSION(fotg210, fotg210_readl(fotg210,
--			&fotg210->caps->hc_capbase));
--	temp = scnprintf(next, size,
--			"bus %s, device %s\n"
--			"%s\n"
--			"EHCI %x.%02x, rh state %s\n",
--			hcd->self.controller->bus->name,
--			dev_name(hcd->self.controller),
--			hcd->product_desc,
--			i >> 8, i & 0x0ff, rh_state_string(fotg210));
--	size -= temp;
--	next += temp;
--
--	/* FIXME interpret both types of params */
--	i = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
--	temp = scnprintf(next, size, "structural params 0x%08x\n", i);
--	size -= temp;
--	next += temp;
--
--	i = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--	temp = scnprintf(next, size, "capability params 0x%08x\n", i);
--	size -= temp;
--	next += temp;
--
--	/* Operational Registers */
--	temp = dbg_status_buf(scratch, sizeof(scratch), label,
--			fotg210_readl(fotg210, &fotg210->regs->status));
--	temp = scnprintf(next, size, fmt, temp, scratch);
--	size -= temp;
--	next += temp;
--
--	temp = dbg_command_buf(scratch, sizeof(scratch), label,
--			fotg210_readl(fotg210, &fotg210->regs->command));
--	temp = scnprintf(next, size, fmt, temp, scratch);
--	size -= temp;
--	next += temp;
--
--	temp = dbg_intr_buf(scratch, sizeof(scratch), label,
--			fotg210_readl(fotg210, &fotg210->regs->intr_enable));
--	temp = scnprintf(next, size, fmt, temp, scratch);
--	size -= temp;
--	next += temp;
--
--	temp = scnprintf(next, size, "uframe %04x\n",
--			fotg210_read_frame_index(fotg210));
--	size -= temp;
--	next += temp;
--
--	if (fotg210->async_unlink) {
--		temp = scnprintf(next, size, "async unlink qh %p\n",
--				fotg210->async_unlink);
--		size -= temp;
--		next += temp;
--	}
--
--#ifdef FOTG210_STATS
--	temp = scnprintf(next, size,
--			"irq normal %ld err %ld iaa %ld(lost %ld)\n",
--			fotg210->stats.normal, fotg210->stats.error,
--			fotg210->stats.iaa, fotg210->stats.lost_iaa);
--	size -= temp;
--	next += temp;
--
--	temp = scnprintf(next, size, "complete %ld unlink %ld\n",
--			fotg210->stats.complete, fotg210->stats.unlink);
--	size -= temp;
--	next += temp;
--#endif
--
--done:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--
--	return buf->alloc_size - size;
--}
--
--static struct debug_buffer
--*alloc_buffer(struct usb_bus *bus, ssize_t (*fill_func)(struct debug_buffer *))
--{
--	struct debug_buffer *buf;
--
--	buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
--
--	if (buf) {
--		buf->bus = bus;
--		buf->fill_func = fill_func;
--		mutex_init(&buf->mutex);
--		buf->alloc_size = PAGE_SIZE;
--	}
--
--	return buf;
--}
--
--static int fill_buffer(struct debug_buffer *buf)
--{
--	int ret = 0;
--
--	if (!buf->output_buf)
--		buf->output_buf = vmalloc(buf->alloc_size);
--
--	if (!buf->output_buf) {
--		ret = -ENOMEM;
--		goto out;
--	}
--
--	ret = buf->fill_func(buf);
--
--	if (ret >= 0) {
--		buf->count = ret;
--		ret = 0;
--	}
--
--out:
--	return ret;
--}
--
--static ssize_t debug_output(struct file *file, char __user *user_buf,
--		size_t len, loff_t *offset)
--{
--	struct debug_buffer *buf = file->private_data;
--	int ret = 0;
--
--	mutex_lock(&buf->mutex);
--	if (buf->count == 0) {
--		ret = fill_buffer(buf);
--		if (ret != 0) {
--			mutex_unlock(&buf->mutex);
--			goto out;
--		}
--	}
--	mutex_unlock(&buf->mutex);
--
--	ret = simple_read_from_buffer(user_buf, len, offset,
--			buf->output_buf, buf->count);
--
--out:
--	return ret;
--
--}
--
--static int debug_close(struct inode *inode, struct file *file)
--{
--	struct debug_buffer *buf = file->private_data;
--
--	if (buf) {
--		vfree(buf->output_buf);
--		kfree(buf);
--	}
--
--	return 0;
--}
--static int debug_async_open(struct inode *inode, struct file *file)
--{
--	file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
--
--	return file->private_data ? 0 : -ENOMEM;
--}
--
--static int debug_periodic_open(struct inode *inode, struct file *file)
--{
--	struct debug_buffer *buf;
--
--	buf = alloc_buffer(inode->i_private, fill_periodic_buffer);
--	if (!buf)
--		return -ENOMEM;
--
--	buf->alloc_size = (sizeof(void *) == 4 ? 6 : 8)*PAGE_SIZE;
--	file->private_data = buf;
--	return 0;
--}
--
--static int debug_registers_open(struct inode *inode, struct file *file)
--{
--	file->private_data = alloc_buffer(inode->i_private,
--			fill_registers_buffer);
--
--	return file->private_data ? 0 : -ENOMEM;
--}
--
--static inline void create_debug_files(struct fotg210_hcd *fotg210)
--{
--	struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
--	struct dentry *root;
--
--	root = debugfs_create_dir(bus->bus_name, fotg210_debug_root);
--
--	debugfs_create_file("async", S_IRUGO, root, bus, &debug_async_fops);
--	debugfs_create_file("periodic", S_IRUGO, root, bus,
--			    &debug_periodic_fops);
--	debugfs_create_file("registers", S_IRUGO, root, bus,
--			    &debug_registers_fops);
--}
--
--static inline void remove_debug_files(struct fotg210_hcd *fotg210)
--{
--	struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
--
--	debugfs_lookup_and_remove(bus->bus_name, fotg210_debug_root);
--}
--
--/* handshake - spin reading hc until handshake completes or fails
-- * @ptr: address of hc register to be read
-- * @mask: bits to look at in result of read
-- * @done: value of those bits when handshake succeeds
-- * @usec: timeout in microseconds
-- *
-- * Returns negative errno, or zero on success
-- *
-- * Success happens when the "mask" bits have the specified value (hardware
-- * handshake done).  There are two failure modes:  "usec" have passed (major
-- * hardware flakeout), or the register reads as all-ones (hardware removed).
-- *
-- * That last failure should_only happen in cases like physical cardbus eject
-- * before driver shutdown. But it also seems to be caused by bugs in cardbus
-- * bridge shutdown:  shutting down the bridge before the devices using it.
-- */
--static int handshake(struct fotg210_hcd *fotg210, void __iomem *ptr,
--		u32 mask, u32 done, int usec)
--{
--	u32 result;
--	int ret;
--
--	ret = readl_poll_timeout_atomic(ptr, result,
--					((result & mask) == done ||
--					 result == U32_MAX), 1, usec);
--	if (result == U32_MAX)		/* card removed */
--		return -ENODEV;
--
--	return ret;
--}
--
--/* Force HC to halt state from unknown (EHCI spec section 2.3).
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static int fotg210_halt(struct fotg210_hcd *fotg210)
--{
--	u32 temp;
--
--	spin_lock_irq(&fotg210->lock);
--
--	/* disable any irqs left enabled by previous code */
--	fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
--
--	/*
--	 * This routine gets called during probe before fotg210->command
--	 * has been initialized, so we can't rely on its value.
--	 */
--	fotg210->command &= ~CMD_RUN;
--	temp = fotg210_readl(fotg210, &fotg210->regs->command);
--	temp &= ~(CMD_RUN | CMD_IAAD);
--	fotg210_writel(fotg210, temp, &fotg210->regs->command);
--
--	spin_unlock_irq(&fotg210->lock);
--	synchronize_irq(fotg210_to_hcd(fotg210)->irq);
--
--	return handshake(fotg210, &fotg210->regs->status,
--			STS_HALT, STS_HALT, 16 * 125);
--}
--
--/* Reset a non-running (STS_HALT == 1) controller.
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static int fotg210_reset(struct fotg210_hcd *fotg210)
--{
--	int retval;
--	u32 command = fotg210_readl(fotg210, &fotg210->regs->command);
--
--	/* If the EHCI debug controller is active, special care must be
--	 * taken before and after a host controller reset
--	 */
--	if (fotg210->debug && !dbgp_reset_prep(fotg210_to_hcd(fotg210)))
--		fotg210->debug = NULL;
--
--	command |= CMD_RESET;
--	dbg_cmd(fotg210, "reset", command);
--	fotg210_writel(fotg210, command, &fotg210->regs->command);
--	fotg210->rh_state = FOTG210_RH_HALTED;
--	fotg210->next_statechange = jiffies;
--	retval = handshake(fotg210, &fotg210->regs->command,
--			CMD_RESET, 0, 250 * 1000);
--
--	if (retval)
--		return retval;
--
--	if (fotg210->debug)
--		dbgp_external_startup(fotg210_to_hcd(fotg210));
--
--	fotg210->port_c_suspend = fotg210->suspended_ports =
--			fotg210->resuming_ports = 0;
--	return retval;
--}
--
--/* Idle the controller (turn off the schedules).
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static void fotg210_quiesce(struct fotg210_hcd *fotg210)
--{
--	u32 temp;
--
--	if (fotg210->rh_state != FOTG210_RH_RUNNING)
--		return;
--
--	/* wait for any schedule enables/disables to take effect */
--	temp = (fotg210->command << 10) & (STS_ASS | STS_PSS);
--	handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, temp,
--			16 * 125);
--
--	/* then disable anything that's still active */
--	spin_lock_irq(&fotg210->lock);
--	fotg210->command &= ~(CMD_ASE | CMD_PSE);
--	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--	spin_unlock_irq(&fotg210->lock);
--
--	/* hardware can take 16 microframes to turn off ... */
--	handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, 0,
--			16 * 125);
--}
--
--static void end_unlink_async(struct fotg210_hcd *fotg210);
--static void unlink_empty_async(struct fotg210_hcd *fotg210);
--static void fotg210_work(struct fotg210_hcd *fotg210);
--static void start_unlink_intr(struct fotg210_hcd *fotg210,
--			      struct fotg210_qh *qh);
--static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--/* Set a bit in the USBCMD register */
--static void fotg210_set_command_bit(struct fotg210_hcd *fotg210, u32 bit)
--{
--	fotg210->command |= bit;
--	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--
--	/* unblock posted write */
--	fotg210_readl(fotg210, &fotg210->regs->command);
--}
--
--/* Clear a bit in the USBCMD register */
--static void fotg210_clear_command_bit(struct fotg210_hcd *fotg210, u32 bit)
--{
--	fotg210->command &= ~bit;
--	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--
--	/* unblock posted write */
--	fotg210_readl(fotg210, &fotg210->regs->command);
--}
--
--/* EHCI timer support...  Now using hrtimers.
-- *
-- * Lots of different events are triggered from fotg210->hrtimer.  Whenever
-- * the timer routine runs, it checks each possible event; events that are
-- * currently enabled and whose expiration time has passed get handled.
-- * The set of enabled events is stored as a collection of bitflags in
-- * fotg210->enabled_hrtimer_events, and they are numbered in order of
-- * increasing delay values (ranging between 1 ms and 100 ms).
-- *
-- * Rather than implementing a sorted list or tree of all pending events,
-- * we keep track only of the lowest-numbered pending event, in
-- * fotg210->next_hrtimer_event.  Whenever fotg210->hrtimer gets restarted, its
-- * expiration time is set to the timeout value for this event.
-- *
-- * As a result, events might not get handled right away; the actual delay
-- * could be anywhere up to twice the requested delay.  This doesn't
-- * matter, because none of the events are especially time-critical.  The
-- * ones that matter most all have a delay of 1 ms, so they will be
-- * handled after 2 ms at most, which is okay.  In addition to this, we
-- * allow for an expiration range of 1 ms.
-- */
--
--/* Delay lengths for the hrtimer event types.
-- * Keep this list sorted by delay length, in the same order as
-- * the event types indexed by enum fotg210_hrtimer_event in fotg210.h.
-- */
--static unsigned event_delays_ns[] = {
--	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_ASS */
--	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_PSS */
--	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_DEAD */
--	1125 * NSEC_PER_USEC,	/* FOTG210_HRTIMER_UNLINK_INTR */
--	2 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_FREE_ITDS */
--	6 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_ASYNC_UNLINKS */
--	10 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_IAA_WATCHDOG */
--	10 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_DISABLE_PERIODIC */
--	15 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_DISABLE_ASYNC */
--	100 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_IO_WATCHDOG */
--};
--
--/* Enable a pending hrtimer event */
--static void fotg210_enable_event(struct fotg210_hcd *fotg210, unsigned event,
--		bool resched)
--{
--	ktime_t *timeout = &fotg210->hr_timeouts[event];
--
--	if (resched)
--		*timeout = ktime_add(ktime_get(), event_delays_ns[event]);
--	fotg210->enabled_hrtimer_events |= (1 << event);
--
--	/* Track only the lowest-numbered pending event */
--	if (event < fotg210->next_hrtimer_event) {
--		fotg210->next_hrtimer_event = event;
--		hrtimer_start_range_ns(&fotg210->hrtimer, *timeout,
--				NSEC_PER_MSEC, HRTIMER_MODE_ABS);
--	}
--}
--
--
--/* Poll the STS_ASS status bit; see when it agrees with CMD_ASE */
--static void fotg210_poll_ASS(struct fotg210_hcd *fotg210)
--{
--	unsigned actual, want;
--
--	/* Don't enable anything if the controller isn't running (e.g., died) */
--	if (fotg210->rh_state != FOTG210_RH_RUNNING)
--		return;
--
--	want = (fotg210->command & CMD_ASE) ? STS_ASS : 0;
--	actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_ASS;
--
--	if (want != actual) {
--
--		/* Poll again later, but give up after about 20 ms */
--		if (fotg210->ASS_poll_count++ < 20) {
--			fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_ASS,
--					true);
--			return;
--		}
--		fotg210_dbg(fotg210, "Waited too long for the async schedule status (%x/%x), giving up\n",
--				want, actual);
--	}
--	fotg210->ASS_poll_count = 0;
--
--	/* The status is up-to-date; restart or stop the schedule as needed */
--	if (want == 0) {	/* Stopped */
--		if (fotg210->async_count > 0)
--			fotg210_set_command_bit(fotg210, CMD_ASE);
--
--	} else {		/* Running */
--		if (fotg210->async_count == 0) {
--
--			/* Turn off the schedule after a while */
--			fotg210_enable_event(fotg210,
--					FOTG210_HRTIMER_DISABLE_ASYNC,
--					true);
--		}
--	}
--}
--
--/* Turn off the async schedule after a brief delay */
--static void fotg210_disable_ASE(struct fotg210_hcd *fotg210)
--{
--	fotg210_clear_command_bit(fotg210, CMD_ASE);
--}
--
--
--/* Poll the STS_PSS status bit; see when it agrees with CMD_PSE */
--static void fotg210_poll_PSS(struct fotg210_hcd *fotg210)
--{
--	unsigned actual, want;
--
--	/* Don't do anything if the controller isn't running (e.g., died) */
--	if (fotg210->rh_state != FOTG210_RH_RUNNING)
--		return;
--
--	want = (fotg210->command & CMD_PSE) ? STS_PSS : 0;
--	actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_PSS;
--
--	if (want != actual) {
--
--		/* Poll again later, but give up after about 20 ms */
--		if (fotg210->PSS_poll_count++ < 20) {
--			fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_PSS,
--					true);
--			return;
--		}
--		fotg210_dbg(fotg210, "Waited too long for the periodic schedule status (%x/%x), giving up\n",
--				want, actual);
--	}
--	fotg210->PSS_poll_count = 0;
--
--	/* The status is up-to-date; restart or stop the schedule as needed */
--	if (want == 0) {	/* Stopped */
--		if (fotg210->periodic_count > 0)
--			fotg210_set_command_bit(fotg210, CMD_PSE);
--
--	} else {		/* Running */
--		if (fotg210->periodic_count == 0) {
--
--			/* Turn off the schedule after a while */
--			fotg210_enable_event(fotg210,
--					FOTG210_HRTIMER_DISABLE_PERIODIC,
--					true);
--		}
--	}
--}
--
--/* Turn off the periodic schedule after a brief delay */
--static void fotg210_disable_PSE(struct fotg210_hcd *fotg210)
--{
--	fotg210_clear_command_bit(fotg210, CMD_PSE);
--}
--
--
--/* Poll the STS_HALT status bit; see when a dead controller stops */
--static void fotg210_handle_controller_death(struct fotg210_hcd *fotg210)
--{
--	if (!(fotg210_readl(fotg210, &fotg210->regs->status) & STS_HALT)) {
--
--		/* Give up after a few milliseconds */
--		if (fotg210->died_poll_count++ < 5) {
--			/* Try again later */
--			fotg210_enable_event(fotg210,
--					FOTG210_HRTIMER_POLL_DEAD, true);
--			return;
--		}
--		fotg210_warn(fotg210, "Waited too long for the controller to stop, giving up\n");
--	}
--
--	/* Clean up the mess */
--	fotg210->rh_state = FOTG210_RH_HALTED;
--	fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
--	fotg210_work(fotg210);
--	end_unlink_async(fotg210);
--
--	/* Not in process context, so don't try to reset the controller */
--}
--
--
--/* Handle unlinked interrupt QHs once they are gone from the hardware */
--static void fotg210_handle_intr_unlinks(struct fotg210_hcd *fotg210)
--{
--	bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
--
--	/*
--	 * Process all the QHs on the intr_unlink list that were added
--	 * before the current unlink cycle began.  The list is in
--	 * temporal order, so stop when we reach the first entry in the
--	 * current cycle.  But if the root hub isn't running then
--	 * process all the QHs on the list.
--	 */
--	fotg210->intr_unlinking = true;
--	while (fotg210->intr_unlink) {
--		struct fotg210_qh *qh = fotg210->intr_unlink;
--
--		if (!stopped && qh->unlink_cycle == fotg210->intr_unlink_cycle)
--			break;
--		fotg210->intr_unlink = qh->unlink_next;
--		qh->unlink_next = NULL;
--		end_unlink_intr(fotg210, qh);
--	}
--
--	/* Handle remaining entries later */
--	if (fotg210->intr_unlink) {
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
--				true);
--		++fotg210->intr_unlink_cycle;
--	}
--	fotg210->intr_unlinking = false;
--}
--
--
--/* Start another free-iTDs/siTDs cycle */
--static void start_free_itds(struct fotg210_hcd *fotg210)
--{
--	if (!(fotg210->enabled_hrtimer_events &
--			BIT(FOTG210_HRTIMER_FREE_ITDS))) {
--		fotg210->last_itd_to_free = list_entry(
--				fotg210->cached_itd_list.prev,
--				struct fotg210_itd, itd_list);
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_FREE_ITDS, true);
--	}
--}
--
--/* Wait for controller to stop using old iTDs and siTDs */
--static void end_free_itds(struct fotg210_hcd *fotg210)
--{
--	struct fotg210_itd *itd, *n;
--
--	if (fotg210->rh_state < FOTG210_RH_RUNNING)
--		fotg210->last_itd_to_free = NULL;
--
--	list_for_each_entry_safe(itd, n, &fotg210->cached_itd_list, itd_list) {
--		list_del(&itd->itd_list);
--		dma_pool_free(fotg210->itd_pool, itd, itd->itd_dma);
--		if (itd == fotg210->last_itd_to_free)
--			break;
--	}
--
--	if (!list_empty(&fotg210->cached_itd_list))
--		start_free_itds(fotg210);
--}
--
--
--/* Handle lost (or very late) IAA interrupts */
--static void fotg210_iaa_watchdog(struct fotg210_hcd *fotg210)
--{
--	if (fotg210->rh_state != FOTG210_RH_RUNNING)
--		return;
--
--	/*
--	 * Lost IAA irqs wedge things badly; seen first with a vt8235.
--	 * So we need this watchdog, but must protect it against both
--	 * (a) SMP races against real IAA firing and retriggering, and
--	 * (b) clean HC shutdown, when IAA watchdog was pending.
--	 */
--	if (fotg210->async_iaa) {
--		u32 cmd, status;
--
--		/* If we get here, IAA is *REALLY* late.  It's barely
--		 * conceivable that the system is so busy that CMD_IAAD
--		 * is still legitimately set, so let's be sure it's
--		 * clear before we read STS_IAA.  (The HC should clear
--		 * CMD_IAAD when it sets STS_IAA.)
--		 */
--		cmd = fotg210_readl(fotg210, &fotg210->regs->command);
--
--		/*
--		 * If IAA is set here it either legitimately triggered
--		 * after the watchdog timer expired (_way_ late, so we'll
--		 * still count it as lost) ... or a silicon erratum:
--		 * - VIA seems to set IAA without triggering the IRQ;
--		 * - IAAD potentially cleared without setting IAA.
--		 */
--		status = fotg210_readl(fotg210, &fotg210->regs->status);
--		if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
--			INCR(fotg210->stats.lost_iaa);
--			fotg210_writel(fotg210, STS_IAA,
--					&fotg210->regs->status);
--		}
--
--		fotg210_dbg(fotg210, "IAA watchdog: status %x cmd %x\n",
--				status, cmd);
--		end_unlink_async(fotg210);
--	}
--}
--
--
--/* Enable the I/O watchdog, if appropriate */
--static void turn_on_io_watchdog(struct fotg210_hcd *fotg210)
--{
--	/* Not needed if the controller isn't running or it's already enabled */
--	if (fotg210->rh_state != FOTG210_RH_RUNNING ||
--			(fotg210->enabled_hrtimer_events &
--			BIT(FOTG210_HRTIMER_IO_WATCHDOG)))
--		return;
--
--	/*
--	 * Isochronous transfers always need the watchdog.
--	 * For other sorts we use it only if the flag is set.
--	 */
--	if (fotg210->isoc_count > 0 || (fotg210->need_io_watchdog &&
--			fotg210->async_count + fotg210->intr_count > 0))
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_IO_WATCHDOG,
--				true);
--}
--
--
--/* Handler functions for the hrtimer event types.
-- * Keep this array in the same order as the event types indexed by
-- * enum fotg210_hrtimer_event in fotg210.h.
-- */
--static void (*event_handlers[])(struct fotg210_hcd *) = {
--	fotg210_poll_ASS,			/* FOTG210_HRTIMER_POLL_ASS */
--	fotg210_poll_PSS,			/* FOTG210_HRTIMER_POLL_PSS */
--	fotg210_handle_controller_death,	/* FOTG210_HRTIMER_POLL_DEAD */
--	fotg210_handle_intr_unlinks,	/* FOTG210_HRTIMER_UNLINK_INTR */
--	end_free_itds,			/* FOTG210_HRTIMER_FREE_ITDS */
--	unlink_empty_async,		/* FOTG210_HRTIMER_ASYNC_UNLINKS */
--	fotg210_iaa_watchdog,		/* FOTG210_HRTIMER_IAA_WATCHDOG */
--	fotg210_disable_PSE,		/* FOTG210_HRTIMER_DISABLE_PERIODIC */
--	fotg210_disable_ASE,		/* FOTG210_HRTIMER_DISABLE_ASYNC */
--	fotg210_work,			/* FOTG210_HRTIMER_IO_WATCHDOG */
--};
--
--static enum hrtimer_restart fotg210_hrtimer_func(struct hrtimer *t)
--{
--	struct fotg210_hcd *fotg210 =
--			container_of(t, struct fotg210_hcd, hrtimer);
--	ktime_t now;
--	unsigned long events;
--	unsigned long flags;
--	unsigned e;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	events = fotg210->enabled_hrtimer_events;
--	fotg210->enabled_hrtimer_events = 0;
--	fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
--
--	/*
--	 * Check each pending event.  If its time has expired, handle
--	 * the event; otherwise re-enable it.
--	 */
--	now = ktime_get();
--	for_each_set_bit(e, &events, FOTG210_HRTIMER_NUM_EVENTS) {
--		if (ktime_compare(now, fotg210->hr_timeouts[e]) >= 0)
--			event_handlers[e](fotg210);
--		else
--			fotg210_enable_event(fotg210, e, false);
--	}
--
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return HRTIMER_NORESTART;
--}
--
--#define fotg210_bus_suspend NULL
--#define fotg210_bus_resume NULL
--
--static int check_reset_complete(struct fotg210_hcd *fotg210, int index,
--		u32 __iomem *status_reg, int port_status)
--{
--	if (!(port_status & PORT_CONNECT))
--		return port_status;
--
--	/* if reset finished and it's still not enabled -- handoff */
--	if (!(port_status & PORT_PE))
--		/* with integrated TT, there's nobody to hand it to! */
--		fotg210_dbg(fotg210, "Failed to enable port %d on root hub TT\n",
--				index + 1);
--	else
--		fotg210_dbg(fotg210, "port %d reset complete, port enabled\n",
--				index + 1);
--
--	return port_status;
--}
--
--
--/* build "status change" packet (one or two bytes) from HC registers */
--
--static int fotg210_hub_status_data(struct usb_hcd *hcd, char *buf)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	u32 temp, status;
--	u32 mask;
--	int retval = 1;
--	unsigned long flags;
--
--	/* init status to no-changes */
--	buf[0] = 0;
--
--	/* Inform the core about resumes-in-progress by returning
--	 * a non-zero value even if there are no status changes.
--	 */
--	status = fotg210->resuming_ports;
--
--	mask = PORT_CSC | PORT_PEC;
--	/* PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND */
--
--	/* no hub change reports (bit 0) for now (power, ...) */
--
--	/* port N changes (bit N)? */
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	temp = fotg210_readl(fotg210, &fotg210->regs->port_status);
--
--	/*
--	 * Return status information even for ports with OWNER set.
--	 * Otherwise hub_wq wouldn't see the disconnect event when a
--	 * high-speed device is switched over to the companion
--	 * controller by the user.
--	 */
--
--	if ((temp & mask) != 0 || test_bit(0, &fotg210->port_c_suspend) ||
--			(fotg210->reset_done[0] &&
--			time_after_eq(jiffies, fotg210->reset_done[0]))) {
--		buf[0] |= 1 << 1;
--		status = STS_PCD;
--	}
--	/* FIXME autosuspend idle root hubs */
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return status ? retval : 0;
--}
--
--static void fotg210_hub_descriptor(struct fotg210_hcd *fotg210,
--		struct usb_hub_descriptor *desc)
--{
--	int ports = HCS_N_PORTS(fotg210->hcs_params);
--	u16 temp;
--
--	desc->bDescriptorType = USB_DT_HUB;
--	desc->bPwrOn2PwrGood = 10;	/* fotg210 1.0, 2.3.9 says 20ms max */
--	desc->bHubContrCurrent = 0;
--
--	desc->bNbrPorts = ports;
--	temp = 1 + (ports / 8);
--	desc->bDescLength = 7 + 2 * temp;
--
--	/* two bitmaps:  ports removable, and usb 1.0 legacy PortPwrCtrlMask */
--	memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
--	memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
--
--	temp = HUB_CHAR_INDV_PORT_OCPM;	/* per-port overcurrent reporting */
--	temp |= HUB_CHAR_NO_LPSM;	/* no power switching */
--	desc->wHubCharacteristics = cpu_to_le16(temp);
--}
--
--static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
--		u16 wIndex, char *buf, u16 wLength)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	int ports = HCS_N_PORTS(fotg210->hcs_params);
--	u32 __iomem *status_reg = &fotg210->regs->port_status;
--	u32 temp, temp1, status;
--	unsigned long flags;
--	int retval = 0;
--	unsigned selector;
--
--	/*
--	 * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
--	 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
--	 * (track current state ourselves) ... blink for diagnostics,
--	 * power, "this is the one", etc.  EHCI spec supports this.
--	 */
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	switch (typeReq) {
--	case ClearHubFeature:
--		switch (wValue) {
--		case C_HUB_LOCAL_POWER:
--		case C_HUB_OVER_CURRENT:
--			/* no hub-wide feature/status flags */
--			break;
--		default:
--			goto error;
--		}
--		break;
--	case ClearPortFeature:
--		if (!wIndex || wIndex > ports)
--			goto error;
--		wIndex--;
--		temp = fotg210_readl(fotg210, status_reg);
--		temp &= ~PORT_RWC_BITS;
--
--		/*
--		 * Even if OWNER is set, so the port is owned by the
--		 * companion controller, hub_wq needs to be able to clear
--		 * the port-change status bits (especially
--		 * USB_PORT_STAT_C_CONNECTION).
--		 */
--
--		switch (wValue) {
--		case USB_PORT_FEAT_ENABLE:
--			fotg210_writel(fotg210, temp & ~PORT_PE, status_reg);
--			break;
--		case USB_PORT_FEAT_C_ENABLE:
--			fotg210_writel(fotg210, temp | PORT_PEC, status_reg);
--			break;
--		case USB_PORT_FEAT_SUSPEND:
--			if (temp & PORT_RESET)
--				goto error;
--			if (!(temp & PORT_SUSPEND))
--				break;
--			if ((temp & PORT_PE) == 0)
--				goto error;
--
--			/* resume signaling for 20 msec */
--			fotg210_writel(fotg210, temp | PORT_RESUME, status_reg);
--			fotg210->reset_done[wIndex] = jiffies
--					+ msecs_to_jiffies(USB_RESUME_TIMEOUT);
--			break;
--		case USB_PORT_FEAT_C_SUSPEND:
--			clear_bit(wIndex, &fotg210->port_c_suspend);
--			break;
--		case USB_PORT_FEAT_C_CONNECTION:
--			fotg210_writel(fotg210, temp | PORT_CSC, status_reg);
--			break;
--		case USB_PORT_FEAT_C_OVER_CURRENT:
--			fotg210_writel(fotg210, temp | OTGISR_OVC,
--					&fotg210->regs->otgisr);
--			break;
--		case USB_PORT_FEAT_C_RESET:
--			/* GetPortStatus clears reset */
--			break;
--		default:
--			goto error;
--		}
--		fotg210_readl(fotg210, &fotg210->regs->command);
--		break;
--	case GetHubDescriptor:
--		fotg210_hub_descriptor(fotg210, (struct usb_hub_descriptor *)
--				buf);
--		break;
--	case GetHubStatus:
--		/* no hub-wide feature/status flags */
--		memset(buf, 0, 4);
--		/*cpu_to_le32s ((u32 *) buf); */
--		break;
--	case GetPortStatus:
--		if (!wIndex || wIndex > ports)
--			goto error;
--		wIndex--;
--		status = 0;
--		temp = fotg210_readl(fotg210, status_reg);
--
--		/* wPortChange bits */
--		if (temp & PORT_CSC)
--			status |= USB_PORT_STAT_C_CONNECTION << 16;
--		if (temp & PORT_PEC)
--			status |= USB_PORT_STAT_C_ENABLE << 16;
--
--		temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
--		if (temp1 & OTGISR_OVC)
--			status |= USB_PORT_STAT_C_OVERCURRENT << 16;
--
--		/* whoever resumes must GetPortStatus to complete it!! */
--		if (temp & PORT_RESUME) {
--
--			/* Remote Wakeup received? */
--			if (!fotg210->reset_done[wIndex]) {
--				/* resume signaling for 20 msec */
--				fotg210->reset_done[wIndex] = jiffies
--						+ msecs_to_jiffies(20);
--				/* check the port again */
--				mod_timer(&fotg210_to_hcd(fotg210)->rh_timer,
--						fotg210->reset_done[wIndex]);
--			}
--
--			/* resume completed? */
--			else if (time_after_eq(jiffies,
--					fotg210->reset_done[wIndex])) {
--				clear_bit(wIndex, &fotg210->suspended_ports);
--				set_bit(wIndex, &fotg210->port_c_suspend);
--				fotg210->reset_done[wIndex] = 0;
--
--				/* stop resume signaling */
--				temp = fotg210_readl(fotg210, status_reg);
--				fotg210_writel(fotg210, temp &
--						~(PORT_RWC_BITS | PORT_RESUME),
--						status_reg);
--				clear_bit(wIndex, &fotg210->resuming_ports);
--				retval = handshake(fotg210, status_reg,
--						PORT_RESUME, 0, 2000);/* 2ms */
--				if (retval != 0) {
--					fotg210_err(fotg210,
--							"port %d resume error %d\n",
--							wIndex + 1, retval);
--					goto error;
--				}
--				temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
--			}
--		}
--
--		/* whoever resets must GetPortStatus to complete it!! */
--		if ((temp & PORT_RESET) && time_after_eq(jiffies,
--				fotg210->reset_done[wIndex])) {
--			status |= USB_PORT_STAT_C_RESET << 16;
--			fotg210->reset_done[wIndex] = 0;
--			clear_bit(wIndex, &fotg210->resuming_ports);
--
--			/* force reset to complete */
--			fotg210_writel(fotg210,
--					temp & ~(PORT_RWC_BITS | PORT_RESET),
--					status_reg);
--			/* REVISIT:  some hardware needs 550+ usec to clear
--			 * this bit; seems too long to spin routinely...
--			 */
--			retval = handshake(fotg210, status_reg,
--					PORT_RESET, 0, 1000);
--			if (retval != 0) {
--				fotg210_err(fotg210, "port %d reset error %d\n",
--						wIndex + 1, retval);
--				goto error;
--			}
--
--			/* see what we found out */
--			temp = check_reset_complete(fotg210, wIndex, status_reg,
--					fotg210_readl(fotg210, status_reg));
--
--			/* restart schedule */
--			fotg210->command |= CMD_RUN;
--			fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--		}
--
--		if (!(temp & (PORT_RESUME|PORT_RESET))) {
--			fotg210->reset_done[wIndex] = 0;
--			clear_bit(wIndex, &fotg210->resuming_ports);
--		}
--
--		/* transfer dedicated ports to the companion hc */
--		if ((temp & PORT_CONNECT) &&
--				test_bit(wIndex, &fotg210->companion_ports)) {
--			temp &= ~PORT_RWC_BITS;
--			fotg210_writel(fotg210, temp, status_reg);
--			fotg210_dbg(fotg210, "port %d --> companion\n",
--					wIndex + 1);
--			temp = fotg210_readl(fotg210, status_reg);
--		}
--
--		/*
--		 * Even if OWNER is set, there's no harm letting hub_wq
--		 * see the wPortStatus values (they should all be 0 except
--		 * for PORT_POWER anyway).
--		 */
--
--		if (temp & PORT_CONNECT) {
--			status |= USB_PORT_STAT_CONNECTION;
--			status |= fotg210_port_speed(fotg210, temp);
--		}
--		if (temp & PORT_PE)
--			status |= USB_PORT_STAT_ENABLE;
--
--		/* maybe the port was unsuspended without our knowledge */
--		if (temp & (PORT_SUSPEND|PORT_RESUME)) {
--			status |= USB_PORT_STAT_SUSPEND;
--		} else if (test_bit(wIndex, &fotg210->suspended_ports)) {
--			clear_bit(wIndex, &fotg210->suspended_ports);
--			clear_bit(wIndex, &fotg210->resuming_ports);
--			fotg210->reset_done[wIndex] = 0;
--			if (temp & PORT_PE)
--				set_bit(wIndex, &fotg210->port_c_suspend);
--		}
--
--		temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
--		if (temp1 & OTGISR_OVC)
--			status |= USB_PORT_STAT_OVERCURRENT;
--		if (temp & PORT_RESET)
--			status |= USB_PORT_STAT_RESET;
--		if (test_bit(wIndex, &fotg210->port_c_suspend))
--			status |= USB_PORT_STAT_C_SUSPEND << 16;
--
--		if (status & ~0xffff)	/* only if wPortChange is interesting */
--			dbg_port(fotg210, "GetStatus", wIndex + 1, temp);
--		put_unaligned_le32(status, buf);
--		break;
--	case SetHubFeature:
--		switch (wValue) {
--		case C_HUB_LOCAL_POWER:
--		case C_HUB_OVER_CURRENT:
--			/* no hub-wide feature/status flags */
--			break;
--		default:
--			goto error;
--		}
--		break;
--	case SetPortFeature:
--		selector = wIndex >> 8;
--		wIndex &= 0xff;
--
--		if (!wIndex || wIndex > ports)
--			goto error;
--		wIndex--;
--		temp = fotg210_readl(fotg210, status_reg);
--		temp &= ~PORT_RWC_BITS;
--		switch (wValue) {
--		case USB_PORT_FEAT_SUSPEND:
--			if ((temp & PORT_PE) == 0
--					|| (temp & PORT_RESET) != 0)
--				goto error;
--
--			/* After above check the port must be connected.
--			 * Set appropriate bit thus could put phy into low power
--			 * mode if we have hostpc feature
--			 */
--			fotg210_writel(fotg210, temp | PORT_SUSPEND,
--					status_reg);
--			set_bit(wIndex, &fotg210->suspended_ports);
--			break;
--		case USB_PORT_FEAT_RESET:
--			if (temp & PORT_RESUME)
--				goto error;
--			/* line status bits may report this as low speed,
--			 * which can be fine if this root hub has a
--			 * transaction translator built in.
--			 */
--			fotg210_dbg(fotg210, "port %d reset\n", wIndex + 1);
--			temp |= PORT_RESET;
--			temp &= ~PORT_PE;
--
--			/*
--			 * caller must wait, then call GetPortStatus
--			 * usb 2.0 spec says 50 ms resets on root
--			 */
--			fotg210->reset_done[wIndex] = jiffies
--					+ msecs_to_jiffies(50);
--			fotg210_writel(fotg210, temp, status_reg);
--			break;
--
--		/* For downstream facing ports (these):  one hub port is put
--		 * into test mode according to USB2 11.24.2.13, then the hub
--		 * must be reset (which for root hub now means rmmod+modprobe,
--		 * or else system reboot).  See EHCI 2.3.9 and 4.14 for info
--		 * about the EHCI-specific stuff.
--		 */
--		case USB_PORT_FEAT_TEST:
--			if (!selector || selector > 5)
--				goto error;
--			spin_unlock_irqrestore(&fotg210->lock, flags);
--			fotg210_quiesce(fotg210);
--			spin_lock_irqsave(&fotg210->lock, flags);
--
--			/* Put all enabled ports into suspend */
--			temp = fotg210_readl(fotg210, status_reg) &
--				~PORT_RWC_BITS;
--			if (temp & PORT_PE)
--				fotg210_writel(fotg210, temp | PORT_SUSPEND,
--						status_reg);
--
--			spin_unlock_irqrestore(&fotg210->lock, flags);
--			fotg210_halt(fotg210);
--			spin_lock_irqsave(&fotg210->lock, flags);
--
--			temp = fotg210_readl(fotg210, status_reg);
--			temp |= selector << 16;
--			fotg210_writel(fotg210, temp, status_reg);
--			break;
--
--		default:
--			goto error;
--		}
--		fotg210_readl(fotg210, &fotg210->regs->command);
--		break;
--
--	default:
--error:
--		/* "stall" on error */
--		retval = -EPIPE;
--	}
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return retval;
--}
--
--static void __maybe_unused fotg210_relinquish_port(struct usb_hcd *hcd,
--		int portnum)
--{
--	return;
--}
--
--static int __maybe_unused fotg210_port_handed_over(struct usb_hcd *hcd,
--		int portnum)
--{
--	return 0;
--}
--
--/* There's basically three types of memory:
-- *	- data used only by the HCD ... kmalloc is fine
-- *	- async and periodic schedules, shared by HC and HCD ... these
-- *	  need to use dma_pool or dma_alloc_coherent
-- *	- driver buffers, read/written by HC ... single shot DMA mapped
-- *
-- * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
-- * No memory seen by this driver is pageable.
-- */
--
--/* Allocate the key transfer structures from the previously allocated pool */
--static inline void fotg210_qtd_init(struct fotg210_hcd *fotg210,
--		struct fotg210_qtd *qtd, dma_addr_t dma)
--{
--	memset(qtd, 0, sizeof(*qtd));
--	qtd->qtd_dma = dma;
--	qtd->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
--	qtd->hw_next = FOTG210_LIST_END(fotg210);
--	qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
--	INIT_LIST_HEAD(&qtd->qtd_list);
--}
--
--static struct fotg210_qtd *fotg210_qtd_alloc(struct fotg210_hcd *fotg210,
--		gfp_t flags)
--{
--	struct fotg210_qtd *qtd;
--	dma_addr_t dma;
--
--	qtd = dma_pool_alloc(fotg210->qtd_pool, flags, &dma);
--	if (qtd != NULL)
--		fotg210_qtd_init(fotg210, qtd, dma);
--
--	return qtd;
--}
--
--static inline void fotg210_qtd_free(struct fotg210_hcd *fotg210,
--		struct fotg210_qtd *qtd)
--{
--	dma_pool_free(fotg210->qtd_pool, qtd, qtd->qtd_dma);
--}
--
--
--static void qh_destroy(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	/* clean qtds first, and know this is not linked */
--	if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
--		fotg210_dbg(fotg210, "unused qh not empty!\n");
--		BUG();
--	}
--	if (qh->dummy)
--		fotg210_qtd_free(fotg210, qh->dummy);
--	dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
--	kfree(qh);
--}
--
--static struct fotg210_qh *fotg210_qh_alloc(struct fotg210_hcd *fotg210,
--		gfp_t flags)
--{
--	struct fotg210_qh *qh;
--	dma_addr_t dma;
--
--	qh = kzalloc(sizeof(*qh), GFP_ATOMIC);
--	if (!qh)
--		goto done;
--	qh->hw = (struct fotg210_qh_hw *)
--		dma_pool_zalloc(fotg210->qh_pool, flags, &dma);
--	if (!qh->hw)
--		goto fail;
--	qh->qh_dma = dma;
--	INIT_LIST_HEAD(&qh->qtd_list);
--
--	/* dummy td enables safe urb queuing */
--	qh->dummy = fotg210_qtd_alloc(fotg210, flags);
--	if (qh->dummy == NULL) {
--		fotg210_dbg(fotg210, "no dummy td\n");
--		goto fail1;
--	}
--done:
--	return qh;
--fail1:
--	dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
--fail:
--	kfree(qh);
--	return NULL;
--}
--
--/* The queue heads and transfer descriptors are managed from pools tied
-- * to each of the "per device" structures.
-- * This is the initialisation and cleanup code.
-- */
--
--static void fotg210_mem_cleanup(struct fotg210_hcd *fotg210)
--{
--	if (fotg210->async)
--		qh_destroy(fotg210, fotg210->async);
--	fotg210->async = NULL;
--
--	if (fotg210->dummy)
--		qh_destroy(fotg210, fotg210->dummy);
--	fotg210->dummy = NULL;
--
--	/* DMA consistent memory and pools */
--	dma_pool_destroy(fotg210->qtd_pool);
--	fotg210->qtd_pool = NULL;
--
--	dma_pool_destroy(fotg210->qh_pool);
--	fotg210->qh_pool = NULL;
--
--	dma_pool_destroy(fotg210->itd_pool);
--	fotg210->itd_pool = NULL;
--
--	if (fotg210->periodic)
--		dma_free_coherent(fotg210_to_hcd(fotg210)->self.controller,
--				fotg210->periodic_size * sizeof(u32),
--				fotg210->periodic, fotg210->periodic_dma);
--	fotg210->periodic = NULL;
--
--	/* shadow periodic table */
--	kfree(fotg210->pshadow);
--	fotg210->pshadow = NULL;
--}
--
--/* remember to add cleanup code (above) if you add anything here */
--static int fotg210_mem_init(struct fotg210_hcd *fotg210, gfp_t flags)
--{
--	int i;
--
--	/* QTDs for control/bulk/intr transfers */
--	fotg210->qtd_pool = dma_pool_create("fotg210_qtd",
--			fotg210_to_hcd(fotg210)->self.controller,
--			sizeof(struct fotg210_qtd),
--			32 /* byte alignment (for hw parts) */,
--			4096 /* can't cross 4K */);
--	if (!fotg210->qtd_pool)
--		goto fail;
--
--	/* QHs for control/bulk/intr transfers */
--	fotg210->qh_pool = dma_pool_create("fotg210_qh",
--			fotg210_to_hcd(fotg210)->self.controller,
--			sizeof(struct fotg210_qh_hw),
--			32 /* byte alignment (for hw parts) */,
--			4096 /* can't cross 4K */);
--	if (!fotg210->qh_pool)
--		goto fail;
--
--	fotg210->async = fotg210_qh_alloc(fotg210, flags);
--	if (!fotg210->async)
--		goto fail;
--
--	/* ITD for high speed ISO transfers */
--	fotg210->itd_pool = dma_pool_create("fotg210_itd",
--			fotg210_to_hcd(fotg210)->self.controller,
--			sizeof(struct fotg210_itd),
--			64 /* byte alignment (for hw parts) */,
--			4096 /* can't cross 4K */);
--	if (!fotg210->itd_pool)
--		goto fail;
--
--	/* Hardware periodic table */
--	fotg210->periodic =
--		dma_alloc_coherent(fotg210_to_hcd(fotg210)->self.controller,
--				fotg210->periodic_size * sizeof(__le32),
--				&fotg210->periodic_dma, 0);
--	if (fotg210->periodic == NULL)
--		goto fail;
--
--	for (i = 0; i < fotg210->periodic_size; i++)
--		fotg210->periodic[i] = FOTG210_LIST_END(fotg210);
--
--	/* software shadow of hardware table */
--	fotg210->pshadow = kcalloc(fotg210->periodic_size, sizeof(void *),
--			flags);
--	if (fotg210->pshadow != NULL)
--		return 0;
--
--fail:
--	fotg210_dbg(fotg210, "couldn't init memory\n");
--	fotg210_mem_cleanup(fotg210);
--	return -ENOMEM;
--}
--/* EHCI hardware queue manipulation ... the core.  QH/QTD manipulation.
-- *
-- * Control, bulk, and interrupt traffic all use "qh" lists.  They list "qtd"
-- * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
-- * buffers needed for the larger number).  We use one QH per endpoint, queue
-- * multiple urbs (all three types) per endpoint.  URBs may need several qtds.
-- *
-- * ISO traffic uses "ISO TD" (itd) records, and (along with
-- * interrupts) needs careful scheduling.  Performance improvements can be
-- * an ongoing challenge.  That's in "ehci-sched.c".
-- *
-- * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
-- * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
-- * (b) special fields in qh entries or (c) split iso entries.  TTs will
-- * buffer low/full speed data so the host collects it at high speed.
-- */
--
--/* fill a qtd, returning how much of the buffer we were able to queue up */
--static int qtd_fill(struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd,
--		dma_addr_t buf, size_t len, int token, int maxpacket)
--{
--	int i, count;
--	u64 addr = buf;
--
--	/* one buffer entry per 4K ... first might be short or unaligned */
--	qtd->hw_buf[0] = cpu_to_hc32(fotg210, (u32)addr);
--	qtd->hw_buf_hi[0] = cpu_to_hc32(fotg210, (u32)(addr >> 32));
--	count = 0x1000 - (buf & 0x0fff);	/* rest of that page */
--	if (likely(len < count))		/* ... iff needed */
--		count = len;
--	else {
--		buf +=  0x1000;
--		buf &= ~0x0fff;
--
--		/* per-qtd limit: from 16K to 20K (best alignment) */
--		for (i = 1; count < len && i < 5; i++) {
--			addr = buf;
--			qtd->hw_buf[i] = cpu_to_hc32(fotg210, (u32)addr);
--			qtd->hw_buf_hi[i] = cpu_to_hc32(fotg210,
--					(u32)(addr >> 32));
--			buf += 0x1000;
--			if ((count + 0x1000) < len)
--				count += 0x1000;
--			else
--				count = len;
--		}
--
--		/* short packets may only terminate transfers */
--		if (count != len)
--			count -= (count % maxpacket);
--	}
--	qtd->hw_token = cpu_to_hc32(fotg210, (count << 16) | token);
--	qtd->length = count;
--
--	return count;
--}
--
--static inline void qh_update(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh, struct fotg210_qtd *qtd)
--{
--	struct fotg210_qh_hw *hw = qh->hw;
--
--	/* writes to an active overlay are unsafe */
--	BUG_ON(qh->qh_state != QH_STATE_IDLE);
--
--	hw->hw_qtd_next = QTD_NEXT(fotg210, qtd->qtd_dma);
--	hw->hw_alt_next = FOTG210_LIST_END(fotg210);
--
--	/* Except for control endpoints, we make hardware maintain data
--	 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
--	 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
--	 * ever clear it.
--	 */
--	if (!(hw->hw_info1 & cpu_to_hc32(fotg210, QH_TOGGLE_CTL))) {
--		unsigned is_out, epnum;
--
--		is_out = qh->is_out;
--		epnum = (hc32_to_cpup(fotg210, &hw->hw_info1) >> 8) & 0x0f;
--		if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
--			hw->hw_token &= ~cpu_to_hc32(fotg210, QTD_TOGGLE);
--			usb_settoggle(qh->dev, epnum, is_out, 1);
--		}
--	}
--
--	hw->hw_token &= cpu_to_hc32(fotg210, QTD_TOGGLE | QTD_STS_PING);
--}
--
--/* if it weren't for a common silicon quirk (writing the dummy into the qh
-- * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
-- * recovery (including urb dequeue) would need software changes to a QH...
-- */
--static void qh_refresh(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	struct fotg210_qtd *qtd;
--
--	if (list_empty(&qh->qtd_list))
--		qtd = qh->dummy;
--	else {
--		qtd = list_entry(qh->qtd_list.next,
--				struct fotg210_qtd, qtd_list);
--		/*
--		 * first qtd may already be partially processed.
--		 * If we come here during unlink, the QH overlay region
--		 * might have reference to the just unlinked qtd. The
--		 * qtd is updated in qh_completions(). Update the QH
--		 * overlay here.
--		 */
--		if (cpu_to_hc32(fotg210, qtd->qtd_dma) == qh->hw->hw_current) {
--			qh->hw->hw_qtd_next = qtd->hw_next;
--			qtd = NULL;
--		}
--	}
--
--	if (qtd)
--		qh_update(fotg210, qh, qtd);
--}
--
--static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--static void fotg210_clear_tt_buffer_complete(struct usb_hcd *hcd,
--		struct usb_host_endpoint *ep)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	struct fotg210_qh *qh = ep->hcpriv;
--	unsigned long flags;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	qh->clearing_tt = 0;
--	if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list)
--			&& fotg210->rh_state == FOTG210_RH_RUNNING)
--		qh_link_async(fotg210, qh);
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static void fotg210_clear_tt_buffer(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh, struct urb *urb, u32 token)
--{
--
--	/* If an async split transaction gets an error or is unlinked,
--	 * the TT buffer may be left in an indeterminate state.  We
--	 * have to clear the TT buffer.
--	 *
--	 * Note: this routine is never called for Isochronous transfers.
--	 */
--	if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) {
--		struct usb_device *tt = urb->dev->tt->hub;
--
--		dev_dbg(&tt->dev,
--				"clear tt buffer port %d, a%d ep%d t%08x\n",
--				urb->dev->ttport, urb->dev->devnum,
--				usb_pipeendpoint(urb->pipe), token);
--
--		if (urb->dev->tt->hub !=
--				fotg210_to_hcd(fotg210)->self.root_hub) {
--			if (usb_hub_clear_tt_buffer(urb) == 0)
--				qh->clearing_tt = 1;
--		}
--	}
--}
--
--static int qtd_copy_status(struct fotg210_hcd *fotg210, struct urb *urb,
--		size_t length, u32 token)
--{
--	int status = -EINPROGRESS;
--
--	/* count IN/OUT bytes, not SETUP (even short packets) */
--	if (likely(QTD_PID(token) != 2))
--		urb->actual_length += length - QTD_LENGTH(token);
--
--	/* don't modify error codes */
--	if (unlikely(urb->unlinked))
--		return status;
--
--	/* force cleanup after short read; not always an error */
--	if (unlikely(IS_SHORT_READ(token)))
--		status = -EREMOTEIO;
--
--	/* serious "can't proceed" faults reported by the hardware */
--	if (token & QTD_STS_HALT) {
--		if (token & QTD_STS_BABBLE) {
--			/* FIXME "must" disable babbling device's port too */
--			status = -EOVERFLOW;
--		/* CERR nonzero + halt --> stall */
--		} else if (QTD_CERR(token)) {
--			status = -EPIPE;
--
--		/* In theory, more than one of the following bits can be set
--		 * since they are sticky and the transaction is retried.
--		 * Which to test first is rather arbitrary.
--		 */
--		} else if (token & QTD_STS_MMF) {
--			/* fs/ls interrupt xfer missed the complete-split */
--			status = -EPROTO;
--		} else if (token & QTD_STS_DBE) {
--			status = (QTD_PID(token) == 1) /* IN ? */
--				? -ENOSR  /* hc couldn't read data */
--				: -ECOMM; /* hc couldn't write data */
--		} else if (token & QTD_STS_XACT) {
--			/* timeout, bad CRC, wrong PID, etc */
--			fotg210_dbg(fotg210, "devpath %s ep%d%s 3strikes\n",
--					urb->dev->devpath,
--					usb_pipeendpoint(urb->pipe),
--					usb_pipein(urb->pipe) ? "in" : "out");
--			status = -EPROTO;
--		} else {	/* unknown */
--			status = -EPROTO;
--		}
--
--		fotg210_dbg(fotg210,
--				"dev%d ep%d%s qtd token %08x --> status %d\n",
--				usb_pipedevice(urb->pipe),
--				usb_pipeendpoint(urb->pipe),
--				usb_pipein(urb->pipe) ? "in" : "out",
--				token, status);
--	}
--
--	return status;
--}
--
--static void fotg210_urb_done(struct fotg210_hcd *fotg210, struct urb *urb,
--		int status)
--__releases(fotg210->lock)
--__acquires(fotg210->lock)
--{
--	if (likely(urb->hcpriv != NULL)) {
--		struct fotg210_qh *qh = (struct fotg210_qh *) urb->hcpriv;
--
--		/* S-mask in a QH means it's an interrupt urb */
--		if ((qh->hw->hw_info2 & cpu_to_hc32(fotg210, QH_SMASK)) != 0) {
--
--			/* ... update hc-wide periodic stats (for usbfs) */
--			fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs--;
--		}
--	}
--
--	if (unlikely(urb->unlinked)) {
--		INCR(fotg210->stats.unlink);
--	} else {
--		/* report non-error and short read status as zero */
--		if (status == -EINPROGRESS || status == -EREMOTEIO)
--			status = 0;
--		INCR(fotg210->stats.complete);
--	}
--
--#ifdef FOTG210_URB_TRACE
--	fotg210_dbg(fotg210,
--			"%s %s urb %p ep%d%s status %d len %d/%d\n",
--			__func__, urb->dev->devpath, urb,
--			usb_pipeendpoint(urb->pipe),
--			usb_pipein(urb->pipe) ? "in" : "out",
--			status,
--			urb->actual_length, urb->transfer_buffer_length);
--#endif
--
--	/* complete() can reenter this HCD */
--	usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--	spin_unlock(&fotg210->lock);
--	usb_hcd_giveback_urb(fotg210_to_hcd(fotg210), urb, status);
--	spin_lock(&fotg210->lock);
--}
--
--static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--/* Process and free completed qtds for a qh, returning URBs to drivers.
-- * Chases up to qh->hw_current.  Returns number of completions called,
-- * indicating how much "real" work we did.
-- */
--static unsigned qh_completions(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh)
--{
--	struct fotg210_qtd *last, *end = qh->dummy;
--	struct fotg210_qtd *qtd, *tmp;
--	int last_status;
--	int stopped;
--	unsigned count = 0;
--	u8 state;
--	struct fotg210_qh_hw *hw = qh->hw;
--
--	if (unlikely(list_empty(&qh->qtd_list)))
--		return count;
--
--	/* completions (or tasks on other cpus) must never clobber HALT
--	 * till we've gone through and cleaned everything up, even when
--	 * they add urbs to this qh's queue or mark them for unlinking.
--	 *
--	 * NOTE:  unlinking expects to be done in queue order.
--	 *
--	 * It's a bug for qh->qh_state to be anything other than
--	 * QH_STATE_IDLE, unless our caller is scan_async() or
--	 * scan_intr().
--	 */
--	state = qh->qh_state;
--	qh->qh_state = QH_STATE_COMPLETING;
--	stopped = (state == QH_STATE_IDLE);
--
--rescan:
--	last = NULL;
--	last_status = -EINPROGRESS;
--	qh->needs_rescan = 0;
--
--	/* remove de-activated QTDs from front of queue.
--	 * after faults (including short reads), cleanup this urb
--	 * then let the queue advance.
--	 * if queue is stopped, handles unlinks.
--	 */
--	list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) {
--		struct urb *urb;
--		u32 token = 0;
--
--		urb = qtd->urb;
--
--		/* clean up any state from previous QTD ...*/
--		if (last) {
--			if (likely(last->urb != urb)) {
--				fotg210_urb_done(fotg210, last->urb,
--						last_status);
--				count++;
--				last_status = -EINPROGRESS;
--			}
--			fotg210_qtd_free(fotg210, last);
--			last = NULL;
--		}
--
--		/* ignore urbs submitted during completions we reported */
--		if (qtd == end)
--			break;
--
--		/* hardware copies qtd out of qh overlay */
--		rmb();
--		token = hc32_to_cpu(fotg210, qtd->hw_token);
--
--		/* always clean up qtds the hc de-activated */
--retry_xacterr:
--		if ((token & QTD_STS_ACTIVE) == 0) {
--
--			/* Report Data Buffer Error: non-fatal but useful */
--			if (token & QTD_STS_DBE)
--				fotg210_dbg(fotg210,
--					"detected DataBufferErr for urb %p ep%d%s len %d, qtd %p [qh %p]\n",
--					urb, usb_endpoint_num(&urb->ep->desc),
--					usb_endpoint_dir_in(&urb->ep->desc)
--						? "in" : "out",
--					urb->transfer_buffer_length, qtd, qh);
--
--			/* on STALL, error, and short reads this urb must
--			 * complete and all its qtds must be recycled.
--			 */
--			if ((token & QTD_STS_HALT) != 0) {
--
--				/* retry transaction errors until we
--				 * reach the software xacterr limit
--				 */
--				if ((token & QTD_STS_XACT) &&
--						QTD_CERR(token) == 0 &&
--						++qh->xacterrs < QH_XACTERR_MAX &&
--						!urb->unlinked) {
--					fotg210_dbg(fotg210,
--						"detected XactErr len %zu/%zu retry %d\n",
--						qtd->length - QTD_LENGTH(token),
--						qtd->length,
--						qh->xacterrs);
--
--					/* reset the token in the qtd and the
--					 * qh overlay (which still contains
--					 * the qtd) so that we pick up from
--					 * where we left off
--					 */
--					token &= ~QTD_STS_HALT;
--					token |= QTD_STS_ACTIVE |
--						 (FOTG210_TUNE_CERR << 10);
--					qtd->hw_token = cpu_to_hc32(fotg210,
--							token);
--					wmb();
--					hw->hw_token = cpu_to_hc32(fotg210,
--							token);
--					goto retry_xacterr;
--				}
--				stopped = 1;
--
--			/* magic dummy for some short reads; qh won't advance.
--			 * that silicon quirk can kick in with this dummy too.
--			 *
--			 * other short reads won't stop the queue, including
--			 * control transfers (status stage handles that) or
--			 * most other single-qtd reads ... the queue stops if
--			 * URB_SHORT_NOT_OK was set so the driver submitting
--			 * the urbs could clean it up.
--			 */
--			} else if (IS_SHORT_READ(token) &&
--					!(qtd->hw_alt_next &
--					FOTG210_LIST_END(fotg210))) {
--				stopped = 1;
--			}
--
--		/* stop scanning when we reach qtds the hc is using */
--		} else if (likely(!stopped
--				&& fotg210->rh_state >= FOTG210_RH_RUNNING)) {
--			break;
--
--		/* scan the whole queue for unlinks whenever it stops */
--		} else {
--			stopped = 1;
--
--			/* cancel everything if we halt, suspend, etc */
--			if (fotg210->rh_state < FOTG210_RH_RUNNING)
--				last_status = -ESHUTDOWN;
--
--			/* this qtd is active; skip it unless a previous qtd
--			 * for its urb faulted, or its urb was canceled.
--			 */
--			else if (last_status == -EINPROGRESS && !urb->unlinked)
--				continue;
--
--			/* qh unlinked; token in overlay may be most current */
--			if (state == QH_STATE_IDLE &&
--					cpu_to_hc32(fotg210, qtd->qtd_dma)
--					== hw->hw_current) {
--				token = hc32_to_cpu(fotg210, hw->hw_token);
--
--				/* An unlink may leave an incomplete
--				 * async transaction in the TT buffer.
--				 * We have to clear it.
--				 */
--				fotg210_clear_tt_buffer(fotg210, qh, urb,
--						token);
--			}
--		}
--
--		/* unless we already know the urb's status, collect qtd status
--		 * and update count of bytes transferred.  in common short read
--		 * cases with only one data qtd (including control transfers),
--		 * queue processing won't halt.  but with two or more qtds (for
--		 * example, with a 32 KB transfer), when the first qtd gets a
--		 * short read the second must be removed by hand.
--		 */
--		if (last_status == -EINPROGRESS) {
--			last_status = qtd_copy_status(fotg210, urb,
--					qtd->length, token);
--			if (last_status == -EREMOTEIO &&
--					(qtd->hw_alt_next &
--					FOTG210_LIST_END(fotg210)))
--				last_status = -EINPROGRESS;
--
--			/* As part of low/full-speed endpoint-halt processing
--			 * we must clear the TT buffer (11.17.5).
--			 */
--			if (unlikely(last_status != -EINPROGRESS &&
--					last_status != -EREMOTEIO)) {
--				/* The TT's in some hubs malfunction when they
--				 * receive this request following a STALL (they
--				 * stop sending isochronous packets).  Since a
--				 * STALL can't leave the TT buffer in a busy
--				 * state (if you believe Figures 11-48 - 11-51
--				 * in the USB 2.0 spec), we won't clear the TT
--				 * buffer in this case.  Strictly speaking this
--				 * is a violation of the spec.
--				 */
--				if (last_status != -EPIPE)
--					fotg210_clear_tt_buffer(fotg210, qh,
--							urb, token);
--			}
--		}
--
--		/* if we're removing something not at the queue head,
--		 * patch the hardware queue pointer.
--		 */
--		if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
--			last = list_entry(qtd->qtd_list.prev,
--					struct fotg210_qtd, qtd_list);
--			last->hw_next = qtd->hw_next;
--		}
--
--		/* remove qtd; it's recycled after possible urb completion */
--		list_del(&qtd->qtd_list);
--		last = qtd;
--
--		/* reinit the xacterr counter for the next qtd */
--		qh->xacterrs = 0;
--	}
--
--	/* last urb's completion might still need calling */
--	if (likely(last != NULL)) {
--		fotg210_urb_done(fotg210, last->urb, last_status);
--		count++;
--		fotg210_qtd_free(fotg210, last);
--	}
--
--	/* Do we need to rescan for URBs dequeued during a giveback? */
--	if (unlikely(qh->needs_rescan)) {
--		/* If the QH is already unlinked, do the rescan now. */
--		if (state == QH_STATE_IDLE)
--			goto rescan;
--
--		/* Otherwise we have to wait until the QH is fully unlinked.
--		 * Our caller will start an unlink if qh->needs_rescan is
--		 * set.  But if an unlink has already started, nothing needs
--		 * to be done.
--		 */
--		if (state != QH_STATE_LINKED)
--			qh->needs_rescan = 0;
--	}
--
--	/* restore original state; caller must unlink or relink */
--	qh->qh_state = state;
--
--	/* be sure the hardware's done with the qh before refreshing
--	 * it after fault cleanup, or recovering from silicon wrongly
--	 * overlaying the dummy qtd (which reduces DMA chatter).
--	 */
--	if (stopped != 0 || hw->hw_qtd_next == FOTG210_LIST_END(fotg210)) {
--		switch (state) {
--		case QH_STATE_IDLE:
--			qh_refresh(fotg210, qh);
--			break;
--		case QH_STATE_LINKED:
--			/* We won't refresh a QH that's linked (after the HC
--			 * stopped the queue).  That avoids a race:
--			 *  - HC reads first part of QH;
--			 *  - CPU updates that first part and the token;
--			 *  - HC reads rest of that QH, including token
--			 * Result:  HC gets an inconsistent image, and then
--			 * DMAs to/from the wrong memory (corrupting it).
--			 *
--			 * That should be rare for interrupt transfers,
--			 * except maybe high bandwidth ...
--			 */
--
--			/* Tell the caller to start an unlink */
--			qh->needs_rescan = 1;
--			break;
--		/* otherwise, unlink already started */
--		}
--	}
--
--	return count;
--}
--
--/* reverse of qh_urb_transaction:  free a list of TDs.
-- * used for cleanup after errors, before HC sees an URB's TDs.
-- */
--static void qtd_list_free(struct fotg210_hcd *fotg210, struct urb *urb,
--		struct list_head *head)
--{
--	struct fotg210_qtd *qtd, *temp;
--
--	list_for_each_entry_safe(qtd, temp, head, qtd_list) {
--		list_del(&qtd->qtd_list);
--		fotg210_qtd_free(fotg210, qtd);
--	}
--}
--
--/* create a list of filled qtds for this URB; won't link into qh.
-- */
--static struct list_head *qh_urb_transaction(struct fotg210_hcd *fotg210,
--		struct urb *urb, struct list_head *head, gfp_t flags)
--{
--	struct fotg210_qtd *qtd, *qtd_prev;
--	dma_addr_t buf;
--	int len, this_sg_len, maxpacket;
--	int is_input;
--	u32 token;
--	int i;
--	struct scatterlist *sg;
--
--	/*
--	 * URBs map to sequences of QTDs:  one logical transaction
--	 */
--	qtd = fotg210_qtd_alloc(fotg210, flags);
--	if (unlikely(!qtd))
--		return NULL;
--	list_add_tail(&qtd->qtd_list, head);
--	qtd->urb = urb;
--
--	token = QTD_STS_ACTIVE;
--	token |= (FOTG210_TUNE_CERR << 10);
--	/* for split transactions, SplitXState initialized to zero */
--
--	len = urb->transfer_buffer_length;
--	is_input = usb_pipein(urb->pipe);
--	if (usb_pipecontrol(urb->pipe)) {
--		/* SETUP pid */
--		qtd_fill(fotg210, qtd, urb->setup_dma,
--				sizeof(struct usb_ctrlrequest),
--				token | (2 /* "setup" */ << 8), 8);
--
--		/* ... and always at least one more pid */
--		token ^= QTD_TOGGLE;
--		qtd_prev = qtd;
--		qtd = fotg210_qtd_alloc(fotg210, flags);
--		if (unlikely(!qtd))
--			goto cleanup;
--		qtd->urb = urb;
--		qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
--		list_add_tail(&qtd->qtd_list, head);
--
--		/* for zero length DATA stages, STATUS is always IN */
--		if (len == 0)
--			token |= (1 /* "in" */ << 8);
--	}
--
--	/*
--	 * data transfer stage:  buffer setup
--	 */
--	i = urb->num_mapped_sgs;
--	if (len > 0 && i > 0) {
--		sg = urb->sg;
--		buf = sg_dma_address(sg);
--
--		/* urb->transfer_buffer_length may be smaller than the
--		 * size of the scatterlist (or vice versa)
--		 */
--		this_sg_len = min_t(int, sg_dma_len(sg), len);
--	} else {
--		sg = NULL;
--		buf = urb->transfer_dma;
--		this_sg_len = len;
--	}
--
--	if (is_input)
--		token |= (1 /* "in" */ << 8);
--	/* else it's already initted to "out" pid (0 << 8) */
--
--	maxpacket = usb_maxpacket(urb->dev, urb->pipe);
--
--	/*
--	 * buffer gets wrapped in one or more qtds;
--	 * last one may be "short" (including zero len)
--	 * and may serve as a control status ack
--	 */
--	for (;;) {
--		int this_qtd_len;
--
--		this_qtd_len = qtd_fill(fotg210, qtd, buf, this_sg_len, token,
--				maxpacket);
--		this_sg_len -= this_qtd_len;
--		len -= this_qtd_len;
--		buf += this_qtd_len;
--
--		/*
--		 * short reads advance to a "magic" dummy instead of the next
--		 * qtd ... that forces the queue to stop, for manual cleanup.
--		 * (this will usually be overridden later.)
--		 */
--		if (is_input)
--			qtd->hw_alt_next = fotg210->async->hw->hw_alt_next;
--
--		/* qh makes control packets use qtd toggle; maybe switch it */
--		if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
--			token ^= QTD_TOGGLE;
--
--		if (likely(this_sg_len <= 0)) {
--			if (--i <= 0 || len <= 0)
--				break;
--			sg = sg_next(sg);
--			buf = sg_dma_address(sg);
--			this_sg_len = min_t(int, sg_dma_len(sg), len);
--		}
--
--		qtd_prev = qtd;
--		qtd = fotg210_qtd_alloc(fotg210, flags);
--		if (unlikely(!qtd))
--			goto cleanup;
--		qtd->urb = urb;
--		qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
--		list_add_tail(&qtd->qtd_list, head);
--	}
--
--	/*
--	 * unless the caller requires manual cleanup after short reads,
--	 * have the alt_next mechanism keep the queue running after the
--	 * last data qtd (the only one, for control and most other cases).
--	 */
--	if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 ||
--			usb_pipecontrol(urb->pipe)))
--		qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
--
--	/*
--	 * control requests may need a terminating data "status" ack;
--	 * other OUT ones may need a terminating short packet
--	 * (zero length).
--	 */
--	if (likely(urb->transfer_buffer_length != 0)) {
--		int one_more = 0;
--
--		if (usb_pipecontrol(urb->pipe)) {
--			one_more = 1;
--			token ^= 0x0100;	/* "in" <--> "out"  */
--			token |= QTD_TOGGLE;	/* force DATA1 */
--		} else if (usb_pipeout(urb->pipe)
--				&& (urb->transfer_flags & URB_ZERO_PACKET)
--				&& !(urb->transfer_buffer_length % maxpacket)) {
--			one_more = 1;
--		}
--		if (one_more) {
--			qtd_prev = qtd;
--			qtd = fotg210_qtd_alloc(fotg210, flags);
--			if (unlikely(!qtd))
--				goto cleanup;
--			qtd->urb = urb;
--			qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
--			list_add_tail(&qtd->qtd_list, head);
--
--			/* never any data in such packets */
--			qtd_fill(fotg210, qtd, 0, 0, token, 0);
--		}
--	}
--
--	/* by default, enable interrupt on urb completion */
--	if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
--		qtd->hw_token |= cpu_to_hc32(fotg210, QTD_IOC);
--	return head;
--
--cleanup:
--	qtd_list_free(fotg210, urb, head);
--	return NULL;
--}
--
--/* Would be best to create all qh's from config descriptors,
-- * when each interface/altsetting is established.  Unlink
-- * any previous qh and cancel its urbs first; endpoints are
-- * implicitly reset then (data toggle too).
-- * That'd mean updating how usbcore talks to HCDs. (2.7?)
-- */
--
--
--/* Each QH holds a qtd list; a QH is used for everything except iso.
-- *
-- * For interrupt urbs, the scheduler must set the microframe scheduling
-- * mask(s) each time the QH gets scheduled.  For highspeed, that's
-- * just one microframe in the s-mask.  For split interrupt transactions
-- * there are additional complications: c-mask, maybe FSTNs.
-- */
--static struct fotg210_qh *qh_make(struct fotg210_hcd *fotg210, struct urb *urb,
--		gfp_t flags)
--{
--	struct fotg210_qh *qh = fotg210_qh_alloc(fotg210, flags);
--	struct usb_host_endpoint *ep;
--	u32 info1 = 0, info2 = 0;
--	int is_input, type;
--	int maxp = 0;
--	int mult;
--	struct usb_tt *tt = urb->dev->tt;
--	struct fotg210_qh_hw *hw;
--
--	if (!qh)
--		return qh;
--
--	/*
--	 * init endpoint/device data for this QH
--	 */
--	info1 |= usb_pipeendpoint(urb->pipe) << 8;
--	info1 |= usb_pipedevice(urb->pipe) << 0;
--
--	is_input = usb_pipein(urb->pipe);
--	type = usb_pipetype(urb->pipe);
--	ep = usb_pipe_endpoint(urb->dev, urb->pipe);
--	maxp = usb_endpoint_maxp(&ep->desc);
--	mult = usb_endpoint_maxp_mult(&ep->desc);
--
--	/* 1024 byte maxpacket is a hardware ceiling.  High bandwidth
--	 * acts like up to 3KB, but is built from smaller packets.
--	 */
--	if (maxp > 1024) {
--		fotg210_dbg(fotg210, "bogus qh maxpacket %d\n", maxp);
--		goto done;
--	}
--
--	/* Compute interrupt scheduling parameters just once, and save.
--	 * - allowing for high bandwidth, how many nsec/uframe are used?
--	 * - split transactions need a second CSPLIT uframe; same question
--	 * - splits also need a schedule gap (for full/low speed I/O)
--	 * - qh has a polling interval
--	 *
--	 * For control/bulk requests, the HC or TT handles these.
--	 */
--	if (type == PIPE_INTERRUPT) {
--		qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
--				is_input, 0, mult * maxp));
--		qh->start = NO_FRAME;
--
--		if (urb->dev->speed == USB_SPEED_HIGH) {
--			qh->c_usecs = 0;
--			qh->gap_uf = 0;
--
--			qh->period = urb->interval >> 3;
--			if (qh->period == 0 && urb->interval != 1) {
--				/* NOTE interval 2 or 4 uframes could work.
--				 * But interval 1 scheduling is simpler, and
--				 * includes high bandwidth.
--				 */
--				urb->interval = 1;
--			} else if (qh->period > fotg210->periodic_size) {
--				qh->period = fotg210->periodic_size;
--				urb->interval = qh->period << 3;
--			}
--		} else {
--			int think_time;
--
--			/* gap is f(FS/LS transfer times) */
--			qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
--					is_input, 0, maxp) / (125 * 1000);
--
--			/* FIXME this just approximates SPLIT/CSPLIT times */
--			if (is_input) {		/* SPLIT, gap, CSPLIT+DATA */
--				qh->c_usecs = qh->usecs + HS_USECS(0);
--				qh->usecs = HS_USECS(1);
--			} else {		/* SPLIT+DATA, gap, CSPLIT */
--				qh->usecs += HS_USECS(1);
--				qh->c_usecs = HS_USECS(0);
--			}
--
--			think_time = tt ? tt->think_time : 0;
--			qh->tt_usecs = NS_TO_US(think_time +
--					usb_calc_bus_time(urb->dev->speed,
--					is_input, 0, maxp));
--			qh->period = urb->interval;
--			if (qh->period > fotg210->periodic_size) {
--				qh->period = fotg210->periodic_size;
--				urb->interval = qh->period;
--			}
--		}
--	}
--
--	/* support for tt scheduling, and access to toggles */
--	qh->dev = urb->dev;
--
--	/* using TT? */
--	switch (urb->dev->speed) {
--	case USB_SPEED_LOW:
--		info1 |= QH_LOW_SPEED;
--		fallthrough;
--
--	case USB_SPEED_FULL:
--		/* EPS 0 means "full" */
--		if (type != PIPE_INTERRUPT)
--			info1 |= (FOTG210_TUNE_RL_TT << 28);
--		if (type == PIPE_CONTROL) {
--			info1 |= QH_CONTROL_EP;		/* for TT */
--			info1 |= QH_TOGGLE_CTL;		/* toggle from qtd */
--		}
--		info1 |= maxp << 16;
--
--		info2 |= (FOTG210_TUNE_MULT_TT << 30);
--
--		/* Some Freescale processors have an erratum in which the
--		 * port number in the queue head was 0..N-1 instead of 1..N.
--		 */
--		if (fotg210_has_fsl_portno_bug(fotg210))
--			info2 |= (urb->dev->ttport-1) << 23;
--		else
--			info2 |= urb->dev->ttport << 23;
--
--		/* set the address of the TT; for TDI's integrated
--		 * root hub tt, leave it zeroed.
--		 */
--		if (tt && tt->hub != fotg210_to_hcd(fotg210)->self.root_hub)
--			info2 |= tt->hub->devnum << 16;
--
--		/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
--
--		break;
--
--	case USB_SPEED_HIGH:		/* no TT involved */
--		info1 |= QH_HIGH_SPEED;
--		if (type == PIPE_CONTROL) {
--			info1 |= (FOTG210_TUNE_RL_HS << 28);
--			info1 |= 64 << 16;	/* usb2 fixed maxpacket */
--			info1 |= QH_TOGGLE_CTL;	/* toggle from qtd */
--			info2 |= (FOTG210_TUNE_MULT_HS << 30);
--		} else if (type == PIPE_BULK) {
--			info1 |= (FOTG210_TUNE_RL_HS << 28);
--			/* The USB spec says that high speed bulk endpoints
--			 * always use 512 byte maxpacket.  But some device
--			 * vendors decided to ignore that, and MSFT is happy
--			 * to help them do so.  So now people expect to use
--			 * such nonconformant devices with Linux too; sigh.
--			 */
--			info1 |= maxp << 16;
--			info2 |= (FOTG210_TUNE_MULT_HS << 30);
--		} else {		/* PIPE_INTERRUPT */
--			info1 |= maxp << 16;
--			info2 |= mult << 30;
--		}
--		break;
--	default:
--		fotg210_dbg(fotg210, "bogus dev %p speed %d\n", urb->dev,
--				urb->dev->speed);
--done:
--		qh_destroy(fotg210, qh);
--		return NULL;
--	}
--
--	/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
--
--	/* init as live, toggle clear, advance to dummy */
--	qh->qh_state = QH_STATE_IDLE;
--	hw = qh->hw;
--	hw->hw_info1 = cpu_to_hc32(fotg210, info1);
--	hw->hw_info2 = cpu_to_hc32(fotg210, info2);
--	qh->is_out = !is_input;
--	usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
--	qh_refresh(fotg210, qh);
--	return qh;
--}
--
--static void enable_async(struct fotg210_hcd *fotg210)
--{
--	if (fotg210->async_count++)
--		return;
--
--	/* Stop waiting to turn off the async schedule */
--	fotg210->enabled_hrtimer_events &= ~BIT(FOTG210_HRTIMER_DISABLE_ASYNC);
--
--	/* Don't start the schedule until ASS is 0 */
--	fotg210_poll_ASS(fotg210);
--	turn_on_io_watchdog(fotg210);
--}
--
--static void disable_async(struct fotg210_hcd *fotg210)
--{
--	if (--fotg210->async_count)
--		return;
--
--	/* The async schedule and async_unlink list are supposed to be empty */
--	WARN_ON(fotg210->async->qh_next.qh || fotg210->async_unlink);
--
--	/* Don't turn off the schedule until ASS is 1 */
--	fotg210_poll_ASS(fotg210);
--}
--
--/* move qh (and its qtds) onto async queue; maybe enable queue.  */
--
--static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	__hc32 dma = QH_NEXT(fotg210, qh->qh_dma);
--	struct fotg210_qh *head;
--
--	/* Don't link a QH if there's a Clear-TT-Buffer pending */
--	if (unlikely(qh->clearing_tt))
--		return;
--
--	WARN_ON(qh->qh_state != QH_STATE_IDLE);
--
--	/* clear halt and/or toggle; and maybe recover from silicon quirk */
--	qh_refresh(fotg210, qh);
--
--	/* splice right after start */
--	head = fotg210->async;
--	qh->qh_next = head->qh_next;
--	qh->hw->hw_next = head->hw->hw_next;
--	wmb();
--
--	head->qh_next.qh = qh;
--	head->hw->hw_next = dma;
--
--	qh->xacterrs = 0;
--	qh->qh_state = QH_STATE_LINKED;
--	/* qtd completions reported later by interrupt */
--
--	enable_async(fotg210);
--}
--
--/* For control/bulk/interrupt, return QH with these TDs appended.
-- * Allocates and initializes the QH if necessary.
-- * Returns null if it can't allocate a QH it needs to.
-- * If the QH has TDs (urbs) already, that's great.
-- */
--static struct fotg210_qh *qh_append_tds(struct fotg210_hcd *fotg210,
--		struct urb *urb, struct list_head *qtd_list,
--		int epnum, void **ptr)
--{
--	struct fotg210_qh *qh = NULL;
--	__hc32 qh_addr_mask = cpu_to_hc32(fotg210, 0x7f);
--
--	qh = (struct fotg210_qh *) *ptr;
--	if (unlikely(qh == NULL)) {
--		/* can't sleep here, we have fotg210->lock... */
--		qh = qh_make(fotg210, urb, GFP_ATOMIC);
--		*ptr = qh;
--	}
--	if (likely(qh != NULL)) {
--		struct fotg210_qtd *qtd;
--
--		if (unlikely(list_empty(qtd_list)))
--			qtd = NULL;
--		else
--			qtd = list_entry(qtd_list->next, struct fotg210_qtd,
--					qtd_list);
--
--		/* control qh may need patching ... */
--		if (unlikely(epnum == 0)) {
--			/* usb_reset_device() briefly reverts to address 0 */
--			if (usb_pipedevice(urb->pipe) == 0)
--				qh->hw->hw_info1 &= ~qh_addr_mask;
--		}
--
--		/* just one way to queue requests: swap with the dummy qtd.
--		 * only hc or qh_refresh() ever modify the overlay.
--		 */
--		if (likely(qtd != NULL)) {
--			struct fotg210_qtd *dummy;
--			dma_addr_t dma;
--			__hc32 token;
--
--			/* to avoid racing the HC, use the dummy td instead of
--			 * the first td of our list (becomes new dummy).  both
--			 * tds stay deactivated until we're done, when the
--			 * HC is allowed to fetch the old dummy (4.10.2).
--			 */
--			token = qtd->hw_token;
--			qtd->hw_token = HALT_BIT(fotg210);
--
--			dummy = qh->dummy;
--
--			dma = dummy->qtd_dma;
--			*dummy = *qtd;
--			dummy->qtd_dma = dma;
--
--			list_del(&qtd->qtd_list);
--			list_add(&dummy->qtd_list, qtd_list);
--			list_splice_tail(qtd_list, &qh->qtd_list);
--
--			fotg210_qtd_init(fotg210, qtd, qtd->qtd_dma);
--			qh->dummy = qtd;
--
--			/* hc must see the new dummy at list end */
--			dma = qtd->qtd_dma;
--			qtd = list_entry(qh->qtd_list.prev,
--					struct fotg210_qtd, qtd_list);
--			qtd->hw_next = QTD_NEXT(fotg210, dma);
--
--			/* let the hc process these next qtds */
--			wmb();
--			dummy->hw_token = token;
--
--			urb->hcpriv = qh;
--		}
--	}
--	return qh;
--}
--
--static int submit_async(struct fotg210_hcd *fotg210, struct urb *urb,
--		struct list_head *qtd_list, gfp_t mem_flags)
--{
--	int epnum;
--	unsigned long flags;
--	struct fotg210_qh *qh = NULL;
--	int rc;
--
--	epnum = urb->ep->desc.bEndpointAddress;
--
--#ifdef FOTG210_URB_TRACE
--	{
--		struct fotg210_qtd *qtd;
--
--		qtd = list_entry(qtd_list->next, struct fotg210_qtd, qtd_list);
--		fotg210_dbg(fotg210,
--				"%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
--				__func__, urb->dev->devpath, urb,
--				epnum & 0x0f, (epnum & USB_DIR_IN)
--					? "in" : "out",
--				urb->transfer_buffer_length,
--				qtd, urb->ep->hcpriv);
--	}
--#endif
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
--		rc = -ESHUTDOWN;
--		goto done;
--	}
--	rc = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
--	if (unlikely(rc))
--		goto done;
--
--	qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
--	if (unlikely(qh == NULL)) {
--		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--		rc = -ENOMEM;
--		goto done;
--	}
--
--	/* Control/bulk operations through TTs don't need scheduling,
--	 * the HC and TT handle it when the TT has a buffer ready.
--	 */
--	if (likely(qh->qh_state == QH_STATE_IDLE))
--		qh_link_async(fotg210, qh);
--done:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	if (unlikely(qh == NULL))
--		qtd_list_free(fotg210, urb, qtd_list);
--	return rc;
--}
--
--static void single_unlink_async(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh)
--{
--	struct fotg210_qh *prev;
--
--	/* Add to the end of the list of QHs waiting for the next IAAD */
--	qh->qh_state = QH_STATE_UNLINK;
--	if (fotg210->async_unlink)
--		fotg210->async_unlink_last->unlink_next = qh;
--	else
--		fotg210->async_unlink = qh;
--	fotg210->async_unlink_last = qh;
--
--	/* Unlink it from the schedule */
--	prev = fotg210->async;
--	while (prev->qh_next.qh != qh)
--		prev = prev->qh_next.qh;
--
--	prev->hw->hw_next = qh->hw->hw_next;
--	prev->qh_next = qh->qh_next;
--	if (fotg210->qh_scan_next == qh)
--		fotg210->qh_scan_next = qh->qh_next.qh;
--}
--
--static void start_iaa_cycle(struct fotg210_hcd *fotg210, bool nested)
--{
--	/*
--	 * Do nothing if an IAA cycle is already running or
--	 * if one will be started shortly.
--	 */
--	if (fotg210->async_iaa || fotg210->async_unlinking)
--		return;
--
--	/* Do all the waiting QHs at once */
--	fotg210->async_iaa = fotg210->async_unlink;
--	fotg210->async_unlink = NULL;
--
--	/* If the controller isn't running, we don't have to wait for it */
--	if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING)) {
--		if (!nested)		/* Avoid recursion */
--			end_unlink_async(fotg210);
--
--	/* Otherwise start a new IAA cycle */
--	} else if (likely(fotg210->rh_state == FOTG210_RH_RUNNING)) {
--		/* Make sure the unlinks are all visible to the hardware */
--		wmb();
--
--		fotg210_writel(fotg210, fotg210->command | CMD_IAAD,
--				&fotg210->regs->command);
--		fotg210_readl(fotg210, &fotg210->regs->command);
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_IAA_WATCHDOG,
--				true);
--	}
--}
--
--/* the async qh for the qtds being unlinked are now gone from the HC */
--
--static void end_unlink_async(struct fotg210_hcd *fotg210)
--{
--	struct fotg210_qh *qh;
--
--	/* Process the idle QHs */
--restart:
--	fotg210->async_unlinking = true;
--	while (fotg210->async_iaa) {
--		qh = fotg210->async_iaa;
--		fotg210->async_iaa = qh->unlink_next;
--		qh->unlink_next = NULL;
--
--		qh->qh_state = QH_STATE_IDLE;
--		qh->qh_next.qh = NULL;
--
--		qh_completions(fotg210, qh);
--		if (!list_empty(&qh->qtd_list) &&
--				fotg210->rh_state == FOTG210_RH_RUNNING)
--			qh_link_async(fotg210, qh);
--		disable_async(fotg210);
--	}
--	fotg210->async_unlinking = false;
--
--	/* Start a new IAA cycle if any QHs are waiting for it */
--	if (fotg210->async_unlink) {
--		start_iaa_cycle(fotg210, true);
--		if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING))
--			goto restart;
--	}
--}
--
--static void unlink_empty_async(struct fotg210_hcd *fotg210)
--{
--	struct fotg210_qh *qh, *next;
--	bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
--	bool check_unlinks_later = false;
--
--	/* Unlink all the async QHs that have been empty for a timer cycle */
--	next = fotg210->async->qh_next.qh;
--	while (next) {
--		qh = next;
--		next = qh->qh_next.qh;
--
--		if (list_empty(&qh->qtd_list) &&
--				qh->qh_state == QH_STATE_LINKED) {
--			if (!stopped && qh->unlink_cycle ==
--					fotg210->async_unlink_cycle)
--				check_unlinks_later = true;
--			else
--				single_unlink_async(fotg210, qh);
--		}
--	}
--
--	/* Start a new IAA cycle if any QHs are waiting for it */
--	if (fotg210->async_unlink)
--		start_iaa_cycle(fotg210, false);
--
--	/* QHs that haven't been empty for long enough will be handled later */
--	if (check_unlinks_later) {
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_ASYNC_UNLINKS,
--				true);
--		++fotg210->async_unlink_cycle;
--	}
--}
--
--/* makes sure the async qh will become idle */
--/* caller must own fotg210->lock */
--
--static void start_unlink_async(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh)
--{
--	/*
--	 * If the QH isn't linked then there's nothing we can do
--	 * unless we were called during a giveback, in which case
--	 * qh_completions() has to deal with it.
--	 */
--	if (qh->qh_state != QH_STATE_LINKED) {
--		if (qh->qh_state == QH_STATE_COMPLETING)
--			qh->needs_rescan = 1;
--		return;
--	}
--
--	single_unlink_async(fotg210, qh);
--	start_iaa_cycle(fotg210, false);
--}
--
--static void scan_async(struct fotg210_hcd *fotg210)
--{
--	struct fotg210_qh *qh;
--	bool check_unlinks_later = false;
--
--	fotg210->qh_scan_next = fotg210->async->qh_next.qh;
--	while (fotg210->qh_scan_next) {
--		qh = fotg210->qh_scan_next;
--		fotg210->qh_scan_next = qh->qh_next.qh;
--rescan:
--		/* clean any finished work for this qh */
--		if (!list_empty(&qh->qtd_list)) {
--			int temp;
--
--			/*
--			 * Unlinks could happen here; completion reporting
--			 * drops the lock.  That's why fotg210->qh_scan_next
--			 * always holds the next qh to scan; if the next qh
--			 * gets unlinked then fotg210->qh_scan_next is adjusted
--			 * in single_unlink_async().
--			 */
--			temp = qh_completions(fotg210, qh);
--			if (qh->needs_rescan) {
--				start_unlink_async(fotg210, qh);
--			} else if (list_empty(&qh->qtd_list)
--					&& qh->qh_state == QH_STATE_LINKED) {
--				qh->unlink_cycle = fotg210->async_unlink_cycle;
--				check_unlinks_later = true;
--			} else if (temp != 0)
--				goto rescan;
--		}
--	}
--
--	/*
--	 * Unlink empty entries, reducing DMA usage as well
--	 * as HCD schedule-scanning costs.  Delay for any qh
--	 * we just scanned, there's a not-unusual case that it
--	 * doesn't stay idle for long.
--	 */
--	if (check_unlinks_later && fotg210->rh_state == FOTG210_RH_RUNNING &&
--			!(fotg210->enabled_hrtimer_events &
--			BIT(FOTG210_HRTIMER_ASYNC_UNLINKS))) {
--		fotg210_enable_event(fotg210,
--				FOTG210_HRTIMER_ASYNC_UNLINKS, true);
--		++fotg210->async_unlink_cycle;
--	}
--}
--/* EHCI scheduled transaction support:  interrupt, iso, split iso
-- * These are called "periodic" transactions in the EHCI spec.
-- *
-- * Note that for interrupt transfers, the QH/QTD manipulation is shared
-- * with the "asynchronous" transaction support (control/bulk transfers).
-- * The only real difference is in how interrupt transfers are scheduled.
-- *
-- * For ISO, we make an "iso_stream" head to serve the same role as a QH.
-- * It keeps track of every ITD (or SITD) that's linked, and holds enough
-- * pre-calculated schedule data to make appending to the queue be quick.
-- */
--static int fotg210_get_frame(struct usb_hcd *hcd);
--
--/* periodic_next_shadow - return "next" pointer on shadow list
-- * @periodic: host pointer to qh/itd
-- * @tag: hardware tag for type of this record
-- */
--static union fotg210_shadow *periodic_next_shadow(struct fotg210_hcd *fotg210,
--		union fotg210_shadow *periodic, __hc32 tag)
--{
--	switch (hc32_to_cpu(fotg210, tag)) {
--	case Q_TYPE_QH:
--		return &periodic->qh->qh_next;
--	case Q_TYPE_FSTN:
--		return &periodic->fstn->fstn_next;
--	default:
--		return &periodic->itd->itd_next;
--	}
--}
--
--static __hc32 *shadow_next_periodic(struct fotg210_hcd *fotg210,
--		union fotg210_shadow *periodic, __hc32 tag)
--{
--	switch (hc32_to_cpu(fotg210, tag)) {
--	/* our fotg210_shadow.qh is actually software part */
--	case Q_TYPE_QH:
--		return &periodic->qh->hw->hw_next;
--	/* others are hw parts */
--	default:
--		return periodic->hw_next;
--	}
--}
--
--/* caller must hold fotg210->lock */
--static void periodic_unlink(struct fotg210_hcd *fotg210, unsigned frame,
--		void *ptr)
--{
--	union fotg210_shadow *prev_p = &fotg210->pshadow[frame];
--	__hc32 *hw_p = &fotg210->periodic[frame];
--	union fotg210_shadow here = *prev_p;
--
--	/* find predecessor of "ptr"; hw and shadow lists are in sync */
--	while (here.ptr && here.ptr != ptr) {
--		prev_p = periodic_next_shadow(fotg210, prev_p,
--				Q_NEXT_TYPE(fotg210, *hw_p));
--		hw_p = shadow_next_periodic(fotg210, &here,
--				Q_NEXT_TYPE(fotg210, *hw_p));
--		here = *prev_p;
--	}
--	/* an interrupt entry (at list end) could have been shared */
--	if (!here.ptr)
--		return;
--
--	/* update shadow and hardware lists ... the old "next" pointers
--	 * from ptr may still be in use, the caller updates them.
--	 */
--	*prev_p = *periodic_next_shadow(fotg210, &here,
--			Q_NEXT_TYPE(fotg210, *hw_p));
--
--	*hw_p = *shadow_next_periodic(fotg210, &here,
--			Q_NEXT_TYPE(fotg210, *hw_p));
--}
--
--/* how many of the uframe's 125 usecs are allocated? */
--static unsigned short periodic_usecs(struct fotg210_hcd *fotg210,
--		unsigned frame, unsigned uframe)
--{
--	__hc32 *hw_p = &fotg210->periodic[frame];
--	union fotg210_shadow *q = &fotg210->pshadow[frame];
--	unsigned usecs = 0;
--	struct fotg210_qh_hw *hw;
--
--	while (q->ptr) {
--		switch (hc32_to_cpu(fotg210, Q_NEXT_TYPE(fotg210, *hw_p))) {
--		case Q_TYPE_QH:
--			hw = q->qh->hw;
--			/* is it in the S-mask? */
--			if (hw->hw_info2 & cpu_to_hc32(fotg210, 1 << uframe))
--				usecs += q->qh->usecs;
--			/* ... or C-mask? */
--			if (hw->hw_info2 & cpu_to_hc32(fotg210,
--					1 << (8 + uframe)))
--				usecs += q->qh->c_usecs;
--			hw_p = &hw->hw_next;
--			q = &q->qh->qh_next;
--			break;
--		/* case Q_TYPE_FSTN: */
--		default:
--			/* for "save place" FSTNs, count the relevant INTR
--			 * bandwidth from the previous frame
--			 */
--			if (q->fstn->hw_prev != FOTG210_LIST_END(fotg210))
--				fotg210_dbg(fotg210, "ignoring FSTN cost ...\n");
--
--			hw_p = &q->fstn->hw_next;
--			q = &q->fstn->fstn_next;
--			break;
--		case Q_TYPE_ITD:
--			if (q->itd->hw_transaction[uframe])
--				usecs += q->itd->stream->usecs;
--			hw_p = &q->itd->hw_next;
--			q = &q->itd->itd_next;
--			break;
--		}
--	}
--	if (usecs > fotg210->uframe_periodic_max)
--		fotg210_err(fotg210, "uframe %d sched overrun: %d usecs\n",
--				frame * 8 + uframe, usecs);
--	return usecs;
--}
--
--static int same_tt(struct usb_device *dev1, struct usb_device *dev2)
--{
--	if (!dev1->tt || !dev2->tt)
--		return 0;
--	if (dev1->tt != dev2->tt)
--		return 0;
--	if (dev1->tt->multi)
--		return dev1->ttport == dev2->ttport;
--	else
--		return 1;
--}
--
--/* return true iff the device's transaction translator is available
-- * for a periodic transfer starting at the specified frame, using
-- * all the uframes in the mask.
-- */
--static int tt_no_collision(struct fotg210_hcd *fotg210, unsigned period,
--		struct usb_device *dev, unsigned frame, u32 uf_mask)
--{
--	if (period == 0)	/* error */
--		return 0;
--
--	/* note bandwidth wastage:  split never follows csplit
--	 * (different dev or endpoint) until the next uframe.
--	 * calling convention doesn't make that distinction.
--	 */
--	for (; frame < fotg210->periodic_size; frame += period) {
--		union fotg210_shadow here;
--		__hc32 type;
--		struct fotg210_qh_hw *hw;
--
--		here = fotg210->pshadow[frame];
--		type = Q_NEXT_TYPE(fotg210, fotg210->periodic[frame]);
--		while (here.ptr) {
--			switch (hc32_to_cpu(fotg210, type)) {
--			case Q_TYPE_ITD:
--				type = Q_NEXT_TYPE(fotg210, here.itd->hw_next);
--				here = here.itd->itd_next;
--				continue;
--			case Q_TYPE_QH:
--				hw = here.qh->hw;
--				if (same_tt(dev, here.qh->dev)) {
--					u32 mask;
--
--					mask = hc32_to_cpu(fotg210,
--							hw->hw_info2);
--					/* "knows" no gap is needed */
--					mask |= mask >> 8;
--					if (mask & uf_mask)
--						break;
--				}
--				type = Q_NEXT_TYPE(fotg210, hw->hw_next);
--				here = here.qh->qh_next;
--				continue;
--			/* case Q_TYPE_FSTN: */
--			default:
--				fotg210_dbg(fotg210,
--						"periodic frame %d bogus type %d\n",
--						frame, type);
--			}
--
--			/* collision or error */
--			return 0;
--		}
--	}
--
--	/* no collision */
--	return 1;
--}
--
--static void enable_periodic(struct fotg210_hcd *fotg210)
--{
--	if (fotg210->periodic_count++)
--		return;
--
--	/* Stop waiting to turn off the periodic schedule */
--	fotg210->enabled_hrtimer_events &=
--		~BIT(FOTG210_HRTIMER_DISABLE_PERIODIC);
--
--	/* Don't start the schedule until PSS is 0 */
--	fotg210_poll_PSS(fotg210);
--	turn_on_io_watchdog(fotg210);
--}
--
--static void disable_periodic(struct fotg210_hcd *fotg210)
--{
--	if (--fotg210->periodic_count)
--		return;
--
--	/* Don't turn off the schedule until PSS is 1 */
--	fotg210_poll_PSS(fotg210);
--}
--
--/* periodic schedule slots have iso tds (normal or split) first, then a
-- * sparse tree for active interrupt transfers.
-- *
-- * this just links in a qh; caller guarantees uframe masks are set right.
-- * no FSTN support (yet; fotg210 0.96+)
-- */
--static void qh_link_periodic(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	unsigned i;
--	unsigned period = qh->period;
--
--	dev_dbg(&qh->dev->dev,
--			"link qh%d-%04x/%p start %d [%d/%d us]\n", period,
--			hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
--			(QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
--			qh->c_usecs);
--
--	/* high bandwidth, or otherwise every microframe */
--	if (period == 0)
--		period = 1;
--
--	for (i = qh->start; i < fotg210->periodic_size; i += period) {
--		union fotg210_shadow *prev = &fotg210->pshadow[i];
--		__hc32 *hw_p = &fotg210->periodic[i];
--		union fotg210_shadow here = *prev;
--		__hc32 type = 0;
--
--		/* skip the iso nodes at list head */
--		while (here.ptr) {
--			type = Q_NEXT_TYPE(fotg210, *hw_p);
--			if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
--				break;
--			prev = periodic_next_shadow(fotg210, prev, type);
--			hw_p = shadow_next_periodic(fotg210, &here, type);
--			here = *prev;
--		}
--
--		/* sorting each branch by period (slow-->fast)
--		 * enables sharing interior tree nodes
--		 */
--		while (here.ptr && qh != here.qh) {
--			if (qh->period > here.qh->period)
--				break;
--			prev = &here.qh->qh_next;
--			hw_p = &here.qh->hw->hw_next;
--			here = *prev;
--		}
--		/* link in this qh, unless some earlier pass did that */
--		if (qh != here.qh) {
--			qh->qh_next = here;
--			if (here.qh)
--				qh->hw->hw_next = *hw_p;
--			wmb();
--			prev->qh = qh;
--			*hw_p = QH_NEXT(fotg210, qh->qh_dma);
--		}
--	}
--	qh->qh_state = QH_STATE_LINKED;
--	qh->xacterrs = 0;
--
--	/* update per-qh bandwidth for usbfs */
--	fotg210_to_hcd(fotg210)->self.bandwidth_allocated += qh->period
--		? ((qh->usecs + qh->c_usecs) / qh->period)
--		: (qh->usecs * 8);
--
--	list_add(&qh->intr_node, &fotg210->intr_qh_list);
--
--	/* maybe enable periodic schedule processing */
--	++fotg210->intr_count;
--	enable_periodic(fotg210);
--}
--
--static void qh_unlink_periodic(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh)
--{
--	unsigned i;
--	unsigned period;
--
--	/*
--	 * If qh is for a low/full-speed device, simply unlinking it
--	 * could interfere with an ongoing split transaction.  To unlink
--	 * it safely would require setting the QH_INACTIVATE bit and
--	 * waiting at least one frame, as described in EHCI 4.12.2.5.
--	 *
--	 * We won't bother with any of this.  Instead, we assume that the
--	 * only reason for unlinking an interrupt QH while the current URB
--	 * is still active is to dequeue all the URBs (flush the whole
--	 * endpoint queue).
--	 *
--	 * If rebalancing the periodic schedule is ever implemented, this
--	 * approach will no longer be valid.
--	 */
--
--	/* high bandwidth, or otherwise part of every microframe */
--	period = qh->period;
--	if (!period)
--		period = 1;
--
--	for (i = qh->start; i < fotg210->periodic_size; i += period)
--		periodic_unlink(fotg210, i, qh);
--
--	/* update per-qh bandwidth for usbfs */
--	fotg210_to_hcd(fotg210)->self.bandwidth_allocated -= qh->period
--		? ((qh->usecs + qh->c_usecs) / qh->period)
--		: (qh->usecs * 8);
--
--	dev_dbg(&qh->dev->dev,
--			"unlink qh%d-%04x/%p start %d [%d/%d us]\n",
--			qh->period, hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
--			(QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
--			qh->c_usecs);
--
--	/* qh->qh_next still "live" to HC */
--	qh->qh_state = QH_STATE_UNLINK;
--	qh->qh_next.ptr = NULL;
--
--	if (fotg210->qh_scan_next == qh)
--		fotg210->qh_scan_next = list_entry(qh->intr_node.next,
--				struct fotg210_qh, intr_node);
--	list_del(&qh->intr_node);
--}
--
--static void start_unlink_intr(struct fotg210_hcd *fotg210,
--		struct fotg210_qh *qh)
--{
--	/* If the QH isn't linked then there's nothing we can do
--	 * unless we were called during a giveback, in which case
--	 * qh_completions() has to deal with it.
--	 */
--	if (qh->qh_state != QH_STATE_LINKED) {
--		if (qh->qh_state == QH_STATE_COMPLETING)
--			qh->needs_rescan = 1;
--		return;
--	}
--
--	qh_unlink_periodic(fotg210, qh);
--
--	/* Make sure the unlinks are visible before starting the timer */
--	wmb();
--
--	/*
--	 * The EHCI spec doesn't say how long it takes the controller to
--	 * stop accessing an unlinked interrupt QH.  The timer delay is
--	 * 9 uframes; presumably that will be long enough.
--	 */
--	qh->unlink_cycle = fotg210->intr_unlink_cycle;
--
--	/* New entries go at the end of the intr_unlink list */
--	if (fotg210->intr_unlink)
--		fotg210->intr_unlink_last->unlink_next = qh;
--	else
--		fotg210->intr_unlink = qh;
--	fotg210->intr_unlink_last = qh;
--
--	if (fotg210->intr_unlinking)
--		;	/* Avoid recursive calls */
--	else if (fotg210->rh_state < FOTG210_RH_RUNNING)
--		fotg210_handle_intr_unlinks(fotg210);
--	else if (fotg210->intr_unlink == qh) {
--		fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
--				true);
--		++fotg210->intr_unlink_cycle;
--	}
--}
--
--static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	struct fotg210_qh_hw *hw = qh->hw;
--	int rc;
--
--	qh->qh_state = QH_STATE_IDLE;
--	hw->hw_next = FOTG210_LIST_END(fotg210);
--
--	qh_completions(fotg210, qh);
--
--	/* reschedule QH iff another request is queued */
--	if (!list_empty(&qh->qtd_list) &&
--			fotg210->rh_state == FOTG210_RH_RUNNING) {
--		rc = qh_schedule(fotg210, qh);
--
--		/* An error here likely indicates handshake failure
--		 * or no space left in the schedule.  Neither fault
--		 * should happen often ...
--		 *
--		 * FIXME kill the now-dysfunctional queued urbs
--		 */
--		if (rc != 0)
--			fotg210_err(fotg210, "can't reschedule qh %p, err %d\n",
--					qh, rc);
--	}
--
--	/* maybe turn off periodic schedule */
--	--fotg210->intr_count;
--	disable_periodic(fotg210);
--}
--
--static int check_period(struct fotg210_hcd *fotg210, unsigned frame,
--		unsigned uframe, unsigned period, unsigned usecs)
--{
--	int claimed;
--
--	/* complete split running into next frame?
--	 * given FSTN support, we could sometimes check...
--	 */
--	if (uframe >= 8)
--		return 0;
--
--	/* convert "usecs we need" to "max already claimed" */
--	usecs = fotg210->uframe_periodic_max - usecs;
--
--	/* we "know" 2 and 4 uframe intervals were rejected; so
--	 * for period 0, check _every_ microframe in the schedule.
--	 */
--	if (unlikely(period == 0)) {
--		do {
--			for (uframe = 0; uframe < 7; uframe++) {
--				claimed = periodic_usecs(fotg210, frame,
--						uframe);
--				if (claimed > usecs)
--					return 0;
--			}
--		} while ((frame += 1) < fotg210->periodic_size);
--
--	/* just check the specified uframe, at that period */
--	} else {
--		do {
--			claimed = periodic_usecs(fotg210, frame, uframe);
--			if (claimed > usecs)
--				return 0;
--		} while ((frame += period) < fotg210->periodic_size);
--	}
--
--	/* success! */
--	return 1;
--}
--
--static int check_intr_schedule(struct fotg210_hcd *fotg210, unsigned frame,
--		unsigned uframe, const struct fotg210_qh *qh, __hc32 *c_maskp)
--{
--	int retval = -ENOSPC;
--	u8 mask = 0;
--
--	if (qh->c_usecs && uframe >= 6)		/* FSTN territory? */
--		goto done;
--
--	if (!check_period(fotg210, frame, uframe, qh->period, qh->usecs))
--		goto done;
--	if (!qh->c_usecs) {
--		retval = 0;
--		*c_maskp = 0;
--		goto done;
--	}
--
--	/* Make sure this tt's buffer is also available for CSPLITs.
--	 * We pessimize a bit; probably the typical full speed case
--	 * doesn't need the second CSPLIT.
--	 *
--	 * NOTE:  both SPLIT and CSPLIT could be checked in just
--	 * one smart pass...
--	 */
--	mask = 0x03 << (uframe + qh->gap_uf);
--	*c_maskp = cpu_to_hc32(fotg210, mask << 8);
--
--	mask |= 1 << uframe;
--	if (tt_no_collision(fotg210, qh->period, qh->dev, frame, mask)) {
--		if (!check_period(fotg210, frame, uframe + qh->gap_uf + 1,
--				qh->period, qh->c_usecs))
--			goto done;
--		if (!check_period(fotg210, frame, uframe + qh->gap_uf,
--				qh->period, qh->c_usecs))
--			goto done;
--		retval = 0;
--	}
--done:
--	return retval;
--}
--
--/* "first fit" scheduling policy used the first time through,
-- * or when the previous schedule slot can't be re-used.
-- */
--static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
--	int status;
--	unsigned uframe;
--	__hc32 c_mask;
--	unsigned frame;	/* 0..(qh->period - 1), or NO_FRAME */
--	struct fotg210_qh_hw *hw = qh->hw;
--
--	qh_refresh(fotg210, qh);
--	hw->hw_next = FOTG210_LIST_END(fotg210);
--	frame = qh->start;
--
--	/* reuse the previous schedule slots, if we can */
--	if (frame < qh->period) {
--		uframe = ffs(hc32_to_cpup(fotg210, &hw->hw_info2) & QH_SMASK);
--		status = check_intr_schedule(fotg210, frame, --uframe,
--				qh, &c_mask);
--	} else {
--		uframe = 0;
--		c_mask = 0;
--		status = -ENOSPC;
--	}
--
--	/* else scan the schedule to find a group of slots such that all
--	 * uframes have enough periodic bandwidth available.
--	 */
--	if (status) {
--		/* "normal" case, uframing flexible except with splits */
--		if (qh->period) {
--			int i;
--
--			for (i = qh->period; status && i > 0; --i) {
--				frame = ++fotg210->random_frame % qh->period;
--				for (uframe = 0; uframe < 8; uframe++) {
--					status = check_intr_schedule(fotg210,
--							frame, uframe, qh,
--							&c_mask);
--					if (status == 0)
--						break;
--				}
--			}
--
--		/* qh->period == 0 means every uframe */
--		} else {
--			frame = 0;
--			status = check_intr_schedule(fotg210, 0, 0, qh,
--					&c_mask);
--		}
--		if (status)
--			goto done;
--		qh->start = frame;
--
--		/* reset S-frame and (maybe) C-frame masks */
--		hw->hw_info2 &= cpu_to_hc32(fotg210, ~(QH_CMASK | QH_SMASK));
--		hw->hw_info2 |= qh->period
--			? cpu_to_hc32(fotg210, 1 << uframe)
--			: cpu_to_hc32(fotg210, QH_SMASK);
--		hw->hw_info2 |= c_mask;
--	} else
--		fotg210_dbg(fotg210, "reused qh %p schedule\n", qh);
--
--	/* stuff into the periodic schedule */
--	qh_link_periodic(fotg210, qh);
--done:
--	return status;
--}
--
--static int intr_submit(struct fotg210_hcd *fotg210, struct urb *urb,
--		struct list_head *qtd_list, gfp_t mem_flags)
--{
--	unsigned epnum;
--	unsigned long flags;
--	struct fotg210_qh *qh;
--	int status;
--	struct list_head empty;
--
--	/* get endpoint and transfer/schedule data */
--	epnum = urb->ep->desc.bEndpointAddress;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
--		status = -ESHUTDOWN;
--		goto done_not_linked;
--	}
--	status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
--	if (unlikely(status))
--		goto done_not_linked;
--
--	/* get qh and force any scheduling errors */
--	INIT_LIST_HEAD(&empty);
--	qh = qh_append_tds(fotg210, urb, &empty, epnum, &urb->ep->hcpriv);
--	if (qh == NULL) {
--		status = -ENOMEM;
--		goto done;
--	}
--	if (qh->qh_state == QH_STATE_IDLE) {
--		status = qh_schedule(fotg210, qh);
--		if (status)
--			goto done;
--	}
--
--	/* then queue the urb's tds to the qh */
--	qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
--	BUG_ON(qh == NULL);
--
--	/* ... update usbfs periodic stats */
--	fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs++;
--
--done:
--	if (unlikely(status))
--		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--done_not_linked:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	if (status)
--		qtd_list_free(fotg210, urb, qtd_list);
--
--	return status;
--}
--
--static void scan_intr(struct fotg210_hcd *fotg210)
--{
--	struct fotg210_qh *qh;
--
--	list_for_each_entry_safe(qh, fotg210->qh_scan_next,
--			&fotg210->intr_qh_list, intr_node) {
--rescan:
--		/* clean any finished work for this qh */
--		if (!list_empty(&qh->qtd_list)) {
--			int temp;
--
--			/*
--			 * Unlinks could happen here; completion reporting
--			 * drops the lock.  That's why fotg210->qh_scan_next
--			 * always holds the next qh to scan; if the next qh
--			 * gets unlinked then fotg210->qh_scan_next is adjusted
--			 * in qh_unlink_periodic().
--			 */
--			temp = qh_completions(fotg210, qh);
--			if (unlikely(qh->needs_rescan ||
--					(list_empty(&qh->qtd_list) &&
--					qh->qh_state == QH_STATE_LINKED)))
--				start_unlink_intr(fotg210, qh);
--			else if (temp != 0)
--				goto rescan;
--		}
--	}
--}
--
--/* fotg210_iso_stream ops work with both ITD and SITD */
--
--static struct fotg210_iso_stream *iso_stream_alloc(gfp_t mem_flags)
--{
--	struct fotg210_iso_stream *stream;
--
--	stream = kzalloc(sizeof(*stream), mem_flags);
--	if (likely(stream != NULL)) {
--		INIT_LIST_HEAD(&stream->td_list);
--		INIT_LIST_HEAD(&stream->free_list);
--		stream->next_uframe = -1;
--	}
--	return stream;
--}
--
--static void iso_stream_init(struct fotg210_hcd *fotg210,
--		struct fotg210_iso_stream *stream, struct usb_device *dev,
--		int pipe, unsigned interval)
--{
--	u32 buf1;
--	unsigned epnum, maxp;
--	int is_input;
--	long bandwidth;
--	unsigned multi;
--	struct usb_host_endpoint *ep;
--
--	/*
--	 * this might be a "high bandwidth" highspeed endpoint,
--	 * as encoded in the ep descriptor's wMaxPacket field
--	 */
--	epnum = usb_pipeendpoint(pipe);
--	is_input = usb_pipein(pipe) ? USB_DIR_IN : 0;
--	ep = usb_pipe_endpoint(dev, pipe);
--	maxp = usb_endpoint_maxp(&ep->desc);
--	if (is_input)
--		buf1 = (1 << 11);
--	else
--		buf1 = 0;
--
--	multi = usb_endpoint_maxp_mult(&ep->desc);
--	buf1 |= maxp;
--	maxp *= multi;
--
--	stream->buf0 = cpu_to_hc32(fotg210, (epnum << 8) | dev->devnum);
--	stream->buf1 = cpu_to_hc32(fotg210, buf1);
--	stream->buf2 = cpu_to_hc32(fotg210, multi);
--
--	/* usbfs wants to report the average usecs per frame tied up
--	 * when transfers on this endpoint are scheduled ...
--	 */
--	if (dev->speed == USB_SPEED_FULL) {
--		interval <<= 3;
--		stream->usecs = NS_TO_US(usb_calc_bus_time(dev->speed,
--				is_input, 1, maxp));
--		stream->usecs /= 8;
--	} else {
--		stream->highspeed = 1;
--		stream->usecs = HS_USECS_ISO(maxp);
--	}
--	bandwidth = stream->usecs * 8;
--	bandwidth /= interval;
--
--	stream->bandwidth = bandwidth;
--	stream->udev = dev;
--	stream->bEndpointAddress = is_input | epnum;
--	stream->interval = interval;
--	stream->maxp = maxp;
--}
--
--static struct fotg210_iso_stream *iso_stream_find(struct fotg210_hcd *fotg210,
--		struct urb *urb)
--{
--	unsigned epnum;
--	struct fotg210_iso_stream *stream;
--	struct usb_host_endpoint *ep;
--	unsigned long flags;
--
--	epnum = usb_pipeendpoint(urb->pipe);
--	if (usb_pipein(urb->pipe))
--		ep = urb->dev->ep_in[epnum];
--	else
--		ep = urb->dev->ep_out[epnum];
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	stream = ep->hcpriv;
--
--	if (unlikely(stream == NULL)) {
--		stream = iso_stream_alloc(GFP_ATOMIC);
--		if (likely(stream != NULL)) {
--			ep->hcpriv = stream;
--			stream->ep = ep;
--			iso_stream_init(fotg210, stream, urb->dev, urb->pipe,
--					urb->interval);
--		}
--
--	/* if dev->ep[epnum] is a QH, hw is set */
--	} else if (unlikely(stream->hw != NULL)) {
--		fotg210_dbg(fotg210, "dev %s ep%d%s, not iso??\n",
--				urb->dev->devpath, epnum,
--				usb_pipein(urb->pipe) ? "in" : "out");
--		stream = NULL;
--	}
--
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return stream;
--}
--
--/* fotg210_iso_sched ops can be ITD-only or SITD-only */
--
--static struct fotg210_iso_sched *iso_sched_alloc(unsigned packets,
--		gfp_t mem_flags)
--{
--	struct fotg210_iso_sched *iso_sched;
--
--	iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags);
--	if (likely(iso_sched != NULL))
--		INIT_LIST_HEAD(&iso_sched->td_list);
--
--	return iso_sched;
--}
--
--static inline void itd_sched_init(struct fotg210_hcd *fotg210,
--		struct fotg210_iso_sched *iso_sched,
--		struct fotg210_iso_stream *stream, struct urb *urb)
--{
--	unsigned i;
--	dma_addr_t dma = urb->transfer_dma;
--
--	/* how many uframes are needed for these transfers */
--	iso_sched->span = urb->number_of_packets * stream->interval;
--
--	/* figure out per-uframe itd fields that we'll need later
--	 * when we fit new itds into the schedule.
--	 */
--	for (i = 0; i < urb->number_of_packets; i++) {
--		struct fotg210_iso_packet *uframe = &iso_sched->packet[i];
--		unsigned length;
--		dma_addr_t buf;
--		u32 trans;
--
--		length = urb->iso_frame_desc[i].length;
--		buf = dma + urb->iso_frame_desc[i].offset;
--
--		trans = FOTG210_ISOC_ACTIVE;
--		trans |= buf & 0x0fff;
--		if (unlikely(((i + 1) == urb->number_of_packets))
--				&& !(urb->transfer_flags & URB_NO_INTERRUPT))
--			trans |= FOTG210_ITD_IOC;
--		trans |= length << 16;
--		uframe->transaction = cpu_to_hc32(fotg210, trans);
--
--		/* might need to cross a buffer page within a uframe */
--		uframe->bufp = (buf & ~(u64)0x0fff);
--		buf += length;
--		if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff))))
--			uframe->cross = 1;
--	}
--}
--
--static void iso_sched_free(struct fotg210_iso_stream *stream,
--		struct fotg210_iso_sched *iso_sched)
--{
--	if (!iso_sched)
--		return;
--	/* caller must hold fotg210->lock!*/
--	list_splice(&iso_sched->td_list, &stream->free_list);
--	kfree(iso_sched);
--}
--
--static int itd_urb_transaction(struct fotg210_iso_stream *stream,
--		struct fotg210_hcd *fotg210, struct urb *urb, gfp_t mem_flags)
--{
--	struct fotg210_itd *itd;
--	dma_addr_t itd_dma;
--	int i;
--	unsigned num_itds;
--	struct fotg210_iso_sched *sched;
--	unsigned long flags;
--
--	sched = iso_sched_alloc(urb->number_of_packets, mem_flags);
--	if (unlikely(sched == NULL))
--		return -ENOMEM;
--
--	itd_sched_init(fotg210, sched, stream, urb);
--
--	if (urb->interval < 8)
--		num_itds = 1 + (sched->span + 7) / 8;
--	else
--		num_itds = urb->number_of_packets;
--
--	/* allocate/init ITDs */
--	spin_lock_irqsave(&fotg210->lock, flags);
--	for (i = 0; i < num_itds; i++) {
--
--		/*
--		 * Use iTDs from the free list, but not iTDs that may
--		 * still be in use by the hardware.
--		 */
--		if (likely(!list_empty(&stream->free_list))) {
--			itd = list_first_entry(&stream->free_list,
--					struct fotg210_itd, itd_list);
--			if (itd->frame == fotg210->now_frame)
--				goto alloc_itd;
--			list_del(&itd->itd_list);
--			itd_dma = itd->itd_dma;
--		} else {
--alloc_itd:
--			spin_unlock_irqrestore(&fotg210->lock, flags);
--			itd = dma_pool_alloc(fotg210->itd_pool, mem_flags,
--					&itd_dma);
--			spin_lock_irqsave(&fotg210->lock, flags);
--			if (!itd) {
--				iso_sched_free(stream, sched);
--				spin_unlock_irqrestore(&fotg210->lock, flags);
--				return -ENOMEM;
--			}
--		}
--
--		memset(itd, 0, sizeof(*itd));
--		itd->itd_dma = itd_dma;
--		list_add(&itd->itd_list, &sched->td_list);
--	}
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--
--	/* temporarily store schedule info in hcpriv */
--	urb->hcpriv = sched;
--	urb->error_count = 0;
--	return 0;
--}
--
--static inline int itd_slot_ok(struct fotg210_hcd *fotg210, u32 mod, u32 uframe,
--		u8 usecs, u32 period)
--{
--	uframe %= period;
--	do {
--		/* can't commit more than uframe_periodic_max usec */
--		if (periodic_usecs(fotg210, uframe >> 3, uframe & 0x7)
--				> (fotg210->uframe_periodic_max - usecs))
--			return 0;
--
--		/* we know urb->interval is 2^N uframes */
--		uframe += period;
--	} while (uframe < mod);
--	return 1;
--}
--
--/* This scheduler plans almost as far into the future as it has actual
-- * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
-- * "as small as possible" to be cache-friendlier.)  That limits the size
-- * transfers you can stream reliably; avoid more than 64 msec per urb.
-- * Also avoid queue depths of less than fotg210's worst irq latency (affected
-- * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
-- * and other factors); or more than about 230 msec total (for portability,
-- * given FOTG210_TUNE_FLS and the slop).  Or, write a smarter scheduler!
-- */
--
--#define SCHEDULE_SLOP 80 /* microframes */
--
--static int iso_stream_schedule(struct fotg210_hcd *fotg210, struct urb *urb,
--		struct fotg210_iso_stream *stream)
--{
--	u32 now, next, start, period, span;
--	int status;
--	unsigned mod = fotg210->periodic_size << 3;
--	struct fotg210_iso_sched *sched = urb->hcpriv;
--
--	period = urb->interval;
--	span = sched->span;
--
--	if (span > mod - SCHEDULE_SLOP) {
--		fotg210_dbg(fotg210, "iso request %p too long\n", urb);
--		status = -EFBIG;
--		goto fail;
--	}
--
--	now = fotg210_read_frame_index(fotg210) & (mod - 1);
--
--	/* Typical case: reuse current schedule, stream is still active.
--	 * Hopefully there are no gaps from the host falling behind
--	 * (irq delays etc), but if there are we'll take the next
--	 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
--	 */
--	if (likely(!list_empty(&stream->td_list))) {
--		u32 excess;
--
--		/* For high speed devices, allow scheduling within the
--		 * isochronous scheduling threshold.  For full speed devices
--		 * and Intel PCI-based controllers, don't (work around for
--		 * Intel ICH9 bug).
--		 */
--		if (!stream->highspeed && fotg210->fs_i_thresh)
--			next = now + fotg210->i_thresh;
--		else
--			next = now;
--
--		/* Fell behind (by up to twice the slop amount)?
--		 * We decide based on the time of the last currently-scheduled
--		 * slot, not the time of the next available slot.
--		 */
--		excess = (stream->next_uframe - period - next) & (mod - 1);
--		if (excess >= mod - 2 * SCHEDULE_SLOP)
--			start = next + excess - mod + period *
--					DIV_ROUND_UP(mod - excess, period);
--		else
--			start = next + excess + period;
--		if (start - now >= mod) {
--			fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
--					urb, start - now - period, period,
--					mod);
--			status = -EFBIG;
--			goto fail;
--		}
--	}
--
--	/* need to schedule; when's the next (u)frame we could start?
--	 * this is bigger than fotg210->i_thresh allows; scheduling itself
--	 * isn't free, the slop should handle reasonably slow cpus.  it
--	 * can also help high bandwidth if the dma and irq loads don't
--	 * jump until after the queue is primed.
--	 */
--	else {
--		int done = 0;
--
--		start = SCHEDULE_SLOP + (now & ~0x07);
--
--		/* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
--
--		/* find a uframe slot with enough bandwidth.
--		 * Early uframes are more precious because full-speed
--		 * iso IN transfers can't use late uframes,
--		 * and therefore they should be allocated last.
--		 */
--		next = start;
--		start += period;
--		do {
--			start--;
--			/* check schedule: enough space? */
--			if (itd_slot_ok(fotg210, mod, start,
--					stream->usecs, period))
--				done = 1;
--		} while (start > next && !done);
--
--		/* no room in the schedule */
--		if (!done) {
--			fotg210_dbg(fotg210, "iso resched full %p (now %d max %d)\n",
--					urb, now, now + mod);
--			status = -ENOSPC;
--			goto fail;
--		}
--	}
--
--	/* Tried to schedule too far into the future? */
--	if (unlikely(start - now + span - period >=
--			mod - 2 * SCHEDULE_SLOP)) {
--		fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
--				urb, start - now, span - period,
--				mod - 2 * SCHEDULE_SLOP);
--		status = -EFBIG;
--		goto fail;
--	}
--
--	stream->next_uframe = start & (mod - 1);
--
--	/* report high speed start in uframes; full speed, in frames */
--	urb->start_frame = stream->next_uframe;
--	if (!stream->highspeed)
--		urb->start_frame >>= 3;
--
--	/* Make sure scan_isoc() sees these */
--	if (fotg210->isoc_count == 0)
--		fotg210->next_frame = now >> 3;
--	return 0;
--
--fail:
--	iso_sched_free(stream, sched);
--	urb->hcpriv = NULL;
--	return status;
--}
--
--static inline void itd_init(struct fotg210_hcd *fotg210,
--		struct fotg210_iso_stream *stream, struct fotg210_itd *itd)
--{
--	int i;
--
--	/* it's been recently zeroed */
--	itd->hw_next = FOTG210_LIST_END(fotg210);
--	itd->hw_bufp[0] = stream->buf0;
--	itd->hw_bufp[1] = stream->buf1;
--	itd->hw_bufp[2] = stream->buf2;
--
--	for (i = 0; i < 8; i++)
--		itd->index[i] = -1;
--
--	/* All other fields are filled when scheduling */
--}
--
--static inline void itd_patch(struct fotg210_hcd *fotg210,
--		struct fotg210_itd *itd, struct fotg210_iso_sched *iso_sched,
--		unsigned index, u16 uframe)
--{
--	struct fotg210_iso_packet *uf = &iso_sched->packet[index];
--	unsigned pg = itd->pg;
--
--	uframe &= 0x07;
--	itd->index[uframe] = index;
--
--	itd->hw_transaction[uframe] = uf->transaction;
--	itd->hw_transaction[uframe] |= cpu_to_hc32(fotg210, pg << 12);
--	itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, uf->bufp & ~(u32)0);
--	itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(uf->bufp >> 32));
--
--	/* iso_frame_desc[].offset must be strictly increasing */
--	if (unlikely(uf->cross)) {
--		u64 bufp = uf->bufp + 4096;
--
--		itd->pg = ++pg;
--		itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, bufp & ~(u32)0);
--		itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(bufp >> 32));
--	}
--}
--
--static inline void itd_link(struct fotg210_hcd *fotg210, unsigned frame,
--		struct fotg210_itd *itd)
--{
--	union fotg210_shadow *prev = &fotg210->pshadow[frame];
--	__hc32 *hw_p = &fotg210->periodic[frame];
--	union fotg210_shadow here = *prev;
--	__hc32 type = 0;
--
--	/* skip any iso nodes which might belong to previous microframes */
--	while (here.ptr) {
--		type = Q_NEXT_TYPE(fotg210, *hw_p);
--		if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
--			break;
--		prev = periodic_next_shadow(fotg210, prev, type);
--		hw_p = shadow_next_periodic(fotg210, &here, type);
--		here = *prev;
--	}
--
--	itd->itd_next = here;
--	itd->hw_next = *hw_p;
--	prev->itd = itd;
--	itd->frame = frame;
--	wmb();
--	*hw_p = cpu_to_hc32(fotg210, itd->itd_dma | Q_TYPE_ITD);
--}
--
--/* fit urb's itds into the selected schedule slot; activate as needed */
--static void itd_link_urb(struct fotg210_hcd *fotg210, struct urb *urb,
--		unsigned mod, struct fotg210_iso_stream *stream)
--{
--	int packet;
--	unsigned next_uframe, uframe, frame;
--	struct fotg210_iso_sched *iso_sched = urb->hcpriv;
--	struct fotg210_itd *itd;
--
--	next_uframe = stream->next_uframe & (mod - 1);
--
--	if (unlikely(list_empty(&stream->td_list))) {
--		fotg210_to_hcd(fotg210)->self.bandwidth_allocated
--				+= stream->bandwidth;
--		fotg210_dbg(fotg210,
--			"schedule devp %s ep%d%s-iso period %d start %d.%d\n",
--			urb->dev->devpath, stream->bEndpointAddress & 0x0f,
--			(stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
--			urb->interval,
--			next_uframe >> 3, next_uframe & 0x7);
--	}
--
--	/* fill iTDs uframe by uframe */
--	for (packet = 0, itd = NULL; packet < urb->number_of_packets;) {
--		if (itd == NULL) {
--			/* ASSERT:  we have all necessary itds */
--
--			/* ASSERT:  no itds for this endpoint in this uframe */
--
--			itd = list_entry(iso_sched->td_list.next,
--					struct fotg210_itd, itd_list);
--			list_move_tail(&itd->itd_list, &stream->td_list);
--			itd->stream = stream;
--			itd->urb = urb;
--			itd_init(fotg210, stream, itd);
--		}
--
--		uframe = next_uframe & 0x07;
--		frame = next_uframe >> 3;
--
--		itd_patch(fotg210, itd, iso_sched, packet, uframe);
--
--		next_uframe += stream->interval;
--		next_uframe &= mod - 1;
--		packet++;
--
--		/* link completed itds into the schedule */
--		if (((next_uframe >> 3) != frame)
--				|| packet == urb->number_of_packets) {
--			itd_link(fotg210, frame & (fotg210->periodic_size - 1),
--					itd);
--			itd = NULL;
--		}
--	}
--	stream->next_uframe = next_uframe;
--
--	/* don't need that schedule data any more */
--	iso_sched_free(stream, iso_sched);
--	urb->hcpriv = NULL;
--
--	++fotg210->isoc_count;
--	enable_periodic(fotg210);
--}
--
--#define ISO_ERRS (FOTG210_ISOC_BUF_ERR | FOTG210_ISOC_BABBLE |\
--		FOTG210_ISOC_XACTERR)
--
--/* Process and recycle a completed ITD.  Return true iff its urb completed,
-- * and hence its completion callback probably added things to the hardware
-- * schedule.
-- *
-- * Note that we carefully avoid recycling this descriptor until after any
-- * completion callback runs, so that it won't be reused quickly.  That is,
-- * assuming (a) no more than two urbs per frame on this endpoint, and also
-- * (b) only this endpoint's completions submit URBs.  It seems some silicon
-- * corrupts things if you reuse completed descriptors very quickly...
-- */
--static bool itd_complete(struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
--{
--	struct urb *urb = itd->urb;
--	struct usb_iso_packet_descriptor *desc;
--	u32 t;
--	unsigned uframe;
--	int urb_index = -1;
--	struct fotg210_iso_stream *stream = itd->stream;
--	struct usb_device *dev;
--	bool retval = false;
--
--	/* for each uframe with a packet */
--	for (uframe = 0; uframe < 8; uframe++) {
--		if (likely(itd->index[uframe] == -1))
--			continue;
--		urb_index = itd->index[uframe];
--		desc = &urb->iso_frame_desc[urb_index];
--
--		t = hc32_to_cpup(fotg210, &itd->hw_transaction[uframe]);
--		itd->hw_transaction[uframe] = 0;
--
--		/* report transfer status */
--		if (unlikely(t & ISO_ERRS)) {
--			urb->error_count++;
--			if (t & FOTG210_ISOC_BUF_ERR)
--				desc->status = usb_pipein(urb->pipe)
--					? -ENOSR  /* hc couldn't read */
--					: -ECOMM; /* hc couldn't write */
--			else if (t & FOTG210_ISOC_BABBLE)
--				desc->status = -EOVERFLOW;
--			else /* (t & FOTG210_ISOC_XACTERR) */
--				desc->status = -EPROTO;
--
--			/* HC need not update length with this error */
--			if (!(t & FOTG210_ISOC_BABBLE)) {
--				desc->actual_length = FOTG210_ITD_LENGTH(t);
--				urb->actual_length += desc->actual_length;
--			}
--		} else if (likely((t & FOTG210_ISOC_ACTIVE) == 0)) {
--			desc->status = 0;
--			desc->actual_length = FOTG210_ITD_LENGTH(t);
--			urb->actual_length += desc->actual_length;
--		} else {
--			/* URB was too late */
--			desc->status = -EXDEV;
--		}
--	}
--
--	/* handle completion now? */
--	if (likely((urb_index + 1) != urb->number_of_packets))
--		goto done;
--
--	/* ASSERT: it's really the last itd for this urb
--	 * list_for_each_entry (itd, &stream->td_list, itd_list)
--	 *	BUG_ON (itd->urb == urb);
--	 */
--
--	/* give urb back to the driver; completion often (re)submits */
--	dev = urb->dev;
--	fotg210_urb_done(fotg210, urb, 0);
--	retval = true;
--	urb = NULL;
--
--	--fotg210->isoc_count;
--	disable_periodic(fotg210);
--
--	if (unlikely(list_is_singular(&stream->td_list))) {
--		fotg210_to_hcd(fotg210)->self.bandwidth_allocated
--				-= stream->bandwidth;
--		fotg210_dbg(fotg210,
--			"deschedule devp %s ep%d%s-iso\n",
--			dev->devpath, stream->bEndpointAddress & 0x0f,
--			(stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
--	}
--
--done:
--	itd->urb = NULL;
--
--	/* Add to the end of the free list for later reuse */
--	list_move_tail(&itd->itd_list, &stream->free_list);
--
--	/* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
--	if (list_empty(&stream->td_list)) {
--		list_splice_tail_init(&stream->free_list,
--				&fotg210->cached_itd_list);
--		start_free_itds(fotg210);
--	}
--
--	return retval;
--}
--
--static int itd_submit(struct fotg210_hcd *fotg210, struct urb *urb,
--		gfp_t mem_flags)
--{
--	int status = -EINVAL;
--	unsigned long flags;
--	struct fotg210_iso_stream *stream;
--
--	/* Get iso_stream head */
--	stream = iso_stream_find(fotg210, urb);
--	if (unlikely(stream == NULL)) {
--		fotg210_dbg(fotg210, "can't get iso stream\n");
--		return -ENOMEM;
--	}
--	if (unlikely(urb->interval != stream->interval &&
--			fotg210_port_speed(fotg210, 0) ==
--			USB_PORT_STAT_HIGH_SPEED)) {
--		fotg210_dbg(fotg210, "can't change iso interval %d --> %d\n",
--				stream->interval, urb->interval);
--		goto done;
--	}
--
--#ifdef FOTG210_URB_TRACE
--	fotg210_dbg(fotg210,
--			"%s %s urb %p ep%d%s len %d, %d pkts %d uframes[%p]\n",
--			__func__, urb->dev->devpath, urb,
--			usb_pipeendpoint(urb->pipe),
--			usb_pipein(urb->pipe) ? "in" : "out",
--			urb->transfer_buffer_length,
--			urb->number_of_packets, urb->interval,
--			stream);
--#endif
--
--	/* allocate ITDs w/o locking anything */
--	status = itd_urb_transaction(stream, fotg210, urb, mem_flags);
--	if (unlikely(status < 0)) {
--		fotg210_dbg(fotg210, "can't init itds\n");
--		goto done;
--	}
--
--	/* schedule ... need to lock */
--	spin_lock_irqsave(&fotg210->lock, flags);
--	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
--		status = -ESHUTDOWN;
--		goto done_not_linked;
--	}
--	status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
--	if (unlikely(status))
--		goto done_not_linked;
--	status = iso_stream_schedule(fotg210, urb, stream);
--	if (likely(status == 0))
--		itd_link_urb(fotg210, urb, fotg210->periodic_size << 3, stream);
--	else
--		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--done_not_linked:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--done:
--	return status;
--}
--
--static inline int scan_frame_queue(struct fotg210_hcd *fotg210, unsigned frame,
--		unsigned now_frame, bool live)
--{
--	unsigned uf;
--	bool modified;
--	union fotg210_shadow q, *q_p;
--	__hc32 type, *hw_p;
--
--	/* scan each element in frame's queue for completions */
--	q_p = &fotg210->pshadow[frame];
--	hw_p = &fotg210->periodic[frame];
--	q.ptr = q_p->ptr;
--	type = Q_NEXT_TYPE(fotg210, *hw_p);
--	modified = false;
--
--	while (q.ptr) {
--		switch (hc32_to_cpu(fotg210, type)) {
--		case Q_TYPE_ITD:
--			/* If this ITD is still active, leave it for
--			 * later processing ... check the next entry.
--			 * No need to check for activity unless the
--			 * frame is current.
--			 */
--			if (frame == now_frame && live) {
--				rmb();
--				for (uf = 0; uf < 8; uf++) {
--					if (q.itd->hw_transaction[uf] &
--							ITD_ACTIVE(fotg210))
--						break;
--				}
--				if (uf < 8) {
--					q_p = &q.itd->itd_next;
--					hw_p = &q.itd->hw_next;
--					type = Q_NEXT_TYPE(fotg210,
--							q.itd->hw_next);
--					q = *q_p;
--					break;
--				}
--			}
--
--			/* Take finished ITDs out of the schedule
--			 * and process them:  recycle, maybe report
--			 * URB completion.  HC won't cache the
--			 * pointer for much longer, if at all.
--			 */
--			*q_p = q.itd->itd_next;
--			*hw_p = q.itd->hw_next;
--			type = Q_NEXT_TYPE(fotg210, q.itd->hw_next);
--			wmb();
--			modified = itd_complete(fotg210, q.itd);
--			q = *q_p;
--			break;
--		default:
--			fotg210_dbg(fotg210, "corrupt type %d frame %d shadow %p\n",
--					type, frame, q.ptr);
--			fallthrough;
--		case Q_TYPE_QH:
--		case Q_TYPE_FSTN:
--			/* End of the iTDs and siTDs */
--			q.ptr = NULL;
--			break;
--		}
--
--		/* assume completion callbacks modify the queue */
--		if (unlikely(modified && fotg210->isoc_count > 0))
--			return -EINVAL;
--	}
--	return 0;
--}
--
--static void scan_isoc(struct fotg210_hcd *fotg210)
--{
--	unsigned uf, now_frame, frame, ret;
--	unsigned fmask = fotg210->periodic_size - 1;
--	bool live;
--
--	/*
--	 * When running, scan from last scan point up to "now"
--	 * else clean up by scanning everything that's left.
--	 * Touches as few pages as possible:  cache-friendly.
--	 */
--	if (fotg210->rh_state >= FOTG210_RH_RUNNING) {
--		uf = fotg210_read_frame_index(fotg210);
--		now_frame = (uf >> 3) & fmask;
--		live = true;
--	} else  {
--		now_frame = (fotg210->next_frame - 1) & fmask;
--		live = false;
--	}
--	fotg210->now_frame = now_frame;
--
--	frame = fotg210->next_frame;
--	for (;;) {
--		ret = 1;
--		while (ret != 0)
--			ret = scan_frame_queue(fotg210, frame,
--					now_frame, live);
--
--		/* Stop when we have reached the current frame */
--		if (frame == now_frame)
--			break;
--		frame = (frame + 1) & fmask;
--	}
--	fotg210->next_frame = now_frame;
--}
--
--/* Display / Set uframe_periodic_max
-- */
--static ssize_t uframe_periodic_max_show(struct device *dev,
--		struct device_attribute *attr, char *buf)
--{
--	struct fotg210_hcd *fotg210;
--	int n;
--
--	fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
--	n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
--	return n;
--}
--
--
--static ssize_t uframe_periodic_max_store(struct device *dev,
--		struct device_attribute *attr, const char *buf, size_t count)
--{
--	struct fotg210_hcd *fotg210;
--	unsigned uframe_periodic_max;
--	unsigned frame, uframe;
--	unsigned short allocated_max;
--	unsigned long flags;
--	ssize_t ret;
--
--	fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
--	if (kstrtouint(buf, 0, &uframe_periodic_max) < 0)
--		return -EINVAL;
--
--	if (uframe_periodic_max < 100 || uframe_periodic_max >= 125) {
--		fotg210_info(fotg210, "rejecting invalid request for uframe_periodic_max=%u\n",
--				uframe_periodic_max);
--		return -EINVAL;
--	}
--
--	ret = -EINVAL;
--
--	/*
--	 * lock, so that our checking does not race with possible periodic
--	 * bandwidth allocation through submitting new urbs.
--	 */
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	/*
--	 * for request to decrease max periodic bandwidth, we have to check
--	 * every microframe in the schedule to see whether the decrease is
--	 * possible.
--	 */
--	if (uframe_periodic_max < fotg210->uframe_periodic_max) {
--		allocated_max = 0;
--
--		for (frame = 0; frame < fotg210->periodic_size; ++frame)
--			for (uframe = 0; uframe < 7; ++uframe)
--				allocated_max = max(allocated_max,
--						periodic_usecs(fotg210, frame,
--						uframe));
--
--		if (allocated_max > uframe_periodic_max) {
--			fotg210_info(fotg210,
--					"cannot decrease uframe_periodic_max because periodic bandwidth is already allocated (%u > %u)\n",
--					allocated_max, uframe_periodic_max);
--			goto out_unlock;
--		}
--	}
--
--	/* increasing is always ok */
--
--	fotg210_info(fotg210,
--			"setting max periodic bandwidth to %u%% (== %u usec/uframe)\n",
--			100 * uframe_periodic_max/125, uframe_periodic_max);
--
--	if (uframe_periodic_max != 100)
--		fotg210_warn(fotg210, "max periodic bandwidth set is non-standard\n");
--
--	fotg210->uframe_periodic_max = uframe_periodic_max;
--	ret = count;
--
--out_unlock:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return ret;
--}
--
--static DEVICE_ATTR_RW(uframe_periodic_max);
--
--static inline int create_sysfs_files(struct fotg210_hcd *fotg210)
--{
--	struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
--
--	return device_create_file(controller, &dev_attr_uframe_periodic_max);
--}
--
--static inline void remove_sysfs_files(struct fotg210_hcd *fotg210)
--{
--	struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
--
--	device_remove_file(controller, &dev_attr_uframe_periodic_max);
--}
--/* On some systems, leaving remote wakeup enabled prevents system shutdown.
-- * The firmware seems to think that powering off is a wakeup event!
-- * This routine turns off remote wakeup and everything else, on all ports.
-- */
--static void fotg210_turn_off_all_ports(struct fotg210_hcd *fotg210)
--{
--	u32 __iomem *status_reg = &fotg210->regs->port_status;
--
--	fotg210_writel(fotg210, PORT_RWC_BITS, status_reg);
--}
--
--/* Halt HC, turn off all ports, and let the BIOS use the companion controllers.
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static void fotg210_silence_controller(struct fotg210_hcd *fotg210)
--{
--	fotg210_halt(fotg210);
--
--	spin_lock_irq(&fotg210->lock);
--	fotg210->rh_state = FOTG210_RH_HALTED;
--	fotg210_turn_off_all_ports(fotg210);
--	spin_unlock_irq(&fotg210->lock);
--}
--
--/* fotg210_shutdown kick in for silicon on any bus (not just pci, etc).
-- * This forcibly disables dma and IRQs, helping kexec and other cases
-- * where the next system software may expect clean state.
-- */
--static void fotg210_shutdown(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
--	spin_lock_irq(&fotg210->lock);
--	fotg210->shutdown = true;
--	fotg210->rh_state = FOTG210_RH_STOPPING;
--	fotg210->enabled_hrtimer_events = 0;
--	spin_unlock_irq(&fotg210->lock);
--
--	fotg210_silence_controller(fotg210);
--
--	hrtimer_cancel(&fotg210->hrtimer);
--}
--
--/* fotg210_work is called from some interrupts, timers, and so on.
-- * it calls driver completion functions, after dropping fotg210->lock.
-- */
--static void fotg210_work(struct fotg210_hcd *fotg210)
--{
--	/* another CPU may drop fotg210->lock during a schedule scan while
--	 * it reports urb completions.  this flag guards against bogus
--	 * attempts at re-entrant schedule scanning.
--	 */
--	if (fotg210->scanning) {
--		fotg210->need_rescan = true;
--		return;
--	}
--	fotg210->scanning = true;
--
--rescan:
--	fotg210->need_rescan = false;
--	if (fotg210->async_count)
--		scan_async(fotg210);
--	if (fotg210->intr_count > 0)
--		scan_intr(fotg210);
--	if (fotg210->isoc_count > 0)
--		scan_isoc(fotg210);
--	if (fotg210->need_rescan)
--		goto rescan;
--	fotg210->scanning = false;
--
--	/* the IO watchdog guards against hardware or driver bugs that
--	 * misplace IRQs, and should let us run completely without IRQs.
--	 * such lossage has been observed on both VT6202 and VT8235.
--	 */
--	turn_on_io_watchdog(fotg210);
--}
--
--/* Called when the fotg210_hcd module is removed.
-- */
--static void fotg210_stop(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
--	fotg210_dbg(fotg210, "stop\n");
--
--	/* no more interrupts ... */
--
--	spin_lock_irq(&fotg210->lock);
--	fotg210->enabled_hrtimer_events = 0;
--	spin_unlock_irq(&fotg210->lock);
--
--	fotg210_quiesce(fotg210);
--	fotg210_silence_controller(fotg210);
--	fotg210_reset(fotg210);
--
--	hrtimer_cancel(&fotg210->hrtimer);
--	remove_sysfs_files(fotg210);
--	remove_debug_files(fotg210);
--
--	/* root hub is shut down separately (first, when possible) */
--	spin_lock_irq(&fotg210->lock);
--	end_free_itds(fotg210);
--	spin_unlock_irq(&fotg210->lock);
--	fotg210_mem_cleanup(fotg210);
--
--#ifdef FOTG210_STATS
--	fotg210_dbg(fotg210, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
--			fotg210->stats.normal, fotg210->stats.error,
--			fotg210->stats.iaa, fotg210->stats.lost_iaa);
--	fotg210_dbg(fotg210, "complete %ld unlink %ld\n",
--			fotg210->stats.complete, fotg210->stats.unlink);
--#endif
--
--	dbg_status(fotg210, "fotg210_stop completed",
--			fotg210_readl(fotg210, &fotg210->regs->status));
--}
--
--/* one-time init, only for memory state */
--static int hcd_fotg210_init(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	u32 temp;
--	int retval;
--	u32 hcc_params;
--	struct fotg210_qh_hw *hw;
--
--	spin_lock_init(&fotg210->lock);
--
--	/*
--	 * keep io watchdog by default, those good HCDs could turn off it later
--	 */
--	fotg210->need_io_watchdog = 1;
--
--	hrtimer_init(&fotg210->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
--	fotg210->hrtimer.function = fotg210_hrtimer_func;
--	fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
--
--	hcc_params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
--	/*
--	 * by default set standard 80% (== 100 usec/uframe) max periodic
--	 * bandwidth as required by USB 2.0
--	 */
--	fotg210->uframe_periodic_max = 100;
--
--	/*
--	 * hw default: 1K periodic list heads, one per frame.
--	 * periodic_size can shrink by USBCMD update if hcc_params allows.
--	 */
--	fotg210->periodic_size = DEFAULT_I_TDPS;
--	INIT_LIST_HEAD(&fotg210->intr_qh_list);
--	INIT_LIST_HEAD(&fotg210->cached_itd_list);
--
--	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
--		/* periodic schedule size can be smaller than default */
--		switch (FOTG210_TUNE_FLS) {
--		case 0:
--			fotg210->periodic_size = 1024;
--			break;
--		case 1:
--			fotg210->periodic_size = 512;
--			break;
--		case 2:
--			fotg210->periodic_size = 256;
--			break;
--		default:
--			BUG();
--		}
--	}
--	retval = fotg210_mem_init(fotg210, GFP_KERNEL);
--	if (retval < 0)
--		return retval;
--
--	/* controllers may cache some of the periodic schedule ... */
--	fotg210->i_thresh = 2;
--
--	/*
--	 * dedicate a qh for the async ring head, since we couldn't unlink
--	 * a 'real' qh without stopping the async schedule [4.8].  use it
--	 * as the 'reclamation list head' too.
--	 * its dummy is used in hw_alt_next of many tds, to prevent the qh
--	 * from automatically advancing to the next td after short reads.
--	 */
--	fotg210->async->qh_next.qh = NULL;
--	hw = fotg210->async->hw;
--	hw->hw_next = QH_NEXT(fotg210, fotg210->async->qh_dma);
--	hw->hw_info1 = cpu_to_hc32(fotg210, QH_HEAD);
--	hw->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
--	hw->hw_qtd_next = FOTG210_LIST_END(fotg210);
--	fotg210->async->qh_state = QH_STATE_LINKED;
--	hw->hw_alt_next = QTD_NEXT(fotg210, fotg210->async->dummy->qtd_dma);
--
--	/* clear interrupt enables, set irq latency */
--	if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
--		log2_irq_thresh = 0;
--	temp = 1 << (16 + log2_irq_thresh);
--	if (HCC_CANPARK(hcc_params)) {
--		/* HW default park == 3, on hardware that supports it (like
--		 * NVidia and ALI silicon), maximizes throughput on the async
--		 * schedule by avoiding QH fetches between transfers.
--		 *
--		 * With fast usb storage devices and NForce2, "park" seems to
--		 * make problems:  throughput reduction (!), data errors...
--		 */
--		if (park) {
--			park = min_t(unsigned, park, 3);
--			temp |= CMD_PARK;
--			temp |= park << 8;
--		}
--		fotg210_dbg(fotg210, "park %d\n", park);
--	}
--	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
--		/* periodic schedule size can be smaller than default */
--		temp &= ~(3 << 2);
--		temp |= (FOTG210_TUNE_FLS << 2);
--	}
--	fotg210->command = temp;
--
--	/* Accept arbitrarily long scatter-gather lists */
--	if (!hcd->localmem_pool)
--		hcd->self.sg_tablesize = ~0;
--	return 0;
--}
--
--/* start HC running; it's halted, hcd_fotg210_init() has been run (once) */
--static int fotg210_run(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	u32 temp;
--
--	hcd->uses_new_polling = 1;
--
--	/* EHCI spec section 4.1 */
--
--	fotg210_writel(fotg210, fotg210->periodic_dma,
--			&fotg210->regs->frame_list);
--	fotg210_writel(fotg210, (u32)fotg210->async->qh_dma,
--			&fotg210->regs->async_next);
--
--	/*
--	 * hcc_params controls whether fotg210->regs->segment must (!!!)
--	 * be used; it constrains QH/ITD/SITD and QTD locations.
--	 * dma_pool consistent memory always uses segment zero.
--	 * streaming mappings for I/O buffers, like dma_map_single(),
--	 * can return segments above 4GB, if the device allows.
--	 *
--	 * NOTE:  the dma mask is visible through dev->dma_mask, so
--	 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
--	 * Scsi_Host.highmem_io, and so forth.  It's readonly to all
--	 * host side drivers though.
--	 */
--	fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
--	/*
--	 * Philips, Intel, and maybe others need CMD_RUN before the
--	 * root hub will detect new devices (why?); NEC doesn't
--	 */
--	fotg210->command &= ~(CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
--	fotg210->command |= CMD_RUN;
--	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--	dbg_cmd(fotg210, "init", fotg210->command);
--
--	/*
--	 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
--	 * are explicitly handed to companion controller(s), so no TT is
--	 * involved with the root hub.  (Except where one is integrated,
--	 * and there's no companion controller unless maybe for USB OTG.)
--	 *
--	 * Turning on the CF flag will transfer ownership of all ports
--	 * from the companions to the EHCI controller.  If any of the
--	 * companions are in the middle of a port reset at the time, it
--	 * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
--	 * guarantees that no resets are in progress.  After we set CF,
--	 * a short delay lets the hardware catch up; new resets shouldn't
--	 * be started before the port switching actions could complete.
--	 */
--	down_write(&ehci_cf_port_reset_rwsem);
--	fotg210->rh_state = FOTG210_RH_RUNNING;
--	/* unblock posted writes */
--	fotg210_readl(fotg210, &fotg210->regs->command);
--	usleep_range(5000, 10000);
--	up_write(&ehci_cf_port_reset_rwsem);
--	fotg210->last_periodic_enable = ktime_get_real();
--
--	temp = HC_VERSION(fotg210,
--			fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
--	fotg210_info(fotg210,
--			"USB %x.%x started, EHCI %x.%02x\n",
--			((fotg210->sbrn & 0xf0) >> 4), (fotg210->sbrn & 0x0f),
--			temp >> 8, temp & 0xff);
--
--	fotg210_writel(fotg210, INTR_MASK,
--			&fotg210->regs->intr_enable); /* Turn On Interrupts */
--
--	/* GRR this is run-once init(), being done every time the HC starts.
--	 * So long as they're part of class devices, we can't do it init()
--	 * since the class device isn't created that early.
--	 */
--	create_debug_files(fotg210);
--	create_sysfs_files(fotg210);
--
--	return 0;
--}
--
--static int fotg210_setup(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	int retval;
--
--	fotg210->regs = (void __iomem *)fotg210->caps +
--			HC_LENGTH(fotg210,
--			fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
--	dbg_hcs_params(fotg210, "reset");
--	dbg_hcc_params(fotg210, "reset");
--
--	/* cache this readonly data; minimize chip reads */
--	fotg210->hcs_params = fotg210_readl(fotg210,
--			&fotg210->caps->hcs_params);
--
--	fotg210->sbrn = HCD_USB2;
--
--	/* data structure init */
--	retval = hcd_fotg210_init(hcd);
--	if (retval)
--		return retval;
--
--	retval = fotg210_halt(fotg210);
--	if (retval)
--		return retval;
--
--	fotg210_reset(fotg210);
--
--	return 0;
--}
--
--static irqreturn_t fotg210_irq(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	u32 status, masked_status, pcd_status = 0, cmd;
--	int bh;
--
--	spin_lock(&fotg210->lock);
--
--	status = fotg210_readl(fotg210, &fotg210->regs->status);
--
--	/* e.g. cardbus physical eject */
--	if (status == ~(u32) 0) {
--		fotg210_dbg(fotg210, "device removed\n");
--		goto dead;
--	}
--
--	/*
--	 * We don't use STS_FLR, but some controllers don't like it to
--	 * remain on, so mask it out along with the other status bits.
--	 */
--	masked_status = status & (INTR_MASK | STS_FLR);
--
--	/* Shared IRQ? */
--	if (!masked_status ||
--			unlikely(fotg210->rh_state == FOTG210_RH_HALTED)) {
--		spin_unlock(&fotg210->lock);
--		return IRQ_NONE;
--	}
--
--	/* clear (just) interrupts */
--	fotg210_writel(fotg210, masked_status, &fotg210->regs->status);
--	cmd = fotg210_readl(fotg210, &fotg210->regs->command);
--	bh = 0;
--
--	/* unrequested/ignored: Frame List Rollover */
--	dbg_status(fotg210, "irq", status);
--
--	/* INT, ERR, and IAA interrupt rates can be throttled */
--
--	/* normal [4.15.1.2] or error [4.15.1.1] completion */
--	if (likely((status & (STS_INT|STS_ERR)) != 0)) {
--		if (likely((status & STS_ERR) == 0))
--			INCR(fotg210->stats.normal);
--		else
--			INCR(fotg210->stats.error);
--		bh = 1;
--	}
--
--	/* complete the unlinking of some qh [4.15.2.3] */
--	if (status & STS_IAA) {
--
--		/* Turn off the IAA watchdog */
--		fotg210->enabled_hrtimer_events &=
--			~BIT(FOTG210_HRTIMER_IAA_WATCHDOG);
--
--		/*
--		 * Mild optimization: Allow another IAAD to reset the
--		 * hrtimer, if one occurs before the next expiration.
--		 * In theory we could always cancel the hrtimer, but
--		 * tests show that about half the time it will be reset
--		 * for some other event anyway.
--		 */
--		if (fotg210->next_hrtimer_event == FOTG210_HRTIMER_IAA_WATCHDOG)
--			++fotg210->next_hrtimer_event;
--
--		/* guard against (alleged) silicon errata */
--		if (cmd & CMD_IAAD)
--			fotg210_dbg(fotg210, "IAA with IAAD still set?\n");
--		if (fotg210->async_iaa) {
--			INCR(fotg210->stats.iaa);
--			end_unlink_async(fotg210);
--		} else
--			fotg210_dbg(fotg210, "IAA with nothing unlinked?\n");
--	}
--
--	/* remote wakeup [4.3.1] */
--	if (status & STS_PCD) {
--		int pstatus;
--		u32 __iomem *status_reg = &fotg210->regs->port_status;
--
--		/* kick root hub later */
--		pcd_status = status;
--
--		/* resume root hub? */
--		if (fotg210->rh_state == FOTG210_RH_SUSPENDED)
--			usb_hcd_resume_root_hub(hcd);
--
--		pstatus = fotg210_readl(fotg210, status_reg);
--
--		if (test_bit(0, &fotg210->suspended_ports) &&
--				((pstatus & PORT_RESUME) ||
--				!(pstatus & PORT_SUSPEND)) &&
--				(pstatus & PORT_PE) &&
--				fotg210->reset_done[0] == 0) {
--
--			/* start 20 msec resume signaling from this port,
--			 * and make hub_wq collect PORT_STAT_C_SUSPEND to
--			 * stop that signaling.  Use 5 ms extra for safety,
--			 * like usb_port_resume() does.
--			 */
--			fotg210->reset_done[0] = jiffies + msecs_to_jiffies(25);
--			set_bit(0, &fotg210->resuming_ports);
--			fotg210_dbg(fotg210, "port 1 remote wakeup\n");
--			mod_timer(&hcd->rh_timer, fotg210->reset_done[0]);
--		}
--	}
--
--	/* PCI errors [4.15.2.4] */
--	if (unlikely((status & STS_FATAL) != 0)) {
--		fotg210_err(fotg210, "fatal error\n");
--		dbg_cmd(fotg210, "fatal", cmd);
--		dbg_status(fotg210, "fatal", status);
--dead:
--		usb_hc_died(hcd);
--
--		/* Don't let the controller do anything more */
--		fotg210->shutdown = true;
--		fotg210->rh_state = FOTG210_RH_STOPPING;
--		fotg210->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
--		fotg210_writel(fotg210, fotg210->command,
--				&fotg210->regs->command);
--		fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
--		fotg210_handle_controller_death(fotg210);
--
--		/* Handle completions when the controller stops */
--		bh = 0;
--	}
--
--	if (bh)
--		fotg210_work(fotg210);
--	spin_unlock(&fotg210->lock);
--	if (pcd_status)
--		usb_hcd_poll_rh_status(hcd);
--	return IRQ_HANDLED;
--}
--
--/* non-error returns are a promise to giveback() the urb later
-- * we drop ownership so next owner (or urb unlink) can get it
-- *
-- * urb + dev is in hcd.self.controller.urb_list
-- * we're queueing TDs onto software and hardware lists
-- *
-- * hcd-specific init for hcpriv hasn't been done yet
-- *
-- * NOTE:  control, bulk, and interrupt share the same code to append TDs
-- * to a (possibly active) QH, and the same QH scanning code.
-- */
--static int fotg210_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
--		gfp_t mem_flags)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	struct list_head qtd_list;
--
--	INIT_LIST_HEAD(&qtd_list);
--
--	switch (usb_pipetype(urb->pipe)) {
--	case PIPE_CONTROL:
--		/* qh_completions() code doesn't handle all the fault cases
--		 * in multi-TD control transfers.  Even 1KB is rare anyway.
--		 */
--		if (urb->transfer_buffer_length > (16 * 1024))
--			return -EMSGSIZE;
--		fallthrough;
--	/* case PIPE_BULK: */
--	default:
--		if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
--			return -ENOMEM;
--		return submit_async(fotg210, urb, &qtd_list, mem_flags);
--
--	case PIPE_INTERRUPT:
--		if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
--			return -ENOMEM;
--		return intr_submit(fotg210, urb, &qtd_list, mem_flags);
--
--	case PIPE_ISOCHRONOUS:
--		return itd_submit(fotg210, urb, mem_flags);
--	}
--}
--
--/* remove from hardware lists
-- * completions normally happen asynchronously
-- */
--
--static int fotg210_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	struct fotg210_qh *qh;
--	unsigned long flags;
--	int rc;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
--	if (rc)
--		goto done;
--
--	switch (usb_pipetype(urb->pipe)) {
--	/* case PIPE_CONTROL: */
--	/* case PIPE_BULK:*/
--	default:
--		qh = (struct fotg210_qh *) urb->hcpriv;
--		if (!qh)
--			break;
--		switch (qh->qh_state) {
--		case QH_STATE_LINKED:
--		case QH_STATE_COMPLETING:
--			start_unlink_async(fotg210, qh);
--			break;
--		case QH_STATE_UNLINK:
--		case QH_STATE_UNLINK_WAIT:
--			/* already started */
--			break;
--		case QH_STATE_IDLE:
--			/* QH might be waiting for a Clear-TT-Buffer */
--			qh_completions(fotg210, qh);
--			break;
--		}
--		break;
--
--	case PIPE_INTERRUPT:
--		qh = (struct fotg210_qh *) urb->hcpriv;
--		if (!qh)
--			break;
--		switch (qh->qh_state) {
--		case QH_STATE_LINKED:
--		case QH_STATE_COMPLETING:
--			start_unlink_intr(fotg210, qh);
--			break;
--		case QH_STATE_IDLE:
--			qh_completions(fotg210, qh);
--			break;
--		default:
--			fotg210_dbg(fotg210, "bogus qh %p state %d\n",
--					qh, qh->qh_state);
--			goto done;
--		}
--		break;
--
--	case PIPE_ISOCHRONOUS:
--		/* itd... */
--
--		/* wait till next completion, do it then. */
--		/* completion irqs can wait up to 1024 msec, */
--		break;
--	}
--done:
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--	return rc;
--}
--
--/* bulk qh holds the data toggle */
--
--static void fotg210_endpoint_disable(struct usb_hcd *hcd,
--		struct usb_host_endpoint *ep)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	unsigned long flags;
--	struct fotg210_qh *qh, *tmp;
--
--	/* ASSERT:  any requests/urbs are being unlinked */
--	/* ASSERT:  nobody can be submitting urbs for this any more */
--
--rescan:
--	spin_lock_irqsave(&fotg210->lock, flags);
--	qh = ep->hcpriv;
--	if (!qh)
--		goto done;
--
--	/* endpoints can be iso streams.  for now, we don't
--	 * accelerate iso completions ... so spin a while.
--	 */
--	if (qh->hw == NULL) {
--		struct fotg210_iso_stream *stream = ep->hcpriv;
--
--		if (!list_empty(&stream->td_list))
--			goto idle_timeout;
--
--		/* BUG_ON(!list_empty(&stream->free_list)); */
--		kfree(stream);
--		goto done;
--	}
--
--	if (fotg210->rh_state < FOTG210_RH_RUNNING)
--		qh->qh_state = QH_STATE_IDLE;
--	switch (qh->qh_state) {
--	case QH_STATE_LINKED:
--	case QH_STATE_COMPLETING:
--		for (tmp = fotg210->async->qh_next.qh;
--				tmp && tmp != qh;
--				tmp = tmp->qh_next.qh)
--			continue;
--		/* periodic qh self-unlinks on empty, and a COMPLETING qh
--		 * may already be unlinked.
--		 */
--		if (tmp)
--			start_unlink_async(fotg210, qh);
--		fallthrough;
--	case QH_STATE_UNLINK:		/* wait for hw to finish? */
--	case QH_STATE_UNLINK_WAIT:
--idle_timeout:
--		spin_unlock_irqrestore(&fotg210->lock, flags);
--		schedule_timeout_uninterruptible(1);
--		goto rescan;
--	case QH_STATE_IDLE:		/* fully unlinked */
--		if (qh->clearing_tt)
--			goto idle_timeout;
--		if (list_empty(&qh->qtd_list)) {
--			qh_destroy(fotg210, qh);
--			break;
--		}
--		fallthrough;
--	default:
--		/* caller was supposed to have unlinked any requests;
--		 * that's not our job.  just leak this memory.
--		 */
--		fotg210_err(fotg210, "qh %p (#%02x) state %d%s\n",
--				qh, ep->desc.bEndpointAddress, qh->qh_state,
--				list_empty(&qh->qtd_list) ? "" : "(has tds)");
--		break;
--	}
--done:
--	ep->hcpriv = NULL;
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static void fotg210_endpoint_reset(struct usb_hcd *hcd,
--		struct usb_host_endpoint *ep)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--	struct fotg210_qh *qh;
--	int eptype = usb_endpoint_type(&ep->desc);
--	int epnum = usb_endpoint_num(&ep->desc);
--	int is_out = usb_endpoint_dir_out(&ep->desc);
--	unsigned long flags;
--
--	if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
--		return;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--	qh = ep->hcpriv;
--
--	/* For Bulk and Interrupt endpoints we maintain the toggle state
--	 * in the hardware; the toggle bits in udev aren't used at all.
--	 * When an endpoint is reset by usb_clear_halt() we must reset
--	 * the toggle bit in the QH.
--	 */
--	if (qh) {
--		usb_settoggle(qh->dev, epnum, is_out, 0);
--		if (!list_empty(&qh->qtd_list)) {
--			WARN_ONCE(1, "clear_halt for a busy endpoint\n");
--		} else if (qh->qh_state == QH_STATE_LINKED ||
--				qh->qh_state == QH_STATE_COMPLETING) {
--
--			/* The toggle value in the QH can't be updated
--			 * while the QH is active.  Unlink it now;
--			 * re-linking will call qh_refresh().
--			 */
--			if (eptype == USB_ENDPOINT_XFER_BULK)
--				start_unlink_async(fotg210, qh);
--			else
--				start_unlink_intr(fotg210, qh);
--		}
--	}
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static int fotg210_get_frame(struct usb_hcd *hcd)
--{
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
--	return (fotg210_read_frame_index(fotg210) >> 3) %
--		fotg210->periodic_size;
--}
--
--/* The EHCI in ChipIdea HDRC cannot be a separate module or device,
-- * because its registers (and irq) are shared between host/gadget/otg
-- * functions  and in order to facilitate role switching we cannot
-- * give the fotg210 driver exclusive access to those.
-- */
--MODULE_DESCRIPTION(DRIVER_DESC);
--MODULE_AUTHOR(DRIVER_AUTHOR);
--MODULE_LICENSE("GPL");
--
--static const struct hc_driver fotg210_fotg210_hc_driver = {
--	.description		= hcd_name,
--	.product_desc		= "Faraday USB2.0 Host Controller",
--	.hcd_priv_size		= sizeof(struct fotg210_hcd),
--
--	/*
--	 * generic hardware linkage
--	 */
--	.irq			= fotg210_irq,
--	.flags			= HCD_MEMORY | HCD_DMA | HCD_USB2,
--
--	/*
--	 * basic lifecycle operations
--	 */
--	.reset			= hcd_fotg210_init,
--	.start			= fotg210_run,
--	.stop			= fotg210_stop,
--	.shutdown		= fotg210_shutdown,
--
--	/*
--	 * managing i/o requests and associated device resources
--	 */
--	.urb_enqueue		= fotg210_urb_enqueue,
--	.urb_dequeue		= fotg210_urb_dequeue,
--	.endpoint_disable	= fotg210_endpoint_disable,
--	.endpoint_reset		= fotg210_endpoint_reset,
--
--	/*
--	 * scheduling support
--	 */
--	.get_frame_number	= fotg210_get_frame,
--
--	/*
--	 * root hub support
--	 */
--	.hub_status_data	= fotg210_hub_status_data,
--	.hub_control		= fotg210_hub_control,
--	.bus_suspend		= fotg210_bus_suspend,
--	.bus_resume		= fotg210_bus_resume,
--
--	.relinquish_port	= fotg210_relinquish_port,
--	.port_handed_over	= fotg210_port_handed_over,
--
--	.clear_tt_buffer_complete = fotg210_clear_tt_buffer_complete,
--};
--
--static void fotg210_init(struct fotg210_hcd *fotg210)
--{
--	u32 value;
--
--	iowrite32(GMIR_MDEV_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
--			&fotg210->regs->gmir);
--
--	value = ioread32(&fotg210->regs->otgcsr);
--	value &= ~OTGCSR_A_BUS_DROP;
--	value |= OTGCSR_A_BUS_REQ;
--	iowrite32(value, &fotg210->regs->otgcsr);
--}
--
--/*
-- * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
-- *
-- * Allocates basic resources for this USB host controller, and
-- * then invokes the start() method for the HCD associated with it
-- * through the hotplug entry's driver_data.
-- */
--static int fotg210_hcd_probe(struct platform_device *pdev)
--{
--	struct device *dev = &pdev->dev;
--	struct usb_hcd *hcd;
--	struct resource *res;
--	int irq;
--	int retval;
--	struct fotg210_hcd *fotg210;
--
--	if (usb_disabled())
--		return -ENODEV;
--
--	pdev->dev.power.power_state = PMSG_ON;
--
--	irq = platform_get_irq(pdev, 0);
--	if (irq < 0)
--		return irq;
--
--	hcd = usb_create_hcd(&fotg210_fotg210_hc_driver, dev,
--			dev_name(dev));
--	if (!hcd) {
--		dev_err(dev, "failed to create hcd\n");
--		retval = -ENOMEM;
--		goto fail_create_hcd;
--	}
--
--	hcd->has_tt = 1;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
--	if (IS_ERR(hcd->regs)) {
--		retval = PTR_ERR(hcd->regs);
--		goto failed_put_hcd;
--	}
--
--	hcd->rsrc_start = res->start;
--	hcd->rsrc_len = resource_size(res);
--
--	fotg210 = hcd_to_fotg210(hcd);
--
--	fotg210->caps = hcd->regs;
--
--	/* It's OK not to supply this clock */
--	fotg210->pclk = clk_get(dev, "PCLK");
--	if (!IS_ERR(fotg210->pclk)) {
--		retval = clk_prepare_enable(fotg210->pclk);
--		if (retval) {
--			dev_err(dev, "failed to enable PCLK\n");
--			goto failed_put_hcd;
--		}
--	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
--		/*
--		 * Percolate deferrals, for anything else,
--		 * just live without the clocking.
--		 */
--		retval = PTR_ERR(fotg210->pclk);
--		goto failed_dis_clk;
--	}
--
--	retval = fotg210_setup(hcd);
--	if (retval)
--		goto failed_dis_clk;
--
--	fotg210_init(fotg210);
--
--	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
--	if (retval) {
--		dev_err(dev, "failed to add hcd with err %d\n", retval);
--		goto failed_dis_clk;
--	}
--	device_wakeup_enable(hcd->self.controller);
--	platform_set_drvdata(pdev, hcd);
--
--	return retval;
--
--failed_dis_clk:
--	if (!IS_ERR(fotg210->pclk)) {
--		clk_disable_unprepare(fotg210->pclk);
--		clk_put(fotg210->pclk);
--	}
--failed_put_hcd:
--	usb_put_hcd(hcd);
--fail_create_hcd:
--	dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
--	return retval;
--}
--
--/*
-- * fotg210_hcd_remove - shutdown processing for EHCI HCDs
-- * @dev: USB Host Controller being removed
-- *
-- */
--static int fotg210_hcd_remove(struct platform_device *pdev)
--{
--	struct usb_hcd *hcd = platform_get_drvdata(pdev);
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
--	if (!IS_ERR(fotg210->pclk)) {
--		clk_disable_unprepare(fotg210->pclk);
--		clk_put(fotg210->pclk);
--	}
--
--	usb_remove_hcd(hcd);
--	usb_put_hcd(hcd);
--
--	return 0;
--}
--
--#ifdef CONFIG_OF
--static const struct of_device_id fotg210_of_match[] = {
--	{ .compatible = "faraday,fotg210" },
--	{},
--};
--MODULE_DEVICE_TABLE(of, fotg210_of_match);
--#endif
--
--static struct platform_driver fotg210_hcd_driver = {
--	.driver = {
--		.name   = "fotg210-hcd",
--		.of_match_table = of_match_ptr(fotg210_of_match),
--	},
--	.probe  = fotg210_hcd_probe,
--	.remove = fotg210_hcd_remove,
--};
--
--static int __init fotg210_hcd_init(void)
--{
--	int retval = 0;
--
--	if (usb_disabled())
--		return -ENODEV;
--
--	set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
--	if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
--			test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
--		pr_warn("Warning! fotg210_hcd should always be loaded before uhci_hcd and ohci_hcd, not after\n");
--
--	pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd\n",
--			hcd_name, sizeof(struct fotg210_qh),
--			sizeof(struct fotg210_qtd),
--			sizeof(struct fotg210_itd));
--
--	fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
--
--	retval = platform_driver_register(&fotg210_hcd_driver);
--	if (retval < 0)
--		goto clean;
--	return retval;
--
--clean:
--	debugfs_remove(fotg210_debug_root);
--	fotg210_debug_root = NULL;
--
--	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
--	return retval;
--}
--module_init(fotg210_hcd_init);
--
--static void __exit fotg210_hcd_cleanup(void)
--{
--	platform_driver_unregister(&fotg210_hcd_driver);
--	debugfs_remove(fotg210_debug_root);
--	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
--}
--module_exit(fotg210_hcd_cleanup);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -0,0 +1,5727 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/* Faraday FOTG210 EHCI-like driver
-+ *
-+ * Copyright (c) 2013 Faraday Technology Corporation
-+ *
-+ * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ *	   Feng-Hsin Chiang <john453@faraday-tech.com>
-+ *	   Po-Yu Chuang <ratbert.chuang@gmail.com>
-+ *
-+ * Most of code borrowed from the Linux-3.7 EHCI driver
-+ */
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/device.h>
-+#include <linux/dmapool.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/vmalloc.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/hrtimer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/usb.h>
-+#include <linux/usb/hcd.h>
-+#include <linux/moduleparam.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/debugfs.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/clk.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/irq.h>
-+#include <asm/unaligned.h>
-+
-+#define DRIVER_AUTHOR "Yuan-Hsin Chen"
-+#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
-+static const char hcd_name[] = "fotg210_hcd";
-+
-+#undef FOTG210_URB_TRACE
-+#define FOTG210_STATS
-+
-+/* magic numbers that can affect system performance */
-+#define FOTG210_TUNE_CERR	3 /* 0-3 qtd retries; 0 == don't stop */
-+#define FOTG210_TUNE_RL_HS	4 /* nak throttle; see 4.9 */
-+#define FOTG210_TUNE_RL_TT	0
-+#define FOTG210_TUNE_MULT_HS	1 /* 1-3 transactions/uframe; 4.10.3 */
-+#define FOTG210_TUNE_MULT_TT	1
-+
-+/* Some drivers think it's safe to schedule isochronous transfers more than 256
-+ * ms into the future (partly as a result of an old bug in the scheduling
-+ * code).  In an attempt to avoid trouble, we will use a minimum scheduling
-+ * length of 512 frames instead of 256.
-+ */
-+#define FOTG210_TUNE_FLS 1 /* (medium) 512-frame schedule */
-+
-+/* Initial IRQ latency:  faster than hw default */
-+static int log2_irq_thresh; /* 0 to 6 */
-+module_param(log2_irq_thresh, int, S_IRUGO);
-+MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
-+
-+/* initial park setting:  slower than hw default */
-+static unsigned park;
-+module_param(park, uint, S_IRUGO);
-+MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
-+
-+/* for link power management(LPM) feature */
-+static unsigned int hird;
-+module_param(hird, int, S_IRUGO);
-+MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
-+
-+#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
-+
-+#include "fotg210-hcd.h"
-+
-+#define fotg210_dbg(fotg210, fmt, args...) \
-+	dev_dbg(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_err(fotg210, fmt, args...) \
-+	dev_err(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_info(fotg210, fmt, args...) \
-+	dev_info(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_warn(fotg210, fmt, args...) \
-+	dev_warn(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+
-+/* check the values in the HCSPARAMS register (host controller _Structural_
-+ * parameters) see EHCI spec, Table 2-4 for each value
-+ */
-+static void dbg_hcs_params(struct fotg210_hcd *fotg210, char *label)
-+{
-+	u32 params = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
-+
-+	fotg210_dbg(fotg210, "%s hcs_params 0x%x ports=%d\n", label, params,
-+			HCS_N_PORTS(params));
-+}
-+
-+/* check the values in the HCCPARAMS register (host controller _Capability_
-+ * parameters) see EHCI Spec, Table 2-5 for each value
-+ */
-+static void dbg_hcc_params(struct fotg210_hcd *fotg210, char *label)
-+{
-+	u32 params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+	fotg210_dbg(fotg210, "%s hcc_params %04x uframes %s%s\n", label,
-+			params,
-+			HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
-+			HCC_CANPARK(params) ? " park" : "");
-+}
-+
-+static void __maybe_unused
-+dbg_qtd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd)
-+{
-+	fotg210_dbg(fotg210, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
-+			hc32_to_cpup(fotg210, &qtd->hw_next),
-+			hc32_to_cpup(fotg210, &qtd->hw_alt_next),
-+			hc32_to_cpup(fotg210, &qtd->hw_token),
-+			hc32_to_cpup(fotg210, &qtd->hw_buf[0]));
-+	if (qtd->hw_buf[1])
-+		fotg210_dbg(fotg210, "  p1=%08x p2=%08x p3=%08x p4=%08x\n",
-+				hc32_to_cpup(fotg210, &qtd->hw_buf[1]),
-+				hc32_to_cpup(fotg210, &qtd->hw_buf[2]),
-+				hc32_to_cpup(fotg210, &qtd->hw_buf[3]),
-+				hc32_to_cpup(fotg210, &qtd->hw_buf[4]));
-+}
-+
-+static void __maybe_unused
-+dbg_qh(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	struct fotg210_qh_hw *hw = qh->hw;
-+
-+	fotg210_dbg(fotg210, "%s qh %p n%08x info %x %x qtd %x\n", label, qh,
-+			hw->hw_next, hw->hw_info1, hw->hw_info2,
-+			hw->hw_current);
-+
-+	dbg_qtd("overlay", fotg210, (struct fotg210_qtd *) &hw->hw_qtd_next);
-+}
-+
-+static void __maybe_unused
-+dbg_itd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
-+{
-+	fotg210_dbg(fotg210, "%s[%d] itd %p, next %08x, urb %p\n", label,
-+			itd->frame, itd, hc32_to_cpu(fotg210, itd->hw_next),
-+			itd->urb);
-+
-+	fotg210_dbg(fotg210,
-+			"  trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-+			hc32_to_cpu(fotg210, itd->hw_transaction[0]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[1]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[2]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[3]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[4]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[5]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[6]),
-+			hc32_to_cpu(fotg210, itd->hw_transaction[7]));
-+
-+	fotg210_dbg(fotg210,
-+			"  buf:   %08x %08x %08x %08x %08x %08x %08x\n",
-+			hc32_to_cpu(fotg210, itd->hw_bufp[0]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[1]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[2]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[3]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[4]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[5]),
-+			hc32_to_cpu(fotg210, itd->hw_bufp[6]));
-+
-+	fotg210_dbg(fotg210, "  index: %d %d %d %d %d %d %d %d\n",
-+			itd->index[0], itd->index[1], itd->index[2],
-+			itd->index[3], itd->index[4], itd->index[5],
-+			itd->index[6], itd->index[7]);
-+}
-+
-+static int __maybe_unused
-+dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
-+{
-+	return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
-+			label, label[0] ? " " : "", status,
-+			(status & STS_ASS) ? " Async" : "",
-+			(status & STS_PSS) ? " Periodic" : "",
-+			(status & STS_RECL) ? " Recl" : "",
-+			(status & STS_HALT) ? " Halt" : "",
-+			(status & STS_IAA) ? " IAA" : "",
-+			(status & STS_FATAL) ? " FATAL" : "",
-+			(status & STS_FLR) ? " FLR" : "",
-+			(status & STS_PCD) ? " PCD" : "",
-+			(status & STS_ERR) ? " ERR" : "",
-+			(status & STS_INT) ? " INT" : "");
-+}
-+
-+static int __maybe_unused
-+dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
-+{
-+	return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
-+			label, label[0] ? " " : "", enable,
-+			(enable & STS_IAA) ? " IAA" : "",
-+			(enable & STS_FATAL) ? " FATAL" : "",
-+			(enable & STS_FLR) ? " FLR" : "",
-+			(enable & STS_PCD) ? " PCD" : "",
-+			(enable & STS_ERR) ? " ERR" : "",
-+			(enable & STS_INT) ? " INT" : "");
-+}
-+
-+static const char *const fls_strings[] = { "1024", "512", "256", "??" };
-+
-+static int dbg_command_buf(char *buf, unsigned len, const char *label,
-+		u32 command)
-+{
-+	return scnprintf(buf, len,
-+			"%s%scommand %07x %s=%d ithresh=%d%s%s%s period=%s%s %s",
-+			label, label[0] ? " " : "", command,
-+			(command & CMD_PARK) ? " park" : "(park)",
-+			CMD_PARK_CNT(command),
-+			(command >> 16) & 0x3f,
-+			(command & CMD_IAAD) ? " IAAD" : "",
-+			(command & CMD_ASE) ? " Async" : "",
-+			(command & CMD_PSE) ? " Periodic" : "",
-+			fls_strings[(command >> 2) & 0x3],
-+			(command & CMD_RESET) ? " Reset" : "",
-+			(command & CMD_RUN) ? "RUN" : "HALT");
-+}
-+
-+static char *dbg_port_buf(char *buf, unsigned len, const char *label, int port,
-+		u32 status)
-+{
-+	char *sig;
-+
-+	/* signaling state */
-+	switch (status & (3 << 10)) {
-+	case 0 << 10:
-+		sig = "se0";
-+		break;
-+	case 1 << 10:
-+		sig = "k";
-+		break; /* low speed */
-+	case 2 << 10:
-+		sig = "j";
-+		break;
-+	default:
-+		sig = "?";
-+		break;
-+	}
-+
-+	scnprintf(buf, len, "%s%sport:%d status %06x %d sig=%s%s%s%s%s%s%s%s",
-+			label, label[0] ? " " : "", port, status,
-+			status >> 25, /*device address */
-+			sig,
-+			(status & PORT_RESET) ? " RESET" : "",
-+			(status & PORT_SUSPEND) ? " SUSPEND" : "",
-+			(status & PORT_RESUME) ? " RESUME" : "",
-+			(status & PORT_PEC) ? " PEC" : "",
-+			(status & PORT_PE) ? " PE" : "",
-+			(status & PORT_CSC) ? " CSC" : "",
-+			(status & PORT_CONNECT) ? " CONNECT" : "");
-+
-+	return buf;
-+}
-+
-+/* functions have the "wrong" filename when they're output... */
-+#define dbg_status(fotg210, label, status) {			\
-+	char _buf[80];						\
-+	dbg_status_buf(_buf, sizeof(_buf), label, status);	\
-+	fotg210_dbg(fotg210, "%s\n", _buf);			\
-+}
-+
-+#define dbg_cmd(fotg210, label, command) {			\
-+	char _buf[80];						\
-+	dbg_command_buf(_buf, sizeof(_buf), label, command);	\
-+	fotg210_dbg(fotg210, "%s\n", _buf);			\
-+}
-+
-+#define dbg_port(fotg210, label, port, status) {			       \
-+	char _buf[80];							       \
-+	fotg210_dbg(fotg210, "%s\n",					       \
-+			dbg_port_buf(_buf, sizeof(_buf), label, port, status));\
-+}
-+
-+/* troubleshooting help: expose state in debugfs */
-+static int debug_async_open(struct inode *, struct file *);
-+static int debug_periodic_open(struct inode *, struct file *);
-+static int debug_registers_open(struct inode *, struct file *);
-+static int debug_async_open(struct inode *, struct file *);
-+
-+static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
-+static int debug_close(struct inode *, struct file *);
-+
-+static const struct file_operations debug_async_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= debug_async_open,
-+	.read		= debug_output,
-+	.release	= debug_close,
-+	.llseek		= default_llseek,
-+};
-+static const struct file_operations debug_periodic_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= debug_periodic_open,
-+	.read		= debug_output,
-+	.release	= debug_close,
-+	.llseek		= default_llseek,
-+};
-+static const struct file_operations debug_registers_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= debug_registers_open,
-+	.read		= debug_output,
-+	.release	= debug_close,
-+	.llseek		= default_llseek,
-+};
-+
-+static struct dentry *fotg210_debug_root;
-+
-+struct debug_buffer {
-+	ssize_t (*fill_func)(struct debug_buffer *);	/* fill method */
-+	struct usb_bus *bus;
-+	struct mutex mutex;	/* protect filling of buffer */
-+	size_t count;		/* number of characters filled into buffer */
-+	char *output_buf;
-+	size_t alloc_size;
-+};
-+
-+static inline char speed_char(u32 scratch)
-+{
-+	switch (scratch & (3 << 12)) {
-+	case QH_FULL_SPEED:
-+		return 'f';
-+
-+	case QH_LOW_SPEED:
-+		return 'l';
-+
-+	case QH_HIGH_SPEED:
-+		return 'h';
-+
-+	default:
-+		return '?';
-+	}
-+}
-+
-+static inline char token_mark(struct fotg210_hcd *fotg210, __hc32 token)
-+{
-+	__u32 v = hc32_to_cpu(fotg210, token);
-+
-+	if (v & QTD_STS_ACTIVE)
-+		return '*';
-+	if (v & QTD_STS_HALT)
-+		return '-';
-+	if (!IS_SHORT_READ(v))
-+		return ' ';
-+	/* tries to advance through hw_alt_next */
-+	return '/';
-+}
-+
-+static void qh_lines(struct fotg210_hcd *fotg210, struct fotg210_qh *qh,
-+		char **nextp, unsigned *sizep)
-+{
-+	u32 scratch;
-+	u32 hw_curr;
-+	struct fotg210_qtd *td;
-+	unsigned temp;
-+	unsigned size = *sizep;
-+	char *next = *nextp;
-+	char mark;
-+	__le32 list_end = FOTG210_LIST_END(fotg210);
-+	struct fotg210_qh_hw *hw = qh->hw;
-+
-+	if (hw->hw_qtd_next == list_end) /* NEC does this */
-+		mark = '@';
-+	else
-+		mark = token_mark(fotg210, hw->hw_token);
-+	if (mark == '/') { /* qh_alt_next controls qh advance? */
-+		if ((hw->hw_alt_next & QTD_MASK(fotg210)) ==
-+		    fotg210->async->hw->hw_alt_next)
-+			mark = '#'; /* blocked */
-+		else if (hw->hw_alt_next == list_end)
-+			mark = '.'; /* use hw_qtd_next */
-+		/* else alt_next points to some other qtd */
-+	}
-+	scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-+	hw_curr = (mark == '*') ? hc32_to_cpup(fotg210, &hw->hw_current) : 0;
-+	temp = scnprintf(next, size,
-+			"qh/%p dev%d %cs ep%d %08x %08x(%08x%c %s nak%d)",
-+			qh, scratch & 0x007f,
-+			speed_char(scratch),
-+			(scratch >> 8) & 0x000f,
-+			scratch, hc32_to_cpup(fotg210, &hw->hw_info2),
-+			hc32_to_cpup(fotg210, &hw->hw_token), mark,
-+			(cpu_to_hc32(fotg210, QTD_TOGGLE) & hw->hw_token)
-+				? "data1" : "data0",
-+			(hc32_to_cpup(fotg210, &hw->hw_alt_next) >> 1) & 0x0f);
-+	size -= temp;
-+	next += temp;
-+
-+	/* hc may be modifying the list as we read it ... */
-+	list_for_each_entry(td, &qh->qtd_list, qtd_list) {
-+		scratch = hc32_to_cpup(fotg210, &td->hw_token);
-+		mark = ' ';
-+		if (hw_curr == td->qtd_dma)
-+			mark = '*';
-+		else if (hw->hw_qtd_next == cpu_to_hc32(fotg210, td->qtd_dma))
-+			mark = '+';
-+		else if (QTD_LENGTH(scratch)) {
-+			if (td->hw_alt_next == fotg210->async->hw->hw_alt_next)
-+				mark = '#';
-+			else if (td->hw_alt_next != list_end)
-+				mark = '/';
-+		}
-+		temp = snprintf(next, size,
-+				"\n\t%p%c%s len=%d %08x urb %p",
-+				td, mark, ({ char *tmp;
-+				switch ((scratch>>8)&0x03) {
-+				case 0:
-+					tmp = "out";
-+					break;
-+				case 1:
-+					tmp = "in";
-+					break;
-+				case 2:
-+					tmp = "setup";
-+					break;
-+				default:
-+					tmp = "?";
-+					break;
-+				 } tmp; }),
-+				(scratch >> 16) & 0x7fff,
-+				scratch,
-+				td->urb);
-+		if (size < temp)
-+			temp = size;
-+		size -= temp;
-+		next += temp;
-+		if (temp == size)
-+			goto done;
-+	}
-+
-+	temp = snprintf(next, size, "\n");
-+	if (size < temp)
-+		temp = size;
-+
-+	size -= temp;
-+	next += temp;
-+
-+done:
-+	*sizep = size;
-+	*nextp = next;
-+}
-+
-+static ssize_t fill_async_buffer(struct debug_buffer *buf)
-+{
-+	struct usb_hcd *hcd;
-+	struct fotg210_hcd *fotg210;
-+	unsigned long flags;
-+	unsigned temp, size;
-+	char *next;
-+	struct fotg210_qh *qh;
-+
-+	hcd = bus_to_hcd(buf->bus);
-+	fotg210 = hcd_to_fotg210(hcd);
-+	next = buf->output_buf;
-+	size = buf->alloc_size;
-+
-+	*next = 0;
-+
-+	/* dumps a snapshot of the async schedule.
-+	 * usually empty except for long-term bulk reads, or head.
-+	 * one QH per line, and TDs we know about
-+	 */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	for (qh = fotg210->async->qh_next.qh; size > 0 && qh;
-+			qh = qh->qh_next.qh)
-+		qh_lines(fotg210, qh, &next, &size);
-+	if (fotg210->async_unlink && size > 0) {
-+		temp = scnprintf(next, size, "\nunlink =\n");
-+		size -= temp;
-+		next += temp;
-+
-+		for (qh = fotg210->async_unlink; size > 0 && qh;
-+				qh = qh->unlink_next)
-+			qh_lines(fotg210, qh, &next, &size);
-+	}
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+	return strlen(buf->output_buf);
-+}
-+
-+/* count tds, get ep direction */
-+static unsigned output_buf_tds_dir(char *buf, struct fotg210_hcd *fotg210,
-+		struct fotg210_qh_hw *hw, struct fotg210_qh *qh, unsigned size)
-+{
-+	u32 scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-+	struct fotg210_qtd *qtd;
-+	char *type = "";
-+	unsigned temp = 0;
-+
-+	/* count tds, get ep direction */
-+	list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
-+		temp++;
-+		switch ((hc32_to_cpu(fotg210, qtd->hw_token) >> 8) & 0x03) {
-+		case 0:
-+			type = "out";
-+			continue;
-+		case 1:
-+			type = "in";
-+			continue;
-+		}
-+	}
-+
-+	return scnprintf(buf, size, "(%c%d ep%d%s [%d/%d] q%d p%d)",
-+			speed_char(scratch), scratch & 0x007f,
-+			(scratch >> 8) & 0x000f, type, qh->usecs,
-+			qh->c_usecs, temp, (scratch >> 16) & 0x7ff);
-+}
-+
-+#define DBG_SCHED_LIMIT 64
-+static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
-+{
-+	struct usb_hcd *hcd;
-+	struct fotg210_hcd *fotg210;
-+	unsigned long flags;
-+	union fotg210_shadow p, *seen;
-+	unsigned temp, size, seen_count;
-+	char *next;
-+	unsigned i;
-+	__hc32 tag;
-+
-+	seen = kmalloc_array(DBG_SCHED_LIMIT, sizeof(*seen), GFP_ATOMIC);
-+	if (!seen)
-+		return 0;
-+
-+	seen_count = 0;
-+
-+	hcd = bus_to_hcd(buf->bus);
-+	fotg210 = hcd_to_fotg210(hcd);
-+	next = buf->output_buf;
-+	size = buf->alloc_size;
-+
-+	temp = scnprintf(next, size, "size = %d\n", fotg210->periodic_size);
-+	size -= temp;
-+	next += temp;
-+
-+	/* dump a snapshot of the periodic schedule.
-+	 * iso changes, interrupt usually doesn't.
-+	 */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	for (i = 0; i < fotg210->periodic_size; i++) {
-+		p = fotg210->pshadow[i];
-+		if (likely(!p.ptr))
-+			continue;
-+
-+		tag = Q_NEXT_TYPE(fotg210, fotg210->periodic[i]);
-+
-+		temp = scnprintf(next, size, "%4d: ", i);
-+		size -= temp;
-+		next += temp;
-+
-+		do {
-+			struct fotg210_qh_hw *hw;
-+
-+			switch (hc32_to_cpu(fotg210, tag)) {
-+			case Q_TYPE_QH:
-+				hw = p.qh->hw;
-+				temp = scnprintf(next, size, " qh%d-%04x/%p",
-+						p.qh->period,
-+						hc32_to_cpup(fotg210,
-+							&hw->hw_info2)
-+							/* uframe masks */
-+							& (QH_CMASK | QH_SMASK),
-+						p.qh);
-+				size -= temp;
-+				next += temp;
-+				/* don't repeat what follows this qh */
-+				for (temp = 0; temp < seen_count; temp++) {
-+					if (seen[temp].ptr != p.ptr)
-+						continue;
-+					if (p.qh->qh_next.ptr) {
-+						temp = scnprintf(next, size,
-+								" ...");
-+						size -= temp;
-+						next += temp;
-+					}
-+					break;
-+				}
-+				/* show more info the first time around */
-+				if (temp == seen_count) {
-+					temp = output_buf_tds_dir(next,
-+							fotg210, hw,
-+							p.qh, size);
-+
-+					if (seen_count < DBG_SCHED_LIMIT)
-+						seen[seen_count++].qh = p.qh;
-+				} else
-+					temp = 0;
-+				tag = Q_NEXT_TYPE(fotg210, hw->hw_next);
-+				p = p.qh->qh_next;
-+				break;
-+			case Q_TYPE_FSTN:
-+				temp = scnprintf(next, size,
-+						" fstn-%8x/%p",
-+						p.fstn->hw_prev, p.fstn);
-+				tag = Q_NEXT_TYPE(fotg210, p.fstn->hw_next);
-+				p = p.fstn->fstn_next;
-+				break;
-+			case Q_TYPE_ITD:
-+				temp = scnprintf(next, size,
-+						" itd/%p", p.itd);
-+				tag = Q_NEXT_TYPE(fotg210, p.itd->hw_next);
-+				p = p.itd->itd_next;
-+				break;
-+			}
-+			size -= temp;
-+			next += temp;
-+		} while (p.ptr);
-+
-+		temp = scnprintf(next, size, "\n");
-+		size -= temp;
-+		next += temp;
-+	}
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	kfree(seen);
-+
-+	return buf->alloc_size - size;
-+}
-+#undef DBG_SCHED_LIMIT
-+
-+static const char *rh_state_string(struct fotg210_hcd *fotg210)
-+{
-+	switch (fotg210->rh_state) {
-+	case FOTG210_RH_HALTED:
-+		return "halted";
-+	case FOTG210_RH_SUSPENDED:
-+		return "suspended";
-+	case FOTG210_RH_RUNNING:
-+		return "running";
-+	case FOTG210_RH_STOPPING:
-+		return "stopping";
-+	}
-+	return "?";
-+}
-+
-+static ssize_t fill_registers_buffer(struct debug_buffer *buf)
-+{
-+	struct usb_hcd *hcd;
-+	struct fotg210_hcd *fotg210;
-+	unsigned long flags;
-+	unsigned temp, size, i;
-+	char *next, scratch[80];
-+	static const char fmt[] = "%*s\n";
-+	static const char label[] = "";
-+
-+	hcd = bus_to_hcd(buf->bus);
-+	fotg210 = hcd_to_fotg210(hcd);
-+	next = buf->output_buf;
-+	size = buf->alloc_size;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	if (!HCD_HW_ACCESSIBLE(hcd)) {
-+		size = scnprintf(next, size,
-+				"bus %s, device %s\n"
-+				"%s\n"
-+				"SUSPENDED(no register access)\n",
-+				hcd->self.controller->bus->name,
-+				dev_name(hcd->self.controller),
-+				hcd->product_desc);
-+		goto done;
-+	}
-+
-+	/* Capability Registers */
-+	i = HC_VERSION(fotg210, fotg210_readl(fotg210,
-+			&fotg210->caps->hc_capbase));
-+	temp = scnprintf(next, size,
-+			"bus %s, device %s\n"
-+			"%s\n"
-+			"EHCI %x.%02x, rh state %s\n",
-+			hcd->self.controller->bus->name,
-+			dev_name(hcd->self.controller),
-+			hcd->product_desc,
-+			i >> 8, i & 0x0ff, rh_state_string(fotg210));
-+	size -= temp;
-+	next += temp;
-+
-+	/* FIXME interpret both types of params */
-+	i = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
-+	temp = scnprintf(next, size, "structural params 0x%08x\n", i);
-+	size -= temp;
-+	next += temp;
-+
-+	i = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+	temp = scnprintf(next, size, "capability params 0x%08x\n", i);
-+	size -= temp;
-+	next += temp;
-+
-+	/* Operational Registers */
-+	temp = dbg_status_buf(scratch, sizeof(scratch), label,
-+			fotg210_readl(fotg210, &fotg210->regs->status));
-+	temp = scnprintf(next, size, fmt, temp, scratch);
-+	size -= temp;
-+	next += temp;
-+
-+	temp = dbg_command_buf(scratch, sizeof(scratch), label,
-+			fotg210_readl(fotg210, &fotg210->regs->command));
-+	temp = scnprintf(next, size, fmt, temp, scratch);
-+	size -= temp;
-+	next += temp;
-+
-+	temp = dbg_intr_buf(scratch, sizeof(scratch), label,
-+			fotg210_readl(fotg210, &fotg210->regs->intr_enable));
-+	temp = scnprintf(next, size, fmt, temp, scratch);
-+	size -= temp;
-+	next += temp;
-+
-+	temp = scnprintf(next, size, "uframe %04x\n",
-+			fotg210_read_frame_index(fotg210));
-+	size -= temp;
-+	next += temp;
-+
-+	if (fotg210->async_unlink) {
-+		temp = scnprintf(next, size, "async unlink qh %p\n",
-+				fotg210->async_unlink);
-+		size -= temp;
-+		next += temp;
-+	}
-+
-+#ifdef FOTG210_STATS
-+	temp = scnprintf(next, size,
-+			"irq normal %ld err %ld iaa %ld(lost %ld)\n",
-+			fotg210->stats.normal, fotg210->stats.error,
-+			fotg210->stats.iaa, fotg210->stats.lost_iaa);
-+	size -= temp;
-+	next += temp;
-+
-+	temp = scnprintf(next, size, "complete %ld unlink %ld\n",
-+			fotg210->stats.complete, fotg210->stats.unlink);
-+	size -= temp;
-+	next += temp;
-+#endif
-+
-+done:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+	return buf->alloc_size - size;
-+}
-+
-+static struct debug_buffer
-+*alloc_buffer(struct usb_bus *bus, ssize_t (*fill_func)(struct debug_buffer *))
-+{
-+	struct debug_buffer *buf;
-+
-+	buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
-+
-+	if (buf) {
-+		buf->bus = bus;
-+		buf->fill_func = fill_func;
-+		mutex_init(&buf->mutex);
-+		buf->alloc_size = PAGE_SIZE;
-+	}
-+
-+	return buf;
-+}
-+
-+static int fill_buffer(struct debug_buffer *buf)
-+{
-+	int ret = 0;
-+
-+	if (!buf->output_buf)
-+		buf->output_buf = vmalloc(buf->alloc_size);
-+
-+	if (!buf->output_buf) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	ret = buf->fill_func(buf);
-+
-+	if (ret >= 0) {
-+		buf->count = ret;
-+		ret = 0;
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+static ssize_t debug_output(struct file *file, char __user *user_buf,
-+		size_t len, loff_t *offset)
-+{
-+	struct debug_buffer *buf = file->private_data;
-+	int ret = 0;
-+
-+	mutex_lock(&buf->mutex);
-+	if (buf->count == 0) {
-+		ret = fill_buffer(buf);
-+		if (ret != 0) {
-+			mutex_unlock(&buf->mutex);
-+			goto out;
-+		}
-+	}
-+	mutex_unlock(&buf->mutex);
-+
-+	ret = simple_read_from_buffer(user_buf, len, offset,
-+			buf->output_buf, buf->count);
-+
-+out:
-+	return ret;
-+
-+}
-+
-+static int debug_close(struct inode *inode, struct file *file)
-+{
-+	struct debug_buffer *buf = file->private_data;
-+
-+	if (buf) {
-+		vfree(buf->output_buf);
-+		kfree(buf);
-+	}
-+
-+	return 0;
-+}
-+static int debug_async_open(struct inode *inode, struct file *file)
-+{
-+	file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
-+
-+	return file->private_data ? 0 : -ENOMEM;
-+}
-+
-+static int debug_periodic_open(struct inode *inode, struct file *file)
-+{
-+	struct debug_buffer *buf;
-+
-+	buf = alloc_buffer(inode->i_private, fill_periodic_buffer);
-+	if (!buf)
-+		return -ENOMEM;
-+
-+	buf->alloc_size = (sizeof(void *) == 4 ? 6 : 8)*PAGE_SIZE;
-+	file->private_data = buf;
-+	return 0;
-+}
-+
-+static int debug_registers_open(struct inode *inode, struct file *file)
-+{
-+	file->private_data = alloc_buffer(inode->i_private,
-+			fill_registers_buffer);
-+
-+	return file->private_data ? 0 : -ENOMEM;
-+}
-+
-+static inline void create_debug_files(struct fotg210_hcd *fotg210)
-+{
-+	struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
-+	struct dentry *root;
-+
-+	root = debugfs_create_dir(bus->bus_name, fotg210_debug_root);
-+
-+	debugfs_create_file("async", S_IRUGO, root, bus, &debug_async_fops);
-+	debugfs_create_file("periodic", S_IRUGO, root, bus,
-+			    &debug_periodic_fops);
-+	debugfs_create_file("registers", S_IRUGO, root, bus,
-+			    &debug_registers_fops);
-+}
-+
-+static inline void remove_debug_files(struct fotg210_hcd *fotg210)
-+{
-+	struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
-+
-+	debugfs_lookup_and_remove(bus->bus_name, fotg210_debug_root);
-+}
-+
-+/* handshake - spin reading hc until handshake completes or fails
-+ * @ptr: address of hc register to be read
-+ * @mask: bits to look at in result of read
-+ * @done: value of those bits when handshake succeeds
-+ * @usec: timeout in microseconds
-+ *
-+ * Returns negative errno, or zero on success
-+ *
-+ * Success happens when the "mask" bits have the specified value (hardware
-+ * handshake done).  There are two failure modes:  "usec" have passed (major
-+ * hardware flakeout), or the register reads as all-ones (hardware removed).
-+ *
-+ * That last failure should_only happen in cases like physical cardbus eject
-+ * before driver shutdown. But it also seems to be caused by bugs in cardbus
-+ * bridge shutdown:  shutting down the bridge before the devices using it.
-+ */
-+static int handshake(struct fotg210_hcd *fotg210, void __iomem *ptr,
-+		u32 mask, u32 done, int usec)
-+{
-+	u32 result;
-+	int ret;
-+
-+	ret = readl_poll_timeout_atomic(ptr, result,
-+					((result & mask) == done ||
-+					 result == U32_MAX), 1, usec);
-+	if (result == U32_MAX)		/* card removed */
-+		return -ENODEV;
-+
-+	return ret;
-+}
-+
-+/* Force HC to halt state from unknown (EHCI spec section 2.3).
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static int fotg210_halt(struct fotg210_hcd *fotg210)
-+{
-+	u32 temp;
-+
-+	spin_lock_irq(&fotg210->lock);
-+
-+	/* disable any irqs left enabled by previous code */
-+	fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+
-+	/*
-+	 * This routine gets called during probe before fotg210->command
-+	 * has been initialized, so we can't rely on its value.
-+	 */
-+	fotg210->command &= ~CMD_RUN;
-+	temp = fotg210_readl(fotg210, &fotg210->regs->command);
-+	temp &= ~(CMD_RUN | CMD_IAAD);
-+	fotg210_writel(fotg210, temp, &fotg210->regs->command);
-+
-+	spin_unlock_irq(&fotg210->lock);
-+	synchronize_irq(fotg210_to_hcd(fotg210)->irq);
-+
-+	return handshake(fotg210, &fotg210->regs->status,
-+			STS_HALT, STS_HALT, 16 * 125);
-+}
-+
-+/* Reset a non-running (STS_HALT == 1) controller.
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static int fotg210_reset(struct fotg210_hcd *fotg210)
-+{
-+	int retval;
-+	u32 command = fotg210_readl(fotg210, &fotg210->regs->command);
-+
-+	/* If the EHCI debug controller is active, special care must be
-+	 * taken before and after a host controller reset
-+	 */
-+	if (fotg210->debug && !dbgp_reset_prep(fotg210_to_hcd(fotg210)))
-+		fotg210->debug = NULL;
-+
-+	command |= CMD_RESET;
-+	dbg_cmd(fotg210, "reset", command);
-+	fotg210_writel(fotg210, command, &fotg210->regs->command);
-+	fotg210->rh_state = FOTG210_RH_HALTED;
-+	fotg210->next_statechange = jiffies;
-+	retval = handshake(fotg210, &fotg210->regs->command,
-+			CMD_RESET, 0, 250 * 1000);
-+
-+	if (retval)
-+		return retval;
-+
-+	if (fotg210->debug)
-+		dbgp_external_startup(fotg210_to_hcd(fotg210));
-+
-+	fotg210->port_c_suspend = fotg210->suspended_ports =
-+			fotg210->resuming_ports = 0;
-+	return retval;
-+}
-+
-+/* Idle the controller (turn off the schedules).
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static void fotg210_quiesce(struct fotg210_hcd *fotg210)
-+{
-+	u32 temp;
-+
-+	if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+		return;
-+
-+	/* wait for any schedule enables/disables to take effect */
-+	temp = (fotg210->command << 10) & (STS_ASS | STS_PSS);
-+	handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, temp,
-+			16 * 125);
-+
-+	/* then disable anything that's still active */
-+	spin_lock_irq(&fotg210->lock);
-+	fotg210->command &= ~(CMD_ASE | CMD_PSE);
-+	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+	spin_unlock_irq(&fotg210->lock);
-+
-+	/* hardware can take 16 microframes to turn off ... */
-+	handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, 0,
-+			16 * 125);
-+}
-+
-+static void end_unlink_async(struct fotg210_hcd *fotg210);
-+static void unlink_empty_async(struct fotg210_hcd *fotg210);
-+static void fotg210_work(struct fotg210_hcd *fotg210);
-+static void start_unlink_intr(struct fotg210_hcd *fotg210,
-+			      struct fotg210_qh *qh);
-+static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+/* Set a bit in the USBCMD register */
-+static void fotg210_set_command_bit(struct fotg210_hcd *fotg210, u32 bit)
-+{
-+	fotg210->command |= bit;
-+	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+
-+	/* unblock posted write */
-+	fotg210_readl(fotg210, &fotg210->regs->command);
-+}
-+
-+/* Clear a bit in the USBCMD register */
-+static void fotg210_clear_command_bit(struct fotg210_hcd *fotg210, u32 bit)
-+{
-+	fotg210->command &= ~bit;
-+	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+
-+	/* unblock posted write */
-+	fotg210_readl(fotg210, &fotg210->regs->command);
-+}
-+
-+/* EHCI timer support...  Now using hrtimers.
-+ *
-+ * Lots of different events are triggered from fotg210->hrtimer.  Whenever
-+ * the timer routine runs, it checks each possible event; events that are
-+ * currently enabled and whose expiration time has passed get handled.
-+ * The set of enabled events is stored as a collection of bitflags in
-+ * fotg210->enabled_hrtimer_events, and they are numbered in order of
-+ * increasing delay values (ranging between 1 ms and 100 ms).
-+ *
-+ * Rather than implementing a sorted list or tree of all pending events,
-+ * we keep track only of the lowest-numbered pending event, in
-+ * fotg210->next_hrtimer_event.  Whenever fotg210->hrtimer gets restarted, its
-+ * expiration time is set to the timeout value for this event.
-+ *
-+ * As a result, events might not get handled right away; the actual delay
-+ * could be anywhere up to twice the requested delay.  This doesn't
-+ * matter, because none of the events are especially time-critical.  The
-+ * ones that matter most all have a delay of 1 ms, so they will be
-+ * handled after 2 ms at most, which is okay.  In addition to this, we
-+ * allow for an expiration range of 1 ms.
-+ */
-+
-+/* Delay lengths for the hrtimer event types.
-+ * Keep this list sorted by delay length, in the same order as
-+ * the event types indexed by enum fotg210_hrtimer_event in fotg210.h.
-+ */
-+static unsigned event_delays_ns[] = {
-+	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_ASS */
-+	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_PSS */
-+	1 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_POLL_DEAD */
-+	1125 * NSEC_PER_USEC,	/* FOTG210_HRTIMER_UNLINK_INTR */
-+	2 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_FREE_ITDS */
-+	6 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_ASYNC_UNLINKS */
-+	10 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_IAA_WATCHDOG */
-+	10 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_DISABLE_PERIODIC */
-+	15 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_DISABLE_ASYNC */
-+	100 * NSEC_PER_MSEC,	/* FOTG210_HRTIMER_IO_WATCHDOG */
-+};
-+
-+/* Enable a pending hrtimer event */
-+static void fotg210_enable_event(struct fotg210_hcd *fotg210, unsigned event,
-+		bool resched)
-+{
-+	ktime_t *timeout = &fotg210->hr_timeouts[event];
-+
-+	if (resched)
-+		*timeout = ktime_add(ktime_get(), event_delays_ns[event]);
-+	fotg210->enabled_hrtimer_events |= (1 << event);
-+
-+	/* Track only the lowest-numbered pending event */
-+	if (event < fotg210->next_hrtimer_event) {
-+		fotg210->next_hrtimer_event = event;
-+		hrtimer_start_range_ns(&fotg210->hrtimer, *timeout,
-+				NSEC_PER_MSEC, HRTIMER_MODE_ABS);
-+	}
-+}
-+
-+
-+/* Poll the STS_ASS status bit; see when it agrees with CMD_ASE */
-+static void fotg210_poll_ASS(struct fotg210_hcd *fotg210)
-+{
-+	unsigned actual, want;
-+
-+	/* Don't enable anything if the controller isn't running (e.g., died) */
-+	if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+		return;
-+
-+	want = (fotg210->command & CMD_ASE) ? STS_ASS : 0;
-+	actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_ASS;
-+
-+	if (want != actual) {
-+
-+		/* Poll again later, but give up after about 20 ms */
-+		if (fotg210->ASS_poll_count++ < 20) {
-+			fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_ASS,
-+					true);
-+			return;
-+		}
-+		fotg210_dbg(fotg210, "Waited too long for the async schedule status (%x/%x), giving up\n",
-+				want, actual);
-+	}
-+	fotg210->ASS_poll_count = 0;
-+
-+	/* The status is up-to-date; restart or stop the schedule as needed */
-+	if (want == 0) {	/* Stopped */
-+		if (fotg210->async_count > 0)
-+			fotg210_set_command_bit(fotg210, CMD_ASE);
-+
-+	} else {		/* Running */
-+		if (fotg210->async_count == 0) {
-+
-+			/* Turn off the schedule after a while */
-+			fotg210_enable_event(fotg210,
-+					FOTG210_HRTIMER_DISABLE_ASYNC,
-+					true);
-+		}
-+	}
-+}
-+
-+/* Turn off the async schedule after a brief delay */
-+static void fotg210_disable_ASE(struct fotg210_hcd *fotg210)
-+{
-+	fotg210_clear_command_bit(fotg210, CMD_ASE);
-+}
-+
-+
-+/* Poll the STS_PSS status bit; see when it agrees with CMD_PSE */
-+static void fotg210_poll_PSS(struct fotg210_hcd *fotg210)
-+{
-+	unsigned actual, want;
-+
-+	/* Don't do anything if the controller isn't running (e.g., died) */
-+	if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+		return;
-+
-+	want = (fotg210->command & CMD_PSE) ? STS_PSS : 0;
-+	actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_PSS;
-+
-+	if (want != actual) {
-+
-+		/* Poll again later, but give up after about 20 ms */
-+		if (fotg210->PSS_poll_count++ < 20) {
-+			fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_PSS,
-+					true);
-+			return;
-+		}
-+		fotg210_dbg(fotg210, "Waited too long for the periodic schedule status (%x/%x), giving up\n",
-+				want, actual);
-+	}
-+	fotg210->PSS_poll_count = 0;
-+
-+	/* The status is up-to-date; restart or stop the schedule as needed */
-+	if (want == 0) {	/* Stopped */
-+		if (fotg210->periodic_count > 0)
-+			fotg210_set_command_bit(fotg210, CMD_PSE);
-+
-+	} else {		/* Running */
-+		if (fotg210->periodic_count == 0) {
-+
-+			/* Turn off the schedule after a while */
-+			fotg210_enable_event(fotg210,
-+					FOTG210_HRTIMER_DISABLE_PERIODIC,
-+					true);
-+		}
-+	}
-+}
-+
-+/* Turn off the periodic schedule after a brief delay */
-+static void fotg210_disable_PSE(struct fotg210_hcd *fotg210)
-+{
-+	fotg210_clear_command_bit(fotg210, CMD_PSE);
-+}
-+
-+
-+/* Poll the STS_HALT status bit; see when a dead controller stops */
-+static void fotg210_handle_controller_death(struct fotg210_hcd *fotg210)
-+{
-+	if (!(fotg210_readl(fotg210, &fotg210->regs->status) & STS_HALT)) {
-+
-+		/* Give up after a few milliseconds */
-+		if (fotg210->died_poll_count++ < 5) {
-+			/* Try again later */
-+			fotg210_enable_event(fotg210,
-+					FOTG210_HRTIMER_POLL_DEAD, true);
-+			return;
-+		}
-+		fotg210_warn(fotg210, "Waited too long for the controller to stop, giving up\n");
-+	}
-+
-+	/* Clean up the mess */
-+	fotg210->rh_state = FOTG210_RH_HALTED;
-+	fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+	fotg210_work(fotg210);
-+	end_unlink_async(fotg210);
-+
-+	/* Not in process context, so don't try to reset the controller */
-+}
-+
-+
-+/* Handle unlinked interrupt QHs once they are gone from the hardware */
-+static void fotg210_handle_intr_unlinks(struct fotg210_hcd *fotg210)
-+{
-+	bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
-+
-+	/*
-+	 * Process all the QHs on the intr_unlink list that were added
-+	 * before the current unlink cycle began.  The list is in
-+	 * temporal order, so stop when we reach the first entry in the
-+	 * current cycle.  But if the root hub isn't running then
-+	 * process all the QHs on the list.
-+	 */
-+	fotg210->intr_unlinking = true;
-+	while (fotg210->intr_unlink) {
-+		struct fotg210_qh *qh = fotg210->intr_unlink;
-+
-+		if (!stopped && qh->unlink_cycle == fotg210->intr_unlink_cycle)
-+			break;
-+		fotg210->intr_unlink = qh->unlink_next;
-+		qh->unlink_next = NULL;
-+		end_unlink_intr(fotg210, qh);
-+	}
-+
-+	/* Handle remaining entries later */
-+	if (fotg210->intr_unlink) {
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-+				true);
-+		++fotg210->intr_unlink_cycle;
-+	}
-+	fotg210->intr_unlinking = false;
-+}
-+
-+
-+/* Start another free-iTDs/siTDs cycle */
-+static void start_free_itds(struct fotg210_hcd *fotg210)
-+{
-+	if (!(fotg210->enabled_hrtimer_events &
-+			BIT(FOTG210_HRTIMER_FREE_ITDS))) {
-+		fotg210->last_itd_to_free = list_entry(
-+				fotg210->cached_itd_list.prev,
-+				struct fotg210_itd, itd_list);
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_FREE_ITDS, true);
-+	}
-+}
-+
-+/* Wait for controller to stop using old iTDs and siTDs */
-+static void end_free_itds(struct fotg210_hcd *fotg210)
-+{
-+	struct fotg210_itd *itd, *n;
-+
-+	if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+		fotg210->last_itd_to_free = NULL;
-+
-+	list_for_each_entry_safe(itd, n, &fotg210->cached_itd_list, itd_list) {
-+		list_del(&itd->itd_list);
-+		dma_pool_free(fotg210->itd_pool, itd, itd->itd_dma);
-+		if (itd == fotg210->last_itd_to_free)
-+			break;
-+	}
-+
-+	if (!list_empty(&fotg210->cached_itd_list))
-+		start_free_itds(fotg210);
-+}
-+
-+
-+/* Handle lost (or very late) IAA interrupts */
-+static void fotg210_iaa_watchdog(struct fotg210_hcd *fotg210)
-+{
-+	if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+		return;
-+
-+	/*
-+	 * Lost IAA irqs wedge things badly; seen first with a vt8235.
-+	 * So we need this watchdog, but must protect it against both
-+	 * (a) SMP races against real IAA firing and retriggering, and
-+	 * (b) clean HC shutdown, when IAA watchdog was pending.
-+	 */
-+	if (fotg210->async_iaa) {
-+		u32 cmd, status;
-+
-+		/* If we get here, IAA is *REALLY* late.  It's barely
-+		 * conceivable that the system is so busy that CMD_IAAD
-+		 * is still legitimately set, so let's be sure it's
-+		 * clear before we read STS_IAA.  (The HC should clear
-+		 * CMD_IAAD when it sets STS_IAA.)
-+		 */
-+		cmd = fotg210_readl(fotg210, &fotg210->regs->command);
-+
-+		/*
-+		 * If IAA is set here it either legitimately triggered
-+		 * after the watchdog timer expired (_way_ late, so we'll
-+		 * still count it as lost) ... or a silicon erratum:
-+		 * - VIA seems to set IAA without triggering the IRQ;
-+		 * - IAAD potentially cleared without setting IAA.
-+		 */
-+		status = fotg210_readl(fotg210, &fotg210->regs->status);
-+		if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
-+			INCR(fotg210->stats.lost_iaa);
-+			fotg210_writel(fotg210, STS_IAA,
-+					&fotg210->regs->status);
-+		}
-+
-+		fotg210_dbg(fotg210, "IAA watchdog: status %x cmd %x\n",
-+				status, cmd);
-+		end_unlink_async(fotg210);
-+	}
-+}
-+
-+
-+/* Enable the I/O watchdog, if appropriate */
-+static void turn_on_io_watchdog(struct fotg210_hcd *fotg210)
-+{
-+	/* Not needed if the controller isn't running or it's already enabled */
-+	if (fotg210->rh_state != FOTG210_RH_RUNNING ||
-+			(fotg210->enabled_hrtimer_events &
-+			BIT(FOTG210_HRTIMER_IO_WATCHDOG)))
-+		return;
-+
-+	/*
-+	 * Isochronous transfers always need the watchdog.
-+	 * For other sorts we use it only if the flag is set.
-+	 */
-+	if (fotg210->isoc_count > 0 || (fotg210->need_io_watchdog &&
-+			fotg210->async_count + fotg210->intr_count > 0))
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_IO_WATCHDOG,
-+				true);
-+}
-+
-+
-+/* Handler functions for the hrtimer event types.
-+ * Keep this array in the same order as the event types indexed by
-+ * enum fotg210_hrtimer_event in fotg210.h.
-+ */
-+static void (*event_handlers[])(struct fotg210_hcd *) = {
-+	fotg210_poll_ASS,			/* FOTG210_HRTIMER_POLL_ASS */
-+	fotg210_poll_PSS,			/* FOTG210_HRTIMER_POLL_PSS */
-+	fotg210_handle_controller_death,	/* FOTG210_HRTIMER_POLL_DEAD */
-+	fotg210_handle_intr_unlinks,	/* FOTG210_HRTIMER_UNLINK_INTR */
-+	end_free_itds,			/* FOTG210_HRTIMER_FREE_ITDS */
-+	unlink_empty_async,		/* FOTG210_HRTIMER_ASYNC_UNLINKS */
-+	fotg210_iaa_watchdog,		/* FOTG210_HRTIMER_IAA_WATCHDOG */
-+	fotg210_disable_PSE,		/* FOTG210_HRTIMER_DISABLE_PERIODIC */
-+	fotg210_disable_ASE,		/* FOTG210_HRTIMER_DISABLE_ASYNC */
-+	fotg210_work,			/* FOTG210_HRTIMER_IO_WATCHDOG */
-+};
-+
-+static enum hrtimer_restart fotg210_hrtimer_func(struct hrtimer *t)
-+{
-+	struct fotg210_hcd *fotg210 =
-+			container_of(t, struct fotg210_hcd, hrtimer);
-+	ktime_t now;
-+	unsigned long events;
-+	unsigned long flags;
-+	unsigned e;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	events = fotg210->enabled_hrtimer_events;
-+	fotg210->enabled_hrtimer_events = 0;
-+	fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
-+
-+	/*
-+	 * Check each pending event.  If its time has expired, handle
-+	 * the event; otherwise re-enable it.
-+	 */
-+	now = ktime_get();
-+	for_each_set_bit(e, &events, FOTG210_HRTIMER_NUM_EVENTS) {
-+		if (ktime_compare(now, fotg210->hr_timeouts[e]) >= 0)
-+			event_handlers[e](fotg210);
-+		else
-+			fotg210_enable_event(fotg210, e, false);
-+	}
-+
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return HRTIMER_NORESTART;
-+}
-+
-+#define fotg210_bus_suspend NULL
-+#define fotg210_bus_resume NULL
-+
-+static int check_reset_complete(struct fotg210_hcd *fotg210, int index,
-+		u32 __iomem *status_reg, int port_status)
-+{
-+	if (!(port_status & PORT_CONNECT))
-+		return port_status;
-+
-+	/* if reset finished and it's still not enabled -- handoff */
-+	if (!(port_status & PORT_PE))
-+		/* with integrated TT, there's nobody to hand it to! */
-+		fotg210_dbg(fotg210, "Failed to enable port %d on root hub TT\n",
-+				index + 1);
-+	else
-+		fotg210_dbg(fotg210, "port %d reset complete, port enabled\n",
-+				index + 1);
-+
-+	return port_status;
-+}
-+
-+
-+/* build "status change" packet (one or two bytes) from HC registers */
-+
-+static int fotg210_hub_status_data(struct usb_hcd *hcd, char *buf)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	u32 temp, status;
-+	u32 mask;
-+	int retval = 1;
-+	unsigned long flags;
-+
-+	/* init status to no-changes */
-+	buf[0] = 0;
-+
-+	/* Inform the core about resumes-in-progress by returning
-+	 * a non-zero value even if there are no status changes.
-+	 */
-+	status = fotg210->resuming_ports;
-+
-+	mask = PORT_CSC | PORT_PEC;
-+	/* PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND */
-+
-+	/* no hub change reports (bit 0) for now (power, ...) */
-+
-+	/* port N changes (bit N)? */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	temp = fotg210_readl(fotg210, &fotg210->regs->port_status);
-+
-+	/*
-+	 * Return status information even for ports with OWNER set.
-+	 * Otherwise hub_wq wouldn't see the disconnect event when a
-+	 * high-speed device is switched over to the companion
-+	 * controller by the user.
-+	 */
-+
-+	if ((temp & mask) != 0 || test_bit(0, &fotg210->port_c_suspend) ||
-+			(fotg210->reset_done[0] &&
-+			time_after_eq(jiffies, fotg210->reset_done[0]))) {
-+		buf[0] |= 1 << 1;
-+		status = STS_PCD;
-+	}
-+	/* FIXME autosuspend idle root hubs */
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return status ? retval : 0;
-+}
-+
-+static void fotg210_hub_descriptor(struct fotg210_hcd *fotg210,
-+		struct usb_hub_descriptor *desc)
-+{
-+	int ports = HCS_N_PORTS(fotg210->hcs_params);
-+	u16 temp;
-+
-+	desc->bDescriptorType = USB_DT_HUB;
-+	desc->bPwrOn2PwrGood = 10;	/* fotg210 1.0, 2.3.9 says 20ms max */
-+	desc->bHubContrCurrent = 0;
-+
-+	desc->bNbrPorts = ports;
-+	temp = 1 + (ports / 8);
-+	desc->bDescLength = 7 + 2 * temp;
-+
-+	/* two bitmaps:  ports removable, and usb 1.0 legacy PortPwrCtrlMask */
-+	memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
-+	memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
-+
-+	temp = HUB_CHAR_INDV_PORT_OCPM;	/* per-port overcurrent reporting */
-+	temp |= HUB_CHAR_NO_LPSM;	/* no power switching */
-+	desc->wHubCharacteristics = cpu_to_le16(temp);
-+}
-+
-+static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
-+		u16 wIndex, char *buf, u16 wLength)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	int ports = HCS_N_PORTS(fotg210->hcs_params);
-+	u32 __iomem *status_reg = &fotg210->regs->port_status;
-+	u32 temp, temp1, status;
-+	unsigned long flags;
-+	int retval = 0;
-+	unsigned selector;
-+
-+	/*
-+	 * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
-+	 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
-+	 * (track current state ourselves) ... blink for diagnostics,
-+	 * power, "this is the one", etc.  EHCI spec supports this.
-+	 */
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	switch (typeReq) {
-+	case ClearHubFeature:
-+		switch (wValue) {
-+		case C_HUB_LOCAL_POWER:
-+		case C_HUB_OVER_CURRENT:
-+			/* no hub-wide feature/status flags */
-+			break;
-+		default:
-+			goto error;
-+		}
-+		break;
-+	case ClearPortFeature:
-+		if (!wIndex || wIndex > ports)
-+			goto error;
-+		wIndex--;
-+		temp = fotg210_readl(fotg210, status_reg);
-+		temp &= ~PORT_RWC_BITS;
-+
-+		/*
-+		 * Even if OWNER is set, so the port is owned by the
-+		 * companion controller, hub_wq needs to be able to clear
-+		 * the port-change status bits (especially
-+		 * USB_PORT_STAT_C_CONNECTION).
-+		 */
-+
-+		switch (wValue) {
-+		case USB_PORT_FEAT_ENABLE:
-+			fotg210_writel(fotg210, temp & ~PORT_PE, status_reg);
-+			break;
-+		case USB_PORT_FEAT_C_ENABLE:
-+			fotg210_writel(fotg210, temp | PORT_PEC, status_reg);
-+			break;
-+		case USB_PORT_FEAT_SUSPEND:
-+			if (temp & PORT_RESET)
-+				goto error;
-+			if (!(temp & PORT_SUSPEND))
-+				break;
-+			if ((temp & PORT_PE) == 0)
-+				goto error;
-+
-+			/* resume signaling for 20 msec */
-+			fotg210_writel(fotg210, temp | PORT_RESUME, status_reg);
-+			fotg210->reset_done[wIndex] = jiffies
-+					+ msecs_to_jiffies(USB_RESUME_TIMEOUT);
-+			break;
-+		case USB_PORT_FEAT_C_SUSPEND:
-+			clear_bit(wIndex, &fotg210->port_c_suspend);
-+			break;
-+		case USB_PORT_FEAT_C_CONNECTION:
-+			fotg210_writel(fotg210, temp | PORT_CSC, status_reg);
-+			break;
-+		case USB_PORT_FEAT_C_OVER_CURRENT:
-+			fotg210_writel(fotg210, temp | OTGISR_OVC,
-+					&fotg210->regs->otgisr);
-+			break;
-+		case USB_PORT_FEAT_C_RESET:
-+			/* GetPortStatus clears reset */
-+			break;
-+		default:
-+			goto error;
-+		}
-+		fotg210_readl(fotg210, &fotg210->regs->command);
-+		break;
-+	case GetHubDescriptor:
-+		fotg210_hub_descriptor(fotg210, (struct usb_hub_descriptor *)
-+				buf);
-+		break;
-+	case GetHubStatus:
-+		/* no hub-wide feature/status flags */
-+		memset(buf, 0, 4);
-+		/*cpu_to_le32s ((u32 *) buf); */
-+		break;
-+	case GetPortStatus:
-+		if (!wIndex || wIndex > ports)
-+			goto error;
-+		wIndex--;
-+		status = 0;
-+		temp = fotg210_readl(fotg210, status_reg);
-+
-+		/* wPortChange bits */
-+		if (temp & PORT_CSC)
-+			status |= USB_PORT_STAT_C_CONNECTION << 16;
-+		if (temp & PORT_PEC)
-+			status |= USB_PORT_STAT_C_ENABLE << 16;
-+
-+		temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-+		if (temp1 & OTGISR_OVC)
-+			status |= USB_PORT_STAT_C_OVERCURRENT << 16;
-+
-+		/* whoever resumes must GetPortStatus to complete it!! */
-+		if (temp & PORT_RESUME) {
-+
-+			/* Remote Wakeup received? */
-+			if (!fotg210->reset_done[wIndex]) {
-+				/* resume signaling for 20 msec */
-+				fotg210->reset_done[wIndex] = jiffies
-+						+ msecs_to_jiffies(20);
-+				/* check the port again */
-+				mod_timer(&fotg210_to_hcd(fotg210)->rh_timer,
-+						fotg210->reset_done[wIndex]);
-+			}
-+
-+			/* resume completed? */
-+			else if (time_after_eq(jiffies,
-+					fotg210->reset_done[wIndex])) {
-+				clear_bit(wIndex, &fotg210->suspended_ports);
-+				set_bit(wIndex, &fotg210->port_c_suspend);
-+				fotg210->reset_done[wIndex] = 0;
-+
-+				/* stop resume signaling */
-+				temp = fotg210_readl(fotg210, status_reg);
-+				fotg210_writel(fotg210, temp &
-+						~(PORT_RWC_BITS | PORT_RESUME),
-+						status_reg);
-+				clear_bit(wIndex, &fotg210->resuming_ports);
-+				retval = handshake(fotg210, status_reg,
-+						PORT_RESUME, 0, 2000);/* 2ms */
-+				if (retval != 0) {
-+					fotg210_err(fotg210,
-+							"port %d resume error %d\n",
-+							wIndex + 1, retval);
-+					goto error;
-+				}
-+				temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
-+			}
-+		}
-+
-+		/* whoever resets must GetPortStatus to complete it!! */
-+		if ((temp & PORT_RESET) && time_after_eq(jiffies,
-+				fotg210->reset_done[wIndex])) {
-+			status |= USB_PORT_STAT_C_RESET << 16;
-+			fotg210->reset_done[wIndex] = 0;
-+			clear_bit(wIndex, &fotg210->resuming_ports);
-+
-+			/* force reset to complete */
-+			fotg210_writel(fotg210,
-+					temp & ~(PORT_RWC_BITS | PORT_RESET),
-+					status_reg);
-+			/* REVISIT:  some hardware needs 550+ usec to clear
-+			 * this bit; seems too long to spin routinely...
-+			 */
-+			retval = handshake(fotg210, status_reg,
-+					PORT_RESET, 0, 1000);
-+			if (retval != 0) {
-+				fotg210_err(fotg210, "port %d reset error %d\n",
-+						wIndex + 1, retval);
-+				goto error;
-+			}
-+
-+			/* see what we found out */
-+			temp = check_reset_complete(fotg210, wIndex, status_reg,
-+					fotg210_readl(fotg210, status_reg));
-+
-+			/* restart schedule */
-+			fotg210->command |= CMD_RUN;
-+			fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+		}
-+
-+		if (!(temp & (PORT_RESUME|PORT_RESET))) {
-+			fotg210->reset_done[wIndex] = 0;
-+			clear_bit(wIndex, &fotg210->resuming_ports);
-+		}
-+
-+		/* transfer dedicated ports to the companion hc */
-+		if ((temp & PORT_CONNECT) &&
-+				test_bit(wIndex, &fotg210->companion_ports)) {
-+			temp &= ~PORT_RWC_BITS;
-+			fotg210_writel(fotg210, temp, status_reg);
-+			fotg210_dbg(fotg210, "port %d --> companion\n",
-+					wIndex + 1);
-+			temp = fotg210_readl(fotg210, status_reg);
-+		}
-+
-+		/*
-+		 * Even if OWNER is set, there's no harm letting hub_wq
-+		 * see the wPortStatus values (they should all be 0 except
-+		 * for PORT_POWER anyway).
-+		 */
-+
-+		if (temp & PORT_CONNECT) {
-+			status |= USB_PORT_STAT_CONNECTION;
-+			status |= fotg210_port_speed(fotg210, temp);
-+		}
-+		if (temp & PORT_PE)
-+			status |= USB_PORT_STAT_ENABLE;
-+
-+		/* maybe the port was unsuspended without our knowledge */
-+		if (temp & (PORT_SUSPEND|PORT_RESUME)) {
-+			status |= USB_PORT_STAT_SUSPEND;
-+		} else if (test_bit(wIndex, &fotg210->suspended_ports)) {
-+			clear_bit(wIndex, &fotg210->suspended_ports);
-+			clear_bit(wIndex, &fotg210->resuming_ports);
-+			fotg210->reset_done[wIndex] = 0;
-+			if (temp & PORT_PE)
-+				set_bit(wIndex, &fotg210->port_c_suspend);
-+		}
-+
-+		temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-+		if (temp1 & OTGISR_OVC)
-+			status |= USB_PORT_STAT_OVERCURRENT;
-+		if (temp & PORT_RESET)
-+			status |= USB_PORT_STAT_RESET;
-+		if (test_bit(wIndex, &fotg210->port_c_suspend))
-+			status |= USB_PORT_STAT_C_SUSPEND << 16;
-+
-+		if (status & ~0xffff)	/* only if wPortChange is interesting */
-+			dbg_port(fotg210, "GetStatus", wIndex + 1, temp);
-+		put_unaligned_le32(status, buf);
-+		break;
-+	case SetHubFeature:
-+		switch (wValue) {
-+		case C_HUB_LOCAL_POWER:
-+		case C_HUB_OVER_CURRENT:
-+			/* no hub-wide feature/status flags */
-+			break;
-+		default:
-+			goto error;
-+		}
-+		break;
-+	case SetPortFeature:
-+		selector = wIndex >> 8;
-+		wIndex &= 0xff;
-+
-+		if (!wIndex || wIndex > ports)
-+			goto error;
-+		wIndex--;
-+		temp = fotg210_readl(fotg210, status_reg);
-+		temp &= ~PORT_RWC_BITS;
-+		switch (wValue) {
-+		case USB_PORT_FEAT_SUSPEND:
-+			if ((temp & PORT_PE) == 0
-+					|| (temp & PORT_RESET) != 0)
-+				goto error;
-+
-+			/* After above check the port must be connected.
-+			 * Set appropriate bit thus could put phy into low power
-+			 * mode if we have hostpc feature
-+			 */
-+			fotg210_writel(fotg210, temp | PORT_SUSPEND,
-+					status_reg);
-+			set_bit(wIndex, &fotg210->suspended_ports);
-+			break;
-+		case USB_PORT_FEAT_RESET:
-+			if (temp & PORT_RESUME)
-+				goto error;
-+			/* line status bits may report this as low speed,
-+			 * which can be fine if this root hub has a
-+			 * transaction translator built in.
-+			 */
-+			fotg210_dbg(fotg210, "port %d reset\n", wIndex + 1);
-+			temp |= PORT_RESET;
-+			temp &= ~PORT_PE;
-+
-+			/*
-+			 * caller must wait, then call GetPortStatus
-+			 * usb 2.0 spec says 50 ms resets on root
-+			 */
-+			fotg210->reset_done[wIndex] = jiffies
-+					+ msecs_to_jiffies(50);
-+			fotg210_writel(fotg210, temp, status_reg);
-+			break;
-+
-+		/* For downstream facing ports (these):  one hub port is put
-+		 * into test mode according to USB2 11.24.2.13, then the hub
-+		 * must be reset (which for root hub now means rmmod+modprobe,
-+		 * or else system reboot).  See EHCI 2.3.9 and 4.14 for info
-+		 * about the EHCI-specific stuff.
-+		 */
-+		case USB_PORT_FEAT_TEST:
-+			if (!selector || selector > 5)
-+				goto error;
-+			spin_unlock_irqrestore(&fotg210->lock, flags);
-+			fotg210_quiesce(fotg210);
-+			spin_lock_irqsave(&fotg210->lock, flags);
-+
-+			/* Put all enabled ports into suspend */
-+			temp = fotg210_readl(fotg210, status_reg) &
-+				~PORT_RWC_BITS;
-+			if (temp & PORT_PE)
-+				fotg210_writel(fotg210, temp | PORT_SUSPEND,
-+						status_reg);
-+
-+			spin_unlock_irqrestore(&fotg210->lock, flags);
-+			fotg210_halt(fotg210);
-+			spin_lock_irqsave(&fotg210->lock, flags);
-+
-+			temp = fotg210_readl(fotg210, status_reg);
-+			temp |= selector << 16;
-+			fotg210_writel(fotg210, temp, status_reg);
-+			break;
-+
-+		default:
-+			goto error;
-+		}
-+		fotg210_readl(fotg210, &fotg210->regs->command);
-+		break;
-+
-+	default:
-+error:
-+		/* "stall" on error */
-+		retval = -EPIPE;
-+	}
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return retval;
-+}
-+
-+static void __maybe_unused fotg210_relinquish_port(struct usb_hcd *hcd,
-+		int portnum)
-+{
-+	return;
-+}
-+
-+static int __maybe_unused fotg210_port_handed_over(struct usb_hcd *hcd,
-+		int portnum)
-+{
-+	return 0;
-+}
-+
-+/* There's basically three types of memory:
-+ *	- data used only by the HCD ... kmalloc is fine
-+ *	- async and periodic schedules, shared by HC and HCD ... these
-+ *	  need to use dma_pool or dma_alloc_coherent
-+ *	- driver buffers, read/written by HC ... single shot DMA mapped
-+ *
-+ * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
-+ * No memory seen by this driver is pageable.
-+ */
-+
-+/* Allocate the key transfer structures from the previously allocated pool */
-+static inline void fotg210_qtd_init(struct fotg210_hcd *fotg210,
-+		struct fotg210_qtd *qtd, dma_addr_t dma)
-+{
-+	memset(qtd, 0, sizeof(*qtd));
-+	qtd->qtd_dma = dma;
-+	qtd->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-+	qtd->hw_next = FOTG210_LIST_END(fotg210);
-+	qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
-+	INIT_LIST_HEAD(&qtd->qtd_list);
-+}
-+
-+static struct fotg210_qtd *fotg210_qtd_alloc(struct fotg210_hcd *fotg210,
-+		gfp_t flags)
-+{
-+	struct fotg210_qtd *qtd;
-+	dma_addr_t dma;
-+
-+	qtd = dma_pool_alloc(fotg210->qtd_pool, flags, &dma);
-+	if (qtd != NULL)
-+		fotg210_qtd_init(fotg210, qtd, dma);
-+
-+	return qtd;
-+}
-+
-+static inline void fotg210_qtd_free(struct fotg210_hcd *fotg210,
-+		struct fotg210_qtd *qtd)
-+{
-+	dma_pool_free(fotg210->qtd_pool, qtd, qtd->qtd_dma);
-+}
-+
-+
-+static void qh_destroy(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	/* clean qtds first, and know this is not linked */
-+	if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
-+		fotg210_dbg(fotg210, "unused qh not empty!\n");
-+		BUG();
-+	}
-+	if (qh->dummy)
-+		fotg210_qtd_free(fotg210, qh->dummy);
-+	dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
-+	kfree(qh);
-+}
-+
-+static struct fotg210_qh *fotg210_qh_alloc(struct fotg210_hcd *fotg210,
-+		gfp_t flags)
-+{
-+	struct fotg210_qh *qh;
-+	dma_addr_t dma;
-+
-+	qh = kzalloc(sizeof(*qh), GFP_ATOMIC);
-+	if (!qh)
-+		goto done;
-+	qh->hw = (struct fotg210_qh_hw *)
-+		dma_pool_zalloc(fotg210->qh_pool, flags, &dma);
-+	if (!qh->hw)
-+		goto fail;
-+	qh->qh_dma = dma;
-+	INIT_LIST_HEAD(&qh->qtd_list);
-+
-+	/* dummy td enables safe urb queuing */
-+	qh->dummy = fotg210_qtd_alloc(fotg210, flags);
-+	if (qh->dummy == NULL) {
-+		fotg210_dbg(fotg210, "no dummy td\n");
-+		goto fail1;
-+	}
-+done:
-+	return qh;
-+fail1:
-+	dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
-+fail:
-+	kfree(qh);
-+	return NULL;
-+}
-+
-+/* The queue heads and transfer descriptors are managed from pools tied
-+ * to each of the "per device" structures.
-+ * This is the initialisation and cleanup code.
-+ */
-+
-+static void fotg210_mem_cleanup(struct fotg210_hcd *fotg210)
-+{
-+	if (fotg210->async)
-+		qh_destroy(fotg210, fotg210->async);
-+	fotg210->async = NULL;
-+
-+	if (fotg210->dummy)
-+		qh_destroy(fotg210, fotg210->dummy);
-+	fotg210->dummy = NULL;
-+
-+	/* DMA consistent memory and pools */
-+	dma_pool_destroy(fotg210->qtd_pool);
-+	fotg210->qtd_pool = NULL;
-+
-+	dma_pool_destroy(fotg210->qh_pool);
-+	fotg210->qh_pool = NULL;
-+
-+	dma_pool_destroy(fotg210->itd_pool);
-+	fotg210->itd_pool = NULL;
-+
-+	if (fotg210->periodic)
-+		dma_free_coherent(fotg210_to_hcd(fotg210)->self.controller,
-+				fotg210->periodic_size * sizeof(u32),
-+				fotg210->periodic, fotg210->periodic_dma);
-+	fotg210->periodic = NULL;
-+
-+	/* shadow periodic table */
-+	kfree(fotg210->pshadow);
-+	fotg210->pshadow = NULL;
-+}
-+
-+/* remember to add cleanup code (above) if you add anything here */
-+static int fotg210_mem_init(struct fotg210_hcd *fotg210, gfp_t flags)
-+{
-+	int i;
-+
-+	/* QTDs for control/bulk/intr transfers */
-+	fotg210->qtd_pool = dma_pool_create("fotg210_qtd",
-+			fotg210_to_hcd(fotg210)->self.controller,
-+			sizeof(struct fotg210_qtd),
-+			32 /* byte alignment (for hw parts) */,
-+			4096 /* can't cross 4K */);
-+	if (!fotg210->qtd_pool)
-+		goto fail;
-+
-+	/* QHs for control/bulk/intr transfers */
-+	fotg210->qh_pool = dma_pool_create("fotg210_qh",
-+			fotg210_to_hcd(fotg210)->self.controller,
-+			sizeof(struct fotg210_qh_hw),
-+			32 /* byte alignment (for hw parts) */,
-+			4096 /* can't cross 4K */);
-+	if (!fotg210->qh_pool)
-+		goto fail;
-+
-+	fotg210->async = fotg210_qh_alloc(fotg210, flags);
-+	if (!fotg210->async)
-+		goto fail;
-+
-+	/* ITD for high speed ISO transfers */
-+	fotg210->itd_pool = dma_pool_create("fotg210_itd",
-+			fotg210_to_hcd(fotg210)->self.controller,
-+			sizeof(struct fotg210_itd),
-+			64 /* byte alignment (for hw parts) */,
-+			4096 /* can't cross 4K */);
-+	if (!fotg210->itd_pool)
-+		goto fail;
-+
-+	/* Hardware periodic table */
-+	fotg210->periodic =
-+		dma_alloc_coherent(fotg210_to_hcd(fotg210)->self.controller,
-+				fotg210->periodic_size * sizeof(__le32),
-+				&fotg210->periodic_dma, 0);
-+	if (fotg210->periodic == NULL)
-+		goto fail;
-+
-+	for (i = 0; i < fotg210->periodic_size; i++)
-+		fotg210->periodic[i] = FOTG210_LIST_END(fotg210);
-+
-+	/* software shadow of hardware table */
-+	fotg210->pshadow = kcalloc(fotg210->periodic_size, sizeof(void *),
-+			flags);
-+	if (fotg210->pshadow != NULL)
-+		return 0;
-+
-+fail:
-+	fotg210_dbg(fotg210, "couldn't init memory\n");
-+	fotg210_mem_cleanup(fotg210);
-+	return -ENOMEM;
-+}
-+/* EHCI hardware queue manipulation ... the core.  QH/QTD manipulation.
-+ *
-+ * Control, bulk, and interrupt traffic all use "qh" lists.  They list "qtd"
-+ * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
-+ * buffers needed for the larger number).  We use one QH per endpoint, queue
-+ * multiple urbs (all three types) per endpoint.  URBs may need several qtds.
-+ *
-+ * ISO traffic uses "ISO TD" (itd) records, and (along with
-+ * interrupts) needs careful scheduling.  Performance improvements can be
-+ * an ongoing challenge.  That's in "ehci-sched.c".
-+ *
-+ * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
-+ * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
-+ * (b) special fields in qh entries or (c) split iso entries.  TTs will
-+ * buffer low/full speed data so the host collects it at high speed.
-+ */
-+
-+/* fill a qtd, returning how much of the buffer we were able to queue up */
-+static int qtd_fill(struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd,
-+		dma_addr_t buf, size_t len, int token, int maxpacket)
-+{
-+	int i, count;
-+	u64 addr = buf;
-+
-+	/* one buffer entry per 4K ... first might be short or unaligned */
-+	qtd->hw_buf[0] = cpu_to_hc32(fotg210, (u32)addr);
-+	qtd->hw_buf_hi[0] = cpu_to_hc32(fotg210, (u32)(addr >> 32));
-+	count = 0x1000 - (buf & 0x0fff);	/* rest of that page */
-+	if (likely(len < count))		/* ... iff needed */
-+		count = len;
-+	else {
-+		buf +=  0x1000;
-+		buf &= ~0x0fff;
-+
-+		/* per-qtd limit: from 16K to 20K (best alignment) */
-+		for (i = 1; count < len && i < 5; i++) {
-+			addr = buf;
-+			qtd->hw_buf[i] = cpu_to_hc32(fotg210, (u32)addr);
-+			qtd->hw_buf_hi[i] = cpu_to_hc32(fotg210,
-+					(u32)(addr >> 32));
-+			buf += 0x1000;
-+			if ((count + 0x1000) < len)
-+				count += 0x1000;
-+			else
-+				count = len;
-+		}
-+
-+		/* short packets may only terminate transfers */
-+		if (count != len)
-+			count -= (count % maxpacket);
-+	}
-+	qtd->hw_token = cpu_to_hc32(fotg210, (count << 16) | token);
-+	qtd->length = count;
-+
-+	return count;
-+}
-+
-+static inline void qh_update(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh, struct fotg210_qtd *qtd)
-+{
-+	struct fotg210_qh_hw *hw = qh->hw;
-+
-+	/* writes to an active overlay are unsafe */
-+	BUG_ON(qh->qh_state != QH_STATE_IDLE);
-+
-+	hw->hw_qtd_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+	hw->hw_alt_next = FOTG210_LIST_END(fotg210);
-+
-+	/* Except for control endpoints, we make hardware maintain data
-+	 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
-+	 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
-+	 * ever clear it.
-+	 */
-+	if (!(hw->hw_info1 & cpu_to_hc32(fotg210, QH_TOGGLE_CTL))) {
-+		unsigned is_out, epnum;
-+
-+		is_out = qh->is_out;
-+		epnum = (hc32_to_cpup(fotg210, &hw->hw_info1) >> 8) & 0x0f;
-+		if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
-+			hw->hw_token &= ~cpu_to_hc32(fotg210, QTD_TOGGLE);
-+			usb_settoggle(qh->dev, epnum, is_out, 1);
-+		}
-+	}
-+
-+	hw->hw_token &= cpu_to_hc32(fotg210, QTD_TOGGLE | QTD_STS_PING);
-+}
-+
-+/* if it weren't for a common silicon quirk (writing the dummy into the qh
-+ * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
-+ * recovery (including urb dequeue) would need software changes to a QH...
-+ */
-+static void qh_refresh(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	struct fotg210_qtd *qtd;
-+
-+	if (list_empty(&qh->qtd_list))
-+		qtd = qh->dummy;
-+	else {
-+		qtd = list_entry(qh->qtd_list.next,
-+				struct fotg210_qtd, qtd_list);
-+		/*
-+		 * first qtd may already be partially processed.
-+		 * If we come here during unlink, the QH overlay region
-+		 * might have reference to the just unlinked qtd. The
-+		 * qtd is updated in qh_completions(). Update the QH
-+		 * overlay here.
-+		 */
-+		if (cpu_to_hc32(fotg210, qtd->qtd_dma) == qh->hw->hw_current) {
-+			qh->hw->hw_qtd_next = qtd->hw_next;
-+			qtd = NULL;
-+		}
-+	}
-+
-+	if (qtd)
-+		qh_update(fotg210, qh, qtd);
-+}
-+
-+static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+static void fotg210_clear_tt_buffer_complete(struct usb_hcd *hcd,
-+		struct usb_host_endpoint *ep)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	struct fotg210_qh *qh = ep->hcpriv;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	qh->clearing_tt = 0;
-+	if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list)
-+			&& fotg210->rh_state == FOTG210_RH_RUNNING)
-+		qh_link_async(fotg210, qh);
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static void fotg210_clear_tt_buffer(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh, struct urb *urb, u32 token)
-+{
-+
-+	/* If an async split transaction gets an error or is unlinked,
-+	 * the TT buffer may be left in an indeterminate state.  We
-+	 * have to clear the TT buffer.
-+	 *
-+	 * Note: this routine is never called for Isochronous transfers.
-+	 */
-+	if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) {
-+		struct usb_device *tt = urb->dev->tt->hub;
-+
-+		dev_dbg(&tt->dev,
-+				"clear tt buffer port %d, a%d ep%d t%08x\n",
-+				urb->dev->ttport, urb->dev->devnum,
-+				usb_pipeendpoint(urb->pipe), token);
-+
-+		if (urb->dev->tt->hub !=
-+				fotg210_to_hcd(fotg210)->self.root_hub) {
-+			if (usb_hub_clear_tt_buffer(urb) == 0)
-+				qh->clearing_tt = 1;
-+		}
-+	}
-+}
-+
-+static int qtd_copy_status(struct fotg210_hcd *fotg210, struct urb *urb,
-+		size_t length, u32 token)
-+{
-+	int status = -EINPROGRESS;
-+
-+	/* count IN/OUT bytes, not SETUP (even short packets) */
-+	if (likely(QTD_PID(token) != 2))
-+		urb->actual_length += length - QTD_LENGTH(token);
-+
-+	/* don't modify error codes */
-+	if (unlikely(urb->unlinked))
-+		return status;
-+
-+	/* force cleanup after short read; not always an error */
-+	if (unlikely(IS_SHORT_READ(token)))
-+		status = -EREMOTEIO;
-+
-+	/* serious "can't proceed" faults reported by the hardware */
-+	if (token & QTD_STS_HALT) {
-+		if (token & QTD_STS_BABBLE) {
-+			/* FIXME "must" disable babbling device's port too */
-+			status = -EOVERFLOW;
-+		/* CERR nonzero + halt --> stall */
-+		} else if (QTD_CERR(token)) {
-+			status = -EPIPE;
-+
-+		/* In theory, more than one of the following bits can be set
-+		 * since they are sticky and the transaction is retried.
-+		 * Which to test first is rather arbitrary.
-+		 */
-+		} else if (token & QTD_STS_MMF) {
-+			/* fs/ls interrupt xfer missed the complete-split */
-+			status = -EPROTO;
-+		} else if (token & QTD_STS_DBE) {
-+			status = (QTD_PID(token) == 1) /* IN ? */
-+				? -ENOSR  /* hc couldn't read data */
-+				: -ECOMM; /* hc couldn't write data */
-+		} else if (token & QTD_STS_XACT) {
-+			/* timeout, bad CRC, wrong PID, etc */
-+			fotg210_dbg(fotg210, "devpath %s ep%d%s 3strikes\n",
-+					urb->dev->devpath,
-+					usb_pipeendpoint(urb->pipe),
-+					usb_pipein(urb->pipe) ? "in" : "out");
-+			status = -EPROTO;
-+		} else {	/* unknown */
-+			status = -EPROTO;
-+		}
-+
-+		fotg210_dbg(fotg210,
-+				"dev%d ep%d%s qtd token %08x --> status %d\n",
-+				usb_pipedevice(urb->pipe),
-+				usb_pipeendpoint(urb->pipe),
-+				usb_pipein(urb->pipe) ? "in" : "out",
-+				token, status);
-+	}
-+
-+	return status;
-+}
-+
-+static void fotg210_urb_done(struct fotg210_hcd *fotg210, struct urb *urb,
-+		int status)
-+__releases(fotg210->lock)
-+__acquires(fotg210->lock)
-+{
-+	if (likely(urb->hcpriv != NULL)) {
-+		struct fotg210_qh *qh = (struct fotg210_qh *) urb->hcpriv;
-+
-+		/* S-mask in a QH means it's an interrupt urb */
-+		if ((qh->hw->hw_info2 & cpu_to_hc32(fotg210, QH_SMASK)) != 0) {
-+
-+			/* ... update hc-wide periodic stats (for usbfs) */
-+			fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs--;
-+		}
-+	}
-+
-+	if (unlikely(urb->unlinked)) {
-+		INCR(fotg210->stats.unlink);
-+	} else {
-+		/* report non-error and short read status as zero */
-+		if (status == -EINPROGRESS || status == -EREMOTEIO)
-+			status = 0;
-+		INCR(fotg210->stats.complete);
-+	}
-+
-+#ifdef FOTG210_URB_TRACE
-+	fotg210_dbg(fotg210,
-+			"%s %s urb %p ep%d%s status %d len %d/%d\n",
-+			__func__, urb->dev->devpath, urb,
-+			usb_pipeendpoint(urb->pipe),
-+			usb_pipein(urb->pipe) ? "in" : "out",
-+			status,
-+			urb->actual_length, urb->transfer_buffer_length);
-+#endif
-+
-+	/* complete() can reenter this HCD */
-+	usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+	spin_unlock(&fotg210->lock);
-+	usb_hcd_giveback_urb(fotg210_to_hcd(fotg210), urb, status);
-+	spin_lock(&fotg210->lock);
-+}
-+
-+static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+/* Process and free completed qtds for a qh, returning URBs to drivers.
-+ * Chases up to qh->hw_current.  Returns number of completions called,
-+ * indicating how much "real" work we did.
-+ */
-+static unsigned qh_completions(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh)
-+{
-+	struct fotg210_qtd *last, *end = qh->dummy;
-+	struct fotg210_qtd *qtd, *tmp;
-+	int last_status;
-+	int stopped;
-+	unsigned count = 0;
-+	u8 state;
-+	struct fotg210_qh_hw *hw = qh->hw;
-+
-+	if (unlikely(list_empty(&qh->qtd_list)))
-+		return count;
-+
-+	/* completions (or tasks on other cpus) must never clobber HALT
-+	 * till we've gone through and cleaned everything up, even when
-+	 * they add urbs to this qh's queue or mark them for unlinking.
-+	 *
-+	 * NOTE:  unlinking expects to be done in queue order.
-+	 *
-+	 * It's a bug for qh->qh_state to be anything other than
-+	 * QH_STATE_IDLE, unless our caller is scan_async() or
-+	 * scan_intr().
-+	 */
-+	state = qh->qh_state;
-+	qh->qh_state = QH_STATE_COMPLETING;
-+	stopped = (state == QH_STATE_IDLE);
-+
-+rescan:
-+	last = NULL;
-+	last_status = -EINPROGRESS;
-+	qh->needs_rescan = 0;
-+
-+	/* remove de-activated QTDs from front of queue.
-+	 * after faults (including short reads), cleanup this urb
-+	 * then let the queue advance.
-+	 * if queue is stopped, handles unlinks.
-+	 */
-+	list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) {
-+		struct urb *urb;
-+		u32 token = 0;
-+
-+		urb = qtd->urb;
-+
-+		/* clean up any state from previous QTD ...*/
-+		if (last) {
-+			if (likely(last->urb != urb)) {
-+				fotg210_urb_done(fotg210, last->urb,
-+						last_status);
-+				count++;
-+				last_status = -EINPROGRESS;
-+			}
-+			fotg210_qtd_free(fotg210, last);
-+			last = NULL;
-+		}
-+
-+		/* ignore urbs submitted during completions we reported */
-+		if (qtd == end)
-+			break;
-+
-+		/* hardware copies qtd out of qh overlay */
-+		rmb();
-+		token = hc32_to_cpu(fotg210, qtd->hw_token);
-+
-+		/* always clean up qtds the hc de-activated */
-+retry_xacterr:
-+		if ((token & QTD_STS_ACTIVE) == 0) {
-+
-+			/* Report Data Buffer Error: non-fatal but useful */
-+			if (token & QTD_STS_DBE)
-+				fotg210_dbg(fotg210,
-+					"detected DataBufferErr for urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-+					urb, usb_endpoint_num(&urb->ep->desc),
-+					usb_endpoint_dir_in(&urb->ep->desc)
-+						? "in" : "out",
-+					urb->transfer_buffer_length, qtd, qh);
-+
-+			/* on STALL, error, and short reads this urb must
-+			 * complete and all its qtds must be recycled.
-+			 */
-+			if ((token & QTD_STS_HALT) != 0) {
-+
-+				/* retry transaction errors until we
-+				 * reach the software xacterr limit
-+				 */
-+				if ((token & QTD_STS_XACT) &&
-+						QTD_CERR(token) == 0 &&
-+						++qh->xacterrs < QH_XACTERR_MAX &&
-+						!urb->unlinked) {
-+					fotg210_dbg(fotg210,
-+						"detected XactErr len %zu/%zu retry %d\n",
-+						qtd->length - QTD_LENGTH(token),
-+						qtd->length,
-+						qh->xacterrs);
-+
-+					/* reset the token in the qtd and the
-+					 * qh overlay (which still contains
-+					 * the qtd) so that we pick up from
-+					 * where we left off
-+					 */
-+					token &= ~QTD_STS_HALT;
-+					token |= QTD_STS_ACTIVE |
-+						 (FOTG210_TUNE_CERR << 10);
-+					qtd->hw_token = cpu_to_hc32(fotg210,
-+							token);
-+					wmb();
-+					hw->hw_token = cpu_to_hc32(fotg210,
-+							token);
-+					goto retry_xacterr;
-+				}
-+				stopped = 1;
-+
-+			/* magic dummy for some short reads; qh won't advance.
-+			 * that silicon quirk can kick in with this dummy too.
-+			 *
-+			 * other short reads won't stop the queue, including
-+			 * control transfers (status stage handles that) or
-+			 * most other single-qtd reads ... the queue stops if
-+			 * URB_SHORT_NOT_OK was set so the driver submitting
-+			 * the urbs could clean it up.
-+			 */
-+			} else if (IS_SHORT_READ(token) &&
-+					!(qtd->hw_alt_next &
-+					FOTG210_LIST_END(fotg210))) {
-+				stopped = 1;
-+			}
-+
-+		/* stop scanning when we reach qtds the hc is using */
-+		} else if (likely(!stopped
-+				&& fotg210->rh_state >= FOTG210_RH_RUNNING)) {
-+			break;
-+
-+		/* scan the whole queue for unlinks whenever it stops */
-+		} else {
-+			stopped = 1;
-+
-+			/* cancel everything if we halt, suspend, etc */
-+			if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+				last_status = -ESHUTDOWN;
-+
-+			/* this qtd is active; skip it unless a previous qtd
-+			 * for its urb faulted, or its urb was canceled.
-+			 */
-+			else if (last_status == -EINPROGRESS && !urb->unlinked)
-+				continue;
-+
-+			/* qh unlinked; token in overlay may be most current */
-+			if (state == QH_STATE_IDLE &&
-+					cpu_to_hc32(fotg210, qtd->qtd_dma)
-+					== hw->hw_current) {
-+				token = hc32_to_cpu(fotg210, hw->hw_token);
-+
-+				/* An unlink may leave an incomplete
-+				 * async transaction in the TT buffer.
-+				 * We have to clear it.
-+				 */
-+				fotg210_clear_tt_buffer(fotg210, qh, urb,
-+						token);
-+			}
-+		}
-+
-+		/* unless we already know the urb's status, collect qtd status
-+		 * and update count of bytes transferred.  in common short read
-+		 * cases with only one data qtd (including control transfers),
-+		 * queue processing won't halt.  but with two or more qtds (for
-+		 * example, with a 32 KB transfer), when the first qtd gets a
-+		 * short read the second must be removed by hand.
-+		 */
-+		if (last_status == -EINPROGRESS) {
-+			last_status = qtd_copy_status(fotg210, urb,
-+					qtd->length, token);
-+			if (last_status == -EREMOTEIO &&
-+					(qtd->hw_alt_next &
-+					FOTG210_LIST_END(fotg210)))
-+				last_status = -EINPROGRESS;
-+
-+			/* As part of low/full-speed endpoint-halt processing
-+			 * we must clear the TT buffer (11.17.5).
-+			 */
-+			if (unlikely(last_status != -EINPROGRESS &&
-+					last_status != -EREMOTEIO)) {
-+				/* The TT's in some hubs malfunction when they
-+				 * receive this request following a STALL (they
-+				 * stop sending isochronous packets).  Since a
-+				 * STALL can't leave the TT buffer in a busy
-+				 * state (if you believe Figures 11-48 - 11-51
-+				 * in the USB 2.0 spec), we won't clear the TT
-+				 * buffer in this case.  Strictly speaking this
-+				 * is a violation of the spec.
-+				 */
-+				if (last_status != -EPIPE)
-+					fotg210_clear_tt_buffer(fotg210, qh,
-+							urb, token);
-+			}
-+		}
-+
-+		/* if we're removing something not at the queue head,
-+		 * patch the hardware queue pointer.
-+		 */
-+		if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
-+			last = list_entry(qtd->qtd_list.prev,
-+					struct fotg210_qtd, qtd_list);
-+			last->hw_next = qtd->hw_next;
-+		}
-+
-+		/* remove qtd; it's recycled after possible urb completion */
-+		list_del(&qtd->qtd_list);
-+		last = qtd;
-+
-+		/* reinit the xacterr counter for the next qtd */
-+		qh->xacterrs = 0;
-+	}
-+
-+	/* last urb's completion might still need calling */
-+	if (likely(last != NULL)) {
-+		fotg210_urb_done(fotg210, last->urb, last_status);
-+		count++;
-+		fotg210_qtd_free(fotg210, last);
-+	}
-+
-+	/* Do we need to rescan for URBs dequeued during a giveback? */
-+	if (unlikely(qh->needs_rescan)) {
-+		/* If the QH is already unlinked, do the rescan now. */
-+		if (state == QH_STATE_IDLE)
-+			goto rescan;
-+
-+		/* Otherwise we have to wait until the QH is fully unlinked.
-+		 * Our caller will start an unlink if qh->needs_rescan is
-+		 * set.  But if an unlink has already started, nothing needs
-+		 * to be done.
-+		 */
-+		if (state != QH_STATE_LINKED)
-+			qh->needs_rescan = 0;
-+	}
-+
-+	/* restore original state; caller must unlink or relink */
-+	qh->qh_state = state;
-+
-+	/* be sure the hardware's done with the qh before refreshing
-+	 * it after fault cleanup, or recovering from silicon wrongly
-+	 * overlaying the dummy qtd (which reduces DMA chatter).
-+	 */
-+	if (stopped != 0 || hw->hw_qtd_next == FOTG210_LIST_END(fotg210)) {
-+		switch (state) {
-+		case QH_STATE_IDLE:
-+			qh_refresh(fotg210, qh);
-+			break;
-+		case QH_STATE_LINKED:
-+			/* We won't refresh a QH that's linked (after the HC
-+			 * stopped the queue).  That avoids a race:
-+			 *  - HC reads first part of QH;
-+			 *  - CPU updates that first part and the token;
-+			 *  - HC reads rest of that QH, including token
-+			 * Result:  HC gets an inconsistent image, and then
-+			 * DMAs to/from the wrong memory (corrupting it).
-+			 *
-+			 * That should be rare for interrupt transfers,
-+			 * except maybe high bandwidth ...
-+			 */
-+
-+			/* Tell the caller to start an unlink */
-+			qh->needs_rescan = 1;
-+			break;
-+		/* otherwise, unlink already started */
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+/* reverse of qh_urb_transaction:  free a list of TDs.
-+ * used for cleanup after errors, before HC sees an URB's TDs.
-+ */
-+static void qtd_list_free(struct fotg210_hcd *fotg210, struct urb *urb,
-+		struct list_head *head)
-+{
-+	struct fotg210_qtd *qtd, *temp;
-+
-+	list_for_each_entry_safe(qtd, temp, head, qtd_list) {
-+		list_del(&qtd->qtd_list);
-+		fotg210_qtd_free(fotg210, qtd);
-+	}
-+}
-+
-+/* create a list of filled qtds for this URB; won't link into qh.
-+ */
-+static struct list_head *qh_urb_transaction(struct fotg210_hcd *fotg210,
-+		struct urb *urb, struct list_head *head, gfp_t flags)
-+{
-+	struct fotg210_qtd *qtd, *qtd_prev;
-+	dma_addr_t buf;
-+	int len, this_sg_len, maxpacket;
-+	int is_input;
-+	u32 token;
-+	int i;
-+	struct scatterlist *sg;
-+
-+	/*
-+	 * URBs map to sequences of QTDs:  one logical transaction
-+	 */
-+	qtd = fotg210_qtd_alloc(fotg210, flags);
-+	if (unlikely(!qtd))
-+		return NULL;
-+	list_add_tail(&qtd->qtd_list, head);
-+	qtd->urb = urb;
-+
-+	token = QTD_STS_ACTIVE;
-+	token |= (FOTG210_TUNE_CERR << 10);
-+	/* for split transactions, SplitXState initialized to zero */
-+
-+	len = urb->transfer_buffer_length;
-+	is_input = usb_pipein(urb->pipe);
-+	if (usb_pipecontrol(urb->pipe)) {
-+		/* SETUP pid */
-+		qtd_fill(fotg210, qtd, urb->setup_dma,
-+				sizeof(struct usb_ctrlrequest),
-+				token | (2 /* "setup" */ << 8), 8);
-+
-+		/* ... and always at least one more pid */
-+		token ^= QTD_TOGGLE;
-+		qtd_prev = qtd;
-+		qtd = fotg210_qtd_alloc(fotg210, flags);
-+		if (unlikely(!qtd))
-+			goto cleanup;
-+		qtd->urb = urb;
-+		qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+		list_add_tail(&qtd->qtd_list, head);
-+
-+		/* for zero length DATA stages, STATUS is always IN */
-+		if (len == 0)
-+			token |= (1 /* "in" */ << 8);
-+	}
-+
-+	/*
-+	 * data transfer stage:  buffer setup
-+	 */
-+	i = urb->num_mapped_sgs;
-+	if (len > 0 && i > 0) {
-+		sg = urb->sg;
-+		buf = sg_dma_address(sg);
-+
-+		/* urb->transfer_buffer_length may be smaller than the
-+		 * size of the scatterlist (or vice versa)
-+		 */
-+		this_sg_len = min_t(int, sg_dma_len(sg), len);
-+	} else {
-+		sg = NULL;
-+		buf = urb->transfer_dma;
-+		this_sg_len = len;
-+	}
-+
-+	if (is_input)
-+		token |= (1 /* "in" */ << 8);
-+	/* else it's already initted to "out" pid (0 << 8) */
-+
-+	maxpacket = usb_maxpacket(urb->dev, urb->pipe);
-+
-+	/*
-+	 * buffer gets wrapped in one or more qtds;
-+	 * last one may be "short" (including zero len)
-+	 * and may serve as a control status ack
-+	 */
-+	for (;;) {
-+		int this_qtd_len;
-+
-+		this_qtd_len = qtd_fill(fotg210, qtd, buf, this_sg_len, token,
-+				maxpacket);
-+		this_sg_len -= this_qtd_len;
-+		len -= this_qtd_len;
-+		buf += this_qtd_len;
-+
-+		/*
-+		 * short reads advance to a "magic" dummy instead of the next
-+		 * qtd ... that forces the queue to stop, for manual cleanup.
-+		 * (this will usually be overridden later.)
-+		 */
-+		if (is_input)
-+			qtd->hw_alt_next = fotg210->async->hw->hw_alt_next;
-+
-+		/* qh makes control packets use qtd toggle; maybe switch it */
-+		if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
-+			token ^= QTD_TOGGLE;
-+
-+		if (likely(this_sg_len <= 0)) {
-+			if (--i <= 0 || len <= 0)
-+				break;
-+			sg = sg_next(sg);
-+			buf = sg_dma_address(sg);
-+			this_sg_len = min_t(int, sg_dma_len(sg), len);
-+		}
-+
-+		qtd_prev = qtd;
-+		qtd = fotg210_qtd_alloc(fotg210, flags);
-+		if (unlikely(!qtd))
-+			goto cleanup;
-+		qtd->urb = urb;
-+		qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+		list_add_tail(&qtd->qtd_list, head);
-+	}
-+
-+	/*
-+	 * unless the caller requires manual cleanup after short reads,
-+	 * have the alt_next mechanism keep the queue running after the
-+	 * last data qtd (the only one, for control and most other cases).
-+	 */
-+	if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 ||
-+			usb_pipecontrol(urb->pipe)))
-+		qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
-+
-+	/*
-+	 * control requests may need a terminating data "status" ack;
-+	 * other OUT ones may need a terminating short packet
-+	 * (zero length).
-+	 */
-+	if (likely(urb->transfer_buffer_length != 0)) {
-+		int one_more = 0;
-+
-+		if (usb_pipecontrol(urb->pipe)) {
-+			one_more = 1;
-+			token ^= 0x0100;	/* "in" <--> "out"  */
-+			token |= QTD_TOGGLE;	/* force DATA1 */
-+		} else if (usb_pipeout(urb->pipe)
-+				&& (urb->transfer_flags & URB_ZERO_PACKET)
-+				&& !(urb->transfer_buffer_length % maxpacket)) {
-+			one_more = 1;
-+		}
-+		if (one_more) {
-+			qtd_prev = qtd;
-+			qtd = fotg210_qtd_alloc(fotg210, flags);
-+			if (unlikely(!qtd))
-+				goto cleanup;
-+			qtd->urb = urb;
-+			qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+			list_add_tail(&qtd->qtd_list, head);
-+
-+			/* never any data in such packets */
-+			qtd_fill(fotg210, qtd, 0, 0, token, 0);
-+		}
-+	}
-+
-+	/* by default, enable interrupt on urb completion */
-+	if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
-+		qtd->hw_token |= cpu_to_hc32(fotg210, QTD_IOC);
-+	return head;
-+
-+cleanup:
-+	qtd_list_free(fotg210, urb, head);
-+	return NULL;
-+}
-+
-+/* Would be best to create all qh's from config descriptors,
-+ * when each interface/altsetting is established.  Unlink
-+ * any previous qh and cancel its urbs first; endpoints are
-+ * implicitly reset then (data toggle too).
-+ * That'd mean updating how usbcore talks to HCDs. (2.7?)
-+ */
-+
-+
-+/* Each QH holds a qtd list; a QH is used for everything except iso.
-+ *
-+ * For interrupt urbs, the scheduler must set the microframe scheduling
-+ * mask(s) each time the QH gets scheduled.  For highspeed, that's
-+ * just one microframe in the s-mask.  For split interrupt transactions
-+ * there are additional complications: c-mask, maybe FSTNs.
-+ */
-+static struct fotg210_qh *qh_make(struct fotg210_hcd *fotg210, struct urb *urb,
-+		gfp_t flags)
-+{
-+	struct fotg210_qh *qh = fotg210_qh_alloc(fotg210, flags);
-+	struct usb_host_endpoint *ep;
-+	u32 info1 = 0, info2 = 0;
-+	int is_input, type;
-+	int maxp = 0;
-+	int mult;
-+	struct usb_tt *tt = urb->dev->tt;
-+	struct fotg210_qh_hw *hw;
-+
-+	if (!qh)
-+		return qh;
-+
-+	/*
-+	 * init endpoint/device data for this QH
-+	 */
-+	info1 |= usb_pipeendpoint(urb->pipe) << 8;
-+	info1 |= usb_pipedevice(urb->pipe) << 0;
-+
-+	is_input = usb_pipein(urb->pipe);
-+	type = usb_pipetype(urb->pipe);
-+	ep = usb_pipe_endpoint(urb->dev, urb->pipe);
-+	maxp = usb_endpoint_maxp(&ep->desc);
-+	mult = usb_endpoint_maxp_mult(&ep->desc);
-+
-+	/* 1024 byte maxpacket is a hardware ceiling.  High bandwidth
-+	 * acts like up to 3KB, but is built from smaller packets.
-+	 */
-+	if (maxp > 1024) {
-+		fotg210_dbg(fotg210, "bogus qh maxpacket %d\n", maxp);
-+		goto done;
-+	}
-+
-+	/* Compute interrupt scheduling parameters just once, and save.
-+	 * - allowing for high bandwidth, how many nsec/uframe are used?
-+	 * - split transactions need a second CSPLIT uframe; same question
-+	 * - splits also need a schedule gap (for full/low speed I/O)
-+	 * - qh has a polling interval
-+	 *
-+	 * For control/bulk requests, the HC or TT handles these.
-+	 */
-+	if (type == PIPE_INTERRUPT) {
-+		qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
-+				is_input, 0, mult * maxp));
-+		qh->start = NO_FRAME;
-+
-+		if (urb->dev->speed == USB_SPEED_HIGH) {
-+			qh->c_usecs = 0;
-+			qh->gap_uf = 0;
-+
-+			qh->period = urb->interval >> 3;
-+			if (qh->period == 0 && urb->interval != 1) {
-+				/* NOTE interval 2 or 4 uframes could work.
-+				 * But interval 1 scheduling is simpler, and
-+				 * includes high bandwidth.
-+				 */
-+				urb->interval = 1;
-+			} else if (qh->period > fotg210->periodic_size) {
-+				qh->period = fotg210->periodic_size;
-+				urb->interval = qh->period << 3;
-+			}
-+		} else {
-+			int think_time;
-+
-+			/* gap is f(FS/LS transfer times) */
-+			qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
-+					is_input, 0, maxp) / (125 * 1000);
-+
-+			/* FIXME this just approximates SPLIT/CSPLIT times */
-+			if (is_input) {		/* SPLIT, gap, CSPLIT+DATA */
-+				qh->c_usecs = qh->usecs + HS_USECS(0);
-+				qh->usecs = HS_USECS(1);
-+			} else {		/* SPLIT+DATA, gap, CSPLIT */
-+				qh->usecs += HS_USECS(1);
-+				qh->c_usecs = HS_USECS(0);
-+			}
-+
-+			think_time = tt ? tt->think_time : 0;
-+			qh->tt_usecs = NS_TO_US(think_time +
-+					usb_calc_bus_time(urb->dev->speed,
-+					is_input, 0, maxp));
-+			qh->period = urb->interval;
-+			if (qh->period > fotg210->periodic_size) {
-+				qh->period = fotg210->periodic_size;
-+				urb->interval = qh->period;
-+			}
-+		}
-+	}
-+
-+	/* support for tt scheduling, and access to toggles */
-+	qh->dev = urb->dev;
-+
-+	/* using TT? */
-+	switch (urb->dev->speed) {
-+	case USB_SPEED_LOW:
-+		info1 |= QH_LOW_SPEED;
-+		fallthrough;
-+
-+	case USB_SPEED_FULL:
-+		/* EPS 0 means "full" */
-+		if (type != PIPE_INTERRUPT)
-+			info1 |= (FOTG210_TUNE_RL_TT << 28);
-+		if (type == PIPE_CONTROL) {
-+			info1 |= QH_CONTROL_EP;		/* for TT */
-+			info1 |= QH_TOGGLE_CTL;		/* toggle from qtd */
-+		}
-+		info1 |= maxp << 16;
-+
-+		info2 |= (FOTG210_TUNE_MULT_TT << 30);
-+
-+		/* Some Freescale processors have an erratum in which the
-+		 * port number in the queue head was 0..N-1 instead of 1..N.
-+		 */
-+		if (fotg210_has_fsl_portno_bug(fotg210))
-+			info2 |= (urb->dev->ttport-1) << 23;
-+		else
-+			info2 |= urb->dev->ttport << 23;
-+
-+		/* set the address of the TT; for TDI's integrated
-+		 * root hub tt, leave it zeroed.
-+		 */
-+		if (tt && tt->hub != fotg210_to_hcd(fotg210)->self.root_hub)
-+			info2 |= tt->hub->devnum << 16;
-+
-+		/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
-+
-+		break;
-+
-+	case USB_SPEED_HIGH:		/* no TT involved */
-+		info1 |= QH_HIGH_SPEED;
-+		if (type == PIPE_CONTROL) {
-+			info1 |= (FOTG210_TUNE_RL_HS << 28);
-+			info1 |= 64 << 16;	/* usb2 fixed maxpacket */
-+			info1 |= QH_TOGGLE_CTL;	/* toggle from qtd */
-+			info2 |= (FOTG210_TUNE_MULT_HS << 30);
-+		} else if (type == PIPE_BULK) {
-+			info1 |= (FOTG210_TUNE_RL_HS << 28);
-+			/* The USB spec says that high speed bulk endpoints
-+			 * always use 512 byte maxpacket.  But some device
-+			 * vendors decided to ignore that, and MSFT is happy
-+			 * to help them do so.  So now people expect to use
-+			 * such nonconformant devices with Linux too; sigh.
-+			 */
-+			info1 |= maxp << 16;
-+			info2 |= (FOTG210_TUNE_MULT_HS << 30);
-+		} else {		/* PIPE_INTERRUPT */
-+			info1 |= maxp << 16;
-+			info2 |= mult << 30;
-+		}
-+		break;
-+	default:
-+		fotg210_dbg(fotg210, "bogus dev %p speed %d\n", urb->dev,
-+				urb->dev->speed);
-+done:
-+		qh_destroy(fotg210, qh);
-+		return NULL;
-+	}
-+
-+	/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
-+
-+	/* init as live, toggle clear, advance to dummy */
-+	qh->qh_state = QH_STATE_IDLE;
-+	hw = qh->hw;
-+	hw->hw_info1 = cpu_to_hc32(fotg210, info1);
-+	hw->hw_info2 = cpu_to_hc32(fotg210, info2);
-+	qh->is_out = !is_input;
-+	usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
-+	qh_refresh(fotg210, qh);
-+	return qh;
-+}
-+
-+static void enable_async(struct fotg210_hcd *fotg210)
-+{
-+	if (fotg210->async_count++)
-+		return;
-+
-+	/* Stop waiting to turn off the async schedule */
-+	fotg210->enabled_hrtimer_events &= ~BIT(FOTG210_HRTIMER_DISABLE_ASYNC);
-+
-+	/* Don't start the schedule until ASS is 0 */
-+	fotg210_poll_ASS(fotg210);
-+	turn_on_io_watchdog(fotg210);
-+}
-+
-+static void disable_async(struct fotg210_hcd *fotg210)
-+{
-+	if (--fotg210->async_count)
-+		return;
-+
-+	/* The async schedule and async_unlink list are supposed to be empty */
-+	WARN_ON(fotg210->async->qh_next.qh || fotg210->async_unlink);
-+
-+	/* Don't turn off the schedule until ASS is 1 */
-+	fotg210_poll_ASS(fotg210);
-+}
-+
-+/* move qh (and its qtds) onto async queue; maybe enable queue.  */
-+
-+static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	__hc32 dma = QH_NEXT(fotg210, qh->qh_dma);
-+	struct fotg210_qh *head;
-+
-+	/* Don't link a QH if there's a Clear-TT-Buffer pending */
-+	if (unlikely(qh->clearing_tt))
-+		return;
-+
-+	WARN_ON(qh->qh_state != QH_STATE_IDLE);
-+
-+	/* clear halt and/or toggle; and maybe recover from silicon quirk */
-+	qh_refresh(fotg210, qh);
-+
-+	/* splice right after start */
-+	head = fotg210->async;
-+	qh->qh_next = head->qh_next;
-+	qh->hw->hw_next = head->hw->hw_next;
-+	wmb();
-+
-+	head->qh_next.qh = qh;
-+	head->hw->hw_next = dma;
-+
-+	qh->xacterrs = 0;
-+	qh->qh_state = QH_STATE_LINKED;
-+	/* qtd completions reported later by interrupt */
-+
-+	enable_async(fotg210);
-+}
-+
-+/* For control/bulk/interrupt, return QH with these TDs appended.
-+ * Allocates and initializes the QH if necessary.
-+ * Returns null if it can't allocate a QH it needs to.
-+ * If the QH has TDs (urbs) already, that's great.
-+ */
-+static struct fotg210_qh *qh_append_tds(struct fotg210_hcd *fotg210,
-+		struct urb *urb, struct list_head *qtd_list,
-+		int epnum, void **ptr)
-+{
-+	struct fotg210_qh *qh = NULL;
-+	__hc32 qh_addr_mask = cpu_to_hc32(fotg210, 0x7f);
-+
-+	qh = (struct fotg210_qh *) *ptr;
-+	if (unlikely(qh == NULL)) {
-+		/* can't sleep here, we have fotg210->lock... */
-+		qh = qh_make(fotg210, urb, GFP_ATOMIC);
-+		*ptr = qh;
-+	}
-+	if (likely(qh != NULL)) {
-+		struct fotg210_qtd *qtd;
-+
-+		if (unlikely(list_empty(qtd_list)))
-+			qtd = NULL;
-+		else
-+			qtd = list_entry(qtd_list->next, struct fotg210_qtd,
-+					qtd_list);
-+
-+		/* control qh may need patching ... */
-+		if (unlikely(epnum == 0)) {
-+			/* usb_reset_device() briefly reverts to address 0 */
-+			if (usb_pipedevice(urb->pipe) == 0)
-+				qh->hw->hw_info1 &= ~qh_addr_mask;
-+		}
-+
-+		/* just one way to queue requests: swap with the dummy qtd.
-+		 * only hc or qh_refresh() ever modify the overlay.
-+		 */
-+		if (likely(qtd != NULL)) {
-+			struct fotg210_qtd *dummy;
-+			dma_addr_t dma;
-+			__hc32 token;
-+
-+			/* to avoid racing the HC, use the dummy td instead of
-+			 * the first td of our list (becomes new dummy).  both
-+			 * tds stay deactivated until we're done, when the
-+			 * HC is allowed to fetch the old dummy (4.10.2).
-+			 */
-+			token = qtd->hw_token;
-+			qtd->hw_token = HALT_BIT(fotg210);
-+
-+			dummy = qh->dummy;
-+
-+			dma = dummy->qtd_dma;
-+			*dummy = *qtd;
-+			dummy->qtd_dma = dma;
-+
-+			list_del(&qtd->qtd_list);
-+			list_add(&dummy->qtd_list, qtd_list);
-+			list_splice_tail(qtd_list, &qh->qtd_list);
-+
-+			fotg210_qtd_init(fotg210, qtd, qtd->qtd_dma);
-+			qh->dummy = qtd;
-+
-+			/* hc must see the new dummy at list end */
-+			dma = qtd->qtd_dma;
-+			qtd = list_entry(qh->qtd_list.prev,
-+					struct fotg210_qtd, qtd_list);
-+			qtd->hw_next = QTD_NEXT(fotg210, dma);
-+
-+			/* let the hc process these next qtds */
-+			wmb();
-+			dummy->hw_token = token;
-+
-+			urb->hcpriv = qh;
-+		}
-+	}
-+	return qh;
-+}
-+
-+static int submit_async(struct fotg210_hcd *fotg210, struct urb *urb,
-+		struct list_head *qtd_list, gfp_t mem_flags)
-+{
-+	int epnum;
-+	unsigned long flags;
-+	struct fotg210_qh *qh = NULL;
-+	int rc;
-+
-+	epnum = urb->ep->desc.bEndpointAddress;
-+
-+#ifdef FOTG210_URB_TRACE
-+	{
-+		struct fotg210_qtd *qtd;
-+
-+		qtd = list_entry(qtd_list->next, struct fotg210_qtd, qtd_list);
-+		fotg210_dbg(fotg210,
-+				"%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-+				__func__, urb->dev->devpath, urb,
-+				epnum & 0x0f, (epnum & USB_DIR_IN)
-+					? "in" : "out",
-+				urb->transfer_buffer_length,
-+				qtd, urb->ep->hcpriv);
-+	}
-+#endif
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+		rc = -ESHUTDOWN;
-+		goto done;
-+	}
-+	rc = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+	if (unlikely(rc))
-+		goto done;
-+
-+	qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-+	if (unlikely(qh == NULL)) {
-+		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+		rc = -ENOMEM;
-+		goto done;
-+	}
-+
-+	/* Control/bulk operations through TTs don't need scheduling,
-+	 * the HC and TT handle it when the TT has a buffer ready.
-+	 */
-+	if (likely(qh->qh_state == QH_STATE_IDLE))
-+		qh_link_async(fotg210, qh);
-+done:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	if (unlikely(qh == NULL))
-+		qtd_list_free(fotg210, urb, qtd_list);
-+	return rc;
-+}
-+
-+static void single_unlink_async(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh)
-+{
-+	struct fotg210_qh *prev;
-+
-+	/* Add to the end of the list of QHs waiting for the next IAAD */
-+	qh->qh_state = QH_STATE_UNLINK;
-+	if (fotg210->async_unlink)
-+		fotg210->async_unlink_last->unlink_next = qh;
-+	else
-+		fotg210->async_unlink = qh;
-+	fotg210->async_unlink_last = qh;
-+
-+	/* Unlink it from the schedule */
-+	prev = fotg210->async;
-+	while (prev->qh_next.qh != qh)
-+		prev = prev->qh_next.qh;
-+
-+	prev->hw->hw_next = qh->hw->hw_next;
-+	prev->qh_next = qh->qh_next;
-+	if (fotg210->qh_scan_next == qh)
-+		fotg210->qh_scan_next = qh->qh_next.qh;
-+}
-+
-+static void start_iaa_cycle(struct fotg210_hcd *fotg210, bool nested)
-+{
-+	/*
-+	 * Do nothing if an IAA cycle is already running or
-+	 * if one will be started shortly.
-+	 */
-+	if (fotg210->async_iaa || fotg210->async_unlinking)
-+		return;
-+
-+	/* Do all the waiting QHs at once */
-+	fotg210->async_iaa = fotg210->async_unlink;
-+	fotg210->async_unlink = NULL;
-+
-+	/* If the controller isn't running, we don't have to wait for it */
-+	if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING)) {
-+		if (!nested)		/* Avoid recursion */
-+			end_unlink_async(fotg210);
-+
-+	/* Otherwise start a new IAA cycle */
-+	} else if (likely(fotg210->rh_state == FOTG210_RH_RUNNING)) {
-+		/* Make sure the unlinks are all visible to the hardware */
-+		wmb();
-+
-+		fotg210_writel(fotg210, fotg210->command | CMD_IAAD,
-+				&fotg210->regs->command);
-+		fotg210_readl(fotg210, &fotg210->regs->command);
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_IAA_WATCHDOG,
-+				true);
-+	}
-+}
-+
-+/* the async qh for the qtds being unlinked are now gone from the HC */
-+
-+static void end_unlink_async(struct fotg210_hcd *fotg210)
-+{
-+	struct fotg210_qh *qh;
-+
-+	/* Process the idle QHs */
-+restart:
-+	fotg210->async_unlinking = true;
-+	while (fotg210->async_iaa) {
-+		qh = fotg210->async_iaa;
-+		fotg210->async_iaa = qh->unlink_next;
-+		qh->unlink_next = NULL;
-+
-+		qh->qh_state = QH_STATE_IDLE;
-+		qh->qh_next.qh = NULL;
-+
-+		qh_completions(fotg210, qh);
-+		if (!list_empty(&qh->qtd_list) &&
-+				fotg210->rh_state == FOTG210_RH_RUNNING)
-+			qh_link_async(fotg210, qh);
-+		disable_async(fotg210);
-+	}
-+	fotg210->async_unlinking = false;
-+
-+	/* Start a new IAA cycle if any QHs are waiting for it */
-+	if (fotg210->async_unlink) {
-+		start_iaa_cycle(fotg210, true);
-+		if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING))
-+			goto restart;
-+	}
-+}
-+
-+static void unlink_empty_async(struct fotg210_hcd *fotg210)
-+{
-+	struct fotg210_qh *qh, *next;
-+	bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
-+	bool check_unlinks_later = false;
-+
-+	/* Unlink all the async QHs that have been empty for a timer cycle */
-+	next = fotg210->async->qh_next.qh;
-+	while (next) {
-+		qh = next;
-+		next = qh->qh_next.qh;
-+
-+		if (list_empty(&qh->qtd_list) &&
-+				qh->qh_state == QH_STATE_LINKED) {
-+			if (!stopped && qh->unlink_cycle ==
-+					fotg210->async_unlink_cycle)
-+				check_unlinks_later = true;
-+			else
-+				single_unlink_async(fotg210, qh);
-+		}
-+	}
-+
-+	/* Start a new IAA cycle if any QHs are waiting for it */
-+	if (fotg210->async_unlink)
-+		start_iaa_cycle(fotg210, false);
-+
-+	/* QHs that haven't been empty for long enough will be handled later */
-+	if (check_unlinks_later) {
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_ASYNC_UNLINKS,
-+				true);
-+		++fotg210->async_unlink_cycle;
-+	}
-+}
-+
-+/* makes sure the async qh will become idle */
-+/* caller must own fotg210->lock */
-+
-+static void start_unlink_async(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh)
-+{
-+	/*
-+	 * If the QH isn't linked then there's nothing we can do
-+	 * unless we were called during a giveback, in which case
-+	 * qh_completions() has to deal with it.
-+	 */
-+	if (qh->qh_state != QH_STATE_LINKED) {
-+		if (qh->qh_state == QH_STATE_COMPLETING)
-+			qh->needs_rescan = 1;
-+		return;
-+	}
-+
-+	single_unlink_async(fotg210, qh);
-+	start_iaa_cycle(fotg210, false);
-+}
-+
-+static void scan_async(struct fotg210_hcd *fotg210)
-+{
-+	struct fotg210_qh *qh;
-+	bool check_unlinks_later = false;
-+
-+	fotg210->qh_scan_next = fotg210->async->qh_next.qh;
-+	while (fotg210->qh_scan_next) {
-+		qh = fotg210->qh_scan_next;
-+		fotg210->qh_scan_next = qh->qh_next.qh;
-+rescan:
-+		/* clean any finished work for this qh */
-+		if (!list_empty(&qh->qtd_list)) {
-+			int temp;
-+
-+			/*
-+			 * Unlinks could happen here; completion reporting
-+			 * drops the lock.  That's why fotg210->qh_scan_next
-+			 * always holds the next qh to scan; if the next qh
-+			 * gets unlinked then fotg210->qh_scan_next is adjusted
-+			 * in single_unlink_async().
-+			 */
-+			temp = qh_completions(fotg210, qh);
-+			if (qh->needs_rescan) {
-+				start_unlink_async(fotg210, qh);
-+			} else if (list_empty(&qh->qtd_list)
-+					&& qh->qh_state == QH_STATE_LINKED) {
-+				qh->unlink_cycle = fotg210->async_unlink_cycle;
-+				check_unlinks_later = true;
-+			} else if (temp != 0)
-+				goto rescan;
-+		}
-+	}
-+
-+	/*
-+	 * Unlink empty entries, reducing DMA usage as well
-+	 * as HCD schedule-scanning costs.  Delay for any qh
-+	 * we just scanned, there's a not-unusual case that it
-+	 * doesn't stay idle for long.
-+	 */
-+	if (check_unlinks_later && fotg210->rh_state == FOTG210_RH_RUNNING &&
-+			!(fotg210->enabled_hrtimer_events &
-+			BIT(FOTG210_HRTIMER_ASYNC_UNLINKS))) {
-+		fotg210_enable_event(fotg210,
-+				FOTG210_HRTIMER_ASYNC_UNLINKS, true);
-+		++fotg210->async_unlink_cycle;
-+	}
-+}
-+/* EHCI scheduled transaction support:  interrupt, iso, split iso
-+ * These are called "periodic" transactions in the EHCI spec.
-+ *
-+ * Note that for interrupt transfers, the QH/QTD manipulation is shared
-+ * with the "asynchronous" transaction support (control/bulk transfers).
-+ * The only real difference is in how interrupt transfers are scheduled.
-+ *
-+ * For ISO, we make an "iso_stream" head to serve the same role as a QH.
-+ * It keeps track of every ITD (or SITD) that's linked, and holds enough
-+ * pre-calculated schedule data to make appending to the queue be quick.
-+ */
-+static int fotg210_get_frame(struct usb_hcd *hcd);
-+
-+/* periodic_next_shadow - return "next" pointer on shadow list
-+ * @periodic: host pointer to qh/itd
-+ * @tag: hardware tag for type of this record
-+ */
-+static union fotg210_shadow *periodic_next_shadow(struct fotg210_hcd *fotg210,
-+		union fotg210_shadow *periodic, __hc32 tag)
-+{
-+	switch (hc32_to_cpu(fotg210, tag)) {
-+	case Q_TYPE_QH:
-+		return &periodic->qh->qh_next;
-+	case Q_TYPE_FSTN:
-+		return &periodic->fstn->fstn_next;
-+	default:
-+		return &periodic->itd->itd_next;
-+	}
-+}
-+
-+static __hc32 *shadow_next_periodic(struct fotg210_hcd *fotg210,
-+		union fotg210_shadow *periodic, __hc32 tag)
-+{
-+	switch (hc32_to_cpu(fotg210, tag)) {
-+	/* our fotg210_shadow.qh is actually software part */
-+	case Q_TYPE_QH:
-+		return &periodic->qh->hw->hw_next;
-+	/* others are hw parts */
-+	default:
-+		return periodic->hw_next;
-+	}
-+}
-+
-+/* caller must hold fotg210->lock */
-+static void periodic_unlink(struct fotg210_hcd *fotg210, unsigned frame,
-+		void *ptr)
-+{
-+	union fotg210_shadow *prev_p = &fotg210->pshadow[frame];
-+	__hc32 *hw_p = &fotg210->periodic[frame];
-+	union fotg210_shadow here = *prev_p;
-+
-+	/* find predecessor of "ptr"; hw and shadow lists are in sync */
-+	while (here.ptr && here.ptr != ptr) {
-+		prev_p = periodic_next_shadow(fotg210, prev_p,
-+				Q_NEXT_TYPE(fotg210, *hw_p));
-+		hw_p = shadow_next_periodic(fotg210, &here,
-+				Q_NEXT_TYPE(fotg210, *hw_p));
-+		here = *prev_p;
-+	}
-+	/* an interrupt entry (at list end) could have been shared */
-+	if (!here.ptr)
-+		return;
-+
-+	/* update shadow and hardware lists ... the old "next" pointers
-+	 * from ptr may still be in use, the caller updates them.
-+	 */
-+	*prev_p = *periodic_next_shadow(fotg210, &here,
-+			Q_NEXT_TYPE(fotg210, *hw_p));
-+
-+	*hw_p = *shadow_next_periodic(fotg210, &here,
-+			Q_NEXT_TYPE(fotg210, *hw_p));
-+}
-+
-+/* how many of the uframe's 125 usecs are allocated? */
-+static unsigned short periodic_usecs(struct fotg210_hcd *fotg210,
-+		unsigned frame, unsigned uframe)
-+{
-+	__hc32 *hw_p = &fotg210->periodic[frame];
-+	union fotg210_shadow *q = &fotg210->pshadow[frame];
-+	unsigned usecs = 0;
-+	struct fotg210_qh_hw *hw;
-+
-+	while (q->ptr) {
-+		switch (hc32_to_cpu(fotg210, Q_NEXT_TYPE(fotg210, *hw_p))) {
-+		case Q_TYPE_QH:
-+			hw = q->qh->hw;
-+			/* is it in the S-mask? */
-+			if (hw->hw_info2 & cpu_to_hc32(fotg210, 1 << uframe))
-+				usecs += q->qh->usecs;
-+			/* ... or C-mask? */
-+			if (hw->hw_info2 & cpu_to_hc32(fotg210,
-+					1 << (8 + uframe)))
-+				usecs += q->qh->c_usecs;
-+			hw_p = &hw->hw_next;
-+			q = &q->qh->qh_next;
-+			break;
-+		/* case Q_TYPE_FSTN: */
-+		default:
-+			/* for "save place" FSTNs, count the relevant INTR
-+			 * bandwidth from the previous frame
-+			 */
-+			if (q->fstn->hw_prev != FOTG210_LIST_END(fotg210))
-+				fotg210_dbg(fotg210, "ignoring FSTN cost ...\n");
-+
-+			hw_p = &q->fstn->hw_next;
-+			q = &q->fstn->fstn_next;
-+			break;
-+		case Q_TYPE_ITD:
-+			if (q->itd->hw_transaction[uframe])
-+				usecs += q->itd->stream->usecs;
-+			hw_p = &q->itd->hw_next;
-+			q = &q->itd->itd_next;
-+			break;
-+		}
-+	}
-+	if (usecs > fotg210->uframe_periodic_max)
-+		fotg210_err(fotg210, "uframe %d sched overrun: %d usecs\n",
-+				frame * 8 + uframe, usecs);
-+	return usecs;
-+}
-+
-+static int same_tt(struct usb_device *dev1, struct usb_device *dev2)
-+{
-+	if (!dev1->tt || !dev2->tt)
-+		return 0;
-+	if (dev1->tt != dev2->tt)
-+		return 0;
-+	if (dev1->tt->multi)
-+		return dev1->ttport == dev2->ttport;
-+	else
-+		return 1;
-+}
-+
-+/* return true iff the device's transaction translator is available
-+ * for a periodic transfer starting at the specified frame, using
-+ * all the uframes in the mask.
-+ */
-+static int tt_no_collision(struct fotg210_hcd *fotg210, unsigned period,
-+		struct usb_device *dev, unsigned frame, u32 uf_mask)
-+{
-+	if (period == 0)	/* error */
-+		return 0;
-+
-+	/* note bandwidth wastage:  split never follows csplit
-+	 * (different dev or endpoint) until the next uframe.
-+	 * calling convention doesn't make that distinction.
-+	 */
-+	for (; frame < fotg210->periodic_size; frame += period) {
-+		union fotg210_shadow here;
-+		__hc32 type;
-+		struct fotg210_qh_hw *hw;
-+
-+		here = fotg210->pshadow[frame];
-+		type = Q_NEXT_TYPE(fotg210, fotg210->periodic[frame]);
-+		while (here.ptr) {
-+			switch (hc32_to_cpu(fotg210, type)) {
-+			case Q_TYPE_ITD:
-+				type = Q_NEXT_TYPE(fotg210, here.itd->hw_next);
-+				here = here.itd->itd_next;
-+				continue;
-+			case Q_TYPE_QH:
-+				hw = here.qh->hw;
-+				if (same_tt(dev, here.qh->dev)) {
-+					u32 mask;
-+
-+					mask = hc32_to_cpu(fotg210,
-+							hw->hw_info2);
-+					/* "knows" no gap is needed */
-+					mask |= mask >> 8;
-+					if (mask & uf_mask)
-+						break;
-+				}
-+				type = Q_NEXT_TYPE(fotg210, hw->hw_next);
-+				here = here.qh->qh_next;
-+				continue;
-+			/* case Q_TYPE_FSTN: */
-+			default:
-+				fotg210_dbg(fotg210,
-+						"periodic frame %d bogus type %d\n",
-+						frame, type);
-+			}
-+
-+			/* collision or error */
-+			return 0;
-+		}
-+	}
-+
-+	/* no collision */
-+	return 1;
-+}
-+
-+static void enable_periodic(struct fotg210_hcd *fotg210)
-+{
-+	if (fotg210->periodic_count++)
-+		return;
-+
-+	/* Stop waiting to turn off the periodic schedule */
-+	fotg210->enabled_hrtimer_events &=
-+		~BIT(FOTG210_HRTIMER_DISABLE_PERIODIC);
-+
-+	/* Don't start the schedule until PSS is 0 */
-+	fotg210_poll_PSS(fotg210);
-+	turn_on_io_watchdog(fotg210);
-+}
-+
-+static void disable_periodic(struct fotg210_hcd *fotg210)
-+{
-+	if (--fotg210->periodic_count)
-+		return;
-+
-+	/* Don't turn off the schedule until PSS is 1 */
-+	fotg210_poll_PSS(fotg210);
-+}
-+
-+/* periodic schedule slots have iso tds (normal or split) first, then a
-+ * sparse tree for active interrupt transfers.
-+ *
-+ * this just links in a qh; caller guarantees uframe masks are set right.
-+ * no FSTN support (yet; fotg210 0.96+)
-+ */
-+static void qh_link_periodic(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	unsigned i;
-+	unsigned period = qh->period;
-+
-+	dev_dbg(&qh->dev->dev,
-+			"link qh%d-%04x/%p start %d [%d/%d us]\n", period,
-+			hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-+			(QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-+			qh->c_usecs);
-+
-+	/* high bandwidth, or otherwise every microframe */
-+	if (period == 0)
-+		period = 1;
-+
-+	for (i = qh->start; i < fotg210->periodic_size; i += period) {
-+		union fotg210_shadow *prev = &fotg210->pshadow[i];
-+		__hc32 *hw_p = &fotg210->periodic[i];
-+		union fotg210_shadow here = *prev;
-+		__hc32 type = 0;
-+
-+		/* skip the iso nodes at list head */
-+		while (here.ptr) {
-+			type = Q_NEXT_TYPE(fotg210, *hw_p);
-+			if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-+				break;
-+			prev = periodic_next_shadow(fotg210, prev, type);
-+			hw_p = shadow_next_periodic(fotg210, &here, type);
-+			here = *prev;
-+		}
-+
-+		/* sorting each branch by period (slow-->fast)
-+		 * enables sharing interior tree nodes
-+		 */
-+		while (here.ptr && qh != here.qh) {
-+			if (qh->period > here.qh->period)
-+				break;
-+			prev = &here.qh->qh_next;
-+			hw_p = &here.qh->hw->hw_next;
-+			here = *prev;
-+		}
-+		/* link in this qh, unless some earlier pass did that */
-+		if (qh != here.qh) {
-+			qh->qh_next = here;
-+			if (here.qh)
-+				qh->hw->hw_next = *hw_p;
-+			wmb();
-+			prev->qh = qh;
-+			*hw_p = QH_NEXT(fotg210, qh->qh_dma);
-+		}
-+	}
-+	qh->qh_state = QH_STATE_LINKED;
-+	qh->xacterrs = 0;
-+
-+	/* update per-qh bandwidth for usbfs */
-+	fotg210_to_hcd(fotg210)->self.bandwidth_allocated += qh->period
-+		? ((qh->usecs + qh->c_usecs) / qh->period)
-+		: (qh->usecs * 8);
-+
-+	list_add(&qh->intr_node, &fotg210->intr_qh_list);
-+
-+	/* maybe enable periodic schedule processing */
-+	++fotg210->intr_count;
-+	enable_periodic(fotg210);
-+}
-+
-+static void qh_unlink_periodic(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh)
-+{
-+	unsigned i;
-+	unsigned period;
-+
-+	/*
-+	 * If qh is for a low/full-speed device, simply unlinking it
-+	 * could interfere with an ongoing split transaction.  To unlink
-+	 * it safely would require setting the QH_INACTIVATE bit and
-+	 * waiting at least one frame, as described in EHCI 4.12.2.5.
-+	 *
-+	 * We won't bother with any of this.  Instead, we assume that the
-+	 * only reason for unlinking an interrupt QH while the current URB
-+	 * is still active is to dequeue all the URBs (flush the whole
-+	 * endpoint queue).
-+	 *
-+	 * If rebalancing the periodic schedule is ever implemented, this
-+	 * approach will no longer be valid.
-+	 */
-+
-+	/* high bandwidth, or otherwise part of every microframe */
-+	period = qh->period;
-+	if (!period)
-+		period = 1;
-+
-+	for (i = qh->start; i < fotg210->periodic_size; i += period)
-+		periodic_unlink(fotg210, i, qh);
-+
-+	/* update per-qh bandwidth for usbfs */
-+	fotg210_to_hcd(fotg210)->self.bandwidth_allocated -= qh->period
-+		? ((qh->usecs + qh->c_usecs) / qh->period)
-+		: (qh->usecs * 8);
-+
-+	dev_dbg(&qh->dev->dev,
-+			"unlink qh%d-%04x/%p start %d [%d/%d us]\n",
-+			qh->period, hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-+			(QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-+			qh->c_usecs);
-+
-+	/* qh->qh_next still "live" to HC */
-+	qh->qh_state = QH_STATE_UNLINK;
-+	qh->qh_next.ptr = NULL;
-+
-+	if (fotg210->qh_scan_next == qh)
-+		fotg210->qh_scan_next = list_entry(qh->intr_node.next,
-+				struct fotg210_qh, intr_node);
-+	list_del(&qh->intr_node);
-+}
-+
-+static void start_unlink_intr(struct fotg210_hcd *fotg210,
-+		struct fotg210_qh *qh)
-+{
-+	/* If the QH isn't linked then there's nothing we can do
-+	 * unless we were called during a giveback, in which case
-+	 * qh_completions() has to deal with it.
-+	 */
-+	if (qh->qh_state != QH_STATE_LINKED) {
-+		if (qh->qh_state == QH_STATE_COMPLETING)
-+			qh->needs_rescan = 1;
-+		return;
-+	}
-+
-+	qh_unlink_periodic(fotg210, qh);
-+
-+	/* Make sure the unlinks are visible before starting the timer */
-+	wmb();
-+
-+	/*
-+	 * The EHCI spec doesn't say how long it takes the controller to
-+	 * stop accessing an unlinked interrupt QH.  The timer delay is
-+	 * 9 uframes; presumably that will be long enough.
-+	 */
-+	qh->unlink_cycle = fotg210->intr_unlink_cycle;
-+
-+	/* New entries go at the end of the intr_unlink list */
-+	if (fotg210->intr_unlink)
-+		fotg210->intr_unlink_last->unlink_next = qh;
-+	else
-+		fotg210->intr_unlink = qh;
-+	fotg210->intr_unlink_last = qh;
-+
-+	if (fotg210->intr_unlinking)
-+		;	/* Avoid recursive calls */
-+	else if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+		fotg210_handle_intr_unlinks(fotg210);
-+	else if (fotg210->intr_unlink == qh) {
-+		fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-+				true);
-+		++fotg210->intr_unlink_cycle;
-+	}
-+}
-+
-+static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	struct fotg210_qh_hw *hw = qh->hw;
-+	int rc;
-+
-+	qh->qh_state = QH_STATE_IDLE;
-+	hw->hw_next = FOTG210_LIST_END(fotg210);
-+
-+	qh_completions(fotg210, qh);
-+
-+	/* reschedule QH iff another request is queued */
-+	if (!list_empty(&qh->qtd_list) &&
-+			fotg210->rh_state == FOTG210_RH_RUNNING) {
-+		rc = qh_schedule(fotg210, qh);
-+
-+		/* An error here likely indicates handshake failure
-+		 * or no space left in the schedule.  Neither fault
-+		 * should happen often ...
-+		 *
-+		 * FIXME kill the now-dysfunctional queued urbs
-+		 */
-+		if (rc != 0)
-+			fotg210_err(fotg210, "can't reschedule qh %p, err %d\n",
-+					qh, rc);
-+	}
-+
-+	/* maybe turn off periodic schedule */
-+	--fotg210->intr_count;
-+	disable_periodic(fotg210);
-+}
-+
-+static int check_period(struct fotg210_hcd *fotg210, unsigned frame,
-+		unsigned uframe, unsigned period, unsigned usecs)
-+{
-+	int claimed;
-+
-+	/* complete split running into next frame?
-+	 * given FSTN support, we could sometimes check...
-+	 */
-+	if (uframe >= 8)
-+		return 0;
-+
-+	/* convert "usecs we need" to "max already claimed" */
-+	usecs = fotg210->uframe_periodic_max - usecs;
-+
-+	/* we "know" 2 and 4 uframe intervals were rejected; so
-+	 * for period 0, check _every_ microframe in the schedule.
-+	 */
-+	if (unlikely(period == 0)) {
-+		do {
-+			for (uframe = 0; uframe < 7; uframe++) {
-+				claimed = periodic_usecs(fotg210, frame,
-+						uframe);
-+				if (claimed > usecs)
-+					return 0;
-+			}
-+		} while ((frame += 1) < fotg210->periodic_size);
-+
-+	/* just check the specified uframe, at that period */
-+	} else {
-+		do {
-+			claimed = periodic_usecs(fotg210, frame, uframe);
-+			if (claimed > usecs)
-+				return 0;
-+		} while ((frame += period) < fotg210->periodic_size);
-+	}
-+
-+	/* success! */
-+	return 1;
-+}
-+
-+static int check_intr_schedule(struct fotg210_hcd *fotg210, unsigned frame,
-+		unsigned uframe, const struct fotg210_qh *qh, __hc32 *c_maskp)
-+{
-+	int retval = -ENOSPC;
-+	u8 mask = 0;
-+
-+	if (qh->c_usecs && uframe >= 6)		/* FSTN territory? */
-+		goto done;
-+
-+	if (!check_period(fotg210, frame, uframe, qh->period, qh->usecs))
-+		goto done;
-+	if (!qh->c_usecs) {
-+		retval = 0;
-+		*c_maskp = 0;
-+		goto done;
-+	}
-+
-+	/* Make sure this tt's buffer is also available for CSPLITs.
-+	 * We pessimize a bit; probably the typical full speed case
-+	 * doesn't need the second CSPLIT.
-+	 *
-+	 * NOTE:  both SPLIT and CSPLIT could be checked in just
-+	 * one smart pass...
-+	 */
-+	mask = 0x03 << (uframe + qh->gap_uf);
-+	*c_maskp = cpu_to_hc32(fotg210, mask << 8);
-+
-+	mask |= 1 << uframe;
-+	if (tt_no_collision(fotg210, qh->period, qh->dev, frame, mask)) {
-+		if (!check_period(fotg210, frame, uframe + qh->gap_uf + 1,
-+				qh->period, qh->c_usecs))
-+			goto done;
-+		if (!check_period(fotg210, frame, uframe + qh->gap_uf,
-+				qh->period, qh->c_usecs))
-+			goto done;
-+		retval = 0;
-+	}
-+done:
-+	return retval;
-+}
-+
-+/* "first fit" scheduling policy used the first time through,
-+ * or when the previous schedule slot can't be re-used.
-+ */
-+static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+	int status;
-+	unsigned uframe;
-+	__hc32 c_mask;
-+	unsigned frame;	/* 0..(qh->period - 1), or NO_FRAME */
-+	struct fotg210_qh_hw *hw = qh->hw;
-+
-+	qh_refresh(fotg210, qh);
-+	hw->hw_next = FOTG210_LIST_END(fotg210);
-+	frame = qh->start;
-+
-+	/* reuse the previous schedule slots, if we can */
-+	if (frame < qh->period) {
-+		uframe = ffs(hc32_to_cpup(fotg210, &hw->hw_info2) & QH_SMASK);
-+		status = check_intr_schedule(fotg210, frame, --uframe,
-+				qh, &c_mask);
-+	} else {
-+		uframe = 0;
-+		c_mask = 0;
-+		status = -ENOSPC;
-+	}
-+
-+	/* else scan the schedule to find a group of slots such that all
-+	 * uframes have enough periodic bandwidth available.
-+	 */
-+	if (status) {
-+		/* "normal" case, uframing flexible except with splits */
-+		if (qh->period) {
-+			int i;
-+
-+			for (i = qh->period; status && i > 0; --i) {
-+				frame = ++fotg210->random_frame % qh->period;
-+				for (uframe = 0; uframe < 8; uframe++) {
-+					status = check_intr_schedule(fotg210,
-+							frame, uframe, qh,
-+							&c_mask);
-+					if (status == 0)
-+						break;
-+				}
-+			}
-+
-+		/* qh->period == 0 means every uframe */
-+		} else {
-+			frame = 0;
-+			status = check_intr_schedule(fotg210, 0, 0, qh,
-+					&c_mask);
-+		}
-+		if (status)
-+			goto done;
-+		qh->start = frame;
-+
-+		/* reset S-frame and (maybe) C-frame masks */
-+		hw->hw_info2 &= cpu_to_hc32(fotg210, ~(QH_CMASK | QH_SMASK));
-+		hw->hw_info2 |= qh->period
-+			? cpu_to_hc32(fotg210, 1 << uframe)
-+			: cpu_to_hc32(fotg210, QH_SMASK);
-+		hw->hw_info2 |= c_mask;
-+	} else
-+		fotg210_dbg(fotg210, "reused qh %p schedule\n", qh);
-+
-+	/* stuff into the periodic schedule */
-+	qh_link_periodic(fotg210, qh);
-+done:
-+	return status;
-+}
-+
-+static int intr_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-+		struct list_head *qtd_list, gfp_t mem_flags)
-+{
-+	unsigned epnum;
-+	unsigned long flags;
-+	struct fotg210_qh *qh;
-+	int status;
-+	struct list_head empty;
-+
-+	/* get endpoint and transfer/schedule data */
-+	epnum = urb->ep->desc.bEndpointAddress;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+		status = -ESHUTDOWN;
-+		goto done_not_linked;
-+	}
-+	status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+	if (unlikely(status))
-+		goto done_not_linked;
-+
-+	/* get qh and force any scheduling errors */
-+	INIT_LIST_HEAD(&empty);
-+	qh = qh_append_tds(fotg210, urb, &empty, epnum, &urb->ep->hcpriv);
-+	if (qh == NULL) {
-+		status = -ENOMEM;
-+		goto done;
-+	}
-+	if (qh->qh_state == QH_STATE_IDLE) {
-+		status = qh_schedule(fotg210, qh);
-+		if (status)
-+			goto done;
-+	}
-+
-+	/* then queue the urb's tds to the qh */
-+	qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-+	BUG_ON(qh == NULL);
-+
-+	/* ... update usbfs periodic stats */
-+	fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs++;
-+
-+done:
-+	if (unlikely(status))
-+		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+done_not_linked:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	if (status)
-+		qtd_list_free(fotg210, urb, qtd_list);
-+
-+	return status;
-+}
-+
-+static void scan_intr(struct fotg210_hcd *fotg210)
-+{
-+	struct fotg210_qh *qh;
-+
-+	list_for_each_entry_safe(qh, fotg210->qh_scan_next,
-+			&fotg210->intr_qh_list, intr_node) {
-+rescan:
-+		/* clean any finished work for this qh */
-+		if (!list_empty(&qh->qtd_list)) {
-+			int temp;
-+
-+			/*
-+			 * Unlinks could happen here; completion reporting
-+			 * drops the lock.  That's why fotg210->qh_scan_next
-+			 * always holds the next qh to scan; if the next qh
-+			 * gets unlinked then fotg210->qh_scan_next is adjusted
-+			 * in qh_unlink_periodic().
-+			 */
-+			temp = qh_completions(fotg210, qh);
-+			if (unlikely(qh->needs_rescan ||
-+					(list_empty(&qh->qtd_list) &&
-+					qh->qh_state == QH_STATE_LINKED)))
-+				start_unlink_intr(fotg210, qh);
-+			else if (temp != 0)
-+				goto rescan;
-+		}
-+	}
-+}
-+
-+/* fotg210_iso_stream ops work with both ITD and SITD */
-+
-+static struct fotg210_iso_stream *iso_stream_alloc(gfp_t mem_flags)
-+{
-+	struct fotg210_iso_stream *stream;
-+
-+	stream = kzalloc(sizeof(*stream), mem_flags);
-+	if (likely(stream != NULL)) {
-+		INIT_LIST_HEAD(&stream->td_list);
-+		INIT_LIST_HEAD(&stream->free_list);
-+		stream->next_uframe = -1;
-+	}
-+	return stream;
-+}
-+
-+static void iso_stream_init(struct fotg210_hcd *fotg210,
-+		struct fotg210_iso_stream *stream, struct usb_device *dev,
-+		int pipe, unsigned interval)
-+{
-+	u32 buf1;
-+	unsigned epnum, maxp;
-+	int is_input;
-+	long bandwidth;
-+	unsigned multi;
-+	struct usb_host_endpoint *ep;
-+
-+	/*
-+	 * this might be a "high bandwidth" highspeed endpoint,
-+	 * as encoded in the ep descriptor's wMaxPacket field
-+	 */
-+	epnum = usb_pipeendpoint(pipe);
-+	is_input = usb_pipein(pipe) ? USB_DIR_IN : 0;
-+	ep = usb_pipe_endpoint(dev, pipe);
-+	maxp = usb_endpoint_maxp(&ep->desc);
-+	if (is_input)
-+		buf1 = (1 << 11);
-+	else
-+		buf1 = 0;
-+
-+	multi = usb_endpoint_maxp_mult(&ep->desc);
-+	buf1 |= maxp;
-+	maxp *= multi;
-+
-+	stream->buf0 = cpu_to_hc32(fotg210, (epnum << 8) | dev->devnum);
-+	stream->buf1 = cpu_to_hc32(fotg210, buf1);
-+	stream->buf2 = cpu_to_hc32(fotg210, multi);
-+
-+	/* usbfs wants to report the average usecs per frame tied up
-+	 * when transfers on this endpoint are scheduled ...
-+	 */
-+	if (dev->speed == USB_SPEED_FULL) {
-+		interval <<= 3;
-+		stream->usecs = NS_TO_US(usb_calc_bus_time(dev->speed,
-+				is_input, 1, maxp));
-+		stream->usecs /= 8;
-+	} else {
-+		stream->highspeed = 1;
-+		stream->usecs = HS_USECS_ISO(maxp);
-+	}
-+	bandwidth = stream->usecs * 8;
-+	bandwidth /= interval;
-+
-+	stream->bandwidth = bandwidth;
-+	stream->udev = dev;
-+	stream->bEndpointAddress = is_input | epnum;
-+	stream->interval = interval;
-+	stream->maxp = maxp;
-+}
-+
-+static struct fotg210_iso_stream *iso_stream_find(struct fotg210_hcd *fotg210,
-+		struct urb *urb)
-+{
-+	unsigned epnum;
-+	struct fotg210_iso_stream *stream;
-+	struct usb_host_endpoint *ep;
-+	unsigned long flags;
-+
-+	epnum = usb_pipeendpoint(urb->pipe);
-+	if (usb_pipein(urb->pipe))
-+		ep = urb->dev->ep_in[epnum];
-+	else
-+		ep = urb->dev->ep_out[epnum];
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	stream = ep->hcpriv;
-+
-+	if (unlikely(stream == NULL)) {
-+		stream = iso_stream_alloc(GFP_ATOMIC);
-+		if (likely(stream != NULL)) {
-+			ep->hcpriv = stream;
-+			stream->ep = ep;
-+			iso_stream_init(fotg210, stream, urb->dev, urb->pipe,
-+					urb->interval);
-+		}
-+
-+	/* if dev->ep[epnum] is a QH, hw is set */
-+	} else if (unlikely(stream->hw != NULL)) {
-+		fotg210_dbg(fotg210, "dev %s ep%d%s, not iso??\n",
-+				urb->dev->devpath, epnum,
-+				usb_pipein(urb->pipe) ? "in" : "out");
-+		stream = NULL;
-+	}
-+
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return stream;
-+}
-+
-+/* fotg210_iso_sched ops can be ITD-only or SITD-only */
-+
-+static struct fotg210_iso_sched *iso_sched_alloc(unsigned packets,
-+		gfp_t mem_flags)
-+{
-+	struct fotg210_iso_sched *iso_sched;
-+
-+	iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags);
-+	if (likely(iso_sched != NULL))
-+		INIT_LIST_HEAD(&iso_sched->td_list);
-+
-+	return iso_sched;
-+}
-+
-+static inline void itd_sched_init(struct fotg210_hcd *fotg210,
-+		struct fotg210_iso_sched *iso_sched,
-+		struct fotg210_iso_stream *stream, struct urb *urb)
-+{
-+	unsigned i;
-+	dma_addr_t dma = urb->transfer_dma;
-+
-+	/* how many uframes are needed for these transfers */
-+	iso_sched->span = urb->number_of_packets * stream->interval;
-+
-+	/* figure out per-uframe itd fields that we'll need later
-+	 * when we fit new itds into the schedule.
-+	 */
-+	for (i = 0; i < urb->number_of_packets; i++) {
-+		struct fotg210_iso_packet *uframe = &iso_sched->packet[i];
-+		unsigned length;
-+		dma_addr_t buf;
-+		u32 trans;
-+
-+		length = urb->iso_frame_desc[i].length;
-+		buf = dma + urb->iso_frame_desc[i].offset;
-+
-+		trans = FOTG210_ISOC_ACTIVE;
-+		trans |= buf & 0x0fff;
-+		if (unlikely(((i + 1) == urb->number_of_packets))
-+				&& !(urb->transfer_flags & URB_NO_INTERRUPT))
-+			trans |= FOTG210_ITD_IOC;
-+		trans |= length << 16;
-+		uframe->transaction = cpu_to_hc32(fotg210, trans);
-+
-+		/* might need to cross a buffer page within a uframe */
-+		uframe->bufp = (buf & ~(u64)0x0fff);
-+		buf += length;
-+		if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff))))
-+			uframe->cross = 1;
-+	}
-+}
-+
-+static void iso_sched_free(struct fotg210_iso_stream *stream,
-+		struct fotg210_iso_sched *iso_sched)
-+{
-+	if (!iso_sched)
-+		return;
-+	/* caller must hold fotg210->lock!*/
-+	list_splice(&iso_sched->td_list, &stream->free_list);
-+	kfree(iso_sched);
-+}
-+
-+static int itd_urb_transaction(struct fotg210_iso_stream *stream,
-+		struct fotg210_hcd *fotg210, struct urb *urb, gfp_t mem_flags)
-+{
-+	struct fotg210_itd *itd;
-+	dma_addr_t itd_dma;
-+	int i;
-+	unsigned num_itds;
-+	struct fotg210_iso_sched *sched;
-+	unsigned long flags;
-+
-+	sched = iso_sched_alloc(urb->number_of_packets, mem_flags);
-+	if (unlikely(sched == NULL))
-+		return -ENOMEM;
-+
-+	itd_sched_init(fotg210, sched, stream, urb);
-+
-+	if (urb->interval < 8)
-+		num_itds = 1 + (sched->span + 7) / 8;
-+	else
-+		num_itds = urb->number_of_packets;
-+
-+	/* allocate/init ITDs */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	for (i = 0; i < num_itds; i++) {
-+
-+		/*
-+		 * Use iTDs from the free list, but not iTDs that may
-+		 * still be in use by the hardware.
-+		 */
-+		if (likely(!list_empty(&stream->free_list))) {
-+			itd = list_first_entry(&stream->free_list,
-+					struct fotg210_itd, itd_list);
-+			if (itd->frame == fotg210->now_frame)
-+				goto alloc_itd;
-+			list_del(&itd->itd_list);
-+			itd_dma = itd->itd_dma;
-+		} else {
-+alloc_itd:
-+			spin_unlock_irqrestore(&fotg210->lock, flags);
-+			itd = dma_pool_alloc(fotg210->itd_pool, mem_flags,
-+					&itd_dma);
-+			spin_lock_irqsave(&fotg210->lock, flags);
-+			if (!itd) {
-+				iso_sched_free(stream, sched);
-+				spin_unlock_irqrestore(&fotg210->lock, flags);
-+				return -ENOMEM;
-+			}
-+		}
-+
-+		memset(itd, 0, sizeof(*itd));
-+		itd->itd_dma = itd_dma;
-+		list_add(&itd->itd_list, &sched->td_list);
-+	}
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+	/* temporarily store schedule info in hcpriv */
-+	urb->hcpriv = sched;
-+	urb->error_count = 0;
-+	return 0;
-+}
-+
-+static inline int itd_slot_ok(struct fotg210_hcd *fotg210, u32 mod, u32 uframe,
-+		u8 usecs, u32 period)
-+{
-+	uframe %= period;
-+	do {
-+		/* can't commit more than uframe_periodic_max usec */
-+		if (periodic_usecs(fotg210, uframe >> 3, uframe & 0x7)
-+				> (fotg210->uframe_periodic_max - usecs))
-+			return 0;
-+
-+		/* we know urb->interval is 2^N uframes */
-+		uframe += period;
-+	} while (uframe < mod);
-+	return 1;
-+}
-+
-+/* This scheduler plans almost as far into the future as it has actual
-+ * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
-+ * "as small as possible" to be cache-friendlier.)  That limits the size
-+ * transfers you can stream reliably; avoid more than 64 msec per urb.
-+ * Also avoid queue depths of less than fotg210's worst irq latency (affected
-+ * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
-+ * and other factors); or more than about 230 msec total (for portability,
-+ * given FOTG210_TUNE_FLS and the slop).  Or, write a smarter scheduler!
-+ */
-+
-+#define SCHEDULE_SLOP 80 /* microframes */
-+
-+static int iso_stream_schedule(struct fotg210_hcd *fotg210, struct urb *urb,
-+		struct fotg210_iso_stream *stream)
-+{
-+	u32 now, next, start, period, span;
-+	int status;
-+	unsigned mod = fotg210->periodic_size << 3;
-+	struct fotg210_iso_sched *sched = urb->hcpriv;
-+
-+	period = urb->interval;
-+	span = sched->span;
-+
-+	if (span > mod - SCHEDULE_SLOP) {
-+		fotg210_dbg(fotg210, "iso request %p too long\n", urb);
-+		status = -EFBIG;
-+		goto fail;
-+	}
-+
-+	now = fotg210_read_frame_index(fotg210) & (mod - 1);
-+
-+	/* Typical case: reuse current schedule, stream is still active.
-+	 * Hopefully there are no gaps from the host falling behind
-+	 * (irq delays etc), but if there are we'll take the next
-+	 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
-+	 */
-+	if (likely(!list_empty(&stream->td_list))) {
-+		u32 excess;
-+
-+		/* For high speed devices, allow scheduling within the
-+		 * isochronous scheduling threshold.  For full speed devices
-+		 * and Intel PCI-based controllers, don't (work around for
-+		 * Intel ICH9 bug).
-+		 */
-+		if (!stream->highspeed && fotg210->fs_i_thresh)
-+			next = now + fotg210->i_thresh;
-+		else
-+			next = now;
-+
-+		/* Fell behind (by up to twice the slop amount)?
-+		 * We decide based on the time of the last currently-scheduled
-+		 * slot, not the time of the next available slot.
-+		 */
-+		excess = (stream->next_uframe - period - next) & (mod - 1);
-+		if (excess >= mod - 2 * SCHEDULE_SLOP)
-+			start = next + excess - mod + period *
-+					DIV_ROUND_UP(mod - excess, period);
-+		else
-+			start = next + excess + period;
-+		if (start - now >= mod) {
-+			fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-+					urb, start - now - period, period,
-+					mod);
-+			status = -EFBIG;
-+			goto fail;
-+		}
-+	}
-+
-+	/* need to schedule; when's the next (u)frame we could start?
-+	 * this is bigger than fotg210->i_thresh allows; scheduling itself
-+	 * isn't free, the slop should handle reasonably slow cpus.  it
-+	 * can also help high bandwidth if the dma and irq loads don't
-+	 * jump until after the queue is primed.
-+	 */
-+	else {
-+		int done = 0;
-+
-+		start = SCHEDULE_SLOP + (now & ~0x07);
-+
-+		/* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
-+
-+		/* find a uframe slot with enough bandwidth.
-+		 * Early uframes are more precious because full-speed
-+		 * iso IN transfers can't use late uframes,
-+		 * and therefore they should be allocated last.
-+		 */
-+		next = start;
-+		start += period;
-+		do {
-+			start--;
-+			/* check schedule: enough space? */
-+			if (itd_slot_ok(fotg210, mod, start,
-+					stream->usecs, period))
-+				done = 1;
-+		} while (start > next && !done);
-+
-+		/* no room in the schedule */
-+		if (!done) {
-+			fotg210_dbg(fotg210, "iso resched full %p (now %d max %d)\n",
-+					urb, now, now + mod);
-+			status = -ENOSPC;
-+			goto fail;
-+		}
-+	}
-+
-+	/* Tried to schedule too far into the future? */
-+	if (unlikely(start - now + span - period >=
-+			mod - 2 * SCHEDULE_SLOP)) {
-+		fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-+				urb, start - now, span - period,
-+				mod - 2 * SCHEDULE_SLOP);
-+		status = -EFBIG;
-+		goto fail;
-+	}
-+
-+	stream->next_uframe = start & (mod - 1);
-+
-+	/* report high speed start in uframes; full speed, in frames */
-+	urb->start_frame = stream->next_uframe;
-+	if (!stream->highspeed)
-+		urb->start_frame >>= 3;
-+
-+	/* Make sure scan_isoc() sees these */
-+	if (fotg210->isoc_count == 0)
-+		fotg210->next_frame = now >> 3;
-+	return 0;
-+
-+fail:
-+	iso_sched_free(stream, sched);
-+	urb->hcpriv = NULL;
-+	return status;
-+}
-+
-+static inline void itd_init(struct fotg210_hcd *fotg210,
-+		struct fotg210_iso_stream *stream, struct fotg210_itd *itd)
-+{
-+	int i;
-+
-+	/* it's been recently zeroed */
-+	itd->hw_next = FOTG210_LIST_END(fotg210);
-+	itd->hw_bufp[0] = stream->buf0;
-+	itd->hw_bufp[1] = stream->buf1;
-+	itd->hw_bufp[2] = stream->buf2;
-+
-+	for (i = 0; i < 8; i++)
-+		itd->index[i] = -1;
-+
-+	/* All other fields are filled when scheduling */
-+}
-+
-+static inline void itd_patch(struct fotg210_hcd *fotg210,
-+		struct fotg210_itd *itd, struct fotg210_iso_sched *iso_sched,
-+		unsigned index, u16 uframe)
-+{
-+	struct fotg210_iso_packet *uf = &iso_sched->packet[index];
-+	unsigned pg = itd->pg;
-+
-+	uframe &= 0x07;
-+	itd->index[uframe] = index;
-+
-+	itd->hw_transaction[uframe] = uf->transaction;
-+	itd->hw_transaction[uframe] |= cpu_to_hc32(fotg210, pg << 12);
-+	itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, uf->bufp & ~(u32)0);
-+	itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(uf->bufp >> 32));
-+
-+	/* iso_frame_desc[].offset must be strictly increasing */
-+	if (unlikely(uf->cross)) {
-+		u64 bufp = uf->bufp + 4096;
-+
-+		itd->pg = ++pg;
-+		itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, bufp & ~(u32)0);
-+		itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(bufp >> 32));
-+	}
-+}
-+
-+static inline void itd_link(struct fotg210_hcd *fotg210, unsigned frame,
-+		struct fotg210_itd *itd)
-+{
-+	union fotg210_shadow *prev = &fotg210->pshadow[frame];
-+	__hc32 *hw_p = &fotg210->periodic[frame];
-+	union fotg210_shadow here = *prev;
-+	__hc32 type = 0;
-+
-+	/* skip any iso nodes which might belong to previous microframes */
-+	while (here.ptr) {
-+		type = Q_NEXT_TYPE(fotg210, *hw_p);
-+		if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-+			break;
-+		prev = periodic_next_shadow(fotg210, prev, type);
-+		hw_p = shadow_next_periodic(fotg210, &here, type);
-+		here = *prev;
-+	}
-+
-+	itd->itd_next = here;
-+	itd->hw_next = *hw_p;
-+	prev->itd = itd;
-+	itd->frame = frame;
-+	wmb();
-+	*hw_p = cpu_to_hc32(fotg210, itd->itd_dma | Q_TYPE_ITD);
-+}
-+
-+/* fit urb's itds into the selected schedule slot; activate as needed */
-+static void itd_link_urb(struct fotg210_hcd *fotg210, struct urb *urb,
-+		unsigned mod, struct fotg210_iso_stream *stream)
-+{
-+	int packet;
-+	unsigned next_uframe, uframe, frame;
-+	struct fotg210_iso_sched *iso_sched = urb->hcpriv;
-+	struct fotg210_itd *itd;
-+
-+	next_uframe = stream->next_uframe & (mod - 1);
-+
-+	if (unlikely(list_empty(&stream->td_list))) {
-+		fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-+				+= stream->bandwidth;
-+		fotg210_dbg(fotg210,
-+			"schedule devp %s ep%d%s-iso period %d start %d.%d\n",
-+			urb->dev->devpath, stream->bEndpointAddress & 0x0f,
-+			(stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
-+			urb->interval,
-+			next_uframe >> 3, next_uframe & 0x7);
-+	}
-+
-+	/* fill iTDs uframe by uframe */
-+	for (packet = 0, itd = NULL; packet < urb->number_of_packets;) {
-+		if (itd == NULL) {
-+			/* ASSERT:  we have all necessary itds */
-+
-+			/* ASSERT:  no itds for this endpoint in this uframe */
-+
-+			itd = list_entry(iso_sched->td_list.next,
-+					struct fotg210_itd, itd_list);
-+			list_move_tail(&itd->itd_list, &stream->td_list);
-+			itd->stream = stream;
-+			itd->urb = urb;
-+			itd_init(fotg210, stream, itd);
-+		}
-+
-+		uframe = next_uframe & 0x07;
-+		frame = next_uframe >> 3;
-+
-+		itd_patch(fotg210, itd, iso_sched, packet, uframe);
-+
-+		next_uframe += stream->interval;
-+		next_uframe &= mod - 1;
-+		packet++;
-+
-+		/* link completed itds into the schedule */
-+		if (((next_uframe >> 3) != frame)
-+				|| packet == urb->number_of_packets) {
-+			itd_link(fotg210, frame & (fotg210->periodic_size - 1),
-+					itd);
-+			itd = NULL;
-+		}
-+	}
-+	stream->next_uframe = next_uframe;
-+
-+	/* don't need that schedule data any more */
-+	iso_sched_free(stream, iso_sched);
-+	urb->hcpriv = NULL;
-+
-+	++fotg210->isoc_count;
-+	enable_periodic(fotg210);
-+}
-+
-+#define ISO_ERRS (FOTG210_ISOC_BUF_ERR | FOTG210_ISOC_BABBLE |\
-+		FOTG210_ISOC_XACTERR)
-+
-+/* Process and recycle a completed ITD.  Return true iff its urb completed,
-+ * and hence its completion callback probably added things to the hardware
-+ * schedule.
-+ *
-+ * Note that we carefully avoid recycling this descriptor until after any
-+ * completion callback runs, so that it won't be reused quickly.  That is,
-+ * assuming (a) no more than two urbs per frame on this endpoint, and also
-+ * (b) only this endpoint's completions submit URBs.  It seems some silicon
-+ * corrupts things if you reuse completed descriptors very quickly...
-+ */
-+static bool itd_complete(struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
-+{
-+	struct urb *urb = itd->urb;
-+	struct usb_iso_packet_descriptor *desc;
-+	u32 t;
-+	unsigned uframe;
-+	int urb_index = -1;
-+	struct fotg210_iso_stream *stream = itd->stream;
-+	struct usb_device *dev;
-+	bool retval = false;
-+
-+	/* for each uframe with a packet */
-+	for (uframe = 0; uframe < 8; uframe++) {
-+		if (likely(itd->index[uframe] == -1))
-+			continue;
-+		urb_index = itd->index[uframe];
-+		desc = &urb->iso_frame_desc[urb_index];
-+
-+		t = hc32_to_cpup(fotg210, &itd->hw_transaction[uframe]);
-+		itd->hw_transaction[uframe] = 0;
-+
-+		/* report transfer status */
-+		if (unlikely(t & ISO_ERRS)) {
-+			urb->error_count++;
-+			if (t & FOTG210_ISOC_BUF_ERR)
-+				desc->status = usb_pipein(urb->pipe)
-+					? -ENOSR  /* hc couldn't read */
-+					: -ECOMM; /* hc couldn't write */
-+			else if (t & FOTG210_ISOC_BABBLE)
-+				desc->status = -EOVERFLOW;
-+			else /* (t & FOTG210_ISOC_XACTERR) */
-+				desc->status = -EPROTO;
-+
-+			/* HC need not update length with this error */
-+			if (!(t & FOTG210_ISOC_BABBLE)) {
-+				desc->actual_length = FOTG210_ITD_LENGTH(t);
-+				urb->actual_length += desc->actual_length;
-+			}
-+		} else if (likely((t & FOTG210_ISOC_ACTIVE) == 0)) {
-+			desc->status = 0;
-+			desc->actual_length = FOTG210_ITD_LENGTH(t);
-+			urb->actual_length += desc->actual_length;
-+		} else {
-+			/* URB was too late */
-+			desc->status = -EXDEV;
-+		}
-+	}
-+
-+	/* handle completion now? */
-+	if (likely((urb_index + 1) != urb->number_of_packets))
-+		goto done;
-+
-+	/* ASSERT: it's really the last itd for this urb
-+	 * list_for_each_entry (itd, &stream->td_list, itd_list)
-+	 *	BUG_ON (itd->urb == urb);
-+	 */
-+
-+	/* give urb back to the driver; completion often (re)submits */
-+	dev = urb->dev;
-+	fotg210_urb_done(fotg210, urb, 0);
-+	retval = true;
-+	urb = NULL;
-+
-+	--fotg210->isoc_count;
-+	disable_periodic(fotg210);
-+
-+	if (unlikely(list_is_singular(&stream->td_list))) {
-+		fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-+				-= stream->bandwidth;
-+		fotg210_dbg(fotg210,
-+			"deschedule devp %s ep%d%s-iso\n",
-+			dev->devpath, stream->bEndpointAddress & 0x0f,
-+			(stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
-+	}
-+
-+done:
-+	itd->urb = NULL;
-+
-+	/* Add to the end of the free list for later reuse */
-+	list_move_tail(&itd->itd_list, &stream->free_list);
-+
-+	/* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
-+	if (list_empty(&stream->td_list)) {
-+		list_splice_tail_init(&stream->free_list,
-+				&fotg210->cached_itd_list);
-+		start_free_itds(fotg210);
-+	}
-+
-+	return retval;
-+}
-+
-+static int itd_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-+		gfp_t mem_flags)
-+{
-+	int status = -EINVAL;
-+	unsigned long flags;
-+	struct fotg210_iso_stream *stream;
-+
-+	/* Get iso_stream head */
-+	stream = iso_stream_find(fotg210, urb);
-+	if (unlikely(stream == NULL)) {
-+		fotg210_dbg(fotg210, "can't get iso stream\n");
-+		return -ENOMEM;
-+	}
-+	if (unlikely(urb->interval != stream->interval &&
-+			fotg210_port_speed(fotg210, 0) ==
-+			USB_PORT_STAT_HIGH_SPEED)) {
-+		fotg210_dbg(fotg210, "can't change iso interval %d --> %d\n",
-+				stream->interval, urb->interval);
-+		goto done;
-+	}
-+
-+#ifdef FOTG210_URB_TRACE
-+	fotg210_dbg(fotg210,
-+			"%s %s urb %p ep%d%s len %d, %d pkts %d uframes[%p]\n",
-+			__func__, urb->dev->devpath, urb,
-+			usb_pipeendpoint(urb->pipe),
-+			usb_pipein(urb->pipe) ? "in" : "out",
-+			urb->transfer_buffer_length,
-+			urb->number_of_packets, urb->interval,
-+			stream);
-+#endif
-+
-+	/* allocate ITDs w/o locking anything */
-+	status = itd_urb_transaction(stream, fotg210, urb, mem_flags);
-+	if (unlikely(status < 0)) {
-+		fotg210_dbg(fotg210, "can't init itds\n");
-+		goto done;
-+	}
-+
-+	/* schedule ... need to lock */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+		status = -ESHUTDOWN;
-+		goto done_not_linked;
-+	}
-+	status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+	if (unlikely(status))
-+		goto done_not_linked;
-+	status = iso_stream_schedule(fotg210, urb, stream);
-+	if (likely(status == 0))
-+		itd_link_urb(fotg210, urb, fotg210->periodic_size << 3, stream);
-+	else
-+		usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+done_not_linked:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+done:
-+	return status;
-+}
-+
-+static inline int scan_frame_queue(struct fotg210_hcd *fotg210, unsigned frame,
-+		unsigned now_frame, bool live)
-+{
-+	unsigned uf;
-+	bool modified;
-+	union fotg210_shadow q, *q_p;
-+	__hc32 type, *hw_p;
-+
-+	/* scan each element in frame's queue for completions */
-+	q_p = &fotg210->pshadow[frame];
-+	hw_p = &fotg210->periodic[frame];
-+	q.ptr = q_p->ptr;
-+	type = Q_NEXT_TYPE(fotg210, *hw_p);
-+	modified = false;
-+
-+	while (q.ptr) {
-+		switch (hc32_to_cpu(fotg210, type)) {
-+		case Q_TYPE_ITD:
-+			/* If this ITD is still active, leave it for
-+			 * later processing ... check the next entry.
-+			 * No need to check for activity unless the
-+			 * frame is current.
-+			 */
-+			if (frame == now_frame && live) {
-+				rmb();
-+				for (uf = 0; uf < 8; uf++) {
-+					if (q.itd->hw_transaction[uf] &
-+							ITD_ACTIVE(fotg210))
-+						break;
-+				}
-+				if (uf < 8) {
-+					q_p = &q.itd->itd_next;
-+					hw_p = &q.itd->hw_next;
-+					type = Q_NEXT_TYPE(fotg210,
-+							q.itd->hw_next);
-+					q = *q_p;
-+					break;
-+				}
-+			}
-+
-+			/* Take finished ITDs out of the schedule
-+			 * and process them:  recycle, maybe report
-+			 * URB completion.  HC won't cache the
-+			 * pointer for much longer, if at all.
-+			 */
-+			*q_p = q.itd->itd_next;
-+			*hw_p = q.itd->hw_next;
-+			type = Q_NEXT_TYPE(fotg210, q.itd->hw_next);
-+			wmb();
-+			modified = itd_complete(fotg210, q.itd);
-+			q = *q_p;
-+			break;
-+		default:
-+			fotg210_dbg(fotg210, "corrupt type %d frame %d shadow %p\n",
-+					type, frame, q.ptr);
-+			fallthrough;
-+		case Q_TYPE_QH:
-+		case Q_TYPE_FSTN:
-+			/* End of the iTDs and siTDs */
-+			q.ptr = NULL;
-+			break;
-+		}
-+
-+		/* assume completion callbacks modify the queue */
-+		if (unlikely(modified && fotg210->isoc_count > 0))
-+			return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+static void scan_isoc(struct fotg210_hcd *fotg210)
-+{
-+	unsigned uf, now_frame, frame, ret;
-+	unsigned fmask = fotg210->periodic_size - 1;
-+	bool live;
-+
-+	/*
-+	 * When running, scan from last scan point up to "now"
-+	 * else clean up by scanning everything that's left.
-+	 * Touches as few pages as possible:  cache-friendly.
-+	 */
-+	if (fotg210->rh_state >= FOTG210_RH_RUNNING) {
-+		uf = fotg210_read_frame_index(fotg210);
-+		now_frame = (uf >> 3) & fmask;
-+		live = true;
-+	} else  {
-+		now_frame = (fotg210->next_frame - 1) & fmask;
-+		live = false;
-+	}
-+	fotg210->now_frame = now_frame;
-+
-+	frame = fotg210->next_frame;
-+	for (;;) {
-+		ret = 1;
-+		while (ret != 0)
-+			ret = scan_frame_queue(fotg210, frame,
-+					now_frame, live);
-+
-+		/* Stop when we have reached the current frame */
-+		if (frame == now_frame)
-+			break;
-+		frame = (frame + 1) & fmask;
-+	}
-+	fotg210->next_frame = now_frame;
-+}
-+
-+/* Display / Set uframe_periodic_max
-+ */
-+static ssize_t uframe_periodic_max_show(struct device *dev,
-+		struct device_attribute *attr, char *buf)
-+{
-+	struct fotg210_hcd *fotg210;
-+	int n;
-+
-+	fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-+	n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
-+	return n;
-+}
-+
-+
-+static ssize_t uframe_periodic_max_store(struct device *dev,
-+		struct device_attribute *attr, const char *buf, size_t count)
-+{
-+	struct fotg210_hcd *fotg210;
-+	unsigned uframe_periodic_max;
-+	unsigned frame, uframe;
-+	unsigned short allocated_max;
-+	unsigned long flags;
-+	ssize_t ret;
-+
-+	fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-+	if (kstrtouint(buf, 0, &uframe_periodic_max) < 0)
-+		return -EINVAL;
-+
-+	if (uframe_periodic_max < 100 || uframe_periodic_max >= 125) {
-+		fotg210_info(fotg210, "rejecting invalid request for uframe_periodic_max=%u\n",
-+				uframe_periodic_max);
-+		return -EINVAL;
-+	}
-+
-+	ret = -EINVAL;
-+
-+	/*
-+	 * lock, so that our checking does not race with possible periodic
-+	 * bandwidth allocation through submitting new urbs.
-+	 */
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	/*
-+	 * for request to decrease max periodic bandwidth, we have to check
-+	 * every microframe in the schedule to see whether the decrease is
-+	 * possible.
-+	 */
-+	if (uframe_periodic_max < fotg210->uframe_periodic_max) {
-+		allocated_max = 0;
-+
-+		for (frame = 0; frame < fotg210->periodic_size; ++frame)
-+			for (uframe = 0; uframe < 7; ++uframe)
-+				allocated_max = max(allocated_max,
-+						periodic_usecs(fotg210, frame,
-+						uframe));
-+
-+		if (allocated_max > uframe_periodic_max) {
-+			fotg210_info(fotg210,
-+					"cannot decrease uframe_periodic_max because periodic bandwidth is already allocated (%u > %u)\n",
-+					allocated_max, uframe_periodic_max);
-+			goto out_unlock;
-+		}
-+	}
-+
-+	/* increasing is always ok */
-+
-+	fotg210_info(fotg210,
-+			"setting max periodic bandwidth to %u%% (== %u usec/uframe)\n",
-+			100 * uframe_periodic_max/125, uframe_periodic_max);
-+
-+	if (uframe_periodic_max != 100)
-+		fotg210_warn(fotg210, "max periodic bandwidth set is non-standard\n");
-+
-+	fotg210->uframe_periodic_max = uframe_periodic_max;
-+	ret = count;
-+
-+out_unlock:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return ret;
-+}
-+
-+static DEVICE_ATTR_RW(uframe_periodic_max);
-+
-+static inline int create_sysfs_files(struct fotg210_hcd *fotg210)
-+{
-+	struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
-+
-+	return device_create_file(controller, &dev_attr_uframe_periodic_max);
-+}
-+
-+static inline void remove_sysfs_files(struct fotg210_hcd *fotg210)
-+{
-+	struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
-+
-+	device_remove_file(controller, &dev_attr_uframe_periodic_max);
-+}
-+/* On some systems, leaving remote wakeup enabled prevents system shutdown.
-+ * The firmware seems to think that powering off is a wakeup event!
-+ * This routine turns off remote wakeup and everything else, on all ports.
-+ */
-+static void fotg210_turn_off_all_ports(struct fotg210_hcd *fotg210)
-+{
-+	u32 __iomem *status_reg = &fotg210->regs->port_status;
-+
-+	fotg210_writel(fotg210, PORT_RWC_BITS, status_reg);
-+}
-+
-+/* Halt HC, turn off all ports, and let the BIOS use the companion controllers.
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static void fotg210_silence_controller(struct fotg210_hcd *fotg210)
-+{
-+	fotg210_halt(fotg210);
-+
-+	spin_lock_irq(&fotg210->lock);
-+	fotg210->rh_state = FOTG210_RH_HALTED;
-+	fotg210_turn_off_all_ports(fotg210);
-+	spin_unlock_irq(&fotg210->lock);
-+}
-+
-+/* fotg210_shutdown kick in for silicon on any bus (not just pci, etc).
-+ * This forcibly disables dma and IRQs, helping kexec and other cases
-+ * where the next system software may expect clean state.
-+ */
-+static void fotg210_shutdown(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+	spin_lock_irq(&fotg210->lock);
-+	fotg210->shutdown = true;
-+	fotg210->rh_state = FOTG210_RH_STOPPING;
-+	fotg210->enabled_hrtimer_events = 0;
-+	spin_unlock_irq(&fotg210->lock);
-+
-+	fotg210_silence_controller(fotg210);
-+
-+	hrtimer_cancel(&fotg210->hrtimer);
-+}
-+
-+/* fotg210_work is called from some interrupts, timers, and so on.
-+ * it calls driver completion functions, after dropping fotg210->lock.
-+ */
-+static void fotg210_work(struct fotg210_hcd *fotg210)
-+{
-+	/* another CPU may drop fotg210->lock during a schedule scan while
-+	 * it reports urb completions.  this flag guards against bogus
-+	 * attempts at re-entrant schedule scanning.
-+	 */
-+	if (fotg210->scanning) {
-+		fotg210->need_rescan = true;
-+		return;
-+	}
-+	fotg210->scanning = true;
-+
-+rescan:
-+	fotg210->need_rescan = false;
-+	if (fotg210->async_count)
-+		scan_async(fotg210);
-+	if (fotg210->intr_count > 0)
-+		scan_intr(fotg210);
-+	if (fotg210->isoc_count > 0)
-+		scan_isoc(fotg210);
-+	if (fotg210->need_rescan)
-+		goto rescan;
-+	fotg210->scanning = false;
-+
-+	/* the IO watchdog guards against hardware or driver bugs that
-+	 * misplace IRQs, and should let us run completely without IRQs.
-+	 * such lossage has been observed on both VT6202 and VT8235.
-+	 */
-+	turn_on_io_watchdog(fotg210);
-+}
-+
-+/* Called when the fotg210_hcd module is removed.
-+ */
-+static void fotg210_stop(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+	fotg210_dbg(fotg210, "stop\n");
-+
-+	/* no more interrupts ... */
-+
-+	spin_lock_irq(&fotg210->lock);
-+	fotg210->enabled_hrtimer_events = 0;
-+	spin_unlock_irq(&fotg210->lock);
-+
-+	fotg210_quiesce(fotg210);
-+	fotg210_silence_controller(fotg210);
-+	fotg210_reset(fotg210);
-+
-+	hrtimer_cancel(&fotg210->hrtimer);
-+	remove_sysfs_files(fotg210);
-+	remove_debug_files(fotg210);
-+
-+	/* root hub is shut down separately (first, when possible) */
-+	spin_lock_irq(&fotg210->lock);
-+	end_free_itds(fotg210);
-+	spin_unlock_irq(&fotg210->lock);
-+	fotg210_mem_cleanup(fotg210);
-+
-+#ifdef FOTG210_STATS
-+	fotg210_dbg(fotg210, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
-+			fotg210->stats.normal, fotg210->stats.error,
-+			fotg210->stats.iaa, fotg210->stats.lost_iaa);
-+	fotg210_dbg(fotg210, "complete %ld unlink %ld\n",
-+			fotg210->stats.complete, fotg210->stats.unlink);
-+#endif
-+
-+	dbg_status(fotg210, "fotg210_stop completed",
-+			fotg210_readl(fotg210, &fotg210->regs->status));
-+}
-+
-+/* one-time init, only for memory state */
-+static int hcd_fotg210_init(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	u32 temp;
-+	int retval;
-+	u32 hcc_params;
-+	struct fotg210_qh_hw *hw;
-+
-+	spin_lock_init(&fotg210->lock);
-+
-+	/*
-+	 * keep io watchdog by default, those good HCDs could turn off it later
-+	 */
-+	fotg210->need_io_watchdog = 1;
-+
-+	hrtimer_init(&fotg210->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-+	fotg210->hrtimer.function = fotg210_hrtimer_func;
-+	fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
-+
-+	hcc_params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+	/*
-+	 * by default set standard 80% (== 100 usec/uframe) max periodic
-+	 * bandwidth as required by USB 2.0
-+	 */
-+	fotg210->uframe_periodic_max = 100;
-+
-+	/*
-+	 * hw default: 1K periodic list heads, one per frame.
-+	 * periodic_size can shrink by USBCMD update if hcc_params allows.
-+	 */
-+	fotg210->periodic_size = DEFAULT_I_TDPS;
-+	INIT_LIST_HEAD(&fotg210->intr_qh_list);
-+	INIT_LIST_HEAD(&fotg210->cached_itd_list);
-+
-+	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-+		/* periodic schedule size can be smaller than default */
-+		switch (FOTG210_TUNE_FLS) {
-+		case 0:
-+			fotg210->periodic_size = 1024;
-+			break;
-+		case 1:
-+			fotg210->periodic_size = 512;
-+			break;
-+		case 2:
-+			fotg210->periodic_size = 256;
-+			break;
-+		default:
-+			BUG();
-+		}
-+	}
-+	retval = fotg210_mem_init(fotg210, GFP_KERNEL);
-+	if (retval < 0)
-+		return retval;
-+
-+	/* controllers may cache some of the periodic schedule ... */
-+	fotg210->i_thresh = 2;
-+
-+	/*
-+	 * dedicate a qh for the async ring head, since we couldn't unlink
-+	 * a 'real' qh without stopping the async schedule [4.8].  use it
-+	 * as the 'reclamation list head' too.
-+	 * its dummy is used in hw_alt_next of many tds, to prevent the qh
-+	 * from automatically advancing to the next td after short reads.
-+	 */
-+	fotg210->async->qh_next.qh = NULL;
-+	hw = fotg210->async->hw;
-+	hw->hw_next = QH_NEXT(fotg210, fotg210->async->qh_dma);
-+	hw->hw_info1 = cpu_to_hc32(fotg210, QH_HEAD);
-+	hw->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-+	hw->hw_qtd_next = FOTG210_LIST_END(fotg210);
-+	fotg210->async->qh_state = QH_STATE_LINKED;
-+	hw->hw_alt_next = QTD_NEXT(fotg210, fotg210->async->dummy->qtd_dma);
-+
-+	/* clear interrupt enables, set irq latency */
-+	if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
-+		log2_irq_thresh = 0;
-+	temp = 1 << (16 + log2_irq_thresh);
-+	if (HCC_CANPARK(hcc_params)) {
-+		/* HW default park == 3, on hardware that supports it (like
-+		 * NVidia and ALI silicon), maximizes throughput on the async
-+		 * schedule by avoiding QH fetches between transfers.
-+		 *
-+		 * With fast usb storage devices and NForce2, "park" seems to
-+		 * make problems:  throughput reduction (!), data errors...
-+		 */
-+		if (park) {
-+			park = min_t(unsigned, park, 3);
-+			temp |= CMD_PARK;
-+			temp |= park << 8;
-+		}
-+		fotg210_dbg(fotg210, "park %d\n", park);
-+	}
-+	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-+		/* periodic schedule size can be smaller than default */
-+		temp &= ~(3 << 2);
-+		temp |= (FOTG210_TUNE_FLS << 2);
-+	}
-+	fotg210->command = temp;
-+
-+	/* Accept arbitrarily long scatter-gather lists */
-+	if (!hcd->localmem_pool)
-+		hcd->self.sg_tablesize = ~0;
-+	return 0;
-+}
-+
-+/* start HC running; it's halted, hcd_fotg210_init() has been run (once) */
-+static int fotg210_run(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	u32 temp;
-+
-+	hcd->uses_new_polling = 1;
-+
-+	/* EHCI spec section 4.1 */
-+
-+	fotg210_writel(fotg210, fotg210->periodic_dma,
-+			&fotg210->regs->frame_list);
-+	fotg210_writel(fotg210, (u32)fotg210->async->qh_dma,
-+			&fotg210->regs->async_next);
-+
-+	/*
-+	 * hcc_params controls whether fotg210->regs->segment must (!!!)
-+	 * be used; it constrains QH/ITD/SITD and QTD locations.
-+	 * dma_pool consistent memory always uses segment zero.
-+	 * streaming mappings for I/O buffers, like dma_map_single(),
-+	 * can return segments above 4GB, if the device allows.
-+	 *
-+	 * NOTE:  the dma mask is visible through dev->dma_mask, so
-+	 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
-+	 * Scsi_Host.highmem_io, and so forth.  It's readonly to all
-+	 * host side drivers though.
-+	 */
-+	fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+	/*
-+	 * Philips, Intel, and maybe others need CMD_RUN before the
-+	 * root hub will detect new devices (why?); NEC doesn't
-+	 */
-+	fotg210->command &= ~(CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-+	fotg210->command |= CMD_RUN;
-+	fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+	dbg_cmd(fotg210, "init", fotg210->command);
-+
-+	/*
-+	 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
-+	 * are explicitly handed to companion controller(s), so no TT is
-+	 * involved with the root hub.  (Except where one is integrated,
-+	 * and there's no companion controller unless maybe for USB OTG.)
-+	 *
-+	 * Turning on the CF flag will transfer ownership of all ports
-+	 * from the companions to the EHCI controller.  If any of the
-+	 * companions are in the middle of a port reset at the time, it
-+	 * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
-+	 * guarantees that no resets are in progress.  After we set CF,
-+	 * a short delay lets the hardware catch up; new resets shouldn't
-+	 * be started before the port switching actions could complete.
-+	 */
-+	down_write(&ehci_cf_port_reset_rwsem);
-+	fotg210->rh_state = FOTG210_RH_RUNNING;
-+	/* unblock posted writes */
-+	fotg210_readl(fotg210, &fotg210->regs->command);
-+	usleep_range(5000, 10000);
-+	up_write(&ehci_cf_port_reset_rwsem);
-+	fotg210->last_periodic_enable = ktime_get_real();
-+
-+	temp = HC_VERSION(fotg210,
-+			fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-+	fotg210_info(fotg210,
-+			"USB %x.%x started, EHCI %x.%02x\n",
-+			((fotg210->sbrn & 0xf0) >> 4), (fotg210->sbrn & 0x0f),
-+			temp >> 8, temp & 0xff);
-+
-+	fotg210_writel(fotg210, INTR_MASK,
-+			&fotg210->regs->intr_enable); /* Turn On Interrupts */
-+
-+	/* GRR this is run-once init(), being done every time the HC starts.
-+	 * So long as they're part of class devices, we can't do it init()
-+	 * since the class device isn't created that early.
-+	 */
-+	create_debug_files(fotg210);
-+	create_sysfs_files(fotg210);
-+
-+	return 0;
-+}
-+
-+static int fotg210_setup(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	int retval;
-+
-+	fotg210->regs = (void __iomem *)fotg210->caps +
-+			HC_LENGTH(fotg210,
-+			fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-+	dbg_hcs_params(fotg210, "reset");
-+	dbg_hcc_params(fotg210, "reset");
-+
-+	/* cache this readonly data; minimize chip reads */
-+	fotg210->hcs_params = fotg210_readl(fotg210,
-+			&fotg210->caps->hcs_params);
-+
-+	fotg210->sbrn = HCD_USB2;
-+
-+	/* data structure init */
-+	retval = hcd_fotg210_init(hcd);
-+	if (retval)
-+		return retval;
-+
-+	retval = fotg210_halt(fotg210);
-+	if (retval)
-+		return retval;
-+
-+	fotg210_reset(fotg210);
-+
-+	return 0;
-+}
-+
-+static irqreturn_t fotg210_irq(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	u32 status, masked_status, pcd_status = 0, cmd;
-+	int bh;
-+
-+	spin_lock(&fotg210->lock);
-+
-+	status = fotg210_readl(fotg210, &fotg210->regs->status);
-+
-+	/* e.g. cardbus physical eject */
-+	if (status == ~(u32) 0) {
-+		fotg210_dbg(fotg210, "device removed\n");
-+		goto dead;
-+	}
-+
-+	/*
-+	 * We don't use STS_FLR, but some controllers don't like it to
-+	 * remain on, so mask it out along with the other status bits.
-+	 */
-+	masked_status = status & (INTR_MASK | STS_FLR);
-+
-+	/* Shared IRQ? */
-+	if (!masked_status ||
-+			unlikely(fotg210->rh_state == FOTG210_RH_HALTED)) {
-+		spin_unlock(&fotg210->lock);
-+		return IRQ_NONE;
-+	}
-+
-+	/* clear (just) interrupts */
-+	fotg210_writel(fotg210, masked_status, &fotg210->regs->status);
-+	cmd = fotg210_readl(fotg210, &fotg210->regs->command);
-+	bh = 0;
-+
-+	/* unrequested/ignored: Frame List Rollover */
-+	dbg_status(fotg210, "irq", status);
-+
-+	/* INT, ERR, and IAA interrupt rates can be throttled */
-+
-+	/* normal [4.15.1.2] or error [4.15.1.1] completion */
-+	if (likely((status & (STS_INT|STS_ERR)) != 0)) {
-+		if (likely((status & STS_ERR) == 0))
-+			INCR(fotg210->stats.normal);
-+		else
-+			INCR(fotg210->stats.error);
-+		bh = 1;
-+	}
-+
-+	/* complete the unlinking of some qh [4.15.2.3] */
-+	if (status & STS_IAA) {
-+
-+		/* Turn off the IAA watchdog */
-+		fotg210->enabled_hrtimer_events &=
-+			~BIT(FOTG210_HRTIMER_IAA_WATCHDOG);
-+
-+		/*
-+		 * Mild optimization: Allow another IAAD to reset the
-+		 * hrtimer, if one occurs before the next expiration.
-+		 * In theory we could always cancel the hrtimer, but
-+		 * tests show that about half the time it will be reset
-+		 * for some other event anyway.
-+		 */
-+		if (fotg210->next_hrtimer_event == FOTG210_HRTIMER_IAA_WATCHDOG)
-+			++fotg210->next_hrtimer_event;
-+
-+		/* guard against (alleged) silicon errata */
-+		if (cmd & CMD_IAAD)
-+			fotg210_dbg(fotg210, "IAA with IAAD still set?\n");
-+		if (fotg210->async_iaa) {
-+			INCR(fotg210->stats.iaa);
-+			end_unlink_async(fotg210);
-+		} else
-+			fotg210_dbg(fotg210, "IAA with nothing unlinked?\n");
-+	}
-+
-+	/* remote wakeup [4.3.1] */
-+	if (status & STS_PCD) {
-+		int pstatus;
-+		u32 __iomem *status_reg = &fotg210->regs->port_status;
-+
-+		/* kick root hub later */
-+		pcd_status = status;
-+
-+		/* resume root hub? */
-+		if (fotg210->rh_state == FOTG210_RH_SUSPENDED)
-+			usb_hcd_resume_root_hub(hcd);
-+
-+		pstatus = fotg210_readl(fotg210, status_reg);
-+
-+		if (test_bit(0, &fotg210->suspended_ports) &&
-+				((pstatus & PORT_RESUME) ||
-+				!(pstatus & PORT_SUSPEND)) &&
-+				(pstatus & PORT_PE) &&
-+				fotg210->reset_done[0] == 0) {
-+
-+			/* start 20 msec resume signaling from this port,
-+			 * and make hub_wq collect PORT_STAT_C_SUSPEND to
-+			 * stop that signaling.  Use 5 ms extra for safety,
-+			 * like usb_port_resume() does.
-+			 */
-+			fotg210->reset_done[0] = jiffies + msecs_to_jiffies(25);
-+			set_bit(0, &fotg210->resuming_ports);
-+			fotg210_dbg(fotg210, "port 1 remote wakeup\n");
-+			mod_timer(&hcd->rh_timer, fotg210->reset_done[0]);
-+		}
-+	}
-+
-+	/* PCI errors [4.15.2.4] */
-+	if (unlikely((status & STS_FATAL) != 0)) {
-+		fotg210_err(fotg210, "fatal error\n");
-+		dbg_cmd(fotg210, "fatal", cmd);
-+		dbg_status(fotg210, "fatal", status);
-+dead:
-+		usb_hc_died(hcd);
-+
-+		/* Don't let the controller do anything more */
-+		fotg210->shutdown = true;
-+		fotg210->rh_state = FOTG210_RH_STOPPING;
-+		fotg210->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
-+		fotg210_writel(fotg210, fotg210->command,
-+				&fotg210->regs->command);
-+		fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+		fotg210_handle_controller_death(fotg210);
-+
-+		/* Handle completions when the controller stops */
-+		bh = 0;
-+	}
-+
-+	if (bh)
-+		fotg210_work(fotg210);
-+	spin_unlock(&fotg210->lock);
-+	if (pcd_status)
-+		usb_hcd_poll_rh_status(hcd);
-+	return IRQ_HANDLED;
-+}
-+
-+/* non-error returns are a promise to giveback() the urb later
-+ * we drop ownership so next owner (or urb unlink) can get it
-+ *
-+ * urb + dev is in hcd.self.controller.urb_list
-+ * we're queueing TDs onto software and hardware lists
-+ *
-+ * hcd-specific init for hcpriv hasn't been done yet
-+ *
-+ * NOTE:  control, bulk, and interrupt share the same code to append TDs
-+ * to a (possibly active) QH, and the same QH scanning code.
-+ */
-+static int fotg210_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
-+		gfp_t mem_flags)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	struct list_head qtd_list;
-+
-+	INIT_LIST_HEAD(&qtd_list);
-+
-+	switch (usb_pipetype(urb->pipe)) {
-+	case PIPE_CONTROL:
-+		/* qh_completions() code doesn't handle all the fault cases
-+		 * in multi-TD control transfers.  Even 1KB is rare anyway.
-+		 */
-+		if (urb->transfer_buffer_length > (16 * 1024))
-+			return -EMSGSIZE;
-+		fallthrough;
-+	/* case PIPE_BULK: */
-+	default:
-+		if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-+			return -ENOMEM;
-+		return submit_async(fotg210, urb, &qtd_list, mem_flags);
-+
-+	case PIPE_INTERRUPT:
-+		if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-+			return -ENOMEM;
-+		return intr_submit(fotg210, urb, &qtd_list, mem_flags);
-+
-+	case PIPE_ISOCHRONOUS:
-+		return itd_submit(fotg210, urb, mem_flags);
-+	}
-+}
-+
-+/* remove from hardware lists
-+ * completions normally happen asynchronously
-+ */
-+
-+static int fotg210_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	struct fotg210_qh *qh;
-+	unsigned long flags;
-+	int rc;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-+	if (rc)
-+		goto done;
-+
-+	switch (usb_pipetype(urb->pipe)) {
-+	/* case PIPE_CONTROL: */
-+	/* case PIPE_BULK:*/
-+	default:
-+		qh = (struct fotg210_qh *) urb->hcpriv;
-+		if (!qh)
-+			break;
-+		switch (qh->qh_state) {
-+		case QH_STATE_LINKED:
-+		case QH_STATE_COMPLETING:
-+			start_unlink_async(fotg210, qh);
-+			break;
-+		case QH_STATE_UNLINK:
-+		case QH_STATE_UNLINK_WAIT:
-+			/* already started */
-+			break;
-+		case QH_STATE_IDLE:
-+			/* QH might be waiting for a Clear-TT-Buffer */
-+			qh_completions(fotg210, qh);
-+			break;
-+		}
-+		break;
-+
-+	case PIPE_INTERRUPT:
-+		qh = (struct fotg210_qh *) urb->hcpriv;
-+		if (!qh)
-+			break;
-+		switch (qh->qh_state) {
-+		case QH_STATE_LINKED:
-+		case QH_STATE_COMPLETING:
-+			start_unlink_intr(fotg210, qh);
-+			break;
-+		case QH_STATE_IDLE:
-+			qh_completions(fotg210, qh);
-+			break;
-+		default:
-+			fotg210_dbg(fotg210, "bogus qh %p state %d\n",
-+					qh, qh->qh_state);
-+			goto done;
-+		}
-+		break;
-+
-+	case PIPE_ISOCHRONOUS:
-+		/* itd... */
-+
-+		/* wait till next completion, do it then. */
-+		/* completion irqs can wait up to 1024 msec, */
-+		break;
-+	}
-+done:
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+	return rc;
-+}
-+
-+/* bulk qh holds the data toggle */
-+
-+static void fotg210_endpoint_disable(struct usb_hcd *hcd,
-+		struct usb_host_endpoint *ep)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	unsigned long flags;
-+	struct fotg210_qh *qh, *tmp;
-+
-+	/* ASSERT:  any requests/urbs are being unlinked */
-+	/* ASSERT:  nobody can be submitting urbs for this any more */
-+
-+rescan:
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	qh = ep->hcpriv;
-+	if (!qh)
-+		goto done;
-+
-+	/* endpoints can be iso streams.  for now, we don't
-+	 * accelerate iso completions ... so spin a while.
-+	 */
-+	if (qh->hw == NULL) {
-+		struct fotg210_iso_stream *stream = ep->hcpriv;
-+
-+		if (!list_empty(&stream->td_list))
-+			goto idle_timeout;
-+
-+		/* BUG_ON(!list_empty(&stream->free_list)); */
-+		kfree(stream);
-+		goto done;
-+	}
-+
-+	if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+		qh->qh_state = QH_STATE_IDLE;
-+	switch (qh->qh_state) {
-+	case QH_STATE_LINKED:
-+	case QH_STATE_COMPLETING:
-+		for (tmp = fotg210->async->qh_next.qh;
-+				tmp && tmp != qh;
-+				tmp = tmp->qh_next.qh)
-+			continue;
-+		/* periodic qh self-unlinks on empty, and a COMPLETING qh
-+		 * may already be unlinked.
-+		 */
-+		if (tmp)
-+			start_unlink_async(fotg210, qh);
-+		fallthrough;
-+	case QH_STATE_UNLINK:		/* wait for hw to finish? */
-+	case QH_STATE_UNLINK_WAIT:
-+idle_timeout:
-+		spin_unlock_irqrestore(&fotg210->lock, flags);
-+		schedule_timeout_uninterruptible(1);
-+		goto rescan;
-+	case QH_STATE_IDLE:		/* fully unlinked */
-+		if (qh->clearing_tt)
-+			goto idle_timeout;
-+		if (list_empty(&qh->qtd_list)) {
-+			qh_destroy(fotg210, qh);
-+			break;
-+		}
-+		fallthrough;
-+	default:
-+		/* caller was supposed to have unlinked any requests;
-+		 * that's not our job.  just leak this memory.
-+		 */
-+		fotg210_err(fotg210, "qh %p (#%02x) state %d%s\n",
-+				qh, ep->desc.bEndpointAddress, qh->qh_state,
-+				list_empty(&qh->qtd_list) ? "" : "(has tds)");
-+		break;
-+	}
-+done:
-+	ep->hcpriv = NULL;
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static void fotg210_endpoint_reset(struct usb_hcd *hcd,
-+		struct usb_host_endpoint *ep)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+	struct fotg210_qh *qh;
-+	int eptype = usb_endpoint_type(&ep->desc);
-+	int epnum = usb_endpoint_num(&ep->desc);
-+	int is_out = usb_endpoint_dir_out(&ep->desc);
-+	unsigned long flags;
-+
-+	if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
-+		return;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+	qh = ep->hcpriv;
-+
-+	/* For Bulk and Interrupt endpoints we maintain the toggle state
-+	 * in the hardware; the toggle bits in udev aren't used at all.
-+	 * When an endpoint is reset by usb_clear_halt() we must reset
-+	 * the toggle bit in the QH.
-+	 */
-+	if (qh) {
-+		usb_settoggle(qh->dev, epnum, is_out, 0);
-+		if (!list_empty(&qh->qtd_list)) {
-+			WARN_ONCE(1, "clear_halt for a busy endpoint\n");
-+		} else if (qh->qh_state == QH_STATE_LINKED ||
-+				qh->qh_state == QH_STATE_COMPLETING) {
-+
-+			/* The toggle value in the QH can't be updated
-+			 * while the QH is active.  Unlink it now;
-+			 * re-linking will call qh_refresh().
-+			 */
-+			if (eptype == USB_ENDPOINT_XFER_BULK)
-+				start_unlink_async(fotg210, qh);
-+			else
-+				start_unlink_intr(fotg210, qh);
-+		}
-+	}
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static int fotg210_get_frame(struct usb_hcd *hcd)
-+{
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+	return (fotg210_read_frame_index(fotg210) >> 3) %
-+		fotg210->periodic_size;
-+}
-+
-+/* The EHCI in ChipIdea HDRC cannot be a separate module or device,
-+ * because its registers (and irq) are shared between host/gadget/otg
-+ * functions  and in order to facilitate role switching we cannot
-+ * give the fotg210 driver exclusive access to those.
-+ */
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR(DRIVER_AUTHOR);
-+MODULE_LICENSE("GPL");
-+
-+static const struct hc_driver fotg210_fotg210_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "Faraday USB2.0 Host Controller",
-+	.hcd_priv_size		= sizeof(struct fotg210_hcd),
-+
-+	/*
-+	 * generic hardware linkage
-+	 */
-+	.irq			= fotg210_irq,
-+	.flags			= HCD_MEMORY | HCD_DMA | HCD_USB2,
-+
-+	/*
-+	 * basic lifecycle operations
-+	 */
-+	.reset			= hcd_fotg210_init,
-+	.start			= fotg210_run,
-+	.stop			= fotg210_stop,
-+	.shutdown		= fotg210_shutdown,
-+
-+	/*
-+	 * managing i/o requests and associated device resources
-+	 */
-+	.urb_enqueue		= fotg210_urb_enqueue,
-+	.urb_dequeue		= fotg210_urb_dequeue,
-+	.endpoint_disable	= fotg210_endpoint_disable,
-+	.endpoint_reset		= fotg210_endpoint_reset,
-+
-+	/*
-+	 * scheduling support
-+	 */
-+	.get_frame_number	= fotg210_get_frame,
-+
-+	/*
-+	 * root hub support
-+	 */
-+	.hub_status_data	= fotg210_hub_status_data,
-+	.hub_control		= fotg210_hub_control,
-+	.bus_suspend		= fotg210_bus_suspend,
-+	.bus_resume		= fotg210_bus_resume,
-+
-+	.relinquish_port	= fotg210_relinquish_port,
-+	.port_handed_over	= fotg210_port_handed_over,
-+
-+	.clear_tt_buffer_complete = fotg210_clear_tt_buffer_complete,
-+};
-+
-+static void fotg210_init(struct fotg210_hcd *fotg210)
-+{
-+	u32 value;
-+
-+	iowrite32(GMIR_MDEV_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-+			&fotg210->regs->gmir);
-+
-+	value = ioread32(&fotg210->regs->otgcsr);
-+	value &= ~OTGCSR_A_BUS_DROP;
-+	value |= OTGCSR_A_BUS_REQ;
-+	iowrite32(value, &fotg210->regs->otgcsr);
-+}
-+
-+/*
-+ * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
-+ *
-+ * Allocates basic resources for this USB host controller, and
-+ * then invokes the start() method for the HCD associated with it
-+ * through the hotplug entry's driver_data.
-+ */
-+static int fotg210_hcd_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct usb_hcd *hcd;
-+	struct resource *res;
-+	int irq;
-+	int retval;
-+	struct fotg210_hcd *fotg210;
-+
-+	if (usb_disabled())
-+		return -ENODEV;
-+
-+	pdev->dev.power.power_state = PMSG_ON;
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return irq;
-+
-+	hcd = usb_create_hcd(&fotg210_fotg210_hc_driver, dev,
-+			dev_name(dev));
-+	if (!hcd) {
-+		dev_err(dev, "failed to create hcd\n");
-+		retval = -ENOMEM;
-+		goto fail_create_hcd;
-+	}
-+
-+	hcd->has_tt = 1;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(hcd->regs)) {
-+		retval = PTR_ERR(hcd->regs);
-+		goto failed_put_hcd;
-+	}
-+
-+	hcd->rsrc_start = res->start;
-+	hcd->rsrc_len = resource_size(res);
-+
-+	fotg210 = hcd_to_fotg210(hcd);
-+
-+	fotg210->caps = hcd->regs;
-+
-+	/* It's OK not to supply this clock */
-+	fotg210->pclk = clk_get(dev, "PCLK");
-+	if (!IS_ERR(fotg210->pclk)) {
-+		retval = clk_prepare_enable(fotg210->pclk);
-+		if (retval) {
-+			dev_err(dev, "failed to enable PCLK\n");
-+			goto failed_put_hcd;
-+		}
-+	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-+		/*
-+		 * Percolate deferrals, for anything else,
-+		 * just live without the clocking.
-+		 */
-+		retval = PTR_ERR(fotg210->pclk);
-+		goto failed_dis_clk;
-+	}
-+
-+	retval = fotg210_setup(hcd);
-+	if (retval)
-+		goto failed_dis_clk;
-+
-+	fotg210_init(fotg210);
-+
-+	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+	if (retval) {
-+		dev_err(dev, "failed to add hcd with err %d\n", retval);
-+		goto failed_dis_clk;
-+	}
-+	device_wakeup_enable(hcd->self.controller);
-+	platform_set_drvdata(pdev, hcd);
-+
-+	return retval;
-+
-+failed_dis_clk:
-+	if (!IS_ERR(fotg210->pclk)) {
-+		clk_disable_unprepare(fotg210->pclk);
-+		clk_put(fotg210->pclk);
-+	}
-+failed_put_hcd:
-+	usb_put_hcd(hcd);
-+fail_create_hcd:
-+	dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
-+	return retval;
-+}
-+
-+/*
-+ * fotg210_hcd_remove - shutdown processing for EHCI HCDs
-+ * @dev: USB Host Controller being removed
-+ *
-+ */
-+static int fotg210_hcd_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
-+	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+	if (!IS_ERR(fotg210->pclk)) {
-+		clk_disable_unprepare(fotg210->pclk);
-+		clk_put(fotg210->pclk);
-+	}
-+
-+	usb_remove_hcd(hcd);
-+	usb_put_hcd(hcd);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id fotg210_of_match[] = {
-+	{ .compatible = "faraday,fotg210" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, fotg210_of_match);
-+#endif
-+
-+static struct platform_driver fotg210_hcd_driver = {
-+	.driver = {
-+		.name   = "fotg210-hcd",
-+		.of_match_table = of_match_ptr(fotg210_of_match),
-+	},
-+	.probe  = fotg210_hcd_probe,
-+	.remove = fotg210_hcd_remove,
-+};
-+
-+static int __init fotg210_hcd_init(void)
-+{
-+	int retval = 0;
-+
-+	if (usb_disabled())
-+		return -ENODEV;
-+
-+	set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+	if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
-+			test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
-+		pr_warn("Warning! fotg210_hcd should always be loaded before uhci_hcd and ohci_hcd, not after\n");
-+
-+	pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd\n",
-+			hcd_name, sizeof(struct fotg210_qh),
-+			sizeof(struct fotg210_qtd),
-+			sizeof(struct fotg210_itd));
-+
-+	fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
-+
-+	retval = platform_driver_register(&fotg210_hcd_driver);
-+	if (retval < 0)
-+		goto clean;
-+	return retval;
-+
-+clean:
-+	debugfs_remove(fotg210_debug_root);
-+	fotg210_debug_root = NULL;
-+
-+	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+	return retval;
-+}
-+module_init(fotg210_hcd_init);
-+
-+static void __exit fotg210_hcd_cleanup(void)
-+{
-+	platform_driver_unregister(&fotg210_hcd_driver);
-+	debugfs_remove(fotg210_debug_root);
-+	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+}
-+module_exit(fotg210_hcd_cleanup);
---- a/drivers/usb/gadget/udc/fotg210-udc.c
-+++ /dev/null
-@@ -1,1239 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
--/*
-- * FOTG210 UDC Driver supports Bulk transfer so far
-- *
-- * Copyright (C) 2013 Faraday Technology Corporation
-- *
-- * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- */
--
--#include <linux/dma-mapping.h>
--#include <linux/err.h>
--#include <linux/interrupt.h>
--#include <linux/io.h>
--#include <linux/module.h>
--#include <linux/platform_device.h>
--#include <linux/usb/ch9.h>
--#include <linux/usb/gadget.h>
--
--#include "fotg210.h"
--
--#define	DRIVER_DESC	"FOTG210 USB Device Controller Driver"
--#define	DRIVER_VERSION	"30-April-2013"
--
--static const char udc_name[] = "fotg210_udc";
--static const char * const fotg210_ep_name[] = {
--	"ep0", "ep1", "ep2", "ep3", "ep4"};
--
--static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
--{
--	u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
--
--	if (ep->dir_in)
--		value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
--	else
--		value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
--	iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
--}
--
--static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
--{
--	u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
--
--	if (ep->dir_in)
--		value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
--	else
--		value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
--	iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
--}
--
--static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
--
--	value |= DCFESR_CX_DONE;
--	iowrite32(value, fotg210->reg + FOTG210_DCFESR);
--}
--
--static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
--			int status)
--{
--	list_del_init(&req->queue);
--
--	/* don't modify queue heads during completion callback */
--	if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
--		req->req.status = -ESHUTDOWN;
--	else
--		req->req.status = status;
--
--	spin_unlock(&ep->fotg210->lock);
--	usb_gadget_giveback_request(&ep->ep, &req->req);
--	spin_lock(&ep->fotg210->lock);
--
--	if (ep->epnum) {
--		if (list_empty(&ep->queue))
--			fotg210_disable_fifo_int(ep);
--	} else {
--		fotg210_set_cxdone(ep->fotg210);
--	}
--}
--
--static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
--				u32 dir_in)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 val;
--
--	/* Driver should map an ep to a fifo and then map the fifo
--	 * to the ep. What a brain-damaged design!
--	 */
--
--	/* map a fifo to an ep */
--	val = ioread32(fotg210->reg + FOTG210_EPMAP);
--	val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
--	val |= EPMAP_FIFONO(epnum, dir_in);
--	iowrite32(val, fotg210->reg + FOTG210_EPMAP);
--
--	/* map the ep to the fifo */
--	val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
--	val &= ~FIFOMAP_EPNOMSK(epnum);
--	val |= FIFOMAP_EPNO(epnum);
--	iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
--
--	/* enable fifo */
--	val = ioread32(fotg210->reg + FOTG210_FIFOCF);
--	val |= FIFOCF_FIFO_EN(epnum - 1);
--	iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
--}
--
--static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 val;
--
--	val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
--	val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
--	iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
--}
--
--static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 val;
--
--	val = ioread32(fotg210->reg + FOTG210_FIFOCF);
--	val |= FIFOCF_TYPE(type, epnum - 1);
--	iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
--}
--
--static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
--				u32 dir_in)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 val;
--	u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
--				FOTG210_OUTEPMPSR(epnum);
--
--	val = ioread32(fotg210->reg + offset);
--	val |= INOUTEPMPSR_MPS(mps);
--	iowrite32(val, fotg210->reg + offset);
--}
--
--static int fotg210_config_ep(struct fotg210_ep *ep,
--		     const struct usb_endpoint_descriptor *desc)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--
--	fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
--	fotg210_set_tfrtype(ep, ep->epnum, ep->type);
--	fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
--	fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
--
--	fotg210->ep[ep->epnum] = ep;
--
--	return 0;
--}
--
--static int fotg210_ep_enable(struct usb_ep *_ep,
--			  const struct usb_endpoint_descriptor *desc)
--{
--	struct fotg210_ep *ep;
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--
--	ep->desc = desc;
--	ep->epnum = usb_endpoint_num(desc);
--	ep->type = usb_endpoint_type(desc);
--	ep->dir_in = usb_endpoint_dir_in(desc);
--	ep->ep.maxpacket = usb_endpoint_maxp(desc);
--
--	return fotg210_config_ep(ep, desc);
--}
--
--static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
--{
--	struct fotg210_ep *ep = fotg210->ep[epnum];
--	u32 value;
--	void __iomem *reg;
--
--	reg = (ep->dir_in) ?
--		fotg210->reg + FOTG210_INEPMPSR(epnum) :
--		fotg210->reg + FOTG210_OUTEPMPSR(epnum);
--
--	/* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
--	 *	 bit. Controller wouldn't clear this bit. WTF!!!
--	 */
--
--	value = ioread32(reg);
--	value |= INOUTEPMPSR_RESET_TSEQ;
--	iowrite32(value, reg);
--
--	value = ioread32(reg);
--	value &= ~INOUTEPMPSR_RESET_TSEQ;
--	iowrite32(value, reg);
--}
--
--static int fotg210_ep_release(struct fotg210_ep *ep)
--{
--	if (!ep->epnum)
--		return 0;
--	ep->epnum = 0;
--	ep->stall = 0;
--	ep->wedged = 0;
--
--	fotg210_reset_tseq(ep->fotg210, ep->epnum);
--
--	return 0;
--}
--
--static int fotg210_ep_disable(struct usb_ep *_ep)
--{
--	struct fotg210_ep *ep;
--	struct fotg210_request *req;
--	unsigned long flags;
--
--	BUG_ON(!_ep);
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--
--	while (!list_empty(&ep->queue)) {
--		req = list_entry(ep->queue.next,
--			struct fotg210_request, queue);
--		spin_lock_irqsave(&ep->fotg210->lock, flags);
--		fotg210_done(ep, req, -ECONNRESET);
--		spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--	}
--
--	return fotg210_ep_release(ep);
--}
--
--static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
--						gfp_t gfp_flags)
--{
--	struct fotg210_request *req;
--
--	req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
--	if (!req)
--		return NULL;
--
--	INIT_LIST_HEAD(&req->queue);
--
--	return &req->req;
--}
--
--static void fotg210_ep_free_request(struct usb_ep *_ep,
--					struct usb_request *_req)
--{
--	struct fotg210_request *req;
--
--	req = container_of(_req, struct fotg210_request, req);
--	kfree(req);
--}
--
--static void fotg210_enable_dma(struct fotg210_ep *ep,
--			      dma_addr_t d, u32 len)
--{
--	u32 value;
--	struct fotg210_udc *fotg210 = ep->fotg210;
--
--	/* set transfer length and direction */
--	value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
--	value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
--	value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
--	iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
--
--	/* set device DMA target FIFO number */
--	value = ioread32(fotg210->reg + FOTG210_DMATFNR);
--	if (ep->epnum)
--		value |= DMATFNR_ACC_FN(ep->epnum - 1);
--	else
--		value |= DMATFNR_ACC_CXF;
--	iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
--
--	/* set DMA memory address */
--	iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
--
--	/* enable MDMA_EROR and MDMA_CMPLT interrupt */
--	value = ioread32(fotg210->reg + FOTG210_DMISGR2);
--	value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
--	iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
--
--	/* start DMA */
--	value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
--	value |= DMACPSR1_DMA_START;
--	iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
--}
--
--static void fotg210_disable_dma(struct fotg210_ep *ep)
--{
--	iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
--}
--
--static void fotg210_wait_dma_done(struct fotg210_ep *ep)
--{
--	u32 value;
--
--	do {
--		value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
--		if ((value & DISGR2_USBRST_INT) ||
--		    (value & DISGR2_DMA_ERROR))
--			goto dma_reset;
--	} while (!(value & DISGR2_DMA_CMPLT));
--
--	value &= ~DISGR2_DMA_CMPLT;
--	iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
--	return;
--
--dma_reset:
--	value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
--	value |= DMACPSR1_DMA_ABORT;
--	iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
--
--	/* reset fifo */
--	if (ep->epnum) {
--		value = ioread32(ep->fotg210->reg +
--				FOTG210_FIBCR(ep->epnum - 1));
--		value |= FIBCR_FFRST;
--		iowrite32(value, ep->fotg210->reg +
--				FOTG210_FIBCR(ep->epnum - 1));
--	} else {
--		value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
--		value |= DCFESR_CX_CLR;
--		iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
--	}
--}
--
--static void fotg210_start_dma(struct fotg210_ep *ep,
--			struct fotg210_request *req)
--{
--	struct device *dev = &ep->fotg210->gadget.dev;
--	dma_addr_t d;
--	u8 *buffer;
--	u32 length;
--
--	if (ep->epnum) {
--		if (ep->dir_in) {
--			buffer = req->req.buf;
--			length = req->req.length;
--		} else {
--			buffer = req->req.buf + req->req.actual;
--			length = ioread32(ep->fotg210->reg +
--					FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
--			if (length > req->req.length - req->req.actual)
--				length = req->req.length - req->req.actual;
--		}
--	} else {
--		buffer = req->req.buf + req->req.actual;
--		if (req->req.length - req->req.actual > ep->ep.maxpacket)
--			length = ep->ep.maxpacket;
--		else
--			length = req->req.length - req->req.actual;
--	}
--
--	d = dma_map_single(dev, buffer, length,
--			ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
--
--	if (dma_mapping_error(dev, d)) {
--		pr_err("dma_mapping_error\n");
--		return;
--	}
--
--	fotg210_enable_dma(ep, d, length);
--
--	/* check if dma is done */
--	fotg210_wait_dma_done(ep);
--
--	fotg210_disable_dma(ep);
--
--	/* update actual transfer length */
--	req->req.actual += length;
--
--	dma_unmap_single(dev, d, length, DMA_TO_DEVICE);
--}
--
--static void fotg210_ep0_queue(struct fotg210_ep *ep,
--				struct fotg210_request *req)
--{
--	if (!req->req.length) {
--		fotg210_done(ep, req, 0);
--		return;
--	}
--	if (ep->dir_in) { /* if IN */
--		fotg210_start_dma(ep, req);
--		if (req->req.length == req->req.actual)
--			fotg210_done(ep, req, 0);
--	} else { /* OUT */
--		u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
--
--		value &= ~DMISGR0_MCX_OUT_INT;
--		iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
--	}
--}
--
--static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
--				gfp_t gfp_flags)
--{
--	struct fotg210_ep *ep;
--	struct fotg210_request *req;
--	unsigned long flags;
--	int request = 0;
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--	req = container_of(_req, struct fotg210_request, req);
--
--	if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
--		return -ESHUTDOWN;
--
--	spin_lock_irqsave(&ep->fotg210->lock, flags);
--
--	if (list_empty(&ep->queue))
--		request = 1;
--
--	list_add_tail(&req->queue, &ep->queue);
--
--	req->req.actual = 0;
--	req->req.status = -EINPROGRESS;
--
--	if (!ep->epnum) /* ep0 */
--		fotg210_ep0_queue(ep, req);
--	else if (request && !ep->stall)
--		fotg210_enable_fifo_int(ep);
--
--	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--
--	return 0;
--}
--
--static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
--{
--	struct fotg210_ep *ep;
--	struct fotg210_request *req;
--	unsigned long flags;
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--	req = container_of(_req, struct fotg210_request, req);
--
--	spin_lock_irqsave(&ep->fotg210->lock, flags);
--	if (!list_empty(&ep->queue))
--		fotg210_done(ep, req, -ECONNRESET);
--	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--
--	return 0;
--}
--
--static void fotg210_set_epnstall(struct fotg210_ep *ep)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 value;
--	void __iomem *reg;
--
--	/* check if IN FIFO is empty before stall */
--	if (ep->dir_in) {
--		do {
--			value = ioread32(fotg210->reg + FOTG210_DCFESR);
--		} while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
--	}
--
--	reg = (ep->dir_in) ?
--		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
--		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
--	value = ioread32(reg);
--	value |= INOUTEPMPSR_STL_EP;
--	iowrite32(value, reg);
--}
--
--static void fotg210_clear_epnstall(struct fotg210_ep *ep)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 value;
--	void __iomem *reg;
--
--	reg = (ep->dir_in) ?
--		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
--		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
--	value = ioread32(reg);
--	value &= ~INOUTEPMPSR_STL_EP;
--	iowrite32(value, reg);
--}
--
--static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
--{
--	struct fotg210_ep *ep;
--	struct fotg210_udc *fotg210;
--	unsigned long flags;
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--
--	fotg210 = ep->fotg210;
--
--	spin_lock_irqsave(&ep->fotg210->lock, flags);
--
--	if (value) {
--		fotg210_set_epnstall(ep);
--		ep->stall = 1;
--		if (wedge)
--			ep->wedged = 1;
--	} else {
--		fotg210_reset_tseq(fotg210, ep->epnum);
--		fotg210_clear_epnstall(ep);
--		ep->stall = 0;
--		ep->wedged = 0;
--		if (!list_empty(&ep->queue))
--			fotg210_enable_fifo_int(ep);
--	}
--
--	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--	return 0;
--}
--
--static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
--{
--	return fotg210_set_halt_and_wedge(_ep, value, 0);
--}
--
--static int fotg210_ep_set_wedge(struct usb_ep *_ep)
--{
--	return fotg210_set_halt_and_wedge(_ep, 1, 1);
--}
--
--static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
--{
--}
--
--static const struct usb_ep_ops fotg210_ep_ops = {
--	.enable		= fotg210_ep_enable,
--	.disable	= fotg210_ep_disable,
--
--	.alloc_request	= fotg210_ep_alloc_request,
--	.free_request	= fotg210_ep_free_request,
--
--	.queue		= fotg210_ep_queue,
--	.dequeue	= fotg210_ep_dequeue,
--
--	.set_halt	= fotg210_ep_set_halt,
--	.fifo_flush	= fotg210_ep_fifo_flush,
--	.set_wedge	= fotg210_ep_set_wedge,
--};
--
--static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
--
--	value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
--		   | TX0BYTE_EP4);
--	iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
--}
--
--static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
--
--	value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
--		   | RX0BYTE_EP4);
--	iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
--}
--
--/* read 8-byte setup packet only */
--static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
--		   u8 *buffer)
--{
--	int i = 0;
--	u8 *tmp = buffer;
--	u32 data;
--	u32 length = 8;
--
--	iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
--
--	for (i = (length >> 2); i > 0; i--) {
--		data = ioread32(fotg210->reg + FOTG210_CXPORT);
--		*tmp = data & 0xFF;
--		*(tmp + 1) = (data >> 8) & 0xFF;
--		*(tmp + 2) = (data >> 16) & 0xFF;
--		*(tmp + 3) = (data >> 24) & 0xFF;
--		tmp = tmp + 4;
--	}
--
--	switch (length % 4) {
--	case 1:
--		data = ioread32(fotg210->reg + FOTG210_CXPORT);
--		*tmp = data & 0xFF;
--		break;
--	case 2:
--		data = ioread32(fotg210->reg + FOTG210_CXPORT);
--		*tmp = data & 0xFF;
--		*(tmp + 1) = (data >> 8) & 0xFF;
--		break;
--	case 3:
--		data = ioread32(fotg210->reg + FOTG210_CXPORT);
--		*tmp = data & 0xFF;
--		*(tmp + 1) = (data >> 8) & 0xFF;
--		*(tmp + 2) = (data >> 16) & 0xFF;
--		break;
--	default:
--		break;
--	}
--
--	iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
--}
--
--static void fotg210_set_configuration(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DAR);
--
--	value |= DAR_AFT_CONF;
--	iowrite32(value, fotg210->reg + FOTG210_DAR);
--}
--
--static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DAR);
--
--	value |= (addr & 0x7F);
--	iowrite32(value, fotg210->reg + FOTG210_DAR);
--}
--
--static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
--
--	value |= DCFESR_CX_STL;
--	iowrite32(value, fotg210->reg + FOTG210_DCFESR);
--}
--
--static void fotg210_request_error(struct fotg210_udc *fotg210)
--{
--	fotg210_set_cxstall(fotg210);
--	pr_err("request error!!\n");
--}
--
--static void fotg210_set_address(struct fotg210_udc *fotg210,
--				struct usb_ctrlrequest *ctrl)
--{
--	if (le16_to_cpu(ctrl->wValue) >= 0x0100) {
--		fotg210_request_error(fotg210);
--	} else {
--		fotg210_set_dev_addr(fotg210, le16_to_cpu(ctrl->wValue));
--		fotg210_set_cxdone(fotg210);
--	}
--}
--
--static void fotg210_set_feature(struct fotg210_udc *fotg210,
--				struct usb_ctrlrequest *ctrl)
--{
--	switch (ctrl->bRequestType & USB_RECIP_MASK) {
--	case USB_RECIP_DEVICE:
--		fotg210_set_cxdone(fotg210);
--		break;
--	case USB_RECIP_INTERFACE:
--		fotg210_set_cxdone(fotg210);
--		break;
--	case USB_RECIP_ENDPOINT: {
--		u8 epnum;
--		epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
--		if (epnum)
--			fotg210_set_epnstall(fotg210->ep[epnum]);
--		else
--			fotg210_set_cxstall(fotg210);
--		fotg210_set_cxdone(fotg210);
--		}
--		break;
--	default:
--		fotg210_request_error(fotg210);
--		break;
--	}
--}
--
--static void fotg210_clear_feature(struct fotg210_udc *fotg210,
--				struct usb_ctrlrequest *ctrl)
--{
--	struct fotg210_ep *ep =
--		fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
--
--	switch (ctrl->bRequestType & USB_RECIP_MASK) {
--	case USB_RECIP_DEVICE:
--		fotg210_set_cxdone(fotg210);
--		break;
--	case USB_RECIP_INTERFACE:
--		fotg210_set_cxdone(fotg210);
--		break;
--	case USB_RECIP_ENDPOINT:
--		if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
--			if (ep->wedged) {
--				fotg210_set_cxdone(fotg210);
--				break;
--			}
--			if (ep->stall)
--				fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
--		}
--		fotg210_set_cxdone(fotg210);
--		break;
--	default:
--		fotg210_request_error(fotg210);
--		break;
--	}
--}
--
--static int fotg210_is_epnstall(struct fotg210_ep *ep)
--{
--	struct fotg210_udc *fotg210 = ep->fotg210;
--	u32 value;
--	void __iomem *reg;
--
--	reg = (ep->dir_in) ?
--		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
--		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
--	value = ioread32(reg);
--	return value & INOUTEPMPSR_STL_EP ? 1 : 0;
--}
--
--/* For EP0 requests triggered by this driver (currently GET_STATUS response) */
--static void fotg210_ep0_complete(struct usb_ep *_ep, struct usb_request *req)
--{
--	struct fotg210_ep *ep;
--	struct fotg210_udc *fotg210;
--
--	ep = container_of(_ep, struct fotg210_ep, ep);
--	fotg210 = ep->fotg210;
--
--	if (req->status || req->actual != req->length) {
--		dev_warn(&fotg210->gadget.dev, "EP0 request failed: %d\n", req->status);
--	}
--}
--
--static void fotg210_get_status(struct fotg210_udc *fotg210,
--				struct usb_ctrlrequest *ctrl)
--{
--	u8 epnum;
--
--	switch (ctrl->bRequestType & USB_RECIP_MASK) {
--	case USB_RECIP_DEVICE:
--		fotg210->ep0_data = cpu_to_le16(1 << USB_DEVICE_SELF_POWERED);
--		break;
--	case USB_RECIP_INTERFACE:
--		fotg210->ep0_data = cpu_to_le16(0);
--		break;
--	case USB_RECIP_ENDPOINT:
--		epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
--		if (epnum)
--			fotg210->ep0_data =
--				cpu_to_le16(fotg210_is_epnstall(fotg210->ep[epnum])
--					    << USB_ENDPOINT_HALT);
--		else
--			fotg210_request_error(fotg210);
--		break;
--
--	default:
--		fotg210_request_error(fotg210);
--		return;		/* exit */
--	}
--
--	fotg210->ep0_req->buf = &fotg210->ep0_data;
--	fotg210->ep0_req->length = 2;
--
--	spin_unlock(&fotg210->lock);
--	fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
--	spin_lock(&fotg210->lock);
--}
--
--static int fotg210_setup_packet(struct fotg210_udc *fotg210,
--				struct usb_ctrlrequest *ctrl)
--{
--	u8 *p = (u8 *)ctrl;
--	u8 ret = 0;
--
--	fotg210_rdsetupp(fotg210, p);
--
--	fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
--
--	if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
--		u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
--		fotg210->gadget.speed = value & DMCR_HS_EN ?
--				USB_SPEED_HIGH : USB_SPEED_FULL;
--	}
--
--	/* check request */
--	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
--		switch (ctrl->bRequest) {
--		case USB_REQ_GET_STATUS:
--			fotg210_get_status(fotg210, ctrl);
--			break;
--		case USB_REQ_CLEAR_FEATURE:
--			fotg210_clear_feature(fotg210, ctrl);
--			break;
--		case USB_REQ_SET_FEATURE:
--			fotg210_set_feature(fotg210, ctrl);
--			break;
--		case USB_REQ_SET_ADDRESS:
--			fotg210_set_address(fotg210, ctrl);
--			break;
--		case USB_REQ_SET_CONFIGURATION:
--			fotg210_set_configuration(fotg210);
--			ret = 1;
--			break;
--		default:
--			ret = 1;
--			break;
--		}
--	} else {
--		ret = 1;
--	}
--
--	return ret;
--}
--
--static void fotg210_ep0out(struct fotg210_udc *fotg210)
--{
--	struct fotg210_ep *ep = fotg210->ep[0];
--
--	if (!list_empty(&ep->queue) && !ep->dir_in) {
--		struct fotg210_request *req;
--
--		req = list_first_entry(&ep->queue,
--			struct fotg210_request, queue);
--
--		if (req->req.length)
--			fotg210_start_dma(ep, req);
--
--		if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
--			fotg210_done(ep, req, 0);
--	} else {
--		pr_err("%s : empty queue\n", __func__);
--	}
--}
--
--static void fotg210_ep0in(struct fotg210_udc *fotg210)
--{
--	struct fotg210_ep *ep = fotg210->ep[0];
--
--	if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
--		struct fotg210_request *req;
--
--		req = list_entry(ep->queue.next,
--				struct fotg210_request, queue);
--
--		if (req->req.length)
--			fotg210_start_dma(ep, req);
--
--		if (req->req.actual == req->req.length)
--			fotg210_done(ep, req, 0);
--	} else {
--		fotg210_set_cxdone(fotg210);
--	}
--}
--
--static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
--
--	value &= ~DISGR0_CX_COMABT_INT;
--	iowrite32(value, fotg210->reg + FOTG210_DISGR0);
--}
--
--static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
--{
--	struct fotg210_request *req = list_entry(ep->queue.next,
--					struct fotg210_request, queue);
--
--	if (req->req.length)
--		fotg210_start_dma(ep, req);
--	fotg210_done(ep, req, 0);
--}
--
--static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
--{
--	struct fotg210_request *req = list_entry(ep->queue.next,
--						 struct fotg210_request, queue);
--	int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
--
--	fotg210_start_dma(ep, req);
--
--	/* Complete the request when it's full or a short packet arrived.
--	 * Like other drivers, short_not_ok isn't handled.
--	 */
--
--	if (req->req.length == req->req.actual ||
--	    (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
--		fotg210_done(ep, req, 0);
--}
--
--static irqreturn_t fotg210_irq(int irq, void *_fotg210)
--{
--	struct fotg210_udc *fotg210 = _fotg210;
--	u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
--	u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
--
--	int_grp &= ~int_msk;
--
--	spin_lock(&fotg210->lock);
--
--	if (int_grp & DIGR_INT_G2) {
--		void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
--		u32 int_grp2 = ioread32(reg);
--		u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
--		u32 value;
--
--		int_grp2 &= ~int_msk2;
--
--		if (int_grp2 & DISGR2_USBRST_INT) {
--			usb_gadget_udc_reset(&fotg210->gadget,
--					     fotg210->driver);
--			value = ioread32(reg);
--			value &= ~DISGR2_USBRST_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 udc reset\n");
--		}
--		if (int_grp2 & DISGR2_SUSP_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_SUSP_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 udc suspend\n");
--		}
--		if (int_grp2 & DISGR2_RESM_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_RESM_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 udc resume\n");
--		}
--		if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_ISO_SEQ_ERR_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 iso sequence error\n");
--		}
--		if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_ISO_SEQ_ABORT_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 iso sequence abort\n");
--		}
--		if (int_grp2 & DISGR2_TX0BYTE_INT) {
--			fotg210_clear_tx0byte(fotg210);
--			value = ioread32(reg);
--			value &= ~DISGR2_TX0BYTE_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 transferred 0 byte\n");
--		}
--		if (int_grp2 & DISGR2_RX0BYTE_INT) {
--			fotg210_clear_rx0byte(fotg210);
--			value = ioread32(reg);
--			value &= ~DISGR2_RX0BYTE_INT;
--			iowrite32(value, reg);
--			pr_info("fotg210 received 0 byte\n");
--		}
--		if (int_grp2 & DISGR2_DMA_ERROR) {
--			value = ioread32(reg);
--			value &= ~DISGR2_DMA_ERROR;
--			iowrite32(value, reg);
--		}
--	}
--
--	if (int_grp & DIGR_INT_G0) {
--		void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
--		u32 int_grp0 = ioread32(reg);
--		u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
--		struct usb_ctrlrequest ctrl;
--
--		int_grp0 &= ~int_msk0;
--
--		/* the highest priority in this source register */
--		if (int_grp0 & DISGR0_CX_COMABT_INT) {
--			fotg210_clear_comabt_int(fotg210);
--			pr_info("fotg210 CX command abort\n");
--		}
--
--		if (int_grp0 & DISGR0_CX_SETUP_INT) {
--			if (fotg210_setup_packet(fotg210, &ctrl)) {
--				spin_unlock(&fotg210->lock);
--				if (fotg210->driver->setup(&fotg210->gadget,
--							   &ctrl) < 0)
--					fotg210_set_cxstall(fotg210);
--				spin_lock(&fotg210->lock);
--			}
--		}
--		if (int_grp0 & DISGR0_CX_COMEND_INT)
--			pr_info("fotg210 cmd end\n");
--
--		if (int_grp0 & DISGR0_CX_IN_INT)
--			fotg210_ep0in(fotg210);
--
--		if (int_grp0 & DISGR0_CX_OUT_INT)
--			fotg210_ep0out(fotg210);
--
--		if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
--			fotg210_set_cxstall(fotg210);
--			pr_info("fotg210 ep0 fail\n");
--		}
--	}
--
--	if (int_grp & DIGR_INT_G1) {
--		void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
--		u32 int_grp1 = ioread32(reg);
--		u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
--		int fifo;
--
--		int_grp1 &= ~int_msk1;
--
--		for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
--			if (int_grp1 & DISGR1_IN_INT(fifo))
--				fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
--
--			if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
--			    (int_grp1 & DISGR1_SPK_INT(fifo)))
--				fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
--		}
--	}
--
--	spin_unlock(&fotg210->lock);
--
--	return IRQ_HANDLED;
--}
--
--static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
--{
--	u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
--
--	reg &= ~PHYTMSR_UNPLUG;
--	iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
--}
--
--static int fotg210_udc_start(struct usb_gadget *g,
--		struct usb_gadget_driver *driver)
--{
--	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
--	u32 value;
--
--	/* hook up the driver */
--	fotg210->driver = driver;
--
--	/* enable device global interrupt */
--	value = ioread32(fotg210->reg + FOTG210_DMCR);
--	value |= DMCR_GLINT_EN;
--	iowrite32(value, fotg210->reg + FOTG210_DMCR);
--
--	return 0;
--}
--
--static void fotg210_init(struct fotg210_udc *fotg210)
--{
--	u32 value;
--
--	/* disable global interrupt and set int polarity to active high */
--	iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
--		  fotg210->reg + FOTG210_GMIR);
--
--	/* disable device global interrupt */
--	value = ioread32(fotg210->reg + FOTG210_DMCR);
--	value &= ~DMCR_GLINT_EN;
--	iowrite32(value, fotg210->reg + FOTG210_DMCR);
--
--	/* enable only grp2 irqs we handle */
--	iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
--		    | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
--		    | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
--		  fotg210->reg + FOTG210_DMISGR2);
--
--	/* disable all fifo interrupt */
--	iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
--
--	/* disable cmd end */
--	value = ioread32(fotg210->reg + FOTG210_DMISGR0);
--	value |= DMISGR0_MCX_COMEND;
--	iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
--}
--
--static int fotg210_udc_stop(struct usb_gadget *g)
--{
--	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
--	unsigned long	flags;
--
--	spin_lock_irqsave(&fotg210->lock, flags);
--
--	fotg210_init(fotg210);
--	fotg210->driver = NULL;
--
--	spin_unlock_irqrestore(&fotg210->lock, flags);
--
--	return 0;
--}
--
--static const struct usb_gadget_ops fotg210_gadget_ops = {
--	.udc_start		= fotg210_udc_start,
--	.udc_stop		= fotg210_udc_stop,
--};
--
--static int fotg210_udc_remove(struct platform_device *pdev)
--{
--	struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
--	int i;
--
--	usb_del_gadget_udc(&fotg210->gadget);
--	iounmap(fotg210->reg);
--	free_irq(platform_get_irq(pdev, 0), fotg210);
--
--	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
--	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
--		kfree(fotg210->ep[i]);
--	kfree(fotg210);
--
--	return 0;
--}
--
--static int fotg210_udc_probe(struct platform_device *pdev)
--{
--	struct resource *res, *ires;
--	struct fotg210_udc *fotg210 = NULL;
--	struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
--	int ret = 0;
--	int i;
--
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	if (!res) {
--		pr_err("platform_get_resource error.\n");
--		return -ENODEV;
--	}
--
--	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
--	if (!ires) {
--		pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
--		return -ENODEV;
--	}
--
--	ret = -ENOMEM;
--
--	/* initialize udc */
--	fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
--	if (fotg210 == NULL)
--		goto err;
--
--	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
--		_ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
--		if (_ep[i] == NULL)
--			goto err_alloc;
--		fotg210->ep[i] = _ep[i];
--	}
--
--	fotg210->reg = ioremap(res->start, resource_size(res));
--	if (fotg210->reg == NULL) {
--		pr_err("ioremap error.\n");
--		goto err_alloc;
--	}
--
--	spin_lock_init(&fotg210->lock);
--
--	platform_set_drvdata(pdev, fotg210);
--
--	fotg210->gadget.ops = &fotg210_gadget_ops;
--
--	fotg210->gadget.max_speed = USB_SPEED_HIGH;
--	fotg210->gadget.dev.parent = &pdev->dev;
--	fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
--	fotg210->gadget.name = udc_name;
--
--	INIT_LIST_HEAD(&fotg210->gadget.ep_list);
--
--	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
--		struct fotg210_ep *ep = fotg210->ep[i];
--
--		if (i) {
--			INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
--			list_add_tail(&fotg210->ep[i]->ep.ep_list,
--				      &fotg210->gadget.ep_list);
--		}
--		ep->fotg210 = fotg210;
--		INIT_LIST_HEAD(&ep->queue);
--		ep->ep.name = fotg210_ep_name[i];
--		ep->ep.ops = &fotg210_ep_ops;
--		usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
--
--		if (i == 0) {
--			ep->ep.caps.type_control = true;
--		} else {
--			ep->ep.caps.type_iso = true;
--			ep->ep.caps.type_bulk = true;
--			ep->ep.caps.type_int = true;
--		}
--
--		ep->ep.caps.dir_in = true;
--		ep->ep.caps.dir_out = true;
--	}
--	usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
--	fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
--	INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
--
--	fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
--				GFP_KERNEL);
--	if (fotg210->ep0_req == NULL)
--		goto err_map;
--
--	fotg210->ep0_req->complete = fotg210_ep0_complete;
--
--	fotg210_init(fotg210);
--
--	fotg210_disable_unplug(fotg210);
--
--	ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
--			  udc_name, fotg210);
--	if (ret < 0) {
--		pr_err("request_irq error (%d)\n", ret);
--		goto err_req;
--	}
--
--	ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
--	if (ret)
--		goto err_add_udc;
--
--	dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
--
--	return 0;
--
--err_add_udc:
--	free_irq(ires->start, fotg210);
--
--err_req:
--	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
--
--err_map:
--	iounmap(fotg210->reg);
--
--err_alloc:
--	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
--		kfree(fotg210->ep[i]);
--	kfree(fotg210);
--
--err:
--	return ret;
--}
--
--static struct platform_driver fotg210_driver = {
--	.driver		= {
--		.name =	udc_name,
--	},
--	.probe		= fotg210_udc_probe,
--	.remove		= fotg210_udc_remove,
--};
--
--module_platform_driver(fotg210_driver);
--
--MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
--MODULE_LICENSE("GPL");
--MODULE_DESCRIPTION(DRIVER_DESC);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -0,0 +1,1239 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * FOTG210 UDC Driver supports Bulk transfer so far
-+ *
-+ * Copyright (C) 2013 Faraday Technology Corporation
-+ *
-+ * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ */
-+
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+
-+#include "fotg210-udc.h"
-+
-+#define	DRIVER_DESC	"FOTG210 USB Device Controller Driver"
-+#define	DRIVER_VERSION	"30-April-2013"
-+
-+static const char udc_name[] = "fotg210_udc";
-+static const char * const fotg210_ep_name[] = {
-+	"ep0", "ep1", "ep2", "ep3", "ep4"};
-+
-+static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
-+{
-+	u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-+
-+	if (ep->dir_in)
-+		value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
-+	else
-+		value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-+	iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
-+}
-+
-+static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
-+{
-+	u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-+
-+	if (ep->dir_in)
-+		value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
-+	else
-+		value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-+	iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
-+}
-+
-+static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+
-+	value |= DCFESR_CX_DONE;
-+	iowrite32(value, fotg210->reg + FOTG210_DCFESR);
-+}
-+
-+static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
-+			int status)
-+{
-+	list_del_init(&req->queue);
-+
-+	/* don't modify queue heads during completion callback */
-+	if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-+		req->req.status = -ESHUTDOWN;
-+	else
-+		req->req.status = status;
-+
-+	spin_unlock(&ep->fotg210->lock);
-+	usb_gadget_giveback_request(&ep->ep, &req->req);
-+	spin_lock(&ep->fotg210->lock);
-+
-+	if (ep->epnum) {
-+		if (list_empty(&ep->queue))
-+			fotg210_disable_fifo_int(ep);
-+	} else {
-+		fotg210_set_cxdone(ep->fotg210);
-+	}
-+}
-+
-+static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
-+				u32 dir_in)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 val;
-+
-+	/* Driver should map an ep to a fifo and then map the fifo
-+	 * to the ep. What a brain-damaged design!
-+	 */
-+
-+	/* map a fifo to an ep */
-+	val = ioread32(fotg210->reg + FOTG210_EPMAP);
-+	val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
-+	val |= EPMAP_FIFONO(epnum, dir_in);
-+	iowrite32(val, fotg210->reg + FOTG210_EPMAP);
-+
-+	/* map the ep to the fifo */
-+	val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-+	val &= ~FIFOMAP_EPNOMSK(epnum);
-+	val |= FIFOMAP_EPNO(epnum);
-+	iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
-+
-+	/* enable fifo */
-+	val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-+	val |= FIFOCF_FIFO_EN(epnum - 1);
-+	iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
-+}
-+
-+static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 val;
-+
-+	val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-+	val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
-+	iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
-+}
-+
-+static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 val;
-+
-+	val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-+	val |= FIFOCF_TYPE(type, epnum - 1);
-+	iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
-+}
-+
-+static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
-+				u32 dir_in)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 val;
-+	u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
-+				FOTG210_OUTEPMPSR(epnum);
-+
-+	val = ioread32(fotg210->reg + offset);
-+	val |= INOUTEPMPSR_MPS(mps);
-+	iowrite32(val, fotg210->reg + offset);
-+}
-+
-+static int fotg210_config_ep(struct fotg210_ep *ep,
-+		     const struct usb_endpoint_descriptor *desc)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+
-+	fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
-+	fotg210_set_tfrtype(ep, ep->epnum, ep->type);
-+	fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
-+	fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
-+
-+	fotg210->ep[ep->epnum] = ep;
-+
-+	return 0;
-+}
-+
-+static int fotg210_ep_enable(struct usb_ep *_ep,
-+			  const struct usb_endpoint_descriptor *desc)
-+{
-+	struct fotg210_ep *ep;
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+	ep->desc = desc;
-+	ep->epnum = usb_endpoint_num(desc);
-+	ep->type = usb_endpoint_type(desc);
-+	ep->dir_in = usb_endpoint_dir_in(desc);
-+	ep->ep.maxpacket = usb_endpoint_maxp(desc);
-+
-+	return fotg210_config_ep(ep, desc);
-+}
-+
-+static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
-+{
-+	struct fotg210_ep *ep = fotg210->ep[epnum];
-+	u32 value;
-+	void __iomem *reg;
-+
-+	reg = (ep->dir_in) ?
-+		fotg210->reg + FOTG210_INEPMPSR(epnum) :
-+		fotg210->reg + FOTG210_OUTEPMPSR(epnum);
-+
-+	/* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
-+	 *	 bit. Controller wouldn't clear this bit. WTF!!!
-+	 */
-+
-+	value = ioread32(reg);
-+	value |= INOUTEPMPSR_RESET_TSEQ;
-+	iowrite32(value, reg);
-+
-+	value = ioread32(reg);
-+	value &= ~INOUTEPMPSR_RESET_TSEQ;
-+	iowrite32(value, reg);
-+}
-+
-+static int fotg210_ep_release(struct fotg210_ep *ep)
-+{
-+	if (!ep->epnum)
-+		return 0;
-+	ep->epnum = 0;
-+	ep->stall = 0;
-+	ep->wedged = 0;
-+
-+	fotg210_reset_tseq(ep->fotg210, ep->epnum);
-+
-+	return 0;
-+}
-+
-+static int fotg210_ep_disable(struct usb_ep *_ep)
-+{
-+	struct fotg210_ep *ep;
-+	struct fotg210_request *req;
-+	unsigned long flags;
-+
-+	BUG_ON(!_ep);
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+	while (!list_empty(&ep->queue)) {
-+		req = list_entry(ep->queue.next,
-+			struct fotg210_request, queue);
-+		spin_lock_irqsave(&ep->fotg210->lock, flags);
-+		fotg210_done(ep, req, -ECONNRESET);
-+		spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+	}
-+
-+	return fotg210_ep_release(ep);
-+}
-+
-+static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
-+						gfp_t gfp_flags)
-+{
-+	struct fotg210_request *req;
-+
-+	req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
-+	if (!req)
-+		return NULL;
-+
-+	INIT_LIST_HEAD(&req->queue);
-+
-+	return &req->req;
-+}
-+
-+static void fotg210_ep_free_request(struct usb_ep *_ep,
-+					struct usb_request *_req)
-+{
-+	struct fotg210_request *req;
-+
-+	req = container_of(_req, struct fotg210_request, req);
-+	kfree(req);
-+}
-+
-+static void fotg210_enable_dma(struct fotg210_ep *ep,
-+			      dma_addr_t d, u32 len)
-+{
-+	u32 value;
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+
-+	/* set transfer length and direction */
-+	value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-+	value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
-+	value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
-+	iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
-+
-+	/* set device DMA target FIFO number */
-+	value = ioread32(fotg210->reg + FOTG210_DMATFNR);
-+	if (ep->epnum)
-+		value |= DMATFNR_ACC_FN(ep->epnum - 1);
-+	else
-+		value |= DMATFNR_ACC_CXF;
-+	iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
-+
-+	/* set DMA memory address */
-+	iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
-+
-+	/* enable MDMA_EROR and MDMA_CMPLT interrupt */
-+	value = ioread32(fotg210->reg + FOTG210_DMISGR2);
-+	value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
-+	iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
-+
-+	/* start DMA */
-+	value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-+	value |= DMACPSR1_DMA_START;
-+	iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
-+}
-+
-+static void fotg210_disable_dma(struct fotg210_ep *ep)
-+{
-+	iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
-+}
-+
-+static void fotg210_wait_dma_done(struct fotg210_ep *ep)
-+{
-+	u32 value;
-+
-+	do {
-+		value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
-+		if ((value & DISGR2_USBRST_INT) ||
-+		    (value & DISGR2_DMA_ERROR))
-+			goto dma_reset;
-+	} while (!(value & DISGR2_DMA_CMPLT));
-+
-+	value &= ~DISGR2_DMA_CMPLT;
-+	iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
-+	return;
-+
-+dma_reset:
-+	value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
-+	value |= DMACPSR1_DMA_ABORT;
-+	iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
-+
-+	/* reset fifo */
-+	if (ep->epnum) {
-+		value = ioread32(ep->fotg210->reg +
-+				FOTG210_FIBCR(ep->epnum - 1));
-+		value |= FIBCR_FFRST;
-+		iowrite32(value, ep->fotg210->reg +
-+				FOTG210_FIBCR(ep->epnum - 1));
-+	} else {
-+		value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
-+		value |= DCFESR_CX_CLR;
-+		iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
-+	}
-+}
-+
-+static void fotg210_start_dma(struct fotg210_ep *ep,
-+			struct fotg210_request *req)
-+{
-+	struct device *dev = &ep->fotg210->gadget.dev;
-+	dma_addr_t d;
-+	u8 *buffer;
-+	u32 length;
-+
-+	if (ep->epnum) {
-+		if (ep->dir_in) {
-+			buffer = req->req.buf;
-+			length = req->req.length;
-+		} else {
-+			buffer = req->req.buf + req->req.actual;
-+			length = ioread32(ep->fotg210->reg +
-+					FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
-+			if (length > req->req.length - req->req.actual)
-+				length = req->req.length - req->req.actual;
-+		}
-+	} else {
-+		buffer = req->req.buf + req->req.actual;
-+		if (req->req.length - req->req.actual > ep->ep.maxpacket)
-+			length = ep->ep.maxpacket;
-+		else
-+			length = req->req.length - req->req.actual;
-+	}
-+
-+	d = dma_map_single(dev, buffer, length,
-+			ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
-+
-+	if (dma_mapping_error(dev, d)) {
-+		pr_err("dma_mapping_error\n");
-+		return;
-+	}
-+
-+	fotg210_enable_dma(ep, d, length);
-+
-+	/* check if dma is done */
-+	fotg210_wait_dma_done(ep);
-+
-+	fotg210_disable_dma(ep);
-+
-+	/* update actual transfer length */
-+	req->req.actual += length;
-+
-+	dma_unmap_single(dev, d, length, DMA_TO_DEVICE);
-+}
-+
-+static void fotg210_ep0_queue(struct fotg210_ep *ep,
-+				struct fotg210_request *req)
-+{
-+	if (!req->req.length) {
-+		fotg210_done(ep, req, 0);
-+		return;
-+	}
-+	if (ep->dir_in) { /* if IN */
-+		fotg210_start_dma(ep, req);
-+		if (req->req.length == req->req.actual)
-+			fotg210_done(ep, req, 0);
-+	} else { /* OUT */
-+		u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
-+
-+		value &= ~DMISGR0_MCX_OUT_INT;
-+		iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
-+	}
-+}
-+
-+static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
-+				gfp_t gfp_flags)
-+{
-+	struct fotg210_ep *ep;
-+	struct fotg210_request *req;
-+	unsigned long flags;
-+	int request = 0;
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+	req = container_of(_req, struct fotg210_request, req);
-+
-+	if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-+		return -ESHUTDOWN;
-+
-+	spin_lock_irqsave(&ep->fotg210->lock, flags);
-+
-+	if (list_empty(&ep->queue))
-+		request = 1;
-+
-+	list_add_tail(&req->queue, &ep->queue);
-+
-+	req->req.actual = 0;
-+	req->req.status = -EINPROGRESS;
-+
-+	if (!ep->epnum) /* ep0 */
-+		fotg210_ep0_queue(ep, req);
-+	else if (request && !ep->stall)
-+		fotg210_enable_fifo_int(ep);
-+
-+	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
-+{
-+	struct fotg210_ep *ep;
-+	struct fotg210_request *req;
-+	unsigned long flags;
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+	req = container_of(_req, struct fotg210_request, req);
-+
-+	spin_lock_irqsave(&ep->fotg210->lock, flags);
-+	if (!list_empty(&ep->queue))
-+		fotg210_done(ep, req, -ECONNRESET);
-+	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+
-+	return 0;
-+}
-+
-+static void fotg210_set_epnstall(struct fotg210_ep *ep)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 value;
-+	void __iomem *reg;
-+
-+	/* check if IN FIFO is empty before stall */
-+	if (ep->dir_in) {
-+		do {
-+			value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+		} while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
-+	}
-+
-+	reg = (ep->dir_in) ?
-+		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+	value = ioread32(reg);
-+	value |= INOUTEPMPSR_STL_EP;
-+	iowrite32(value, reg);
-+}
-+
-+static void fotg210_clear_epnstall(struct fotg210_ep *ep)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 value;
-+	void __iomem *reg;
-+
-+	reg = (ep->dir_in) ?
-+		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+	value = ioread32(reg);
-+	value &= ~INOUTEPMPSR_STL_EP;
-+	iowrite32(value, reg);
-+}
-+
-+static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
-+{
-+	struct fotg210_ep *ep;
-+	struct fotg210_udc *fotg210;
-+	unsigned long flags;
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+	fotg210 = ep->fotg210;
-+
-+	spin_lock_irqsave(&ep->fotg210->lock, flags);
-+
-+	if (value) {
-+		fotg210_set_epnstall(ep);
-+		ep->stall = 1;
-+		if (wedge)
-+			ep->wedged = 1;
-+	} else {
-+		fotg210_reset_tseq(fotg210, ep->epnum);
-+		fotg210_clear_epnstall(ep);
-+		ep->stall = 0;
-+		ep->wedged = 0;
-+		if (!list_empty(&ep->queue))
-+			fotg210_enable_fifo_int(ep);
-+	}
-+
-+	spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+	return 0;
-+}
-+
-+static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
-+{
-+	return fotg210_set_halt_and_wedge(_ep, value, 0);
-+}
-+
-+static int fotg210_ep_set_wedge(struct usb_ep *_ep)
-+{
-+	return fotg210_set_halt_and_wedge(_ep, 1, 1);
-+}
-+
-+static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
-+{
-+}
-+
-+static const struct usb_ep_ops fotg210_ep_ops = {
-+	.enable		= fotg210_ep_enable,
-+	.disable	= fotg210_ep_disable,
-+
-+	.alloc_request	= fotg210_ep_alloc_request,
-+	.free_request	= fotg210_ep_free_request,
-+
-+	.queue		= fotg210_ep_queue,
-+	.dequeue	= fotg210_ep_dequeue,
-+
-+	.set_halt	= fotg210_ep_set_halt,
-+	.fifo_flush	= fotg210_ep_fifo_flush,
-+	.set_wedge	= fotg210_ep_set_wedge,
-+};
-+
-+static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
-+
-+	value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
-+		   | TX0BYTE_EP4);
-+	iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
-+}
-+
-+static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
-+
-+	value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
-+		   | RX0BYTE_EP4);
-+	iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
-+}
-+
-+/* read 8-byte setup packet only */
-+static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
-+		   u8 *buffer)
-+{
-+	int i = 0;
-+	u8 *tmp = buffer;
-+	u32 data;
-+	u32 length = 8;
-+
-+	iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
-+
-+	for (i = (length >> 2); i > 0; i--) {
-+		data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+		*tmp = data & 0xFF;
-+		*(tmp + 1) = (data >> 8) & 0xFF;
-+		*(tmp + 2) = (data >> 16) & 0xFF;
-+		*(tmp + 3) = (data >> 24) & 0xFF;
-+		tmp = tmp + 4;
-+	}
-+
-+	switch (length % 4) {
-+	case 1:
-+		data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+		*tmp = data & 0xFF;
-+		break;
-+	case 2:
-+		data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+		*tmp = data & 0xFF;
-+		*(tmp + 1) = (data >> 8) & 0xFF;
-+		break;
-+	case 3:
-+		data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+		*tmp = data & 0xFF;
-+		*(tmp + 1) = (data >> 8) & 0xFF;
-+		*(tmp + 2) = (data >> 16) & 0xFF;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
-+}
-+
-+static void fotg210_set_configuration(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_DAR);
-+
-+	value |= DAR_AFT_CONF;
-+	iowrite32(value, fotg210->reg + FOTG210_DAR);
-+}
-+
-+static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_DAR);
-+
-+	value |= (addr & 0x7F);
-+	iowrite32(value, fotg210->reg + FOTG210_DAR);
-+}
-+
-+static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+
-+	value |= DCFESR_CX_STL;
-+	iowrite32(value, fotg210->reg + FOTG210_DCFESR);
-+}
-+
-+static void fotg210_request_error(struct fotg210_udc *fotg210)
-+{
-+	fotg210_set_cxstall(fotg210);
-+	pr_err("request error!!\n");
-+}
-+
-+static void fotg210_set_address(struct fotg210_udc *fotg210,
-+				struct usb_ctrlrequest *ctrl)
-+{
-+	if (le16_to_cpu(ctrl->wValue) >= 0x0100) {
-+		fotg210_request_error(fotg210);
-+	} else {
-+		fotg210_set_dev_addr(fotg210, le16_to_cpu(ctrl->wValue));
-+		fotg210_set_cxdone(fotg210);
-+	}
-+}
-+
-+static void fotg210_set_feature(struct fotg210_udc *fotg210,
-+				struct usb_ctrlrequest *ctrl)
-+{
-+	switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+	case USB_RECIP_DEVICE:
-+		fotg210_set_cxdone(fotg210);
-+		break;
-+	case USB_RECIP_INTERFACE:
-+		fotg210_set_cxdone(fotg210);
-+		break;
-+	case USB_RECIP_ENDPOINT: {
-+		u8 epnum;
-+		epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
-+		if (epnum)
-+			fotg210_set_epnstall(fotg210->ep[epnum]);
-+		else
-+			fotg210_set_cxstall(fotg210);
-+		fotg210_set_cxdone(fotg210);
-+		}
-+		break;
-+	default:
-+		fotg210_request_error(fotg210);
-+		break;
-+	}
-+}
-+
-+static void fotg210_clear_feature(struct fotg210_udc *fotg210,
-+				struct usb_ctrlrequest *ctrl)
-+{
-+	struct fotg210_ep *ep =
-+		fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
-+
-+	switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+	case USB_RECIP_DEVICE:
-+		fotg210_set_cxdone(fotg210);
-+		break;
-+	case USB_RECIP_INTERFACE:
-+		fotg210_set_cxdone(fotg210);
-+		break;
-+	case USB_RECIP_ENDPOINT:
-+		if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
-+			if (ep->wedged) {
-+				fotg210_set_cxdone(fotg210);
-+				break;
-+			}
-+			if (ep->stall)
-+				fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
-+		}
-+		fotg210_set_cxdone(fotg210);
-+		break;
-+	default:
-+		fotg210_request_error(fotg210);
-+		break;
-+	}
-+}
-+
-+static int fotg210_is_epnstall(struct fotg210_ep *ep)
-+{
-+	struct fotg210_udc *fotg210 = ep->fotg210;
-+	u32 value;
-+	void __iomem *reg;
-+
-+	reg = (ep->dir_in) ?
-+		fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+		fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+	value = ioread32(reg);
-+	return value & INOUTEPMPSR_STL_EP ? 1 : 0;
-+}
-+
-+/* For EP0 requests triggered by this driver (currently GET_STATUS response) */
-+static void fotg210_ep0_complete(struct usb_ep *_ep, struct usb_request *req)
-+{
-+	struct fotg210_ep *ep;
-+	struct fotg210_udc *fotg210;
-+
-+	ep = container_of(_ep, struct fotg210_ep, ep);
-+	fotg210 = ep->fotg210;
-+
-+	if (req->status || req->actual != req->length) {
-+		dev_warn(&fotg210->gadget.dev, "EP0 request failed: %d\n", req->status);
-+	}
-+}
-+
-+static void fotg210_get_status(struct fotg210_udc *fotg210,
-+				struct usb_ctrlrequest *ctrl)
-+{
-+	u8 epnum;
-+
-+	switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+	case USB_RECIP_DEVICE:
-+		fotg210->ep0_data = cpu_to_le16(1 << USB_DEVICE_SELF_POWERED);
-+		break;
-+	case USB_RECIP_INTERFACE:
-+		fotg210->ep0_data = cpu_to_le16(0);
-+		break;
-+	case USB_RECIP_ENDPOINT:
-+		epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
-+		if (epnum)
-+			fotg210->ep0_data =
-+				cpu_to_le16(fotg210_is_epnstall(fotg210->ep[epnum])
-+					    << USB_ENDPOINT_HALT);
-+		else
-+			fotg210_request_error(fotg210);
-+		break;
-+
-+	default:
-+		fotg210_request_error(fotg210);
-+		return;		/* exit */
-+	}
-+
-+	fotg210->ep0_req->buf = &fotg210->ep0_data;
-+	fotg210->ep0_req->length = 2;
-+
-+	spin_unlock(&fotg210->lock);
-+	fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
-+	spin_lock(&fotg210->lock);
-+}
-+
-+static int fotg210_setup_packet(struct fotg210_udc *fotg210,
-+				struct usb_ctrlrequest *ctrl)
-+{
-+	u8 *p = (u8 *)ctrl;
-+	u8 ret = 0;
-+
-+	fotg210_rdsetupp(fotg210, p);
-+
-+	fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
-+
-+	if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
-+		u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
-+		fotg210->gadget.speed = value & DMCR_HS_EN ?
-+				USB_SPEED_HIGH : USB_SPEED_FULL;
-+	}
-+
-+	/* check request */
-+	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
-+		switch (ctrl->bRequest) {
-+		case USB_REQ_GET_STATUS:
-+			fotg210_get_status(fotg210, ctrl);
-+			break;
-+		case USB_REQ_CLEAR_FEATURE:
-+			fotg210_clear_feature(fotg210, ctrl);
-+			break;
-+		case USB_REQ_SET_FEATURE:
-+			fotg210_set_feature(fotg210, ctrl);
-+			break;
-+		case USB_REQ_SET_ADDRESS:
-+			fotg210_set_address(fotg210, ctrl);
-+			break;
-+		case USB_REQ_SET_CONFIGURATION:
-+			fotg210_set_configuration(fotg210);
-+			ret = 1;
-+			break;
-+		default:
-+			ret = 1;
-+			break;
-+		}
-+	} else {
-+		ret = 1;
-+	}
-+
-+	return ret;
-+}
-+
-+static void fotg210_ep0out(struct fotg210_udc *fotg210)
-+{
-+	struct fotg210_ep *ep = fotg210->ep[0];
-+
-+	if (!list_empty(&ep->queue) && !ep->dir_in) {
-+		struct fotg210_request *req;
-+
-+		req = list_first_entry(&ep->queue,
-+			struct fotg210_request, queue);
-+
-+		if (req->req.length)
-+			fotg210_start_dma(ep, req);
-+
-+		if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
-+			fotg210_done(ep, req, 0);
-+	} else {
-+		pr_err("%s : empty queue\n", __func__);
-+	}
-+}
-+
-+static void fotg210_ep0in(struct fotg210_udc *fotg210)
-+{
-+	struct fotg210_ep *ep = fotg210->ep[0];
-+
-+	if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
-+		struct fotg210_request *req;
-+
-+		req = list_entry(ep->queue.next,
-+				struct fotg210_request, queue);
-+
-+		if (req->req.length)
-+			fotg210_start_dma(ep, req);
-+
-+		if (req->req.actual == req->req.length)
-+			fotg210_done(ep, req, 0);
-+	} else {
-+		fotg210_set_cxdone(fotg210);
-+	}
-+}
-+
-+static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
-+{
-+	u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
-+
-+	value &= ~DISGR0_CX_COMABT_INT;
-+	iowrite32(value, fotg210->reg + FOTG210_DISGR0);
-+}
-+
-+static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
-+{
-+	struct fotg210_request *req = list_entry(ep->queue.next,
-+					struct fotg210_request, queue);
-+
-+	if (req->req.length)
-+		fotg210_start_dma(ep, req);
-+	fotg210_done(ep, req, 0);
-+}
-+
-+static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
-+{
-+	struct fotg210_request *req = list_entry(ep->queue.next,
-+						 struct fotg210_request, queue);
-+	int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
-+
-+	fotg210_start_dma(ep, req);
-+
-+	/* Complete the request when it's full or a short packet arrived.
-+	 * Like other drivers, short_not_ok isn't handled.
-+	 */
-+
-+	if (req->req.length == req->req.actual ||
-+	    (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
-+		fotg210_done(ep, req, 0);
-+}
-+
-+static irqreturn_t fotg210_irq(int irq, void *_fotg210)
-+{
-+	struct fotg210_udc *fotg210 = _fotg210;
-+	u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
-+	u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
-+
-+	int_grp &= ~int_msk;
-+
-+	spin_lock(&fotg210->lock);
-+
-+	if (int_grp & DIGR_INT_G2) {
-+		void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
-+		u32 int_grp2 = ioread32(reg);
-+		u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
-+		u32 value;
-+
-+		int_grp2 &= ~int_msk2;
-+
-+		if (int_grp2 & DISGR2_USBRST_INT) {
-+			usb_gadget_udc_reset(&fotg210->gadget,
-+					     fotg210->driver);
-+			value = ioread32(reg);
-+			value &= ~DISGR2_USBRST_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 udc reset\n");
-+		}
-+		if (int_grp2 & DISGR2_SUSP_INT) {
-+			value = ioread32(reg);
-+			value &= ~DISGR2_SUSP_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 udc suspend\n");
-+		}
-+		if (int_grp2 & DISGR2_RESM_INT) {
-+			value = ioread32(reg);
-+			value &= ~DISGR2_RESM_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 udc resume\n");
-+		}
-+		if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
-+			value = ioread32(reg);
-+			value &= ~DISGR2_ISO_SEQ_ERR_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 iso sequence error\n");
-+		}
-+		if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
-+			value = ioread32(reg);
-+			value &= ~DISGR2_ISO_SEQ_ABORT_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 iso sequence abort\n");
-+		}
-+		if (int_grp2 & DISGR2_TX0BYTE_INT) {
-+			fotg210_clear_tx0byte(fotg210);
-+			value = ioread32(reg);
-+			value &= ~DISGR2_TX0BYTE_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 transferred 0 byte\n");
-+		}
-+		if (int_grp2 & DISGR2_RX0BYTE_INT) {
-+			fotg210_clear_rx0byte(fotg210);
-+			value = ioread32(reg);
-+			value &= ~DISGR2_RX0BYTE_INT;
-+			iowrite32(value, reg);
-+			pr_info("fotg210 received 0 byte\n");
-+		}
-+		if (int_grp2 & DISGR2_DMA_ERROR) {
-+			value = ioread32(reg);
-+			value &= ~DISGR2_DMA_ERROR;
-+			iowrite32(value, reg);
-+		}
-+	}
-+
-+	if (int_grp & DIGR_INT_G0) {
-+		void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
-+		u32 int_grp0 = ioread32(reg);
-+		u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
-+		struct usb_ctrlrequest ctrl;
-+
-+		int_grp0 &= ~int_msk0;
-+
-+		/* the highest priority in this source register */
-+		if (int_grp0 & DISGR0_CX_COMABT_INT) {
-+			fotg210_clear_comabt_int(fotg210);
-+			pr_info("fotg210 CX command abort\n");
-+		}
-+
-+		if (int_grp0 & DISGR0_CX_SETUP_INT) {
-+			if (fotg210_setup_packet(fotg210, &ctrl)) {
-+				spin_unlock(&fotg210->lock);
-+				if (fotg210->driver->setup(&fotg210->gadget,
-+							   &ctrl) < 0)
-+					fotg210_set_cxstall(fotg210);
-+				spin_lock(&fotg210->lock);
-+			}
-+		}
-+		if (int_grp0 & DISGR0_CX_COMEND_INT)
-+			pr_info("fotg210 cmd end\n");
-+
-+		if (int_grp0 & DISGR0_CX_IN_INT)
-+			fotg210_ep0in(fotg210);
-+
-+		if (int_grp0 & DISGR0_CX_OUT_INT)
-+			fotg210_ep0out(fotg210);
-+
-+		if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
-+			fotg210_set_cxstall(fotg210);
-+			pr_info("fotg210 ep0 fail\n");
-+		}
-+	}
-+
-+	if (int_grp & DIGR_INT_G1) {
-+		void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
-+		u32 int_grp1 = ioread32(reg);
-+		u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
-+		int fifo;
-+
-+		int_grp1 &= ~int_msk1;
-+
-+		for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
-+			if (int_grp1 & DISGR1_IN_INT(fifo))
-+				fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
-+
-+			if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
-+			    (int_grp1 & DISGR1_SPK_INT(fifo)))
-+				fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
-+		}
-+	}
-+
-+	spin_unlock(&fotg210->lock);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
-+{
-+	u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
-+
-+	reg &= ~PHYTMSR_UNPLUG;
-+	iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
-+}
-+
-+static int fotg210_udc_start(struct usb_gadget *g,
-+		struct usb_gadget_driver *driver)
-+{
-+	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+	u32 value;
-+
-+	/* hook up the driver */
-+	fotg210->driver = driver;
-+
-+	/* enable device global interrupt */
-+	value = ioread32(fotg210->reg + FOTG210_DMCR);
-+	value |= DMCR_GLINT_EN;
-+	iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
-+	return 0;
-+}
-+
-+static void fotg210_init(struct fotg210_udc *fotg210)
-+{
-+	u32 value;
-+
-+	/* disable global interrupt and set int polarity to active high */
-+	iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-+		  fotg210->reg + FOTG210_GMIR);
-+
-+	/* disable device global interrupt */
-+	value = ioread32(fotg210->reg + FOTG210_DMCR);
-+	value &= ~DMCR_GLINT_EN;
-+	iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
-+	/* enable only grp2 irqs we handle */
-+	iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
-+		    | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
-+		    | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
-+		  fotg210->reg + FOTG210_DMISGR2);
-+
-+	/* disable all fifo interrupt */
-+	iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
-+
-+	/* disable cmd end */
-+	value = ioread32(fotg210->reg + FOTG210_DMISGR0);
-+	value |= DMISGR0_MCX_COMEND;
-+	iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
-+}
-+
-+static int fotg210_udc_stop(struct usb_gadget *g)
-+{
-+	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+	unsigned long	flags;
-+
-+	spin_lock_irqsave(&fotg210->lock, flags);
-+
-+	fotg210_init(fotg210);
-+	fotg210->driver = NULL;
-+
-+	spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+	return 0;
-+}
-+
-+static const struct usb_gadget_ops fotg210_gadget_ops = {
-+	.udc_start		= fotg210_udc_start,
-+	.udc_stop		= fotg210_udc_stop,
-+};
-+
-+static int fotg210_udc_remove(struct platform_device *pdev)
-+{
-+	struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
-+	int i;
-+
-+	usb_del_gadget_udc(&fotg210->gadget);
-+	iounmap(fotg210->reg);
-+	free_irq(platform_get_irq(pdev, 0), fotg210);
-+
-+	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
-+	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-+		kfree(fotg210->ep[i]);
-+	kfree(fotg210);
-+
-+	return 0;
-+}
-+
-+static int fotg210_udc_probe(struct platform_device *pdev)
-+{
-+	struct resource *res, *ires;
-+	struct fotg210_udc *fotg210 = NULL;
-+	struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
-+	int ret = 0;
-+	int i;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		pr_err("platform_get_resource error.\n");
-+		return -ENODEV;
-+	}
-+
-+	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (!ires) {
-+		pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
-+		return -ENODEV;
-+	}
-+
-+	ret = -ENOMEM;
-+
-+	/* initialize udc */
-+	fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
-+	if (fotg210 == NULL)
-+		goto err;
-+
-+	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-+		_ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-+		if (_ep[i] == NULL)
-+			goto err_alloc;
-+		fotg210->ep[i] = _ep[i];
-+	}
-+
-+	fotg210->reg = ioremap(res->start, resource_size(res));
-+	if (fotg210->reg == NULL) {
-+		pr_err("ioremap error.\n");
-+		goto err_alloc;
-+	}
-+
-+	spin_lock_init(&fotg210->lock);
-+
-+	platform_set_drvdata(pdev, fotg210);
-+
-+	fotg210->gadget.ops = &fotg210_gadget_ops;
-+
-+	fotg210->gadget.max_speed = USB_SPEED_HIGH;
-+	fotg210->gadget.dev.parent = &pdev->dev;
-+	fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
-+	fotg210->gadget.name = udc_name;
-+
-+	INIT_LIST_HEAD(&fotg210->gadget.ep_list);
-+
-+	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-+		struct fotg210_ep *ep = fotg210->ep[i];
-+
-+		if (i) {
-+			INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
-+			list_add_tail(&fotg210->ep[i]->ep.ep_list,
-+				      &fotg210->gadget.ep_list);
-+		}
-+		ep->fotg210 = fotg210;
-+		INIT_LIST_HEAD(&ep->queue);
-+		ep->ep.name = fotg210_ep_name[i];
-+		ep->ep.ops = &fotg210_ep_ops;
-+		usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
-+
-+		if (i == 0) {
-+			ep->ep.caps.type_control = true;
-+		} else {
-+			ep->ep.caps.type_iso = true;
-+			ep->ep.caps.type_bulk = true;
-+			ep->ep.caps.type_int = true;
-+		}
-+
-+		ep->ep.caps.dir_in = true;
-+		ep->ep.caps.dir_out = true;
-+	}
-+	usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
-+	fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
-+	INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
-+
-+	fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
-+				GFP_KERNEL);
-+	if (fotg210->ep0_req == NULL)
-+		goto err_map;
-+
-+	fotg210->ep0_req->complete = fotg210_ep0_complete;
-+
-+	fotg210_init(fotg210);
-+
-+	fotg210_disable_unplug(fotg210);
-+
-+	ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
-+			  udc_name, fotg210);
-+	if (ret < 0) {
-+		pr_err("request_irq error (%d)\n", ret);
-+		goto err_req;
-+	}
-+
-+	ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
-+	if (ret)
-+		goto err_add_udc;
-+
-+	dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
-+
-+	return 0;
-+
-+err_add_udc:
-+	free_irq(ires->start, fotg210);
-+
-+err_req:
-+	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
-+
-+err_map:
-+	iounmap(fotg210->reg);
-+
-+err_alloc:
-+	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-+		kfree(fotg210->ep[i]);
-+	kfree(fotg210);
-+
-+err:
-+	return ret;
-+}
-+
-+static struct platform_driver fotg210_driver = {
-+	.driver		= {
-+		.name =	udc_name,
-+	},
-+	.probe		= fotg210_udc_probe,
-+	.remove		= fotg210_udc_remove,
-+};
-+
-+module_platform_driver(fotg210_driver);
-+
-+MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION(DRIVER_DESC);
---- a/drivers/usb/gadget/udc/Kconfig
-+++ b/drivers/usb/gadget/udc/Kconfig
-@@ -108,17 +108,6 @@ config USB_FUSB300
- 	help
- 	   Faraday usb device controller FUSB300 driver
- 
--config USB_FOTG210_UDC
--	depends on HAS_DMA
--	tristate "Faraday FOTG210 USB Peripheral Controller"
--	help
--	   Faraday USB2.0 OTG controller which can be configured as
--	   high speed or full speed USB device. This driver supppors
--	   Bulk Transfer so far.
--
--	   Say "y" to link the driver statically, or "m" to build a
--	   dynamically linked module called "fotg210_udc".
--
- config USB_GR_UDC
- 	tristate "Aeroflex Gaisler GRUSBDC USB Peripheral Controller Driver"
- 	depends on HAS_DMA
---- a/drivers/usb/gadget/udc/Makefile
-+++ b/drivers/usb/gadget/udc/Makefile
-@@ -34,7 +34,6 @@ obj-$(CONFIG_USB_EG20T)		+= pch_udc.o
- obj-$(CONFIG_USB_MV_UDC)	+= mv_udc.o
- mv_udc-y			:= mv_udc_core.o
- obj-$(CONFIG_USB_FUSB300)	+= fusb300_udc.o
--obj-$(CONFIG_USB_FOTG210_UDC)	+= fotg210-udc.o
- obj-$(CONFIG_USB_MV_U3D)	+= mv_u3d_core.o
- obj-$(CONFIG_USB_GR_UDC)	+= gr_udc.o
- obj-$(CONFIG_USB_GADGET_XILINX)	+= udc-xilinx.o
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -389,17 +389,6 @@ config USB_ISP1362_HCD
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called isp1362-hcd.
- 
--config USB_FOTG210_HCD
--	tristate "FOTG210 HCD support"
--	depends on USB && HAS_DMA && HAS_IOMEM
--	help
--	  Faraday FOTG210 is an OTG controller which can be configured as
--	  an USB2.0 host. It is designed to meet USB2.0 EHCI specification
--	  with minor modification.
--
--	  To compile this driver as a module, choose M here: the
--	  module will be called fotg210-hcd.
--
- config USB_MAX3421_HCD
- 	tristate "MAX3421 HCD (USB-over-SPI) support"
- 	depends on USB && SPI
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -84,6 +84,5 @@ obj-$(CONFIG_USB_EHCI_FSL)	+= ehci-fsl.o
- obj-$(CONFIG_USB_EHCI_MV)	+= ehci-mv.o
- obj-$(CONFIG_USB_HCD_BCMA)	+= bcma-hcd.o
- obj-$(CONFIG_USB_HCD_SSB)	+= ssb-hcd.o
--obj-$(CONFIG_USB_FOTG210_HCD)	+= fotg210-hcd.o
- obj-$(CONFIG_USB_MAX3421_HCD)	+= max3421-hcd.o
- obj-$(CONFIG_USB_XEN_HCD)	+= xen-hcd.o
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-hcd.h
-@@ -0,0 +1,688 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#ifndef __LINUX_FOTG210_H
-+#define __LINUX_FOTG210_H
-+
-+#include <linux/usb/ehci-dbgp.h>
-+
-+/* definitions used for the EHCI driver */
-+
-+/*
-+ * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
-+ * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
-+ * the host controller implementation.
-+ *
-+ * To facilitate the strongest possible byte-order checking from "sparse"
-+ * and so on, we use __leXX unless that's not practical.
-+ */
-+#define __hc32	__le32
-+#define __hc16	__le16
-+
-+/* statistics can be kept for tuning/monitoring */
-+struct fotg210_stats {
-+	/* irq usage */
-+	unsigned long		normal;
-+	unsigned long		error;
-+	unsigned long		iaa;
-+	unsigned long		lost_iaa;
-+
-+	/* termination of urbs from core */
-+	unsigned long		complete;
-+	unsigned long		unlink;
-+};
-+
-+/* fotg210_hcd->lock guards shared data against other CPUs:
-+ *   fotg210_hcd:	async, unlink, periodic (and shadow), ...
-+ *   usb_host_endpoint: hcpriv
-+ *   fotg210_qh:	qh_next, qtd_list
-+ *   fotg210_qtd:	qtd_list
-+ *
-+ * Also, hold this lock when talking to HC registers or
-+ * when updating hw_* fields in shared qh/qtd/... structures.
-+ */
-+
-+#define	FOTG210_MAX_ROOT_PORTS	1		/* see HCS_N_PORTS */
-+
-+/*
-+ * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
-+ * controller may be doing DMA.  Lower values mean there's no DMA.
-+ */
-+enum fotg210_rh_state {
-+	FOTG210_RH_HALTED,
-+	FOTG210_RH_SUSPENDED,
-+	FOTG210_RH_RUNNING,
-+	FOTG210_RH_STOPPING
-+};
-+
-+/*
-+ * Timer events, ordered by increasing delay length.
-+ * Always update event_delays_ns[] and event_handlers[] (defined in
-+ * ehci-timer.c) in parallel with this list.
-+ */
-+enum fotg210_hrtimer_event {
-+	FOTG210_HRTIMER_POLL_ASS,	/* Poll for async schedule off */
-+	FOTG210_HRTIMER_POLL_PSS,	/* Poll for periodic schedule off */
-+	FOTG210_HRTIMER_POLL_DEAD,	/* Wait for dead controller to stop */
-+	FOTG210_HRTIMER_UNLINK_INTR,	/* Wait for interrupt QH unlink */
-+	FOTG210_HRTIMER_FREE_ITDS,	/* Wait for unused iTDs and siTDs */
-+	FOTG210_HRTIMER_ASYNC_UNLINKS,	/* Unlink empty async QHs */
-+	FOTG210_HRTIMER_IAA_WATCHDOG,	/* Handle lost IAA interrupts */
-+	FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
-+	FOTG210_HRTIMER_DISABLE_ASYNC,	/* Wait to disable async sched */
-+	FOTG210_HRTIMER_IO_WATCHDOG,	/* Check for missing IRQs */
-+	FOTG210_HRTIMER_NUM_EVENTS	/* Must come last */
-+};
-+#define FOTG210_HRTIMER_NO_EVENT	99
-+
-+struct fotg210_hcd {			/* one per controller */
-+	/* timing support */
-+	enum fotg210_hrtimer_event	next_hrtimer_event;
-+	unsigned		enabled_hrtimer_events;
-+	ktime_t			hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
-+	struct hrtimer		hrtimer;
-+
-+	int			PSS_poll_count;
-+	int			ASS_poll_count;
-+	int			died_poll_count;
-+
-+	/* glue to PCI and HCD framework */
-+	struct fotg210_caps __iomem *caps;
-+	struct fotg210_regs __iomem *regs;
-+	struct ehci_dbg_port __iomem *debug;
-+
-+	__u32			hcs_params;	/* cached register copy */
-+	spinlock_t		lock;
-+	enum fotg210_rh_state	rh_state;
-+
-+	/* general schedule support */
-+	bool			scanning:1;
-+	bool			need_rescan:1;
-+	bool			intr_unlinking:1;
-+	bool			async_unlinking:1;
-+	bool			shutdown:1;
-+	struct fotg210_qh		*qh_scan_next;
-+
-+	/* async schedule support */
-+	struct fotg210_qh		*async;
-+	struct fotg210_qh		*dummy;		/* For AMD quirk use */
-+	struct fotg210_qh		*async_unlink;
-+	struct fotg210_qh		*async_unlink_last;
-+	struct fotg210_qh		*async_iaa;
-+	unsigned		async_unlink_cycle;
-+	unsigned		async_count;	/* async activity count */
-+
-+	/* periodic schedule support */
-+#define	DEFAULT_I_TDPS		1024		/* some HCs can do less */
-+	unsigned		periodic_size;
-+	__hc32			*periodic;	/* hw periodic table */
-+	dma_addr_t		periodic_dma;
-+	struct list_head	intr_qh_list;
-+	unsigned		i_thresh;	/* uframes HC might cache */
-+
-+	union fotg210_shadow	*pshadow;	/* mirror hw periodic table */
-+	struct fotg210_qh		*intr_unlink;
-+	struct fotg210_qh		*intr_unlink_last;
-+	unsigned		intr_unlink_cycle;
-+	unsigned		now_frame;	/* frame from HC hardware */
-+	unsigned		next_frame;	/* scan periodic, start here */
-+	unsigned		intr_count;	/* intr activity count */
-+	unsigned		isoc_count;	/* isoc activity count */
-+	unsigned		periodic_count;	/* periodic activity count */
-+	/* max periodic time per uframe */
-+	unsigned		uframe_periodic_max;
-+
-+
-+	/* list of itds completed while now_frame was still active */
-+	struct list_head	cached_itd_list;
-+	struct fotg210_itd	*last_itd_to_free;
-+
-+	/* per root hub port */
-+	unsigned long		reset_done[FOTG210_MAX_ROOT_PORTS];
-+
-+	/* bit vectors (one bit per port)
-+	 * which ports were already suspended at the start of a bus suspend
-+	 */
-+	unsigned long		bus_suspended;
-+
-+	/* which ports are edicated to the companion controller */
-+	unsigned long		companion_ports;
-+
-+	/* which ports are owned by the companion during a bus suspend */
-+	unsigned long		owned_ports;
-+
-+	/* which ports have the change-suspend feature turned on */
-+	unsigned long		port_c_suspend;
-+
-+	/* which ports are suspended */
-+	unsigned long		suspended_ports;
-+
-+	/* which ports have started to resume */
-+	unsigned long		resuming_ports;
-+
-+	/* per-HC memory pools (could be per-bus, but ...) */
-+	struct dma_pool		*qh_pool;	/* qh per active urb */
-+	struct dma_pool		*qtd_pool;	/* one or more per qh */
-+	struct dma_pool		*itd_pool;	/* itd per iso urb */
-+
-+	unsigned		random_frame;
-+	unsigned long		next_statechange;
-+	ktime_t			last_periodic_enable;
-+	u32			command;
-+
-+	/* SILICON QUIRKS */
-+	unsigned		need_io_watchdog:1;
-+	unsigned		fs_i_thresh:1;	/* Intel iso scheduling */
-+
-+	u8			sbrn;		/* packed release number */
-+
-+	/* irq statistics */
-+#ifdef FOTG210_STATS
-+	struct fotg210_stats	stats;
-+#	define INCR(x) ((x)++)
-+#else
-+#	define INCR(x) do {} while (0)
-+#endif
-+
-+	/* silicon clock */
-+	struct clk		*pclk;
-+};
-+
-+/* convert between an HCD pointer and the corresponding FOTG210_HCD */
-+static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
-+{
-+	return (struct fotg210_hcd *)(hcd->hcd_priv);
-+}
-+static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
-+{
-+	return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
-+
-+/* Section 2.2 Host Controller Capability Registers */
-+struct fotg210_caps {
-+	/* these fields are specified as 8 and 16 bit registers,
-+	 * but some hosts can't perform 8 or 16 bit PCI accesses.
-+	 * some hosts treat caplength and hciversion as parts of a 32-bit
-+	 * register, others treat them as two separate registers, this
-+	 * affects the memory map for big endian controllers.
-+	 */
-+	u32		hc_capbase;
-+#define HC_LENGTH(fotg210, p)	(0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
-+				(fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
-+#define HC_VERSION(fotg210, p)	(0xffff&((p) >> /* bits 31:16 / offset 02h */ \
-+				(fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
-+	u32		hcs_params;     /* HCSPARAMS - offset 0x4 */
-+#define HCS_N_PORTS(p)		(((p)>>0)&0xf)	/* bits 3:0, ports on HC */
-+
-+	u32		hcc_params;	/* HCCPARAMS - offset 0x8 */
-+#define HCC_CANPARK(p)		((p)&(1 << 2))  /* true: can park on async qh */
-+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
-+	u8		portroute[8];	 /* nibbles for routing - offset 0xC */
-+};
-+
-+
-+/* Section 2.3 Host Controller Operational Registers */
-+struct fotg210_regs {
-+
-+	/* USBCMD: offset 0x00 */
-+	u32		command;
-+
-+/* EHCI 1.1 addendum */
-+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
-+#define CMD_PARK	(1<<11)		/* enable "park" on async qh */
-+#define CMD_PARK_CNT(c)	(((c)>>8)&3)	/* how many transfers to park for */
-+#define CMD_IAAD	(1<<6)		/* "doorbell" interrupt async advance */
-+#define CMD_ASE		(1<<5)		/* async schedule enable */
-+#define CMD_PSE		(1<<4)		/* periodic schedule enable */
-+/* 3:2 is periodic frame list size */
-+#define CMD_RESET	(1<<1)		/* reset HC not bus */
-+#define CMD_RUN		(1<<0)		/* start/stop HC */
-+
-+	/* USBSTS: offset 0x04 */
-+	u32		status;
-+#define STS_ASS		(1<<15)		/* Async Schedule Status */
-+#define STS_PSS		(1<<14)		/* Periodic Schedule Status */
-+#define STS_RECL	(1<<13)		/* Reclamation */
-+#define STS_HALT	(1<<12)		/* Not running (any reason) */
-+/* some bits reserved */
-+	/* these STS_* flags are also intr_enable bits (USBINTR) */
-+#define STS_IAA		(1<<5)		/* Interrupted on async advance */
-+#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
-+#define STS_FLR		(1<<3)		/* frame list rolled over */
-+#define STS_PCD		(1<<2)		/* port change detect */
-+#define STS_ERR		(1<<1)		/* "error" completion (overflow, ...) */
-+#define STS_INT		(1<<0)		/* "normal" completion (short, ...) */
-+
-+	/* USBINTR: offset 0x08 */
-+	u32		intr_enable;
-+
-+	/* FRINDEX: offset 0x0C */
-+	u32		frame_index;	/* current microframe number */
-+	/* CTRLDSSEGMENT: offset 0x10 */
-+	u32		segment;	/* address bits 63:32 if needed */
-+	/* PERIODICLISTBASE: offset 0x14 */
-+	u32		frame_list;	/* points to periodic list */
-+	/* ASYNCLISTADDR: offset 0x18 */
-+	u32		async_next;	/* address of next async queue head */
-+
-+	u32	reserved1;
-+	/* PORTSC: offset 0x20 */
-+	u32	port_status;
-+/* 31:23 reserved */
-+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))	/* USB 1.1 device */
-+#define PORT_RESET	(1<<8)		/* reset port */
-+#define PORT_SUSPEND	(1<<7)		/* suspend port */
-+#define PORT_RESUME	(1<<6)		/* resume it */
-+#define PORT_PEC	(1<<3)		/* port enable change */
-+#define PORT_PE		(1<<2)		/* port enable */
-+#define PORT_CSC	(1<<1)		/* connect status change */
-+#define PORT_CONNECT	(1<<0)		/* device connected */
-+#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
-+	u32     reserved2[19];
-+
-+	/* OTGCSR: offet 0x70 */
-+	u32     otgcsr;
-+#define OTGCSR_HOST_SPD_TYP     (3 << 22)
-+#define OTGCSR_A_BUS_DROP	(1 << 5)
-+#define OTGCSR_A_BUS_REQ	(1 << 4)
-+
-+	/* OTGISR: offset 0x74 */
-+	u32     otgisr;
-+#define OTGISR_OVC	(1 << 10)
-+
-+	u32     reserved3[15];
-+
-+	/* GMIR: offset 0xB4 */
-+	u32     gmir;
-+#define GMIR_INT_POLARITY	(1 << 3) /*Active High*/
-+#define GMIR_MHC_INT		(1 << 2)
-+#define GMIR_MOTG_INT		(1 << 1)
-+#define GMIR_MDEV_INT	(1 << 0)
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define	QTD_NEXT(fotg210, dma)	cpu_to_hc32(fotg210, (u32)dma)
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.5
-+ * QTD: describe data transfer components (buffer, direction, ...)
-+ * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
-+ *
-+ * These are associated only with "QH" (Queue Head) structures,
-+ * used with control, bulk, and interrupt transfers.
-+ */
-+struct fotg210_qtd {
-+	/* first part defined by EHCI spec */
-+	__hc32			hw_next;	/* see EHCI 3.5.1 */
-+	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
-+	__hc32			hw_token;	/* see EHCI 3.5.3 */
-+#define	QTD_TOGGLE	(1 << 31)	/* data toggle */
-+#define	QTD_LENGTH(tok)	(((tok)>>16) & 0x7fff)
-+#define	QTD_IOC		(1 << 15)	/* interrupt on complete */
-+#define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
-+#define	QTD_PID(tok)	(((tok)>>8) & 0x3)
-+#define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
-+#define	QTD_STS_HALT	(1 << 6)	/* halted on error */
-+#define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
-+#define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
-+#define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
-+#define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
-+#define	QTD_STS_STS	(1 << 1)	/* split transaction state */
-+#define	QTD_STS_PING	(1 << 0)	/* issue PING? */
-+
-+#define ACTIVE_BIT(fotg210)	cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
-+#define HALT_BIT(fotg210)		cpu_to_hc32(fotg210, QTD_STS_HALT)
-+#define STATUS_BIT(fotg210)	cpu_to_hc32(fotg210, QTD_STS_STS)
-+
-+	__hc32			hw_buf[5];	/* see EHCI 3.5.4 */
-+	__hc32			hw_buf_hi[5];	/* Appendix B */
-+
-+	/* the rest is HCD-private */
-+	dma_addr_t		qtd_dma;		/* qtd address */
-+	struct list_head	qtd_list;		/* sw qtd list */
-+	struct urb		*urb;			/* qtd's urb */
-+	size_t			length;			/* length of buffer */
-+} __aligned(32);
-+
-+/* mask NakCnt+T in qh->hw_alt_next */
-+#define QTD_MASK(fotg210)	cpu_to_hc32(fotg210, ~0x1f)
-+
-+#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* type tag from {qh,itd,fstn}->hw_next */
-+#define Q_NEXT_TYPE(fotg210, dma)	((dma) & cpu_to_hc32(fotg210, 3 << 1))
-+
-+/*
-+ * Now the following defines are not converted using the
-+ * cpu_to_le32() macro anymore, since we have to support
-+ * "dynamic" switching between be and le support, so that the driver
-+ * can be used on one system with SoC EHCI controller using big-endian
-+ * descriptors as well as a normal little-endian PCI EHCI controller.
-+ */
-+/* values for that type tag */
-+#define Q_TYPE_ITD	(0 << 1)
-+#define Q_TYPE_QH	(1 << 1)
-+#define Q_TYPE_SITD	(2 << 1)
-+#define Q_TYPE_FSTN	(3 << 1)
-+
-+/* next async queue entry, or pointer to interrupt/periodic QH */
-+#define QH_NEXT(fotg210, dma) \
-+	(cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
-+
-+/* for periodic/async schedules and qtd lists, mark end of list */
-+#define FOTG210_LIST_END(fotg210) \
-+	cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
-+
-+/*
-+ * Entries in periodic shadow table are pointers to one of four kinds
-+ * of data structure.  That's dictated by the hardware; a type tag is
-+ * encoded in the low bits of the hardware's periodic schedule.  Use
-+ * Q_NEXT_TYPE to get the tag.
-+ *
-+ * For entries in the async schedule, the type tag always says "qh".
-+ */
-+union fotg210_shadow {
-+	struct fotg210_qh	*qh;		/* Q_TYPE_QH */
-+	struct fotg210_itd	*itd;		/* Q_TYPE_ITD */
-+	struct fotg210_fstn	*fstn;		/* Q_TYPE_FSTN */
-+	__hc32			*hw_next;	/* (all types) */
-+	void			*ptr;
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.6
-+ * QH: describes control/bulk/interrupt endpoints
-+ * See Fig 3-7 "Queue Head Structure Layout".
-+ *
-+ * These appear in both the async and (for interrupt) periodic schedules.
-+ */
-+
-+/* first part defined by EHCI spec */
-+struct fotg210_qh_hw {
-+	__hc32			hw_next;	/* see EHCI 3.6.1 */
-+	__hc32			hw_info1;	/* see EHCI 3.6.2 */
-+#define	QH_CONTROL_EP	(1 << 27)	/* FS/LS control endpoint */
-+#define	QH_HEAD		(1 << 15)	/* Head of async reclamation list */
-+#define	QH_TOGGLE_CTL	(1 << 14)	/* Data toggle control */
-+#define	QH_HIGH_SPEED	(2 << 12)	/* Endpoint speed */
-+#define	QH_LOW_SPEED	(1 << 12)
-+#define	QH_FULL_SPEED	(0 << 12)
-+#define	QH_INACTIVATE	(1 << 7)	/* Inactivate on next transaction */
-+	__hc32			hw_info2;	/* see EHCI 3.6.2 */
-+#define	QH_SMASK	0x000000ff
-+#define	QH_CMASK	0x0000ff00
-+#define	QH_HUBADDR	0x007f0000
-+#define	QH_HUBPORT	0x3f800000
-+#define	QH_MULT		0xc0000000
-+	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
-+
-+	/* qtd overlay (hardware parts of a struct fotg210_qtd) */
-+	__hc32			hw_qtd_next;
-+	__hc32			hw_alt_next;
-+	__hc32			hw_token;
-+	__hc32			hw_buf[5];
-+	__hc32			hw_buf_hi[5];
-+} __aligned(32);
-+
-+struct fotg210_qh {
-+	struct fotg210_qh_hw	*hw;		/* Must come first */
-+	/* the rest is HCD-private */
-+	dma_addr_t		qh_dma;		/* address of qh */
-+	union fotg210_shadow	qh_next;	/* ptr to qh; or periodic */
-+	struct list_head	qtd_list;	/* sw qtd list */
-+	struct list_head	intr_node;	/* list of intr QHs */
-+	struct fotg210_qtd	*dummy;
-+	struct fotg210_qh	*unlink_next;	/* next on unlink list */
-+
-+	unsigned		unlink_cycle;
-+
-+	u8			needs_rescan;	/* Dequeue during giveback */
-+	u8			qh_state;
-+#define	QH_STATE_LINKED		1		/* HC sees this */
-+#define	QH_STATE_UNLINK		2		/* HC may still see this */
-+#define	QH_STATE_IDLE		3		/* HC doesn't see this */
-+#define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on unlink q */
-+#define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
-+
-+	u8			xacterrs;	/* XactErr retry counter */
-+#define	QH_XACTERR_MAX		32		/* XactErr retry limit */
-+
-+	/* periodic schedule info */
-+	u8			usecs;		/* intr bandwidth */
-+	u8			gap_uf;		/* uframes split/csplit gap */
-+	u8			c_usecs;	/* ... split completion bw */
-+	u16			tt_usecs;	/* tt downstream bandwidth */
-+	unsigned short		period;		/* polling interval */
-+	unsigned short		start;		/* where polling starts */
-+#define NO_FRAME ((unsigned short)~0)			/* pick new start */
-+
-+	struct usb_device	*dev;		/* access to TT */
-+	unsigned		is_out:1;	/* bulk or intr OUT */
-+	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* description of one iso transaction (up to 3 KB data if highspeed) */
-+struct fotg210_iso_packet {
-+	/* These will be copied to iTD when scheduling */
-+	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
-+	__hc32			transaction;	/* itd->hw_transaction[i] |= */
-+	u8			cross;		/* buf crosses pages */
-+	/* for full speed OUT splits */
-+	u32			buf1;
-+};
-+
-+/* temporary schedule data for packets from iso urbs (both speeds)
-+ * each packet is one logical usb transaction to the device (not TT),
-+ * beginning at stream->next_uframe
-+ */
-+struct fotg210_iso_sched {
-+	struct list_head	td_list;
-+	unsigned		span;
-+	struct fotg210_iso_packet	packet[];
-+};
-+
-+/*
-+ * fotg210_iso_stream - groups all (s)itds for this endpoint.
-+ * acts like a qh would, if EHCI had them for ISO.
-+ */
-+struct fotg210_iso_stream {
-+	/* first field matches fotg210_hq, but is NULL */
-+	struct fotg210_qh_hw	*hw;
-+
-+	u8			bEndpointAddress;
-+	u8			highspeed;
-+	struct list_head	td_list;	/* queued itds */
-+	struct list_head	free_list;	/* list of unused itds */
-+	struct usb_device	*udev;
-+	struct usb_host_endpoint *ep;
-+
-+	/* output of (re)scheduling */
-+	int			next_uframe;
-+	__hc32			splits;
-+
-+	/* the rest is derived from the endpoint descriptor,
-+	 * trusting urb->interval == f(epdesc->bInterval) and
-+	 * including the extra info for hw_bufp[0..2]
-+	 */
-+	u8			usecs, c_usecs;
-+	u16			interval;
-+	u16			tt_usecs;
-+	u16			maxp;
-+	u16			raw_mask;
-+	unsigned		bandwidth;
-+
-+	/* This is used to initialize iTD's hw_bufp fields */
-+	__hc32			buf0;
-+	__hc32			buf1;
-+	__hc32			buf2;
-+
-+	/* this is used to initialize sITD's tt info */
-+	__hc32			address;
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.3
-+ * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
-+ *
-+ * Schedule records for high speed iso xfers
-+ */
-+struct fotg210_itd {
-+	/* first part defined by EHCI spec */
-+	__hc32			hw_next;	/* see EHCI 3.3.1 */
-+	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
-+#define FOTG210_ISOC_ACTIVE	(1<<31)	/* activate transfer this slot */
-+#define FOTG210_ISOC_BUF_ERR	(1<<30)	/* Data buffer error */
-+#define FOTG210_ISOC_BABBLE	(1<<29)	/* babble detected */
-+#define FOTG210_ISOC_XACTERR	(1<<28)	/* XactErr - transaction error */
-+#define	FOTG210_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)
-+#define	FOTG210_ITD_IOC		(1 << 15)	/* interrupt on complete */
-+
-+#define ITD_ACTIVE(fotg210)	cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
-+
-+	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
-+	__hc32			hw_bufp_hi[7];	/* Appendix B */
-+
-+	/* the rest is HCD-private */
-+	dma_addr_t		itd_dma;	/* for this itd */
-+	union fotg210_shadow	itd_next;	/* ptr to periodic q entry */
-+
-+	struct urb		*urb;
-+	struct fotg210_iso_stream	*stream;	/* endpoint's queue */
-+	struct list_head	itd_list;	/* list of stream's itds */
-+
-+	/* any/all hw_transactions here may be used by that urb */
-+	unsigned		frame;		/* where scheduled */
-+	unsigned		pg;
-+	unsigned		index[8];	/* in urb->iso_frame_desc */
-+} __aligned(32);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.96 Section 3.7
-+ * Periodic Frame Span Traversal Node (FSTN)
-+ *
-+ * Manages split interrupt transactions (using TT) that span frame boundaries
-+ * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
-+ * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
-+ * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
-+ */
-+struct fotg210_fstn {
-+	__hc32			hw_next;	/* any periodic q entry */
-+	__hc32			hw_prev;	/* qh or FOTG210_LIST_END */
-+
-+	/* the rest is HCD-private */
-+	dma_addr_t		fstn_dma;
-+	union fotg210_shadow	fstn_next;	/* ptr to periodic q entry */
-+} __aligned(32);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Prepare the PORTSC wakeup flags during controller suspend/resume */
-+
-+#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
-+		fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
-+
-+#define fotg210_prepare_ports_for_controller_resume(fotg210)		\
-+		fotg210_adjust_port_wakeup_flags(fotg210, false, false)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * Some EHCI controllers have a Transaction Translator built into the
-+ * root hub. This is a non-standard feature.  Each controller will need
-+ * to add code to the following inline functions, and call them as
-+ * needed (mostly in root hub code).
-+ */
-+
-+static inline unsigned int
-+fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
-+{
-+	return (readl(&fotg210->regs->otgcsr)
-+		& OTGCSR_HOST_SPD_TYP) >> 22;
-+}
-+
-+/* Returns the speed of a device attached to a port on the root hub. */
-+static inline unsigned int
-+fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
-+{
-+	switch (fotg210_get_speed(fotg210, portsc)) {
-+	case 0:
-+		return 0;
-+	case 1:
-+		return USB_PORT_STAT_LOW_SPEED;
-+	case 2:
-+	default:
-+		return USB_PORT_STAT_HIGH_SPEED;
-+	}
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define	fotg210_has_fsl_portno_bug(e)		(0)
-+
-+/*
-+ * While most USB host controllers implement their registers in
-+ * little-endian format, a minority (celleb companion chip) implement
-+ * them in big endian format.
-+ *
-+ * This attempts to support either format at compile time without a
-+ * runtime penalty, or both formats with the additional overhead
-+ * of checking a flag bit.
-+ *
-+ */
-+
-+#define fotg210_big_endian_mmio(e)	0
-+#define fotg210_big_endian_capbase(e)	0
-+
-+static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
-+		__u32 __iomem *regs)
-+{
-+	return readl(regs);
-+}
-+
-+static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
-+		const unsigned int val, __u32 __iomem *regs)
-+{
-+	writel(val, regs);
-+}
-+
-+/* cpu to fotg210 */
-+static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
-+{
-+	return cpu_to_le32(x);
-+}
-+
-+/* fotg210 to cpu */
-+static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
-+{
-+	return le32_to_cpu(x);
-+}
-+
-+static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
-+			       const __hc32 *x)
-+{
-+	return le32_to_cpup(x);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
-+{
-+	return fotg210_readl(fotg210, &fotg210->regs->frame_index);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#endif /* __LINUX_FOTG210_H */
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -0,0 +1,249 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Faraday FOTG210 USB OTG controller
-+ *
-+ * Copyright (C) 2013 Faraday Technology Corporation
-+ * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ */
-+
-+#include <linux/kernel.h>
-+
-+#define FOTG210_MAX_NUM_EP	5 /* ep0...ep4 */
-+#define FOTG210_MAX_FIFO_NUM	4 /* fifo0...fifo4 */
-+
-+/* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
-+#define FOTG210_GMIR		0xC4
-+#define GMIR_INT_POLARITY	0x8 /*Active High*/
-+#define GMIR_MHC_INT		0x4
-+#define GMIR_MOTG_INT		0x2
-+#define GMIR_MDEV_INT		0x1
-+
-+/*  Device Main Control Register(0x100) */
-+#define FOTG210_DMCR		0x100
-+#define DMCR_HS_EN		(1 << 6)
-+#define DMCR_CHIP_EN		(1 << 5)
-+#define DMCR_SFRST		(1 << 4)
-+#define DMCR_GOSUSP		(1 << 3)
-+#define DMCR_GLINT_EN		(1 << 2)
-+#define DMCR_HALF_SPEED		(1 << 1)
-+#define DMCR_CAP_RMWAKUP	(1 << 0)
-+
-+/* Device Address Register(0x104) */
-+#define FOTG210_DAR		0x104
-+#define DAR_AFT_CONF		(1 << 7)
-+
-+/* Device Test Register(0x108) */
-+#define FOTG210_DTR		0x108
-+#define DTR_TST_CLRFF		(1 << 0)
-+
-+/* PHY Test Mode Selector register(0x114) */
-+#define FOTG210_PHYTMSR		0x114
-+#define PHYTMSR_TST_PKT		(1 << 4)
-+#define PHYTMSR_TST_SE0NAK	(1 << 3)
-+#define PHYTMSR_TST_KSTA	(1 << 2)
-+#define PHYTMSR_TST_JSTA	(1 << 1)
-+#define PHYTMSR_UNPLUG		(1 << 0)
-+
-+/* Cx configuration and FIFO Empty Status register(0x120) */
-+#define FOTG210_DCFESR		0x120
-+#define DCFESR_FIFO_EMPTY(fifo)	(1 << 8 << (fifo))
-+#define DCFESR_CX_EMP		(1 << 5)
-+#define DCFESR_CX_CLR		(1 << 3)
-+#define DCFESR_CX_STL		(1 << 2)
-+#define DCFESR_TST_PKDONE	(1 << 1)
-+#define DCFESR_CX_DONE		(1 << 0)
-+
-+/* Device IDLE Counter Register(0x124) */
-+#define FOTG210_DICR		0x124
-+
-+/* Device Mask of Interrupt Group Register (0x130) */
-+#define FOTG210_DMIGR		0x130
-+#define DMIGR_MINT_G0		(1 << 0)
-+
-+/* Device Mask of Interrupt Source Group 0(0x134) */
-+#define FOTG210_DMISGR0		0x134
-+#define DMISGR0_MCX_COMEND	(1 << 3)
-+#define DMISGR0_MCX_OUT_INT	(1 << 2)
-+#define DMISGR0_MCX_IN_INT	(1 << 1)
-+#define DMISGR0_MCX_SETUP_INT	(1 << 0)
-+
-+/* Device Mask of Interrupt Source Group 1 Register(0x138)*/
-+#define FOTG210_DMISGR1		0x138
-+#define DMISGR1_MF3_IN_INT	(1 << 19)
-+#define DMISGR1_MF2_IN_INT	(1 << 18)
-+#define DMISGR1_MF1_IN_INT	(1 << 17)
-+#define DMISGR1_MF0_IN_INT	(1 << 16)
-+#define DMISGR1_MF_IN_INT(fifo)	(1 << (16 + (fifo)))
-+#define DMISGR1_MF3_SPK_INT	(1 << 7)
-+#define DMISGR1_MF3_OUT_INT	(1 << 6)
-+#define DMISGR1_MF2_SPK_INT	(1 << 5)
-+#define DMISGR1_MF2_OUT_INT	(1 << 4)
-+#define DMISGR1_MF1_SPK_INT	(1 << 3)
-+#define DMISGR1_MF1_OUT_INT	(1 << 2)
-+#define DMISGR1_MF0_SPK_INT	(1 << 1)
-+#define DMISGR1_MF0_OUT_INT	(1 << 0)
-+#define DMISGR1_MF_OUTSPK_INT(fifo)	(0x3 << (fifo) * 2)
-+
-+/* Device Mask of Interrupt Source Group 2 Register (0x13C) */
-+#define FOTG210_DMISGR2		0x13C
-+#define DMISGR2_MDMA_ERROR	(1 << 8)
-+#define DMISGR2_MDMA_CMPLT	(1 << 7)
-+
-+/* Device Interrupt group Register (0x140) */
-+#define FOTG210_DIGR		0x140
-+#define DIGR_INT_G2		(1 << 2)
-+#define DIGR_INT_G1		(1 << 1)
-+#define DIGR_INT_G0		(1 << 0)
-+
-+/* Device Interrupt Source Group 0 Register (0x144) */
-+#define FOTG210_DISGR0		0x144
-+#define DISGR0_CX_COMABT_INT	(1 << 5)
-+#define DISGR0_CX_COMFAIL_INT	(1 << 4)
-+#define DISGR0_CX_COMEND_INT	(1 << 3)
-+#define DISGR0_CX_OUT_INT	(1 << 2)
-+#define DISGR0_CX_IN_INT	(1 << 1)
-+#define DISGR0_CX_SETUP_INT	(1 << 0)
-+
-+/* Device Interrupt Source Group 1 Register (0x148) */
-+#define FOTG210_DISGR1		0x148
-+#define DISGR1_OUT_INT(fifo)	(1 << ((fifo) * 2))
-+#define DISGR1_SPK_INT(fifo)	(1 << 1 << ((fifo) * 2))
-+#define DISGR1_IN_INT(fifo)	(1 << 16 << (fifo))
-+
-+/* Device Interrupt Source Group 2 Register (0x14C) */
-+#define FOTG210_DISGR2		0x14C
-+#define DISGR2_DMA_ERROR	(1 << 8)
-+#define DISGR2_DMA_CMPLT	(1 << 7)
-+#define DISGR2_RX0BYTE_INT	(1 << 6)
-+#define DISGR2_TX0BYTE_INT	(1 << 5)
-+#define DISGR2_ISO_SEQ_ABORT_INT	(1 << 4)
-+#define DISGR2_ISO_SEQ_ERR_INT	(1 << 3)
-+#define DISGR2_RESM_INT		(1 << 2)
-+#define DISGR2_SUSP_INT		(1 << 1)
-+#define DISGR2_USBRST_INT	(1 << 0)
-+
-+/* Device Receive Zero-Length Data Packet Register (0x150)*/
-+#define FOTG210_RX0BYTE		0x150
-+#define RX0BYTE_EP8		(1 << 7)
-+#define RX0BYTE_EP7		(1 << 6)
-+#define RX0BYTE_EP6		(1 << 5)
-+#define RX0BYTE_EP5		(1 << 4)
-+#define RX0BYTE_EP4		(1 << 3)
-+#define RX0BYTE_EP3		(1 << 2)
-+#define RX0BYTE_EP2		(1 << 1)
-+#define RX0BYTE_EP1		(1 << 0)
-+
-+/* Device Transfer Zero-Length Data Packet Register (0x154)*/
-+#define FOTG210_TX0BYTE		0x154
-+#define TX0BYTE_EP8		(1 << 7)
-+#define TX0BYTE_EP7		(1 << 6)
-+#define TX0BYTE_EP6		(1 << 5)
-+#define TX0BYTE_EP5		(1 << 4)
-+#define TX0BYTE_EP4		(1 << 3)
-+#define TX0BYTE_EP3		(1 << 2)
-+#define TX0BYTE_EP2		(1 << 1)
-+#define TX0BYTE_EP1		(1 << 0)
-+
-+/* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
-+#define FOTG210_INEPMPSR(ep)	(0x160 + 4 * ((ep) - 1))
-+#define INOUTEPMPSR_MPS(mps)	((mps) & 0x2FF)
-+#define INOUTEPMPSR_STL_EP	(1 << 11)
-+#define INOUTEPMPSR_RESET_TSEQ	(1 << 12)
-+
-+/* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
-+#define FOTG210_OUTEPMPSR(ep)	(0x180 + 4 * ((ep) - 1))
-+
-+/* Device Endpoint 1~4 Map Register (0x1A0) */
-+#define FOTG210_EPMAP		0x1A0
-+#define EPMAP_FIFONO(ep, dir)		\
-+	((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
-+#define EPMAP_FIFONOMSK(ep, dir)	\
-+	((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
-+
-+/* Device FIFO Map Register (0x1A8) */
-+#define FOTG210_FIFOMAP		0x1A8
-+#define FIFOMAP_DIROUT(fifo)	(0x0 << 4 << (fifo) * 8)
-+#define FIFOMAP_DIRIN(fifo)	(0x1 << 4 << (fifo) * 8)
-+#define FIFOMAP_BIDIR(fifo)	(0x2 << 4 << (fifo) * 8)
-+#define FIFOMAP_NA(fifo)	(0x3 << 4 << (fifo) * 8)
-+#define FIFOMAP_EPNO(ep)	((ep) << ((ep) - 1) * 8)
-+#define FIFOMAP_EPNOMSK(ep)	(0xF << ((ep) - 1) * 8)
-+
-+/* Device FIFO Confuguration Register (0x1AC) */
-+#define FOTG210_FIFOCF		0x1AC
-+#define FIFOCF_TYPE(type, fifo)	((type) << (fifo) * 8)
-+#define FIFOCF_BLK_SIN(fifo)	(0x0 << (fifo) * 8 << 2)
-+#define FIFOCF_BLK_DUB(fifo)	(0x1 << (fifo) * 8 << 2)
-+#define FIFOCF_BLK_TRI(fifo)	(0x2 << (fifo) * 8 << 2)
-+#define FIFOCF_BLKSZ_512(fifo)	(0x0 << (fifo) * 8 << 4)
-+#define FIFOCF_BLKSZ_1024(fifo)	(0x1 << (fifo) * 8 << 4)
-+#define FIFOCF_FIFO_EN(fifo)	(0x1 << (fifo) * 8 << 5)
-+
-+/* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
-+#define FOTG210_FIBCR(fifo)	(0x1B0 + (fifo) * 4)
-+#define FIBCR_BCFX		0x7FF
-+#define FIBCR_FFRST		(1 << 12)
-+
-+/* Device DMA Target FIFO Number Register (0x1C0) */
-+#define FOTG210_DMATFNR		0x1C0
-+#define DMATFNR_ACC_CXF		(1 << 4)
-+#define DMATFNR_ACC_F3		(1 << 3)
-+#define DMATFNR_ACC_F2		(1 << 2)
-+#define DMATFNR_ACC_F1		(1 << 1)
-+#define DMATFNR_ACC_F0		(1 << 0)
-+#define DMATFNR_ACC_FN(fifo)	(1 << (fifo))
-+#define DMATFNR_DISDMA		0
-+
-+/* Device DMA Controller Parameter setting 1 Register (0x1C8) */
-+#define FOTG210_DMACPSR1	0x1C8
-+#define DMACPSR1_DMA_LEN(len)	(((len) & 0xFFFF) << 8)
-+#define DMACPSR1_DMA_ABORT	(1 << 3)
-+#define DMACPSR1_DMA_TYPE(dir_in)	(((dir_in) ? 1 : 0) << 1)
-+#define DMACPSR1_DMA_START	(1 << 0)
-+
-+/* Device DMA Controller Parameter setting 2 Register (0x1CC) */
-+#define FOTG210_DMACPSR2	0x1CC
-+
-+/* Device DMA Controller Parameter setting 3 Register (0x1CC) */
-+#define FOTG210_CXPORT		0x1D0
-+
-+struct fotg210_request {
-+	struct usb_request	req;
-+	struct list_head	queue;
-+};
-+
-+struct fotg210_ep {
-+	struct usb_ep		ep;
-+	struct fotg210_udc	*fotg210;
-+
-+	struct list_head	queue;
-+	unsigned		stall:1;
-+	unsigned		wedged:1;
-+	unsigned		use_dma:1;
-+
-+	unsigned char		epnum;
-+	unsigned char		type;
-+	unsigned char		dir_in;
-+	unsigned int		maxp;
-+	const struct usb_endpoint_descriptor	*desc;
-+};
-+
-+struct fotg210_udc {
-+	spinlock_t		lock; /* protect the struct */
-+	void __iomem		*reg;
-+
-+	unsigned long		irq_trigger;
-+
-+	struct usb_gadget		gadget;
-+	struct usb_gadget_driver	*driver;
-+
-+	struct fotg210_ep	*ep[FOTG210_MAX_NUM_EP];
-+
-+	struct usb_request	*ep0_req;	/* for internal request */
-+	__le16			ep0_data;
-+	u8			ep0_dir;	/* 0/0x80  out/in */
-+
-+	u8			reenum;		/* if re-enumeration */
-+};
-+
-+#define gadget_to_fotg210(g)	container_of((g), struct fotg210_udc, gadget)
---- a/drivers/usb/gadget/udc/fotg210.h
-+++ /dev/null
-@@ -1,249 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0+
--/*
-- * Faraday FOTG210 USB OTG controller
-- *
-- * Copyright (C) 2013 Faraday Technology Corporation
-- * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- */
--
--#include <linux/kernel.h>
--
--#define FOTG210_MAX_NUM_EP	5 /* ep0...ep4 */
--#define FOTG210_MAX_FIFO_NUM	4 /* fifo0...fifo4 */
--
--/* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
--#define FOTG210_GMIR		0xC4
--#define GMIR_INT_POLARITY	0x8 /*Active High*/
--#define GMIR_MHC_INT		0x4
--#define GMIR_MOTG_INT		0x2
--#define GMIR_MDEV_INT		0x1
--
--/*  Device Main Control Register(0x100) */
--#define FOTG210_DMCR		0x100
--#define DMCR_HS_EN		(1 << 6)
--#define DMCR_CHIP_EN		(1 << 5)
--#define DMCR_SFRST		(1 << 4)
--#define DMCR_GOSUSP		(1 << 3)
--#define DMCR_GLINT_EN		(1 << 2)
--#define DMCR_HALF_SPEED		(1 << 1)
--#define DMCR_CAP_RMWAKUP	(1 << 0)
--
--/* Device Address Register(0x104) */
--#define FOTG210_DAR		0x104
--#define DAR_AFT_CONF		(1 << 7)
--
--/* Device Test Register(0x108) */
--#define FOTG210_DTR		0x108
--#define DTR_TST_CLRFF		(1 << 0)
--
--/* PHY Test Mode Selector register(0x114) */
--#define FOTG210_PHYTMSR		0x114
--#define PHYTMSR_TST_PKT		(1 << 4)
--#define PHYTMSR_TST_SE0NAK	(1 << 3)
--#define PHYTMSR_TST_KSTA	(1 << 2)
--#define PHYTMSR_TST_JSTA	(1 << 1)
--#define PHYTMSR_UNPLUG		(1 << 0)
--
--/* Cx configuration and FIFO Empty Status register(0x120) */
--#define FOTG210_DCFESR		0x120
--#define DCFESR_FIFO_EMPTY(fifo)	(1 << 8 << (fifo))
--#define DCFESR_CX_EMP		(1 << 5)
--#define DCFESR_CX_CLR		(1 << 3)
--#define DCFESR_CX_STL		(1 << 2)
--#define DCFESR_TST_PKDONE	(1 << 1)
--#define DCFESR_CX_DONE		(1 << 0)
--
--/* Device IDLE Counter Register(0x124) */
--#define FOTG210_DICR		0x124
--
--/* Device Mask of Interrupt Group Register (0x130) */
--#define FOTG210_DMIGR		0x130
--#define DMIGR_MINT_G0		(1 << 0)
--
--/* Device Mask of Interrupt Source Group 0(0x134) */
--#define FOTG210_DMISGR0		0x134
--#define DMISGR0_MCX_COMEND	(1 << 3)
--#define DMISGR0_MCX_OUT_INT	(1 << 2)
--#define DMISGR0_MCX_IN_INT	(1 << 1)
--#define DMISGR0_MCX_SETUP_INT	(1 << 0)
--
--/* Device Mask of Interrupt Source Group 1 Register(0x138)*/
--#define FOTG210_DMISGR1		0x138
--#define DMISGR1_MF3_IN_INT	(1 << 19)
--#define DMISGR1_MF2_IN_INT	(1 << 18)
--#define DMISGR1_MF1_IN_INT	(1 << 17)
--#define DMISGR1_MF0_IN_INT	(1 << 16)
--#define DMISGR1_MF_IN_INT(fifo)	(1 << (16 + (fifo)))
--#define DMISGR1_MF3_SPK_INT	(1 << 7)
--#define DMISGR1_MF3_OUT_INT	(1 << 6)
--#define DMISGR1_MF2_SPK_INT	(1 << 5)
--#define DMISGR1_MF2_OUT_INT	(1 << 4)
--#define DMISGR1_MF1_SPK_INT	(1 << 3)
--#define DMISGR1_MF1_OUT_INT	(1 << 2)
--#define DMISGR1_MF0_SPK_INT	(1 << 1)
--#define DMISGR1_MF0_OUT_INT	(1 << 0)
--#define DMISGR1_MF_OUTSPK_INT(fifo)	(0x3 << (fifo) * 2)
--
--/* Device Mask of Interrupt Source Group 2 Register (0x13C) */
--#define FOTG210_DMISGR2		0x13C
--#define DMISGR2_MDMA_ERROR	(1 << 8)
--#define DMISGR2_MDMA_CMPLT	(1 << 7)
--
--/* Device Interrupt group Register (0x140) */
--#define FOTG210_DIGR		0x140
--#define DIGR_INT_G2		(1 << 2)
--#define DIGR_INT_G1		(1 << 1)
--#define DIGR_INT_G0		(1 << 0)
--
--/* Device Interrupt Source Group 0 Register (0x144) */
--#define FOTG210_DISGR0		0x144
--#define DISGR0_CX_COMABT_INT	(1 << 5)
--#define DISGR0_CX_COMFAIL_INT	(1 << 4)
--#define DISGR0_CX_COMEND_INT	(1 << 3)
--#define DISGR0_CX_OUT_INT	(1 << 2)
--#define DISGR0_CX_IN_INT	(1 << 1)
--#define DISGR0_CX_SETUP_INT	(1 << 0)
--
--/* Device Interrupt Source Group 1 Register (0x148) */
--#define FOTG210_DISGR1		0x148
--#define DISGR1_OUT_INT(fifo)	(1 << ((fifo) * 2))
--#define DISGR1_SPK_INT(fifo)	(1 << 1 << ((fifo) * 2))
--#define DISGR1_IN_INT(fifo)	(1 << 16 << (fifo))
--
--/* Device Interrupt Source Group 2 Register (0x14C) */
--#define FOTG210_DISGR2		0x14C
--#define DISGR2_DMA_ERROR	(1 << 8)
--#define DISGR2_DMA_CMPLT	(1 << 7)
--#define DISGR2_RX0BYTE_INT	(1 << 6)
--#define DISGR2_TX0BYTE_INT	(1 << 5)
--#define DISGR2_ISO_SEQ_ABORT_INT	(1 << 4)
--#define DISGR2_ISO_SEQ_ERR_INT	(1 << 3)
--#define DISGR2_RESM_INT		(1 << 2)
--#define DISGR2_SUSP_INT		(1 << 1)
--#define DISGR2_USBRST_INT	(1 << 0)
--
--/* Device Receive Zero-Length Data Packet Register (0x150)*/
--#define FOTG210_RX0BYTE		0x150
--#define RX0BYTE_EP8		(1 << 7)
--#define RX0BYTE_EP7		(1 << 6)
--#define RX0BYTE_EP6		(1 << 5)
--#define RX0BYTE_EP5		(1 << 4)
--#define RX0BYTE_EP4		(1 << 3)
--#define RX0BYTE_EP3		(1 << 2)
--#define RX0BYTE_EP2		(1 << 1)
--#define RX0BYTE_EP1		(1 << 0)
--
--/* Device Transfer Zero-Length Data Packet Register (0x154)*/
--#define FOTG210_TX0BYTE		0x154
--#define TX0BYTE_EP8		(1 << 7)
--#define TX0BYTE_EP7		(1 << 6)
--#define TX0BYTE_EP6		(1 << 5)
--#define TX0BYTE_EP5		(1 << 4)
--#define TX0BYTE_EP4		(1 << 3)
--#define TX0BYTE_EP3		(1 << 2)
--#define TX0BYTE_EP2		(1 << 1)
--#define TX0BYTE_EP1		(1 << 0)
--
--/* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
--#define FOTG210_INEPMPSR(ep)	(0x160 + 4 * ((ep) - 1))
--#define INOUTEPMPSR_MPS(mps)	((mps) & 0x2FF)
--#define INOUTEPMPSR_STL_EP	(1 << 11)
--#define INOUTEPMPSR_RESET_TSEQ	(1 << 12)
--
--/* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
--#define FOTG210_OUTEPMPSR(ep)	(0x180 + 4 * ((ep) - 1))
--
--/* Device Endpoint 1~4 Map Register (0x1A0) */
--#define FOTG210_EPMAP		0x1A0
--#define EPMAP_FIFONO(ep, dir)		\
--	((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
--#define EPMAP_FIFONOMSK(ep, dir)	\
--	((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
--
--/* Device FIFO Map Register (0x1A8) */
--#define FOTG210_FIFOMAP		0x1A8
--#define FIFOMAP_DIROUT(fifo)	(0x0 << 4 << (fifo) * 8)
--#define FIFOMAP_DIRIN(fifo)	(0x1 << 4 << (fifo) * 8)
--#define FIFOMAP_BIDIR(fifo)	(0x2 << 4 << (fifo) * 8)
--#define FIFOMAP_NA(fifo)	(0x3 << 4 << (fifo) * 8)
--#define FIFOMAP_EPNO(ep)	((ep) << ((ep) - 1) * 8)
--#define FIFOMAP_EPNOMSK(ep)	(0xF << ((ep) - 1) * 8)
--
--/* Device FIFO Confuguration Register (0x1AC) */
--#define FOTG210_FIFOCF		0x1AC
--#define FIFOCF_TYPE(type, fifo)	((type) << (fifo) * 8)
--#define FIFOCF_BLK_SIN(fifo)	(0x0 << (fifo) * 8 << 2)
--#define FIFOCF_BLK_DUB(fifo)	(0x1 << (fifo) * 8 << 2)
--#define FIFOCF_BLK_TRI(fifo)	(0x2 << (fifo) * 8 << 2)
--#define FIFOCF_BLKSZ_512(fifo)	(0x0 << (fifo) * 8 << 4)
--#define FIFOCF_BLKSZ_1024(fifo)	(0x1 << (fifo) * 8 << 4)
--#define FIFOCF_FIFO_EN(fifo)	(0x1 << (fifo) * 8 << 5)
--
--/* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
--#define FOTG210_FIBCR(fifo)	(0x1B0 + (fifo) * 4)
--#define FIBCR_BCFX		0x7FF
--#define FIBCR_FFRST		(1 << 12)
--
--/* Device DMA Target FIFO Number Register (0x1C0) */
--#define FOTG210_DMATFNR		0x1C0
--#define DMATFNR_ACC_CXF		(1 << 4)
--#define DMATFNR_ACC_F3		(1 << 3)
--#define DMATFNR_ACC_F2		(1 << 2)
--#define DMATFNR_ACC_F1		(1 << 1)
--#define DMATFNR_ACC_F0		(1 << 0)
--#define DMATFNR_ACC_FN(fifo)	(1 << (fifo))
--#define DMATFNR_DISDMA		0
--
--/* Device DMA Controller Parameter setting 1 Register (0x1C8) */
--#define FOTG210_DMACPSR1	0x1C8
--#define DMACPSR1_DMA_LEN(len)	(((len) & 0xFFFF) << 8)
--#define DMACPSR1_DMA_ABORT	(1 << 3)
--#define DMACPSR1_DMA_TYPE(dir_in)	(((dir_in) ? 1 : 0) << 1)
--#define DMACPSR1_DMA_START	(1 << 0)
--
--/* Device DMA Controller Parameter setting 2 Register (0x1CC) */
--#define FOTG210_DMACPSR2	0x1CC
--
--/* Device DMA Controller Parameter setting 3 Register (0x1CC) */
--#define FOTG210_CXPORT		0x1D0
--
--struct fotg210_request {
--	struct usb_request	req;
--	struct list_head	queue;
--};
--
--struct fotg210_ep {
--	struct usb_ep		ep;
--	struct fotg210_udc	*fotg210;
--
--	struct list_head	queue;
--	unsigned		stall:1;
--	unsigned		wedged:1;
--	unsigned		use_dma:1;
--
--	unsigned char		epnum;
--	unsigned char		type;
--	unsigned char		dir_in;
--	unsigned int		maxp;
--	const struct usb_endpoint_descriptor	*desc;
--};
--
--struct fotg210_udc {
--	spinlock_t		lock; /* protect the struct */
--	void __iomem		*reg;
--
--	unsigned long		irq_trigger;
--
--	struct usb_gadget		gadget;
--	struct usb_gadget_driver	*driver;
--
--	struct fotg210_ep	*ep[FOTG210_MAX_NUM_EP];
--
--	struct usb_request	*ep0_req;	/* for internal request */
--	__le16			ep0_data;
--	u8			ep0_dir;	/* 0/0x80  out/in */
--
--	u8			reenum;		/* if re-enumeration */
--};
--
--#define gadget_to_fotg210(g)	container_of((g), struct fotg210_udc, gadget)
---- a/drivers/usb/host/fotg210.h
-+++ /dev/null
-@@ -1,688 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 */
--#ifndef __LINUX_FOTG210_H
--#define __LINUX_FOTG210_H
--
--#include <linux/usb/ehci-dbgp.h>
--
--/* definitions used for the EHCI driver */
--
--/*
-- * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
-- * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
-- * the host controller implementation.
-- *
-- * To facilitate the strongest possible byte-order checking from "sparse"
-- * and so on, we use __leXX unless that's not practical.
-- */
--#define __hc32	__le32
--#define __hc16	__le16
--
--/* statistics can be kept for tuning/monitoring */
--struct fotg210_stats {
--	/* irq usage */
--	unsigned long		normal;
--	unsigned long		error;
--	unsigned long		iaa;
--	unsigned long		lost_iaa;
--
--	/* termination of urbs from core */
--	unsigned long		complete;
--	unsigned long		unlink;
--};
--
--/* fotg210_hcd->lock guards shared data against other CPUs:
-- *   fotg210_hcd:	async, unlink, periodic (and shadow), ...
-- *   usb_host_endpoint: hcpriv
-- *   fotg210_qh:	qh_next, qtd_list
-- *   fotg210_qtd:	qtd_list
-- *
-- * Also, hold this lock when talking to HC registers or
-- * when updating hw_* fields in shared qh/qtd/... structures.
-- */
--
--#define	FOTG210_MAX_ROOT_PORTS	1		/* see HCS_N_PORTS */
--
--/*
-- * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
-- * controller may be doing DMA.  Lower values mean there's no DMA.
-- */
--enum fotg210_rh_state {
--	FOTG210_RH_HALTED,
--	FOTG210_RH_SUSPENDED,
--	FOTG210_RH_RUNNING,
--	FOTG210_RH_STOPPING
--};
--
--/*
-- * Timer events, ordered by increasing delay length.
-- * Always update event_delays_ns[] and event_handlers[] (defined in
-- * ehci-timer.c) in parallel with this list.
-- */
--enum fotg210_hrtimer_event {
--	FOTG210_HRTIMER_POLL_ASS,	/* Poll for async schedule off */
--	FOTG210_HRTIMER_POLL_PSS,	/* Poll for periodic schedule off */
--	FOTG210_HRTIMER_POLL_DEAD,	/* Wait for dead controller to stop */
--	FOTG210_HRTIMER_UNLINK_INTR,	/* Wait for interrupt QH unlink */
--	FOTG210_HRTIMER_FREE_ITDS,	/* Wait for unused iTDs and siTDs */
--	FOTG210_HRTIMER_ASYNC_UNLINKS,	/* Unlink empty async QHs */
--	FOTG210_HRTIMER_IAA_WATCHDOG,	/* Handle lost IAA interrupts */
--	FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
--	FOTG210_HRTIMER_DISABLE_ASYNC,	/* Wait to disable async sched */
--	FOTG210_HRTIMER_IO_WATCHDOG,	/* Check for missing IRQs */
--	FOTG210_HRTIMER_NUM_EVENTS	/* Must come last */
--};
--#define FOTG210_HRTIMER_NO_EVENT	99
--
--struct fotg210_hcd {			/* one per controller */
--	/* timing support */
--	enum fotg210_hrtimer_event	next_hrtimer_event;
--	unsigned		enabled_hrtimer_events;
--	ktime_t			hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
--	struct hrtimer		hrtimer;
--
--	int			PSS_poll_count;
--	int			ASS_poll_count;
--	int			died_poll_count;
--
--	/* glue to PCI and HCD framework */
--	struct fotg210_caps __iomem *caps;
--	struct fotg210_regs __iomem *regs;
--	struct ehci_dbg_port __iomem *debug;
--
--	__u32			hcs_params;	/* cached register copy */
--	spinlock_t		lock;
--	enum fotg210_rh_state	rh_state;
--
--	/* general schedule support */
--	bool			scanning:1;
--	bool			need_rescan:1;
--	bool			intr_unlinking:1;
--	bool			async_unlinking:1;
--	bool			shutdown:1;
--	struct fotg210_qh		*qh_scan_next;
--
--	/* async schedule support */
--	struct fotg210_qh		*async;
--	struct fotg210_qh		*dummy;		/* For AMD quirk use */
--	struct fotg210_qh		*async_unlink;
--	struct fotg210_qh		*async_unlink_last;
--	struct fotg210_qh		*async_iaa;
--	unsigned		async_unlink_cycle;
--	unsigned		async_count;	/* async activity count */
--
--	/* periodic schedule support */
--#define	DEFAULT_I_TDPS		1024		/* some HCs can do less */
--	unsigned		periodic_size;
--	__hc32			*periodic;	/* hw periodic table */
--	dma_addr_t		periodic_dma;
--	struct list_head	intr_qh_list;
--	unsigned		i_thresh;	/* uframes HC might cache */
--
--	union fotg210_shadow	*pshadow;	/* mirror hw periodic table */
--	struct fotg210_qh		*intr_unlink;
--	struct fotg210_qh		*intr_unlink_last;
--	unsigned		intr_unlink_cycle;
--	unsigned		now_frame;	/* frame from HC hardware */
--	unsigned		next_frame;	/* scan periodic, start here */
--	unsigned		intr_count;	/* intr activity count */
--	unsigned		isoc_count;	/* isoc activity count */
--	unsigned		periodic_count;	/* periodic activity count */
--	/* max periodic time per uframe */
--	unsigned		uframe_periodic_max;
--
--
--	/* list of itds completed while now_frame was still active */
--	struct list_head	cached_itd_list;
--	struct fotg210_itd	*last_itd_to_free;
--
--	/* per root hub port */
--	unsigned long		reset_done[FOTG210_MAX_ROOT_PORTS];
--
--	/* bit vectors (one bit per port)
--	 * which ports were already suspended at the start of a bus suspend
--	 */
--	unsigned long		bus_suspended;
--
--	/* which ports are edicated to the companion controller */
--	unsigned long		companion_ports;
--
--	/* which ports are owned by the companion during a bus suspend */
--	unsigned long		owned_ports;
--
--	/* which ports have the change-suspend feature turned on */
--	unsigned long		port_c_suspend;
--
--	/* which ports are suspended */
--	unsigned long		suspended_ports;
--
--	/* which ports have started to resume */
--	unsigned long		resuming_ports;
--
--	/* per-HC memory pools (could be per-bus, but ...) */
--	struct dma_pool		*qh_pool;	/* qh per active urb */
--	struct dma_pool		*qtd_pool;	/* one or more per qh */
--	struct dma_pool		*itd_pool;	/* itd per iso urb */
--
--	unsigned		random_frame;
--	unsigned long		next_statechange;
--	ktime_t			last_periodic_enable;
--	u32			command;
--
--	/* SILICON QUIRKS */
--	unsigned		need_io_watchdog:1;
--	unsigned		fs_i_thresh:1;	/* Intel iso scheduling */
--
--	u8			sbrn;		/* packed release number */
--
--	/* irq statistics */
--#ifdef FOTG210_STATS
--	struct fotg210_stats	stats;
--#	define INCR(x) ((x)++)
--#else
--#	define INCR(x) do {} while (0)
--#endif
--
--	/* silicon clock */
--	struct clk		*pclk;
--};
--
--/* convert between an HCD pointer and the corresponding FOTG210_HCD */
--static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
--{
--	return (struct fotg210_hcd *)(hcd->hcd_priv);
--}
--static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
--{
--	return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
--}
--
--/*-------------------------------------------------------------------------*/
--
--/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
--
--/* Section 2.2 Host Controller Capability Registers */
--struct fotg210_caps {
--	/* these fields are specified as 8 and 16 bit registers,
--	 * but some hosts can't perform 8 or 16 bit PCI accesses.
--	 * some hosts treat caplength and hciversion as parts of a 32-bit
--	 * register, others treat them as two separate registers, this
--	 * affects the memory map for big endian controllers.
--	 */
--	u32		hc_capbase;
--#define HC_LENGTH(fotg210, p)	(0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
--				(fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
--#define HC_VERSION(fotg210, p)	(0xffff&((p) >> /* bits 31:16 / offset 02h */ \
--				(fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
--	u32		hcs_params;     /* HCSPARAMS - offset 0x4 */
--#define HCS_N_PORTS(p)		(((p)>>0)&0xf)	/* bits 3:0, ports on HC */
--
--	u32		hcc_params;	/* HCCPARAMS - offset 0x8 */
--#define HCC_CANPARK(p)		((p)&(1 << 2))  /* true: can park on async qh */
--#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
--	u8		portroute[8];	 /* nibbles for routing - offset 0xC */
--};
--
--
--/* Section 2.3 Host Controller Operational Registers */
--struct fotg210_regs {
--
--	/* USBCMD: offset 0x00 */
--	u32		command;
--
--/* EHCI 1.1 addendum */
--/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
--#define CMD_PARK	(1<<11)		/* enable "park" on async qh */
--#define CMD_PARK_CNT(c)	(((c)>>8)&3)	/* how many transfers to park for */
--#define CMD_IAAD	(1<<6)		/* "doorbell" interrupt async advance */
--#define CMD_ASE		(1<<5)		/* async schedule enable */
--#define CMD_PSE		(1<<4)		/* periodic schedule enable */
--/* 3:2 is periodic frame list size */
--#define CMD_RESET	(1<<1)		/* reset HC not bus */
--#define CMD_RUN		(1<<0)		/* start/stop HC */
--
--	/* USBSTS: offset 0x04 */
--	u32		status;
--#define STS_ASS		(1<<15)		/* Async Schedule Status */
--#define STS_PSS		(1<<14)		/* Periodic Schedule Status */
--#define STS_RECL	(1<<13)		/* Reclamation */
--#define STS_HALT	(1<<12)		/* Not running (any reason) */
--/* some bits reserved */
--	/* these STS_* flags are also intr_enable bits (USBINTR) */
--#define STS_IAA		(1<<5)		/* Interrupted on async advance */
--#define STS_FATAL	(1<<4)		/* such as some PCI access errors */
--#define STS_FLR		(1<<3)		/* frame list rolled over */
--#define STS_PCD		(1<<2)		/* port change detect */
--#define STS_ERR		(1<<1)		/* "error" completion (overflow, ...) */
--#define STS_INT		(1<<0)		/* "normal" completion (short, ...) */
--
--	/* USBINTR: offset 0x08 */
--	u32		intr_enable;
--
--	/* FRINDEX: offset 0x0C */
--	u32		frame_index;	/* current microframe number */
--	/* CTRLDSSEGMENT: offset 0x10 */
--	u32		segment;	/* address bits 63:32 if needed */
--	/* PERIODICLISTBASE: offset 0x14 */
--	u32		frame_list;	/* points to periodic list */
--	/* ASYNCLISTADDR: offset 0x18 */
--	u32		async_next;	/* address of next async queue head */
--
--	u32	reserved1;
--	/* PORTSC: offset 0x20 */
--	u32	port_status;
--/* 31:23 reserved */
--#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))	/* USB 1.1 device */
--#define PORT_RESET	(1<<8)		/* reset port */
--#define PORT_SUSPEND	(1<<7)		/* suspend port */
--#define PORT_RESUME	(1<<6)		/* resume it */
--#define PORT_PEC	(1<<3)		/* port enable change */
--#define PORT_PE		(1<<2)		/* port enable */
--#define PORT_CSC	(1<<1)		/* connect status change */
--#define PORT_CONNECT	(1<<0)		/* device connected */
--#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
--	u32     reserved2[19];
--
--	/* OTGCSR: offet 0x70 */
--	u32     otgcsr;
--#define OTGCSR_HOST_SPD_TYP     (3 << 22)
--#define OTGCSR_A_BUS_DROP	(1 << 5)
--#define OTGCSR_A_BUS_REQ	(1 << 4)
--
--	/* OTGISR: offset 0x74 */
--	u32     otgisr;
--#define OTGISR_OVC	(1 << 10)
--
--	u32     reserved3[15];
--
--	/* GMIR: offset 0xB4 */
--	u32     gmir;
--#define GMIR_INT_POLARITY	(1 << 3) /*Active High*/
--#define GMIR_MHC_INT		(1 << 2)
--#define GMIR_MOTG_INT		(1 << 1)
--#define GMIR_MDEV_INT	(1 << 0)
--};
--
--/*-------------------------------------------------------------------------*/
--
--#define	QTD_NEXT(fotg210, dma)	cpu_to_hc32(fotg210, (u32)dma)
--
--/*
-- * EHCI Specification 0.95 Section 3.5
-- * QTD: describe data transfer components (buffer, direction, ...)
-- * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
-- *
-- * These are associated only with "QH" (Queue Head) structures,
-- * used with control, bulk, and interrupt transfers.
-- */
--struct fotg210_qtd {
--	/* first part defined by EHCI spec */
--	__hc32			hw_next;	/* see EHCI 3.5.1 */
--	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
--	__hc32			hw_token;	/* see EHCI 3.5.3 */
--#define	QTD_TOGGLE	(1 << 31)	/* data toggle */
--#define	QTD_LENGTH(tok)	(((tok)>>16) & 0x7fff)
--#define	QTD_IOC		(1 << 15)	/* interrupt on complete */
--#define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
--#define	QTD_PID(tok)	(((tok)>>8) & 0x3)
--#define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
--#define	QTD_STS_HALT	(1 << 6)	/* halted on error */
--#define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
--#define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
--#define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
--#define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
--#define	QTD_STS_STS	(1 << 1)	/* split transaction state */
--#define	QTD_STS_PING	(1 << 0)	/* issue PING? */
--
--#define ACTIVE_BIT(fotg210)	cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
--#define HALT_BIT(fotg210)		cpu_to_hc32(fotg210, QTD_STS_HALT)
--#define STATUS_BIT(fotg210)	cpu_to_hc32(fotg210, QTD_STS_STS)
--
--	__hc32			hw_buf[5];	/* see EHCI 3.5.4 */
--	__hc32			hw_buf_hi[5];	/* Appendix B */
--
--	/* the rest is HCD-private */
--	dma_addr_t		qtd_dma;		/* qtd address */
--	struct list_head	qtd_list;		/* sw qtd list */
--	struct urb		*urb;			/* qtd's urb */
--	size_t			length;			/* length of buffer */
--} __aligned(32);
--
--/* mask NakCnt+T in qh->hw_alt_next */
--#define QTD_MASK(fotg210)	cpu_to_hc32(fotg210, ~0x1f)
--
--#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
--
--/*-------------------------------------------------------------------------*/
--
--/* type tag from {qh,itd,fstn}->hw_next */
--#define Q_NEXT_TYPE(fotg210, dma)	((dma) & cpu_to_hc32(fotg210, 3 << 1))
--
--/*
-- * Now the following defines are not converted using the
-- * cpu_to_le32() macro anymore, since we have to support
-- * "dynamic" switching between be and le support, so that the driver
-- * can be used on one system with SoC EHCI controller using big-endian
-- * descriptors as well as a normal little-endian PCI EHCI controller.
-- */
--/* values for that type tag */
--#define Q_TYPE_ITD	(0 << 1)
--#define Q_TYPE_QH	(1 << 1)
--#define Q_TYPE_SITD	(2 << 1)
--#define Q_TYPE_FSTN	(3 << 1)
--
--/* next async queue entry, or pointer to interrupt/periodic QH */
--#define QH_NEXT(fotg210, dma) \
--	(cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
--
--/* for periodic/async schedules and qtd lists, mark end of list */
--#define FOTG210_LIST_END(fotg210) \
--	cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
--
--/*
-- * Entries in periodic shadow table are pointers to one of four kinds
-- * of data structure.  That's dictated by the hardware; a type tag is
-- * encoded in the low bits of the hardware's periodic schedule.  Use
-- * Q_NEXT_TYPE to get the tag.
-- *
-- * For entries in the async schedule, the type tag always says "qh".
-- */
--union fotg210_shadow {
--	struct fotg210_qh	*qh;		/* Q_TYPE_QH */
--	struct fotg210_itd	*itd;		/* Q_TYPE_ITD */
--	struct fotg210_fstn	*fstn;		/* Q_TYPE_FSTN */
--	__hc32			*hw_next;	/* (all types) */
--	void			*ptr;
--};
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.95 Section 3.6
-- * QH: describes control/bulk/interrupt endpoints
-- * See Fig 3-7 "Queue Head Structure Layout".
-- *
-- * These appear in both the async and (for interrupt) periodic schedules.
-- */
--
--/* first part defined by EHCI spec */
--struct fotg210_qh_hw {
--	__hc32			hw_next;	/* see EHCI 3.6.1 */
--	__hc32			hw_info1;	/* see EHCI 3.6.2 */
--#define	QH_CONTROL_EP	(1 << 27)	/* FS/LS control endpoint */
--#define	QH_HEAD		(1 << 15)	/* Head of async reclamation list */
--#define	QH_TOGGLE_CTL	(1 << 14)	/* Data toggle control */
--#define	QH_HIGH_SPEED	(2 << 12)	/* Endpoint speed */
--#define	QH_LOW_SPEED	(1 << 12)
--#define	QH_FULL_SPEED	(0 << 12)
--#define	QH_INACTIVATE	(1 << 7)	/* Inactivate on next transaction */
--	__hc32			hw_info2;	/* see EHCI 3.6.2 */
--#define	QH_SMASK	0x000000ff
--#define	QH_CMASK	0x0000ff00
--#define	QH_HUBADDR	0x007f0000
--#define	QH_HUBPORT	0x3f800000
--#define	QH_MULT		0xc0000000
--	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
--
--	/* qtd overlay (hardware parts of a struct fotg210_qtd) */
--	__hc32			hw_qtd_next;
--	__hc32			hw_alt_next;
--	__hc32			hw_token;
--	__hc32			hw_buf[5];
--	__hc32			hw_buf_hi[5];
--} __aligned(32);
--
--struct fotg210_qh {
--	struct fotg210_qh_hw	*hw;		/* Must come first */
--	/* the rest is HCD-private */
--	dma_addr_t		qh_dma;		/* address of qh */
--	union fotg210_shadow	qh_next;	/* ptr to qh; or periodic */
--	struct list_head	qtd_list;	/* sw qtd list */
--	struct list_head	intr_node;	/* list of intr QHs */
--	struct fotg210_qtd	*dummy;
--	struct fotg210_qh	*unlink_next;	/* next on unlink list */
--
--	unsigned		unlink_cycle;
--
--	u8			needs_rescan;	/* Dequeue during giveback */
--	u8			qh_state;
--#define	QH_STATE_LINKED		1		/* HC sees this */
--#define	QH_STATE_UNLINK		2		/* HC may still see this */
--#define	QH_STATE_IDLE		3		/* HC doesn't see this */
--#define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on unlink q */
--#define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
--
--	u8			xacterrs;	/* XactErr retry counter */
--#define	QH_XACTERR_MAX		32		/* XactErr retry limit */
--
--	/* periodic schedule info */
--	u8			usecs;		/* intr bandwidth */
--	u8			gap_uf;		/* uframes split/csplit gap */
--	u8			c_usecs;	/* ... split completion bw */
--	u16			tt_usecs;	/* tt downstream bandwidth */
--	unsigned short		period;		/* polling interval */
--	unsigned short		start;		/* where polling starts */
--#define NO_FRAME ((unsigned short)~0)			/* pick new start */
--
--	struct usb_device	*dev;		/* access to TT */
--	unsigned		is_out:1;	/* bulk or intr OUT */
--	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
--};
--
--/*-------------------------------------------------------------------------*/
--
--/* description of one iso transaction (up to 3 KB data if highspeed) */
--struct fotg210_iso_packet {
--	/* These will be copied to iTD when scheduling */
--	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
--	__hc32			transaction;	/* itd->hw_transaction[i] |= */
--	u8			cross;		/* buf crosses pages */
--	/* for full speed OUT splits */
--	u32			buf1;
--};
--
--/* temporary schedule data for packets from iso urbs (both speeds)
-- * each packet is one logical usb transaction to the device (not TT),
-- * beginning at stream->next_uframe
-- */
--struct fotg210_iso_sched {
--	struct list_head	td_list;
--	unsigned		span;
--	struct fotg210_iso_packet	packet[];
--};
--
--/*
-- * fotg210_iso_stream - groups all (s)itds for this endpoint.
-- * acts like a qh would, if EHCI had them for ISO.
-- */
--struct fotg210_iso_stream {
--	/* first field matches fotg210_hq, but is NULL */
--	struct fotg210_qh_hw	*hw;
--
--	u8			bEndpointAddress;
--	u8			highspeed;
--	struct list_head	td_list;	/* queued itds */
--	struct list_head	free_list;	/* list of unused itds */
--	struct usb_device	*udev;
--	struct usb_host_endpoint *ep;
--
--	/* output of (re)scheduling */
--	int			next_uframe;
--	__hc32			splits;
--
--	/* the rest is derived from the endpoint descriptor,
--	 * trusting urb->interval == f(epdesc->bInterval) and
--	 * including the extra info for hw_bufp[0..2]
--	 */
--	u8			usecs, c_usecs;
--	u16			interval;
--	u16			tt_usecs;
--	u16			maxp;
--	u16			raw_mask;
--	unsigned		bandwidth;
--
--	/* This is used to initialize iTD's hw_bufp fields */
--	__hc32			buf0;
--	__hc32			buf1;
--	__hc32			buf2;
--
--	/* this is used to initialize sITD's tt info */
--	__hc32			address;
--};
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.95 Section 3.3
-- * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
-- *
-- * Schedule records for high speed iso xfers
-- */
--struct fotg210_itd {
--	/* first part defined by EHCI spec */
--	__hc32			hw_next;	/* see EHCI 3.3.1 */
--	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
--#define FOTG210_ISOC_ACTIVE	(1<<31)	/* activate transfer this slot */
--#define FOTG210_ISOC_BUF_ERR	(1<<30)	/* Data buffer error */
--#define FOTG210_ISOC_BABBLE	(1<<29)	/* babble detected */
--#define FOTG210_ISOC_XACTERR	(1<<28)	/* XactErr - transaction error */
--#define	FOTG210_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)
--#define	FOTG210_ITD_IOC		(1 << 15)	/* interrupt on complete */
--
--#define ITD_ACTIVE(fotg210)	cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
--
--	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
--	__hc32			hw_bufp_hi[7];	/* Appendix B */
--
--	/* the rest is HCD-private */
--	dma_addr_t		itd_dma;	/* for this itd */
--	union fotg210_shadow	itd_next;	/* ptr to periodic q entry */
--
--	struct urb		*urb;
--	struct fotg210_iso_stream	*stream;	/* endpoint's queue */
--	struct list_head	itd_list;	/* list of stream's itds */
--
--	/* any/all hw_transactions here may be used by that urb */
--	unsigned		frame;		/* where scheduled */
--	unsigned		pg;
--	unsigned		index[8];	/* in urb->iso_frame_desc */
--} __aligned(32);
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.96 Section 3.7
-- * Periodic Frame Span Traversal Node (FSTN)
-- *
-- * Manages split interrupt transactions (using TT) that span frame boundaries
-- * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
-- * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
-- * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
-- */
--struct fotg210_fstn {
--	__hc32			hw_next;	/* any periodic q entry */
--	__hc32			hw_prev;	/* qh or FOTG210_LIST_END */
--
--	/* the rest is HCD-private */
--	dma_addr_t		fstn_dma;
--	union fotg210_shadow	fstn_next;	/* ptr to periodic q entry */
--} __aligned(32);
--
--/*-------------------------------------------------------------------------*/
--
--/* Prepare the PORTSC wakeup flags during controller suspend/resume */
--
--#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
--		fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
--
--#define fotg210_prepare_ports_for_controller_resume(fotg210)		\
--		fotg210_adjust_port_wakeup_flags(fotg210, false, false)
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * Some EHCI controllers have a Transaction Translator built into the
-- * root hub. This is a non-standard feature.  Each controller will need
-- * to add code to the following inline functions, and call them as
-- * needed (mostly in root hub code).
-- */
--
--static inline unsigned int
--fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
--{
--	return (readl(&fotg210->regs->otgcsr)
--		& OTGCSR_HOST_SPD_TYP) >> 22;
--}
--
--/* Returns the speed of a device attached to a port on the root hub. */
--static inline unsigned int
--fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
--{
--	switch (fotg210_get_speed(fotg210, portsc)) {
--	case 0:
--		return 0;
--	case 1:
--		return USB_PORT_STAT_LOW_SPEED;
--	case 2:
--	default:
--		return USB_PORT_STAT_HIGH_SPEED;
--	}
--}
--
--/*-------------------------------------------------------------------------*/
--
--#define	fotg210_has_fsl_portno_bug(e)		(0)
--
--/*
-- * While most USB host controllers implement their registers in
-- * little-endian format, a minority (celleb companion chip) implement
-- * them in big endian format.
-- *
-- * This attempts to support either format at compile time without a
-- * runtime penalty, or both formats with the additional overhead
-- * of checking a flag bit.
-- *
-- */
--
--#define fotg210_big_endian_mmio(e)	0
--#define fotg210_big_endian_capbase(e)	0
--
--static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
--		__u32 __iomem *regs)
--{
--	return readl(regs);
--}
--
--static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
--		const unsigned int val, __u32 __iomem *regs)
--{
--	writel(val, regs);
--}
--
--/* cpu to fotg210 */
--static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
--{
--	return cpu_to_le32(x);
--}
--
--/* fotg210 to cpu */
--static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
--{
--	return le32_to_cpu(x);
--}
--
--static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
--			       const __hc32 *x)
--{
--	return le32_to_cpup(x);
--}
--
--/*-------------------------------------------------------------------------*/
--
--static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
--{
--	return fotg210_readl(fotg210, &fotg210->regs->frame_index);
--}
--
--/*-------------------------------------------------------------------------*/
--
--#endif /* __LINUX_FOTG210_H */
diff --git a/target/linux/gemini/patches-6.1/0003-usb-fotg210-Compile-into-one-module.patch b/target/linux/gemini/patches-6.1/0003-usb-fotg210-Compile-into-one-module.patch
deleted file mode 100644
index 5c7b4ff9c7..0000000000
--- a/target/linux/gemini/patches-6.1/0003-usb-fotg210-Compile-into-one-module.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From 0dbc77a99267a5efef0603a4b49ac02ece6a3f23 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:07 +0200
-Subject: [PATCH 03/29] usb: fotg210: Compile into one module
-
-It is since ages perfectly possible to compile both of these
-modules into the same kernel, which makes no sense since it
-is one piece of hardware.
-
-Compile one module named "fotg210.ko" for both HCD and UDC
-drivers by collecting the init calls into a fotg210-core.c
-file and start to centralize things handling one and the same
-piece of hardware.
-
-Stub out the initcalls if one or the other part of the driver
-was not selected.
-
-Tested by compiling one or the other or both of the drivers
-into the kernel and as modules.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-2-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -12,7 +12,7 @@ config USB_FOTG210
- if USB_FOTG210
- 
- config USB_FOTG210_HCD
--	tristate "Faraday FOTG210 USB Host Controller support"
-+	bool "Faraday FOTG210 USB Host Controller support"
- 	depends on USB
- 	help
- 	  Faraday FOTG210 is an OTG controller which can be configured as
-@@ -24,7 +24,7 @@ config USB_FOTG210_HCD
- 
- config USB_FOTG210_UDC
- 	depends on USB_GADGET
--	tristate "Faraday FOTG210 USB Peripheral Controller support"
-+	bool "Faraday FOTG210 USB Peripheral Controller support"
- 	help
- 	   Faraday USB2.0 OTG controller which can be configured as
- 	   high speed or full speed USB device. This driver suppports
---- a/drivers/usb/fotg210/Makefile
-+++ b/drivers/usb/fotg210/Makefile
-@@ -1,3 +1,10 @@
- # SPDX-License-Identifier: GPL-2.0
--obj-$(CONFIG_USB_FOTG210_HCD)	+= fotg210-hcd.o
--obj-$(CONFIG_USB_FOTG210_UDC)	+= fotg210-udc.o
-+
-+# This setup links the different object files into one single
-+# module so we don't have to EXPORT() a lot of internal symbols
-+# or create unnecessary submodules.
-+fotg210-objs-y				+= fotg210-core.o
-+fotg210-objs-$(CONFIG_USB_FOTG210_HCD)	+= fotg210-hcd.o
-+fotg210-objs-$(CONFIG_USB_FOTG210_UDC)	+= fotg210-udc.o
-+fotg210-objs				:= $(fotg210-objs-y)
-+obj-$(CONFIG_USB_FOTG210)		+= fotg210.o
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -0,0 +1,79 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Central probing code for the FOTG210 dual role driver
-+ * We register one driver for the hardware and then we decide
-+ * whether to proceed with probing the host or the peripheral
-+ * driver.
-+ */
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb.h>
-+
-+#include "fotg210.h"
-+
-+static int fotg210_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD)) {
-+		ret = fotg210_hcd_probe(pdev);
-+		if (ret)
-+			return ret;
-+	}
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+		ret = fotg210_udc_probe(pdev);
-+
-+	return ret;
-+}
-+
-+static int fotg210_remove(struct platform_device *pdev)
-+{
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+		fotg210_hcd_remove(pdev);
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+		fotg210_udc_remove(pdev);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id fotg210_of_match[] = {
-+	{ .compatible = "faraday,fotg210" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, fotg210_of_match);
-+#endif
-+
-+static struct platform_driver fotg210_driver = {
-+	.driver = {
-+		.name   = "fotg210",
-+		.of_match_table = of_match_ptr(fotg210_of_match),
-+	},
-+	.probe  = fotg210_probe,
-+	.remove = fotg210_remove,
-+};
-+
-+static int __init fotg210_init(void)
-+{
-+	if (usb_disabled())
-+		return -ENODEV;
-+
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+		fotg210_hcd_init();
-+	return platform_driver_register(&fotg210_driver);
-+}
-+module_init(fotg210_init);
-+
-+static void __exit fotg210_cleanup(void)
-+{
-+	platform_driver_unregister(&fotg210_driver);
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+		fotg210_hcd_cleanup();
-+}
-+module_exit(fotg210_cleanup);
-+
-+MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("FOTG210 Dual Role Controller Driver");
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -39,8 +39,8 @@
- #include <asm/irq.h>
- #include <asm/unaligned.h>
- 
--#define DRIVER_AUTHOR "Yuan-Hsin Chen"
--#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
-+#include "fotg210.h"
-+
- static const char hcd_name[] = "fotg210_hcd";
- 
- #undef FOTG210_URB_TRACE
-@@ -5490,9 +5490,6 @@ static int fotg210_get_frame(struct usb_
-  * functions  and in order to facilitate role switching we cannot
-  * give the fotg210 driver exclusive access to those.
-  */
--MODULE_DESCRIPTION(DRIVER_DESC);
--MODULE_AUTHOR(DRIVER_AUTHOR);
--MODULE_LICENSE("GPL");
- 
- static const struct hc_driver fotg210_fotg210_hc_driver = {
- 	.description		= hcd_name,
-@@ -5560,7 +5557,7 @@ static void fotg210_init(struct fotg210_
-  * then invokes the start() method for the HCD associated with it
-  * through the hotplug entry's driver_data.
-  */
--static int fotg210_hcd_probe(struct platform_device *pdev)
-+int fotg210_hcd_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
- 	struct usb_hcd *hcd;
-@@ -5652,7 +5649,7 @@ fail_create_hcd:
-  * @dev: USB Host Controller being removed
-  *
-  */
--static int fotg210_hcd_remove(struct platform_device *pdev)
-+int fotg210_hcd_remove(struct platform_device *pdev)
- {
- 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
- 	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-@@ -5668,27 +5665,8 @@ static int fotg210_hcd_remove(struct pla
- 	return 0;
- }
- 
--#ifdef CONFIG_OF
--static const struct of_device_id fotg210_of_match[] = {
--	{ .compatible = "faraday,fotg210" },
--	{},
--};
--MODULE_DEVICE_TABLE(of, fotg210_of_match);
--#endif
--
--static struct platform_driver fotg210_hcd_driver = {
--	.driver = {
--		.name   = "fotg210-hcd",
--		.of_match_table = of_match_ptr(fotg210_of_match),
--	},
--	.probe  = fotg210_hcd_probe,
--	.remove = fotg210_hcd_remove,
--};
--
--static int __init fotg210_hcd_init(void)
-+int __init fotg210_hcd_init(void)
- {
--	int retval = 0;
--
- 	if (usb_disabled())
- 		return -ENODEV;
- 
-@@ -5704,24 +5682,11 @@ static int __init fotg210_hcd_init(void)
- 
- 	fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
- 
--	retval = platform_driver_register(&fotg210_hcd_driver);
--	if (retval < 0)
--		goto clean;
--	return retval;
--
--clean:
--	debugfs_remove(fotg210_debug_root);
--	fotg210_debug_root = NULL;
--
--	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
--	return retval;
-+	return 0;
- }
--module_init(fotg210_hcd_init);
- 
--static void __exit fotg210_hcd_cleanup(void)
-+void __exit fotg210_hcd_cleanup(void)
- {
--	platform_driver_unregister(&fotg210_hcd_driver);
- 	debugfs_remove(fotg210_debug_root);
- 	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
- }
--module_exit(fotg210_hcd_cleanup);
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -16,6 +16,7 @@
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
- 
-+#include "fotg210.h"
- #include "fotg210-udc.h"
- 
- #define	DRIVER_DESC	"FOTG210 USB Device Controller Driver"
-@@ -1081,7 +1082,7 @@ static const struct usb_gadget_ops fotg2
- 	.udc_stop		= fotg210_udc_stop,
- };
- 
--static int fotg210_udc_remove(struct platform_device *pdev)
-+int fotg210_udc_remove(struct platform_device *pdev)
- {
- 	struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
- 	int i;
-@@ -1098,7 +1099,7 @@ static int fotg210_udc_remove(struct pla
- 	return 0;
- }
- 
--static int fotg210_udc_probe(struct platform_device *pdev)
-+int fotg210_udc_probe(struct platform_device *pdev)
- {
- 	struct resource *res, *ires;
- 	struct fotg210_udc *fotg210 = NULL;
-@@ -1223,17 +1224,3 @@ err_alloc:
- err:
- 	return ret;
- }
--
--static struct platform_driver fotg210_driver = {
--	.driver		= {
--		.name =	udc_name,
--	},
--	.probe		= fotg210_udc_probe,
--	.remove		= fotg210_udc_remove,
--};
--
--module_platform_driver(fotg210_driver);
--
--MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
--MODULE_LICENSE("GPL");
--MODULE_DESCRIPTION(DRIVER_DESC);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -0,0 +1,42 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#ifndef __FOTG210_H
-+#define __FOTG210_H
-+
-+#ifdef CONFIG_USB_FOTG210_HCD
-+int fotg210_hcd_probe(struct platform_device *pdev);
-+int fotg210_hcd_remove(struct platform_device *pdev);
-+int fotg210_hcd_init(void);
-+void fotg210_hcd_cleanup(void);
-+#else
-+static inline int fotg210_hcd_probe(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+static inline int fotg210_hcd_remove(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+static inline int fotg210_hcd_init(void)
-+{
-+	return 0;
-+}
-+static inline void fotg210_hcd_cleanup(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_USB_FOTG210_UDC
-+int fotg210_udc_probe(struct platform_device *pdev);
-+int fotg210_udc_remove(struct platform_device *pdev);
-+#else
-+static inline int fotg210_udc_probe(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+static inline int fotg210_udc_remove(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+#endif
-+
-+#endif /* __FOTG210_H */
diff --git a/target/linux/gemini/patches-6.1/0004-usb-fotg210-Select-subdriver-by-mode.patch b/target/linux/gemini/patches-6.1/0004-usb-fotg210-Select-subdriver-by-mode.patch
deleted file mode 100644
index 6a19a0aa4d..0000000000
--- a/target/linux/gemini/patches-6.1/0004-usb-fotg210-Select-subdriver-by-mode.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 7c0b661926097e935f2711857596fc2277b2304a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:08 +0200
-Subject: [PATCH 04/29] usb: fotg210: Select subdriver by mode
-
-Check which mode the hardware is in, and selecte the peripheral
-driver if the hardware is in explicit peripheral mode, otherwise
-select host mode.
-
-This should solve the immediate problem that both subdrivers
-can get probed.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -10,30 +10,37 @@
- #include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/usb.h>
-+#include <linux/usb/otg.h>
- 
- #include "fotg210.h"
- 
- static int fotg210_probe(struct platform_device *pdev)
- {
-+	struct device *dev = &pdev->dev;
-+	enum usb_dr_mode mode;
- 	int ret;
- 
--	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD)) {
--		ret = fotg210_hcd_probe(pdev);
--		if (ret)
--			return ret;
--	}
--	if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+	mode = usb_get_dr_mode(dev);
-+
-+	if (mode == USB_DR_MODE_PERIPHERAL)
- 		ret = fotg210_udc_probe(pdev);
-+	else
-+		ret = fotg210_hcd_probe(pdev);
- 
- 	return ret;
- }
- 
- static int fotg210_remove(struct platform_device *pdev)
- {
--	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
--		fotg210_hcd_remove(pdev);
--	if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+	struct device *dev = &pdev->dev;
-+	enum usb_dr_mode mode;
-+
-+	mode = usb_get_dr_mode(dev);
-+
-+	if (mode == USB_DR_MODE_PERIPHERAL)
- 		fotg210_udc_remove(pdev);
-+	else
-+		fotg210_hcd_remove(pdev);
- 
- 	return 0;
- }
diff --git a/target/linux/gemini/patches-6.1/0005-usb-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-6.1/0005-usb-fotg2-add-Gemini-specific-handling.patch
deleted file mode 100644
index daf8d85611..0000000000
--- a/target/linux/gemini/patches-6.1/0005-usb-fotg2-add-Gemini-specific-handling.patch
+++ /dev/null
@@ -1,135 +0,0 @@
-From f7f6c8aca91093e2f886ec97910b1a7d9a69bf9b Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 9 Nov 2022 21:05:54 +0100
-Subject: [PATCH 05/29] usb: fotg2: add Gemini-specific handling
-
-The Cortina Systems Gemini has bolted on a PHY inside the
-silicon that can be handled by six bits in a MISC register in
-the system controller.
-
-If we are running on Gemini, look up a syscon regmap through
-a phandle and enable VBUS and optionally the Mini-B connector.
-
-If the device is flagged as "wakeup-source" using the standard
-DT bindings, we also enable this in the global controller for
-respective port.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221109200554.1957185-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -5,6 +5,7 @@ config USB_FOTG210
- 	depends on USB || USB_GADGET
- 	depends on HAS_DMA && HAS_IOMEM
- 	default ARCH_GEMINI
-+	select MFD_SYSCON
- 	help
- 	  Faraday FOTG210 is a dual-mode USB controller that can act
- 	  in both host controller and peripheral controller mode.
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -5,15 +5,86 @@
-  * whether to proceed with probing the host or the peripheral
-  * driver.
-  */
-+#include <linux/bitops.h>
- #include <linux/device.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/platform_device.h>
-+#include <linux/regmap.h>
- #include <linux/usb.h>
- #include <linux/usb/otg.h>
- 
- #include "fotg210.h"
- 
-+/*
-+ * Gemini-specific initialization function, only executed on the
-+ * Gemini SoC using the global misc control register.
-+ *
-+ * The gemini USB blocks are connected to either Mini-A (host mode) or
-+ * Mini-B (peripheral mode) plugs. There is no role switch support on the
-+ * Gemini SoC, just either-or.
-+ */
-+#define GEMINI_GLOBAL_MISC_CTRL		0x30
-+#define GEMINI_MISC_USB0_WAKEUP		BIT(14)
-+#define GEMINI_MISC_USB1_WAKEUP		BIT(15)
-+#define GEMINI_MISC_USB0_VBUS_ON	BIT(22)
-+#define GEMINI_MISC_USB1_VBUS_ON	BIT(23)
-+#define GEMINI_MISC_USB0_MINI_B		BIT(29)
-+#define GEMINI_MISC_USB1_MINI_B		BIT(30)
-+
-+static int fotg210_gemini_init(struct device *dev, struct resource *res,
-+			       enum usb_dr_mode mode)
-+{
-+	struct device_node *np = dev->of_node;
-+	struct regmap *map;
-+	bool wakeup;
-+	u32 mask, val;
-+	int ret;
-+
-+	map = syscon_regmap_lookup_by_phandle(np, "syscon");
-+	if (IS_ERR(map)) {
-+		dev_err(dev, "no syscon\n");
-+		return PTR_ERR(map);
-+	}
-+	wakeup = of_property_read_bool(np, "wakeup-source");
-+
-+	/*
-+	 * Figure out if this is USB0 or USB1 by simply checking the
-+	 * physical base address.
-+	 */
-+	mask = 0;
-+	if (res->start == 0x69000000) {
-+		mask = GEMINI_MISC_USB1_VBUS_ON | GEMINI_MISC_USB1_MINI_B |
-+			GEMINI_MISC_USB1_WAKEUP;
-+		if (mode == USB_DR_MODE_HOST)
-+			val = GEMINI_MISC_USB1_VBUS_ON;
-+		else
-+			val = GEMINI_MISC_USB1_MINI_B;
-+		if (wakeup)
-+			val |= GEMINI_MISC_USB1_WAKEUP;
-+	} else {
-+		mask = GEMINI_MISC_USB0_VBUS_ON | GEMINI_MISC_USB0_MINI_B |
-+			GEMINI_MISC_USB0_WAKEUP;
-+		if (mode == USB_DR_MODE_HOST)
-+			val = GEMINI_MISC_USB0_VBUS_ON;
-+		else
-+			val = GEMINI_MISC_USB0_MINI_B;
-+		if (wakeup)
-+			val |= GEMINI_MISC_USB0_WAKEUP;
-+	}
-+
-+	ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
-+	if (ret) {
-+		dev_err(dev, "failed to initialize Gemini PHY\n");
-+		return ret;
-+	}
-+
-+	dev_info(dev, "initialized Gemini PHY in %s mode\n",
-+		 (mode == USB_DR_MODE_HOST) ? "host" : "gadget");
-+	return 0;
-+}
-+
- static int fotg210_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-@@ -22,6 +93,15 @@ static int fotg210_probe(struct platform
- 
- 	mode = usb_get_dr_mode(dev);
- 
-+	if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
-+		struct resource *res;
-+
-+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+		ret = fotg210_gemini_init(dev, res, mode);
-+		if (ret)
-+			return ret;
-+	}
-+
- 	if (mode == USB_DR_MODE_PERIPHERAL)
- 		ret = fotg210_udc_probe(pdev);
- 	else
diff --git a/target/linux/gemini/patches-6.1/0006-usb-fotg210-Fix-Kconfig-for-USB-host-modules.patch b/target/linux/gemini/patches-6.1/0006-usb-fotg210-Fix-Kconfig-for-USB-host-modules.patch
deleted file mode 100644
index bd3a42415a..0000000000
--- a/target/linux/gemini/patches-6.1/0006-usb-fotg210-Fix-Kconfig-for-USB-host-modules.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 6e002d41889bc52213a26ff91338d340505e0336 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 11 Nov 2022 15:48:21 +0100
-Subject: [PATCH 06/29] usb: fotg210: Fix Kconfig for USB host modules
-
-The kernel robot reports a link failure when activating the
-FOTG210 host subdriver with =y on a system where the USB host
-core is a module (CONFIG_USB=m).
-
-This is a bit of special case, so mimic the Kconfig incantations
-from DWC3: let the subdrivers for host or peripheral depend
-on the host or gadget support being =y or the same as the
-FOTG210 core itself.
-
-This should ensure that either:
-
-- The host (CONFIG_USB) or gadget (CONFIG_GADGET) is compiled
-  in and then the FOTG210 can be either module or compiled
-  in.
-
-- The host or gadget is modular, and then the FOTG210 module
-  must be a module too, or we cannot resolve the symbols
-  at link time.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Link: https://lore.kernel.org/linux-usb/202211112132.0BUPGKCd-lkp@intel.com/
-Cc: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221111144821.113665-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -14,7 +14,7 @@ if USB_FOTG210
- 
- config USB_FOTG210_HCD
- 	bool "Faraday FOTG210 USB Host Controller support"
--	depends on USB
-+	depends on USB=y || USB=USB_FOTG210
- 	help
- 	  Faraday FOTG210 is an OTG controller which can be configured as
- 	  an USB2.0 host. It is designed to meet USB2.0 EHCI specification
-@@ -24,7 +24,7 @@ config USB_FOTG210_HCD
- 	  module will be called fotg210-hcd.
- 
- config USB_FOTG210_UDC
--	depends on USB_GADGET
-+	depends on USB_GADGET=y || USB_GADGET=USB_FOTG210
- 	bool "Faraday FOTG210 USB Peripheral Controller support"
- 	help
- 	   Faraday USB2.0 OTG controller which can be configured as
diff --git a/target/linux/gemini/patches-6.1/0007-usb-USB_FOTG210-should-depend-on-ARCH_GEMINI.patch b/target/linux/gemini/patches-6.1/0007-usb-USB_FOTG210-should-depend-on-ARCH_GEMINI.patch
deleted file mode 100644
index 6afef0d820..0000000000
--- a/target/linux/gemini/patches-6.1/0007-usb-USB_FOTG210-should-depend-on-ARCH_GEMINI.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 466b10510add46afd21ca19505b29d35ad853370 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert+renesas@glider.be>
-Date: Mon, 21 Nov 2022 16:22:19 +0100
-Subject: [PATCH 07/29] usb: USB_FOTG210 should depend on ARCH_GEMINI
-
-The Faraday Technology FOTG210 USB2 Dual Role Controller is only present
-on Cortina Systems Gemini SoCs.  Hence add a dependency on ARCH_GEMINI,
-to prevent asking the user about its drivers when configuring a kernel
-without Cortina Systems Gemini SoC support.
-
-Fixes: 1dd33a9f1b95ab59 ("usb: fotg210: Collect pieces of dual mode controller")
-Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/a989b3b798ecaf3b45f35160e30e605636d66a77.1669044086.git.geert+renesas@glider.be
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -4,6 +4,7 @@ config USB_FOTG210
- 	tristate "Faraday FOTG210 USB2 Dual Role controller"
- 	depends on USB || USB_GADGET
- 	depends on HAS_DMA && HAS_IOMEM
-+	depends on ARCH_GEMINI || COMPILE_TEST
- 	default ARCH_GEMINI
- 	select MFD_SYSCON
- 	help
diff --git a/target/linux/gemini/patches-6.1/0008-fotg210-udc-Use-dev-pointer-in-probe-and-dev_message.patch b/target/linux/gemini/patches-6.1/0008-fotg210-udc-Use-dev-pointer-in-probe-and-dev_message.patch
deleted file mode 100644
index 2a595e885d..0000000000
--- a/target/linux/gemini/patches-6.1/0008-fotg210-udc-Use-dev-pointer-in-probe-and-dev_message.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 27cd321a365fecac857e41ad1681062994142e4a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:51:58 +0100
-Subject: [PATCH 08/29] fotg210-udc: Use dev pointer in probe and dev_messages
-
-Add a local struct device *dev pointer and use dev_err()
-etc to report status.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1104,6 +1104,7 @@ int fotg210_udc_probe(struct platform_de
- 	struct resource *res, *ires;
- 	struct fotg210_udc *fotg210 = NULL;
- 	struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
-+	struct device *dev = &pdev->dev;
- 	int ret = 0;
- 	int i;
- 
-@@ -1135,7 +1136,7 @@ int fotg210_udc_probe(struct platform_de
- 
- 	fotg210->reg = ioremap(res->start, resource_size(res));
- 	if (fotg210->reg == NULL) {
--		pr_err("ioremap error.\n");
-+		dev_err(dev, "ioremap error\n");
- 		goto err_alloc;
- 	}
- 
-@@ -1146,8 +1147,8 @@ int fotg210_udc_probe(struct platform_de
- 	fotg210->gadget.ops = &fotg210_gadget_ops;
- 
- 	fotg210->gadget.max_speed = USB_SPEED_HIGH;
--	fotg210->gadget.dev.parent = &pdev->dev;
--	fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
-+	fotg210->gadget.dev.parent = dev;
-+	fotg210->gadget.dev.dma_mask = dev->dma_mask;
- 	fotg210->gadget.name = udc_name;
- 
- 	INIT_LIST_HEAD(&fotg210->gadget.ep_list);
-@@ -1195,15 +1196,15 @@ int fotg210_udc_probe(struct platform_de
- 	ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
- 			  udc_name, fotg210);
- 	if (ret < 0) {
--		pr_err("request_irq error (%d)\n", ret);
-+		dev_err(dev, "request_irq error (%d)\n", ret);
- 		goto err_req;
- 	}
- 
--	ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
-+	ret = usb_add_gadget_udc(dev, &fotg210->gadget);
- 	if (ret)
- 		goto err_add_udc;
- 
--	dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
-+	dev_info(dev, "version %s\n", DRIVER_VERSION);
- 
- 	return 0;
- 
diff --git a/target/linux/gemini/patches-6.1/0009-fotg210-udc-Support-optional-external-PHY.patch b/target/linux/gemini/patches-6.1/0009-fotg210-udc-Support-optional-external-PHY.patch
deleted file mode 100644
index 498875c535..0000000000
--- a/target/linux/gemini/patches-6.1/0009-fotg210-udc-Support-optional-external-PHY.patch
+++ /dev/null
@@ -1,158 +0,0 @@
-From 03e4b585ac947e2d422bedf03179bbfec3aca3cf Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:51:59 +0100
-Subject: [PATCH 09/29] fotg210-udc: Support optional external PHY
-
-This adds support for an optional external PHY to the FOTG210
-UDC driver.
-
-Tested with the GPIO VBUS PHY driver on the Gemini SoC.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-2-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,6 +15,8 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-+#include <linux/usb/otg.h>
-+#include <linux/usb/phy.h>
- 
- #include "fotg210.h"
- #include "fotg210-udc.h"
-@@ -1022,10 +1024,18 @@ static int fotg210_udc_start(struct usb_
- {
- 	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
- 	u32 value;
-+	int ret;
- 
- 	/* hook up the driver */
- 	fotg210->driver = driver;
- 
-+	if (!IS_ERR_OR_NULL(fotg210->phy)) {
-+		ret = otg_set_peripheral(fotg210->phy->otg,
-+					 &fotg210->gadget);
-+		if (ret)
-+			dev_err(fotg210->dev, "can't bind to phy\n");
-+	}
-+
- 	/* enable device global interrupt */
- 	value = ioread32(fotg210->reg + FOTG210_DMCR);
- 	value |= DMCR_GLINT_EN;
-@@ -1067,6 +1077,9 @@ static int fotg210_udc_stop(struct usb_g
- 	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
- 	unsigned long	flags;
- 
-+	if (!IS_ERR_OR_NULL(fotg210->phy))
-+		return otg_set_peripheral(fotg210->phy->otg, NULL);
-+
- 	spin_lock_irqsave(&fotg210->lock, flags);
- 
- 	fotg210_init(fotg210);
-@@ -1082,12 +1095,50 @@ static const struct usb_gadget_ops fotg2
- 	.udc_stop		= fotg210_udc_stop,
- };
- 
-+/**
-+ * fotg210_phy_event - Called by phy upon VBus event
-+ * @nb: notifier block
-+ * @action: phy action, is vbus connect or disconnect
-+ * @data: the usb_gadget structure in fotg210
-+ *
-+ * Called by the USB Phy when a cable connect or disconnect is sensed.
-+ *
-+ * Returns NOTIFY_OK or NOTIFY_DONE
-+ */
-+static int fotg210_phy_event(struct notifier_block *nb, unsigned long action,
-+			     void *data)
-+{
-+	struct usb_gadget *gadget = data;
-+
-+	if (!gadget)
-+		return NOTIFY_DONE;
-+
-+	switch (action) {
-+	case USB_EVENT_VBUS:
-+		usb_gadget_vbus_connect(gadget);
-+		return NOTIFY_OK;
-+	case USB_EVENT_NONE:
-+		usb_gadget_vbus_disconnect(gadget);
-+		return NOTIFY_OK;
-+	default:
-+		return NOTIFY_DONE;
-+	}
-+}
-+
-+static struct notifier_block fotg210_phy_notifier = {
-+	.notifier_call = fotg210_phy_event,
-+};
-+
- int fotg210_udc_remove(struct platform_device *pdev)
- {
- 	struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
- 	int i;
- 
- 	usb_del_gadget_udc(&fotg210->gadget);
-+	if (!IS_ERR_OR_NULL(fotg210->phy)) {
-+		usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
-+		usb_put_phy(fotg210->phy);
-+	}
- 	iounmap(fotg210->reg);
- 	free_irq(platform_get_irq(pdev, 0), fotg210);
- 
-@@ -1127,6 +1178,22 @@ int fotg210_udc_probe(struct platform_de
- 	if (fotg210 == NULL)
- 		goto err;
- 
-+	fotg210->dev = dev;
-+
-+	fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
-+	if (IS_ERR(fotg210->phy)) {
-+		ret = PTR_ERR(fotg210->phy);
-+		if (ret == -EPROBE_DEFER)
-+			goto err;
-+		dev_info(dev, "no PHY found\n");
-+		fotg210->phy = NULL;
-+	} else {
-+		ret = usb_phy_init(fotg210->phy);
-+		if (ret)
-+			goto err;
-+		dev_info(dev, "found and initialized PHY\n");
-+	}
-+
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
- 		_ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
- 		if (_ep[i] == NULL)
-@@ -1200,6 +1267,9 @@ int fotg210_udc_probe(struct platform_de
- 		goto err_req;
- 	}
- 
-+	if (!IS_ERR_OR_NULL(fotg210->phy))
-+		usb_register_notifier(fotg210->phy, &fotg210_phy_notifier);
-+
- 	ret = usb_add_gadget_udc(dev, &fotg210->gadget);
- 	if (ret)
- 		goto err_add_udc;
-@@ -1209,6 +1279,8 @@ int fotg210_udc_probe(struct platform_de
- 	return 0;
- 
- err_add_udc:
-+	if (!IS_ERR_OR_NULL(fotg210->phy))
-+		usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
- 	free_irq(ires->start, fotg210);
- 
- err_req:
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -234,6 +234,8 @@ struct fotg210_udc {
- 
- 	unsigned long		irq_trigger;
- 
-+	struct device			*dev;
-+	struct usb_phy			*phy;
- 	struct usb_gadget		gadget;
- 	struct usb_gadget_driver	*driver;
- 
diff --git a/target/linux/gemini/patches-6.1/0010-fotg210-udc-Handle-PCLK.patch b/target/linux/gemini/patches-6.1/0010-fotg210-udc-Handle-PCLK.patch
deleted file mode 100644
index 8da3de3b47..0000000000
--- a/target/linux/gemini/patches-6.1/0010-fotg210-udc-Handle-PCLK.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 772ea3ec2b9363b45ef9a4768ea205f758c3debc Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:52:00 +0100
-Subject: [PATCH 10/29] fotg210-udc: Handle PCLK
-
-This adds optional handling of the peripheral clock PCLK.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,6 +15,7 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-+#include <linux/clk.h>
- #include <linux/usb/otg.h>
- #include <linux/usb/phy.h>
- 
-@@ -1145,6 +1146,10 @@ int fotg210_udc_remove(struct platform_d
- 	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- 		kfree(fotg210->ep[i]);
-+
-+	if (!IS_ERR(fotg210->pclk))
-+		clk_disable_unprepare(fotg210->pclk);
-+
- 	kfree(fotg210);
- 
- 	return 0;
-@@ -1180,17 +1185,34 @@ int fotg210_udc_probe(struct platform_de
- 
- 	fotg210->dev = dev;
- 
-+	/* It's OK not to supply this clock */
-+	fotg210->pclk = devm_clk_get(dev, "PCLK");
-+	if (!IS_ERR(fotg210->pclk)) {
-+		ret = clk_prepare_enable(fotg210->pclk);
-+		if (ret) {
-+			dev_err(dev, "failed to enable PCLK\n");
-+			return ret;
-+		}
-+	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-+		/*
-+		 * Percolate deferrals, for anything else,
-+		 * just live without the clocking.
-+		 */
-+		ret = -EPROBE_DEFER;
-+		goto err;
-+	}
-+
- 	fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
- 	if (IS_ERR(fotg210->phy)) {
- 		ret = PTR_ERR(fotg210->phy);
- 		if (ret == -EPROBE_DEFER)
--			goto err;
-+			goto err_pclk;
- 		dev_info(dev, "no PHY found\n");
- 		fotg210->phy = NULL;
- 	} else {
- 		ret = usb_phy_init(fotg210->phy);
- 		if (ret)
--			goto err;
-+			goto err_pclk;
- 		dev_info(dev, "found and initialized PHY\n");
- 	}
- 
-@@ -1292,6 +1314,10 @@ err_map:
- err_alloc:
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- 		kfree(fotg210->ep[i]);
-+err_pclk:
-+	if (!IS_ERR(fotg210->pclk))
-+		clk_disable_unprepare(fotg210->pclk);
-+
- 	kfree(fotg210);
- 
- err:
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -231,6 +231,7 @@ struct fotg210_ep {
- struct fotg210_udc {
- 	spinlock_t		lock; /* protect the struct */
- 	void __iomem		*reg;
-+	struct clk		*pclk;
- 
- 	unsigned long		irq_trigger;
- 
diff --git a/target/linux/gemini/patches-6.1/0011-fotg210-udc-Get-IRQ-using-platform_get_irq.patch b/target/linux/gemini/patches-6.1/0011-fotg210-udc-Get-IRQ-using-platform_get_irq.patch
deleted file mode 100644
index 9544de7cb0..0000000000
--- a/target/linux/gemini/patches-6.1/0011-fotg210-udc-Get-IRQ-using-platform_get_irq.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From eda686d41e298a9d16708d2ec8d12d8e682dd7ca Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:52:01 +0100
-Subject: [PATCH 11/29] fotg210-udc: Get IRQ using platform_get_irq()
-
-The platform_get_irq() is necessary to use to get dynamic
-IRQ resolution when instantiating the device from the
-device tree. IRQs are not passed as resources in that
-case.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-4-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1157,10 +1157,11 @@ int fotg210_udc_remove(struct platform_d
- 
- int fotg210_udc_probe(struct platform_device *pdev)
- {
--	struct resource *res, *ires;
-+	struct resource *res;
- 	struct fotg210_udc *fotg210 = NULL;
- 	struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
- 	struct device *dev = &pdev->dev;
-+	int irq;
- 	int ret = 0;
- 	int i;
- 
-@@ -1170,9 +1171,9 @@ int fotg210_udc_probe(struct platform_de
- 		return -ENODEV;
- 	}
- 
--	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
--	if (!ires) {
--		pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		pr_err("could not get irq\n");
- 		return -ENODEV;
- 	}
- 
-@@ -1202,7 +1203,7 @@ int fotg210_udc_probe(struct platform_de
- 		goto err;
- 	}
- 
--	fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
-+	fotg210->phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
- 	if (IS_ERR(fotg210->phy)) {
- 		ret = PTR_ERR(fotg210->phy);
- 		if (ret == -EPROBE_DEFER)
-@@ -1282,7 +1283,7 @@ int fotg210_udc_probe(struct platform_de
- 
- 	fotg210_disable_unplug(fotg210);
- 
--	ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
-+	ret = request_irq(irq, fotg210_irq, IRQF_SHARED,
- 			  udc_name, fotg210);
- 	if (ret < 0) {
- 		dev_err(dev, "request_irq error (%d)\n", ret);
-@@ -1303,7 +1304,7 @@ int fotg210_udc_probe(struct platform_de
- err_add_udc:
- 	if (!IS_ERR_OR_NULL(fotg210->phy))
- 		usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
--	free_irq(ires->start, fotg210);
-+	free_irq(irq, fotg210);
- 
- err_req:
- 	fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
diff --git a/target/linux/gemini/patches-6.1/0012-usb-fotg210-udc-Remove-a-useless-assignment.patch b/target/linux/gemini/patches-6.1/0012-usb-fotg210-udc-Remove-a-useless-assignment.patch
deleted file mode 100644
index 8c33c50b2c..0000000000
--- a/target/linux/gemini/patches-6.1/0012-usb-fotg210-udc-Remove-a-useless-assignment.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 7889a2f0256c55e0184dffd0001d0782f9e4cb83 Mon Sep 17 00:00:00 2001
-From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Date: Mon, 14 Nov 2022 21:38:04 +0100
-Subject: [PATCH 12/29] usb: fotg210-udc: Remove a useless assignment
-
-There is no need to use an intermediate array for these memory allocations,
-so, axe it.
-
-While at it, turn a '== NULL' into a shorter '!' when testing memory
-allocation failure.
-
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/deab9696fc4000499470e7ccbca7c36fca17bd4e.1668458274.git.christophe.jaillet@wanadoo.fr
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1159,7 +1159,6 @@ int fotg210_udc_probe(struct platform_de
- {
- 	struct resource *res;
- 	struct fotg210_udc *fotg210 = NULL;
--	struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
- 	struct device *dev = &pdev->dev;
- 	int irq;
- 	int ret = 0;
-@@ -1218,10 +1217,9 @@ int fotg210_udc_probe(struct platform_de
- 	}
- 
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
--		_ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
--		if (_ep[i] == NULL)
-+		fotg210->ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-+		if (!fotg210->ep[i])
- 			goto err_alloc;
--		fotg210->ep[i] = _ep[i];
- 	}
- 
- 	fotg210->reg = ioremap(res->start, resource_size(res));
diff --git a/target/linux/gemini/patches-6.1/0013-usb-fotg210-udc-fix-potential-memory-leak-in-fotg210.patch b/target/linux/gemini/patches-6.1/0013-usb-fotg210-udc-fix-potential-memory-leak-in-fotg210.patch
deleted file mode 100644
index 178135662f..0000000000
--- a/target/linux/gemini/patches-6.1/0013-usb-fotg210-udc-fix-potential-memory-leak-in-fotg210.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 7b95ade85ac18eec63e81ac58a482b3e88361ffd Mon Sep 17 00:00:00 2001
-From: Yi Yang <yiyang13@huawei.com>
-Date: Fri, 2 Dec 2022 09:21:26 +0800
-Subject: [PATCH 13/29] usb: fotg210-udc: fix potential memory leak in
- fotg210_udc_probe()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In fotg210_udc_probe(), if devm_clk_get() or clk_prepare_enable()
-fails, 'fotg210' will not be freed, which will lead to a memory leak.
-Fix it by moving kfree() to a proper location.
-
-In addition，we can use "return -ENOMEM" instead of "goto err"
-to simplify the code.
-
-Fixes: 718a38d092ec ("fotg210-udc: Handle PCLK")
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: Yi Yang <yiyang13@huawei.com>
-Link: https://lore.kernel.org/r/20221202012126.246953-1-yiyang13@huawei.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1176,12 +1176,10 @@ int fotg210_udc_probe(struct platform_de
- 		return -ENODEV;
- 	}
- 
--	ret = -ENOMEM;
--
- 	/* initialize udc */
- 	fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
- 	if (fotg210 == NULL)
--		goto err;
-+		return -ENOMEM;
- 
- 	fotg210->dev = dev;
- 
-@@ -1191,7 +1189,7 @@ int fotg210_udc_probe(struct platform_de
- 		ret = clk_prepare_enable(fotg210->pclk);
- 		if (ret) {
- 			dev_err(dev, "failed to enable PCLK\n");
--			return ret;
-+			goto err;
- 		}
- 	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
- 		/*
-@@ -1317,8 +1315,7 @@ err_pclk:
- 	if (!IS_ERR(fotg210->pclk))
- 		clk_disable_unprepare(fotg210->pclk);
- 
--	kfree(fotg210);
--
- err:
-+	kfree(fotg210);
- 	return ret;
- }
diff --git a/target/linux/gemini/patches-6.1/0014-usb-fotg210-fix-OTG-only-build.patch b/target/linux/gemini/patches-6.1/0014-usb-fotg210-fix-OTG-only-build.patch
deleted file mode 100644
index acdf1796f3..0000000000
--- a/target/linux/gemini/patches-6.1/0014-usb-fotg210-fix-OTG-only-build.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From d8eed400495029ba551704ff0fae1dad87332291 Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Thu, 15 Dec 2022 17:57:20 +0100
-Subject: [PATCH 14/29] usb: fotg210: fix OTG-only build
-
-The fotg210 module combines the HCD and OTG drivers, which then
-fails to build when only the USB gadget support is enabled
-in the kernel but host support is not:
-
-aarch64-linux-ld: drivers/usb/fotg210/fotg210-core.o: in function `fotg210_init':
-fotg210-core.c:(.init.text+0xc): undefined reference to `usb_disabled'
-
-Move the check for usb_disabled() after the check for the HCD module,
-and let the OTG driver still be probed in this configuration.
-
-A nicer approach might be to have the common portion built as a
-library module, with the two platform other files registering
-their own platform_driver instances separately.
-
-Fixes: ddacd6ef44ca ("usb: fotg210: Fix Kconfig for USB host modules")
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Link: https://lore.kernel.org/r/20221215165728.2062984-1-arnd@kernel.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -144,10 +144,7 @@ static struct platform_driver fotg210_dr
- 
- static int __init fotg210_init(void)
- {
--	if (usb_disabled())
--		return -ENODEV;
--
--	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+	if (IS_ENABLED(CONFIG_USB_FOTG210_HCD) && !usb_disabled())
- 		fotg210_hcd_init();
- 	return platform_driver_register(&fotg210_driver);
- }
diff --git a/target/linux/gemini/patches-6.1/0015-usb-fotg210-udc-fix-error-return-code-in-fotg210_udc.patch b/target/linux/gemini/patches-6.1/0015-usb-fotg210-udc-fix-error-return-code-in-fotg210_udc.patch
deleted file mode 100644
index a9bbca58b4..0000000000
--- a/target/linux/gemini/patches-6.1/0015-usb-fotg210-udc-fix-error-return-code-in-fotg210_udc.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From eaaa85d907fe27852dd960b2bc5d7bcf11bc3ebd Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Fri, 30 Dec 2022 14:54:27 +0800
-Subject: [PATCH 15/29] usb: fotg210-udc: fix error return code in
- fotg210_udc_probe()
-
-After commit  5f217ccd520f ("fotg210-udc: Support optional external PHY"),
-the error code is re-assigned to 0 in fotg210_udc_probe(), if allocate or
-map memory fails after the assignment, it can't return an error code. Set
-the error code to -ENOMEM to fix this problem.
-
-Fixes: 5f217ccd520f ("fotg210-udc: Support optional external PHY")
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221230065427.944586-1-yangyingliang@huawei.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1214,6 +1214,8 @@ int fotg210_udc_probe(struct platform_de
- 		dev_info(dev, "found and initialized PHY\n");
- 	}
- 
-+	ret = -ENOMEM;
-+
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
- 		fotg210->ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
- 		if (!fotg210->ep[i])
diff --git a/target/linux/gemini/patches-6.1/0016-usb-fotg210-List-different-variants.patch b/target/linux/gemini/patches-6.1/0016-usb-fotg210-List-different-variants.patch
deleted file mode 100644
index 6ff6d28ad3..0000000000
--- a/target/linux/gemini/patches-6.1/0016-usb-fotg210-List-different-variants.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 407577548b2fcd41cc72ee05df1f05a430ed30a0 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:16 +0100
-Subject: [PATCH 16/29] usb: fotg210: List different variants
-
-There are at least two variants of the FOTG: FOTG200 and
-FOTG210. Handle them in this driver and let's add
-more quirks as we go along.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-2-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -127,7 +127,9 @@ static int fotg210_remove(struct platfor
- 
- #ifdef CONFIG_OF
- static const struct of_device_id fotg210_of_match[] = {
-+	{ .compatible = "faraday,fotg200" },
- 	{ .compatible = "faraday,fotg210" },
-+	/* TODO: can we also handle FUSB220? */
- 	{},
- };
- MODULE_DEVICE_TABLE(of, fotg210_of_match);
diff --git a/target/linux/gemini/patches-6.1/0017-usb-fotg210-Acquire-memory-resource-in-core.patch b/target/linux/gemini/patches-6.1/0017-usb-fotg210-Acquire-memory-resource-in-core.patch
deleted file mode 100644
index 7dbd511ecb..0000000000
--- a/target/linux/gemini/patches-6.1/0017-usb-fotg210-Acquire-memory-resource-in-core.patch
+++ /dev/null
@@ -1,245 +0,0 @@
-From fa735ad1afeb5791d5562617b9bbed74574d3e81 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:17 +0100
-Subject: [PATCH 17/29] usb: fotg210: Acquire memory resource in core
-
-The subdrivers are obtaining and mapping the memory resource
-separately. Create a common state container for the shared
-resources and start populating this by acquiring the IO
-memory resource and remap it and pass this to the subdrivers
-for host and peripheral.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-3-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -33,9 +33,10 @@
- #define GEMINI_MISC_USB0_MINI_B		BIT(29)
- #define GEMINI_MISC_USB1_MINI_B		BIT(30)
- 
--static int fotg210_gemini_init(struct device *dev, struct resource *res,
-+static int fotg210_gemini_init(struct fotg210 *fotg, struct resource *res,
- 			       enum usb_dr_mode mode)
- {
-+	struct device *dev = fotg->dev;
- 	struct device_node *np = dev->of_node;
- 	struct regmap *map;
- 	bool wakeup;
-@@ -47,6 +48,7 @@ static int fotg210_gemini_init(struct de
- 		dev_err(dev, "no syscon\n");
- 		return PTR_ERR(map);
- 	}
-+	fotg->map = map;
- 	wakeup = of_property_read_bool(np, "wakeup-source");
- 
- 	/*
-@@ -55,6 +57,7 @@ static int fotg210_gemini_init(struct de
- 	 */
- 	mask = 0;
- 	if (res->start == 0x69000000) {
-+		fotg->port = GEMINI_PORT_1;
- 		mask = GEMINI_MISC_USB1_VBUS_ON | GEMINI_MISC_USB1_MINI_B |
- 			GEMINI_MISC_USB1_WAKEUP;
- 		if (mode == USB_DR_MODE_HOST)
-@@ -64,6 +67,7 @@ static int fotg210_gemini_init(struct de
- 		if (wakeup)
- 			val |= GEMINI_MISC_USB1_WAKEUP;
- 	} else {
-+		fotg->port = GEMINI_PORT_0;
- 		mask = GEMINI_MISC_USB0_VBUS_ON | GEMINI_MISC_USB0_MINI_B |
- 			GEMINI_MISC_USB0_WAKEUP;
- 		if (mode == USB_DR_MODE_HOST)
-@@ -89,23 +93,34 @@ static int fotg210_probe(struct platform
- {
- 	struct device *dev = &pdev->dev;
- 	enum usb_dr_mode mode;
-+	struct fotg210 *fotg;
- 	int ret;
- 
-+	fotg = devm_kzalloc(dev, sizeof(*fotg), GFP_KERNEL);
-+	if (!fotg)
-+		return -ENOMEM;
-+	fotg->dev = dev;
-+
-+	fotg->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!fotg->res)
-+		return -ENODEV;
-+
-+	fotg->base = devm_ioremap_resource(dev, fotg->res);
-+	if (!fotg->base)
-+		return -ENOMEM;
-+
- 	mode = usb_get_dr_mode(dev);
- 
- 	if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
--		struct resource *res;
--
--		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--		ret = fotg210_gemini_init(dev, res, mode);
-+		ret = fotg210_gemini_init(fotg, fotg->res, mode);
- 		if (ret)
- 			return ret;
- 	}
- 
- 	if (mode == USB_DR_MODE_PERIPHERAL)
--		ret = fotg210_udc_probe(pdev);
-+		ret = fotg210_udc_probe(pdev, fotg);
- 	else
--		ret = fotg210_hcd_probe(pdev);
-+		ret = fotg210_hcd_probe(pdev, fotg);
- 
- 	return ret;
- }
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -5557,11 +5557,10 @@ static void fotg210_init(struct fotg210_
-  * then invokes the start() method for the HCD associated with it
-  * through the hotplug entry's driver_data.
-  */
--int fotg210_hcd_probe(struct platform_device *pdev)
-+int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg)
- {
- 	struct device *dev = &pdev->dev;
- 	struct usb_hcd *hcd;
--	struct resource *res;
- 	int irq;
- 	int retval;
- 	struct fotg210_hcd *fotg210;
-@@ -5585,18 +5584,14 @@ int fotg210_hcd_probe(struct platform_de
- 
- 	hcd->has_tt = 1;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
--	if (IS_ERR(hcd->regs)) {
--		retval = PTR_ERR(hcd->regs);
--		goto failed_put_hcd;
--	}
-+	hcd->regs = fotg->base;
- 
--	hcd->rsrc_start = res->start;
--	hcd->rsrc_len = resource_size(res);
-+	hcd->rsrc_start = fotg->res->start;
-+	hcd->rsrc_len = resource_size(fotg->res);
- 
- 	fotg210 = hcd_to_fotg210(hcd);
- 
-+	fotg210->fotg = fotg;
- 	fotg210->caps = hcd->regs;
- 
- 	/* It's OK not to supply this clock */
---- a/drivers/usb/fotg210/fotg210-hcd.h
-+++ b/drivers/usb/fotg210/fotg210-hcd.h
-@@ -182,6 +182,7 @@ struct fotg210_hcd {			/* one per contro
- #	define INCR(x) do {} while (0)
- #endif
- 
-+	struct fotg210		*fotg;		/* Overarching FOTG210 device */
- 	/* silicon clock */
- 	struct clk		*pclk;
- };
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1155,21 +1155,14 @@ int fotg210_udc_remove(struct platform_d
- 	return 0;
- }
- 
--int fotg210_udc_probe(struct platform_device *pdev)
-+int fotg210_udc_probe(struct platform_device *pdev, struct fotg210 *fotg)
- {
--	struct resource *res;
- 	struct fotg210_udc *fotg210 = NULL;
- 	struct device *dev = &pdev->dev;
- 	int irq;
- 	int ret = 0;
- 	int i;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	if (!res) {
--		pr_err("platform_get_resource error.\n");
--		return -ENODEV;
--	}
--
- 	irq = platform_get_irq(pdev, 0);
- 	if (irq < 0) {
- 		pr_err("could not get irq\n");
-@@ -1182,6 +1175,7 @@ int fotg210_udc_probe(struct platform_de
- 		return -ENOMEM;
- 
- 	fotg210->dev = dev;
-+	fotg210->fotg = fotg;
- 
- 	/* It's OK not to supply this clock */
- 	fotg210->pclk = devm_clk_get(dev, "PCLK");
-@@ -1222,11 +1216,7 @@ int fotg210_udc_probe(struct platform_de
- 			goto err_alloc;
- 	}
- 
--	fotg210->reg = ioremap(res->start, resource_size(res));
--	if (fotg210->reg == NULL) {
--		dev_err(dev, "ioremap error\n");
--		goto err_alloc;
--	}
-+	fotg210->reg = fotg->base;
- 
- 	spin_lock_init(&fotg210->lock);
- 
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -236,6 +236,7 @@ struct fotg210_udc {
- 	unsigned long		irq_trigger;
- 
- 	struct device			*dev;
-+	struct fotg210			*fotg;
- 	struct usb_phy			*phy;
- 	struct usb_gadget		gadget;
- 	struct usb_gadget_driver	*driver;
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -2,13 +2,28 @@
- #ifndef __FOTG210_H
- #define __FOTG210_H
- 
-+enum gemini_port {
-+	GEMINI_PORT_NONE = 0,
-+	GEMINI_PORT_0,
-+	GEMINI_PORT_1,
-+};
-+
-+struct fotg210 {
-+	struct device *dev;
-+	struct resource *res;
-+	void __iomem *base;
-+	struct regmap *map;
-+	enum gemini_port port;
-+};
-+
- #ifdef CONFIG_USB_FOTG210_HCD
--int fotg210_hcd_probe(struct platform_device *pdev);
-+int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_hcd_remove(struct platform_device *pdev);
- int fotg210_hcd_init(void);
- void fotg210_hcd_cleanup(void);
- #else
--static inline int fotg210_hcd_probe(struct platform_device *pdev)
-+static inline int fotg210_hcd_probe(struct platform_device *pdev,
-+				    struct fotg210 *fotg)
- {
- 	return 0;
- }
-@@ -26,10 +41,11 @@ static inline void fotg210_hcd_cleanup(v
- #endif
- 
- #ifdef CONFIG_USB_FOTG210_UDC
--int fotg210_udc_probe(struct platform_device *pdev);
-+int fotg210_udc_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_udc_remove(struct platform_device *pdev);
- #else
--static inline int fotg210_udc_probe(struct platform_device *pdev)
-+static inline int fotg210_udc_probe(struct platform_device *pdev,
-+				    struct fotg210 *fotg)
- {
- 	return 0;
- }
diff --git a/target/linux/gemini/patches-6.1/0018-usb-fotg210-Move-clock-handling-to-core.patch b/target/linux/gemini/patches-6.1/0018-usb-fotg210-Move-clock-handling-to-core.patch
deleted file mode 100644
index 9894f4dc66..0000000000
--- a/target/linux/gemini/patches-6.1/0018-usb-fotg210-Move-clock-handling-to-core.patch
+++ /dev/null
@@ -1,196 +0,0 @@
-From fb8e1e8dbc47e7aff7624b47adaa0a84d2983802 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:18 +0100
-Subject: [PATCH 18/29] usb: fotg210: Move clock handling to core
-
-Grab the optional silicon block clock, prepare and enable it in
-the core before proceeding to prepare the host or peripheral
-driver. This saves duplicate code and also uses the simple
-devm_clk_get_optional_enabled() to do everything we really
-want to do.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-4-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -6,6 +6,7 @@
-  * driver.
-  */
- #include <linux/bitops.h>
-+#include <linux/clk.h>
- #include <linux/device.h>
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
-@@ -109,6 +110,10 @@ static int fotg210_probe(struct platform
- 	if (!fotg->base)
- 		return -ENOMEM;
- 
-+	fotg->pclk = devm_clk_get_optional_enabled(dev, "PCLK");
-+	if (IS_ERR(fotg->pclk))
-+		return PTR_ERR(fotg->pclk);
-+
- 	mode = usb_get_dr_mode(dev);
- 
- 	if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -33,7 +33,6 @@
- #include <linux/platform_device.h>
- #include <linux/io.h>
- #include <linux/iopoll.h>
--#include <linux/clk.h>
- 
- #include <asm/byteorder.h>
- #include <asm/irq.h>
-@@ -5594,44 +5593,22 @@ int fotg210_hcd_probe(struct platform_de
- 	fotg210->fotg = fotg;
- 	fotg210->caps = hcd->regs;
- 
--	/* It's OK not to supply this clock */
--	fotg210->pclk = clk_get(dev, "PCLK");
--	if (!IS_ERR(fotg210->pclk)) {
--		retval = clk_prepare_enable(fotg210->pclk);
--		if (retval) {
--			dev_err(dev, "failed to enable PCLK\n");
--			goto failed_put_hcd;
--		}
--	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
--		/*
--		 * Percolate deferrals, for anything else,
--		 * just live without the clocking.
--		 */
--		retval = PTR_ERR(fotg210->pclk);
--		goto failed_dis_clk;
--	}
--
- 	retval = fotg210_setup(hcd);
- 	if (retval)
--		goto failed_dis_clk;
-+		goto failed_put_hcd;
- 
- 	fotg210_init(fotg210);
- 
- 	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- 	if (retval) {
- 		dev_err(dev, "failed to add hcd with err %d\n", retval);
--		goto failed_dis_clk;
-+		goto failed_put_hcd;
- 	}
- 	device_wakeup_enable(hcd->self.controller);
- 	platform_set_drvdata(pdev, hcd);
- 
- 	return retval;
- 
--failed_dis_clk:
--	if (!IS_ERR(fotg210->pclk)) {
--		clk_disable_unprepare(fotg210->pclk);
--		clk_put(fotg210->pclk);
--	}
- failed_put_hcd:
- 	usb_put_hcd(hcd);
- fail_create_hcd:
-@@ -5647,12 +5624,6 @@ fail_create_hcd:
- int fotg210_hcd_remove(struct platform_device *pdev)
- {
- 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
--	struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
--	if (!IS_ERR(fotg210->pclk)) {
--		clk_disable_unprepare(fotg210->pclk);
--		clk_put(fotg210->pclk);
--	}
- 
- 	usb_remove_hcd(hcd);
- 	usb_put_hcd(hcd);
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,7 +15,6 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
--#include <linux/clk.h>
- #include <linux/usb/otg.h>
- #include <linux/usb/phy.h>
- 
-@@ -1147,9 +1146,6 @@ int fotg210_udc_remove(struct platform_d
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- 		kfree(fotg210->ep[i]);
- 
--	if (!IS_ERR(fotg210->pclk))
--		clk_disable_unprepare(fotg210->pclk);
--
- 	kfree(fotg210);
- 
- 	return 0;
-@@ -1177,34 +1173,17 @@ int fotg210_udc_probe(struct platform_de
- 	fotg210->dev = dev;
- 	fotg210->fotg = fotg;
- 
--	/* It's OK not to supply this clock */
--	fotg210->pclk = devm_clk_get(dev, "PCLK");
--	if (!IS_ERR(fotg210->pclk)) {
--		ret = clk_prepare_enable(fotg210->pclk);
--		if (ret) {
--			dev_err(dev, "failed to enable PCLK\n");
--			goto err;
--		}
--	} else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
--		/*
--		 * Percolate deferrals, for anything else,
--		 * just live without the clocking.
--		 */
--		ret = -EPROBE_DEFER;
--		goto err;
--	}
--
- 	fotg210->phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
- 	if (IS_ERR(fotg210->phy)) {
- 		ret = PTR_ERR(fotg210->phy);
- 		if (ret == -EPROBE_DEFER)
--			goto err_pclk;
-+			goto err_free;
- 		dev_info(dev, "no PHY found\n");
- 		fotg210->phy = NULL;
- 	} else {
- 		ret = usb_phy_init(fotg210->phy);
- 		if (ret)
--			goto err_pclk;
-+			goto err_free;
- 		dev_info(dev, "found and initialized PHY\n");
- 	}
- 
-@@ -1303,11 +1282,8 @@ err_map:
- err_alloc:
- 	for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- 		kfree(fotg210->ep[i]);
--err_pclk:
--	if (!IS_ERR(fotg210->pclk))
--		clk_disable_unprepare(fotg210->pclk);
- 
--err:
-+err_free:
- 	kfree(fotg210);
- 	return ret;
- }
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -231,7 +231,6 @@ struct fotg210_ep {
- struct fotg210_udc {
- 	spinlock_t		lock; /* protect the struct */
- 	void __iomem		*reg;
--	struct clk		*pclk;
- 
- 	unsigned long		irq_trigger;
- 
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -12,6 +12,7 @@ struct fotg210 {
- 	struct device *dev;
- 	struct resource *res;
- 	void __iomem *base;
-+	struct clk *pclk;
- 	struct regmap *map;
- 	enum gemini_port port;
- };
diff --git a/target/linux/gemini/patches-6.1/0019-usb-fotg210-Check-role-register-in-core.patch b/target/linux/gemini/patches-6.1/0019-usb-fotg210-Check-role-register-in-core.patch
deleted file mode 100644
index 892b0d31af..0000000000
--- a/target/linux/gemini/patches-6.1/0019-usb-fotg210-Check-role-register-in-core.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From b1b07abb598211de3ce7f52abdf8dcb24384341e Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:19 +0100
-Subject: [PATCH 19/29] usb: fotg210: Check role register in core
-
-Read the role register and check that we are in host/peripheral
-mode and issue warnings if we're not in the right role when
-probing respective driver.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-5-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -18,6 +18,11 @@
- 
- #include "fotg210.h"
- 
-+/* Role Register 0x80 */
-+#define FOTG210_RR			0x80
-+#define FOTG210_RR_ID			BIT(21) /* 1 = B-device, 0 = A-device */
-+#define FOTG210_RR_CROLE		BIT(20) /* 1 = device, 0 = host */
-+
- /*
-  * Gemini-specific initialization function, only executed on the
-  * Gemini SoC using the global misc control register.
-@@ -95,6 +100,7 @@ static int fotg210_probe(struct platform
- 	struct device *dev = &pdev->dev;
- 	enum usb_dr_mode mode;
- 	struct fotg210 *fotg;
-+	u32 val;
- 	int ret;
- 
- 	fotg = devm_kzalloc(dev, sizeof(*fotg), GFP_KERNEL);
-@@ -122,10 +128,16 @@ static int fotg210_probe(struct platform
- 			return ret;
- 	}
- 
--	if (mode == USB_DR_MODE_PERIPHERAL)
-+	val = readl(fotg->base + FOTG210_RR);
-+	if (mode == USB_DR_MODE_PERIPHERAL) {
-+		if (!(val & FOTG210_RR_CROLE))
-+			dev_err(dev, "block not in device role\n");
- 		ret = fotg210_udc_probe(pdev, fotg);
--	else
-+	} else {
-+		if (val & FOTG210_RR_CROLE)
-+			dev_err(dev, "block not in host role\n");
- 		ret = fotg210_hcd_probe(pdev, fotg);
-+	}
- 
- 	return ret;
- }
diff --git a/target/linux/gemini/patches-6.1/0020-usb-fotg210-udc-Assign-of_node-and-speed-on-start.patch b/target/linux/gemini/patches-6.1/0020-usb-fotg210-udc-Assign-of_node-and-speed-on-start.patch
deleted file mode 100644
index 20f8f94350..0000000000
--- a/target/linux/gemini/patches-6.1/0020-usb-fotg210-udc-Assign-of_node-and-speed-on-start.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From d7c2b0b6da75b86cf5ddbcd51a74d74e19bbf178 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:20 +0100
-Subject: [PATCH 20/29] usb: fotg210-udc: Assign of_node and speed on start
-
-Follow the example set by other drivers to assign of_node
-and speed to the driver when binding, also print bound
-info akin to other UDC drivers.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-6-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1028,6 +1028,10 @@ static int fotg210_udc_start(struct usb_
- 
- 	/* hook up the driver */
- 	fotg210->driver = driver;
-+	fotg210->gadget.dev.of_node = fotg210->dev->of_node;
-+	fotg210->gadget.speed = USB_SPEED_UNKNOWN;
-+
-+	dev_info(fotg210->dev, "bound driver %s\n", driver->driver.name);
- 
- 	if (!IS_ERR_OR_NULL(fotg210->phy)) {
- 		ret = otg_set_peripheral(fotg210->phy->otg,
-@@ -1084,6 +1088,7 @@ static int fotg210_udc_stop(struct usb_g
- 
- 	fotg210_init(fotg210);
- 	fotg210->driver = NULL;
-+	fotg210->gadget.speed = USB_SPEED_UNKNOWN;
- 
- 	spin_unlock_irqrestore(&fotg210->lock, flags);
- 
diff --git a/target/linux/gemini/patches-6.1/0021-usb-fotg210-udc-Implement-VBUS-session.patch b/target/linux/gemini/patches-6.1/0021-usb-fotg210-udc-Implement-VBUS-session.patch
deleted file mode 100644
index d98561f0d4..0000000000
--- a/target/linux/gemini/patches-6.1/0021-usb-fotg210-udc-Implement-VBUS-session.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From 2fbbfb2c556944945639b17b13fcb1e05272b646 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:21 +0100
-Subject: [PATCH 21/29] usb: fotg210-udc: Implement VBUS session
-
-Implement VBUS session handling for FOTG210. This is
-mainly used by the UDC driver which needs to call down to
-the FOTG210 core and enable/disable VBUS, as this needs to be
-handled outside of the HCD and UDC drivers, by platform
-specific glue code.
-
-The Gemini has a special bit in a system register to turn
-VBUS on and off so we implement this in the FOTG210 core.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-7-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -95,6 +95,35 @@ static int fotg210_gemini_init(struct fo
- 	return 0;
- }
- 
-+/**
-+ * fotg210_vbus() - Called by gadget driver to enable/disable VBUS
-+ * @enable: true to enable VBUS, false to disable VBUS
-+ */
-+void fotg210_vbus(struct fotg210 *fotg, bool enable)
-+{
-+	u32 mask;
-+	u32 val;
-+	int ret;
-+
-+	switch (fotg->port) {
-+	case GEMINI_PORT_0:
-+		mask = GEMINI_MISC_USB0_VBUS_ON;
-+		val = enable ? GEMINI_MISC_USB0_VBUS_ON : 0;
-+		break;
-+	case GEMINI_PORT_1:
-+		mask = GEMINI_MISC_USB1_VBUS_ON;
-+		val = enable ? GEMINI_MISC_USB1_VBUS_ON : 0;
-+		break;
-+	default:
-+		return;
-+	}
-+	ret = regmap_update_bits(fotg->map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
-+	if (ret)
-+		dev_err(fotg->dev, "failed to %s VBUS\n",
-+			enable ? "enable" : "disable");
-+	dev_info(fotg->dev, "%s: %s VBUS\n", __func__, enable ? "enable" : "disable");
-+}
-+
- static int fotg210_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1095,9 +1095,26 @@ static int fotg210_udc_stop(struct usb_g
- 	return 0;
- }
- 
-+/**
-+ * fotg210_vbus_session - Called by external transceiver to enable/disable udc
-+ * @_gadget: usb gadget
-+ * @is_active: 0 if should disable UDC VBUS, 1 if should enable
-+ *
-+ * Returns 0
-+ */
-+static int fotg210_vbus_session(struct usb_gadget *g, int is_active)
-+{
-+	struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+
-+	/* Call down to core integration layer to drive or disable VBUS */
-+	fotg210_vbus(fotg210->fotg, is_active);
-+	return 0;
-+}
-+
- static const struct usb_gadget_ops fotg210_gadget_ops = {
- 	.udc_start		= fotg210_udc_start,
- 	.udc_stop		= fotg210_udc_stop,
-+	.vbus_session		= fotg210_vbus_session,
- };
- 
- /**
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -17,6 +17,8 @@ struct fotg210 {
- 	enum gemini_port port;
- };
- 
-+void fotg210_vbus(struct fotg210 *fotg, bool enable);
-+
- #ifdef CONFIG_USB_FOTG210_HCD
- int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_hcd_remove(struct platform_device *pdev);
diff --git a/target/linux/gemini/patches-6.1/0022-fotg210-udc-Introduce-and-use-a-fotg210_ack_int-func.patch b/target/linux/gemini/patches-6.1/0022-fotg210-udc-Introduce-and-use-a-fotg210_ack_int-func.patch
deleted file mode 100644
index fc5831eb23..0000000000
--- a/target/linux/gemini/patches-6.1/0022-fotg210-udc-Introduce-and-use-a-fotg210_ack_int-func.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From f011d1eab23f4c063c5441c0d5a22898adf9145c Mon Sep 17 00:00:00 2001
-From: Fabian Vogt <fabian@ritter-vogt.de>
-Date: Mon, 23 Jan 2023 08:35:07 +0100
-Subject: [PATCH 22/29] fotg210-udc: Introduce and use a fotg210_ack_int
- function
-
-This is in preparation of support for devices where interrupts are acked
-differently.
-
-Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073508.2350402-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -28,6 +28,14 @@ static const char udc_name[] = "fotg210_
- static const char * const fotg210_ep_name[] = {
- 	"ep0", "ep1", "ep2", "ep3", "ep4"};
- 
-+static void fotg210_ack_int(struct fotg210_udc *fotg210, u32 offset, u32 mask)
-+{
-+	u32 value = ioread32(fotg210->reg + offset);
-+
-+	value &= ~mask;
-+	iowrite32(value, fotg210->reg + offset);
-+}
-+
- static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
- {
- 	u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-@@ -303,8 +311,7 @@ static void fotg210_wait_dma_done(struct
- 			goto dma_reset;
- 	} while (!(value & DISGR2_DMA_CMPLT));
- 
--	value &= ~DISGR2_DMA_CMPLT;
--	iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
-+	fotg210_ack_int(ep->fotg210, FOTG210_DISGR2, DISGR2_DMA_CMPLT);
- 	return;
- 
- dma_reset:
-@@ -844,14 +851,6 @@ static void fotg210_ep0in(struct fotg210
- 	}
- }
- 
--static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
--{
--	u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
--
--	value &= ~DISGR0_CX_COMABT_INT;
--	iowrite32(value, fotg210->reg + FOTG210_DISGR0);
--}
--
- static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
- {
- 	struct fotg210_request *req = list_entry(ep->queue.next,
-@@ -893,60 +892,43 @@ static irqreturn_t fotg210_irq(int irq,
- 		void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
- 		u32 int_grp2 = ioread32(reg);
- 		u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
--		u32 value;
- 
- 		int_grp2 &= ~int_msk2;
- 
- 		if (int_grp2 & DISGR2_USBRST_INT) {
- 			usb_gadget_udc_reset(&fotg210->gadget,
- 					     fotg210->driver);
--			value = ioread32(reg);
--			value &= ~DISGR2_USBRST_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_USBRST_INT);
- 			pr_info("fotg210 udc reset\n");
- 		}
- 		if (int_grp2 & DISGR2_SUSP_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_SUSP_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_SUSP_INT);
- 			pr_info("fotg210 udc suspend\n");
- 		}
- 		if (int_grp2 & DISGR2_RESM_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_RESM_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_RESM_INT);
- 			pr_info("fotg210 udc resume\n");
- 		}
- 		if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_ISO_SEQ_ERR_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_ISO_SEQ_ERR_INT);
- 			pr_info("fotg210 iso sequence error\n");
- 		}
- 		if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
--			value = ioread32(reg);
--			value &= ~DISGR2_ISO_SEQ_ABORT_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_ISO_SEQ_ABORT_INT);
- 			pr_info("fotg210 iso sequence abort\n");
- 		}
- 		if (int_grp2 & DISGR2_TX0BYTE_INT) {
- 			fotg210_clear_tx0byte(fotg210);
--			value = ioread32(reg);
--			value &= ~DISGR2_TX0BYTE_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_TX0BYTE_INT);
- 			pr_info("fotg210 transferred 0 byte\n");
- 		}
- 		if (int_grp2 & DISGR2_RX0BYTE_INT) {
- 			fotg210_clear_rx0byte(fotg210);
--			value = ioread32(reg);
--			value &= ~DISGR2_RX0BYTE_INT;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_RX0BYTE_INT);
- 			pr_info("fotg210 received 0 byte\n");
- 		}
- 		if (int_grp2 & DISGR2_DMA_ERROR) {
--			value = ioread32(reg);
--			value &= ~DISGR2_DMA_ERROR;
--			iowrite32(value, reg);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_DMA_ERROR);
- 		}
- 	}
- 
-@@ -960,7 +942,7 @@ static irqreturn_t fotg210_irq(int irq,
- 
- 		/* the highest priority in this source register */
- 		if (int_grp0 & DISGR0_CX_COMABT_INT) {
--			fotg210_clear_comabt_int(fotg210);
-+			fotg210_ack_int(fotg210, FOTG210_DISGR0, DISGR0_CX_COMABT_INT);
- 			pr_info("fotg210 CX command abort\n");
- 		}
- 
diff --git a/target/linux/gemini/patches-6.1/0023-fotg210-udc-Improve-device-initialization.patch b/target/linux/gemini/patches-6.1/0023-fotg210-udc-Improve-device-initialization.patch
deleted file mode 100644
index fde17a48b3..0000000000
--- a/target/linux/gemini/patches-6.1/0023-fotg210-udc-Improve-device-initialization.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 367747c7813cecf19b46ef7134691f903ab76dc9 Mon Sep 17 00:00:00 2001
-From: Fabian Vogt <fabian@ritter-vogt.de>
-Date: Mon, 23 Jan 2023 08:35:08 +0100
-Subject: [PATCH 23/29] fotg210-udc: Improve device initialization
-
-Reset the device explicitly to get into a known state and also set the chip
-enable bit. Additionally, mask interrupts which aren't handled.
-
-Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073508.2350402-4-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -7,6 +7,7 @@
-  * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
-  */
- 
-+#include <linux/delay.h>
- #include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/interrupt.h>
-@@ -1022,6 +1023,11 @@ static int fotg210_udc_start(struct usb_
- 			dev_err(fotg210->dev, "can't bind to phy\n");
- 	}
- 
-+	/* chip enable */
-+	value = ioread32(fotg210->reg + FOTG210_DMCR);
-+	value |= DMCR_CHIP_EN;
-+	iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
- 	/* enable device global interrupt */
- 	value = ioread32(fotg210->reg + FOTG210_DMCR);
- 	value |= DMCR_GLINT_EN;
-@@ -1038,6 +1044,15 @@ static void fotg210_init(struct fotg210_
- 	iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
- 		  fotg210->reg + FOTG210_GMIR);
- 
-+	/* mask interrupts for groups other than 0-2 */
-+	iowrite32(~(DMIGR_MINT_G0 | DMIGR_MINT_G1 | DMIGR_MINT_G2),
-+		  fotg210->reg + FOTG210_DMIGR);
-+
-+	/* udc software reset */
-+	iowrite32(DMCR_SFRST, fotg210->reg + FOTG210_DMCR);
-+	/* Better wait a bit, but without a datasheet, no idea how long. */
-+	usleep_range(100, 200);
-+
- 	/* disable device global interrupt */
- 	value = ioread32(fotg210->reg + FOTG210_DMCR);
- 	value &= ~DMCR_GLINT_EN;
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -58,6 +58,8 @@
- 
- /* Device Mask of Interrupt Group Register (0x130) */
- #define FOTG210_DMIGR		0x130
-+#define DMIGR_MINT_G2		(1 << 2)
-+#define DMIGR_MINT_G1		(1 << 1)
- #define DMIGR_MINT_G0		(1 << 0)
- 
- /* Device Mask of Interrupt Source Group 0(0x134) */
diff --git a/target/linux/gemini/patches-6.1/0024-usb-fotg210-hcd-use-sysfs_emit-to-instead-of-scnprin.patch b/target/linux/gemini/patches-6.1/0024-usb-fotg210-hcd-use-sysfs_emit-to-instead-of-scnprin.patch
deleted file mode 100644
index 680836110a..0000000000
--- a/target/linux/gemini/patches-6.1/0024-usb-fotg210-hcd-use-sysfs_emit-to-instead-of-scnprin.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 482830a70408a5d30af264b3d6706f818c78b2b2 Mon Sep 17 00:00:00 2001
-From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Date: Fri, 20 Jan 2023 17:44:33 +0200
-Subject: [PATCH 24/29] usb: fotg210-hcd: use sysfs_emit() to instead of
- scnprintf()
-
-Follow the advice of the Documentation/filesystems/sysfs.rst and show()
-should only use sysfs_emit() or sysfs_emit_at() when formatting the
-value to be returned to user space.
-
-Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Link: https://lore.kernel.org/r/20230120154437.22025-1-andriy.shevchenko@linux.intel.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -4686,14 +4686,11 @@ static ssize_t uframe_periodic_max_show(
- 		struct device_attribute *attr, char *buf)
- {
- 	struct fotg210_hcd *fotg210;
--	int n;
- 
- 	fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
--	n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
--	return n;
-+	return sysfs_emit(buf, "%d\n", fotg210->uframe_periodic_max);
- }
- 
--
- static ssize_t uframe_periodic_max_store(struct device *dev,
- 		struct device_attribute *attr, const char *buf, size_t count)
- {
diff --git a/target/linux/gemini/patches-6.1/0025-ARM-dts-gemini-Push-down-flash-address-size-cells.patch b/target/linux/gemini/patches-6.1/0025-ARM-dts-gemini-Push-down-flash-address-size-cells.patch
deleted file mode 100644
index 1e031f1d4f..0000000000
--- a/target/linux/gemini/patches-6.1/0025-ARM-dts-gemini-Push-down-flash-address-size-cells.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 6b84aa39a063eec883d410a9893cec70fce56163 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:28 +0100
-Subject: [PATCH 25/29] ARM: dts: gemini: Push down flash address/size cells
-
-The platforms not defining any OF partions complain like
-this:
-
-../arch/arm/boot/dts/gemini.dtsi:19.25-28.5: Warning
- (avoid_unnecessary_addr_size): /soc/flash@30000000: unnecessary
- #address-cells/#size-cells without "ranges" or child "reg" property
-
-Get rid of this by only defining the address-cells and
-size-cells where it is actually used by OF partitions.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-1-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-@@ -164,6 +164,8 @@
- 			compatible = "cortina,gemini-flash", "jedec-flash";
- 			status = "okay";
- 			reg = <0x30000000 0x00080000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
- 
- 			/*
- 			 * This "RedBoot" is the Storlink derivative.
---- a/arch/arm/boot/dts/gemini-wbd111.dts
-+++ b/arch/arm/boot/dts/gemini-wbd111.dts
-@@ -86,6 +86,8 @@
- 			status = "okay";
- 			/* 8MB of flash */
- 			reg = <0x30000000 0x00800000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
- 
- 			partition@0 {
- 				label = "RedBoot";
---- a/arch/arm/boot/dts/gemini-wbd222.dts
-+++ b/arch/arm/boot/dts/gemini-wbd222.dts
-@@ -90,6 +90,8 @@
- 			status = "okay";
- 			/* 8MB of flash */
- 			reg = <0x30000000 0x00800000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
- 
- 			partition@0 {
- 				label = "RedBoot";
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -22,8 +22,6 @@
- 			pinctrl-names = "default";
- 			pinctrl-0 = <&pflash_default_pins>;
- 			bank-width = <2>;
--			#address-cells = <1>;
--			#size-cells = <1>;
- 			status = "disabled";
- 		};
- 
diff --git a/target/linux/gemini/patches-6.1/0026-ARM-dts-gemini-wbd111-Use-RedBoot-partion-parser.patch b/target/linux/gemini/patches-6.1/0026-ARM-dts-gemini-wbd111-Use-RedBoot-partion-parser.patch
deleted file mode 100644
index 1aff23ed1b..0000000000
--- a/target/linux/gemini/patches-6.1/0026-ARM-dts-gemini-wbd111-Use-RedBoot-partion-parser.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 0e733f5af628210f372585e431504a7024e7b571 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:29 +0100
-Subject: [PATCH 26/29] ARM: dts: gemini: wbd111: Use RedBoot partion parser
-
-This is clearly a RedBoot partitioned device with 0x20000
-sized erase blocks.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-2-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-wbd111.dts
-+++ b/arch/arm/boot/dts/gemini-wbd111.dts
-@@ -86,36 +86,11 @@
- 			status = "okay";
- 			/* 8MB of flash */
- 			reg = <0x30000000 0x00800000>;
--			#address-cells = <1>;
--			#size-cells = <1>;
- 
--			partition@0 {
--				label = "RedBoot";
--				reg = <0x00000000 0x00020000>;
--				read-only;
--			};
--			partition@20000 {
--				label = "kernel";
--				reg = <0x00020000 0x00100000>;
--			};
--			partition@120000 {
--				label = "rootfs";
--				reg = <0x00120000 0x006a0000>;
--			};
--			partition@7c0000 {
--				label = "VCTL";
--				reg = <0x007c0000 0x00010000>;
--				read-only;
--			};
--			partition@7d0000 {
--				label = "cfg";
--				reg = <0x007d0000 0x00010000>;
--				read-only;
--			};
--			partition@7e0000 {
--				label = "FIS";
--				reg = <0x007e0000 0x00010000>;
--				read-only;
-+			partitions {
-+				compatible = "redboot-fis";
-+				/* Eraseblock at 0x7e0000 */
-+				fis-index-block = <0x3f>;
- 			};
- 		};
- 
diff --git a/target/linux/gemini/patches-6.1/0027-ARM-dts-gemini-wbd222-Use-RedBoot-partion-parser.patch b/target/linux/gemini/patches-6.1/0027-ARM-dts-gemini-wbd222-Use-RedBoot-partion-parser.patch
deleted file mode 100644
index 8cafeaa0df..0000000000
--- a/target/linux/gemini/patches-6.1/0027-ARM-dts-gemini-wbd222-Use-RedBoot-partion-parser.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 8558e2e1110a5daa4ac9e1c5b5c15e1651a8fb94 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:30 +0100
-Subject: [PATCH 27/29] ARM: dts: gemini: wbd222: Use RedBoot partion parser
-
-This is clearly a RedBoot partitioned device with 0x20000
-sized erase blocks.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-3-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-wbd222.dts
-+++ b/arch/arm/boot/dts/gemini-wbd222.dts
-@@ -90,36 +90,11 @@
- 			status = "okay";
- 			/* 8MB of flash */
- 			reg = <0x30000000 0x00800000>;
--			#address-cells = <1>;
--			#size-cells = <1>;
- 
--			partition@0 {
--				label = "RedBoot";
--				reg = <0x00000000 0x00020000>;
--				read-only;
--			};
--			partition@20000 {
--				label = "kernel";
--				reg = <0x00020000 0x00100000>;
--			};
--			partition@120000 {
--				label = "rootfs";
--				reg = <0x00120000 0x006a0000>;
--			};
--			partition@7c0000 {
--				label = "VCTL";
--				reg = <0x007c0000 0x00010000>;
--				read-only;
--			};
--			partition@7d0000 {
--				label = "cfg";
--				reg = <0x007d0000 0x00010000>;
--				read-only;
--			};
--			partition@7e0000 {
--				label = "FIS";
--				reg = <0x007e0000 0x00010000>;
--				read-only;
-+			partitions {
-+				compatible = "redboot-fis";
-+				/* Eraseblock at 0x7e0000 */
-+				fis-index-block = <0x3f>;
- 			};
- 		};
- 
diff --git a/target/linux/gemini/patches-6.1/0028-ARM-dts-gemini-Fix-USB-block-version.patch b/target/linux/gemini/patches-6.1/0028-ARM-dts-gemini-Fix-USB-block-version.patch
deleted file mode 100644
index fb93b70a31..0000000000
--- a/target/linux/gemini/patches-6.1/0028-ARM-dts-gemini-Fix-USB-block-version.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From d5c01ce4a1016507c69682894cf6b66301abca3d Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 23 Jan 2023 08:39:15 +0100
-Subject: [PATCH 28/29] ARM: dts: gemini: Fix USB block version
-
-The FOTG version in the Gemini is the FOTG200, fix this
-up.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073916.2350839-1-linus.walleij@linaro.org
----
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -439,7 +439,7 @@
- 		};
- 
- 		usb0: usb@68000000 {
--			compatible = "cortina,gemini-usb", "faraday,fotg210";
-+			compatible = "cortina,gemini-usb", "faraday,fotg200";
- 			reg = <0x68000000 0x1000>;
- 			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
- 			resets = <&syscon GEMINI_RESET_USB0>;
-@@ -460,7 +460,7 @@
- 		};
- 
- 		usb1: usb@69000000 {
--			compatible = "cortina,gemini-usb", "faraday,fotg210";
-+			compatible = "cortina,gemini-usb", "faraday,fotg200";
- 			reg = <0x69000000 0x1000>;
- 			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
- 			resets = <&syscon GEMINI_RESET_USB1>;
diff --git a/target/linux/gemini/patches-6.1/0029-ARM-dts-gemini-Enable-DNS313-FOTG210-as-periph.patch b/target/linux/gemini/patches-6.1/0029-ARM-dts-gemini-Enable-DNS313-FOTG210-as-periph.patch
deleted file mode 100644
index 667878170b..0000000000
--- a/target/linux/gemini/patches-6.1/0029-ARM-dts-gemini-Enable-DNS313-FOTG210-as-periph.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 296184694ae7a4e388603c95499e98d30b21cc09 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 23 Jan 2023 08:39:16 +0100
-Subject: [PATCH 29/29] ARM: dts: gemini: Enable DNS313 FOTG210 as periph
-
-Add the GPIO-based VBUS phy, and enable the FOTG210
-USB1 block for use as peripheral.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073916.2350839-2-linus.walleij@linaro.org
----
---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-@@ -80,6 +80,15 @@
- 		#cooling-cells = <2>;
- 	};
- 
-+	/*
-+	 * This is the type B USB connector on the device,
-+	 * a GPIO-controlled USB VBUS detect
-+	 */
-+	usb1_phy: phy {
-+		compatible = "gpio-usb-b-connector", "usb-b-connector";
-+		#phy-cells = <0>;
-+		vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-+	};
- 
- 	/* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
- 	i2c {
-@@ -302,5 +311,13 @@
- 		ide@63000000 {
- 			status = "okay";
- 		};
-+
-+		usb@69000000 {
-+			status = "okay";
-+			dr_mode = "peripheral";
-+			usb-phy = <&usb1_phy>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&usb_default_pins>;
-+		};
- 	};
- };
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -455,6 +455,8 @@
- 			 */
- 			pinctrl-names = "default";
- 			pinctrl-0 = <&usb_default_pins>;
-+			/* Default to host mode */
-+			dr_mode = "host";
- 			syscon = <&syscon>;
- 			status = "disabled";
- 		};
diff --git a/target/linux/gemini/patches-6.1/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch b/target/linux/gemini/patches-6.1/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch
deleted file mode 100644
index 99e0d2731d..0000000000
--- a/target/linux/gemini/patches-6.1/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 36ee838bf83c01cff7cb47c7b07be278d2950ac0 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 11 Mar 2019 15:44:29 +0100
-Subject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt
-
-Rename the firmware partition so that the firmware MTD
-splitter will do its job, drop the rootfs arguments as
-the MTD splitter will set this up automatically.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
-@@ -20,7 +20,7 @@
- 	};
- 
- 	chosen {
--		bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
-+		bootargs = "console=ttyS0,19200n8 consoleblank=300";
- 		stdout-path = "uart0:19200n8";
- 	};
- 
-@@ -317,9 +317,9 @@
- 				 * this is called "upgrade" on the vendor system.
- 				 */
- 				partition@40000 {
--					label = "upgrade";
-+					compatible = "wrg";
-+					label = "firmware";
- 					reg = <0x00040000 0x01f40000>;
--					read-only;
- 				};
- 				/* RGDB, Residental Gateway Database? */
- 				partition@1f80000 {
diff --git a/target/linux/gemini/patches-6.6/0001-net-ethernet-cortina-Drop-TSO-support.patch b/target/linux/gemini/patches-6.6/0001-net-ethernet-cortina-Drop-TSO-support.patch
new file mode 100644
index 0000000000..43e0cb283a
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0001-net-ethernet-cortina-Drop-TSO-support.patch
@@ -0,0 +1,78 @@
+From f8001196455311eb128fcafd98cb2050a70218df Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 6 Jan 2024 01:12:22 +0100
+Subject: [PATCH 4/4] net: ethernet: cortina: Drop TSO support
+
+The recent change to allow large frames without hardware checksumming
+slotted in software checksumming in the driver if hardware could not
+do it.
+
+This will however upset TSO (TCP Segment Offloading). Typical
+error dumps includes this:
+
+skb len=2961 headroom=222 headlen=66 tailroom=0
+(...)
+WARNING: CPU: 0 PID: 956 at net/core/dev.c:3259 skb_warn_bad_offload+0x7c/0x108
+gemini-ethernet-port: caps=(0x0000010000154813, 0x00002007ffdd7889)
+
+And the packets do not go through.
+
+The TSO implementation is bogus: a TSO enabled driver must propagate
+the skb_shinfo(skb)->gso_size value to the TSO engine on the NIC.
+
+Drop the size check and TSO offloading features for now: this
+needs to be fixed up properly.
+
+After this ethernet works fine on Gemini devices with a direct connected
+PHY such as D-Link DNS-313.
+
+Also tested to still be working with a DSA switch using the Gemini
+ethernet as conduit interface.
+
+Link: https://lore.kernel.org/netdev/CANn89iJLfxng1sYL5Zk0mknXpyYQPCp83m3KgD2KJ2_hKCpEUg@mail.gmail.com/
+Suggested-by: Eric Dumazet <edumazet@google.com>
+Fixes: d4d0c5b4d279 ("net: ethernet: cortina: Handle large frames")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/cortina/gemini.c | 15 ++-------------
+ 1 file changed, 2 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -79,8 +79,7 @@ MODULE_PARM_DESC(debug, "Debug level (0=
+ #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
+ 
+ #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
+-		NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
+-		NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
++			       NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)
+ 
+ /**
+  * struct gmac_queue_page - page buffer per-page info
+@@ -1143,23 +1142,13 @@ static int gmac_map_tx_bufs(struct net_d
+ 	struct gmac_txdesc *txd;
+ 	skb_frag_t *skb_frag;
+ 	dma_addr_t mapping;
+-	unsigned short mtu;
+ 	void *buffer;
+ 	int ret;
+ 
+-	mtu  = ETH_HLEN;
+-	mtu += netdev->mtu;
+-	if (skb->protocol == htons(ETH_P_8021Q))
+-		mtu += VLAN_HLEN;
+-
++	/* TODO: implement proper TSO using MTU in word3 */
+ 	word1 = skb->len;
+ 	word3 = SOF_BIT;
+ 
+-	if (word1 > mtu) {
+-		word1 |= TSS_MTU_ENABLE_BIT;
+-		word3 |= mtu;
+-	}
+-
+ 	if (skb->len >= ETH_FRAME_LEN) {
+ 		/* Hardware offloaded checksumming isn't working on frames
+ 		 * bigger than 1514 bytes. A hypothesis about this is that the
diff --git a/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch b/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch
new file mode 100644
index 0000000000..1d1ee2b46c
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0002-ARM-dts-gemini-Map-reset-keys-to-KEY_RESTART.patch
@@ -0,0 +1,103 @@
+From 091cde88b5ff2a2ca5739ce41f9cf5640a95222f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 11 Feb 2024 22:24:25 +0100
+Subject: [PATCH] ARM: dts: gemini: Map reset keys to KEY_RESTART
+
+This maps the misc "reset", "setup" and "facory reset" keys to the
+only key a standard userspace is likely to understand: KEY_RESTART.
+On OpenWrt this will simply restart the system under controlled
+forms.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20240211-gemini-dts-v1-3-6c09adeb4c2e@linaro.org
+---
+ arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-sl93512r.dts      | 2 +-
+ arch/arm/boot/dts/gemini/gemini-sq201.dts         | 2 +-
+ arch/arm/boot/dts/gemini/gemini-wbd111.dts        | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-wbd222.dts        | 4 ++--
+ 6 files changed, 10 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
+@@ -27,10 +27,10 @@
+ 	gpio_keys {
+ 		compatible = "gpio-keys";
+ 
+-		button-esc {
++		button-reset {
+ 			debounce-interval = <100>;
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
+ 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts
+@@ -33,10 +33,10 @@
+ 	gpio_keys {
+ 		compatible = "gpio-keys";
+ 
+-		button-esc {
++		button-reset {
+ 			debounce-interval = <100>;
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ 		};
+--- a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts
++++ b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts
+@@ -43,7 +43,7 @@
+ 		button-setup {
+ 			debounce-interval = <50>;
+ 			wakeup-source;
+-			linux,code = <KEY_SETUP>;
++			linux,code = <KEY_RESTART>;
+ 			label = "factory reset";
+ 			/* Conflict with NAND flash */
+ 			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-sq201.dts
++++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts
+@@ -30,7 +30,7 @@
+ 		button-setup {
+ 			debounce-interval = <100>;
+ 			wakeup-source;
+-			linux,code = <KEY_SETUP>;
++			linux,code = <KEY_RESTART>;
+ 			label = "factory reset";
+ 			/* Conflict with NAND flash */
+ 			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini/gemini-wbd111.dts
+@@ -28,10 +28,10 @@
+ 	gpio_keys {
+ 		compatible = "gpio-keys";
+ 
+-		button-setup {
++		button-reset {
+ 			debounce-interval = <100>;
+ 			wakeup-source;
+-			linux,code = <KEY_SETUP>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			/* Conflict with ICE */
+ 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini/gemini-wbd222.dts
+@@ -27,10 +27,10 @@
+ 	gpio_keys {
+ 		compatible = "gpio-keys";
+ 
+-		button-setup {
++		button-reset {
+ 			debounce-interval = <100>;
+ 			wakeup-source;
+-			linux,code = <KEY_SETUP>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			/* Conflict with ICE */
+ 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/gemini/patches-6.6/0003-net-ethernet-cortina-Locking-fixes.patch b/target/linux/gemini/patches-6.6/0003-net-ethernet-cortina-Locking-fixes.patch
new file mode 100644
index 0000000000..661e9287c0
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0003-net-ethernet-cortina-Locking-fixes.patch
@@ -0,0 +1,73 @@
+From 81889eb2b37bc21df4ff259441e8fc12d4f27cd9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 08:48:31 +0200
+Subject: [PATCH] net: ethernet: cortina: Locking fixes
+
+This fixes a probably long standing problem in the Cortina
+Gemini ethernet driver: there are some paths in the code
+where the IRQ registers are written without taking the proper
+locks.
+
+Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1107,10 +1107,13 @@ static void gmac_tx_irq_enable(struct ne
+ {
+ 	struct gemini_ethernet_port *port = netdev_priv(netdev);
+ 	struct gemini_ethernet *geth = port->geth;
++	unsigned long flags;
+ 	u32 val, mask;
+ 
+ 	netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
+ 
++	spin_lock_irqsave(&geth->irq_lock, flags);
++
+ 	mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
+ 
+ 	if (en)
+@@ -1119,6 +1122,8 @@ static void gmac_tx_irq_enable(struct ne
+ 	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
+ 	val = en ? val | mask : val & ~mask;
+ 	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++
++	spin_unlock_irqrestore(&geth->irq_lock, flags);
+ }
+ 
+ static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
+@@ -1415,15 +1420,19 @@ static unsigned int gmac_rx(struct net_d
+ 	union gmac_rxdesc_3 word3;
+ 	struct page *page = NULL;
+ 	unsigned int page_offs;
++	unsigned long flags;
+ 	unsigned short r, w;
+ 	union dma_rwptr rw;
+ 	dma_addr_t mapping;
+ 	int frag_nr = 0;
+ 
++	spin_lock_irqsave(&geth->irq_lock, flags);
+ 	rw.bits32 = readl(ptr_reg);
+ 	/* Reset interrupt as all packages until here are taken into account */
+ 	writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
+ 	       geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++	spin_unlock_irqrestore(&geth->irq_lock, flags);
++
+ 	r = rw.bits.rptr;
+ 	w = rw.bits.wptr;
+ 
+@@ -1726,10 +1735,9 @@ static irqreturn_t gmac_irq(int irq, voi
+ 		gmac_update_hw_stats(netdev);
+ 
+ 	if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
++		spin_lock(&geth->irq_lock);
+ 		writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
+ 		       geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
+-
+-		spin_lock(&geth->irq_lock);
+ 		u64_stats_update_begin(&port->ir_stats_syncp);
+ 		++port->stats.rx_fifo_errors;
+ 		u64_stats_update_end(&port->ir_stats_syncp);
diff --git a/target/linux/gemini/patches-6.6/0004-net-ethernet-cortina-Restore-TSO-support.patch b/target/linux/gemini/patches-6.6/0004-net-ethernet-cortina-Restore-TSO-support.patch
new file mode 100644
index 0000000000..809941a95d
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0004-net-ethernet-cortina-Restore-TSO-support.patch
@@ -0,0 +1,124 @@
+From 30fcba19ed88997a2909e4a68b4d39ff371357c3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 1 May 2024 21:46:31 +0200
+Subject: [PATCH 1/5] net: ethernet: cortina: Restore TSO support
+
+An earlier commit deleted the TSO support in the Cortina Gemini
+driver because the driver was confusing gso_size and MTU,
+probably because what the Linux kernel calls "gso_size" was
+called "MTU" in the datasheet.
+
+Restore the functionality properly reading the gso_size from
+the skbuff.
+
+Tested with iperf3, running a server on a different machine
+and client on the device with the cortina gemini ethernet:
+
+Connecting to host 192.168.1.2, port 5201
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=27da
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=0b92
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=2bda
+(...)
+
+(The hardware MSS 0x05ea here includes the ethernet headers.)
+
+If I disable all segment offloading on the receiving host and
+dump packets using tcpdump -xx like this:
+
+ethtool -K enp2s0 gro off gso off tso off
+tcpdump -xx -i enp2s0 host 192.168.1.136
+
+I get segmented packages such as this when running iperf3:
+
+23:16:54.024139 IP OpenWrt.lan.59168 > Fecusia.targus-getdata1:
+Flags [.], seq 1486:2934, ack 1, win 4198,
+options [nop,nop,TS val 3886192908 ecr 3601341877], length 1448
+0x0000:  fc34 9701 a0c6 14d6 4da8 3c4f 0800 4500
+0x0010:  05dc 16a0 4000 4006 9aa1 c0a8 0188 c0a8
+0x0020:  0102 e720 1451 ff25 9822 4c52 29cf 8010
+0x0030:  1066 ac8c 0000 0101 080a e7a2 990c d6a8
+(...)
+0x05c0:  5e49 e109 fe8c 4617 5e18 7a82 7eae d647
+0x05d0:  e8ee ae64 dc88 c897 3f8a 07a4 3a33 6b1b
+0x05e0:  3501 a30f 2758 cc44 4b4a
+
+Several such packets often follow after each other verifying
+the segmentation into 0x05a8 (1448) byte packages also on the
+reveiving end. As can be seen, the ethernet frames are
+0x05ea (1514) in size.
+
+Performance with iperf3 before this patch: ~15.5 Mbit/s
+Performance with iperf3 after this patch: ~175 Mbit/s
+
+This was running a 60 second test (twice) the best measurement
+was 179 Mbit/s.
+
+For comparison if I run iperf3 with UDP I get around 1.05 Mbit/s
+both before and after this patch.
+
+While this is a gigabit ethernet interface, the CPU is a cheap
+D-Link DIR-685 router (based on the ARMv5 Faraday FA526 at
+~50 MHz), and the software is not supposed to drive traffic,
+as the device has a DSA chip, so this kind of numbers can be
+expected.
+
+Fixes: ac631873c9e7 ("net: ethernet: cortina: Drop TSO support")
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 23 +++++++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -79,7 +79,8 @@ MODULE_PARM_DESC(debug, "Debug level (0=
+ #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
+ 
+ #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
+-			       NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)
++			       NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
++			       NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
+ 
+ /**
+  * struct gmac_queue_page - page buffer per-page info
+@@ -1148,13 +1149,25 @@ static int gmac_map_tx_bufs(struct net_d
+ 	skb_frag_t *skb_frag;
+ 	dma_addr_t mapping;
+ 	void *buffer;
++	u16 mss;
+ 	int ret;
+ 
+-	/* TODO: implement proper TSO using MTU in word3 */
+ 	word1 = skb->len;
+ 	word3 = SOF_BIT;
+ 
+-	if (skb->len >= ETH_FRAME_LEN) {
++	mss = skb_shinfo(skb)->gso_size;
++	if (mss) {
++		/* This means we are dealing with TCP and skb->len is the
++		 * sum total of all the segments. The TSO will deal with
++		 * chopping this up for us.
++		 */
++		/* The accelerator needs the full frame size here */
++		mss += skb_tcp_all_headers(skb);
++		netdev_dbg(netdev, "segment offloading mss = %04x len=%04x\n",
++			   mss, skb->len);
++		word1 |= TSS_MTU_ENABLE_BIT;
++		word3 |= mss;
++	} else if (skb->len >= ETH_FRAME_LEN) {
+ 		/* Hardware offloaded checksumming isn't working on frames
+ 		 * bigger than 1514 bytes. A hypothesis about this is that the
+ 		 * checksum buffer is only 1518 bytes, so when the frames get
+@@ -1169,7 +1182,9 @@ static int gmac_map_tx_bufs(struct net_d
+ 				return ret;
+ 		}
+ 		word1 |= TSS_BYPASS_BIT;
+-	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
++	}
++
++	if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ 		int tcp = 0;
+ 
+ 		/* We do not switch off the checksumming on non TCP/UDP
diff --git a/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch b/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch
new file mode 100644
index 0000000000..c690b8fddb
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0005-net-ethernet-cortina-Use-TSO-also-on-common-TCP.patch
@@ -0,0 +1,95 @@
+From 91fb8a7328dda827bc6c0da240a1eb17028416cd Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 23:59:28 +0200
+Subject: [PATCH 2/5] net: ethernet: cortina: Use TSO also on common TCP
+
+It is possible to push the segment offloader to also
+process non-segmented frames: just pass the skb->len
+or desired MSS to the offloader and it will handle them.
+
+This is especially good if the user sets up the MTU
+and the frames get big, because the checksumming engine
+cannot handle any frames bigger than 1518 bytes, so
+segmenting them all to be at max that will be helpful
+for the hardware, which only need to quirk odd frames
+such as big UDP ping packets.
+
+The vendor driver always uses the TSO like this, and
+the driver seems more stable after this, so apparently
+the hardware may have been engineered to always use
+the TSO on anything it can handle.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 31 +++++++++++++++++++++------
+ 1 file changed, 24 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1148,6 +1148,7 @@ static int gmac_map_tx_bufs(struct net_d
+ 	struct gmac_txdesc *txd;
+ 	skb_frag_t *skb_frag;
+ 	dma_addr_t mapping;
++	bool tcp = false;
+ 	void *buffer;
+ 	u16 mss;
+ 	int ret;
+@@ -1155,6 +1156,13 @@ static int gmac_map_tx_bufs(struct net_d
+ 	word1 = skb->len;
+ 	word3 = SOF_BIT;
+ 
++	/* Determine if we are doing TCP */
++	if (skb->protocol == htons(ETH_P_IP))
++		tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP);
++	else
++		/* IPv6 */
++		tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP);
++
+ 	mss = skb_shinfo(skb)->gso_size;
+ 	if (mss) {
+ 		/* This means we are dealing with TCP and skb->len is the
+@@ -1167,6 +1175,20 @@ static int gmac_map_tx_bufs(struct net_d
+ 			   mss, skb->len);
+ 		word1 |= TSS_MTU_ENABLE_BIT;
+ 		word3 |= mss;
++	} else if (tcp) {
++		/* Even if we are not using TSO, use the segment offloader
++		 * for transferring the TCP frame: the TSO engine will deal
++		 * with chopping up frames that exceed ETH_DATA_LEN which
++		 * the checksumming engine cannot handle (see below) into
++		 * manageable chunks. It flawlessly deals with quite big
++		 * frames and frames containing custom DSA EtherTypes.
++		 */
++		mss = netdev->mtu + skb_tcp_all_headers(skb);
++		mss = min(mss, skb->len);
++		netdev_dbg(netdev, "botched TSO len %04x mtu %04x mss %04x\n",
++			   skb->len, netdev->mtu, mss);
++		word1 |= TSS_MTU_ENABLE_BIT;
++		word3 |= mss;
+ 	} else if (skb->len >= ETH_FRAME_LEN) {
+ 		/* Hardware offloaded checksumming isn't working on frames
+ 		 * bigger than 1514 bytes. A hypothesis about this is that the
+@@ -1185,21 +1207,16 @@ static int gmac_map_tx_bufs(struct net_d
+ 	}
+ 
+ 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
+-		int tcp = 0;
+-
+ 		/* We do not switch off the checksumming on non TCP/UDP
+ 		 * frames: as is shown from tests, the checksumming engine
+ 		 * is smart enough to see that a frame is not actually TCP
+ 		 * or UDP and then just pass it through without any changes
+ 		 * to the frame.
+ 		 */
+-		if (skb->protocol == htons(ETH_P_IP)) {
++		if (skb->protocol == htons(ETH_P_IP))
+ 			word1 |= TSS_IP_CHKSUM_BIT;
+-			tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
+-		} else { /* IPv6 */
++		else
+ 			word1 |= TSS_IPV6_ENABLE_BIT;
+-			tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
+-		}
+ 
+ 		word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
+ 	}
diff --git a/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch b/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch
new file mode 100644
index 0000000000..bbdef8fefc
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0006-net-ethernet-cortina-Rename-adjust-link-callback.patch
@@ -0,0 +1,36 @@
+From fa01c904b844e6033445f75b0b4d46a8e83b6086 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:48:27 +0200
+Subject: [PATCH 3/5] net: ethernet: cortina: Rename adjust link callback
+
+The callback passed to of_phy_get_and_connect() in the
+Cortina Gemini driver is called "gmac_speed_set" which is
+archaic, rename it to "gmac_adjust_link" following the
+pattern of most other drivers.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -288,7 +288,7 @@ static void gmac_set_flow_control(struct
+ 	spin_unlock_irqrestore(&port->config_lock, flags);
+ }
+ 
+-static void gmac_speed_set(struct net_device *netdev)
++static void gmac_adjust_link(struct net_device *netdev)
+ {
+ 	struct gemini_ethernet_port *port = netdev_priv(netdev);
+ 	struct phy_device *phydev = netdev->phydev;
+@@ -367,7 +367,7 @@ static int gmac_setup_phy(struct net_dev
+ 
+ 	phy = of_phy_get_and_connect(netdev,
+ 				     dev->of_node,
+-				     gmac_speed_set);
++				     gmac_adjust_link);
+ 	if (!phy)
+ 		return -ENODEV;
+ 	netdev->phydev = phy;
diff --git a/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch b/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch
new file mode 100644
index 0000000000..a1b8707f72
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0007-net-ethernet-cortina-Use-negotiated-TX-RX-pause.patch
@@ -0,0 +1,46 @@
+From 50ac9765c674bac803719c6b8294670edc6df31d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:44:39 +0200
+Subject: [PATCH 4/5] net: ethernet: cortina: Use negotiated TX/RX pause
+
+Instead of directly poking into registers of the PHY, use
+the existing function to query phylib about this directly.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -293,8 +293,8 @@ static void gmac_adjust_link(struct net_
+ 	struct gemini_ethernet_port *port = netdev_priv(netdev);
+ 	struct phy_device *phydev = netdev->phydev;
+ 	union gmac_status status, old_status;
+-	int pause_tx = 0;
+-	int pause_rx = 0;
++	bool pause_tx = false;
++	bool pause_rx = false;
+ 
+ 	status.bits32 = readl(port->gmac_base + GMAC_STATUS);
+ 	old_status.bits32 = status.bits32;
+@@ -329,14 +329,9 @@ static void gmac_adjust_link(struct net_
+ 	}
+ 
+ 	if (phydev->duplex == DUPLEX_FULL) {
+-		u16 lcladv = phy_read(phydev, MII_ADVERTISE);
+-		u16 rmtadv = phy_read(phydev, MII_LPA);
+-		u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
+-
+-		if (cap & FLOW_CTRL_RX)
+-			pause_rx = 1;
+-		if (cap & FLOW_CTRL_TX)
+-			pause_tx = 1;
++		phy_get_pause(phydev, &pause_tx, &pause_rx);
++		netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n",
++			   pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF");
+ 	}
+ 
+ 	gmac_set_flow_control(netdev, pause_tx, pause_rx);
diff --git a/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch b/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch
new file mode 100644
index 0000000000..ad7594e855
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/0008-net-ethernet-cortina-Implement-.set_pauseparam.patch
@@ -0,0 +1,46 @@
+From 4eed4b87f17d10b7586349c13c3a30f9c24c9ba4 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 8 May 2024 23:21:17 +0200
+Subject: [PATCH 5/5] net: ethernet: cortina: Implement .set_pauseparam()
+
+The Cortina Gemini ethernet can very well set up TX or RX
+pausing, so add this functionality to the driver in a
+.set_pauseparam() callback. Essentially just call down to
+phylib and let phylib deal with this, .adjust_link()
+will respect the setting from phylib.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -2143,6 +2143,19 @@ static void gmac_get_pauseparam(struct n
+ 	pparam->autoneg = true;
+ }
+ 
++static int gmac_set_pauseparam(struct net_device *netdev,
++			       struct ethtool_pauseparam *pparam)
++{
++	struct phy_device *phydev = netdev->phydev;
++
++	if (!pparam->autoneg)
++		return -EOPNOTSUPP;
++
++	phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause);
++
++	return 0;
++}
++
+ static void gmac_get_ringparam(struct net_device *netdev,
+ 			       struct ethtool_ringparam *rp,
+ 			       struct kernel_ethtool_ringparam *kernel_rp,
+@@ -2263,6 +2276,7 @@ static const struct ethtool_ops gmac_351
+ 	.set_link_ksettings = gmac_set_ksettings,
+ 	.nway_reset	= gmac_nway_reset,
+ 	.get_pauseparam	= gmac_get_pauseparam,
++	.set_pauseparam = gmac_set_pauseparam,
+ 	.get_ringparam	= gmac_get_ringparam,
+ 	.set_ringparam	= gmac_set_ringparam,
+ 	.get_coalesce	= gmac_get_coalesce,
diff --git a/target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch b/target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch
new file mode 100644
index 0000000000..613c3a842f
--- /dev/null
+++ b/target/linux/gemini/patches-6.6/300-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch
@@ -0,0 +1,37 @@
+From c1aa34cd568bc7b86b82353034070c32b6ebe6db Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 11 Mar 2019 15:44:29 +0100
+Subject: [PATCH] ARM: dts: Augment DIR-685 partition table for OpenWrt
+
+Rename the firmware partition so that the firmware MTD
+splitter will do its job, drop the rootfs arguments as
+the MTD splitter will set this up automatically.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
+@@ -20,7 +20,7 @@
+ 	};
+ 
+ 	chosen {
+-		bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
++		bootargs = "console=ttyS0,19200n8 consoleblank=300";
+ 		stdout-path = "uart0:19200n8";
+ 	};
+ 
+@@ -317,9 +317,9 @@
+ 				 * this is called "upgrade" on the vendor system.
+ 				 */
+ 				partition@40000 {
+-					label = "upgrade";
++					compatible = "wrg";
++					label = "firmware";
+ 					reg = <0x00040000 0x01f40000>;
+-					read-only;
+ 				};
+ 				/* RGDB, Residental Gateway Database? */
+ 				partition@1f80000 {
diff --git a/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch
index 2ea2e2497a..8e4de36db0 100644
--- a/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch
+++ b/target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch
@@ -73,7 +73,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
 
 --- a/arch/Kconfig
 +++ b/arch/Kconfig
-@@ -1299,6 +1299,14 @@ config ARCH_HAS_ELFCORE_COMPAT
+@@ -1307,6 +1307,14 @@ config ARCH_HAS_ELFCORE_COMPAT
  config ARCH_HAS_PARANOID_L1D_FLUSH
  	bool
  
@@ -90,7 +90,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
  source "scripts/gcc-plugins/Kconfig"
 --- a/arch/x86/Kconfig
 +++ b/arch/x86/Kconfig
-@@ -85,6 +85,7 @@ config X86
+@@ -86,6 +86,7 @@ config X86
  	select ARCH_HAS_PMEM_API		if X86_64
  	select ARCH_HAS_PTE_DEVMAP		if X86_64
  	select ARCH_HAS_PTE_SPECIAL
diff --git a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch
index 85710eb79b..ff4bb4df3e 100644
--- a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch
+++ b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch
@@ -552,7 +552,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
 --- a/kernel/bounds.c
 +++ b/kernel/bounds.c
 @@ -22,6 +22,11 @@ int main(void)
- 	DEFINE(NR_CPUS_BITS, bits_per(CONFIG_NR_CPUS));
+ 	DEFINE(NR_CPUS_BITS, order_base_2(CONFIG_NR_CPUS));
  #endif
  	DEFINE(SPINLOCK_SIZE, sizeof(spinlock_t));
 +#ifdef CONFIG_LRU_GEN
diff --git a/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch b/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch
index f56a968589..8e5c718042 100644
--- a/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch
+++ b/target/linux/generic/backport-5.15/700-v5.17-net-dsa-introduce-tagger-owned-storage-for-private.patch
@@ -124,7 +124,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	list_del(&dst->list);
  	kfree(dst);
  }
-@@ -805,7 +809,7 @@ static int dsa_switch_setup_tag_protocol
+@@ -827,7 +831,7 @@ static int dsa_switch_setup_tag_protocol
  	int port, err;
  
  	if (tag_ops->proto == dst->default_proto)
@@ -133,7 +133,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	for (port = 0; port < ds->num_ports; port++) {
  		if (!dsa_is_cpu_port(ds, port))
-@@ -821,6 +825,17 @@ static int dsa_switch_setup_tag_protocol
+@@ -843,6 +847,17 @@ static int dsa_switch_setup_tag_protocol
  		}
  	}
  
@@ -151,7 +151,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return 0;
  }
  
-@@ -1132,6 +1147,46 @@ static void dsa_tree_teardown(struct dsa
+@@ -1154,6 +1169,46 @@ static void dsa_tree_teardown(struct dsa
  	dst->setup = false;
  }
  
@@ -198,7 +198,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /* Since the dsa/tagging sysfs device attribute is per master, the assumption
   * is that all DSA switches within a tree share the same tagger, otherwise
   * they would have formed disjoint trees (different "dsa,member" values).
-@@ -1164,12 +1219,15 @@ int dsa_tree_change_tag_proto(struct dsa
+@@ -1186,12 +1241,15 @@ int dsa_tree_change_tag_proto(struct dsa
  			goto out_unlock;
  	}
  
@@ -216,7 +216,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	rtnl_unlock();
  
-@@ -1257,6 +1315,7 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1279,6 +1337,7 @@ static int dsa_port_parse_cpu(struct dsa
  	struct dsa_switch *ds = dp->ds;
  	struct dsa_switch_tree *dst = ds->dst;
  	enum dsa_tag_protocol default_proto;
@@ -224,7 +224,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/* Find out which protocol the switch would prefer. */
  	default_proto = dsa_get_tag_protocol(dp, master);
-@@ -1311,6 +1370,12 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1333,6 +1392,12 @@ static int dsa_port_parse_cpu(struct dsa
  		 */
  		dsa_tag_driver_put(tag_ops);
  	} else {
diff --git a/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch b/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch
index 0c50ae6fb9..8c81ebc7f5 100644
--- a/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch
+++ b/target/linux/generic/backport-5.15/701-v5.17-dsa-make-tagging-protocols-connect-to-individual-switches.patch
@@ -101,7 +101,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	list_del(&dst->list);
  	kfree(dst);
  }
-@@ -826,17 +822,29 @@ static int dsa_switch_setup_tag_protocol
+@@ -848,17 +844,29 @@ static int dsa_switch_setup_tag_protocol
  	}
  
  connect:
@@ -132,7 +132,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int dsa_switch_setup(struct dsa_switch *ds)
-@@ -1156,13 +1164,6 @@ static int dsa_tree_bind_tag_proto(struc
+@@ -1178,13 +1186,6 @@ static int dsa_tree_bind_tag_proto(struc
  
  	dst->tag_ops = tag_ops;
  
@@ -146,7 +146,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* Notify the switches from this tree about the connection
  	 * to the new tagger
  	 */
-@@ -1172,16 +1173,14 @@ static int dsa_tree_bind_tag_proto(struc
+@@ -1194,16 +1195,14 @@ static int dsa_tree_bind_tag_proto(struc
  		goto out_disconnect;
  
  	/* Notify the old tagger about the disconnection from this tree */
@@ -167,7 +167,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	dst->tag_ops = old_tag_ops;
  
  	return err;
-@@ -1315,7 +1314,6 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1337,7 +1336,6 @@ static int dsa_port_parse_cpu(struct dsa
  	struct dsa_switch *ds = dp->ds;
  	struct dsa_switch_tree *dst = ds->dst;
  	enum dsa_tag_protocol default_proto;
@@ -175,7 +175,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/* Find out which protocol the switch would prefer. */
  	default_proto = dsa_get_tag_protocol(dp, master);
-@@ -1370,12 +1368,6 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1392,12 +1390,6 @@ static int dsa_port_parse_cpu(struct dsa
  		 */
  		dsa_tag_driver_put(tag_ops);
  	} else {
diff --git a/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch b/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch
deleted file mode 100644
index 9f2512a1d0..0000000000
--- a/target/linux/generic/backport-5.15/702-v5.19-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Mon, 7 Feb 2022 10:27:22 +0100
-Subject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent
- DMA
-
-It improves performance by eliminating the need for a cache flush on rx and tx
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -357,7 +357,7 @@
- 		};
- 
- 		cci_control2: slave-if@5000 {
--			compatible = "arm,cci-400-ctrl-if";
-+			compatible = "arm,cci-400-ctrl-if", "syscon";
- 			interface-type = "ace";
- 			reg = <0x5000 0x1000>;
- 		};
-@@ -938,6 +938,8 @@
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- 		mediatek,ethsys = <&ethsys>;
- 		mediatek,sgmiisys = <&sgmiisys>;
-+		mediatek,cci-control = <&cci_control2>;
-+		dma-coherent;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		status = "disabled";
diff --git a/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch b/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch
deleted file mode 100644
index 2c6e3fd3cd..0000000000
--- a/target/linux/generic/backport-5.15/702-v5.19-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Sat, 5 Feb 2022 18:36:36 +0100
-Subject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for
- Wireless Ethernet Dispatch
-
-Introduce wed0 and wed1 nodes in order to enable offloading forwarding
-between ethernet and wireless devices on the mt7622 chipset.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -894,6 +894,11 @@
- 		};
- 	};
- 
-+	hifsys: syscon@1af00000 {
-+		compatible = "mediatek,mt7622-hifsys", "syscon";
-+		reg = <0 0x1af00000 0 0x70>;
-+	};
-+
- 	ethsys: syscon@1b000000 {
- 		compatible = "mediatek,mt7622-ethsys",
- 			     "syscon";
-@@ -912,6 +917,26 @@
- 		#dma-cells = <1>;
- 	};
- 
-+	pcie_mirror: pcie-mirror@10000400 {
-+		compatible = "mediatek,mt7622-pcie-mirror",
-+			     "syscon";
-+		reg = <0 0x10000400 0 0x10>;
-+	};
-+
-+	wed0: wed@1020a000 {
-+		compatible = "mediatek,mt7622-wed",
-+			     "syscon";
-+		reg = <0 0x1020a000 0 0x1000>;
-+		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
-+	wed1: wed@1020b000 {
-+		compatible = "mediatek,mt7622-wed",
-+			     "syscon";
-+		reg = <0 0x1020b000 0 0x1000>;
-+		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
- 	eth: ethernet@1b100000 {
- 		compatible = "mediatek,mt7622-eth",
- 			     "mediatek,mt2701-eth",
-@@ -939,6 +964,9 @@
- 		mediatek,ethsys = <&ethsys>;
- 		mediatek,sgmiisys = <&sgmiisys>;
- 		mediatek,cci-control = <&cci_control2>;
-+		mediatek,wed = <&wed0>, <&wed1>;
-+		mediatek,pcie-mirror = <&pcie_mirror>;
-+		mediatek,hifsys = <&hifsys>;
- 		dma-coherent;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
diff --git a/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch b/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch
index 70d46c16cd..22125a4546 100644
--- a/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch
+++ b/target/linux/generic/backport-5.15/702-v5.19-13-net-ethernet-mtk_eth_soc-use-standard-property-for-c.patch
@@ -13,7 +13,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -963,7 +963,7 @@
+@@ -957,7 +957,7 @@
  		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
  		mediatek,ethsys = <&ethsys>;
  		mediatek,sgmiisys = <&sgmiisys>;
diff --git a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch
index 3f7f328247..f65b0cafa8 100644
--- a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch
+++ b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch
@@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1243,27 +1243,31 @@ static int
+@@ -1425,27 +1425,31 @@ static int
  mt7530_port_bridge_join(struct dsa_switch *ds, int port,
  			struct net_device *bridge)
  {
@@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	/* Add the all other ports to this port matrix. */
-@@ -1368,24 +1372,28 @@ static void
+@@ -1550,24 +1554,28 @@ static void
  mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
  			 struct net_device *bridge)
  {
diff --git a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch
index c3902bb9c5..e04bb11e80 100644
--- a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch
+++ b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch
@@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2499,6 +2499,32 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2687,6 +2687,32 @@ mt7531_setup(struct dsa_switch *ds)
  	return 0;
  }
  
@@ -56,7 +56,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static bool
  mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
  			  const struct phylink_link_state *state)
-@@ -2535,6 +2561,37 @@ static bool mt7531_is_rgmii_port(struct
+@@ -2723,6 +2749,37 @@ static bool mt7531_is_rgmii_port(struct
  	return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
  }
  
@@ -94,7 +94,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static bool
  mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
  			  const struct phylink_link_state *state)
-@@ -3011,6 +3068,18 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3199,6 +3256,18 @@ mt7531_cpu_port_config(struct dsa_switch
  	return 0;
  }
  
@@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void
  mt7530_mac_port_validate(struct dsa_switch *ds, int port,
  			 unsigned long *supported)
-@@ -3246,6 +3315,7 @@ static const struct dsa_switch_ops mt753
+@@ -3435,6 +3504,7 @@ static const struct dsa_switch_ops mt753
  	.port_vlan_del		= mt7530_port_vlan_del,
  	.port_mirror_add	= mt753x_port_mirror_add,
  	.port_mirror_del	= mt753x_port_mirror_del,
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	.phylink_validate	= mt753x_phylink_validate,
  	.phylink_mac_link_state	= mt753x_phylink_mac_link_state,
  	.phylink_mac_config	= mt753x_phylink_mac_config,
-@@ -3263,6 +3333,7 @@ static const struct mt753x_info mt753x_t
+@@ -3452,6 +3522,7 @@ static const struct mt753x_info mt753x_t
  		.phy_read = mt7530_phy_read,
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
@@ -129,7 +129,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.phy_mode_supported = mt7530_phy_mode_supported,
  		.mac_port_validate = mt7530_mac_port_validate,
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
-@@ -3274,6 +3345,7 @@ static const struct mt753x_info mt753x_t
+@@ -3463,6 +3534,7 @@ static const struct mt753x_info mt753x_t
  		.phy_read = mt7530_phy_read,
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
@@ -137,7 +137,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.phy_mode_supported = mt7530_phy_mode_supported,
  		.mac_port_validate = mt7530_mac_port_validate,
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
-@@ -3286,6 +3358,7 @@ static const struct mt753x_info mt753x_t
+@@ -3475,6 +3547,7 @@ static const struct mt753x_info mt753x_t
  		.phy_write = mt7531_ind_phy_write,
  		.pad_setup = mt7531_pad_setup,
  		.cpu_port_config = mt7531_cpu_port_config,
@@ -145,7 +145,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.phy_mode_supported = mt7531_phy_mode_supported,
  		.mac_port_validate = mt7531_mac_port_validate,
  		.mac_port_get_state = mt7531_phylink_mac_link_state,
-@@ -3348,6 +3421,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3537,6 +3610,7 @@ mt7530_probe(struct mdio_device *mdiodev
  	 */
  	if (!priv->info->sw_setup || !priv->info->pad_setup ||
  	    !priv->info->phy_read || !priv->info->phy_write ||
@@ -155,7 +155,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	    !priv->info->mac_port_get_state || !priv->info->mac_port_config)
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -796,6 +796,8 @@ struct mt753x_info {
+@@ -807,6 +807,8 @@ struct mt753x_info {
  	int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
  	int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
  	int (*cpu_port_config)(struct dsa_switch *ds, int port);
diff --git a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch
index d1d56f5aa8..31be0e7be3 100644
--- a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch
+++ b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch
@@ -21,7 +21,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2525,37 +2525,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2713,37 +2713,6 @@ static void mt7530_mac_port_get_caps(str
  	}
  }
  
@@ -59,7 +59,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
  {
  	return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
-@@ -2592,44 +2561,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2780,44 +2749,6 @@ static void mt7531_mac_port_get_caps(str
  	}
  }
  
@@ -104,7 +104,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int
  mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
  {
-@@ -2884,9 +2815,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -3072,9 +3003,6 @@ mt753x_phylink_mac_config(struct dsa_swi
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr_cur, mcr_new;
  
@@ -114,7 +114,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	switch (port) {
  	case 0 ... 4: /* Internal phy */
  		if (state->interface != PHY_INTERFACE_MODE_GMII)
-@@ -3102,12 +3030,6 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3290,12 +3218,6 @@ mt753x_phylink_validate(struct dsa_switc
  	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
  	struct mt7530_priv *priv = ds->priv;
  
@@ -127,7 +127,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	phylink_set_port_modes(mask);
  
  	if (state->interface != PHY_INTERFACE_MODE_TRGMII &&
-@@ -3334,7 +3256,6 @@ static const struct mt753x_info mt753x_t
+@@ -3523,7 +3445,6 @@ static const struct mt753x_info mt753x_t
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
@@ -135,7 +135,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_validate = mt7530_mac_port_validate,
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
  		.mac_port_config = mt7530_mac_config,
-@@ -3346,7 +3267,6 @@ static const struct mt753x_info mt753x_t
+@@ -3535,7 +3456,6 @@ static const struct mt753x_info mt753x_t
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
@@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_validate = mt7530_mac_port_validate,
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
  		.mac_port_config = mt7530_mac_config,
-@@ -3359,7 +3279,6 @@ static const struct mt753x_info mt753x_t
+@@ -3548,7 +3468,6 @@ static const struct mt753x_info mt753x_t
  		.pad_setup = mt7531_pad_setup,
  		.cpu_port_config = mt7531_cpu_port_config,
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
@@ -151,7 +151,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_validate = mt7531_mac_port_validate,
  		.mac_port_get_state = mt7531_phylink_mac_link_state,
  		.mac_port_config = mt7531_mac_config,
-@@ -3422,7 +3341,6 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3611,7 +3530,6 @@ mt7530_probe(struct mdio_device *mdiodev
  	if (!priv->info->sw_setup || !priv->info->pad_setup ||
  	    !priv->info->phy_read || !priv->info->phy_write ||
  	    !priv->info->mac_port_get_caps ||
@@ -161,7 +161,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return -EINVAL;
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -798,8 +798,6 @@ struct mt753x_info {
+@@ -809,8 +809,6 @@ struct mt753x_info {
  	int (*cpu_port_config)(struct dsa_switch *ds, int port);
  	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
  				  struct phylink_config *config);
diff --git a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch
index 19b44d35ed..2a5d5ae9d9 100644
--- a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch
+++ b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3054,11 +3054,6 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3242,11 +3242,6 @@ mt753x_phylink_validate(struct dsa_switc
  
  	linkmode_and(supported, supported, mask);
  	linkmode_and(state->advertising, state->advertising, mask);
diff --git a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch
index 5e55f92fc7..ad672312e4 100644
--- a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch
+++ b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch
@@ -23,7 +23,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2632,12 +2632,13 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2820,12 +2820,13 @@ static int mt7531_rgmii_setup(struct mt7
  }
  
  static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
@@ -38,7 +38,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		phylink_set(supported, 2500baseX_Full);
  		phylink_set(supported, 2500baseT_Full);
  	}
-@@ -3010,16 +3011,18 @@ static void mt753x_phylink_get_caps(stru
+@@ -3198,16 +3199,18 @@ static void mt753x_phylink_get_caps(stru
  
  static void
  mt7530_mac_port_validate(struct dsa_switch *ds, int port,
@@ -58,7 +58,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -3042,12 +3045,13 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3230,12 +3233,13 @@ mt753x_phylink_validate(struct dsa_switc
  	}
  
  	/* This switch only supports 1G full-duplex. */
@@ -76,7 +76,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	phylink_set(mask, Asym_Pause);
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -799,6 +799,7 @@ struct mt753x_info {
+@@ -810,6 +810,7 @@ struct mt753x_info {
  	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
  				  struct phylink_config *config);
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
diff --git a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch
index ddf368fa1a..8d9802f1ee 100644
--- a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch
+++ b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2631,19 +2631,6 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2819,19 +2819,6 @@ static int mt7531_rgmii_setup(struct mt7
  	return 0;
  }
  
@@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void
  mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
  			   unsigned int mode, phy_interface_t interface,
-@@ -3010,51 +2997,21 @@ static void mt753x_phylink_get_caps(stru
+@@ -3198,51 +3185,21 @@ static void mt753x_phylink_get_caps(stru
  }
  
  static void
@@ -97,7 +97,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	linkmode_and(supported, supported, mask);
  	linkmode_and(state->advertising, state->advertising, mask);
-@@ -3255,7 +3212,6 @@ static const struct mt753x_info mt753x_t
+@@ -3444,7 +3401,6 @@ static const struct mt753x_info mt753x_t
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
@@ -105,7 +105,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3266,7 +3222,6 @@ static const struct mt753x_info mt753x_t
+@@ -3455,7 +3411,6 @@ static const struct mt753x_info mt753x_t
  		.phy_write = mt7530_phy_write,
  		.pad_setup = mt7530_pad_clk_setup,
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
@@ -113,7 +113,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_get_state = mt7530_phylink_mac_link_state,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3278,7 +3233,6 @@ static const struct mt753x_info mt753x_t
+@@ -3467,7 +3422,6 @@ static const struct mt753x_info mt753x_t
  		.pad_setup = mt7531_pad_setup,
  		.cpu_port_config = mt7531_cpu_port_config,
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_get_state = mt7531_phylink_mac_link_state,
  		.mac_port_config = mt7531_mac_config,
  		.mac_pcs_an_restart = mt7531_sgmii_restart_an,
-@@ -3340,7 +3294,6 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3529,7 +3483,6 @@ mt7530_probe(struct mdio_device *mdiodev
  	if (!priv->info->sw_setup || !priv->info->pad_setup ||
  	    !priv->info->phy_read || !priv->info->phy_write ||
  	    !priv->info->mac_port_get_caps ||
diff --git a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch
index 7f69ea2fb4..149c12c1fb 100644
--- a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch
+++ b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  /* String, offset, and register size in bytes if different from 4 bytes */
  static const struct mt7530_mib_desc mt7530_mib[] = {
  	MIB_DESC(1, 0x00, "TxDrop"),
-@@ -2631,12 +2636,11 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2819,12 +2824,11 @@ static int mt7531_rgmii_setup(struct mt7
  	return 0;
  }
  
@@ -50,7 +50,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	unsigned int val;
  
  	/* For adjusting speed and duplex of SGMII force mode. */
-@@ -2662,6 +2666,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw
+@@ -2850,6 +2854,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw
  
  	/* MT7531 SGMII 1G force mode can only work in full duplex mode,
  	 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
@@ -60,7 +60,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	 */
  	if ((speed == SPEED_10 || speed == SPEED_100) &&
  	    duplex != DUPLEX_FULL)
-@@ -2737,9 +2744,10 @@ static int mt7531_sgmii_setup_mode_an(st
+@@ -2925,9 +2932,10 @@ static int mt7531_sgmii_setup_mode_an(st
  	return 0;
  }
  
@@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	u32 val;
  
  	/* Only restart AN when AN is enabled */
-@@ -2796,6 +2804,24 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2984,6 +2992,24 @@ mt753x_mac_config(struct dsa_switch *ds,
  	return priv->info->mac_port_config(ds, port, mode, state->interface);
  }
  
@@ -98,7 +98,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void
  mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  			  const struct phylink_link_state *state)
-@@ -2857,17 +2883,6 @@ unsupported:
+@@ -3045,17 +3071,6 @@ unsupported:
  		mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
  }
  
@@ -116,7 +116,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
  					 unsigned int mode,
  					 phy_interface_t interface)
-@@ -2877,16 +2892,13 @@ static void mt753x_phylink_mac_link_down
+@@ -3065,16 +3080,13 @@ static void mt753x_phylink_mac_link_down
  	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
  }
  
@@ -139,7 +139,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
-@@ -2899,8 +2911,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -3087,8 +3099,6 @@ static void mt753x_phylink_mac_link_up(s
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr;
  
@@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
  
  	/* MT753x MAC works in 1G full duplex mode for all up-clocked
-@@ -2978,6 +2988,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3166,6 +3176,8 @@ mt7531_cpu_port_config(struct dsa_switch
  		return ret;
  	mt7530_write(priv, MT7530_PMCR_P(port),
  		     PMCR_CPU_PORT_SETTING(priv->id));
@@ -157,7 +157,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
  				   speed, DUPLEX_FULL, true, true);
  
-@@ -3017,16 +3029,13 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3205,16 +3217,13 @@ mt753x_phylink_validate(struct dsa_switc
  	linkmode_and(state->advertising, state->advertising, mask);
  }
  
@@ -178,7 +178,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
  
  	state->link = (pmsr & PMSR_LINK);
-@@ -3053,8 +3062,6 @@ mt7530_phylink_mac_link_state(struct dsa
+@@ -3241,8 +3250,6 @@ mt7530_phylink_mac_link_state(struct dsa
  		state->pause |= MLO_PAUSE_RX;
  	if (pmsr & PMSR_TX_FC)
  		state->pause |= MLO_PAUSE_TX;
@@ -187,7 +187,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static int
-@@ -3096,32 +3103,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3284,32 +3291,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
  	return 0;
  }
  
@@ -249,7 +249,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (ret)
  		return ret;
-@@ -3134,6 +3158,13 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3322,6 +3346,13 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -263,7 +263,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return ret;
  }
  
-@@ -3195,9 +3226,8 @@ static const struct dsa_switch_ops mt753
+@@ -3384,9 +3415,8 @@ static const struct dsa_switch_ops mt753
  	.port_mirror_del	= mt753x_port_mirror_del,
  	.phylink_get_caps	= mt753x_phylink_get_caps,
  	.phylink_validate	= mt753x_phylink_validate,
@@ -274,7 +274,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	.phylink_mac_link_down	= mt753x_phylink_mac_link_down,
  	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
  	.get_mac_eee		= mt753x_get_mac_eee,
-@@ -3207,36 +3237,34 @@ static const struct dsa_switch_ops mt753
+@@ -3396,36 +3426,34 @@ static const struct dsa_switch_ops mt753
  static const struct mt753x_info mt753x_table[] = {
  	[ID_MT7621] = {
  		.id = ID_MT7621,
@@ -314,7 +314,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	},
  };
  
-@@ -3294,7 +3322,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3483,7 +3511,7 @@ mt7530_probe(struct mdio_device *mdiodev
  	if (!priv->info->sw_setup || !priv->info->pad_setup ||
  	    !priv->info->phy_read || !priv->info->phy_write ||
  	    !priv->info->mac_port_get_caps ||
@@ -325,7 +325,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	priv->id = priv->info->id;
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -768,6 +768,12 @@ static const char *p5_intf_modes(unsigne
+@@ -779,6 +779,12 @@ static const char *p5_intf_modes(unsigne
  
  struct mt7530_priv;
  
@@ -338,7 +338,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  /* struct mt753x_info -	This is the main data structure for holding the specific
   *			part for each supported device
   * @sw_setup:		Holding the handler to a device initialization
-@@ -779,18 +785,14 @@ struct mt7530_priv;
+@@ -790,18 +796,14 @@ struct mt7530_priv;
   *			port
   * @mac_port_validate:	Holding the way to set addition validate type for a
   *			certan MAC port
@@ -359,7 +359,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	int (*sw_setup)(struct dsa_switch *ds);
  	int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
  	int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
-@@ -801,15 +803,9 @@ struct mt753x_info {
+@@ -812,15 +814,9 @@ struct mt753x_info {
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
  				  phy_interface_t interface,
  				  unsigned long *supported);
@@ -375,7 +375,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
  
  /* struct mt7530_priv -	This is the main data structure for holding the state
-@@ -851,6 +847,7 @@ struct mt7530_priv {
+@@ -862,6 +858,7 @@ struct mt7530_priv {
  	u8			mirror_tx;
  
  	struct mt7530_port	ports[MT7530_NUM_PORTS];
diff --git a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch
index 565a5d0bc5..6e406ace0d 100644
--- a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch
+++ b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3008,25 +3008,16 @@ static void mt753x_phylink_get_caps(stru
+@@ -3196,25 +3196,16 @@ static void mt753x_phylink_get_caps(stru
  	priv->info->mac_port_get_caps(ds, port, config);
  }
  
@@ -55,7 +55,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
-@@ -3128,12 +3119,14 @@ static void mt7530_pcs_an_restart(struct
+@@ -3316,12 +3307,14 @@ static void mt7530_pcs_an_restart(struct
  }
  
  static const struct phylink_pcs_ops mt7530_pcs_ops = {
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	.pcs_get_state = mt7531_pcs_get_state,
  	.pcs_config = mt753x_pcs_config,
  	.pcs_an_restart = mt7531_pcs_an_restart,
-@@ -3225,7 +3218,6 @@ static const struct dsa_switch_ops mt753
+@@ -3414,7 +3407,6 @@ static const struct dsa_switch_ops mt753
  	.port_mirror_add	= mt753x_port_mirror_add,
  	.port_mirror_del	= mt753x_port_mirror_del,
  	.phylink_get_caps	= mt753x_phylink_get_caps,
diff --git a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch
index da9fe699e3..afcfcaba34 100644
--- a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch
+++ b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch
@@ -19,7 +19,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3005,6 +3005,12 @@ static void mt753x_phylink_get_caps(stru
+@@ -3193,6 +3193,12 @@ static void mt753x_phylink_get_caps(stru
  	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  				   MAC_10 | MAC_100 | MAC_1000FD;
  
diff --git a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch
index eea598a7f4..bf2938d03b 100644
--- a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch
+++ b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch
@@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3143,9 +3143,16 @@ static int
+@@ -3331,9 +3331,16 @@ static int
  mt753x_setup(struct dsa_switch *ds)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (ret)
  		return ret;
  
-@@ -3157,13 +3164,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3345,13 +3352,6 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
diff --git a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
index c0dce51a2a..320b5c1ef9 100644
--- a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
+++ b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1589,11 +1589,11 @@ static void
+@@ -1771,11 +1771,11 @@ static void
  mt7530_hw_vlan_add(struct mt7530_priv *priv,
  		   struct mt7530_hw_vlan_entry *entry)
  {
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Validate the entry with independent learning, create egress tag per
  	 * VLAN and joining the port as one of the port members.
-@@ -1604,22 +1604,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
+@@ -1786,22 +1786,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
  
  	/* Decide whether adding tag or not for those outgoing packets from the
  	 * port inside the VLAN.
@@ -72,7 +72,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static void
-@@ -1638,11 +1636,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
+@@ -1820,11 +1818,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
  		return;
  	}
  
diff --git a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
index 7a4ee56cf9..eef19b4cb5 100644
--- a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
+++ b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch
@@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1093,6 +1093,7 @@ static int
+@@ -1275,6 +1275,7 @@ static int
  mt7530_port_enable(struct dsa_switch *ds, int port,
  		   struct phy_device *phy)
  {
@@ -29,7 +29,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct mt7530_priv *priv = ds->priv;
  
  	mutex_lock(&priv->reg_mutex);
-@@ -1101,7 +1102,11 @@ mt7530_port_enable(struct dsa_switch *ds
+@@ -1283,7 +1284,11 @@ mt7530_port_enable(struct dsa_switch *ds
  	 * restore the port matrix if the port is the member of a certain
  	 * bridge.
  	 */
@@ -42,7 +42,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	priv->ports[port].enable = true;
  	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
  		   priv->ports[port].pm);
-@@ -1249,7 +1254,8 @@ mt7530_port_bridge_join(struct dsa_switc
+@@ -1431,7 +1436,8 @@ mt7530_port_bridge_join(struct dsa_switc
  			struct net_device *bridge)
  {
  	struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
@@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct mt7530_priv *priv = ds->priv;
  
  	mutex_lock(&priv->reg_mutex);
-@@ -1326,9 +1332,12 @@ mt7530_port_set_vlan_unaware(struct dsa_
+@@ -1508,9 +1514,12 @@ mt7530_port_set_vlan_unaware(struct dsa_
  	 * the CPU port get out of VLAN filtering mode.
  	 */
  	if (all_user_ports_removed) {
@@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			     | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
  	}
  }
-@@ -1378,6 +1387,7 @@ mt7530_port_bridge_leave(struct dsa_swit
+@@ -1560,6 +1569,7 @@ mt7530_port_bridge_leave(struct dsa_swit
  			 struct net_device *bridge)
  {
  	struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
@@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct mt7530_priv *priv = ds->priv;
  
  	mutex_lock(&priv->reg_mutex);
-@@ -1406,8 +1416,8 @@ mt7530_port_bridge_leave(struct dsa_swit
+@@ -1588,8 +1598,8 @@ mt7530_port_bridge_leave(struct dsa_swit
  	 */
  	if (priv->ports[port].enable)
  		mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* When a port is removed from the bridge, the port would be set up
  	 * back to the default as is at initial boot which is a VLAN-unaware
-@@ -1570,6 +1580,9 @@ static int
+@@ -1752,6 +1762,9 @@ static int
  mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
  			   struct netlink_ext_ack *extack)
  {
@@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (vlan_filtering) {
  		/* The port is being kept as VLAN-unaware port when bridge is
  		 * set up with vlan_filtering not being set, Otherwise, the
-@@ -1577,7 +1590,7 @@ mt7530_port_vlan_filtering(struct dsa_sw
+@@ -1759,7 +1772,7 @@ mt7530_port_vlan_filtering(struct dsa_sw
  		 * for becoming a VLAN-aware port.
  		 */
  		mt7530_port_set_vlan_aware(ds, port);
diff --git a/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch b/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch
index e331226fc4..dbc28efc94 100644
--- a/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch
+++ b/target/linux/generic/backport-5.15/765-v5.17-04-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch
@@ -30,7 +30,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/dsa/dsa2.c
 +++ b/net/dsa/dsa2.c
-@@ -1034,6 +1034,8 @@ static int dsa_tree_setup_master(struct
+@@ -1056,6 +1056,8 @@ static int dsa_tree_setup_master(struct
  	struct dsa_port *dp;
  	int err;
  
@@ -39,7 +39,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	list_for_each_entry(dp, &dst->ports, list) {
  		if (dsa_port_is_cpu(dp)) {
  			err = dsa_master_setup(dp->master, dp);
-@@ -1042,6 +1044,8 @@ static int dsa_tree_setup_master(struct
+@@ -1064,6 +1066,8 @@ static int dsa_tree_setup_master(struct
  		}
  	}
  
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return 0;
  }
  
-@@ -1049,9 +1053,13 @@ static void dsa_tree_teardown_master(str
+@@ -1071,9 +1075,13 @@ static void dsa_tree_teardown_master(str
  {
  	struct dsa_port *dp;
  
diff --git a/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch b/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch
index e6472c61da..fbb9c94ec1 100644
--- a/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch
+++ b/target/linux/generic/backport-5.15/765-v5.17-05-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch
@@ -27,7 +27,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/dsa/dsa2.c
 +++ b/net/dsa/dsa2.c
-@@ -999,23 +999,28 @@ static void dsa_tree_teardown_switches(s
+@@ -1021,23 +1021,28 @@ static void dsa_tree_teardown_switches(s
  		dsa_switch_teardown(dp->ds);
  }
  
@@ -66,7 +66,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		}
  	}
  
-@@ -1024,7 +1029,21 @@ static int dsa_tree_setup_switches(struc
+@@ -1046,7 +1051,21 @@ static int dsa_tree_setup_switches(struc
  teardown:
  	dsa_tree_teardown_ports(dst);
  
@@ -89,7 +89,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return err;
  }
-@@ -1111,10 +1130,14 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1133,10 +1152,14 @@ static int dsa_tree_setup(struct dsa_swi
  	if (err)
  		goto teardown_cpu_ports;
  
@@ -105,7 +105,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	err = dsa_tree_setup_lags(dst);
  	if (err)
  		goto teardown_master;
-@@ -1127,8 +1150,9 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1149,8 +1172,9 @@ static int dsa_tree_setup(struct dsa_swi
  
  teardown_master:
  	dsa_tree_teardown_master(dst);
diff --git a/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch b/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch
index 93cad0c98a..a46e06ef8b 100644
--- a/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch
+++ b/target/linux/generic/backport-5.15/765-v5.17-06-net-next-net-dsa-setup-master-before-ports.patch
@@ -43,7 +43,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/dsa/dsa2.c
 +++ b/net/dsa/dsa2.c
-@@ -545,6 +545,7 @@ static void dsa_port_teardown(struct dsa
+@@ -567,6 +567,7 @@ static void dsa_port_teardown(struct dsa
  	struct devlink_port *dlp = &dp->devlink_port;
  	struct dsa_switch *ds = dp->ds;
  	struct dsa_mac_addr *a, *tmp;
@@ -51,7 +51,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	if (!dp->setup)
  		return;
-@@ -566,9 +567,11 @@ static void dsa_port_teardown(struct dsa
+@@ -588,9 +589,11 @@ static void dsa_port_teardown(struct dsa
  		dsa_port_link_unregister_of(dp);
  		break;
  	case DSA_PORT_TYPE_USER:
@@ -65,7 +65,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		}
  		break;
  	}
-@@ -1130,17 +1133,17 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1152,17 +1155,17 @@ static int dsa_tree_setup(struct dsa_swi
  	if (err)
  		goto teardown_cpu_ports;
  
@@ -87,7 +87,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	dst->setup = true;
  
-@@ -1148,10 +1151,10 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1170,10 +1173,10 @@ static int dsa_tree_setup(struct dsa_swi
  
  	return 0;
  
@@ -100,7 +100,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  teardown_switches:
  	dsa_tree_teardown_switches(dst);
  teardown_cpu_ports:
-@@ -1169,10 +1172,10 @@ static void dsa_tree_teardown(struct dsa
+@@ -1191,10 +1194,10 @@ static void dsa_tree_teardown(struct dsa
  
  	dsa_tree_teardown_lags(dst);
  
diff --git a/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch b/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch
index bffdcb2881..15122950ce 100644
--- a/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch
+++ b/target/linux/generic/backport-5.15/766-v5.18-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch
@@ -68,7 +68,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p)
  {
  	return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED;
-@@ -949,6 +959,13 @@ struct dsa_switch_ops {
+@@ -957,6 +967,13 @@ struct dsa_switch_ops {
  	int	(*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid,
  				      u16 flags);
  	int	(*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid);
@@ -84,7 +84,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes)		\
 --- a/net/dsa/dsa2.c
 +++ b/net/dsa/dsa2.c
-@@ -1275,6 +1275,52 @@ out_unlock:
+@@ -1297,6 +1297,52 @@ out_unlock:
  	return err;
  }
  
diff --git a/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch b/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch
index 6478d580c0..c55c5271d4 100644
--- a/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch
+++ b/target/linux/generic/backport-5.15/766-v5.18-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  #include "dsa_priv.h"
  
-@@ -1060,9 +1061,18 @@ static int dsa_tree_setup_master(struct
+@@ -1082,9 +1083,18 @@ static int dsa_tree_setup_master(struct
  
  	list_for_each_entry(dp, &dst->ports, list) {
  		if (dsa_port_is_cpu(dp)) {
@@ -64,7 +64,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		}
  	}
  
-@@ -1077,9 +1087,19 @@ static void dsa_tree_teardown_master(str
+@@ -1099,9 +1109,19 @@ static void dsa_tree_teardown_master(str
  
  	rtnl_lock();
  
diff --git a/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch
index 7b89dbc206..7f16b936cd 100644
--- a/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch
+++ b/target/linux/generic/backport-5.15/782-v6.1-net-dsa-mt7530-add-support-for-in-band-link-status.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2791,9 +2791,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2979,9 +2979,6 @@ mt7531_mac_config(struct dsa_switch *ds,
  	case PHY_INTERFACE_MODE_NA:
  	case PHY_INTERFACE_MODE_1000BASEX:
  	case PHY_INTERFACE_MODE_2500BASEX:
@@ -29,7 +29,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		return mt7531_sgmii_setup_mode_force(priv, port, interface);
  	default:
  		return -EINVAL;
-@@ -2869,13 +2866,6 @@ unsupported:
+@@ -3057,13 +3054,6 @@ unsupported:
  		return;
  	}
  
@@ -43,7 +43,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
  	mcr_new = mcr_cur;
  	mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -3012,6 +3002,9 @@ static void mt753x_phylink_get_caps(stru
+@@ -3200,6 +3190,9 @@ static void mt753x_phylink_get_caps(stru
  	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  				   MAC_10 | MAC_100 | MAC_1000FD;
  
@@ -53,7 +53,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* This driver does not make use of the speed, duplex, pause or the
  	 * advertisement in its mac_config, so it is safe to mark this driver
  	 * as non-legacy.
-@@ -3077,6 +3070,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3265,6 +3258,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
  
  	status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
  	state->link = !!(status & MT7531_SGMII_LINK_STATUS);
@@ -61,7 +61,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (state->interface == PHY_INTERFACE_MODE_SGMII &&
  	    (status & MT7531_SGMII_AN_ENABLE)) {
  		val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
-@@ -3107,16 +3101,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3295,16 +3289,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
  	return 0;
  }
  
@@ -109,7 +109,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -3157,6 +3179,8 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3345,6 +3367,8 @@ mt753x_setup(struct dsa_switch *ds)
  		priv->pcs[i].pcs.ops = priv->info->pcs_ops;
  		priv->pcs[i].priv = priv;
  		priv->pcs[i].port = i;
@@ -120,7 +120,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	ret = priv->info->sw_setup(ds);
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -400,6 +400,7 @@ enum mt7530_vlan_port_acc_frm {
+@@ -410,6 +410,7 @@ enum mt7530_vlan_port_acc_frm {
  #define  MT7531_SGMII_LINK_STATUS	BIT(18)
  #define  MT7531_SGMII_AN_ENABLE		BIT(12)
  #define  MT7531_SGMII_AN_RESTART	BIT(9)
diff --git a/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch b/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch
index b9d3018f11..8060ad5afc 100644
--- a/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch
+++ b/target/linux/generic/backport-5.15/788-v6.3-net-dsa-mt7530-use-external-PCS-driver.patch
@@ -81,7 +81,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  #include <linux/phylink.h>
  #include <linux/regmap.h>
  #include <linux/regulator/consumer.h>
-@@ -2643,128 +2644,11 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2831,128 +2832,11 @@ static int mt7531_rgmii_setup(struct mt7
  	return 0;
  }
  
@@ -210,7 +210,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  static int
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
-@@ -2787,11 +2671,11 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2975,11 +2859,11 @@ mt7531_mac_config(struct dsa_switch *ds,
  		phydev = dp->slave->phydev;
  		return mt7531_rgmii_setup(priv, port, interface, phydev);
  	case PHY_INTERFACE_MODE_SGMII:
@@ -224,7 +224,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	default:
  		return -EINVAL;
  	}
-@@ -2816,11 +2700,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
+@@ -3004,11 +2888,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
  
  	switch (interface) {
  	case PHY_INTERFACE_MODE_TRGMII:
@@ -238,7 +238,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	default:
  		return NULL;
  	}
-@@ -3061,86 +2945,6 @@ static void mt7530_pcs_get_state(struct
+@@ -3249,86 +3133,6 @@ static void mt7530_pcs_get_state(struct
  		state->pause |= MLO_PAUSE_TX;
  }
  
@@ -325,7 +325,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  			     phy_interface_t interface,
  			     const unsigned long *advertising,
-@@ -3160,18 +2964,57 @@ static const struct phylink_pcs_ops mt75
+@@ -3348,18 +3152,57 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -389,7 +389,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	int i, ret;
  
  	/* Initialise the PCS devices */
-@@ -3179,8 +3022,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3367,8 +3210,6 @@ mt753x_setup(struct dsa_switch *ds)
  		priv->pcs[i].pcs.ops = priv->info->pcs_ops;
  		priv->pcs[i].priv = priv;
  		priv->pcs[i].port = i;
@@ -398,7 +398,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	}
  
  	ret = priv->info->sw_setup(ds);
-@@ -3195,6 +3036,16 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3383,6 +3224,16 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -415,7 +415,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	return ret;
  }
  
-@@ -3286,7 +3137,7 @@ static const struct mt753x_info mt753x_t
+@@ -3475,7 +3326,7 @@ static const struct mt753x_info mt753x_t
  	},
  	[ID_MT7531] = {
  		.id = ID_MT7531,
@@ -424,7 +424,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  		.sw_setup = mt7531_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
-@@ -3394,7 +3245,7 @@ static void
+@@ -3583,7 +3434,7 @@ static void
  mt7530_remove(struct mdio_device *mdiodev)
  {
  	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
@@ -433,7 +433,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  
  	if (!priv)
  		return;
-@@ -3413,6 +3264,10 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3602,6 +3453,10 @@ mt7530_remove(struct mdio_device *mdiode
  		mt7530_free_irq(priv);
  
  	dsa_unregister_switch(priv->ds);
@@ -446,7 +446,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  	dev_set_drvdata(&mdiodev->dev, NULL);
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm {
  					 CCR_TX_OCT_CNT_BAD)
  
  /* MT7531 SGMII register group */
@@ -496,7 +496,7 @@ Tested-by: Frank Wunderlich <frank-w@public-files.de>
  
  /* Register for system reset */
  #define MT7530_SYS_CTRL			0x7000
-@@ -730,13 +691,13 @@ struct mt7530_fdb {
+@@ -741,13 +702,13 @@ struct mt7530_fdb {
   * @pm:		The matrix used to show all connections with the port.
   * @pvid:	The VLAN specified is to be considered a PVID at ingress.  Any
   *		untagged frames will be assigned to the related VLAN.
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
index 34db4fce0b..62d9c78cca 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2996,26 +2996,56 @@ static const struct regmap_bus mt7531_re
+@@ -3184,26 +3184,56 @@ static const struct regmap_bus mt7531_re
  	.reg_update_bits = mt7530_regmap_update_bits,
  };
  
@@ -88,7 +88,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	int i, ret;
  
  	/* Initialise the PCS devices */
-@@ -3037,15 +3067,11 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3225,15 +3255,11 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
index 04060b48ba..e9f69a8777 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2969,7 +2969,7 @@ static int mt7530_regmap_read(void *cont
+@@ -3157,7 +3157,7 @@ static int mt7530_regmap_read(void *cont
  {
  	struct mt7530_priv *priv = context;
  
@@ -28,7 +28,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return 0;
  };
  
-@@ -2977,23 +2977,25 @@ static int mt7530_regmap_write(void *con
+@@ -3165,23 +3165,25 @@ static int mt7530_regmap_write(void *con
  {
  	struct mt7530_priv *priv = context;
  
@@ -62,7 +62,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  static int
-@@ -3019,6 +3021,9 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3207,6 +3209,9 @@ mt7531_create_sgmii(struct mt7530_priv *
  		mt7531_pcs_config[i]->reg_stride = 4;
  		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
  		mt7531_pcs_config[i]->max_register = 0x17c;
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
index 48854fd234..a2dcc08b02 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
@@ -133,7 +133,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -2965,22 +2986,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3153,22 +3174,6 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -156,7 +156,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void
  mt7530_mdio_regmap_lock(void *mdio_lock)
  {
-@@ -2993,7 +2998,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
+@@ -3181,7 +3186,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
  	mutex_unlock(mdio_lock);
  }
  
@@ -165,7 +165,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.reg_write = mt7530_regmap_write,
  	.reg_read = mt7530_regmap_read,
  };
-@@ -3026,7 +3031,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3214,7 +3219,7 @@ mt7531_create_sgmii(struct mt7530_priv *
  		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
  
  		regmap = devm_regmap_init(priv->dev,
@@ -174,7 +174,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  					  mt7531_pcs_config[i]);
  		if (IS_ERR(regmap)) {
  			ret = PTR_ERR(regmap);
-@@ -3191,6 +3196,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
+@@ -3380,6 +3385,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
  static int
  mt7530_probe(struct mdio_device *mdiodev)
  {
@@ -182,7 +182,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	struct mt7530_priv *priv;
  	struct device_node *dn;
  
-@@ -3270,6 +3276,21 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3459,6 +3465,21 @@ mt7530_probe(struct mdio_device *mdiodev
  	mutex_init(&priv->reg_mutex);
  	dev_set_drvdata(&mdiodev->dev, priv);
  
@@ -206,7 +206,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -774,6 +774,7 @@ struct mt753x_info {
+@@ -785,6 +785,7 @@ struct mt753x_info {
   * @dev:		The device pointer
   * @ds:			The pointer to the dsa core structure
   * @bus:		The bus used for the device and built-in PHY
@@ -214,7 +214,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @rstc:		The pointer to reset control used by MCM
   * @core_pwr:		The power supplied into the core
   * @io_pwr:		The power supplied into the I/O
-@@ -794,6 +795,7 @@ struct mt7530_priv {
+@@ -805,6 +806,7 @@ struct mt7530_priv {
  	struct device		*dev;
  	struct dsa_switch	*ds;
  	struct mii_bus		*bus;
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
index b4bcdd0c9d..abbecd5e40 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3077,12 +3077,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3265,12 +3265,6 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -31,7 +31,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return ret;
  }
  
-@@ -3199,6 +3193,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3388,6 +3382,7 @@ mt7530_probe(struct mdio_device *mdiodev
  	static struct regmap_config *regmap_config;
  	struct mt7530_priv *priv;
  	struct device_node *dn;
@@ -39,7 +39,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	dn = mdiodev->dev.of_node;
  
-@@ -3291,6 +3286,12 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3480,6 +3475,12 @@ mt7530_probe(struct mdio_device *mdiodev
  	if (IS_ERR(priv->regmap))
  		return PTR_ERR(priv->regmap);
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch
index b9507e6d9b..ef02d46938 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch
@@ -114,7 +114,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -646,14 +650,13 @@ static int
+@@ -660,14 +664,13 @@ static int
  mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
  			int regnum)
  {
@@ -130,7 +130,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -686,7 +689,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
+@@ -700,7 +703,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
  
  	ret = val & MT7531_MDIO_RW_DATA_MASK;
  out:
@@ -139,7 +139,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -695,14 +698,13 @@ static int
+@@ -709,14 +712,13 @@ static int
  mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
  			 int regnum, u32 data)
  {
@@ -155,7 +155,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -734,7 +736,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
+@@ -748,7 +750,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
  	}
  
  out:
@@ -164,7 +164,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -742,14 +744,13 @@ out:
+@@ -756,14 +758,13 @@ out:
  static int
  mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
  {
@@ -180,7 +180,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -772,7 +773,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
+@@ -786,7 +787,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
  
  	ret = val & MT7531_MDIO_RW_DATA_MASK;
  out:
@@ -189,7 +189,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -781,14 +782,13 @@ static int
+@@ -795,14 +796,13 @@ static int
  mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
  			 u16 data)
  {
@@ -205,7 +205,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
  				 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -810,7 +810,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
+@@ -824,7 +824,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
  	}
  
  out:
@@ -214,7 +214,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -1162,7 +1162,6 @@ static int
+@@ -1344,7 +1344,6 @@ static int
  mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -222,7 +222,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	int length;
  	u32 val;
  
-@@ -1173,7 +1172,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1355,7 +1354,7 @@ mt7530_port_change_mtu(struct dsa_switch
  	if (!dsa_is_cpu_port(ds, port))
  		return 0;
  
@@ -231,7 +231,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	val = mt7530_mii_read(priv, MT7530_GMACCR);
  	val &= ~MAX_RX_PKT_LEN_MASK;
-@@ -1194,7 +1193,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1376,7 +1375,7 @@ mt7530_port_change_mtu(struct dsa_switch
  
  	mt7530_mii_write(priv, MT7530_GMACCR, val);
  
@@ -240,7 +240,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return 0;
  }
-@@ -1990,10 +1989,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
+@@ -2172,10 +2171,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
  	u32 val;
  	int p;
  
@@ -253,7 +253,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	for (p = 0; p < MT7530_NUM_PHYS; p++) {
  		if (BIT(p) & val) {
-@@ -2029,7 +2028,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
+@@ -2211,7 +2210,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
  {
  	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  
@@ -262,7 +262,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -2038,7 +2037,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
+@@ -2220,7 +2219,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
  	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  
  	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
index b04a84965b..2e1ed2e652 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
@@ -21,7 +21,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -951,6 +951,24 @@ mt7530_set_ageing_time(struct dsa_switch
+@@ -965,6 +965,24 @@ mt7530_set_ageing_time(struct dsa_switch
  	return 0;
  }
  
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	struct mt7530_priv *priv = ds->priv;
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -709,24 +709,6 @@ enum p5_interface_select {
+@@ -720,24 +720,6 @@ enum p5_interface_select {
  	P5_INTF_SEL_GMAC5_SGMII,
  };
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
index 3f656c7a67..c9ff26ff20 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3205,44 +3205,21 @@ static const struct of_device_id mt7530_
+@@ -3394,44 +3394,21 @@ static const struct of_device_id mt7530_
  MODULE_DEVICE_TABLE(of, mt7530_of_match);
  
  static int
@@ -67,7 +67,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (!priv->info)
  		return -EINVAL;
  
-@@ -3256,23 +3233,53 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3445,23 +3422,53 @@ mt7530_probe(struct mdio_device *mdiodev
  		return -EINVAL;
  
  	priv->id = priv->info->id;
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
  						      GPIOD_OUT_LOW);
  		if (IS_ERR(priv->reset)) {
-@@ -3281,12 +3288,15 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3470,12 +3477,15 @@ mt7530_probe(struct mdio_device *mdiodev
  		}
  	}
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
index efbabf668c..7c1c80e7bc 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3323,6 +3323,17 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3512,6 +3512,17 @@ mt7530_probe(struct mdio_device *mdiodev
  }
  
  static void
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_remove(struct mdio_device *mdiodev)
  {
  	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-@@ -3341,16 +3352,11 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3530,16 +3541,11 @@ mt7530_remove(struct mdio_device *mdiode
  		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
  			ret);
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
index ee944a6fc5..84883147ac 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
@@ -416,7 +416,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static u32
  mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
  {
-@@ -3003,72 +2954,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3191,72 +3142,6 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -489,7 +489,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int
  mt753x_setup(struct dsa_switch *ds)
  {
-@@ -3127,7 +3012,7 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3315,7 +3200,7 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -497,8 +497,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +const struct dsa_switch_ops mt7530_switch_ops = {
  	.get_tag_protocol	= mtk_get_tag_protocol,
  	.setup			= mt753x_setup,
- 	.get_strings		= mt7530_get_strings,
-@@ -3161,8 +3046,9 @@ static const struct dsa_switch_ops mt753
+ 	.preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
+@@ -3350,8 +3235,9 @@ static const struct dsa_switch_ops mt753
  	.get_mac_eee		= mt753x_get_mac_eee,
  	.set_mac_eee		= mt753x_set_mac_eee,
  };
@@ -509,7 +509,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	[ID_MT7621] = {
  		.id = ID_MT7621,
  		.pcs_ops = &mt7530_pcs_ops,
-@@ -3195,16 +3081,9 @@ static const struct mt753x_info mt753x_t
+@@ -3384,16 +3270,9 @@ static const struct mt753x_info mt753x_t
  		.mac_port_config = mt7531_mac_config,
  	},
  };
@@ -528,7 +528,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_probe_common(struct mt7530_priv *priv)
  {
  	struct device *dev = priv->dev;
-@@ -3241,88 +3120,9 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3430,88 +3309,9 @@ mt7530_probe_common(struct mt7530_priv *
  
  	return 0;
  }
@@ -619,7 +619,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_remove_common(struct mt7530_priv *priv)
  {
  	if (priv->irq)
-@@ -3333,57 +3133,6 @@ mt7530_remove_common(struct mt7530_priv
+@@ -3522,57 +3322,6 @@ mt7530_remove_common(struct mt7530_priv
  	mutex_destroy(&priv->reg_mutex);
  }
  
@@ -679,7 +679,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  MODULE_LICENSE("GPL");
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -834,4 +834,10 @@ static inline void INIT_MT7530_DUMMY_POL
+@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL
  	p->reg = reg;
  }
  
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
index e6c1b941dd..c8417091f9 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
@@ -184,7 +184,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +MODULE_LICENSE("GPL");
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2037,6 +2037,47 @@ static const struct irq_domain_ops mt753
+@@ -2219,6 +2219,47 @@ static const struct irq_domain_ops mt753
  };
  
  static void
@@ -232,7 +232,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_setup_mdio_irq(struct mt7530_priv *priv)
  {
  	struct dsa_switch *ds = priv->ds;
-@@ -2070,8 +2111,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2252,8 +2293,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
  		return priv->irq ? : -EINVAL;
  	}
  
@@ -250,7 +250,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (!priv->irq_domain) {
  		dev_err(dev, "failed to create IRQ domain\n");
  		return -ENOMEM;
-@@ -2566,6 +2614,25 @@ static void mt7531_mac_port_get_caps(str
+@@ -2754,6 +2802,25 @@ static void mt7531_mac_port_get_caps(str
  	}
  }
  
@@ -276,7 +276,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int
  mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
  {
-@@ -2642,6 +2709,17 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2830,6 +2897,17 @@ static bool mt753x_is_mac_port(u32 port)
  }
  
  static int
@@ -294,7 +294,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2711,7 +2789,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2899,7 +2977,8 @@ mt753x_phylink_mac_config(struct dsa_swi
  
  	switch (port) {
  	case 0 ... 4: /* Internal phy */
@@ -304,7 +304,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			goto unsupported;
  		break;
  	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
-@@ -2789,7 +2868,8 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2977,7 +3056,8 @@ static void mt753x_phylink_mac_link_up(s
  	/* MT753x MAC works in 1G full duplex mode for all up-clocked
  	 * variants.
  	 */
@@ -314,7 +314,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	    (phy_interface_mode_is_8023z(interface))) {
  		speed = SPEED_1000;
  		duplex = DUPLEX_FULL;
-@@ -2869,6 +2949,21 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3057,6 +3137,21 @@ mt7531_cpu_port_config(struct dsa_switch
  	return 0;
  }
  
@@ -336,7 +336,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
  				    struct phylink_config *config)
  {
-@@ -3014,6 +3109,27 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3202,6 +3297,27 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -364,7 +364,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  const struct dsa_switch_ops mt7530_switch_ops = {
  	.get_tag_protocol	= mtk_get_tag_protocol,
  	.setup			= mt753x_setup,
-@@ -3082,6 +3198,17 @@ const struct mt753x_info mt753x_table[]
+@@ -3271,6 +3387,17 @@ const struct mt753x_info mt753x_table[]
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
  	},
@@ -392,9 +392,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  #define	NUM_TRGMII_CTRL			5
-@@ -54,11 +55,11 @@ enum mt753x_id {
- #define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
+@@ -59,11 +60,11 @@ enum mt753x_id {
  #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
+ #define  MT7531_CPU_PMAP(x)		FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
  
 -#define MT753X_MIRROR_REG(id)		(((id) == ID_MT7531) ? \
 +#define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
@@ -407,7 +407,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  					 MT7531_MIRROR_MASK : MIRROR_MASK)
  
  /* Registers for BPDU and PAE frame control*/
-@@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm {
  					 MT7531_FORCE_DPX | \
  					 MT7531_FORCE_RX_FC | \
  					 MT7531_FORCE_TX_FC)
diff --git a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch
index 071680f100..2689647319 100644
--- a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch
+++ b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch
@@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3076,6 +3076,12 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3264,6 +3264,12 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -88,7 +88,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -768,10 +768,10 @@ struct mt753x_info {
+@@ -779,10 +779,10 @@ struct mt753x_info {
   *			registers
   * @p6_interface	Holding the current port 6 interface
   * @p5_intf_sel:	Holding the current port 5 interface select
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   */
  struct mt7530_priv {
  	struct device		*dev;
-@@ -790,7 +790,6 @@ struct mt7530_priv {
+@@ -801,7 +801,6 @@ struct mt7530_priv {
  	unsigned int		p5_intf_sel;
  	u8			mirror_rx;
  	u8			mirror_tx;
@@ -108,7 +108,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct mt7530_port	ports[MT7530_NUM_PORTS];
  	struct mt753x_pcs	pcs[MT7530_NUM_PORTS];
  	/* protect among processes for registers access*/
-@@ -798,6 +797,7 @@ struct mt7530_priv {
+@@ -809,6 +808,7 @@ struct mt7530_priv {
  	int irq;
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
diff --git a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
index 698e524c35..b2af169b92 100644
--- a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
+++ b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ax88179_reset(dev);
  
-@@ -1507,17 +1508,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1502,17 +1503,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
  {
  	u32 tx_hdr1, tx_hdr2;
  	int frame_size = dev->maxpacket;
@@ -57,7 +57,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if ((skb_header_cloned(skb) || headroom < 0) &&
  	    pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  		dev_kfree_skb_any(skb);
-@@ -1528,6 +1531,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1523,6 +1526,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
  	put_unaligned_le32(tx_hdr1, ptr);
  	put_unaligned_le32(tx_hdr2, ptr + 4);
  
diff --git a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch
index 725af4b52c..4a63b89f57 100644
--- a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch
+++ b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch
@@ -17,7 +17,7 @@ Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 
 --- a/drivers/bluetooth/btusb.c
 +++ b/drivers/bluetooth/btusb.c
-@@ -2287,6 +2287,23 @@ struct btmtk_section_map {
+@@ -2289,6 +2289,23 @@ struct btmtk_section_map {
  	};
  } __packed;
  
@@ -41,7 +41,7 @@ Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
  static void btusb_mtk_wmt_recv(struct urb *urb)
  {
  	struct hci_dev *hdev = urb->context;
-@@ -3941,6 +3958,7 @@ static int btusb_probe(struct usb_interf
+@@ -3943,6 +3960,7 @@ static int btusb_probe(struct usb_interf
  		hdev->shutdown = btusb_mtk_shutdown;
  		hdev->manufacturer = 70;
  		hdev->cmd_timeout = btusb_mtk_cmd_timeout;
diff --git a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch
index d72866eabf..d21adada97 100644
--- a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch
+++ b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch
@@ -18,7 +18,7 @@ Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 
 --- a/drivers/bluetooth/btusb.c
 +++ b/drivers/bluetooth/btusb.c
-@@ -2292,7 +2292,7 @@ static int btusb_set_bdaddr_mtk(struct h
+@@ -2294,7 +2294,7 @@ static int btusb_set_bdaddr_mtk(struct h
  	struct sk_buff *skb;
  	long ret;
  
diff --git a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch
index ebb6cc4717..30492ac48d 100644
--- a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch
+++ b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch
@@ -58,7 +58,7 @@ Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 
 --- a/drivers/bluetooth/btusb.c
 +++ b/drivers/bluetooth/btusb.c
-@@ -476,6 +476,9 @@ static const struct usb_device_id blackl
+@@ -478,6 +478,9 @@ static const struct usb_device_id blackl
  	{ USB_DEVICE(0x13d3, 0x3564), .driver_info = BTUSB_MEDIATEK |
  						     BTUSB_WIDEBAND_SPEECH |
  						     BTUSB_VALID_LE_STATES },
diff --git a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch
index a8c7ca003a..6bcd81c3b8 100644
--- a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch
+++ b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch
@@ -56,7 +56,7 @@ Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
 
 --- a/drivers/bluetooth/btusb.c
 +++ b/drivers/bluetooth/btusb.c
-@@ -467,6 +467,9 @@ static const struct usb_device_id blackl
+@@ -469,6 +469,9 @@ static const struct usb_device_id blackl
  						     BTUSB_VALID_LE_STATES },
  
  	/* Additional MediaTek MT7921 Bluetooth devices */
diff --git a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch
index b46e6926d1..b6b76f64fc 100644
--- a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch
+++ b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch
@@ -54,7 +54,7 @@ Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
 
 --- a/drivers/bluetooth/btusb.c
 +++ b/drivers/bluetooth/btusb.c
-@@ -485,6 +485,9 @@ static const struct usb_device_id blackl
+@@ -487,6 +487,9 @@ static const struct usb_device_id blackl
  	{ USB_DEVICE(0x0489, 0xe0cd), .driver_info = BTUSB_MEDIATEK |
  						     BTUSB_WIDEBAND_SPEECH |
  						     BTUSB_VALID_LE_STATES },
diff --git a/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch b/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch
new file mode 100644
index 0000000000..239adff1af
--- /dev/null
+++ b/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch
@@ -0,0 +1,161 @@
+From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001
+From: Tanzir Hasan <tanzirh@google.com>
+Date: Tue, 26 Dec 2023 18:00:00 +0000
+Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h
+
+This patch creates wordpart.h and includes it in asm/word-at-a-time.h
+for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h
+because of REPEAT_BYTE. Moving this to another header and including it
+where necessary allows us to not include the bloated kernel.h. Making
+this implicit dependency on REPEAT_BYTE explicit allows for later
+improvements in the lib/string.c inclusion list.
+
+Suggested-by: Al Viro <viro@zeniv.linux.org.uk>
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Tanzir Hasan <tanzirh@google.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ arch/arm/include/asm/word-at-a-time.h     |  3 ++-
+ arch/arm64/include/asm/word-at-a-time.h   |  3 ++-
+ arch/powerpc/include/asm/word-at-a-time.h |  4 ++--
+ arch/riscv/include/asm/word-at-a-time.h   |  3 ++-
+ arch/s390/include/asm/word-at-a-time.h    |  3 ++-
+ arch/sh/include/asm/word-at-a-time.h      |  2 ++
+ arch/x86/include/asm/word-at-a-time.h     |  3 ++-
+ arch/x86/kvm/mmu/mmu.c                    |  1 +
+ fs/namei.c                                |  2 +-
+ include/asm-generic/word-at-a-time.h      |  3 ++-
+ include/linux/kernel.h                    |  8 --------
+ include/linux/wordpart.h                  | 13 +++++++++++++
+ 12 files changed, 31 insertions(+), 17 deletions(-)
+ create mode 100644 include/linux/wordpart.h
+
+--- a/arch/arm/include/asm/word-at-a-time.h
++++ b/arch/arm/include/asm/word-at-a-time.h
+@@ -8,7 +8,8 @@
+  * Little-endian word-at-a-time zero byte handling.
+  * Heavily based on the x86 algorithm.
+  */
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ struct word_at_a_time {
+ 	const unsigned long one_bits, high_bits;
+--- a/arch/arm64/include/asm/word-at-a-time.h
++++ b/arch/arm64/include/asm/word-at-a-time.h
+@@ -9,7 +9,8 @@
+ 
+ #ifndef __AARCH64EB__
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ struct word_at_a_time {
+ 	const unsigned long one_bits, high_bits;
+--- a/arch/powerpc/include/asm/word-at-a-time.h
++++ b/arch/powerpc/include/asm/word-at-a-time.h
+@@ -4,8 +4,8 @@
+ /*
+  * Word-at-a-time interfaces for PowerPC.
+  */
+-
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/asm-compat.h>
+ #include <asm/extable.h>
+ 
+--- a/arch/sh/include/asm/word-at-a-time.h
++++ b/arch/sh/include/asm/word-at-a-time.h
+@@ -5,6 +5,8 @@
+ #ifdef CONFIG_CPU_BIG_ENDIAN
+ # include <asm-generic/word-at-a-time.h>
+ #else
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ /*
+  * Little-endian version cribbed from x86.
+  */
+--- a/arch/x86/include/asm/word-at-a-time.h
++++ b/arch/x86/include/asm/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ /*
+  * This is largely generic for little-endian machines, but the
+--- a/arch/x86/kvm/mmu/mmu.c
++++ b/arch/x86/kvm/mmu/mmu.c
+@@ -44,6 +44,7 @@
+ #include <linux/kern_levels.h>
+ #include <linux/kstrtox.h>
+ #include <linux/kthread.h>
++#include <linux/wordpart.h>
+ 
+ #include <asm/page.h>
+ #include <asm/memtype.h>
+--- a/fs/namei.c
++++ b/fs/namei.c
+@@ -17,8 +17,8 @@
+ 
+ #include <linux/init.h>
+ #include <linux/export.h>
+-#include <linux/kernel.h>
+ #include <linux/slab.h>
++#include <linux/wordpart.h>
+ #include <linux/fs.h>
+ #include <linux/namei.h>
+ #include <linux/pagemap.h>
+--- a/include/asm-generic/word-at-a-time.h
++++ b/include/asm-generic/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/byteorder.h>
+ 
+ #ifdef __BIG_ENDIAN
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -36,14 +36,6 @@
+ 
+ #define STACK_MAGIC	0xdeadbeef
+ 
+-/**
+- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+- * @x: value to repeat
+- *
+- * NOTE: @x is not checked for > 0xff; larger values produce odd results.
+- */
+-#define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
+-
+ /* generic data direction definitions */
+ #define READ			0
+ #define WRITE			1
+--- /dev/null
++++ b/include/linux/wordpart.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _LINUX_WORDPART_H
++#define _LINUX_WORDPART_H
++/**
++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
++ * @x: value to repeat
++ *
++ * NOTE: @x is not checked for > 0xff; larger values produce odd results.
++ */
++#define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
++
++#endif // _LINUX_WORDPART_H
diff --git a/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch b/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch
new file mode 100644
index 0000000000..9bbd515852
--- /dev/null
+++ b/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch
@@ -0,0 +1,107 @@
+From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 14 Feb 2024 19:26:32 +0200
+Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to
+ wordpart.h
+
+The wordpart.h header is collecting APIs related to the handling
+parts of the word (usually in byte granularity). The upper_*_bits()
+and lower_*_bits() are good candidates to be moved to there.
+
+This helps to clean up header dependency hell with regard to kernel.h
+as the latter gathers completely unrelated stuff together and slows
+down compilation (especially when it's included into other header).
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com
+Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ include/linux/kernel.h   | 30 ++----------------------------
+ include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+), 28 deletions(-)
+
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -30,6 +30,8 @@
+ #include <linux/build_bug.h>
+ #include <linux/static_call_types.h>
+ #include <linux/instruction_pointer.h>
++#include <linux/wordpart.h>
++
+ #include <asm/byteorder.h>
+ 
+ #include <uapi/linux/kernel.h>
+@@ -55,34 +57,6 @@
+ }					\
+ )
+ 
+-/**
+- * upper_32_bits - return bits 32-63 of a number
+- * @n: the number we're accessing
+- *
+- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+- * the "right shift count >= width of type" warning when that quantity is
+- * 32-bits.
+- */
+-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+-
+-/**
+- * lower_32_bits - return bits 0-31 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
+-
+-/**
+- * upper_16_bits - return bits 16-31 of a number
+- * @n: the number we're accessing
+- */
+-#define upper_16_bits(n) ((u16)((n) >> 16))
+-
+-/**
+- * lower_16_bits - return bits 0-15 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_16_bits(n) ((u16)((n) & 0xffff))
+-
+ struct completion;
+ struct user;
+ 
+--- a/include/linux/wordpart.h
++++ b/include/linux/wordpart.h
+@@ -2,6 +2,35 @@
+ 
+ #ifndef _LINUX_WORDPART_H
+ #define _LINUX_WORDPART_H
++
++/**
++ * upper_32_bits - return bits 32-63 of a number
++ * @n: the number we're accessing
++ *
++ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
++ * the "right shift count >= width of type" warning when that quantity is
++ * 32-bits.
++ */
++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
++
++/**
++ * lower_32_bits - return bits 0-31 of a number
++ * @n: the number we're accessing
++ */
++#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
++
++/**
++ * upper_16_bits - return bits 16-31 of a number
++ * @n: the number we're accessing
++ */
++#define upper_16_bits(n) ((u16)((n) >> 16))
++
++/**
++ * lower_16_bits - return bits 0-15 of a number
++ * @n: the number we're accessing
++ */
++#define lower_16_bits(n) ((u16)((n) & 0xffff))
++
+ /**
+  * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+  * @x: value to repeat
diff --git a/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch b/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch
new file mode 100644
index 0000000000..6dbec3c752
--- /dev/null
+++ b/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch
@@ -0,0 +1,107 @@
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Wed, 3 Jan 2024 15:44:21 +0100
+Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation
+
+The existing code always pulls the IPv6 header and sets the transport
+offset initially. Then optionally again pulls any extension headers in
+ipv6_gso_pull_exthdrs and sets the transport offset again on return from
+that call. skb->data is set at the start of the first extension header
+before calling ipv6_gso_pull_exthdrs, and must disable the frag0
+optimization because that function uses pskb_may_pull/pskb_pull instead of
+skb_gro_ helpers. It sets the GRO offset to the TCP header with
+skb_gro_pull and sets the transport header. Then returns skb->data to its
+position before this block.
+
+This commit introduces a new helper function - ipv6_gro_pull_exthdrs -
+which is used in ipv6_gro_receive to pull ipv6 ext headers instead of
+ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all
+operations use skb_gro_* helpers, and the frag0 fast path can be taken for
+IPv6 packets with ext headers.
+
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Reviewed-by: David Ahern <dsahern@kernel.org>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -36,6 +36,40 @@
+ 		INDIRECT_CALL_L4(cb, f2, f1, head, skb);	\
+ })
+ 
++static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto)
++{
++	const struct net_offload *ops = NULL;
++	struct ipv6_opt_hdr *opth;
++
++	for (;;) {
++		int len;
++
++		ops = rcu_dereference(inet6_offloads[proto]);
++
++		if (unlikely(!ops))
++			break;
++
++		if (!(ops->flags & INET6_PROTO_GSO_EXTHDR))
++			break;
++
++		opth = skb_gro_header(skb, off + sizeof(*opth), off);
++		if (unlikely(!opth))
++			break;
++
++		len = ipv6_optlen(opth);
++
++		opth = skb_gro_header(skb, off + len, off);
++		if (unlikely(!opth))
++			break;
++		proto = opth->nexthdr;
++
++		off += len;
++	}
++
++	skb_gro_pull(skb, off - skb_network_offset(skb));
++	return proto;
++}
++
+ static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto)
+ {
+ 	const struct net_offload *ops = NULL;
+@@ -224,28 +258,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ 		goto out;
+ 
+ 	skb_set_network_header(skb, off);
+-	skb_gro_pull(skb, sizeof(*iph));
+-	skb_set_transport_header(skb, skb_gro_offset(skb));
+ 
+-	flush += ntohs(iph->payload_len) != skb_gro_len(skb);
++	flush += ntohs(iph->payload_len) != skb->len - hlen;
+ 
+ 	proto = iph->nexthdr;
+ 	ops = rcu_dereference(inet6_offloads[proto]);
+ 	if (!ops || !ops->callbacks.gro_receive) {
+-		pskb_pull(skb, skb_gro_offset(skb));
+-		skb_gro_frag0_invalidate(skb);
+-		proto = ipv6_gso_pull_exthdrs(skb, proto);
+-		skb_gro_pull(skb, -skb_transport_offset(skb));
+-		skb_reset_transport_header(skb);
+-		__skb_push(skb, skb_gro_offset(skb));
++		proto = ipv6_gro_pull_exthdrs(skb, hlen, proto);
+ 
+ 		ops = rcu_dereference(inet6_offloads[proto]);
+ 		if (!ops || !ops->callbacks.gro_receive)
+ 			goto out;
+ 
+-		iph = ipv6_hdr(skb);
++		iph = skb_gro_network_header(skb);
++	} else {
++		skb_gro_pull(skb, sizeof(*iph));
+ 	}
+ 
++	skb_set_transport_header(skb, skb_gro_offset(skb));
++
+ 	NAPI_GRO_CB(skb)->proto = proto;
+ 
+ 	flush--;
diff --git a/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch b/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch
index 51250ac97a..0119925ab0 100644
--- a/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch
+++ b/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch
@@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		}
 --- a/net/dsa/dsa2.c
 +++ b/net/dsa/dsa2.c
-@@ -1736,6 +1736,15 @@ static int dsa_switch_probe(struct dsa_s
+@@ -1758,6 +1758,15 @@ static int dsa_switch_probe(struct dsa_s
  	if (!ds->num_ports)
  		return -EINVAL;
  
diff --git a/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch b/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch
index f662a76368..e0319fd355 100644
--- a/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch
+++ b/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3010,9 +3010,6 @@ static void mt753x_phylink_get_caps(stru
+@@ -3198,9 +3198,6 @@ static void mt753x_phylink_get_caps(stru
  	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  				   MAC_10 | MAC_100 | MAC_1000FD;
  
diff --git a/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch b/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch
index 36ff3549e9..2697f2e563 100644
--- a/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch
+++ b/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  #include <linux/phylink.h>
  #include <linux/regmap.h>
  #include <linux/regulator/consumer.h>
-@@ -2651,128 +2652,11 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2839,128 +2840,11 @@ static int mt7531_rgmii_setup(struct mt7
  	return 0;
  }
  
@@ -173,7 +173,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
-@@ -2795,11 +2679,11 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2983,11 +2867,11 @@ mt7531_mac_config(struct dsa_switch *ds,
  		phydev = dp->slave->phydev;
  		return mt7531_rgmii_setup(priv, port, interface, phydev);
  	case PHY_INTERFACE_MODE_SGMII:
@@ -187,7 +187,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		return -EINVAL;
  	}
-@@ -2824,11 +2708,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
+@@ -3012,11 +2896,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
  
  	switch (interface) {
  	case PHY_INTERFACE_MODE_TRGMII:
@@ -201,7 +201,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		return NULL;
  	}
-@@ -3066,86 +2950,6 @@ static void mt7530_pcs_get_state(struct
+@@ -3254,86 +3138,6 @@ static void mt7530_pcs_get_state(struct
  		state->pause |= MLO_PAUSE_TX;
  }
  
@@ -288,7 +288,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  			     phy_interface_t interface,
  			     const unsigned long *advertising,
-@@ -3165,18 +2969,57 @@ static const struct phylink_pcs_ops mt75
+@@ -3353,18 +3157,57 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -352,7 +352,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i, ret;
  
  	/* Initialise the PCS devices */
-@@ -3184,8 +3027,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3372,8 +3215,6 @@ mt753x_setup(struct dsa_switch *ds)
  		priv->pcs[i].pcs.ops = priv->info->pcs_ops;
  		priv->pcs[i].priv = priv;
  		priv->pcs[i].port = i;
@@ -361,7 +361,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	ret = priv->info->sw_setup(ds);
-@@ -3200,6 +3041,16 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3388,6 +3229,16 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -378,7 +378,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return ret;
  }
  
-@@ -3291,7 +3142,7 @@ static const struct mt753x_info mt753x_t
+@@ -3480,7 +3331,7 @@ static const struct mt753x_info mt753x_t
  	},
  	[ID_MT7531] = {
  		.id = ID_MT7531,
@@ -387,7 +387,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.sw_setup = mt7531_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
-@@ -3399,7 +3250,7 @@ static void
+@@ -3588,7 +3439,7 @@ static void
  mt7530_remove(struct mdio_device *mdiodev)
  {
  	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
@@ -396,7 +396,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (!priv)
  		return;
-@@ -3418,6 +3269,10 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3607,6 +3458,10 @@ mt7530_remove(struct mdio_device *mdiode
  		mt7530_free_irq(priv);
  
  	dsa_unregister_switch(priv->ds);
@@ -409,7 +409,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm {
  					 CCR_TX_OCT_CNT_BAD)
  
  /* MT7531 SGMII register group */
@@ -459,7 +459,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  /* Register for system reset */
  #define MT7530_SYS_CTRL			0x7000
-@@ -730,13 +691,13 @@ struct mt7530_fdb {
+@@ -741,13 +702,13 @@ struct mt7530_fdb {
   * @pm:		The matrix used to show all connections with the port.
   * @pvid:	The VLAN specified is to be considered a PVID at ingress.  Any
   *		untagged frames will be assigned to the related VLAN.
diff --git a/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
index ed24c452e2..1bf19a813e 100644
--- a/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
+++ b/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3001,26 +3001,56 @@ static const struct regmap_bus mt7531_re
+@@ -3189,26 +3189,56 @@ static const struct regmap_bus mt7531_re
  	.reg_update_bits = mt7530_regmap_update_bits,
  };
  
@@ -88,7 +88,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	int i, ret;
  
  	/* Initialise the PCS devices */
-@@ -3042,15 +3072,11 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3230,15 +3260,11 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
diff --git a/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
index 0298ebd274..bd28b4be76 100644
--- a/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
+++ b/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2974,7 +2974,7 @@ static int mt7530_regmap_read(void *cont
+@@ -3162,7 +3162,7 @@ static int mt7530_regmap_read(void *cont
  {
  	struct mt7530_priv *priv = context;
  
@@ -28,7 +28,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return 0;
  };
  
-@@ -2982,23 +2982,25 @@ static int mt7530_regmap_write(void *con
+@@ -3170,23 +3170,25 @@ static int mt7530_regmap_write(void *con
  {
  	struct mt7530_priv *priv = context;
  
@@ -62,7 +62,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  static int
-@@ -3024,6 +3026,9 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3212,6 +3214,9 @@ mt7531_create_sgmii(struct mt7530_priv *
  		mt7531_pcs_config[i]->reg_stride = 4;
  		mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
  		mt7531_pcs_config[i]->max_register = 0x17c;
diff --git a/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
index e5625f67de..42c225d91c 100644
--- a/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
+++ b/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch
@@ -133,7 +133,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -2970,22 +2991,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3158,22 +3179,6 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -156,7 +156,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void
  mt7530_mdio_regmap_lock(void *mdio_lock)
  {
-@@ -2998,7 +3003,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
+@@ -3186,7 +3191,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
  	mutex_unlock(mdio_lock);
  }
  
@@ -165,7 +165,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.reg_write = mt7530_regmap_write,
  	.reg_read = mt7530_regmap_read,
  };
-@@ -3031,7 +3036,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3219,7 +3224,7 @@ mt7531_create_sgmii(struct mt7530_priv *
  		mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
  
  		regmap = devm_regmap_init(priv->dev,
@@ -174,7 +174,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  					  mt7531_pcs_config[i]);
  		if (IS_ERR(regmap)) {
  			ret = PTR_ERR(regmap);
-@@ -3196,6 +3201,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
+@@ -3385,6 +3390,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
  static int
  mt7530_probe(struct mdio_device *mdiodev)
  {
@@ -182,7 +182,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	struct mt7530_priv *priv;
  	struct device_node *dn;
  
-@@ -3275,6 +3281,21 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3464,6 +3470,21 @@ mt7530_probe(struct mdio_device *mdiodev
  	mutex_init(&priv->reg_mutex);
  	dev_set_drvdata(&mdiodev->dev, priv);
  
@@ -206,7 +206,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -774,6 +774,7 @@ struct mt753x_info {
+@@ -785,6 +785,7 @@ struct mt753x_info {
   * @dev:		The device pointer
   * @ds:			The pointer to the dsa core structure
   * @bus:		The bus used for the device and built-in PHY
@@ -214,7 +214,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @rstc:		The pointer to reset control used by MCM
   * @core_pwr:		The power supplied into the core
   * @io_pwr:		The power supplied into the I/O
-@@ -794,6 +795,7 @@ struct mt7530_priv {
+@@ -805,6 +806,7 @@ struct mt7530_priv {
  	struct device		*dev;
  	struct dsa_switch	*ds;
  	struct mii_bus		*bus;
diff --git a/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
index ca1f38f9c2..9cd817c056 100644
--- a/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
+++ b/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3082,12 +3082,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3270,12 +3270,6 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -31,7 +31,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	return ret;
  }
  
-@@ -3204,6 +3198,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3393,6 +3387,7 @@ mt7530_probe(struct mdio_device *mdiodev
  	static struct regmap_config *regmap_config;
  	struct mt7530_priv *priv;
  	struct device_node *dn;
@@ -39,7 +39,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	dn = mdiodev->dev.of_node;
  
-@@ -3296,6 +3291,12 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3485,6 +3480,12 @@ mt7530_probe(struct mdio_device *mdiodev
  	if (IS_ERR(priv->regmap))
  		return PTR_ERR(priv->regmap);
  
diff --git a/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch
index 813e976810..4f77078eef 100644
--- a/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch
+++ b/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch
@@ -114,7 +114,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -645,14 +649,13 @@ static int
+@@ -659,14 +663,13 @@ static int
  mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
  			int regnum)
  {
@@ -130,7 +130,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -685,7 +688,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
+@@ -699,7 +702,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
  
  	ret = val & MT7531_MDIO_RW_DATA_MASK;
  out:
@@ -139,7 +139,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -694,14 +697,13 @@ static int
+@@ -708,14 +711,13 @@ static int
  mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
  			 int regnum, u32 data)
  {
@@ -155,7 +155,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -733,7 +735,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
+@@ -747,7 +749,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
  	}
  
  out:
@@ -164,7 +164,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -741,14 +743,13 @@ out:
+@@ -755,14 +757,13 @@ out:
  static int
  mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
  {
@@ -180,7 +180,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
  				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -771,7 +772,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
+@@ -785,7 +786,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
  
  	ret = val & MT7531_MDIO_RW_DATA_MASK;
  out:
@@ -189,7 +189,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -780,14 +781,13 @@ static int
+@@ -794,14 +795,13 @@ static int
  mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
  			 u16 data)
  {
@@ -205,7 +205,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
  				 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -809,7 +809,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
+@@ -823,7 +823,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
  	}
  
  out:
@@ -214,7 +214,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return ret;
  }
-@@ -1161,7 +1161,6 @@ static int
+@@ -1343,7 +1343,6 @@ static int
  mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -222,7 +222,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	int length;
  	u32 val;
  
-@@ -1172,7 +1171,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1354,7 +1353,7 @@ mt7530_port_change_mtu(struct dsa_switch
  	if (!dsa_is_cpu_port(ds, port))
  		return 0;
  
@@ -231,7 +231,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	val = mt7530_mii_read(priv, MT7530_GMACCR);
  	val &= ~MAX_RX_PKT_LEN_MASK;
-@@ -1193,7 +1192,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1375,7 +1374,7 @@ mt7530_port_change_mtu(struct dsa_switch
  
  	mt7530_mii_write(priv, MT7530_GMACCR, val);
  
@@ -240,7 +240,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return 0;
  }
-@@ -1994,10 +1993,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
+@@ -2176,10 +2175,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
  	u32 val;
  	int p;
  
@@ -253,7 +253,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	for (p = 0; p < MT7530_NUM_PHYS; p++) {
  		if (BIT(p) & val) {
-@@ -2033,7 +2032,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
+@@ -2215,7 +2214,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
  {
  	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  
@@ -262,7 +262,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -2042,7 +2041,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
+@@ -2224,7 +2223,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
  	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  
  	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
diff --git a/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
index 177f6af780..9cb0b2dd61 100644
--- a/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
+++ b/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch
@@ -21,7 +21,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -950,6 +950,24 @@ mt7530_set_ageing_time(struct dsa_switch
+@@ -964,6 +964,24 @@ mt7530_set_ageing_time(struct dsa_switch
  	return 0;
  }
  
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	struct mt7530_priv *priv = ds->priv;
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -709,24 +709,6 @@ enum p5_interface_select {
+@@ -720,24 +720,6 @@ enum p5_interface_select {
  	P5_INTF_SEL_GMAC5_SGMII,
  };
  
diff --git a/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
index 8950caaaef..a6af682826 100644
--- a/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
+++ b/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3210,44 +3210,21 @@ static const struct of_device_id mt7530_
+@@ -3399,44 +3399,21 @@ static const struct of_device_id mt7530_
  MODULE_DEVICE_TABLE(of, mt7530_of_match);
  
  static int
@@ -67,7 +67,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (!priv->info)
  		return -EINVAL;
  
-@@ -3261,23 +3238,53 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3450,23 +3427,53 @@ mt7530_probe(struct mdio_device *mdiodev
  		return -EINVAL;
  
  	priv->id = priv->info->id;
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
  						      GPIOD_OUT_LOW);
  		if (IS_ERR(priv->reset)) {
-@@ -3286,12 +3293,15 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3475,12 +3482,15 @@ mt7530_probe(struct mdio_device *mdiodev
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
index 24eadb589e..4192753e89 100644
--- a/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
+++ b/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3328,6 +3328,17 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3517,6 +3517,17 @@ mt7530_probe(struct mdio_device *mdiodev
  }
  
  static void
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_remove(struct mdio_device *mdiodev)
  {
  	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-@@ -3346,15 +3357,10 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3535,15 +3546,10 @@ mt7530_remove(struct mdio_device *mdiode
  		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
  			ret);
  
diff --git a/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
index a6bb7d9e7b..72a499381f 100644
--- a/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
+++ b/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
@@ -420,7 +420,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static u32
  mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
  {
-@@ -3008,72 +2959,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3196,72 +3147,6 @@ static const struct phylink_pcs_ops mt75
  	.pcs_an_restart = mt7530_pcs_an_restart,
  };
  
@@ -493,7 +493,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int
  mt753x_setup(struct dsa_switch *ds)
  {
-@@ -3132,7 +3017,7 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3320,7 +3205,7 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -501,8 +501,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +const struct dsa_switch_ops mt7530_switch_ops = {
  	.get_tag_protocol	= mtk_get_tag_protocol,
  	.setup			= mt753x_setup,
- 	.get_strings		= mt7530_get_strings,
-@@ -3166,8 +3051,9 @@ static const struct dsa_switch_ops mt753
+ 	.preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
+@@ -3355,8 +3240,9 @@ static const struct dsa_switch_ops mt753
  	.get_mac_eee		= mt753x_get_mac_eee,
  	.set_mac_eee		= mt753x_set_mac_eee,
  };
@@ -513,7 +513,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	[ID_MT7621] = {
  		.id = ID_MT7621,
  		.pcs_ops = &mt7530_pcs_ops,
-@@ -3200,16 +3086,9 @@ static const struct mt753x_info mt753x_t
+@@ -3389,16 +3275,9 @@ static const struct mt753x_info mt753x_t
  		.mac_port_config = mt7531_mac_config,
  	},
  };
@@ -532,7 +532,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_probe_common(struct mt7530_priv *priv)
  {
  	struct device *dev = priv->dev;
-@@ -3246,88 +3125,9 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3435,88 +3314,9 @@ mt7530_probe_common(struct mt7530_priv *
  
  	return 0;
  }
@@ -623,7 +623,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_remove_common(struct mt7530_priv *priv)
  {
  	if (priv->irq)
-@@ -3337,55 +3137,7 @@ mt7530_remove_common(struct mt7530_priv
+@@ -3526,55 +3326,7 @@ mt7530_remove_common(struct mt7530_priv
  
  	mutex_destroy(&priv->reg_mutex);
  }
@@ -682,7 +682,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -834,4 +834,10 @@ static inline void INIT_MT7530_DUMMY_POL
+@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL
  	p->reg = reg;
  }
  
diff --git a/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
index 9bc3f54c23..f5573fc6c4 100644
--- a/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
+++ b/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
@@ -184,7 +184,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +MODULE_LICENSE("GPL");
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2041,6 +2041,47 @@ static const struct irq_domain_ops mt753
+@@ -2223,6 +2223,47 @@ static const struct irq_domain_ops mt753
  };
  
  static void
@@ -232,7 +232,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7530_setup_mdio_irq(struct mt7530_priv *priv)
  {
  	struct dsa_switch *ds = priv->ds;
-@@ -2074,8 +2115,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2256,8 +2297,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
  		return priv->irq ? : -EINVAL;
  	}
  
@@ -250,7 +250,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (!priv->irq_domain) {
  		dev_err(dev, "failed to create IRQ domain\n");
  		return -ENOMEM;
-@@ -2574,6 +2622,25 @@ static void mt7531_mac_port_get_caps(str
+@@ -2762,6 +2810,25 @@ static void mt7531_mac_port_get_caps(str
  	}
  }
  
@@ -276,7 +276,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int
  mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
  {
-@@ -2650,6 +2717,17 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2838,6 +2905,17 @@ static bool mt753x_is_mac_port(u32 port)
  }
  
  static int
@@ -294,7 +294,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2719,7 +2797,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2907,7 +2985,8 @@ mt753x_phylink_mac_config(struct dsa_swi
  
  	switch (port) {
  	case 0 ... 4: /* Internal phy */
@@ -304,7 +304,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			goto unsupported;
  		break;
  	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
-@@ -2797,7 +2876,8 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2985,7 +3064,8 @@ static void mt753x_phylink_mac_link_up(s
  	/* MT753x MAC works in 1G full duplex mode for all up-clocked
  	 * variants.
  	 */
@@ -314,7 +314,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	    (phy_interface_mode_is_8023z(interface))) {
  		speed = SPEED_1000;
  		duplex = DUPLEX_FULL;
-@@ -2877,6 +2957,21 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3065,6 +3145,21 @@ mt7531_cpu_port_config(struct dsa_switch
  	return 0;
  }
  
@@ -336,7 +336,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
  				    struct phylink_config *config)
  {
-@@ -3019,6 +3114,27 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3207,6 +3302,27 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -364,7 +364,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  const struct dsa_switch_ops mt7530_switch_ops = {
  	.get_tag_protocol	= mtk_get_tag_protocol,
  	.setup			= mt753x_setup,
-@@ -3087,6 +3203,17 @@ const struct mt753x_info mt753x_table[]
+@@ -3276,6 +3392,17 @@ const struct mt753x_info mt753x_table[]
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
  	},
@@ -392,9 +392,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  #define	NUM_TRGMII_CTRL			5
-@@ -54,11 +55,11 @@ enum mt753x_id {
- #define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
+@@ -59,11 +60,11 @@ enum mt753x_id {
  #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
+ #define  MT7531_CPU_PMAP(x)		FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
  
 -#define MT753X_MIRROR_REG(id)		(((id) == ID_MT7531) ? \
 +#define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
@@ -407,7 +407,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  					 MT7531_MIRROR_MASK : MIRROR_MASK)
  
  /* Registers for BPDU and PAE frame control*/
-@@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm {
  					 MT7531_FORCE_DPX | \
  					 MT7531_FORCE_RX_FC | \
  					 MT7531_FORCE_TX_FC)
diff --git a/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch
index ef2d07ab79..40209b0305 100644
--- a/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch
+++ b/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch
@@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3081,6 +3081,12 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3269,6 +3269,12 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
@@ -88,7 +88,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -768,10 +768,10 @@ struct mt753x_info {
+@@ -779,10 +779,10 @@ struct mt753x_info {
   *			registers
   * @p6_interface	Holding the current port 6 interface
   * @p5_intf_sel:	Holding the current port 5 interface select
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   */
  struct mt7530_priv {
  	struct device		*dev;
-@@ -790,7 +790,6 @@ struct mt7530_priv {
+@@ -801,7 +801,6 @@ struct mt7530_priv {
  	unsigned int		p5_intf_sel;
  	u8			mirror_rx;
  	u8			mirror_tx;
@@ -108,7 +108,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct mt7530_port	ports[MT7530_NUM_PORTS];
  	struct mt753x_pcs	pcs[MT7530_NUM_PORTS];
  	/* protect among processes for registers access*/
-@@ -798,6 +797,7 @@ struct mt7530_priv {
+@@ -809,6 +808,7 @@ struct mt7530_priv {
  	int irq;
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
diff --git a/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch b/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch
deleted file mode 100644
index 068fb38a4e..0000000000
--- a/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 4b11e3eb0eb7245a0d22a5dc4161c54eea42910c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 17 Jun 2023 09:26:44 +0300
-Subject: [PATCH 16/48] net: dsa: mt7530: set all CPU ports in MT7531_CPU_PMAP
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-MT7531_CPU_PMAP represents the destination port mask for trapped-to-CPU
-frames (further restricted by PCR_MATRIX).
-
-Currently the driver sets the first CPU port as the single port in this bit
-mask, which works fine regardless of whether the device tree defines port
-5, 6 or 5+6 as CPU ports. This is because the logic coincides with DSA's
-logic of picking the first CPU port as the CPU port that all user ports are
-affine to, by default.
-
-An upcoming change would like to influence DSA's selection of the default
-CPU port to no longer be the first one, and in that case, this logic needs
-adaptation.
-
-Since there is no observed leakage or duplication of frames if all CPU
-ports are defined in this bit mask, simply include them all.
-
-Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
-Suggested-by: Vladimir Oltean <olteanv@gmail.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
-Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 15 +++++++--------
- drivers/net/dsa/mt7530.h |  1 +
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1069,6 +1069,13 @@ mt753x_cpu_port_enable(struct dsa_switch
- 	if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
- 		mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
- 
-+	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
-+	 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
-+	 * is affine to the inbound user port.
-+	 */
-+	if (priv->id == ID_MT7531 || priv->id == ID_MT7988)
-+		mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
-+
- 	/* CPU port gets connected to all user ports of
- 	 * the switch.
- 	 */
-@@ -2411,16 +2418,8 @@ static int
- mt7531_setup_common(struct dsa_switch *ds)
- {
- 	struct mt7530_priv *priv = ds->priv;
--	struct dsa_port *cpu_dp;
- 	int ret, i;
- 
--	/* BPDU to CPU port */
--	dsa_switch_for_each_cpu_port(cpu_dp, ds) {
--		mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
--			   BIT(cpu_dp->index));
--		break;
--	}
--
- 	mt753x_trap_frames(priv);
- 
- 	/* Enable and reset MIB counters */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -54,6 +54,7 @@ enum mt753x_id {
- #define  MT7531_MIRROR_PORT_GET(x)	(((x) >> 16) & MIRROR_MASK)
- #define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
- #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
-+#define  MT7531_CPU_PMAP(x)		FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
- 
- #define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
- 					 MT7531_CFC : MT7530_MFC)
diff --git a/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch b/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch
index bbf6d9b16f..78e332b1c2 100644
--- a/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch
+++ b/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3036,7 +3036,7 @@ static void mt7530_pcs_get_state(struct
+@@ -3225,7 +3225,7 @@ static void mt7530_pcs_get_state(struct
  		state->pause |= MLO_PAUSE_TX;
  }
  
@@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			     phy_interface_t interface,
  			     const unsigned long *advertising,
  			     bool permit_pause_to_mac)
-@@ -3064,6 +3064,7 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3253,6 +3253,7 @@ mt753x_setup(struct dsa_switch *ds)
  	/* Initialise the PCS devices */
  	for (i = 0; i < priv->ds->num_ports; i++) {
  		priv->pcs[i].pcs.ops = priv->info->pcs_ops;
diff --git a/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch b/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
index e9a36eea41..d69ee7f104 100644
--- a/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
+++ b/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
@@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2851,15 +2851,6 @@ static void mt753x_phylink_mac_link_down
+@@ -3040,15 +3040,6 @@ static void mt753x_phylink_mac_link_down
  	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
  }
  
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
  				       unsigned int mode,
  				       phy_interface_t interface,
-@@ -2948,8 +2939,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3137,8 +3128,6 @@ mt7531_cpu_port_config(struct dsa_switch
  		return ret;
  	mt7530_write(priv, MT7530_PMCR_P(port),
  		     PMCR_CPU_PORT_SETTING(priv->id));
diff --git a/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch b/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch
index e8fec3f6a1..8af6820270 100644
--- a/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch
+++ b/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch
@@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -829,8 +829,7 @@ mt7530_get_strings(struct dsa_switch *ds
+@@ -843,8 +843,7 @@ mt7530_get_strings(struct dsa_switch *ds
  		return;
  
  	for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
diff --git a/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch b/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
index 8b374679ca..4c6c057739 100644
--- a/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
+++ b/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
@@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2175,24 +2175,40 @@ mt7530_free_irq_common(struct mt7530_pri
+@@ -2350,24 +2350,40 @@ mt7530_free_irq_common(struct mt7530_pri
  static void
  mt7530_free_irq(struct mt7530_priv *priv)
  {
@@ -92,7 +92,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	bus->priv = priv;
  	bus->name = KBUILD_MODNAME "-mii";
  	snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
-@@ -2201,16 +2217,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2376,16 +2392,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  	bus->parent = dev;
  	bus->phy_mask = ~ds->phys_mii_mask;
  
diff --git a/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
index 381902472c..0b141b4a3f 100644
--- a/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
+++ b/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2883,8 +2883,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -3072,8 +3072,7 @@ static void mt753x_phylink_mac_link_up(s
  	/* MT753x MAC works in 1G full duplex mode for all up-clocked
  	 * variants.
  	 */
diff --git a/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch b/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
index c3f55f8106..44d8e07c12 100644
--- a/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
+++ b/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1064,10 +1064,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+@@ -1239,10 +1239,6 @@ mt753x_cpu_port_enable(struct dsa_switch
  	mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
  		   UNU_FFP(BIT(port)));
  
@@ -46,10 +46,10 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 -	if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
 -		mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
 -
- 	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
- 	 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
- 	 * is affine to the inbound user port.
-@@ -3125,6 +3121,36 @@ static int mt753x_set_mac_eee(struct dsa
+ 	/* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames
+ 	 * will be forwarded to the CPU port that is affine to the inbound user
+ 	 * port.
+@@ -3314,6 +3310,36 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  {
  	return 0;
-@@ -3179,6 +3205,7 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3369,6 +3395,7 @@ const struct dsa_switch_ops mt7530_switc
  	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
  	.get_mac_eee		= mt753x_get_mac_eee,
  	.set_mac_eee		= mt753x_set_mac_eee,
@@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -41,8 +41,8 @@ enum mt753x_id {
+@@ -45,8 +45,8 @@ enum mt753x_id {
  #define  UNU_FFP(x)			(((x) & 0xff) << 8)
  #define  UNU_FFP_MASK			UNU_FFP(~0)
  #define  CPU_EN				BIT(7)
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  #define  MIRROR_EN			BIT(3)
  #define  MIRROR_PORT(x)			((x) & 0x7)
  #define  MIRROR_MASK			0x7
-@@ -773,6 +773,7 @@ struct mt753x_info {
+@@ -783,6 +783,7 @@ struct mt753x_info {
   * @irq_domain:		IRQ domain of the switch irq_chip
   * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
   * @create_sgmii:	Pointer to function creating SGMII PCS instance(s)
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   */
  struct mt7530_priv {
  	struct device		*dev;
-@@ -799,6 +800,7 @@ struct mt7530_priv {
+@@ -809,6 +810,7 @@ struct mt7530_priv {
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
  	int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
diff --git a/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch b/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
index 35abed6b03..3454948b86 100644
--- a/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
+++ b/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
@@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -703,7 +703,7 @@ struct mt7530_port {
+@@ -713,7 +713,7 @@ struct mt7530_port {
  
  /* Port 5 interface select definitions */
  enum p5_interface_select {
@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	P5_INTF_SEL_PHY_P0,
  	P5_INTF_SEL_PHY_P4,
  	P5_INTF_SEL_GMAC5,
-@@ -789,7 +789,7 @@ struct mt7530_priv {
+@@ -799,7 +799,7 @@ struct mt7530_priv {
  	bool			mcm;
  	phy_interface_t		p6_interface;
  	phy_interface_t		p5_interface;
diff --git a/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch b/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
index 03329f8ba8..357579e2bd 100644
--- a/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
+++ b/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
@@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  						    GFP_KERNEL);
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -473,15 +473,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+@@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
  	return 0;
  }
  
@@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int
  mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  {
-@@ -496,9 +487,6 @@ mt7531_pll_setup(struct mt7530_priv *pri
+@@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *pri
  	u32 xtal;
  	u32 val;
  
@@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	val = mt7530_read(priv, MT7531_CREV);
  	top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
  	hwstrap = mt7530_read(priv, MT7531_HWTRAP);
-@@ -913,8 +901,6 @@ static const char *p5_intf_modes(unsigne
+@@ -927,8 +915,6 @@ static const char *p5_intf_modes(unsigne
  		return "PHY P4";
  	case P5_INTF_SEL_GMAC5:
  		return "GMAC5";
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		return "unknown";
  	}
-@@ -2515,6 +2501,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2697,6 +2683,12 @@ mt7531_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
@@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	/* all MACs must be forced link-down before sw reset */
  	for (i = 0; i < MT7530_NUM_PORTS; i++)
  		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-@@ -2524,21 +2516,18 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2706,21 +2698,18 @@ mt7531_setup(struct dsa_switch *ds)
  		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
  		     SYS_CTRL_REG_RST);
  
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
  		   MT7531_GPIO0_INTERRUPT);
-@@ -2598,11 +2587,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2787,11 +2776,6 @@ static void mt7530_mac_port_get_caps(str
  	}
  }
  
@@ -153,7 +153,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
  				     struct phylink_config *config)
  {
-@@ -2615,7 +2599,7 @@ static void mt7531_mac_port_get_caps(str
+@@ -2804,7 +2788,7 @@ static void mt7531_mac_port_get_caps(str
  		break;
  
  	case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
@@ -162,7 +162,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			phy_interface_set_rgmii(config->supported_interfaces);
  			break;
  		}
-@@ -2682,7 +2666,7 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2871,7 +2855,7 @@ static int mt7531_rgmii_setup(struct mt7
  {
  	u32 val;
  
@@ -171,7 +171,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev_err(priv->dev, "RGMII mode is not available for port %d\n",
  			port);
  		return -EINVAL;
-@@ -2925,7 +2909,7 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3114,7 +3098,7 @@ mt7531_cpu_port_config(struct dsa_switch
  
  	switch (port) {
  	case 5:
@@ -180,7 +180,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			interface = PHY_INTERFACE_MODE_RGMII;
  		else
  			interface = PHY_INTERFACE_MODE_2500BASEX;
-@@ -3083,7 +3067,7 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3272,7 +3256,7 @@ mt753x_setup(struct dsa_switch *ds)
  		mt7530_free_irq_common(priv);
  
  	if (priv->create_sgmii) {
@@ -191,7 +191,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -707,7 +707,6 @@ enum p5_interface_select {
+@@ -717,7 +717,6 @@ enum p5_interface_select {
  	P5_INTF_SEL_PHY_P0,
  	P5_INTF_SEL_PHY_P4,
  	P5_INTF_SEL_GMAC5,
@@ -199,7 +199,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  };
  
  struct mt7530_priv;
-@@ -769,6 +768,8 @@ struct mt753x_info {
+@@ -779,6 +778,8 @@ struct mt753x_info {
   *			registers
   * @p6_interface	Holding the current port 6 interface
   * @p5_intf_sel:	Holding the current port 5 interface select
@@ -208,7 +208,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @irq:		IRQ number of the switch
   * @irq_domain:		IRQ domain of the switch irq_chip
   * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
-@@ -790,6 +791,7 @@ struct mt7530_priv {
+@@ -800,6 +801,7 @@ struct mt7530_priv {
  	phy_interface_t		p6_interface;
  	phy_interface_t		p5_interface;
  	enum p5_interface_select p5_intf_sel;
@@ -216,7 +216,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u8			mirror_rx;
  	u8			mirror_tx;
  	struct mt7530_port	ports[MT7530_NUM_PORTS];
-@@ -799,7 +801,7 @@ struct mt7530_priv {
+@@ -809,7 +811,7 @@ struct mt7530_priv {
  	int irq;
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
diff --git a/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch b/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
index 1489c4f2f3..46dbd53ede 100644
--- a/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
+++ b/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
@@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2565,12 +2565,14 @@ static void mt7530_mac_port_get_caps(str
+@@ -2754,12 +2754,14 @@ static void mt7530_mac_port_get_caps(str
  				     struct phylink_config *config)
  {
  	switch (port) {
@@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		phy_interface_set_rgmii(config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_MII,
  			  config->supported_interfaces);
-@@ -2578,7 +2580,8 @@ static void mt7530_mac_port_get_caps(str
+@@ -2767,7 +2769,8 @@ static void mt7530_mac_port_get_caps(str
  			  config->supported_interfaces);
  		break;
  
@@ -64,7 +64,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_RGMII,
  			  config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -2593,19 +2596,24 @@ static void mt7531_mac_port_get_caps(str
+@@ -2782,19 +2785,24 @@ static void mt7531_mac_port_get_caps(str
  	struct mt7530_priv *priv = ds->priv;
  
  	switch (port) {
@@ -92,7 +92,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_SGMII,
  			  config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_1000BASEX,
-@@ -2624,11 +2632,13 @@ static void mt7988_mac_port_get_caps(str
+@@ -2813,11 +2821,13 @@ static void mt7988_mac_port_get_caps(str
  	phy_interface_zero(config->supported_interfaces);
  
  	switch (port) {
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	case 6:
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  config->supported_interfaces);
-@@ -2792,12 +2802,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2981,12 +2991,12 @@ mt753x_phylink_mac_config(struct dsa_swi
  	u32 mcr_cur, mcr_new;
  
  	switch (port) {
@@ -122,7 +122,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (priv->p5_interface == state->interface)
  			break;
  
-@@ -2807,7 +2817,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2996,7 +3006,7 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p5_intf_sel != P5_DISABLED)
  			priv->p5_interface = state->interface;
  		break;
diff --git a/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch b/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
index 6fbf259735..43f629b243 100644
--- a/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
+++ b/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
@@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2353,16 +2353,15 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2532,16 +2532,15 @@ mt7530_setup(struct dsa_switch *ds)
  		return ret;
  
  	/* Setup port 5 */
@@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for_each_child_of_node(dn, mac_np) {
  			if (!of_device_is_compatible(mac_np,
  						     "mediatek,eth-mac"))
-@@ -2393,6 +2392,8 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2572,6 +2571,8 @@ mt7530_setup(struct dsa_switch *ds)
  			of_node_put(phy_node);
  			break;
  		}
@@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  #ifdef CONFIG_GPIOLIB
-@@ -2403,8 +2404,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2582,8 +2583,6 @@ mt7530_setup(struct dsa_switch *ds)
  	}
  #endif /* CONFIG_GPIOLIB */
  
diff --git a/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch b/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch
index 94692d948f..385d587729 100644
--- a/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch
+++ b/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch
@@ -31,7 +31,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -971,8 +971,6 @@ static void mt7530_setup_port5(struct ds
+@@ -985,8 +985,6 @@ static void mt7530_setup_port5(struct ds
  	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
  		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
  
diff --git a/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch b/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
index c121eb4a35..b4c0b75c49 100644
--- a/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
+++ b/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -935,9 +935,6 @@ static void mt7530_setup_port5(struct ds
+@@ -949,9 +949,6 @@ static void mt7530_setup_port5(struct ds
  		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
  		val &= ~MHWTRAP_P5_DIS;
  		break;
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
  			priv->p5_intf_sel);
-@@ -2358,8 +2355,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2537,8 +2534,6 @@ mt7530_setup(struct dsa_switch *ds)
  		 * Set priv->p5_intf_sel to the appropriate value if PHY muxing
  		 * is detected.
  		 */
@@ -49,7 +49,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for_each_child_of_node(dn, mac_np) {
  			if (!of_device_is_compatible(mac_np,
  						     "mediatek,eth-mac"))
-@@ -2391,7 +2386,9 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2570,7 +2565,9 @@ mt7530_setup(struct dsa_switch *ds)
  			break;
  		}
  
diff --git a/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch b/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch
index 9b610e0bdb..89527e2b39 100644
--- a/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch
+++ b/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch
@@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -936,9 +936,7 @@ static void mt7530_setup_port5(struct ds
+@@ -950,9 +950,7 @@ static void mt7530_setup_port5(struct ds
  		val &= ~MHWTRAP_P5_DIS;
  		break;
  	default:
@@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	/* Setup RGMII settings */
-@@ -968,7 +966,6 @@ static void mt7530_setup_port5(struct ds
+@@ -982,7 +980,6 @@ static void mt7530_setup_port5(struct ds
  	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
  		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
  
diff --git a/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch b/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
index dba1cb734e..0dc4baf0c7 100644
--- a/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
+++ b/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
@@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -408,13 +408,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+@@ -422,13 +422,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
  
  	xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	switch (interface) {
  	case PHY_INTERFACE_MODE_RGMII:
  		trgint = 0;
-@@ -2286,6 +2279,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2461,6 +2454,12 @@ mt7530_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
diff --git a/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch b/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch
index 90f8e095ef..46e1b50f24 100644
--- a/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch
+++ b/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -404,65 +404,54 @@ static int
+@@ -418,65 +418,54 @@ static int
  mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
  {
  	struct mt7530_priv *priv = ds->priv;
diff --git a/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch b/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
index 93eccc8637..7d78b7df70 100644
--- a/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
+++ b/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
@@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -400,8 +400,8 @@ static void mt7530_pll_setup(struct mt75
+@@ -414,8 +414,8 @@ mt753x_preferred_default_local_cpu_port(
  }
  
  /* Setup port 6 interface mode and TRGMII TX circuit */
@@ -58,7 +58,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	struct mt7530_priv *priv = ds->priv;
  	u32 ncpo1, ssc_delta, xtal;
-@@ -412,7 +412,7 @@ mt7530_pad_clk_setup(struct dsa_switch *
+@@ -426,7 +426,7 @@ mt7530_pad_clk_setup(struct dsa_switch *
  	if (interface == PHY_INTERFACE_MODE_RGMII) {
  		mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
  			   P6_INTF_MODE(0));
@@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
-@@ -451,7 +451,11 @@ mt7530_pad_clk_setup(struct dsa_switch *
+@@ -465,7 +465,11 @@ mt7530_pad_clk_setup(struct dsa_switch *
  
  	/* Enable the MT7530 TRGMII clocks */
  	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
@@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return 0;
  }
  
-@@ -2640,11 +2644,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2829,11 +2833,10 @@ mt7530_mac_config(struct dsa_switch *ds,
  {
  	struct mt7530_priv *priv = ds->priv;
  
diff --git a/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch b/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
index a423c0899c..725830e769 100644
--- a/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
+++ b/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
@@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -453,18 +453,6 @@ mt7530_setup_port6(struct dsa_switch *ds
+@@ -467,18 +467,6 @@ mt7530_setup_port6(struct dsa_switch *ds
  	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
  }
  
@@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void
  mt7531_pll_setup(struct mt7530_priv *priv)
  {
-@@ -2631,14 +2619,6 @@ static void mt7988_mac_port_get_caps(str
+@@ -2820,14 +2808,6 @@ static void mt7988_mac_port_get_caps(str
  }
  
  static int
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2803,8 +2783,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2992,8 +2972,6 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p6_interface == state->interface)
  			break;
  
@@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (mt753x_mac_config(ds, port, mode, state) < 0)
  			goto unsupported;
  
-@@ -3127,11 +3105,6 @@ mt753x_conduit_state_change(struct dsa_s
+@@ -3316,11 +3294,6 @@ mt753x_conduit_state_change(struct dsa_s
  	mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
  }
  
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mt7988_setup(struct dsa_switch *ds)
  {
  	struct mt7530_priv *priv = ds->priv;
-@@ -3192,7 +3165,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3382,7 +3355,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7530_setup,
  		.phy_read = mt7530_phy_read,
  		.phy_write = mt7530_phy_write,
@@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3202,7 +3174,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3392,7 +3364,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7530_setup,
  		.phy_read = mt7530_phy_read,
  		.phy_write = mt7530_phy_write,
@@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3212,7 +3183,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3402,7 +3373,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7531_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.cpu_port_config = mt7531_cpu_port_config,
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
-@@ -3223,7 +3193,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3413,7 +3383,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7988_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.cpu_port_config = mt7988_cpu_port_config,
  		.mac_port_get_caps = mt7988_mac_port_get_caps,
  		.mac_port_config = mt7988_mac_config,
-@@ -3253,9 +3222,8 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3443,9 +3412,8 @@ mt7530_probe_common(struct mt7530_priv *
  	/* Sanity check if these required device operations are filled
  	 * properly.
  	 */
@@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -722,8 +722,6 @@ struct mt753x_pcs {
+@@ -732,8 +732,6 @@ struct mt753x_pcs {
   * @sw_setup:		Holding the handler to a device initialization
   * @phy_read:		Holding the way reading PHY port
   * @phy_write:		Holding the way writing PHY port
@@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @phy_mode_supported:	Check if the PHY type is being supported on a certain
   *			port
   * @mac_port_validate:	Holding the way to set addition validate type for a
-@@ -739,7 +737,6 @@ struct mt753x_info {
+@@ -749,7 +747,6 @@ struct mt753x_info {
  	int (*sw_setup)(struct dsa_switch *ds);
  	int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
  	int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
diff --git a/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
index 3667dbf54a..606c48234c 100644
--- a/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
+++ b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
@@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2604,7 +2604,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2793,7 +2793,7 @@ static void mt7988_mac_port_get_caps(str
  
  	switch (port) {
  	/* Ports which are connected to switch PHYs. There is no MII pinout. */
diff --git a/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch b/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
index 48433705f6..e2f1f23435 100644
--- a/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
+++ b/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2600,8 +2600,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2789,8 +2789,6 @@ static void mt7531_mac_port_get_caps(str
  static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
  				     struct phylink_config *config)
  {
diff --git a/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch b/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
index b707de87ed..be6fe39f38 100644
--- a/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
+++ b/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2683,17 +2683,6 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2872,17 +2872,6 @@ static bool mt753x_is_mac_port(u32 port)
  }
  
  static int
@@ -51,7 +51,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2733,6 +2722,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2922,6 +2911,9 @@ mt753x_mac_config(struct dsa_switch *ds,
  {
  	struct mt7530_priv *priv = ds->priv;
  
@@ -61,7 +61,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return priv->info->mac_port_config(ds, port, mode, state->interface);
  }
  
-@@ -3193,7 +3185,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3383,7 +3375,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write = mt7531_ind_phy_write,
  		.cpu_port_config = mt7988_cpu_port_config,
  		.mac_port_get_caps = mt7988_mac_port_get_caps,
@@ -69,7 +69,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	},
  };
  EXPORT_SYMBOL_GPL(mt753x_table);
-@@ -3221,8 +3212,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3411,8 +3402,7 @@ mt7530_probe_common(struct mt7530_priv *
  	 * properly.
  	 */
  	if (!priv->info->sw_setup || !priv->info->phy_read ||
diff --git a/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch b/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
index 5dfb8bddbb..b8473ed128 100644
--- a/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
+++ b/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2084,7 +2084,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2259,7 +2259,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
  	}
  
  	/* This register must be set for MT7530 to properly fire interrupts */
diff --git a/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch b/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
index 565f16a47f..216a781087 100644
--- a/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
+++ b/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
@@ -22,7 +22,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2478,14 +2478,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2660,14 +2660,12 @@ mt7531_setup(struct dsa_switch *ds)
  	val = mt7530_read(priv, MT7531_TOP_SIG_SR);
  	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
  
diff --git a/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch b/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
index d636e2d564..f920a6604d 100644
--- a/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
+++ b/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
@@ -36,7 +36,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2614,7 +2614,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2803,7 +2803,7 @@ static void mt7988_mac_port_get_caps(str
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2624,22 +2624,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2813,22 +2813,14 @@ mt7530_mac_config(struct dsa_switch *ds,
  		mt7530_setup_port5(priv->ds, interface);
  	else if (port == 6)
  		mt7530_setup_port6(priv->ds, interface);
@@ -71,7 +71,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
  	val |= GP_CLK_EN;
  	val &= ~GP_MODE_MASK;
-@@ -2667,20 +2659,14 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2856,20 +2848,14 @@ static int mt7531_rgmii_setup(struct mt7
  		case PHY_INTERFACE_MODE_RGMII_ID:
  			break;
  		default:
@@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2688,42 +2674,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2877,42 +2863,21 @@ mt7531_mac_config(struct dsa_switch *ds,
  	struct phy_device *phydev;
  	struct dsa_port *dp;
  
@@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static struct phylink_pcs *
-@@ -2752,17 +2717,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2941,17 +2906,11 @@ mt753x_phylink_mac_config(struct dsa_swi
  	u32 mcr_cur, mcr_new;
  
  	switch (port) {
@@ -162,7 +162,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  		if (priv->p5_intf_sel != P5_DISABLED)
  			priv->p5_interface = state->interface;
-@@ -2771,16 +2730,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2960,16 +2919,10 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p6_interface == state->interface)
  			break;
  
@@ -180,7 +180,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
-@@ -2863,7 +2816,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3052,7 +3005,6 @@ mt7531_cpu_port_config(struct dsa_switch
  	struct mt7530_priv *priv = ds->priv;
  	phy_interface_t interface;
  	int speed;
@@ -188,7 +188,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	switch (port) {
  	case 5:
-@@ -2888,9 +2840,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3077,9 +3029,8 @@ mt7531_cpu_port_config(struct dsa_switch
  	else
  		speed = SPEED_1000;
  
@@ -202,7 +202,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -743,9 +743,9 @@ struct mt753x_info {
+@@ -753,9 +753,9 @@ struct mt753x_info {
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
  				  phy_interface_t interface,
  				  unsigned long *supported);
diff --git a/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch b/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
index 60b369c8f8..eb0a5706ec 100644
--- a/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
+++ b/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
@@ -57,8 +57,8 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -995,18 +995,10 @@ mt753x_trap_frames(struct mt7530_priv *p
- 		   MT753X_BPDU_CPU_ONLY);
+@@ -1170,18 +1170,10 @@ mt753x_trap_frames(struct mt7530_priv *p
+ 			   MT753X_BPDU_CPU_ONLY);
  }
  
 -static int
@@ -77,7 +77,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* Enable Mediatek header mode on the cpu port */
  	mt7530_write(priv, MT7530_PVC_P(port),
-@@ -1032,8 +1024,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+@@ -1207,8 +1199,6 @@ mt753x_cpu_port_enable(struct dsa_switch
  	/* Set to fallback mode for independent VLAN learning */
  	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
  		   MT7530_PORT_FALLBACK_MODE);
@@ -86,16 +86,16 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static int
-@@ -2288,8 +2278,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2461,8 +2451,6 @@ mt7530_setup(struct dsa_switch *ds)
  	val |= MHWTRAP_MANUAL;
  	mt7530_write(priv, MT7530_MHWTRAP, val);
  
 -	priv->p6_interface = PHY_INTERFACE_MODE_NA;
 -
- 	mt753x_trap_frames(priv);
+ 	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ 		mt7530_pll_setup(priv);
  
- 	/* Enable and reset MIB counters */
-@@ -2304,9 +2292,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2480,9 +2468,7 @@ mt7530_setup(struct dsa_switch *ds)
  		mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  
  		if (dsa_is_cpu_port(ds, i)) {
@@ -106,7 +106,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		} else {
  			mt7530_port_disable(ds, i);
  
-@@ -2410,9 +2396,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2589,9 +2575,7 @@ mt7531_setup_common(struct dsa_switch *d
  		mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
  
  		if (dsa_is_cpu_port(ds, i)) {
@@ -117,7 +117,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		} else {
  			mt7530_port_disable(ds, i);
  
-@@ -2501,10 +2485,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2683,10 +2667,6 @@ mt7531_setup(struct dsa_switch *ds)
  	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
  		   MT7531_GPIO0_INTERRUPT);
  
@@ -125,10 +125,10 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 -	priv->p5_interface = PHY_INTERFACE_MODE_NA;
 -	priv->p6_interface = PHY_INTERFACE_MODE_NA;
 -
- 	/* Enable PHY core PLL, since phy_device has not yet been created
- 	 * provided for phy_[read,write]_mmd_indirect is called, we provide
- 	 * our own mt7531_ind_mmd_phy_[read,write] to complete this
-@@ -2716,26 +2696,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ 	/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ 	 * phy_device has not yet been created provided for
+ 	 * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2905,26 +2885,9 @@ mt753x_phylink_mac_config(struct dsa_swi
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr_cur, mcr_new;
  
@@ -156,7 +156,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
  	mcr_new = mcr_cur;
  	mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -2771,17 +2734,10 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2960,17 +2923,10 @@ static void mt753x_phylink_mac_link_up(s
  
  	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
  
@@ -176,7 +176,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		mcr |= PMCR_FORCE_SPEED_1000;
  		break;
  	case SPEED_100:
-@@ -2799,6 +2755,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2988,6 +2944,7 @@ static void mt753x_phylink_mac_link_up(s
  	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
  		switch (speed) {
  		case SPEED_1000:
@@ -184,7 +184,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  			mcr |= PMCR_FORCE_EEE1G;
  			break;
  		case SPEED_100:
-@@ -2810,61 +2767,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2999,61 +2956,6 @@ static void mt753x_phylink_mac_link_up(s
  	mt7530_set(priv, MT7530_PMCR_P(port), mcr);
  }
  
@@ -246,7 +246,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
  				    struct phylink_config *config)
  {
-@@ -3122,7 +3024,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3312,7 +3214,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7531_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
@@ -254,7 +254,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
  	},
-@@ -3132,7 +3033,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3322,7 +3223,6 @@ const struct mt753x_info mt753x_table[]
  		.sw_setup = mt7988_setup,
  		.phy_read = mt7531_ind_phy_read,
  		.phy_write = mt7531_ind_phy_write,
@@ -264,7 +264,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -331,13 +331,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
  					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
  					 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
  					 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
@@ -278,7 +278,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  #define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
  #define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
-@@ -737,7 +730,6 @@ struct mt753x_info {
+@@ -747,7 +740,6 @@ struct mt753x_info {
  	int (*sw_setup)(struct dsa_switch *ds);
  	int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
  	int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
@@ -286,7 +286,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
  				  struct phylink_config *config);
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
-@@ -763,7 +755,6 @@ struct mt753x_info {
+@@ -773,7 +765,6 @@ struct mt753x_info {
   * @ports:		Holding the state among ports
   * @reg_mutex:		The lock for protecting among process accessing
   *			registers
@@ -294,7 +294,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
   * @p5_intf_sel:	Holding the current port 5 interface select
   * @p5_sgmii:		Flag for distinguishing if port 5 of the MT7531 switch
   *			has got SGMII
-@@ -785,8 +776,6 @@ struct mt7530_priv {
+@@ -795,8 +786,6 @@ struct mt7530_priv {
  	const struct mt753x_info *info;
  	unsigned int		id;
  	bool			mcm;
diff --git a/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch b/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
index f14634c17a..c83a627808 100644
--- a/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
+++ b/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
@@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2661,16 +2661,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2850,16 +2850,6 @@ mt7531_mac_config(struct dsa_switch *ds,
  	}
  }
  
@@ -35,7 +35,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static struct phylink_pcs *
  mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
  			      phy_interface_t interface)
-@@ -2696,8 +2686,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2885,8 +2875,8 @@ mt753x_phylink_mac_config(struct dsa_swi
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr_cur, mcr_new;
  
diff --git a/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch b/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
index 2fa17d4558..84ee7416bf 100644
--- a/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
+++ b/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2845,17 +2845,9 @@ static int
+@@ -3034,17 +3034,9 @@ static int
  mt753x_setup(struct dsa_switch *ds)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	if (ret)
  		return ret;
  
-@@ -2867,6 +2859,14 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3056,6 +3048,14 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
diff --git a/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch b/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
index d7c8180c8a..814a9d06e7 100644
--- a/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
+++ b/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
@@ -24,7 +24,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1047,7 +1047,6 @@ mt7530_port_enable(struct dsa_switch *ds
+@@ -1222,7 +1222,6 @@ mt7530_port_enable(struct dsa_switch *ds
  	priv->ports[port].enable = true;
  	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
  		   priv->ports[port].pm);
@@ -32,7 +32,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mutex_unlock(&priv->reg_mutex);
  
-@@ -1067,7 +1066,6 @@ mt7530_port_disable(struct dsa_switch *d
+@@ -1242,7 +1241,6 @@ mt7530_port_disable(struct dsa_switch *d
  	priv->ports[port].enable = false;
  	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
  		   PCR_MATRIX_CLR);
@@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mutex_unlock(&priv->reg_mutex);
  }
-@@ -2284,6 +2282,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2460,6 +2458,12 @@ mt7530_setup(struct dsa_switch *ds)
  	mt7530_mib_reset(ds);
  
  	for (i = 0; i < MT7530_NUM_PORTS; i++) {
@@ -53,7 +53,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		/* Disable forwarding by default on all ports */
  		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
  			   PCR_MATRIX_CLR);
-@@ -2386,6 +2390,12 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2565,6 +2569,12 @@ mt7531_setup_common(struct dsa_switch *d
  		     UNU_FFP_MASK);
  
  	for (i = 0; i < MT7530_NUM_PORTS; i++) {
diff --git a/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch b/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch
index d29b183be1..d9f91a932a 100644
--- a/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch
+++ b/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch
@@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2694,23 +2694,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2883,23 +2883,13 @@ mt753x_phylink_mac_config(struct dsa_swi
  			  const struct phylink_link_state *state)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -324,8 +324,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
  					 MT7531_FORCE_DPX | \
  					 MT7531_FORCE_RX_FC | \
  					 MT7531_FORCE_TX_FC)
diff --git a/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch b/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch
deleted file mode 100644
index e00615d540..0000000000
--- a/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From cfa7c85f92cd3814ad9748eb1ab25658c7f7cc67 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Wed, 20 Mar 2024 23:45:30 +0300
-Subject: [PATCH 48/48] net: dsa: mt7530: fix improper frames on all 25MHz and
- 40MHz XTAL MT7530
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530 switch after reset initialises with a core clock frequency that
-works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
-frequency must be set to 500MHz.
-
-The mt7530_pll_setup() function is responsible of setting the core clock
-frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
-causes MT7530 switch with 25MHz XTAL to egress and ingress frames
-improperly.
-
-Introduce a check to run it only on MT7530 with 40MHz XTAL.
-
-The core clock frequency is set by writing to a switch PHY's register.
-Access to the PHY's register is done via the MDIO bus the switch is also
-on. Therefore, it works only when the switch makes switch PHYs listen on
-the MDIO bus the switch is on. This is controlled either by the state of
-the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
-modifiable trap register.
-
-When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
-accessing PHY registers via the PHY indirect access control register of the
-switch.
-
-When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
-accessing PHY registers via the MDIO bus the switch is on.
-
-For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
-the core clock frequency won't be set to 500MHz, causing the switch to
-egress and ingress frames improperly.
-
-Run mt7530_pll_setup() after PHY direct access is set on the modifiable
-trap register.
-
-With these two changes, all MT7530 switches with 25MHz and 40MHz, and
-P1_LED_1 pulled high or low, will egress and ingress frames properly.
-
-Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/dsa/mt7530.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2259,8 +2259,6 @@ mt7530_setup(struct dsa_switch *ds)
- 		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- 		     SYS_CTRL_REG_RST);
- 
--	mt7530_pll_setup(priv);
--
- 	/* Lower Tx driving for TRGMII path */
- 	for (i = 0; i < NUM_TRGMII_CTRL; i++)
- 		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
-@@ -2276,6 +2274,9 @@ mt7530_setup(struct dsa_switch *ds)
- 	val |= MHWTRAP_MANUAL;
- 	mt7530_write(priv, MT7530_MHWTRAP, val);
- 
-+	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
-+		mt7530_pll_setup(priv);
-+
- 	mt753x_trap_frames(priv);
- 
- 	/* Enable and reset MIB counters */
diff --git a/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch b/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch
deleted file mode 100644
index dc202a55e6..0000000000
--- a/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 8 Apr 2024 10:08:53 +0300
-Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
- all boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
-enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
-(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
-the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
-SkyLake Huang (黃啟澤) from MediaTek for providing information on the
-internal EEE switch bit.
-
-There are existing boards that were not designed to pull the pin low.
-Because of that, the EEE status currently depends on the board design.
-
-The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
-used to control an LED. Once the bit is unset, the pin will be low. That
-will make the active low LED turn on. The pin is controlled by the switch
-PHY. It seems that the PHY controls the pin in the way that it inverts the
-pin state. That means depending on the wiring of the LED connected to
-LAN2LED0 on the board, the LED may be on without an active link.
-
-To not cause this unwanted behaviour whilst enabling EEE on all boards, set
-the internal EEE switch bit on the CORE_PLL_GROUP4 register.
-
-My testing on MT7531 shows a certain amount of traffic loss when EEE is
-enabled. That said, I haven't come across a board that enables EEE. So
-enable EEE on the switch MACs but disable EEE advertisement on the switch
-PHYs. This way, we don't change the behaviour of the majority of the boards
-that have this switch. The mediatek-ge PHY driver already disables EEE
-advertisement on the switch PHYs but my testing shows that it is somehow
-enabled afterwards. Disabling EEE advertisement before the PHY driver
-initialises keeps it off.
-
-With this change, EEE can now be enabled using ethtool.
-
-Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
- drivers/net/dsa/mt7530.h |  1 +
- 2 files changed, 13 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2496,18 +2496,25 @@ mt7531_setup(struct dsa_switch *ds)
- 	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- 		   MT7531_GPIO0_INTERRUPT);
- 
--	/* Enable PHY core PLL, since phy_device has not yet been created
--	 * provided for phy_[read,write]_mmd_indirect is called, we provide
--	 * our own mt7531_ind_mmd_phy_[read,write] to complete this
--	 * function.
-+	/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
-+	 * phy_device has not yet been created provided for
-+	 * phy_[read,write]_mmd_indirect is called, we provide our own
-+	 * mt7531_ind_mmd_phy_[read,write] to complete this function.
- 	 */
- 	val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
- 				      MDIO_MMD_VEND2, CORE_PLL_GROUP4);
--	val |= MT7531_PHY_PLL_BYPASS_MODE;
-+	val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
- 	val &= ~MT7531_PHY_PLL_OFF;
- 	mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
- 				 CORE_PLL_GROUP4, val);
- 
-+	/* Disable EEE advertisement on the switch PHYs. */
-+	for (i = MT753X_CTRL_PHY_ADDR;
-+	     i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
-+		mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
-+					 0);
-+	}
-+
- 	mt7531_setup_common(ds);
- 
- 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -616,6 +616,7 @@ enum mt7531_clk_skew {
- #define  RG_SYSPLL_DDSFBK_EN		BIT(12)
- #define  RG_SYSPLL_BIAS_EN		BIT(11)
- #define  RG_SYSPLL_BIAS_LPF_EN		BIT(10)
-+#define  MT7531_RG_SYSPLL_DMY2		BIT(6)
- #define  MT7531_PHY_PLL_OFF		BIT(5)
- #define  MT7531_PHY_PLL_BYPASS_MODE	BIT(4)
- 
diff --git a/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch b/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch
deleted file mode 100644
index 4d70e774a4..0000000000
--- a/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch
+++ /dev/null
@@ -1,483 +0,0 @@
-From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Tue, 9 Apr 2024 18:01:14 +0300
-Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST
- Port State
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer
-(DLL) of the Open Systems Interconnection basic reference model (OSI/RM)
-are described; the medium access control (MAC) and logical link control
-(LLC) sublayers. The MAC sublayer is the one facing the physical layer.
-
-In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-of the Bridge, at least two Ports, and higher layer entities with at least
-a Spanning Tree Protocol Entity included.
-
-Each Bridge Port also functions as an end station and shall provide the MAC
-Service to an LLC Entity. Each instance of the MAC Service is provided to a
-distinct LLC Entity that supports protocol identification, multiplexing,
-and demultiplexing, for protocol data unit (PDU) transmission and reception
-by one or more higher layer entities.
-
-It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-Entity associated with each Bridge Port is modeled as being directly
-connected to the attached Local Area Network (LAN).
-
-On the switch with CPU port architecture, CPU port functions as Management
-Port, and the Management Port functionality is provided by software which
-functions as an end station. Software is connected to an IEEE 802 LAN that
-is wholly contained within the system that incorporates the Bridge.
-Software provides access to the LLC Entity associated with each Bridge Port
-by the value of the source port field on the special tag on the frame
-received by software.
-
-We call frames that carry control information to determine the active
-topology and current extent of each Virtual Local Area Network (VLAN),
-i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN
-Registration Protocol Data Units (MVRPDUs), and frames from other link
-constrained protocols, such as Extensible Authentication Protocol over LAN
-(EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They
-are not forwarded by a Bridge. Permanently configured entries in the
-filtering database (FDB) ensure that such frames are discarded by the
-Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in
-detail:
-
-Each of the reserved MAC addresses specified in Table 8-1
-(01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-permanently configured in the FDB in C-VLAN components and ERs.
-
-Each of the reserved MAC addresses specified in Table 8-2
-(01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-configured in the FDB in S-VLAN components.
-
-Each of the reserved MAC addresses specified in Table 8-3
-(01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB
-in TPMR components.
-
-The FDB entries for reserved MAC addresses shall specify filtering for all
-Bridge Ports and all VIDs. Management shall not provide the capability to
-modify or remove entries for reserved MAC addresses.
-
-The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-propagation of PDUs within a Bridged Network, as follows:
-
-  The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that
-  no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
-  component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
-  PDUs transmitted using this destination address, or any other addresses
-  that appear in Table 8-1, Table 8-2, and Table 8-3
-  (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
-  therefore travel no further than those stations that can be reached via a
-  single individual LAN from the originating station.
-
-  The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
-  address that no conformant S-VLAN component, C-VLAN component, or MAC
-  Bridge can forward; however, this address is relayed by a TPMR component.
-  PDUs using this destination address, or any of the other addresses that
-  appear in both Table 8-1 and Table 8-2 but not in Table 8-3
-  (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed
-  by any TPMRs but will propagate no further than the nearest S-VLAN
-  component, C-VLAN component, or MAC Bridge.
-
-  The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an
-  address that no conformant C-VLAN component, MAC Bridge can forward;
-  however, it is relayed by TPMR components and S-VLAN components. PDUs
-  using this destination address, or any of the other addresses that appear
-  in Table 8-1 but not in either Table 8-2 or Table 8-3
-  (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and
-  S-VLAN components but will propagate no further than the nearest C-VLAN
-  component or MAC Bridge.
-
-Because the LLC Entity associated with each Bridge Port is provided via CPU
-port, we must not filter these frames but forward them to CPU port.
-
-In a Bridge, the transmission Port is majorly decided by ingress and egress
-rules, FDB, and spanning tree Port State functions of the Forwarding
-Process. For link-local frames, only CPU port should be designated as
-destination port in the FDB, and the other functions of the Forwarding
-Process must not interfere with the decision of the transmission Port. We
-call this process trapping frames to CPU port.
-
-Therefore, on the switch with CPU port architecture, link-local frames must
-be trapped to CPU port, and certain link-local frames received by a Port of
-a Bridge comprising a TPMR component or an S-VLAN component must be
-excluded from it.
-
-A Bridge of the switch with CPU port architecture cannot comprise a
-Two-Port MAC Relay (TPMR) component as a TPMR component supports only a
-subset of the functionality of a MAC Bridge. A Bridge comprising two Ports
-(Management Port doesn't count) of this architecture will either function
-as a standard MAC Bridge or a standard VLAN Bridge.
-
-Therefore, a Bridge of this architecture can only comprise S-VLAN
-components, C-VLAN components, or MAC Bridge components. Since there's no
-TPMR component, we don't need to relay PDUs using the destination addresses
-specified on the Nearest non-TPMR section, and the proportion of the
-Nearest Customer Bridge section where they must be relayed by TPMR
-components.
-
-One option to trap link-local frames to CPU port is to add static FDB
-entries with CPU port designated as destination port. However, because that
-Independent VLAN Learning (IVL) is being used on every VID, each entry only
-applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-Bridge component or a C-VLAN component, there would have to be 16 times
-4096 entries. This switch intellectual property can only hold a maximum of
-2048 entries. Using this option, there also isn't a mechanism to prevent
-link-local frames from being discarded when the spanning tree Port State of
-the reception Port is discarding.
-
-The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-registers. Whilst this applies to every VID, it doesn't contain all of the
-reserved MAC addresses without affecting the remaining Standard Group MAC
-Addresses. The REV_UN frame tag utilised using the RGAC4 register covers
-the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-The latter option provides better but not complete conformance.
-
-This switch intellectual property also does not provide a mechanism to trap
-link-local frames with specific destination addresses to CPU port by
-Bridge, to conform to the filtering rules for the distinct Bridge
-components.
-
-Therefore, regardless of the type of the Bridge component, link-local
-frames with these destination addresses will be trapped to CPU port:
-
-01-80-C2-00-00-[00,01,02,03,0E]
-
-In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-
-  Link-local frames with these destination addresses won't be trapped to
-  CPU port which won't conform to IEEE Std 802.1Q-2022:
-
-  01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-
-In a Bridge comprising an S-VLAN component:
-
-  Link-local frames with these destination addresses will be trapped to CPU
-  port which won't conform to IEEE Std 802.1Q-2022:
-
-  01-80-C2-00-00-00
-
-  Link-local frames with these destination addresses won't be trapped to
-  CPU port which won't conform to IEEE Std 802.1Q-2022:
-
-  01-80-C2-00-00-[04,05,06,07,08,09,0A]
-
-Currently on this switch intellectual property, if the spanning tree Port
-State of the reception Port is discarding, link-local frames will be
-discarded.
-
-To trap link-local frames regardless of the spanning tree Port State, make
-the switch regard them as Bridge Protocol Data Units (BPDUs). This switch
-intellectual property only lets the frames regarded as BPDUs bypass the
-spanning tree Port State function of the Forwarding Process.
-
-With this change, the only remaining interference is the ingress rules.
-When the reception Port has no PVID assigned on software, VLAN-untagged
-frames won't be allowed in. There doesn't seem to be a mechanism on the
-switch intellectual property to have link-local frames bypass this function
-of the Forwarding Process.
-
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------
- drivers/net/dsa/mt7530.h |   5 +
- 2 files changed, 200 insertions(+), 34 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -943,20 +943,173 @@ static void mt7530_setup_port5(struct ds
- 	mutex_unlock(&priv->reg_mutex);
- }
- 
--/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
-- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
-- * must only be propagated to C-VLAN and MAC Bridge components. That means
-- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
-- * these frames are supposed to be processed by the CPU (software). So we make
-- * the switch only forward them to the CPU port. And if received from a CPU
-- * port, forward to a single port. The software is responsible of making the
-- * switch conform to the latter by setting a single port as destination port on
-- * the special tag.
-- *
-- * This switch intellectual property cannot conform to this part of the standard
-- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
-- * DAs, it also includes :22-FF which the scope of propagation is not supposed
-- * to be restricted for these MAC DAs.
-+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
-+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
-+ * described; the medium access control (MAC) and logical link control (LLC)
-+ * sublayers. The MAC sublayer is the one facing the physical layer.
-+ *
-+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-+ * of the Bridge, at least two Ports, and higher layer entities with at least a
-+ * Spanning Tree Protocol Entity included.
-+ *
-+ * Each Bridge Port also functions as an end station and shall provide the MAC
-+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
-+ * distinct LLC Entity that supports protocol identification, multiplexing, and
-+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
-+ * one or more higher layer entities.
-+ *
-+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-+ * Entity associated with each Bridge Port is modeled as being directly
-+ * connected to the attached Local Area Network (LAN).
-+ *
-+ * On the switch with CPU port architecture, CPU port functions as Management
-+ * Port, and the Management Port functionality is provided by software which
-+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
-+ * wholly contained within the system that incorporates the Bridge. Software
-+ * provides access to the LLC Entity associated with each Bridge Port by the
-+ * value of the source port field on the special tag on the frame received by
-+ * software.
-+ *
-+ * We call frames that carry control information to determine the active
-+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
-+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
-+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
-+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
-+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
-+ * forwarded by a Bridge. Permanently configured entries in the filtering
-+ * database (FDB) ensure that such frames are discarded by the Forwarding
-+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-1
-+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-+ * permanently configured in the FDB in C-VLAN components and ERs.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-2
-+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-+ * configured in the FDB in S-VLAN components.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-3
-+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
-+ * TPMR components.
-+ *
-+ * The FDB entries for reserved MAC addresses shall specify filtering for all
-+ * Bridge Ports and all VIDs. Management shall not provide the capability to
-+ * modify or remove entries for reserved MAC addresses.
-+ *
-+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-+ * propagation of PDUs within a Bridged Network, as follows:
-+ *
-+ *   The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
-+ *   conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
-+ *   component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
-+ *   PDUs transmitted using this destination address, or any other addresses
-+ *   that appear in Table 8-1, Table 8-2, and Table 8-3
-+ *   (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
-+ *   therefore travel no further than those stations that can be reached via a
-+ *   single individual LAN from the originating station.
-+ *
-+ *   The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
-+ *   address that no conformant S-VLAN component, C-VLAN component, or MAC
-+ *   Bridge can forward; however, this address is relayed by a TPMR component.
-+ *   PDUs using this destination address, or any of the other addresses that
-+ *   appear in both Table 8-1 and Table 8-2 but not in Table 8-3
-+ *   (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
-+ *   any TPMRs but will propagate no further than the nearest S-VLAN component,
-+ *   C-VLAN component, or MAC Bridge.
-+ *
-+ *   The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
-+ *   that no conformant C-VLAN component, MAC Bridge can forward; however, it is
-+ *   relayed by TPMR components and S-VLAN components. PDUs using this
-+ *   destination address, or any of the other addresses that appear in Table 8-1
-+ *   but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
-+ *   will be relayed by TPMR components and S-VLAN components but will propagate
-+ *   no further than the nearest C-VLAN component or MAC Bridge.
-+ *
-+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
-+ * port, we must not filter these frames but forward them to CPU port.
-+ *
-+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
-+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
-+ * For link-local frames, only CPU port should be designated as destination port
-+ * in the FDB, and the other functions of the Forwarding Process must not
-+ * interfere with the decision of the transmission Port. We call this process
-+ * trapping frames to CPU port.
-+ *
-+ * Therefore, on the switch with CPU port architecture, link-local frames must
-+ * be trapped to CPU port, and certain link-local frames received by a Port of a
-+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
-+ * from it.
-+ *
-+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
-+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
-+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
-+ * doesn't count) of this architecture will either function as a standard MAC
-+ * Bridge or a standard VLAN Bridge.
-+ *
-+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
-+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
-+ * we don't need to relay PDUs using the destination addresses specified on the
-+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
-+ * section where they must be relayed by TPMR components.
-+ *
-+ * One option to trap link-local frames to CPU port is to add static FDB entries
-+ * with CPU port designated as destination port. However, because that
-+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
-+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
-+ * entries. This switch intellectual property can only hold a maximum of 2048
-+ * entries. Using this option, there also isn't a mechanism to prevent
-+ * link-local frames from being discarded when the spanning tree Port State of
-+ * the reception Port is discarding.
-+ *
-+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-+ * registers. Whilst this applies to every VID, it doesn't contain all of the
-+ * reserved MAC addresses without affecting the remaining Standard Group MAC
-+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
-+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-+ * The latter option provides better but not complete conformance.
-+ *
-+ * This switch intellectual property also does not provide a mechanism to trap
-+ * link-local frames with specific destination addresses to CPU port by Bridge,
-+ * to conform to the filtering rules for the distinct Bridge components.
-+ *
-+ * Therefore, regardless of the type of the Bridge component, link-local frames
-+ * with these destination addresses will be trapped to CPU port:
-+ *
-+ * 01-80-C2-00-00-[00,01,02,03,0E]
-+ *
-+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-+ *
-+ *   Link-local frames with these destination addresses won't be trapped to CPU
-+ *   port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ *   01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-+ *
-+ * In a Bridge comprising an S-VLAN component:
-+ *
-+ *   Link-local frames with these destination addresses will be trapped to CPU
-+ *   port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ *   01-80-C2-00-00-00
-+ *
-+ *   Link-local frames with these destination addresses won't be trapped to CPU
-+ *   port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ *   01-80-C2-00-00-[04,05,06,07,08,09,0A]
-+ *
-+ * To trap link-local frames to CPU port as conformant as this switch
-+ * intellectual property can allow, link-local frames are made to be regarded as
-+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
-+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
-+ * State function of the Forwarding Process.
-+ *
-+ * The only remaining interference is the ingress rules. When the reception Port
-+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
-+ * There doesn't seem to be a mechanism on the switch intellectual property to
-+ * have link-local frames bypass this function of the Forwarding Process.
-  */
- static void
- mt753x_trap_frames(struct mt7530_priv *priv)
-@@ -964,35 +1117,43 @@ mt753x_trap_frames(struct mt7530_priv *p
- 	/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
- 	 * VLAN-untagged.
- 	 */
--	mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
--		   MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
--		   MT753X_BPDU_PORT_FW_MASK,
--		   MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--		   MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_BPDU_CPU_ONLY);
-+	mt7530_rmw(priv, MT753X_BPC,
-+		   MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
-+			   MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
-+			   MT753X_BPDU_PORT_FW_MASK,
-+		   MT753X_PAE_BPDU_FR |
-+			   MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+			   MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_BPDU_CPU_ONLY);
- 
- 	/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
- 	 * them VLAN-untagged.
- 	 */
--	mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
--		   MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
--		   MT753X_R01_PORT_FW_MASK,
--		   MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--		   MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_BPDU_CPU_ONLY);
-+	mt7530_rmw(priv, MT753X_RGAC1,
-+		   MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
-+			   MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
-+			   MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
-+		   MT753X_R02_BPDU_FR |
-+			   MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+			   MT753X_R01_BPDU_FR |
-+			   MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_BPDU_CPU_ONLY);
- 
- 	/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
- 	 * them VLAN-untagged.
- 	 */
--	mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
--		   MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
--		   MT753X_R03_PORT_FW_MASK,
--		   MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--		   MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--		   MT753X_BPDU_CPU_ONLY);
-+	mt7530_rmw(priv, MT753X_RGAC2,
-+		   MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
-+			   MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
-+			   MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
-+		   MT753X_R0E_BPDU_FR |
-+			   MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+			   MT753X_R03_BPDU_FR |
-+			   MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   MT753X_BPDU_CPU_ONLY);
- }
- 
- static void
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -65,6 +65,7 @@ enum mt753x_id {
- 
- /* Registers for BPDU and PAE frame control*/
- #define MT753X_BPC			0x24
-+#define  MT753X_PAE_BPDU_FR		BIT(25)
- #define  MT753X_PAE_EG_TAG_MASK		GENMASK(24, 22)
- #define  MT753X_PAE_EG_TAG(x)		FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
- #define  MT753X_PAE_PORT_FW_MASK	GENMASK(18, 16)
-@@ -75,20 +76,24 @@ enum mt753x_id {
- 
- /* Register for :01 and :02 MAC DA frame control */
- #define MT753X_RGAC1			0x28
-+#define  MT753X_R02_BPDU_FR		BIT(25)
- #define  MT753X_R02_EG_TAG_MASK		GENMASK(24, 22)
- #define  MT753X_R02_EG_TAG(x)		FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
- #define  MT753X_R02_PORT_FW_MASK	GENMASK(18, 16)
- #define  MT753X_R02_PORT_FW(x)		FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
-+#define  MT753X_R01_BPDU_FR		BIT(9)
- #define  MT753X_R01_EG_TAG_MASK		GENMASK(8, 6)
- #define  MT753X_R01_EG_TAG(x)		FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
- #define  MT753X_R01_PORT_FW_MASK	GENMASK(2, 0)
- 
- /* Register for :03 and :0E MAC DA frame control */
- #define MT753X_RGAC2			0x2c
-+#define  MT753X_R0E_BPDU_FR		BIT(25)
- #define  MT753X_R0E_EG_TAG_MASK		GENMASK(24, 22)
- #define  MT753X_R0E_EG_TAG(x)		FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
- #define  MT753X_R0E_PORT_FW_MASK	GENMASK(18, 16)
- #define  MT753X_R0E_PORT_FW(x)		FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
-+#define  MT753X_R03_BPDU_FR		BIT(9)
- #define  MT753X_R03_EG_TAG_MASK		GENMASK(8, 6)
- #define  MT753X_R03_EG_TAG(x)		FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
- #define  MT753X_R03_PORT_FW_MASK	GENMASK(2, 0)
diff --git a/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patc b/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patc
deleted file mode 100644
index ca2657d57d..0000000000
--- a/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patc
+++ /dev/null
@@ -1,135 +0,0 @@
-From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Fri, 12 Apr 2024 16:15:34 +0100
-Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Convert mt753x to provide its own phylink MAC operations, thus avoiding
-the shim layer in DSA's port.c
-
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
- 1 file changed, 29 insertions(+), 17 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2841,28 +2841,34 @@ mt7531_mac_config(struct dsa_switch *ds,
- }
- 
- static struct phylink_pcs *
--mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
-+mt753x_phylink_mac_select_pcs(struct phylink_config *config,
- 			      phy_interface_t interface)
- {
--	struct mt7530_priv *priv = ds->priv;
-+	struct dsa_port *dp = dsa_phylink_to_port(config);
-+	struct mt7530_priv *priv = dp->ds->priv;
- 
- 	switch (interface) {
- 	case PHY_INTERFACE_MODE_TRGMII:
--		return &priv->pcs[port].pcs;
-+		return &priv->pcs[dp->index].pcs;
- 	case PHY_INTERFACE_MODE_SGMII:
- 	case PHY_INTERFACE_MODE_1000BASEX:
- 	case PHY_INTERFACE_MODE_2500BASEX:
--		return priv->ports[port].sgmii_pcs;
-+		return priv->ports[dp->index].sgmii_pcs;
- 	default:
- 		return NULL;
- 	}
- }
- 
- static void
--mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
-+mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
- 			  const struct phylink_link_state *state)
- {
--	struct mt7530_priv *priv = ds->priv;
-+	struct dsa_port *dp = dsa_phylink_to_port(config);
-+	struct dsa_switch *ds = dp->ds;
-+	struct mt7530_priv *priv;
-+	int port = dp->index;
-+
-+	priv = ds->priv;
- 
- 	if ((port == 5 || port == 6) && priv->info->mac_port_config)
- 		priv->info->mac_port_config(ds, port, mode, state->interface);
-@@ -2872,23 +2878,25 @@ mt753x_phylink_mac_config(struct dsa_swi
- 		mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
- }
- 
--static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
-+static void mt753x_phylink_mac_link_down(struct phylink_config *config,
- 					 unsigned int mode,
- 					 phy_interface_t interface)
- {
--	struct mt7530_priv *priv = ds->priv;
-+	struct dsa_port *dp = dsa_phylink_to_port(config);
-+	struct mt7530_priv *priv = dp->ds->priv;
- 
--	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
-+	mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
- }
- 
--static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
-+static void mt753x_phylink_mac_link_up(struct phylink_config *config,
-+				       struct phy_device *phydev,
- 				       unsigned int mode,
- 				       phy_interface_t interface,
--				       struct phy_device *phydev,
- 				       int speed, int duplex,
- 				       bool tx_pause, bool rx_pause)
- {
--	struct mt7530_priv *priv = ds->priv;
-+	struct dsa_port *dp = dsa_phylink_to_port(config);
-+	struct mt7530_priv *priv = dp->ds->priv;
- 	u32 mcr;
- 
- 	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
-@@ -2923,7 +2931,7 @@ static void mt753x_phylink_mac_link_up(s
- 		}
- 	}
- 
--	mt7530_set(priv, MT7530_PMCR_P(port), mcr);
-+	mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
- }
- 
- static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
-@@ -3148,16 +3156,19 @@ const struct dsa_switch_ops mt7530_switc
- 	.port_mirror_add	= mt753x_port_mirror_add,
- 	.port_mirror_del	= mt753x_port_mirror_del,
- 	.phylink_get_caps	= mt753x_phylink_get_caps,
--	.phylink_mac_select_pcs	= mt753x_phylink_mac_select_pcs,
--	.phylink_mac_config	= mt753x_phylink_mac_config,
--	.phylink_mac_link_down	= mt753x_phylink_mac_link_down,
--	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
- 	.get_mac_eee		= mt753x_get_mac_eee,
- 	.set_mac_eee		= mt753x_set_mac_eee,
- 	.master_state_change	= mt753x_conduit_state_change,
- };
- EXPORT_SYMBOL_GPL(mt7530_switch_ops);
- 
-+static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
-+	.mac_select_pcs	= mt753x_phylink_mac_select_pcs,
-+	.mac_config	= mt753x_phylink_mac_config,
-+	.mac_link_down	= mt753x_phylink_mac_link_down,
-+	.mac_link_up	= mt753x_phylink_mac_link_up,
-+};
-+
- const struct mt753x_info mt753x_table[] = {
- 	[ID_MT7621] = {
- 		.id = ID_MT7621,
-@@ -3227,6 +3238,7 @@ mt7530_probe_common(struct mt7530_priv *
- 	priv->dev = dev;
- 	priv->ds->priv = priv;
- 	priv->ds->ops = &mt7530_switch_ops;
-+	priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
- 	mutex_init(&priv->reg_mutex);
- 	dev_set_drvdata(dev, priv);
- 
diff --git a/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch b/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch
new file mode 100644
index 0000000000..8962e560f7
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch
@@ -0,0 +1,135 @@
+From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 Apr 2024 16:15:34 +0100
+Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Convert mt753x to provide its own phylink MAC operations, thus avoiding
+the shim layer in DSA's port.c
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
+ 1 file changed, 29 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2861,28 +2861,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+ 
+ static struct phylink_pcs *
+-mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
++mt753x_phylink_mac_select_pcs(struct phylink_config *config,
+ 			      phy_interface_t interface)
+ {
+-	struct mt7530_priv *priv = ds->priv;
++	struct dsa_port *dp = dsa_phylink_to_port(config);
++	struct mt7530_priv *priv = dp->ds->priv;
+ 
+ 	switch (interface) {
+ 	case PHY_INTERFACE_MODE_TRGMII:
+-		return &priv->pcs[port].pcs;
++		return &priv->pcs[dp->index].pcs;
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+-		return priv->ports[port].sgmii_pcs;
++		return priv->ports[dp->index].sgmii_pcs;
+ 	default:
+ 		return NULL;
+ 	}
+ }
+ 
+ static void
+-mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
+ 			  const struct phylink_link_state *state)
+ {
+-	struct mt7530_priv *priv = ds->priv;
++	struct dsa_port *dp = dsa_phylink_to_port(config);
++	struct dsa_switch *ds = dp->ds;
++	struct mt7530_priv *priv;
++	int port = dp->index;
++
++	priv = ds->priv;
+ 
+ 	if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ 		priv->info->mac_port_config(ds, port, mode, state->interface);
+@@ -2892,23 +2898,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+ 		mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+ 
+-static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+ 					 unsigned int mode,
+ 					 phy_interface_t interface)
+ {
+-	struct mt7530_priv *priv = ds->priv;
++	struct dsa_port *dp = dsa_phylink_to_port(config);
++	struct mt7530_priv *priv = dp->ds->priv;
+ 
+-	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
++	mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+ 
+-static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_up(struct phylink_config *config,
++				       struct phy_device *phydev,
+ 				       unsigned int mode,
+ 				       phy_interface_t interface,
+-				       struct phy_device *phydev,
+ 				       int speed, int duplex,
+ 				       bool tx_pause, bool rx_pause)
+ {
+-	struct mt7530_priv *priv = ds->priv;
++	struct dsa_port *dp = dsa_phylink_to_port(config);
++	struct mt7530_priv *priv = dp->ds->priv;
+ 	u32 mcr;
+ 
+ 	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+@@ -2943,7 +2951,7 @@ static void mt753x_phylink_mac_link_up(s
+ 		}
+ 	}
+ 
+-	mt7530_set(priv, MT7530_PMCR_P(port), mcr);
++	mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
+ }
+ 
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+@@ -3169,16 +3177,19 @@ const struct dsa_switch_ops mt7530_switc
+ 	.port_mirror_add	= mt753x_port_mirror_add,
+ 	.port_mirror_del	= mt753x_port_mirror_del,
+ 	.phylink_get_caps	= mt753x_phylink_get_caps,
+-	.phylink_mac_select_pcs	= mt753x_phylink_mac_select_pcs,
+-	.phylink_mac_config	= mt753x_phylink_mac_config,
+-	.phylink_mac_link_down	= mt753x_phylink_mac_link_down,
+-	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
+ 	.get_mac_eee		= mt753x_get_mac_eee,
+ 	.set_mac_eee		= mt753x_set_mac_eee,
+ 	.master_state_change	= mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+ 
++static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
++	.mac_select_pcs	= mt753x_phylink_mac_select_pcs,
++	.mac_config	= mt753x_phylink_mac_config,
++	.mac_link_down	= mt753x_phylink_mac_link_down,
++	.mac_link_up	= mt753x_phylink_mac_link_up,
++};
++
+ const struct mt753x_info mt753x_table[] = {
+ 	[ID_MT7621] = {
+ 		.id = ID_MT7621,
+@@ -3248,6 +3259,7 @@ mt7530_probe_common(struct mt7530_priv *
+ 	priv->dev = dev;
+ 	priv->ds->priv = priv;
+ 	priv->ds->ops = &mt7530_switch_ops;
++	priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
+ 	mutex_init(&priv->reg_mutex);
+ 	dev_set_drvdata(dev, priv);
+ 
diff --git a/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch b/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch
deleted file mode 100644
index 7640a9cb41..0000000000
--- a/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From d4097ddef078a113643a6dcde01e99741f852adb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 13 Apr 2024 16:01:39 +0300
-Subject: [PATCH 2/5] net: dsa: mt7530: fix mirroring frames received on local
- port
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This switch intellectual property provides a bit on the ARL global control
-register which controls allowing mirroring frames which are received on the
-local port (monitor port). This bit is unset after reset.
-
-This ability must be enabled to fully support the port mirroring feature on
-this switch intellectual property.
-
-Therefore, this patch fixes the traffic not being reflected on a port,
-which would be configured like below:
-
-  tc qdisc add dev swp0 clsact
-
-  tc filter add dev swp0 ingress matchall skip_sw \
-  action mirred egress mirror dev swp0
-
-As a side note, this configuration provides the hairpinning feature for a
-single port.
-
-Fixes: 37feab6076aa ("net: dsa: mt7530: add support for port mirroring")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 6 ++++++
- drivers/net/dsa/mt7530.h | 4 ++++
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2471,6 +2471,9 @@ mt7530_setup(struct dsa_switch *ds)
- 			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- 	}
- 
-+	/* Allow mirroring frames received on the local port (monitor port). */
-+	mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
- 	ret = mt7530_setup_vlan0(priv);
- 	if (ret)
-@@ -2582,6 +2585,9 @@ mt7531_setup_common(struct dsa_switch *d
- 			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- 	}
- 
-+	/* Allow mirroring frames received on the local port (monitor port). */
-+	mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- 	/* Flush the FDB table */
- 	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
- 	if (ret < 0)
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -32,6 +32,10 @@ enum mt753x_id {
- #define SYSC_REG_RSTCTRL		0x34
- #define  RESET_MCM			BIT(2)
- 
-+/* Register for ARL global control */
-+#define MT753X_AGC			0xc
-+#define  LOCAL_EN			BIT(7)
-+
- /* Registers to mac forward control for unknown frames */
- #define MT7530_MFC			0x10
- #define  BC_FFP(x)			(((x) & 0xff) << 24)
diff --git a/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch b/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch
index 304ea21adc..cd5b7b287d 100644
--- a/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch
+++ b/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch
@@ -26,7 +26,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -1876,14 +1876,16 @@ mt7530_port_vlan_del(struct dsa_switch *
+@@ -1890,14 +1890,16 @@ mt7530_port_vlan_del(struct dsa_switch *
  
  static int mt753x_mirror_port_get(unsigned int id, u32 val)
  {
diff --git a/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch b/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch
index 6b6a255e26..e9c8f955c9 100644
--- a/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch
+++ b/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch
@@ -184,7 +184,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  err:
  	if (ret < 0)
  		dev_err(&bus->dev,
-@@ -2670,16 +2678,19 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2684,16 +2692,19 @@ mt7531_setup(struct dsa_switch *ds)
  	 * phy_[read,write]_mmd_indirect is called, we provide our own
  	 * mt7531_ind_mmd_phy_[read,write] to complete this function.
  	 */
diff --git a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/backport-6.1/790-54-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
index 44cf60cf14..44cf60cf14 100644
--- a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
+++ b/target/linux/generic/backport-6.1/790-54-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
diff --git a/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
new file mode 100644
index 0000000000..158e5f8c00
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
@@ -0,0 +1,200 @@
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -903,7 +903,7 @@ static void mt7530_setup_port5(struct ds
+ 		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+ 
+ 		/* Setup the MAC by default for the cpu port */
+-		mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ 		break;
+ 	case P5_INTF_SEL_GMAC5:
+ 		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2449,8 +2449,8 @@ mt7530_setup(struct dsa_switch *ds)
+ 		/* Clear link settings and enable force mode to force link down
+ 		 * on all ports until they're enabled later.
+ 		 */
+-		mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+-			   PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++		mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++			   MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+ 
+ 		/* Disable forwarding by default on all ports */
+ 		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2560,8 +2560,8 @@ mt7531_setup_common(struct dsa_switch *d
+ 		/* Clear link settings and enable force mode to force link down
+ 		 * on all ports until they're enabled later.
+ 		 */
+-		mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+-			   MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++		mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++			   MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+ 
+ 		/* Disable forwarding by default on all ports */
+ 		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2644,7 +2644,7 @@ mt7531_setup(struct dsa_switch *ds)
+ 
+ 	/* Force link down on all ports before internal reset */
+ 	for (i = 0; i < MT7530_NUM_PORTS; i++)
+-		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++		mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+ 
+ 	/* Reset the switch through internal reset */
+ 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2886,7 +2886,7 @@ mt753x_phylink_mac_config(struct phylink
+ 
+ 	/* Are we connected to external phy */
+ 	if (port == 5 && dsa_is_user_port(ds, 5))
+-		mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++		mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+ 
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_down
+ 	struct dsa_port *dp = dsa_phylink_to_port(config);
+ 	struct mt7530_priv *priv = dp->ds->priv;
+ 
+-	mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++	mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+ 
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2910,7 +2910,7 @@ static void mt753x_phylink_mac_link_up(s
+ 	struct mt7530_priv *priv = dp->ds->priv;
+ 	u32 mcr;
+ 
+-	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++	mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+ 
+ 	switch (speed) {
+ 	case SPEED_1000:
+@@ -2925,9 +2925,9 @@ static void mt753x_phylink_mac_link_up(s
+ 	if (duplex == DUPLEX_FULL) {
+ 		mcr |= PMCR_FORCE_FDX;
+ 		if (tx_pause)
+-			mcr |= PMCR_TX_FC_EN;
++			mcr |= PMCR_FORCE_TX_FC_EN;
+ 		if (rx_pause)
+-			mcr |= PMCR_RX_FC_EN;
++			mcr |= PMCR_FORCE_RX_FC_EN;
+ 	}
+ 
+ 	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2942,7 +2942,7 @@ static void mt753x_phylink_mac_link_up(s
+ 		}
+ 	}
+ 
+-	mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++	mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+ 
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define  G0_PORT_VID_DEF		G0_PORT_VID(0)
+ 
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x)		(0x3000 + ((x) * 0x100))
+-#define  PMCR_IFG_XMIT(x)		(((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x)		(0x3000 + ((x) * 0x100))
++#define  PMCR_IFG_XMIT_MASK		GENMASK(19, 18)
++#define  PMCR_IFG_XMIT(x)		FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define  PMCR_EXT_PHY			BIT(17)
+ #define  PMCR_MAC_MODE			BIT(16)
+-#define  PMCR_FORCE_MODE		BIT(15)
+-#define  PMCR_TX_EN			BIT(14)
+-#define  PMCR_RX_EN			BIT(13)
++#define  MT7530_FORCE_MODE		BIT(15)
++#define  PMCR_MAC_TX_EN			BIT(14)
++#define  PMCR_MAC_RX_EN			BIT(13)
+ #define  PMCR_BACKOFF_EN		BIT(9)
+ #define  PMCR_BACKPR_EN			BIT(8)
+ #define  PMCR_FORCE_EEE1G		BIT(7)
+ #define  PMCR_FORCE_EEE100		BIT(6)
+-#define  PMCR_TX_FC_EN			BIT(5)
+-#define  PMCR_RX_FC_EN			BIT(4)
++#define  PMCR_FORCE_RX_FC_EN		BIT(5)
++#define  PMCR_FORCE_TX_FC_EN		BIT(4)
+ #define  PMCR_FORCE_SPEED_1000		BIT(3)
+ #define  PMCR_FORCE_SPEED_100		BIT(2)
+ #define  PMCR_FORCE_FDX			BIT(1)
+ #define  PMCR_FORCE_LNK			BIT(0)
+-#define  PMCR_SPEED_MASK		(PMCR_FORCE_SPEED_100 | \
+-					 PMCR_FORCE_SPEED_1000)
+-#define  MT7531_FORCE_LNK		BIT(31)
+-#define  MT7531_FORCE_SPD		BIT(30)
+-#define  MT7531_FORCE_DPX		BIT(29)
+-#define  MT7531_FORCE_RX_FC		BIT(28)
+-#define  MT7531_FORCE_TX_FC		BIT(27)
+-#define  MT7531_FORCE_EEE100		BIT(26)
+-#define  MT7531_FORCE_EEE1G		BIT(25)
+-#define  MT7531_FORCE_MODE		(MT7531_FORCE_LNK | \
+-					 MT7531_FORCE_SPD | \
+-					 MT7531_FORCE_DPX | \
+-					 MT7531_FORCE_RX_FC | \
+-					 MT7531_FORCE_TX_FC | \
+-					 MT7531_FORCE_EEE100 | \
+-					 MT7531_FORCE_EEE1G)
+-#define  PMCR_LINK_SETTINGS_MASK	(PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+-					 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+-					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+-					 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+-					 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define  MT7531_FORCE_MODE_LNK		BIT(31)
++#define  MT7531_FORCE_MODE_SPD		BIT(30)
++#define  MT7531_FORCE_MODE_DPX		BIT(29)
++#define  MT7531_FORCE_MODE_RX_FC	BIT(28)
++#define  MT7531_FORCE_MODE_TX_FC	BIT(27)
++#define  MT7531_FORCE_MODE_EEE100	BIT(26)
++#define  MT7531_FORCE_MODE_EEE1G	BIT(25)
++#define  MT7531_FORCE_MODE_MASK		(MT7531_FORCE_MODE_LNK | \
++					 MT7531_FORCE_MODE_SPD | \
++					 MT7531_FORCE_MODE_DPX | \
++					 MT7531_FORCE_MODE_RX_FC | \
++					 MT7531_FORCE_MODE_TX_FC | \
++					 MT7531_FORCE_MODE_EEE100 | \
++					 MT7531_FORCE_MODE_EEE1G)
++#define  PMCR_LINK_SETTINGS_MASK	(PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++					 PMCR_FORCE_EEE1G | \
++					 PMCR_FORCE_EEE100 | \
++					 PMCR_FORCE_RX_FC_EN | \
++					 PMCR_FORCE_TX_FC_EN | \
++					 PMCR_FORCE_SPEED_1000 | \
++					 PMCR_FORCE_SPEED_100 | \
++					 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+ 
+ #define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
+ #define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
diff --git a/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
new file mode 100644
index 0000000000..9a0ce7c36c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
@@ -0,0 +1,185 @@
+From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:10 +0300
+Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
+ MT7530 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The p5_intf_sel pointer is used to store the information of whether PHY
+muxing is used or not. PHY muxing is a feature specific to port 5 of the
+MT7530 switch. Do not use it for other switch models.
+
+Rename the pointer to p5_mode to store the mode the port is being used in.
+Rename the p5_interface_select enum to mt7530_p5_mode, the string
+representation to mt7530_p5_mode_str, and the enum elements.
+
+If PHY muxing is not detected, the default mode, GMAC5, will be used.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 15 +++++-----
+ 2 files changed, 33 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -864,19 +864,15 @@ mt7530_set_ageing_time(struct dsa_switch
+ 	return 0;
+ }
+ 
+-static const char *p5_intf_modes(unsigned int p5_interface)
++static const char *mt7530_p5_mode_str(unsigned int mode)
+ {
+-	switch (p5_interface) {
+-	case P5_DISABLED:
+-		return "DISABLED";
+-	case P5_INTF_SEL_PHY_P0:
+-		return "PHY P0";
+-	case P5_INTF_SEL_PHY_P4:
+-		return "PHY P4";
+-	case P5_INTF_SEL_GMAC5:
+-		return "GMAC5";
++	switch (mode) {
++	case MUX_PHY_P0:
++		return "MUX PHY P0";
++	case MUX_PHY_P4:
++		return "MUX PHY P4";
+ 	default:
+-		return "unknown";
++		return "GMAC5";
+ 	}
+ }
+ 
+@@ -893,23 +889,23 @@ static void mt7530_setup_port5(struct ds
+ 	val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ 	val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+ 
+-	switch (priv->p5_intf_sel) {
+-	case P5_INTF_SEL_PHY_P0:
+-		/* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
++	switch (priv->p5_mode) {
++	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
++	case MUX_PHY_P0:
+ 		val |= MHWTRAP_PHY0_SEL;
+ 		fallthrough;
+-	case P5_INTF_SEL_PHY_P4:
+-		/* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
++
++	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
++	case MUX_PHY_P4:
+ 		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+ 
+ 		/* Setup the MAC by default for the cpu port */
+ 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ 		break;
+-	case P5_INTF_SEL_GMAC5:
+-		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+-		val &= ~MHWTRAP_P5_DIS;
+-		break;
++
++	/* GMAC5: P5 -> SoC MAC or external PHY */
+ 	default:
++		val &= ~MHWTRAP_P5_DIS;
+ 		break;
+ 	}
+ 
+@@ -937,8 +933,8 @@ static void mt7530_setup_port5(struct ds
+ 
+ 	mt7530_write(priv, MT7530_MHWTRAP, val);
+ 
+-	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+-		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
++	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
++		mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+ 
+ 	mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2481,13 +2477,11 @@ mt7530_setup(struct dsa_switch *ds)
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Setup port 5 */
+-	if (!dsa_is_unused_port(ds, 5)) {
+-		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-	} else {
++	/* Check for PHY muxing on port 5 */
++	if (dsa_is_unused_port(ds, 5)) {
+ 		/* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
+-		 * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+-		 * is detected.
++		 * Set priv->p5_mode to the appropriate value if PHY muxing is
++		 * detected.
+ 		 */
+ 		for_each_child_of_node(dn, mac_np) {
+ 			if (!of_device_is_compatible(mac_np,
+@@ -2511,17 +2505,16 @@ mt7530_setup(struct dsa_switch *ds)
+ 				}
+ 				id = of_mdio_parse_addr(ds->dev, phy_node);
+ 				if (id == 0)
+-					priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
++					priv->p5_mode = MUX_PHY_P0;
+ 				if (id == 4)
+-					priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
++					priv->p5_mode = MUX_PHY_P4;
+ 			}
+ 			of_node_put(mac_np);
+ 			of_node_put(phy_node);
+ 			break;
+ 		}
+ 
+-		if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
+-		    priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++		if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
+ 			mt7530_setup_port5(ds, interface);
+ 	}
+ 
+@@ -2659,9 +2652,6 @@ mt7531_setup(struct dsa_switch *ds)
+ 			   MT7531_EXT_P_MDIO_12);
+ 	}
+ 
+-	if (!dsa_is_unused_port(ds, 5))
+-		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-
+ 	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ 		   MT7531_GPIO0_INTERRUPT);
+ 
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -708,12 +708,11 @@ struct mt7530_port {
+ 	struct phylink_pcs *sgmii_pcs;
+ };
+ 
+-/* Port 5 interface select definitions */
+-enum p5_interface_select {
+-	P5_DISABLED,
+-	P5_INTF_SEL_PHY_P0,
+-	P5_INTF_SEL_PHY_P4,
+-	P5_INTF_SEL_GMAC5,
++/* Port 5 mode definitions of the MT7530 switch */
++enum mt7530_p5_mode {
++	GMAC5,
++	MUX_PHY_P0,
++	MUX_PHY_P4,
+ };
+ 
+ struct mt7530_priv;
+@@ -769,7 +768,7 @@ struct mt753x_info {
+  * @ports:		Holding the state among ports
+  * @reg_mutex:		The lock for protecting among process accessing
+  *			registers
+- * @p5_intf_sel:	Holding the current port 5 interface select
++ * @p5_mode:		Holding the current mode of port 5 of the MT7530 switch
+  * @p5_sgmii:		Flag for distinguishing if port 5 of the MT7531 switch
+  *			has got SGMII
+  * @irq:		IRQ number of the switch
+@@ -791,7 +790,7 @@ struct mt7530_priv {
+ 	const struct mt753x_info *info;
+ 	unsigned int		id;
+ 	bool			mcm;
+-	enum p5_interface_select p5_intf_sel;
++	enum mt7530_p5_mode	p5_mode;
+ 	bool			p5_sgmii;
+ 	u8			mirror_rx;
+ 	u8			mirror_tx;
diff --git a/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
new file mode 100644
index 0000000000..c8ffd5f07c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
@@ -0,0 +1,169 @@
+From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:11 +0300
+Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
+ mt753x_to_cpu_fw
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt753x_bpdu_port_fw enum is globally used for manipulating the process
+of deciding the forwardable ports, specifically concerning the CPU port(s).
+Therefore, rename it and the values in it to mt753x_to_cpu_fw.
+
+Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
+ drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
+ 2 files changed, 56 insertions(+), 64 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1114,42 +1114,34 @@ mt753x_trap_frames(struct mt7530_priv *p
+ 	 * VLAN-untagged.
+ 	 */
+ 	mt7530_rmw(priv, MT753X_BPC,
+-		   MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
+-			   MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+-			   MT753X_BPDU_PORT_FW_MASK,
+-		   MT753X_PAE_BPDU_FR |
+-			   MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+-			   MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_BPDU_CPU_ONLY);
++		   PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
++			   BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
++		   PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
++			   BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   TO_CPU_FW_CPU_ONLY);
+ 
+ 	/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ 	 * them VLAN-untagged.
+ 	 */
+ 	mt7530_rmw(priv, MT753X_RGAC1,
+-		   MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
+-			   MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
+-			   MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
+-		   MT753X_R02_BPDU_FR |
+-			   MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+-			   MT753X_R01_BPDU_FR |
+-			   MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_BPDU_CPU_ONLY);
++		   R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
++			   R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
++		   R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
++			   R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   TO_CPU_FW_CPU_ONLY);
+ 
+ 	/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ 	 * them VLAN-untagged.
+ 	 */
+ 	mt7530_rmw(priv, MT753X_RGAC2,
+-		   MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
+-			   MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
+-			   MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
+-		   MT753X_R0E_BPDU_FR |
+-			   MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+-			   MT753X_R03_BPDU_FR |
+-			   MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+-			   MT753X_BPDU_CPU_ONLY);
++		   R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
++			   R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
++		   R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
++			   R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++			   TO_CPU_FW_CPU_ONLY);
+ }
+ 
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -67,47 +67,47 @@ enum mt753x_id {
+ #define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+ 					 MT7531_MIRROR_MASK : MIRROR_MASK)
+ 
+-/* Registers for BPDU and PAE frame control*/
++/* Register for BPDU and PAE frame control */
+ #define MT753X_BPC			0x24
+-#define  MT753X_PAE_BPDU_FR		BIT(25)
+-#define  MT753X_PAE_EG_TAG_MASK		GENMASK(24, 22)
+-#define  MT753X_PAE_EG_TAG(x)		FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+-#define  MT753X_PAE_PORT_FW_MASK	GENMASK(18, 16)
+-#define  MT753X_PAE_PORT_FW(x)		FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
+-#define  MT753X_BPDU_EG_TAG_MASK	GENMASK(8, 6)
+-#define  MT753X_BPDU_EG_TAG(x)		FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
+-#define  MT753X_BPDU_PORT_FW_MASK	GENMASK(2, 0)
++#define  PAE_BPDU_FR			BIT(25)
++#define  PAE_EG_TAG_MASK		GENMASK(24, 22)
++#define  PAE_EG_TAG(x)			FIELD_PREP(PAE_EG_TAG_MASK, x)
++#define  PAE_PORT_FW_MASK		GENMASK(18, 16)
++#define  PAE_PORT_FW(x)			FIELD_PREP(PAE_PORT_FW_MASK, x)
++#define  BPDU_EG_TAG_MASK		GENMASK(8, 6)
++#define  BPDU_EG_TAG(x)			FIELD_PREP(BPDU_EG_TAG_MASK, x)
++#define  BPDU_PORT_FW_MASK		GENMASK(2, 0)
+ 
+-/* Register for :01 and :02 MAC DA frame control */
++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
+ #define MT753X_RGAC1			0x28
+-#define  MT753X_R02_BPDU_FR		BIT(25)
+-#define  MT753X_R02_EG_TAG_MASK		GENMASK(24, 22)
+-#define  MT753X_R02_EG_TAG(x)		FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+-#define  MT753X_R02_PORT_FW_MASK	GENMASK(18, 16)
+-#define  MT753X_R02_PORT_FW(x)		FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
+-#define  MT753X_R01_BPDU_FR		BIT(9)
+-#define  MT753X_R01_EG_TAG_MASK		GENMASK(8, 6)
+-#define  MT753X_R01_EG_TAG(x)		FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+-#define  MT753X_R01_PORT_FW_MASK	GENMASK(2, 0)
++#define  R02_BPDU_FR			BIT(25)
++#define  R02_EG_TAG_MASK		GENMASK(24, 22)
++#define  R02_EG_TAG(x)			FIELD_PREP(R02_EG_TAG_MASK, x)
++#define  R02_PORT_FW_MASK		GENMASK(18, 16)
++#define  R02_PORT_FW(x)			FIELD_PREP(R02_PORT_FW_MASK, x)
++#define  R01_BPDU_FR			BIT(9)
++#define  R01_EG_TAG_MASK		GENMASK(8, 6)
++#define  R01_EG_TAG(x)			FIELD_PREP(R01_EG_TAG_MASK, x)
++#define  R01_PORT_FW_MASK		GENMASK(2, 0)
+ 
+-/* Register for :03 and :0E MAC DA frame control */
++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
+ #define MT753X_RGAC2			0x2c
+-#define  MT753X_R0E_BPDU_FR		BIT(25)
+-#define  MT753X_R0E_EG_TAG_MASK		GENMASK(24, 22)
+-#define  MT753X_R0E_EG_TAG(x)		FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+-#define  MT753X_R0E_PORT_FW_MASK	GENMASK(18, 16)
+-#define  MT753X_R0E_PORT_FW(x)		FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
+-#define  MT753X_R03_BPDU_FR		BIT(9)
+-#define  MT753X_R03_EG_TAG_MASK		GENMASK(8, 6)
+-#define  MT753X_R03_EG_TAG(x)		FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+-#define  MT753X_R03_PORT_FW_MASK	GENMASK(2, 0)
++#define  R0E_BPDU_FR			BIT(25)
++#define  R0E_EG_TAG_MASK		GENMASK(24, 22)
++#define  R0E_EG_TAG(x)			FIELD_PREP(R0E_EG_TAG_MASK, x)
++#define  R0E_PORT_FW_MASK		GENMASK(18, 16)
++#define  R0E_PORT_FW(x)			FIELD_PREP(R0E_PORT_FW_MASK, x)
++#define  R03_BPDU_FR			BIT(9)
++#define  R03_EG_TAG_MASK		GENMASK(8, 6)
++#define  R03_EG_TAG(x)			FIELD_PREP(R03_EG_TAG_MASK, x)
++#define  R03_PORT_FW_MASK		GENMASK(2, 0)
+ 
+-enum mt753x_bpdu_port_fw {
+-	MT753X_BPDU_FOLLOW_MFC,
+-	MT753X_BPDU_CPU_EXCLUDE = 4,
+-	MT753X_BPDU_CPU_INCLUDE = 5,
+-	MT753X_BPDU_CPU_ONLY = 6,
+-	MT753X_BPDU_DROP = 7,
++enum mt753x_to_cpu_fw {
++	TO_CPU_FW_SYSTEM_DEFAULT,
++	TO_CPU_FW_CPU_EXCLUDE = 4,
++	TO_CPU_FW_CPU_INCLUDE = 5,
++	TO_CPU_FW_CPU_ONLY = 6,
++	TO_CPU_FW_DROP = 7,
+ };
+ 
+ /* Registers for address table access */
diff --git a/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
new file mode 100644
index 0000000000..c977fe46cd
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
@@ -0,0 +1,201 @@
+From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:12 +0300
+Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
+ add MT7531_QRY_FFP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
+SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
+MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
+IGMP/MLD Query Frame Flooding Ports mask for MT7531.
+
+Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
+
+Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
+macros.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 ++++++++--------------
+ drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
+ 2 files changed, 57 insertions(+), 50 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1154,7 +1154,7 @@ mt753x_cpu_port_enable(struct dsa_switch
+ 		     PORT_SPEC_TAG);
+ 
+ 	/* Enable flooding on the CPU port */
+-	mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
++	mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ 		   UNU_FFP(BIT(port)));
+ 
+ 	/* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames
+@@ -1318,15 +1318,15 @@ mt7530_port_bridge_flags(struct dsa_swit
+ 			   flags.val & BR_LEARNING ? 0 : SA_DIS);
+ 
+ 	if (flags.mask & BR_FLOOD)
+-		mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
++		mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
+ 			   flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+ 
+ 	if (flags.mask & BR_MCAST_FLOOD)
+-		mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
++		mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
+ 			   flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+ 
+ 	if (flags.mask & BR_BCAST_FLOOD)
+-		mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
++		mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
+ 			   flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+ 
+ 	return 0;
+@@ -1862,20 +1862,6 @@ mt7530_port_vlan_del(struct dsa_switch *
+ 	return 0;
+ }
+ 
+-static int mt753x_mirror_port_get(unsigned int id, u32 val)
+-{
+-	return (id == ID_MT7531 || id == ID_MT7988) ?
+-		       MT7531_MIRROR_PORT_GET(val) :
+-		       MIRROR_PORT(val);
+-}
+-
+-static int mt753x_mirror_port_set(unsigned int id, u32 val)
+-{
+-	return (id == ID_MT7531 || id == ID_MT7988) ?
+-		       MT7531_MIRROR_PORT_SET(val) :
+-		       MIRROR_PORT(val);
+-}
+-
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
+ 				  struct dsa_mall_mirror_tc_entry *mirror,
+ 				  bool ingress, struct netlink_ext_ack *extack)
+@@ -1891,14 +1877,14 @@ static int mt753x_port_mirror_add(struct
+ 	val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+ 
+ 	/* MT7530 only supports one monitor port */
+-	monitor_port = mt753x_mirror_port_get(priv->id, val);
++	monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
+ 	if (val & MT753X_MIRROR_EN(priv->id) &&
+ 	    monitor_port != mirror->to_local_port)
+ 		return -EEXIST;
+ 
+ 	val |= MT753X_MIRROR_EN(priv->id);
+-	val &= ~MT753X_MIRROR_MASK(priv->id);
+-	val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
++	val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
++	val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
+ 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+ 
+ 	val = mt7530_read(priv, MT7530_PCR_P(port));
+@@ -2538,7 +2524,7 @@ mt7531_setup_common(struct dsa_switch *d
+ 	mt7530_mib_reset(ds);
+ 
+ 	/* Disable flooding on all ports */
+-	mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
++	mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ 		     UNU_FFP_MASK);
+ 
+ 	for (i = 0; i < MT7530_NUM_PORTS; i++) {
+@@ -3100,10 +3086,12 @@ mt753x_conduit_state_change(struct dsa_s
+ 	else
+ 		priv->active_cpu_ports &= ~mask;
+ 
+-	if (priv->active_cpu_ports)
+-		val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++	if (priv->active_cpu_ports) {
++		val = MT7530_CPU_EN |
++		      MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
++	}
+ 
+-	mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++	mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ }
+ 
+ static int mt7988_setup(struct dsa_switch *ds)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -36,36 +36,55 @@ enum mt753x_id {
+ #define MT753X_AGC			0xc
+ #define  LOCAL_EN			BIT(7)
+ 
+-/* Registers to mac forward control for unknown frames */
+-#define MT7530_MFC			0x10
+-#define  BC_FFP(x)			(((x) & 0xff) << 24)
+-#define  BC_FFP_MASK			BC_FFP(~0)
+-#define  UNM_FFP(x)			(((x) & 0xff) << 16)
+-#define  UNM_FFP_MASK			UNM_FFP(~0)
+-#define  UNU_FFP(x)			(((x) & 0xff) << 8)
+-#define  UNU_FFP_MASK			UNU_FFP(~0)
+-#define  CPU_EN				BIT(7)
+-#define  CPU_PORT_MASK			GENMASK(6, 4)
+-#define  CPU_PORT(x)			FIELD_PREP(CPU_PORT_MASK, x)
+-#define  MIRROR_EN			BIT(3)
+-#define  MIRROR_PORT(x)			((x) & 0x7)
+-#define  MIRROR_MASK			0x7
++/* Register for MAC forward control */
++#define MT753X_MFC			0x10
++#define  BC_FFP_MASK			GENMASK(31, 24)
++#define  BC_FFP(x)			FIELD_PREP(BC_FFP_MASK, x)
++#define  UNM_FFP_MASK			GENMASK(23, 16)
++#define  UNM_FFP(x)			FIELD_PREP(UNM_FFP_MASK, x)
++#define  UNU_FFP_MASK			GENMASK(15, 8)
++#define  UNU_FFP(x)			FIELD_PREP(UNU_FFP_MASK, x)
++#define  MT7530_CPU_EN			BIT(7)
++#define  MT7530_CPU_PORT_MASK		GENMASK(6, 4)
++#define  MT7530_CPU_PORT(x)		FIELD_PREP(MT7530_CPU_PORT_MASK, x)
++#define  MT7530_MIRROR_EN		BIT(3)
++#define  MT7530_MIRROR_PORT_MASK	GENMASK(2, 0)
++#define  MT7530_MIRROR_PORT_GET(x)	FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
++#define  MT7530_MIRROR_PORT_SET(x)	FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
++#define  MT7531_QRY_FFP_MASK		GENMASK(7, 0)
++#define  MT7531_QRY_FFP(x)		FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+ 
+-/* Registers for CPU forward control */
++/* Register for CPU forward control */
+ #define MT7531_CFC			0x4
+ #define  MT7531_MIRROR_EN		BIT(19)
+-#define  MT7531_MIRROR_MASK		(MIRROR_MASK << 16)
+-#define  MT7531_MIRROR_PORT_GET(x)	(((x) >> 16) & MIRROR_MASK)
+-#define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
++#define  MT7531_MIRROR_PORT_MASK	GENMASK(18, 16)
++#define  MT7531_MIRROR_PORT_GET(x)	FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
++#define  MT7531_MIRROR_PORT_SET(x)	FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
+ #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
+ #define  MT7531_CPU_PMAP(x)		FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+ 
+-#define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+-					 MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+-					 MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
+-					 MT7531_MIRROR_MASK : MIRROR_MASK)
++#define MT753X_MIRROR_REG(id)		((id == ID_MT7531 || \
++					  id == ID_MT7988) ? \
++					 MT7531_CFC : MT753X_MFC)
++
++#define MT753X_MIRROR_EN(id)		((id == ID_MT7531 || \
++					  id == ID_MT7988) ? \
++					 MT7531_MIRROR_EN : MT7530_MIRROR_EN)
++
++#define MT753X_MIRROR_PORT_MASK(id)	((id == ID_MT7531 || \
++					  id == ID_MT7988) ? \
++					 MT7531_MIRROR_PORT_MASK : \
++					 MT7530_MIRROR_PORT_MASK)
++
++#define MT753X_MIRROR_PORT_GET(id, val)	((id == ID_MT7531 || \
++					  id == ID_MT7988) ? \
++					 MT7531_MIRROR_PORT_GET(val) : \
++					 MT7530_MIRROR_PORT_GET(val))
++
++#define MT753X_MIRROR_PORT_SET(id, val)	((id == ID_MT7531 || \
++					  id == ID_MT7988) ? \
++					 MT7531_MIRROR_PORT_SET(val) : \
++					 MT7530_MIRROR_PORT_SET(val))
+ 
+ /* Register for BPDU and PAE frame control */
+ #define MT753X_BPC			0x24
diff --git a/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
new file mode 100644
index 0000000000..3c487d21f6
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
@@ -0,0 +1,257 @@
+From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:13 +0300
+Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
+ MT7530_MHWTRAP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
+It's called hardware trap on MT7530, software trap on MT7531. That's
+because some bits of the trap on MT7530 cannot be modified by software
+whilst all bits of the trap on MT7531 can. Rename the definitions for them
+to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
+definitions specific to the switch model.
+
+Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
+
+Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
+par with the "MT7621 Giga Switch Programming Guide v0.3" document.
+
+Make an enumaration for the XTAL frequency. Set the data type of the xtal
+variable on mt7531_pll_setup() to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
+ drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
+ 2 files changed, 54 insertions(+), 55 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
+ 
+ 	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+ 
+-	xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++	xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+ 
+-	if (xtal == HWTRAP_XTAL_25MHZ)
++	if (xtal == MT7530_XTAL_25MHZ)
+ 		ssc_delta = 0x57;
+ 	else
+ 		ssc_delta = 0x87;
+ 
+ 	if (priv->id == ID_MT7621) {
+ 		/* PLL frequency: 125MHz: 1.0GBit */
+-		if (xtal == HWTRAP_XTAL_40MHZ)
++		if (xtal == MT7530_XTAL_40MHZ)
+ 			ncpo1 = 0x0640;
+-		if (xtal == HWTRAP_XTAL_25MHZ)
++		if (xtal == MT7530_XTAL_25MHZ)
+ 			ncpo1 = 0x0a00;
+ 	} else { /* PLL frequency: 250MHz: 2.0Gbit */
+-		if (xtal == HWTRAP_XTAL_40MHZ)
++		if (xtal == MT7530_XTAL_40MHZ)
+ 			ncpo1 = 0x0c80;
+-		if (xtal == HWTRAP_XTAL_25MHZ)
++		if (xtal == MT7530_XTAL_25MHZ)
+ 			ncpo1 = 0x1400;
+ 	}
+ 
+@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
++	enum mt7531_xtal_fsel xtal;
+ 	u32 top_sig;
+ 	u32 hwstrap;
+-	u32 xtal;
+ 	u32 val;
+ 
+ 	val = mt7530_read(priv, MT7531_CREV);
+ 	top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+-	hwstrap = mt7530_read(priv, MT7531_HWTRAP);
++	hwstrap = mt7530_read(priv, MT753X_TRAP);
+ 	if ((val & CHIP_REV_M) > 0)
+-		xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
+-						    HWTRAP_XTAL_FSEL_25MHZ;
++		xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
++						    MT7531_XTAL_FSEL_25MHZ;
+ 	else
+-		xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
++		xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
++						   MT7531_XTAL_FSEL_40MHZ;
+ 
+ 	/* Step 1 : Disable MT7531 COREPLL */
+ 	val = mt7530_read(priv, MT7531_PLLGP_EN);
+@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ 	usleep_range(25, 35);
+ 
+ 	switch (xtal) {
+-	case HWTRAP_XTAL_FSEL_25MHZ:
++	case MT7531_XTAL_FSEL_25MHZ:
+ 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ 		val &= ~RG_COREPLL_SDM_PCW_M;
+ 		val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
+ 		mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ 		break;
+-	case HWTRAP_XTAL_FSEL_40MHZ:
++	case MT7531_XTAL_FSEL_40MHZ:
+ 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ 		val &= ~RG_COREPLL_SDM_PCW_M;
+ 		val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
+@@ -884,20 +885,20 @@ static void mt7530_setup_port5(struct ds
+ 
+ 	mutex_lock(&priv->reg_mutex);
+ 
+-	val = mt7530_read(priv, MT7530_MHWTRAP);
++	val = mt7530_read(priv, MT753X_MTRAP);
+ 
+-	val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+-	val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
++	val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
++	val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
+ 
+ 	switch (priv->p5_mode) {
+ 	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+ 	case MUX_PHY_P0:
+-		val |= MHWTRAP_PHY0_SEL;
++		val |= MT7530_P5_PHY0_SEL;
+ 		fallthrough;
+ 
+ 	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ 	case MUX_PHY_P4:
+-		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
++		val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+ 
+ 		/* Setup the MAC by default for the cpu port */
+ 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+@@ -905,13 +906,13 @@ static void mt7530_setup_port5(struct ds
+ 
+ 	/* GMAC5: P5 -> SoC MAC or external PHY */
+ 	default:
+-		val &= ~MHWTRAP_P5_DIS;
++		val &= ~MT7530_P5_DIS;
+ 		break;
+ 	}
+ 
+ 	/* Setup RGMII settings */
+ 	if (phy_interface_mode_is_rgmii(interface)) {
+-		val |= MHWTRAP_P5_RGMII_MODE;
++		val |= MT7530_P5_RGMII_MODE;
+ 
+ 		/* P5 RGMII RX Clock Control: delay setting for 1000M */
+ 		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+@@ -931,7 +932,7 @@ static void mt7530_setup_port5(struct ds
+ 			     P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ 	}
+ 
+-	mt7530_write(priv, MT7530_MHWTRAP, val);
++	mt7530_write(priv, MT753X_MTRAP, val);
+ 
+ 	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
+ 		mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+@@ -2370,7 +2371,7 @@ mt7530_setup(struct dsa_switch *ds)
+ 	}
+ 
+ 	/* Waiting for MT7530 got to stable */
+-	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++	INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 				 20, 1000000);
+ 	if (ret < 0) {
+@@ -2385,7 +2386,7 @@ mt7530_setup(struct dsa_switch *ds)
+ 		return -ENODEV;
+ 	}
+ 
+-	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
+ 		dev_err(priv->dev,
+ 			"MT7530 with a 20MHz XTAL is not supported!\n");
+ 		return -EINVAL;
+@@ -2406,12 +2407,12 @@ mt7530_setup(struct dsa_switch *ds)
+ 			   RD_TAP_MASK, RD_TAP(16));
+ 
+ 	/* Enable port 6 */
+-	val = mt7530_read(priv, MT7530_MHWTRAP);
+-	val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
+-	val |= MHWTRAP_MANUAL;
+-	mt7530_write(priv, MT7530_MHWTRAP, val);
++	val = mt7530_read(priv, MT753X_MTRAP);
++	val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
++	val |= MT7530_CHG_TRAP;
++	mt7530_write(priv, MT753X_MTRAP, val);
+ 
+-	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
++	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ 		mt7530_pll_setup(priv);
+ 
+ 	mt753x_trap_frames(priv);
+@@ -2591,7 +2592,7 @@ mt7531_setup(struct dsa_switch *ds)
+ 	}
+ 
+ 	/* Waiting for MT7530 got to stable */
+-	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++	INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 				 20, 1000000);
+ 	if (ret < 0) {
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
+ 	MT7531_CLK_SKEW_REVERSE = 3,
+ };
+ 
+-/* Register for hw trap status */
+-#define MT7530_HWTRAP			0x7800
+-#define  HWTRAP_XTAL_MASK		(BIT(10) | BIT(9))
+-#define  HWTRAP_XTAL_25MHZ		(BIT(10) | BIT(9))
+-#define  HWTRAP_XTAL_40MHZ		(BIT(10))
+-#define  HWTRAP_XTAL_20MHZ		(BIT(9))
++/* Register for trap status */
++#define MT753X_TRAP			0x7800
++#define  MT7530_XTAL_MASK		(BIT(10) | BIT(9))
++#define  MT7530_XTAL_25MHZ		(BIT(10) | BIT(9))
++#define  MT7530_XTAL_40MHZ		BIT(10)
++#define  MT7530_XTAL_20MHZ		BIT(9)
++#define  MT7531_XTAL25			BIT(7)
+ 
+-#define MT7531_HWTRAP			0x7800
+-#define  HWTRAP_XTAL_FSEL_MASK		BIT(7)
+-#define  HWTRAP_XTAL_FSEL_25MHZ		BIT(7)
+-#define  HWTRAP_XTAL_FSEL_40MHZ		0
+-/* Unique fields of (M)HWSTRAP for MT7531 */
+-#define  XTAL_FSEL_S			7
+-#define  XTAL_FSEL_M			BIT(7)
+-#define  PHY_EN				BIT(6)
+-#define  CHG_STRAP			BIT(8)
++/* Register for trap modification */
++#define MT753X_MTRAP			0x7804
++#define  MT7530_P5_PHY0_SEL		BIT(20)
++#define  MT7530_CHG_TRAP		BIT(16)
++#define  MT7530_P5_MAC_SEL		BIT(13)
++#define  MT7530_P6_DIS			BIT(8)
++#define  MT7530_P5_RGMII_MODE		BIT(7)
++#define  MT7530_P5_DIS			BIT(6)
++#define  MT7530_PHY_INDIRECT_ACCESS	BIT(5)
++#define  MT7531_CHG_STRAP		BIT(8)
++#define  MT7531_PHY_EN			BIT(6)
+ 
+-/* Register for hw trap modification */
+-#define MT7530_MHWTRAP			0x7804
+-#define  MHWTRAP_PHY0_SEL		BIT(20)
+-#define  MHWTRAP_MANUAL			BIT(16)
+-#define  MHWTRAP_P5_MAC_SEL		BIT(13)
+-#define  MHWTRAP_P6_DIS			BIT(8)
+-#define  MHWTRAP_P5_RGMII_MODE		BIT(7)
+-#define  MHWTRAP_P5_DIS			BIT(6)
+-#define  MHWTRAP_PHY_ACCESS		BIT(5)
++enum mt7531_xtal_fsel {
++	MT7531_XTAL_FSEL_25MHZ,
++	MT7531_XTAL_FSEL_40MHZ,
++};
+ 
+ /* Register for TOP signal control */
+ #define MT7530_TOP_SIG_CTRL		0x7808
diff --git a/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
new file mode 100644
index 0000000000..cfc38f81d0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
@@ -0,0 +1,117 @@
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -887,8 +887,7 @@ static void mt7530_setup_port5(struct ds
+ 
+ 	val = mt7530_read(priv, MT753X_MTRAP);
+ 
+-	val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+-	val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++	val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+ 
+ 	switch (priv->p5_mode) {
+ 	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -898,15 +897,13 @@ static void mt7530_setup_port5(struct ds
+ 
+ 	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ 	case MUX_PHY_P4:
+-		val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ 		/* Setup the MAC by default for the cpu port */
+ 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ 		break;
+ 
+ 	/* GMAC5: P5 -> SoC MAC or external PHY */
+ 	default:
+-		val &= ~MT7530_P5_DIS;
++		val |= MT7530_P5_MAC_SEL;
+ 		break;
+ 	}
+ 
+@@ -1200,6 +1197,14 @@ mt7530_port_enable(struct dsa_switch *ds
+ 
+ 	mutex_unlock(&priv->reg_mutex);
+ 
++	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++		return 0;
++
++	if (port == 5)
++		mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++	else if (port == 6)
++		mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ 	return 0;
+ }
+ 
+@@ -1218,6 +1223,14 @@ mt7530_port_disable(struct dsa_switch *d
+ 		   PCR_MATRIX_CLR);
+ 
+ 	mutex_unlock(&priv->reg_mutex);
++
++	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++		return;
++
++	if (port == 5)
++		mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++	else if (port == 6)
++		mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+ 
+ static int
+@@ -2406,11 +2419,11 @@ mt7530_setup(struct dsa_switch *ds)
+ 		mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ 			   RD_TAP_MASK, RD_TAP(16));
+ 
+-	/* Enable port 6 */
+-	val = mt7530_read(priv, MT753X_MTRAP);
+-	val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+-	val |= MT7530_CHG_TRAP;
+-	mt7530_write(priv, MT753X_MTRAP, val);
++	/* Allow modifying the trap and directly access PHY registers via the
++	 * MDIO bus the switch is on.
++	 */
++	mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++		   MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+ 
+ 	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ 		mt7530_pll_setup(priv);
+@@ -2493,8 +2506,11 @@ mt7530_setup(struct dsa_switch *ds)
+ 			break;
+ 		}
+ 
+-		if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++		if (priv->p5_mode == MUX_PHY_P0 ||
++		    priv->p5_mode == MUX_PHY_P4) {
++			mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ 			mt7530_setup_port5(ds, interface);
++		}
+ 	}
+ 
+ #ifdef CONFIG_GPIOLIB
diff --git a/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
new file mode 100644
index 0000000000..178ac8022f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
@@ -0,0 +1,39 @@
+From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:15 +0300
+Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
+ mt7531_setup_common on error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7530_setup_mdio() and mt7531_setup_common() functions should be
+checked for errors. Return if the functions return a non-zero value.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2672,7 +2672,9 @@ mt7531_setup(struct dsa_switch *ds)
+ 					 0);
+ 	}
+ 
+-	mt7531_setup_common(ds);
++	ret = mt7531_setup_common(ds);
++	if (ret)
++		return ret;
+ 
+ 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
+ 	ret = mt7530_setup_vlan0(priv);
+@@ -3031,6 +3033,8 @@ mt753x_setup(struct dsa_switch *ds)
+ 	ret = mt7530_setup_mdio(priv);
+ 	if (ret && priv->irq)
+ 		mt7530_free_irq_common(priv);
++	if (ret)
++		return ret;
+ 
+ 	/* Initialise the PCS devices */
+ 	for (i = 0; i < priv->ds->num_ports; i++) {
diff --git a/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
new file mode 100644
index 0000000000..af8edf5a42
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
@@ -0,0 +1,75 @@
+From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:16 +0300
+Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
+ switch model
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the support of the MT7988 SoC switch, the MAC speed capabilities
+defined on mt753x_phylink_get_caps() won't apply to all switch models
+anymore. Move them to more appropriate locations instead of overwriting
+config->mac_capabilities.
+
+Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
+the support of MT7531 and MT7988 SoC switch.
+
+Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2690,6 +2690,8 @@ mt7531_setup(struct dsa_switch *ds)
+ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+ 				     struct phylink_config *config)
+ {
++	config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ 	switch (port) {
+ 	/* Ports which are connected to switch PHYs. There is no MII pinout. */
+ 	case 0 ... 4:
+@@ -2721,6 +2723,8 @@ static void mt7531_mac_port_get_caps(str
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+ 
++	config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ 	switch (port) {
+ 	/* Ports which are connected to switch PHYs. There is no MII pinout. */
+ 	case 0 ... 4:
+@@ -2760,14 +2764,17 @@ static void mt7988_mac_port_get_caps(str
+ 	case 0 ... 3:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
++
++		config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ 		break;
+ 
+ 	/* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ 	case 6:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
+-		config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+-					   MAC_10000FD;
++
++		config->mac_capabilities |= MAC_10000FD;
++		break;
+ 	}
+ }
+ 
+@@ -2937,9 +2944,7 @@ static void mt753x_phylink_get_caps(stru
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+ 
+-	/* This switch only supports full-duplex at 1Gbps */
+-	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+-				   MAC_10 | MAC_100 | MAC_1000FD;
++	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
+ 
+ 	/* This driver does not make use of the speed, duplex, pause or the
+ 	 * advertisement in its mac_config, so it is safe to mark this driver
diff --git a/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
new file mode 100644
index 0000000000..3825952dc3
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
@@ -0,0 +1,33 @@
+From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:17 +0300
+Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Get rid of checking whether functions are filled properly. priv->info which
+is an mt753x_info structure is filled and checked for before this check.
+It's unnecessary checking whether it's filled properly.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3235,13 +3235,6 @@ mt7530_probe_common(struct mt7530_priv *
+ 	if (!priv->info)
+ 		return -EINVAL;
+ 
+-	/* Sanity check if these required device operations are filled
+-	 * properly.
+-	 */
+-	if (!priv->info->sw_setup || !priv->info->phy_read ||
+-	    !priv->info->phy_write || !priv->info->mac_port_get_caps)
+-		return -EINVAL;
+-
+ 	priv->id = priv->info->id;
+ 	priv->dev = dev;
+ 	priv->ds->priv = priv;
diff --git a/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
new file mode 100644
index 0000000000..df47458014
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
@@ -0,0 +1,71 @@
+From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:18 +0300
+Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
+FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
+SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c |  8 ++++----
+ drivers/net/dsa/mt7530.h | 13 +++++++------
+ 2 files changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3062,10 +3062,10 @@ static int mt753x_get_mac_eee(struct dsa
+ 			      struct ethtool_eee *e)
+ {
+ 	struct mt7530_priv *priv = ds->priv;
+-	u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
++	u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+ 
+ 	e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
+-	e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
++	e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
+ 
+ 	return 0;
+ }
+@@ -3079,11 +3079,11 @@ static int mt753x_set_mac_eee(struct dsa
+ 	if (e->tx_lpi_timer > 0xFFF)
+ 		return -EINVAL;
+ 
+-	set = SET_LPI_THRESH(e->tx_lpi_timer);
++	set = LPI_THRESH_SET(e->tx_lpi_timer);
+ 	if (!e->tx_lpi_enabled)
+ 		/* Force LPI Mode without a delay */
+ 		set |= LPI_MODE_EN;
+-	mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
++	mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
+ 
+ 	return 0;
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
+ 					 PMCR_FORCE_SPEED_100 | \
+ 					 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+ 
+-#define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
+-#define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
+-#define  WAKEUP_TIME_100(x)		(((x) & 0xFF) << 16)
++#define MT753X_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
++#define  WAKEUP_TIME_1000_MASK		GENMASK(31, 24)
++#define  WAKEUP_TIME_1000(x)		FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
++#define  WAKEUP_TIME_100_MASK		GENMASK(23, 16)
++#define  WAKEUP_TIME_100(x)		FIELD_PREP(WAKEUP_TIME_100_MASK, x)
+ #define  LPI_THRESH_MASK		GENMASK(15, 4)
+-#define  LPI_THRESH_SHT			4
+-#define  SET_LPI_THRESH(x)		(((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
+-#define  GET_LPI_THRESH(x)		(((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
++#define  LPI_THRESH_GET(x)		FIELD_GET(LPI_THRESH_MASK, x)
++#define  LPI_THRESH_SET(x)		FIELD_PREP(LPI_THRESH_MASK, x)
+ #define  LPI_MODE_EN			BIT(0)
+ 
+ #define MT7530_PMSR_P(x)		(0x3008 + (x) * 0x100)
diff --git a/target/linux/generic/pending-6.1/795-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/backport-6.1/790-65-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
index 7ce2d4c04e..7ce2d4c04e 100644
--- a/target/linux/generic/pending-6.1/795-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
+++ b/target/linux/generic/backport-6.1/790-65-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
diff --git a/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
new file mode 100644
index 0000000000..e9512421c2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
@@ -0,0 +1,57 @@
+From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:20 +0300
+Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
+ MT7530_NUM_PORTS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use priv->ds->num_ports on all for loops which configure the switch
+registers. In the future, the value of MT7530_NUM_PORTS will depend on
+priv->id. Therefore, this change prepares the subdriver for a simpler
+implementation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1418,7 +1418,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ 	mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
+ 		   G0_PORT_VID_DEF);
+ 
+-	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++	for (i = 0; i < priv->ds->num_ports; i++) {
+ 		if (dsa_is_user_port(ds, i) &&
+ 		    dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ 			all_user_ports_removed = false;
+@@ -2433,7 +2433,7 @@ mt7530_setup(struct dsa_switch *ds)
+ 	/* Enable and reset MIB counters */
+ 	mt7530_mib_reset(ds);
+ 
+-	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++	for (i = 0; i < priv->ds->num_ports; i++) {
+ 		/* Clear link settings and enable force mode to force link down
+ 		 * on all ports until they're enabled later.
+ 		 */
+@@ -2544,7 +2544,7 @@ mt7531_setup_common(struct dsa_switch *d
+ 	mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ 		     UNU_FFP_MASK);
+ 
+-	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++	for (i = 0; i < priv->ds->num_ports; i++) {
+ 		/* Clear link settings and enable force mode to force link down
+ 		 * on all ports until they're enabled later.
+ 		 */
+@@ -2631,7 +2631,7 @@ mt7531_setup(struct dsa_switch *ds)
+ 	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+ 
+ 	/* Force link down on all ports before internal reset */
+-	for (i = 0; i < MT7530_NUM_PORTS; i++)
++	for (i = 0; i < priv->ds->num_ports; i++)
+ 		mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+ 
+ 	/* Reset the switch through internal reset */
diff --git a/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
new file mode 100644
index 0000000000..3b3330bdce
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
@@ -0,0 +1,37 @@
+From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:21 +0300
+Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
+ mt7531_rgmii_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7531_rgmii_setup() function does not use the port variable, do not
+pass the variable to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2790,7 +2790,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+ 		mt7530_setup_port6(priv->ds, interface);
+ }
+ 
+-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++static void mt7531_rgmii_setup(struct mt7530_priv *priv,
+ 			       phy_interface_t interface,
+ 			       struct phy_device *phydev)
+ {
+@@ -2841,7 +2841,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+ 	if (phy_interface_mode_is_rgmii(interface)) {
+ 		dp = dsa_to_port(ds, port);
+ 		phydev = dp->slave->phydev;
+-		mt7531_rgmii_setup(priv, port, interface, phydev);
++		mt7531_rgmii_setup(priv, interface, phydev);
+ 	}
+ }
+ 
diff --git a/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
new file mode 100644
index 0000000000..6d28e5b5f9
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
@@ -0,0 +1,33 @@
+From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:22 +0300
+Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
+ better
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
+Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
+expose the MDIO bus of the switch. Replace the comment with a better
+explanation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2640,7 +2640,10 @@ mt7531_setup(struct dsa_switch *ds)
+ 	if (!priv->p5_sgmii) {
+ 		mt7531_pll_setup(priv);
+ 	} else {
+-		/* Let ds->slave_mii_bus be able to access external phy. */
++		/* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
++		 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
++		 * to expose the MDIO bus of the switch.
++		 */
+ 		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ 			   MT7531_EXT_P_MDC_11);
+ 		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
diff --git a/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch
new file mode 100644
index 0000000000..29079e03c5
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch
@@ -0,0 +1,45 @@
+From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sun, 28 Apr 2024 12:19:58 +0300
+Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is
+ being used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DSA initalises the ds->num_ports amount of ports in
+dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5
+won't be defined in the device tree. Because of this, the type member of
+the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED.
+The dsa_port_setup() function calls ds->ops->port_disable() when the port
+type is DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being
+used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1227,7 +1227,8 @@ mt7530_port_disable(struct dsa_switch *d
+ 	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ 		return;
+ 
+-	if (port == 5)
++	/* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */
++	if (port == 5 && priv->p5_mode == GMAC5)
+ 		mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ 	else if (port == 6)
+ 		mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
diff --git a/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch b/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch
new file mode 100644
index 0000000000..69bbb8e229
--- /dev/null
+++ b/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch
@@ -0,0 +1,45 @@
+From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 30 Apr 2024 08:01:33 +0300
+Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
+direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
+bus the switch listens on. The PHY muxing feature makes use of this.
+
+This is problematic as the PHY may be attached before the switch is
+initialised, in which case, the PHY will fail to be attached.
+
+Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
+of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of
+the switch on the device tree. Extend the check to detect PHY muxing when
+the PHY is defined on the MDIO bus of the switch on the device tree.
+
+When the PHY is described this way, the switch will be initialised first,
+then the switch MDIO bus will be registered. Only after these steps, the
+PHY will be attached.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2489,7 +2489,8 @@ mt7530_setup(struct dsa_switch *ds)
+ 			if (!phy_node)
+ 				continue;
+ 
+-			if (phy_node->parent == priv->dev->of_node->parent) {
++			if (phy_node->parent == priv->dev->of_node->parent ||
++			    phy_node->parent->parent == priv->dev->of_node) {
+ 				ret = of_get_phy_mode(mac_np, &interface);
+ 				if (ret && ret != -ENODEV) {
+ 					of_node_put(mac_np);
diff --git a/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch b/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch
new file mode 100644
index 0000000000..40e857de04
--- /dev/null
+++ b/target/linux/generic/backport-6.1/797-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch
@@ -0,0 +1,89 @@
+From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
+From: Greg Ungerer <gerg@kernel.org>
+Date: Fri, 24 Nov 2023 14:15:28 +1000
+Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
+
+As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
+be filled") Marvell 88e6350 switches fail to be probed:
+
+    ...
+    mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
+    mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
+    error creating PHYLINK: -22
+    mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
+    ...
+
+The problem stems from the use of mv88e6185_phylink_get_caps() to get
+the device capabilities. Create a new dedicated phylink_get_caps for the
+6351 family (which the 6350 is one of) to properly support their set of
+capabilities.
+
+According to chip.h the 6351 switch family includes the 6171, 6175, 6350
+and 6351 switches, so update each of these to use the correct
+phylink_get_caps.
+
+Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
+Signed-off-by: Greg Ungerer <gerg@kernel.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
+ 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
+ }
+ 
++static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
++				       struct phylink_config *config)
++{
++	unsigned long *supported = config->supported_interfaces;
++
++	/* Translate the default cmode */
++	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
++
++	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
++				   MAC_1000FD;
++}
++
+ static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
+ {
+ 	u16 reg, val;
+@@ -4489,7 +4501,7 @@ static const struct mv88e6xxx_ops mv88e6
+ 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ 	.stu_getnext = mv88e6352_g1_stu_getnext,
+ 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+-	.phylink_get_caps = mv88e6185_phylink_get_caps,
++	.phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+ 
+ static const struct mv88e6xxx_ops mv88e6172_ops = {
+@@ -4590,7 +4602,7 @@ static const struct mv88e6xxx_ops mv88e6
+ 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ 	.stu_getnext = mv88e6352_g1_stu_getnext,
+ 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+-	.phylink_get_caps = mv88e6185_phylink_get_caps,
++	.phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+ 
+ static const struct mv88e6xxx_ops mv88e6176_ops = {
+@@ -5247,7 +5259,7 @@ static const struct mv88e6xxx_ops mv88e6
+ 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ 	.stu_getnext = mv88e6352_g1_stu_getnext,
+ 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+-	.phylink_get_caps = mv88e6185_phylink_get_caps,
++	.phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+ 
+ static const struct mv88e6xxx_ops mv88e6351_ops = {
+@@ -5293,7 +5305,7 @@ static const struct mv88e6xxx_ops mv88e6
+ 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+ 	.avb_ops = &mv88e6352_avb_ops,
+ 	.ptp_ops = &mv88e6352_ptp_ops,
+-	.phylink_get_caps = mv88e6185_phylink_get_caps,
++	.phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+ 
+ static const struct mv88e6xxx_ops mv88e6352_ops = {
diff --git a/target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch b/target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch
new file mode 100644
index 0000000000..7f963b3cf6
--- /dev/null
+++ b/target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch
@@ -0,0 +1,1140 @@
+From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001
+From: Eric Woudstra <ericwouds@gmail.com>
+Date: Tue, 26 Mar 2024 17:23:05 +0100
+Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver
+
+Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports
+100/1000/2500 Mbps with auto negotiation only.
+
+The driver uses two firmware files, for which updated versions are added to
+linux-firmware already.
+
+Note: At phy-address + 8 there is another device on the mdio bus, that
+belongs to the EN881H. While the original driver writes to it, Airoha
+has confirmed this is not needed. Therefore, communication with this
+device is not included in this driver.
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/Makefile      |    1 +
+ drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1092 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -63,6 +63,11 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AIR_EN8811H_PHY
++	tristate "Airoha EN8811H 2.5 Gigabit PHY"
++	help
++	  Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1086 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <linux/wordpart.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID		0x03a2a411
++
++#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM	0x00000000
++#define AIR_FW_ADDR_DSP	0x00100000
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS		0x1d
++#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
++#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
++#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
++#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
++
++#define AIR_EXT_PAGE_ACCESS		0x1f
++#define   AIR_PHY_PAGE_STANDARD			0x0000
++#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
++
++/* MII Registers Page 4*/
++#define AIR_BPBUS_MODE			0x10
++#define   AIR_BPBUS_MODE_ADDR_FIXED		0x0000
++#define   AIR_BPBUS_MODE_ADDR_INCR		BIT(15)
++#define AIR_BPBUS_WR_ADDR_HIGH		0x11
++#define AIR_BPBUS_WR_ADDR_LOW		0x12
++#define AIR_BPBUS_WR_DATA_HIGH		0x13
++#define AIR_BPBUS_WR_DATA_LOW		0x14
++#define AIR_BPBUS_RD_ADDR_HIGH		0x15
++#define AIR_BPBUS_RD_ADDR_LOW		0x16
++#define AIR_BPBUS_RD_DATA_HIGH		0x17
++#define AIR_BPBUS_RD_DATA_LOW		0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS		0x8009
++#define   EN8811H_PHY_READY			0x02
++
++#define AIR_PHY_MCU_CMD_1		0x800c
++#define AIR_PHY_MCU_CMD_1_MODE1			0x0
++#define AIR_PHY_MCU_CMD_2		0x800d
++#define AIR_PHY_MCU_CMD_2_MODE1			0x0
++#define AIR_PHY_MCU_CMD_3		0x800e
++#define AIR_PHY_MCU_CMD_3_MODE1			0x1101
++#define AIR_PHY_MCU_CMD_3_DOCMD			0x1100
++#define AIR_PHY_MCU_CMD_4		0x800f
++#define AIR_PHY_MCU_CMD_4_MODE1			0x0002
++#define AIR_PHY_MCU_CMD_4_INTCLR		0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR			0x021
++#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
++#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
++#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
++#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
++
++#define AIR_PHY_LED_DUR_ON		0x022
++
++#define AIR_PHY_LED_DUR_BLINK		0x023
++
++#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
++#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
++#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
++#define   AIR_PHY_LED_ON_LINK100		BIT(1)
++#define   AIR_PHY_LED_ON_LINK10			BIT(2)
++#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
++#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
++#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
++#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
++#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
++#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
++#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
++
++#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
++#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
++#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
++#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
++#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
++#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
++#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
++#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
++#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
++#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
++#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
++#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
++#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA		0x3b30
++#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
++
++#define EN8811H_FW_VERSION		0x3b3c
++
++#define EN8811H_POLARITY		0xca0f8
++#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
++#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
++
++#define EN8811H_GPIO_OUTPUT		0xcf8b8
++#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1		0x0f0018
++#define   EN8811H_FW_CTRL_1_START		0x0
++#define   EN8811H_FW_CTRL_1_FINISH		0x1
++#define EN8811H_FW_CTRL_2		0x800000
++#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
++
++/* Led definitions */
++#define EN8811H_LED_COUNT	3
++
++/* Default LED setup:
++ * GPIO5 <-> LED0  On: Link detected, blink Rx/Tx
++ * GPIO4 <-> LED1  On: Link detected at 2500 or 1000 Mbps
++ * GPIO3 <-> LED2  On: Link detected at 2500 or  100 Mbps
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK)      | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_1000))
++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_100))
++
++struct led {
++	unsigned long rules;
++	unsigned long state;
++};
++
++struct en8811h_priv {
++	u32		firmware_version;
++	bool		mcu_needs_restart;
++	struct led	led[EN8811H_LED_COUNT];
++};
++
++enum {
++	AIR_PHY_LED_STATE_FORCE_ON,
++	AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++	AIR_PHY_LED_DUR_BLINK_32MS,
++	AIR_PHY_LED_DUR_BLINK_64MS,
++	AIR_PHY_LED_DUR_BLINK_128MS,
++	AIR_PHY_LED_DUR_BLINK_256MS,
++	AIR_PHY_LED_DUR_BLINK_512MS,
++	AIR_PHY_LED_DUR_BLINK_1024MS,
++};
++
++enum {
++	AIR_LED_DISABLE,
++	AIR_LED_ENABLE,
++};
++
++enum {
++	AIR_ACTIVE_LOW,
++	AIR_ACTIVE_HIGH,
++};
++
++enum {
++	AIR_LED_MODE_DISABLE,
++	AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT	1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS)
++
++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++					      BIT(TRIGGER_NETDEV_LINK)        |
++					      BIT(TRIGGER_NETDEV_LINK_10)     |
++					      BIT(TRIGGER_NETDEV_LINK_100)    |
++					      BIT(TRIGGER_NETDEV_LINK_1000)   |
++					      BIT(TRIGGER_NETDEV_LINK_2500)   |
++					      BIT(TRIGGER_NETDEV_RX)          |
++					      BIT(TRIGGER_NETDEV_TX);
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++				    u32 pbus_address, u32 pbus_data)
++{
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++			  upper_16_bits(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++			  lower_16_bits(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++				  u32 pbus_address, u32 pbus_data)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_write(phydev, pbus_address,
++					       pbus_data);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++				   u32 pbus_address, u32 *pbus_data)
++{
++	int pbus_data_low, pbus_data_high;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	*pbus_data = pbus_data_low | (pbus_data_high << 16);
++	return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++				 u32 pbus_address, u32 *pbus_data)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_modify(struct phy_device *phydev,
++				     u32 pbus_address, u32 mask, u32 set)
++{
++	int pbus_data_low, pbus_data_high;
++	u32 pbus_data_old, pbus_data_new;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	pbus_data_old = pbus_data_low | (pbus_data_high << 16);
++	pbus_data_new = (pbus_data_old & ~mask) | set;
++	if (pbus_data_new == pbus_data_old)
++		return 0;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++			  upper_16_bits(pbus_data_new));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++			  lower_16_bits(pbus_data_new));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_modify(struct phy_device *phydev,
++				   u32 pbus_address, u32 mask, u32 set)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
++						set);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++			   const struct firmware *fw)
++{
++	unsigned int offset;
++	int ret;
++	u16 val;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(address));
++	if (ret < 0)
++		return ret;
++
++	for (offset = 0; offset < fw->size; offset += 4) {
++		val = get_unaligned_le16(&fw->data[offset + 2]);
++		ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);
++		if (ret < 0)
++			return ret;
++
++		val = get_unaligned_le16(&fw->data[offset]);
++		ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++			 const struct firmware *fw)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_write_buf(phydev, address, fw);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_wait_mcu_ready(struct phy_device *phydev)
++{
++	int ret, reg_value;
++
++	/* Because of mdio-lock, may have to wait for multiple loads */
++	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					EN8811H_PHY_FW_STATUS, reg_value,
++					reg_value == EN8811H_PHY_READY,
++					20000, 7500000, true);
++	if (ret) {
++		phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw1, *fw2;
++	int ret;
++
++	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++	if (ret < 0)
++		return ret;
++
++	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++	if (ret < 0)
++		goto en8811h_load_firmware_rel1;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++				      EN8811H_FW_CTRL_2_LOADING,
++				      EN8811H_FW_CTRL_2_LOADING);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++				      EN8811H_FW_CTRL_2_LOADING, 0);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = en8811h_wait_mcu_ready(phydev);
++
++	air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
++			      &priv->firmware_version);
++	phydev_info(phydev, "MD32 firmware version: %08x\n",
++		    priv->firmware_version);
++
++en8811h_load_firmware_out:
++	release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++	release_firmware(fw1);
++
++	if (ret < 0)
++		phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++	return ret;
++}
++
++static int en8811h_restart_mcu(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		return ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		return ret;
++
++	return en8811h_wait_mcu_ready(phydev);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (on)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++				      AIR_PHY_LED_ON(index),
++				      AIR_PHY_LED_ON_MASK,
++				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++	return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++				bool blinking)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (blinking)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++				     AIR_PHY_LED_BLINK(index),
++				     blinking ?
++				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++	else
++		return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++			     unsigned long *delay_on,
++			     unsigned long *delay_off)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool blinking = false;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++		blinking = true;
++		*delay_on = 50;
++		*delay_off = 50;
++	}
++
++	err = air_hw_led_blink_set(phydev, index, blinking);
++	if (err)
++		return err;
++
++	/* led-blink set, so switch led-on off */
++	err = air_hw_led_on_set(phydev, index, false);
++	if (err)
++		return err;
++
++	/* hw-control is off*/
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++				  enum led_brightness value)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* led-on set, so switch led-blink off */
++	err = air_hw_led_blink_set(phydev, index, false);
++	if (err)
++		return err;
++
++	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++	if (err)
++		return err;
++
++	/* hw-control is off */
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	*rules = priv->led[index].rules;
++
++	return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u16 on = 0, blink = 0;
++	int ret;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	priv->led[index].rules = rules;
++
++	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++		on |= AIR_PHY_LED_ON_FDX;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK10;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK100;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK1000;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK2500;
++
++	if (rules & BIT(TRIGGER_NETDEV_RX)) {
++		blink |= AIR_PHY_LED_BLINK_10RX   |
++			 AIR_PHY_LED_BLINK_100RX  |
++			 AIR_PHY_LED_BLINK_1000RX |
++			 AIR_PHY_LED_BLINK_2500RX;
++	}
++
++	if (rules & BIT(TRIGGER_NETDEV_TX)) {
++		blink |= AIR_PHY_LED_BLINK_10TX   |
++			 AIR_PHY_LED_BLINK_100TX  |
++			 AIR_PHY_LED_BLINK_1000TX |
++			 AIR_PHY_LED_BLINK_2500TX;
++	}
++
++	if (blink || on) {
++		/* switch hw-control on, so led-on and led-blink are off */
++		clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++			  &priv->led[index].state);
++		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++			  &priv->led[index].state);
++	} else {
++		priv->led[index].rules = 0;
++	}
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_MASK, on);
++
++	if (ret < 0)
++		return ret;
++
++	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++			     blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++	int val = 0;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (state == AIR_LED_ENABLE)
++		val |= AIR_PHY_LED_ON_ENABLE;
++	else
++		val &= ~AIR_PHY_LED_ON_ENABLE;
++
++	if (pol == AIR_ACTIVE_HIGH)
++		val |= AIR_PHY_LED_ON_POLARITY;
++	else
++		val &= ~AIR_PHY_LED_ON_POLARITY;
++
++	err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_ENABLE |
++			     AIR_PHY_LED_ON_POLARITY, val);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int ret, i;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++			    dur);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++			    dur >> 1);
++	if (ret < 0)
++		return ret;
++
++	switch (mode) {
++	case AIR_LED_MODE_DISABLE:
++		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_MODE_MASK, 0);
++		if (ret < 0)
++			return ret;
++		break;
++	case AIR_LED_MODE_USER_DEFINE:
++		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_CLK_EN,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_CLK_EN);
++		if (ret < 0)
++			return ret;
++		break;
++	default:
++		phydev_err(phydev, "LED mode %d is not supported\n", mode);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < num; ++i) {
++		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++		if (ret < 0) {
++			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++			return ret;
++		}
++		air_led_hw_control_set(phydev, i, priv->led[i].rules);
++	}
++
++	return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~en8811h_led_trig)
++		return -EOPNOTSUPP;
++
++	return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv;
++	int ret;
++
++	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++	phydev->priv = priv;
++
++	ret = en8811h_load_firmware(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* mcu has just restarted after firmware load */
++	priv->mcu_needs_restart = false;
++
++	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_DISABLE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to disable leds: %d\n", ret);
++		return ret;
++	}
++
++	/* Configure led gpio pins as output */
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
++				      EN8811H_GPIO_OUTPUT_345,
++				      EN8811H_GPIO_OUTPUT_345);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	u32 pbus_value;
++	int ret;
++
++	/* If restart happened in .probe(), no need to restart now */
++	if (priv->mcu_needs_restart) {
++		ret = en8811h_restart_mcu(phydev);
++		if (ret < 0)
++			return ret;
++	} else {
++		/* Next calls to .config_init() mcu needs to restart */
++		priv->mcu_needs_restart = true;
++	}
++
++	/* Select mode 1, the only mode supported.
++	 * Configures the SerDes for 2500Base-X with rate adaptation
++	 */
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
++			    AIR_PHY_MCU_CMD_1_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
++			    AIR_PHY_MCU_CMD_2_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++			    AIR_PHY_MCU_CMD_3_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++			    AIR_PHY_MCU_CMD_4_MODE1);
++	if (ret < 0)
++		return ret;
++
++	/* Serdes polarity */
++	pbus_value = 0;
++	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
++	else
++		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++	else
++		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
++				      EN8811H_POLARITY_RX_REVERSE |
++				      EN8811H_POLARITY_TX_NORMAL, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_USER_DEFINE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++	linkmode_set_bit_array(phy_basic_ports_array,
++			       ARRAY_SIZE(phy_basic_ports_array),
++			       phydev->supported);
++
++	return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++				     phy_interface_t iface)
++{
++	return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	int ret;
++	u32 adv;
++
++	if (phydev->autoneg == AUTONEG_DISABLE) {
++		phydev_warn(phydev, "Disabling autoneg is not supported\n");
++		return -EINVAL;
++	}
++
++	adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
++	if (ret < 0)
++		return ret;
++	if (ret > 0)
++		changed = true;
++
++	return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u32 pbus_value;
++	int ret, val;
++
++	ret = genphy_update_link(phydev);
++	if (ret)
++		return ret;
++
++	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++	phydev->rate_matching = RATE_MATCH_PAUSE;
++
++	ret = genphy_read_master_slave(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_read_lpa(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Get link partner 2.5GBASE-T ability from vendor register */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++	if (ret < 0)
++		return ret;
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			 phydev->lp_advertising,
++			 pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++	if (phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	if (!phydev->link)
++		return 0;
++
++	/* Get real speed from vendor register */
++	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++	if (val < 0)
++		return val;
++	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++	case AIR_AUX_CTRL_STATUS_SPEED_2500:
++		phydev->speed = SPEED_2500;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_1000:
++		phydev->speed = SPEED_1000;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_100:
++		phydev->speed = SPEED_100;
++		break;
++	}
++
++	/* Firmware before version 24011202 has no vendor register 2P5G_LPA.
++	 * Assume link partner advertised it if connected at 2500Mbps.
++	 */
++	if (priv->firmware_version < 0x24011202) {
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 phydev->speed == SPEED_2500);
++	}
++
++	/* Only supports full duplex */
++	phydev->duplex = DUPLEX_FULL;
++
++	return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++			    AIR_PHY_MCU_CMD_3_DOCMD);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++			    AIR_PHY_MCU_CMD_4_INTCLR);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = en8811h_clear_intr(phydev);
++	if (ret < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++	.name			= "Airoha EN8811H",
++	.probe			= en8811h_probe,
++	.get_features		= en8811h_get_features,
++	.config_init		= en8811h_config_init,
++	.get_rate_matching	= en8811h_get_rate_matching,
++	.config_aneg		= en8811h_config_aneg,
++	.read_status		= en8811h_read_status,
++	.config_intr		= en8811h_clear_intr,
++	.handle_interrupt	= en8811h_handle_interrupt,
++	.led_hw_is_supported	= en8811h_led_hw_is_supported,
++	.read_page		= air_phy_read_page,
++	.write_page		= air_phy_write_page,
++	.led_blink_set		= air_led_blink_set,
++	.led_brightness_set	= air_led_brightness_set,
++	.led_hw_control_set	= air_led_hw_control_set,
++	.led_hw_control_get	= air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch b/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch
new file mode 100644
index 0000000000..1bd0eefe77
--- /dev/null
+++ b/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch
@@ -0,0 +1,47 @@
+From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Fri, 5 Apr 2024 13:08:59 +0300
+Subject: [PATCH] net: phy: air_en8811h: fix some error codes
+
+These error paths accidentally return "ret" which is zero/success
+instead of the correct error code.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/air_en8811h.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc
+ 
+ 	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ 	if (pbus_data_high < 0)
+-		return ret;
++		return pbus_data_high;
+ 
+ 	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ 	if (pbus_data_low < 0)
+-		return ret;
++		return pbus_data_low;
+ 
+ 	*pbus_data = pbus_data_low | (pbus_data_high << 16);
+ 	return 0;
+@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str
+ 
+ 	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ 	if (pbus_data_high < 0)
+-		return ret;
++		return pbus_data_high;
+ 
+ 	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ 	if (pbus_data_low < 0)
+-		return ret;
++		return pbus_data_low;
+ 
+ 	pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ 	pbus_data_new = (pbus_data_old & ~mask) | set;
diff --git a/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch b/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
index 58777cd280..8c062dc3b4 100644
--- a/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
+++ b/target/linux/generic/backport-6.1/807-v6.5-01-net-dsa-mv88e6xxx-pass-directly-chip-structure-to-mv.patch
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
  	} else {
  		if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
-@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
+@@ -851,7 +849,7 @@ static void mv88e6xxx_get_caps(struct ds
  	chip->info->ops->phylink_get_caps(chip, port, config);
  	mv88e6xxx_reg_unlock(chip);
  
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  config->supported_interfaces);
  		/* Internal ports with no phy-mode need GMII for PHYLIB */
-@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
+@@ -872,7 +870,7 @@ static void mv88e6xxx_mac_config(struct
  
  	mv88e6xxx_reg_lock(chip);
  
diff --git a/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch b/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch
index 12ea3ebda0..b50cb08454 100644
--- a/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch
+++ b/target/linux/generic/backport-6.1/807-v6.5-04-net-dsa-mv88e6xxx-fix-88E6393X-family-internal-phys-.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -5944,7 +5944,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5956,7 +5956,8 @@ static const struct mv88e6xxx_info mv88e
  		.name = "Marvell 88E6191X",
  		.num_databases = 4096,
  		.num_ports = 11,	/* 10 + Z80 */
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.max_vid = 8191,
  		.max_sid = 63,
  		.port_base_addr = 0x0,
-@@ -5967,7 +5968,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5979,7 +5980,8 @@ static const struct mv88e6xxx_info mv88e
  		.name = "Marvell 88E6193X",
  		.num_databases = 4096,
  		.num_ports = 11,	/* 10 + Z80 */
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.max_vid = 8191,
  		.max_sid = 63,
  		.port_base_addr = 0x0,
-@@ -6286,7 +6288,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -6298,7 +6300,8 @@ static const struct mv88e6xxx_info mv88e
  		.name = "Marvell 88E6393X",
  		.num_databases = 4096,
  		.num_ports = 11,	/* 10 + Z80 */
diff --git a/target/linux/generic/backport-6.1/807-v6.5-05-net-dsa-mv88e6xxx-pass-mv88e6xxx_chip-structure-to-p.patch b/target/linux/generic/backport-6.1/807-v6.5-05-net-dsa-mv88e6xxx-pass-mv88e6xxx_chip-structure-to-p.patch
index 72dfcee82c..d027bd3a8b 100644
--- a/target/linux/generic/backport-6.1/807-v6.5-05-net-dsa-mv88e6xxx-pass-mv88e6xxx_chip-structure-to-p.patch
+++ b/target/linux/generic/backport-6.1/807-v6.5-05-net-dsa-mv88e6xxx-pass-mv88e6xxx_chip-structure-to-p.patch
@@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3328,7 +3328,7 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3340,7 +3340,7 @@ static int mv88e6xxx_setup_port(struct m
  		caps = pl_config.mac_capabilities;
  
  		if (chip->info->ops->port_max_speed_mode)
diff --git a/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch b/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch
index dc6d5497f2..220fec68c3 100644
--- a/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch
+++ b/target/linux/generic/backport-6.1/807-v6.5-06-net-dsa-mv88e6xxx-enable-support-for-88E6361-switch.patch
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
+@@ -809,6 +809,8 @@ static void mv88e6393x_phylink_get_caps(
  	unsigned long *supported = config->supported_interfaces;
  	bool is_6191x =
  		chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
@@ -35,7 +35,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
  
-@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
+@@ -823,13 +825,17 @@ static void mv88e6393x_phylink_get_caps(
  		/* 6191X supports >1G modes only on port 10 */
  		if (!is_6191x || port == 10) {
  			__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
@@ -58,7 +58,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		}
  	}
  
-@@ -6231,6 +6237,32 @@ static const struct mv88e6xxx_info mv88e
+@@ -6243,6 +6249,32 @@ static const struct mv88e6xxx_info mv88e
  		.ptp_support = true,
  		.ops = &mv88e6352_ops,
  	},
diff --git a/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch b/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
index 2969462838..e8e73c1e5f 100644
--- a/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
+++ b/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
@@ -16,8 +16,8 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -72,9 +72,9 @@ config SFP
- comment "MII PHY device drivers"
+@@ -77,9 +77,9 @@ config AIR_EN8811H_PHY
+ 	  Currently supports the Airoha EN8811H PHY.
  
  config AMD_PHY
 -	tristate "AMD PHYs"
diff --git a/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch b/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch
new file mode 100644
index 0000000000..adc924c09a
--- /dev/null
+++ b/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch
@@ -0,0 +1,161 @@
+From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001
+From: Tanzir Hasan <tanzirh@google.com>
+Date: Tue, 26 Dec 2023 18:00:00 +0000
+Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h
+
+This patch creates wordpart.h and includes it in asm/word-at-a-time.h
+for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h
+because of REPEAT_BYTE. Moving this to another header and including it
+where necessary allows us to not include the bloated kernel.h. Making
+this implicit dependency on REPEAT_BYTE explicit allows for later
+improvements in the lib/string.c inclusion list.
+
+Suggested-by: Al Viro <viro@zeniv.linux.org.uk>
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Tanzir Hasan <tanzirh@google.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ arch/arm/include/asm/word-at-a-time.h     |  3 ++-
+ arch/arm64/include/asm/word-at-a-time.h   |  3 ++-
+ arch/powerpc/include/asm/word-at-a-time.h |  4 ++--
+ arch/riscv/include/asm/word-at-a-time.h   |  3 ++-
+ arch/s390/include/asm/word-at-a-time.h    |  3 ++-
+ arch/sh/include/asm/word-at-a-time.h      |  2 ++
+ arch/x86/include/asm/word-at-a-time.h     |  3 ++-
+ arch/x86/kvm/mmu/mmu.c                    |  1 +
+ fs/namei.c                                |  2 +-
+ include/asm-generic/word-at-a-time.h      |  3 ++-
+ include/linux/kernel.h                    |  8 --------
+ include/linux/wordpart.h                  | 13 +++++++++++++
+ 12 files changed, 31 insertions(+), 17 deletions(-)
+ create mode 100644 include/linux/wordpart.h
+
+--- a/arch/arm/include/asm/word-at-a-time.h
++++ b/arch/arm/include/asm/word-at-a-time.h
+@@ -8,7 +8,8 @@
+  * Little-endian word-at-a-time zero byte handling.
+  * Heavily based on the x86 algorithm.
+  */
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ struct word_at_a_time {
+ 	const unsigned long one_bits, high_bits;
+--- a/arch/arm64/include/asm/word-at-a-time.h
++++ b/arch/arm64/include/asm/word-at-a-time.h
+@@ -9,7 +9,8 @@
+ 
+ #ifndef __AARCH64EB__
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ struct word_at_a_time {
+ 	const unsigned long one_bits, high_bits;
+--- a/arch/powerpc/include/asm/word-at-a-time.h
++++ b/arch/powerpc/include/asm/word-at-a-time.h
+@@ -4,8 +4,8 @@
+ /*
+  * Word-at-a-time interfaces for PowerPC.
+  */
+-
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/asm-compat.h>
+ #include <asm/extable.h>
+ 
+--- a/arch/sh/include/asm/word-at-a-time.h
++++ b/arch/sh/include/asm/word-at-a-time.h
+@@ -5,6 +5,8 @@
+ #ifdef CONFIG_CPU_BIG_ENDIAN
+ # include <asm-generic/word-at-a-time.h>
+ #else
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ /*
+  * Little-endian version cribbed from x86.
+  */
+--- a/arch/x86/include/asm/word-at-a-time.h
++++ b/arch/x86/include/asm/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ 
+ /*
+  * This is largely generic for little-endian machines, but the
+--- a/arch/x86/kvm/mmu/mmu.c
++++ b/arch/x86/kvm/mmu/mmu.c
+@@ -47,6 +47,7 @@
+ #include <linux/kern_levels.h>
+ #include <linux/kstrtox.h>
+ #include <linux/kthread.h>
++#include <linux/wordpart.h>
+ 
+ #include <asm/page.h>
+ #include <asm/memtype.h>
+--- a/fs/namei.c
++++ b/fs/namei.c
+@@ -17,8 +17,8 @@
+ 
+ #include <linux/init.h>
+ #include <linux/export.h>
+-#include <linux/kernel.h>
+ #include <linux/slab.h>
++#include <linux/wordpart.h>
+ #include <linux/fs.h>
+ #include <linux/filelock.h>
+ #include <linux/namei.h>
+--- a/include/asm-generic/word-at-a-time.h
++++ b/include/asm-generic/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+ 
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/byteorder.h>
+ 
+ #ifdef __BIG_ENDIAN
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -38,14 +38,6 @@
+ 
+ #define STACK_MAGIC	0xdeadbeef
+ 
+-/**
+- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+- * @x: value to repeat
+- *
+- * NOTE: @x is not checked for > 0xff; larger values produce odd results.
+- */
+-#define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
+-
+ /* generic data direction definitions */
+ #define READ			0
+ #define WRITE			1
+--- /dev/null
++++ b/include/linux/wordpart.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _LINUX_WORDPART_H
++#define _LINUX_WORDPART_H
++/**
++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
++ * @x: value to repeat
++ *
++ * NOTE: @x is not checked for > 0xff; larger values produce odd results.
++ */
++#define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
++
++#endif // _LINUX_WORDPART_H
diff --git a/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch b/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch
new file mode 100644
index 0000000000..b9c40e6206
--- /dev/null
+++ b/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch
@@ -0,0 +1,107 @@
+From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 14 Feb 2024 19:26:32 +0200
+Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to
+ wordpart.h
+
+The wordpart.h header is collecting APIs related to the handling
+parts of the word (usually in byte granularity). The upper_*_bits()
+and lower_*_bits() are good candidates to be moved to there.
+
+This helps to clean up header dependency hell with regard to kernel.h
+as the latter gathers completely unrelated stuff together and slows
+down compilation (especially when it's included into other header).
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com
+Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ include/linux/kernel.h   | 30 ++----------------------------
+ include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+), 28 deletions(-)
+
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -32,6 +32,8 @@
+ #include <linux/sprintf.h>
+ #include <linux/static_call_types.h>
+ #include <linux/instruction_pointer.h>
++#include <linux/wordpart.h>
++
+ #include <asm/byteorder.h>
+ 
+ #include <uapi/linux/kernel.h>
+@@ -57,34 +59,6 @@
+ }					\
+ )
+ 
+-/**
+- * upper_32_bits - return bits 32-63 of a number
+- * @n: the number we're accessing
+- *
+- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+- * the "right shift count >= width of type" warning when that quantity is
+- * 32-bits.
+- */
+-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+-
+-/**
+- * lower_32_bits - return bits 0-31 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
+-
+-/**
+- * upper_16_bits - return bits 16-31 of a number
+- * @n: the number we're accessing
+- */
+-#define upper_16_bits(n) ((u16)((n) >> 16))
+-
+-/**
+- * lower_16_bits - return bits 0-15 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_16_bits(n) ((u16)((n) & 0xffff))
+-
+ struct completion;
+ struct user;
+ 
+--- a/include/linux/wordpart.h
++++ b/include/linux/wordpart.h
+@@ -2,6 +2,35 @@
+ 
+ #ifndef _LINUX_WORDPART_H
+ #define _LINUX_WORDPART_H
++
++/**
++ * upper_32_bits - return bits 32-63 of a number
++ * @n: the number we're accessing
++ *
++ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
++ * the "right shift count >= width of type" warning when that quantity is
++ * 32-bits.
++ */
++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
++
++/**
++ * lower_32_bits - return bits 0-31 of a number
++ * @n: the number we're accessing
++ */
++#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
++
++/**
++ * upper_16_bits - return bits 16-31 of a number
++ * @n: the number we're accessing
++ */
++#define upper_16_bits(n) ((u16)((n) >> 16))
++
++/**
++ * lower_16_bits - return bits 0-15 of a number
++ * @n: the number we're accessing
++ */
++#define lower_16_bits(n) ((u16)((n) & 0xffff))
++
+ /**
+  * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+  * @x: value to repeat
diff --git a/target/linux/generic/backport-6.6/701-v6.8-net-sfp-bus-fix-SFP-mode-detect-from-bitrate.patch b/target/linux/generic/backport-6.6/701-v6.8-net-sfp-bus-fix-SFP-mode-detect-from-bitrate.patch
new file mode 100644
index 0000000000..83145012b9
--- /dev/null
+++ b/target/linux/generic/backport-6.6/701-v6.8-net-sfp-bus-fix-SFP-mode-detect-from-bitrate.patch
@@ -0,0 +1,46 @@
+From 97eb5d51b4a584a60e5d096bdb6b33edc9f50d8d Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 15 Jan 2024 12:43:38 +0000
+Subject: [PATCH] net: sfp-bus: fix SFP mode detect from bitrate
+
+The referenced commit moved the setting of the Autoneg and pause bits
+early in sfp_parse_support(). However, we check whether the modes are
+empty before using the bitrate to set some modes. Setting these bits
+so early causes that test to always be false, preventing this working,
+and thus some modules that used to work no longer do.
+
+Move them just before the call to the quirk.
+
+Fixes: 8110633db49d ("net: sfp-bus: allow SFP quirks to override Autoneg and pause bits")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Link: https://lore.kernel.org/r/E1rPMJW-001Ahf-L0@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/sfp-bus.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -151,10 +151,6 @@ void sfp_parse_support(struct sfp_bus *b
+ 	unsigned int br_min, br_nom, br_max;
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = { 0, };
+ 
+-	phylink_set(modes, Autoneg);
+-	phylink_set(modes, Pause);
+-	phylink_set(modes, Asym_Pause);
+-
+ 	/* Decode the bitrate information to MBd */
+ 	br_min = br_nom = br_max = 0;
+ 	if (id->base.br_nominal) {
+@@ -339,6 +335,10 @@ void sfp_parse_support(struct sfp_bus *b
+ 		}
+ 	}
+ 
++	phylink_set(modes, Autoneg);
++	phylink_set(modes, Pause);
++	phylink_set(modes, Asym_Pause);
++
+ 	if (bus->sfp_quirk && bus->sfp_quirk->modes)
+ 		bus->sfp_quirk->modes(id, modes, interfaces);
+ 
diff --git a/target/linux/generic/backport-6.6/740-v6.10-net-stmmac-dwmac-ipq806x-account-for-rgmii-txid-rxid.patch b/target/linux/generic/backport-6.6/740-v6.10-net-stmmac-dwmac-ipq806x-account-for-rgmii-txid-rxid.patch
new file mode 100644
index 0000000000..ab8e9ffab5
--- /dev/null
+++ b/target/linux/generic/backport-6.6/740-v6.10-net-stmmac-dwmac-ipq806x-account-for-rgmii-txid-rxid.patch
@@ -0,0 +1,68 @@
+From abb45a2477f533cd4aab3085defdff131e2e8c4f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 6 May 2024 14:32:46 +0200
+Subject: [PATCH] net: stmmac: dwmac-ipq806x: account for rgmii-txid/rxid/id
+ phy-mode
+
+Currently the ipq806x dwmac driver is almost always used attached to the
+CPU port of a switch and phy-mode was always set to "rgmii" or "sgmii".
+
+Some device came up with a special configuration where the PHY is
+directly attached to the GMAC port and in those case phy-mode needs to
+be set to "rgmii-id" to make the PHY correctly work and receive packets.
+
+Since the driver supports only "rgmii" and "sgmii" mode, when "rgmii-id"
+(or variants) mode is set, the mode is rejected and probe fails.
+
+Add support also for these phy-modes to correctly setup PHYs that requires
+delay applied to tx/rx.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
+@@ -171,6 +171,9 @@ static int ipq806x_gmac_set_speed(struct
+ 
+ 	switch (gmac->phy_mode) {
+ 	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
+ 		div = get_clk_div_rgmii(gmac, speed);
+ 		clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
+ 			   NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
+@@ -412,6 +415,9 @@ static int ipq806x_gmac_probe(struct pla
+ 	val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
+ 	switch (gmac->phy_mode) {
+ 	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
+ 		val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
+ 		break;
+ 	case PHY_INTERFACE_MODE_SGMII:
+@@ -427,6 +433,9 @@ static int ipq806x_gmac_probe(struct pla
+ 	val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
+ 	switch (gmac->phy_mode) {
+ 	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
+ 		val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
+ 			NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
+ 		break;
+@@ -444,6 +453,9 @@ static int ipq806x_gmac_probe(struct pla
+ 	val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
+ 	switch (gmac->phy_mode) {
+ 	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
+ 		val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
+ 			NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
+ 		break;
diff --git a/target/linux/generic/backport-6.6/751-01-STABLE-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/generic/backport-6.6/751-01-STABLE-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
new file mode 100644
index 0000000000..22aceecc53
--- /dev/null
+++ b/target/linux/generic/backport-6.6/751-01-STABLE-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
@@ -0,0 +1,605 @@
+From 5d0fad48d2dec175ecb999974b94203c577973ef Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Wed, 8 May 2024 11:43:34 +0100
+Subject: [PATCH] net: ethernet: mediatek: split tx and rx fields in
+ mtk_soc_data struct
+
+Split tx and rx fields in mtk_soc_data struct. This is a preliminary
+patch to roll back to ADMAv1 for MT7986 and MT7981 SoC in order to fix a
+hw hang if the device receives a corrupted packet when using ADMAv2.0.
+
+Fixes: 197c9e9b17b1 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
+Link: https://lore.kernel.org/r/70a799b1f060ec2f57883e88ccb420ac0fb0abb5.1715164770.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  29 +--
+ 2 files changed, 139 insertions(+), 100 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1138,7 +1138,7 @@ static int mtk_init_fq_dma(struct mtk_et
+ 		eth->scratch_ring = eth->sram_base;
+ 	else
+ 		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
+-						       cnt * soc->txrx.txd_size,
++						       cnt * soc->tx.desc_size,
+ 						       &eth->phy_scratch_ring,
+ 						       GFP_KERNEL);
+ 	if (unlikely(!eth->scratch_ring))
+@@ -1154,16 +1154,16 @@ static int mtk_init_fq_dma(struct mtk_et
+ 	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
+ 		return -ENOMEM;
+ 
+-	phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
++	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
+ 
+ 	for (i = 0; i < cnt; i++) {
+ 		struct mtk_tx_dma_v2 *txd;
+ 
+-		txd = eth->scratch_ring + i * soc->txrx.txd_size;
++		txd = eth->scratch_ring + i * soc->tx.desc_size;
+ 		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
+ 		if (i < cnt - 1)
+ 			txd->txd2 = eth->phy_scratch_ring +
+-				    (i + 1) * soc->txrx.txd_size;
++				    (i + 1) * soc->tx.desc_size;
+ 
+ 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ 		txd->txd4 = 0;
+@@ -1412,7 +1412,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ 	if (itxd == ring->last_free)
+ 		return -ENOMEM;
+ 
+-	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
++	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
+ 	memset(itx_buf, 0, sizeof(*itx_buf));
+ 
+ 	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
+@@ -1453,7 +1453,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ 
+ 			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
+ 			txd_info.size = min_t(unsigned int, frag_size,
+-					      soc->txrx.dma_max_len);
++					      soc->tx.dma_max_len);
+ 			txd_info.qid = queue;
+ 			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
+ 					!(frag_size - txd_info.size);
+@@ -1466,7 +1466,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ 			mtk_tx_set_dma_desc(dev, txd, &txd_info);
+ 
+ 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
+-						    soc->txrx.txd_size);
++						    soc->tx.desc_size);
+ 			if (new_desc)
+ 				memset(tx_buf, 0, sizeof(*tx_buf));
+ 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
+@@ -1509,7 +1509,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ 	} else {
+ 		int next_idx;
+ 
+-		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
++		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
+ 					 ring->dma_size);
+ 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
+ 	}
+@@ -1518,7 +1518,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ 
+ err_dma:
+ 	do {
+-		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
++		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
+ 
+ 		/* unmap dma */
+ 		mtk_tx_unmap(eth, tx_buf, NULL, false);
+@@ -1543,7 +1543,7 @@ static int mtk_cal_txd_req(struct mtk_et
+ 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ 			frag = &skb_shinfo(skb)->frags[i];
+ 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
+-					       eth->soc->txrx.dma_max_len);
++					       eth->soc->tx.dma_max_len);
+ 		}
+ 	} else {
+ 		nfrags += skb_shinfo(skb)->nr_frags;
+@@ -1650,7 +1650,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
+ 
+ 		ring = &eth->rx_ring[i];
+ 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
+-		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
++		rxd = ring->dma + idx * eth->soc->rx.desc_size;
+ 		if (rxd->rxd2 & RX_DMA_DONE) {
+ 			ring->calc_idx_update = true;
+ 			return ring;
+@@ -1818,7 +1818,7 @@ static int mtk_xdp_submit_frame(struct m
+ 	}
+ 	htxd = txd;
+ 
+-	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
++	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
+ 	memset(tx_buf, 0, sizeof(*tx_buf));
+ 	htx_buf = tx_buf;
+ 
+@@ -1837,7 +1837,7 @@ static int mtk_xdp_submit_frame(struct m
+ 				goto unmap;
+ 
+ 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
+-						    soc->txrx.txd_size);
++						    soc->tx.desc_size);
+ 			memset(tx_buf, 0, sizeof(*tx_buf));
+ 			n_desc++;
+ 		}
+@@ -1875,7 +1875,7 @@ static int mtk_xdp_submit_frame(struct m
+ 	} else {
+ 		int idx;
+ 
+-		idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
++		idx = txd_to_idx(ring, txd, soc->tx.desc_size);
+ 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
+ 			MT7628_TX_CTX_IDX0);
+ 	}
+@@ -1886,7 +1886,7 @@ static int mtk_xdp_submit_frame(struct m
+ 
+ unmap:
+ 	while (htxd != txd) {
+-		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
++		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
+ 		mtk_tx_unmap(eth, tx_buf, NULL, false);
+ 
+ 		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+@@ -2017,7 +2017,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			goto rx_done;
+ 
+ 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
+-		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
++		rxd = ring->dma + idx * eth->soc->rx.desc_size;
+ 		data = ring->data[idx];
+ 
+ 		if (!mtk_rx_get_desc(eth, &trxd, rxd))
+@@ -2152,7 +2152,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			rxdcsum = &trxd.rxd4;
+ 		}
+ 
+-		if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
++		if (*rxdcsum & eth->soc->rx.dma_l4_valid)
+ 			skb->ip_summed = CHECKSUM_UNNECESSARY;
+ 		else
+ 			skb_checksum_none_assert(skb);
+@@ -2276,7 +2276,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 			break;
+ 
+ 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
+-					    eth->soc->txrx.txd_size);
++					    eth->soc->tx.desc_size);
+ 		if (!tx_buf->data)
+ 			break;
+ 
+@@ -2327,7 +2327,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
+ 		}
+ 		mtk_tx_unmap(eth, tx_buf, &bq, true);
+ 
+-		desc = ring->dma + cpu * eth->soc->txrx.txd_size;
++		desc = ring->dma + cpu * eth->soc->tx.desc_size;
+ 		ring->last_free = desc;
+ 		atomic_inc(&ring->free_count);
+ 
+@@ -2417,7 +2417,7 @@ static int mtk_napi_rx(struct napi_struc
+ 	do {
+ 		int rx_done;
+ 
+-		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
++		mtk_w32(eth, eth->soc->rx.irq_done_mask,
+ 			reg_map->pdma.irq_status);
+ 		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
+ 		rx_done_total += rx_done;
+@@ -2433,10 +2433,10 @@ static int mtk_napi_rx(struct napi_struc
+ 			return budget;
+ 
+ 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
+-		 eth->soc->txrx.rx_irq_done_mask);
++		 eth->soc->rx.irq_done_mask);
+ 
+ 	if (napi_complete_done(napi, rx_done_total))
+-		mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
++		mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
+ 
+ 	return rx_done_total;
+ }
+@@ -2445,7 +2445,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ {
+ 	const struct mtk_soc_data *soc = eth->soc;
+ 	struct mtk_tx_ring *ring = &eth->tx_ring;
+-	int i, sz = soc->txrx.txd_size;
++	int i, sz = soc->tx.desc_size;
+ 	struct mtk_tx_dma_v2 *txd;
+ 	int ring_size;
+ 	u32 ofs, val;
+@@ -2568,14 +2568,14 @@ static void mtk_tx_clean(struct mtk_eth
+ 	}
+ 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+-				  ring->dma_size * soc->txrx.txd_size,
++				  ring->dma_size * soc->tx.desc_size,
+ 				  ring->dma, ring->phys);
+ 		ring->dma = NULL;
+ 	}
+ 
+ 	if (ring->dma_pdma) {
+ 		dma_free_coherent(eth->dma_dev,
+-				  ring->dma_size * soc->txrx.txd_size,
++				  ring->dma_size * soc->tx.desc_size,
+ 				  ring->dma_pdma, ring->phys_pdma);
+ 		ring->dma_pdma = NULL;
+ 	}
+@@ -2630,15 +2630,15 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
+ 	    rx_flag != MTK_RX_FLAGS_NORMAL) {
+ 		ring->dma = dma_alloc_coherent(eth->dma_dev,
+-					       rx_dma_size * eth->soc->txrx.rxd_size,
+-					       &ring->phys, GFP_KERNEL);
++				rx_dma_size * eth->soc->rx.desc_size,
++				&ring->phys, GFP_KERNEL);
+ 	} else {
+ 		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
+ 
+ 		ring->dma = tx_ring->dma + tx_ring_size *
+-			    eth->soc->txrx.txd_size * (ring_no + 1);
++			    eth->soc->tx.desc_size * (ring_no + 1);
+ 		ring->phys = tx_ring->phys + tx_ring_size *
+-			     eth->soc->txrx.txd_size * (ring_no + 1);
++			     eth->soc->tx.desc_size * (ring_no + 1);
+ 	}
+ 
+ 	if (!ring->dma)
+@@ -2649,7 +2649,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 		dma_addr_t dma_addr;
+ 		void *data;
+ 
+-		rxd = ring->dma + i * eth->soc->txrx.rxd_size;
++		rxd = ring->dma + i * eth->soc->rx.desc_size;
+ 		if (ring->page_pool) {
+ 			data = mtk_page_pool_get_buff(ring->page_pool,
+ 						      &dma_addr, GFP_KERNEL);
+@@ -2740,7 +2740,7 @@ static void mtk_rx_clean(struct mtk_eth
+ 			if (!ring->data[i])
+ 				continue;
+ 
+-			rxd = ring->dma + i * eth->soc->txrx.rxd_size;
++			rxd = ring->dma + i * eth->soc->rx.desc_size;
+ 			if (!rxd->rxd1)
+ 				continue;
+ 
+@@ -2757,7 +2757,7 @@ static void mtk_rx_clean(struct mtk_eth
+ 
+ 	if (!in_sram && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+-				  ring->dma_size * eth->soc->txrx.rxd_size,
++				  ring->dma_size * eth->soc->rx.desc_size,
+ 				  ring->dma, ring->phys);
+ 		ring->dma = NULL;
+ 	}
+@@ -3120,7 +3120,7 @@ static void mtk_dma_free(struct mtk_eth
+ 			netdev_reset_queue(eth->netdev[i]);
+ 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
+ 		dma_free_coherent(eth->dma_dev,
+-				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
++				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
+ 				  eth->scratch_ring, eth->phy_scratch_ring);
+ 		eth->scratch_ring = NULL;
+ 		eth->phy_scratch_ring = 0;
+@@ -3170,7 +3170,7 @@ static irqreturn_t mtk_handle_irq_rx(int
+ 
+ 	eth->rx_events++;
+ 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
+-		mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++		mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ 		__napi_schedule(&eth->rx_napi);
+ 	}
+ 
+@@ -3196,9 +3196,9 @@ static irqreturn_t mtk_handle_irq(int ir
+ 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+ 
+ 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
+-	    eth->soc->txrx.rx_irq_done_mask) {
++	    eth->soc->rx.irq_done_mask) {
+ 		if (mtk_r32(eth, reg_map->pdma.irq_status) &
+-		    eth->soc->txrx.rx_irq_done_mask)
++		    eth->soc->rx.irq_done_mask)
+ 			mtk_handle_irq_rx(irq, _eth);
+ 	}
+ 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
+@@ -3216,10 +3216,10 @@ static void mtk_poll_controller(struct n
+ 	struct mtk_eth *eth = mac->hw;
+ 
+ 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+-	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ 	mtk_handle_irq_rx(eth->irq[2], dev);
+ 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+-	mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
++	mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
+ }
+ #endif
+ 
+@@ -3383,7 +3383,7 @@ static int mtk_open(struct net_device *d
+ 		napi_enable(&eth->tx_napi);
+ 		napi_enable(&eth->rx_napi);
+ 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+-		mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
++		mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
+ 		refcount_set(&eth->dma_refcnt, 1);
+ 	}
+ 	else
+@@ -3467,7 +3467,7 @@ static int mtk_stop(struct net_device *d
+ 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
+ 
+ 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+-	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ 	napi_disable(&eth->tx_napi);
+ 	napi_disable(&eth->rx_napi);
+ 
+@@ -3943,9 +3943,9 @@ static int mtk_hw_init(struct mtk_eth *e
+ 
+ 	/* FE int grouping */
+ 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
+-	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
++	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
+ 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
+-	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
++	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
+ 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+ 	if (mtk_is_netsys_v3_or_greater(eth)) {
+@@ -5037,11 +5037,15 @@ static const struct mtk_soc_data mt2701_
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
+ 	.version = 1,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+@@ -5057,11 +5061,15 @@ static const struct mtk_soc_data mt7621_
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+@@ -5079,11 +5087,15 @@ static const struct mtk_soc_data mt7622_
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+@@ -5100,11 +5112,15 @@ static const struct mtk_soc_data mt7623_
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.disable_pll_modes = true,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+@@ -5119,11 +5135,15 @@ static const struct mtk_soc_data mt7629_
+ 	.required_pctl = false,
+ 	.has_accounting = true,
+ 	.version = 1,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+@@ -5141,11 +5161,15 @@ static const struct mtk_soc_data mt7981_
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma_v2),
+-		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma_v2),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma_v2),
++		.irq_done_mask = MTK_RX_DONE_INT_V2,
++		.dma_l4_valid = RX_DMA_L4_VALID_V2,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ 		.dma_len_offset = 8,
+ 	},
+@@ -5163,11 +5187,15 @@ static const struct mtk_soc_data mt7986_
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma_v2),
+-		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma_v2),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma_v2),
++		.irq_done_mask = MTK_RX_DONE_INT_V2,
++		.dma_l4_valid = RX_DMA_L4_VALID_V2,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ 		.dma_len_offset = 8,
+ 	},
+@@ -5185,11 +5213,15 @@ static const struct mtk_soc_data mt7988_
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma_v2),
+-		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma_v2),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma_v2),
++		.irq_done_mask = MTK_RX_DONE_INT_V2,
++		.dma_l4_valid = RX_DMA_L4_VALID_V2,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ 		.dma_len_offset = 8,
+ 	},
+@@ -5202,11 +5234,15 @@ static const struct mtk_soc_data rt5350_
+ 	.required_clks = MT7628_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.version = 1,
+-	.txrx = {
+-		.txd_size = sizeof(struct mtk_tx_dma),
+-		.rxd_size = sizeof(struct mtk_rx_dma),
+-		.rx_irq_done_mask = MTK_RX_DONE_INT,
+-		.rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
++	.tx = {
++		.desc_size = sizeof(struct mtk_tx_dma),
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
++	},
++	.rx = {
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
++		.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
+ 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
+ 		.dma_len_offset = 16,
+ 	},
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -327,8 +327,8 @@
+ /* QDMA descriptor txd3 */
+ #define TX_DMA_OWNER_CPU	BIT(31)
+ #define TX_DMA_LS0		BIT(30)
+-#define TX_DMA_PLEN0(x)		(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+-#define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
++#define TX_DMA_PLEN0(x)		(((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
++#define TX_DMA_PLEN1(x)		((x) & eth->soc->tx.dma_max_len)
+ #define TX_DMA_SWC		BIT(14)
+ #define TX_DMA_PQID		GENMASK(3, 0)
+ #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
+@@ -348,8 +348,8 @@
+ /* QDMA descriptor rxd2 */
+ #define RX_DMA_DONE		BIT(31)
+ #define RX_DMA_LSO		BIT(30)
+-#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+-#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
++#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
++#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
+ #define RX_DMA_VTAG		BIT(15)
+ #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
+ #if IS_ENABLED(CONFIG_64BIT)
+@@ -1153,10 +1153,9 @@ struct mtk_reg_map {
+  * @foe_entry_size		Foe table entry size.
+  * @has_accounting		Bool indicating support for accounting of
+  *				offloaded flows.
+- * @txd_size			Tx DMA descriptor size.
+- * @rxd_size			Rx DMA descriptor size.
+- * @rx_irq_done_mask		Rx irq done register mask.
+- * @rx_dma_l4_valid		Rx DMA valid register mask.
++ * @desc_size			Tx/Rx DMA descriptor size.
++ * @irq_done_mask		Rx irq done register mask.
++ * @dma_l4_valid		Rx DMA valid register mask.
+  * @dma_max_len			Max DMA tx/rx buffer length.
+  * @dma_len_offset		Tx/Rx DMA length field offset.
+  */
+@@ -1174,13 +1173,17 @@ struct mtk_soc_data {
+ 	bool		has_accounting;
+ 	bool		disable_pll_modes;
+ 	struct {
+-		u32	txd_size;
+-		u32	rxd_size;
+-		u32	rx_irq_done_mask;
+-		u32	rx_dma_l4_valid;
++		u32	desc_size;
+ 		u32	dma_max_len;
+ 		u32	dma_len_offset;
+-	} txrx;
++	} tx;
++	struct {
++		u32	desc_size;
++		u32	irq_done_mask;
++		u32	dma_l4_valid;
++		u32	dma_max_len;
++		u32	dma_len_offset;
++	} rx;
+ };
+ 
+ #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
diff --git a/target/linux/generic/backport-6.6/751-02-STABLE-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/generic/backport-6.6/751-02-STABLE-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
new file mode 100644
index 0000000000..e71ff0923c
--- /dev/null
+++ b/target/linux/generic/backport-6.6/751-02-STABLE-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
@@ -0,0 +1,128 @@
+From 4d572e867bdb372bb4add39a0fa495c6a9c9a8da Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 8 May 2024 11:43:56 +0100
+Subject: [PATCH] net: ethernet: mediatek: use ADMAv1 instead of ADMAv2.0 on
+ MT7981 and MT7986
+
+ADMAv2.0 is plagued by RX hangs which can't easily detected and happen upon
+receival of a corrupted Ethernet frame.
+
+Use ADMAv1 instead which is also still present and usable, and doesn't
+suffer from that problem.
+
+Fixes: 197c9e9b17b1 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/57cef74bbd0c243366ad1ff4221e3f72f437ec80.1715164770.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
+ 1 file changed, 23 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
+ 	.tx_irq_mask		= 0x461c,
+ 	.tx_irq_status		= 0x4618,
+ 	.pdma = {
+-		.rx_ptr		= 0x6100,
+-		.rx_cnt_cfg	= 0x6104,
+-		.pcrx_ptr	= 0x6108,
+-		.glo_cfg	= 0x6204,
+-		.rst_idx	= 0x6208,
+-		.delay_irq	= 0x620c,
+-		.irq_status	= 0x6220,
+-		.irq_mask	= 0x6228,
+-		.adma_rx_dbg0	= 0x6238,
+-		.int_grp	= 0x6250,
++		.rx_ptr		= 0x4100,
++		.rx_cnt_cfg	= 0x4104,
++		.pcrx_ptr	= 0x4108,
++		.glo_cfg	= 0x4204,
++		.rst_idx	= 0x4208,
++		.delay_irq	= 0x420c,
++		.irq_status	= 0x4220,
++		.irq_mask	= 0x4228,
++		.adma_rx_dbg0	= 0x4238,
++		.int_grp	= 0x4250,
+ 	},
+ 	.qdma = {
+ 		.qtx_cfg	= 0x4400,
+@@ -1106,7 +1106,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+ 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v3_or_greater(eth)) {
+ 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ 	}
+@@ -2024,7 +2024,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (mtk_is_netsys_v2_or_greater(eth)) {
++		if (mtk_is_netsys_v3_or_greater(eth)) {
+ 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
+ 
+ 			switch (val) {
+@@ -2136,7 +2136,7 @@ static int mtk_poll_rx(struct napi_struc
+ 		skb->dev = netdev;
+ 		bytes += skb->len;
+ 
+-		if (mtk_is_netsys_v2_or_greater(eth)) {
++		if (mtk_is_netsys_v3_or_greater(eth)) {
+ 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
+ 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
+ 			if (hash != MTK_RXD5_FOE_ENTRY)
+@@ -2686,7 +2686,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 
+ 		rxd->rxd3 = 0;
+ 		rxd->rxd4 = 0;
+-		if (mtk_is_netsys_v2_or_greater(eth)) {
++		if (mtk_is_netsys_v3_or_greater(eth)) {
+ 			rxd->rxd5 = 0;
+ 			rxd->rxd6 = 0;
+ 			rxd->rxd7 = 0;
+@@ -3889,7 +3889,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	else
+ 		mtk_hw_reset(eth);
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v3_or_greater(eth)) {
+ 		/* Set FE to PDMAv2 if necessary */
+ 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
+@@ -5167,11 +5167,11 @@ static const struct mtk_soc_data mt7981_
+ 		.dma_len_offset = 8,
+ 	},
+ 	.rx = {
+-		.desc_size = sizeof(struct mtk_rx_dma_v2),
+-		.irq_done_mask = MTK_RX_DONE_INT_V2,
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
+ 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
+-		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+-		.dma_len_offset = 8,
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
+ 	},
+ };
+ 
+@@ -5193,11 +5193,11 @@ static const struct mtk_soc_data mt7986_
+ 		.dma_len_offset = 8,
+ 	},
+ 	.rx = {
+-		.desc_size = sizeof(struct mtk_rx_dma_v2),
+-		.irq_done_mask = MTK_RX_DONE_INT_V2,
++		.desc_size = sizeof(struct mtk_rx_dma),
++		.irq_done_mask = MTK_RX_DONE_INT,
+ 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
+-		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+-		.dma_len_offset = 8,
++		.dma_max_len = MTK_TX_DMA_BUF_LEN,
++		.dma_len_offset = 16,
+ 	},
+ };
+ 
diff --git a/target/linux/generic/backport-6.6/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch b/target/linux/generic/backport-6.6/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch
index d6ef40cd5b..b9d3582a73 100644
--- a/target/linux/generic/backport-6.6/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch
+++ b/target/linux/generic/backport-6.6/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch
@@ -14,7 +14,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1713,19 +1713,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
+@@ -1709,19 +1709,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
  int mtk_wed_flow_add(int index)
  {
  	struct mtk_wed_hw *hw = hw_list[index];
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		goto out;
  	}
  
-@@ -1744,14 +1745,15 @@ void mtk_wed_flow_remove(int index)
+@@ -1740,14 +1741,15 @@ void mtk_wed_flow_remove(int index)
  {
  	struct mtk_wed_hw *hw = hw_list[index];
  
diff --git a/target/linux/generic/backport-6.6/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch b/target/linux/generic/backport-6.6/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch
index af4600a986..6d1d9a4069 100644
--- a/target/linux/generic/backport-6.6/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch
+++ b/target/linux/generic/backport-6.6/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch
@@ -52,15 +52,15 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wdma_clr(dev, MTK_WDMA_GLO_CFG,
  			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
 @@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
  	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- 	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
  
 -	if (dev->hw->version == 1)
 +	if (mtk_wed_is_v1(dev->hw))
  		return;
  
  	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -625,7 +625,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -624,7 +624,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
  		MTK_WED_CTRL_WED_TX_BM_EN |
  		MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
  
@@ -69,7 +69,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return;
  
  	wed_clr(dev, MTK_WED_CTRL,
-@@ -731,7 +731,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -730,7 +730,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
  static void
  mtk_wed_set_wpdma(struct mtk_wed_device *dev)
  {
@@ -78,7 +78,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
  	} else {
  		mtk_wed_bus_init(dev);
-@@ -762,7 +762,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -761,7 +761,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
  	      MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
  	wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
  
@@ -87,7 +87,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		u32 offset = dev->hw->index ? 0x04000400 : 0;
  
  		wdma_set(dev, MTK_WDMA_GLO_CFG,
-@@ -935,7 +935,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -934,7 +934,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  
  	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
  
@@ -96,7 +96,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_TX_BM_TKID,
  			FIELD_PREP(MTK_WED_TX_BM_TKID_START,
  				   dev->wlan.token_start) |
-@@ -968,7 +968,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -967,7 +967,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  
  	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
  
@@ -105,7 +105,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_set(dev, MTK_WED_CTRL,
  			MTK_WED_CTRL_WED_TX_BM_EN |
  			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
-@@ -1218,7 +1218,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1217,7 +1217,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
  	}
  
  	dev->init_done = false;
@@ -114,7 +114,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return;
  
  	if (!busy) {
-@@ -1344,7 +1344,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1343,7 +1343,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  		MTK_WED_CTRL_WED_TX_BM_EN |
  		MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
  
@@ -123,7 +123,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
  			MTK_WED_PCIE_INT_TRIGGER_STATUS);
  
-@@ -1417,7 +1417,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1416,7 +1416,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
  		 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
  		 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
  
@@ -132,7 +132,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wdma_set(dev, MTK_WDMA_GLO_CFG,
  			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
  	} else {
-@@ -1466,7 +1466,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1465,7 +1465,7 @@ mtk_wed_start(struct mtk_wed_device *dev
  
  	mtk_wed_set_ext_int(dev, true);
  
@@ -141,7 +141,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
  			  FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
  				     dev->hw->index);
-@@ -1551,7 +1551,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,7 +1550,7 @@ mtk_wed_attach(struct mtk_wed_device *de
  	}
  
  	mtk_wed_hw_init_early(dev);
@@ -150,7 +150,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
  				   BIT(hw->index), 0);
  	} else {
-@@ -1619,7 +1619,7 @@ static int
+@@ -1618,7 +1618,7 @@ static int
  mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
  {
  	struct mtk_wed_ring *ring = &dev->txfree_ring;
@@ -159,7 +159,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/*
  	 * For txfree event handling, the same DMA ring is shared between WED
-@@ -1677,7 +1677,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
+@@ -1676,7 +1676,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
  {
  	u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
  
@@ -168,7 +168,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
  	else
  		ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
-@@ -1844,7 +1844,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
+@@ -1840,7 +1840,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
  {
  	struct mtk_wed_hw *hw = wed->hw;
  
@@ -177,7 +177,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return -EOPNOTSUPP;
  
  	switch (type) {
-@@ -1918,9 +1918,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1914,9 +1914,9 @@ void mtk_wed_add_hw(struct device_node *
  	hw->wdma = wdma;
  	hw->index = index;
  	hw->irq = irq;
diff --git a/target/linux/generic/backport-6.6/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch b/target/linux/generic/backport-6.6/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch
index d5bacde325..02ef4e6401 100644
--- a/target/linux/generic/backport-6.6/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch
+++ b/target/linux/generic/backport-6.6/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch
@@ -16,15 +16,15 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
 @@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
  	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- 	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
  
 -	if (mtk_wed_is_v1(dev->hw))
 +	if (!mtk_wed_get_rx_capa(dev))
  		return;
  
  	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -733,16 +733,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
  {
  	if (mtk_wed_is_v1(dev->hw)) {
  		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
@@ -55,7 +55,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -974,15 +979,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
  	} else {
  		wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
@@ -82,7 +82,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
-@@ -1354,8 +1361,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  
  		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
  	} else {
@@ -91,7 +91,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		/* initail tx interrupt trigger */
  		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
  			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1374,15 +1379,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
  				   dev->wlan.txfree_tbit));
  
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  		wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
  		wed_set(dev, MTK_WED_WDMA_INT_CTRL,
-@@ -1401,6 +1411,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  static void
  mtk_wed_dma_enable(struct mtk_wed_device *dev)
  {
@@ -130,7 +130,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
  
  	wed_set(dev, MTK_WED_GLO_CFG,
-@@ -1420,33 +1432,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
  	if (mtk_wed_is_v1(dev->hw)) {
  		wdma_set(dev, MTK_WDMA_GLO_CFG,
  			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
@@ -186,7 +186,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -1473,7 +1485,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
  
  		val |= BIT(0) | (BIT(1) * !!dev->hw->index);
  		regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
@@ -195,7 +195,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		/* driver set mid ready and only once */
  		wed_w32(dev, MTK_WED_EXT_INT_MASK1,
  			MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
-@@ -1485,7 +1497,6 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
  
  		if (mtk_wed_rro_cfg(dev))
  			return;
@@ -203,7 +203,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
-@@ -1551,13 +1562,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
  	}
  
  	mtk_wed_hw_init_early(dev);
diff --git a/target/linux/generic/backport-6.6/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch b/target/linux/generic/backport-6.6/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch
index 71b32c545b..3e750ec1d4 100644
--- a/target/linux/generic/backport-6.6/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch
+++ b/target/linux/generic/backport-6.6/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch
@@ -38,7 +38,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void
  wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
  {
-@@ -747,7 +767,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -746,7 +766,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
  		return;
  
  	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
@@ -47,7 +47,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -941,22 +961,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -940,22 +960,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
  
  	if (mtk_wed_is_v1(dev->hw)) {
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
  			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
  			MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -971,6 +979,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -970,6 +978,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  			MTK_WED_TX_TKID_DYN_THR_HI);
  	}
  
@@ -82,7 +82,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
  
  	if (mtk_wed_is_v1(dev->hw)) {
-@@ -1105,13 +1118,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1104,13 +1117,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  	if (ret) {
  		mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
  	} else {
@@ -98,7 +98,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_RESET_IDX, 0);
  	}
  
-@@ -1164,7 +1172,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1163,7 +1171,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
  	if (busy) {
  		mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
  	} else {
@@ -108,7 +108,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_RESET_IDX, 0);
  	}
  
-@@ -1256,7 +1265,6 @@ static int
+@@ -1255,7 +1264,6 @@ static int
  mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
  			   bool reset)
  {
@@ -116,7 +116,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	struct mtk_wed_ring *wdma;
  
  	if (idx >= ARRAY_SIZE(dev->rx_wdma))
-@@ -1264,7 +1272,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1263,7 +1271,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
  
  	wdma = &dev->rx_wdma[idx];
  	if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
@@ -125,7 +125,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return -ENOMEM;
  
  	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1285,7 +1293,6 @@ static int
+@@ -1284,7 +1292,6 @@ static int
  mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
  			   bool reset)
  {
@@ -133,7 +133,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	struct mtk_wed_ring *wdma;
  
  	if (idx >= ARRAY_SIZE(dev->tx_wdma))
-@@ -1293,7 +1300,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1292,7 +1299,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
  
  	wdma = &dev->tx_wdma[idx];
  	if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
@@ -142,7 +142,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return -ENOMEM;
  
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1932,7 +1939,12 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1928,7 +1935,12 @@ void mtk_wed_add_hw(struct device_node *
  	hw->irq = irq;
  	hw->version = eth->soc->version;
  
@@ -156,7 +156,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
  				"mediatek,pcie-mirror");
  		hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
-@@ -1946,6 +1958,8 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1942,6 +1954,8 @@ void mtk_wed_add_hw(struct device_node *
  			regmap_write(hw->mirror, 0, 0);
  			regmap_write(hw->mirror, 4, 0);
  		}
diff --git a/target/linux/generic/backport-6.6/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch b/target/linux/generic/backport-6.6/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
index 12733b142f..5a271a5628 100644
--- a/target/linux/generic/backport-6.6/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
+++ b/target/linux/generic/backport-6.6/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
@@ -302,7 +302,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	mtk_wed_set_512_support(dev, false);
-@@ -652,6 +699,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -651,6 +698,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
  		MTK_WED_CTRL_RX_ROUTE_QM_EN |
  		MTK_WED_CTRL_WED_RX_BM_EN |
  		MTK_WED_CTRL_RX_RRO_QM_EN);
@@ -317,7 +317,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -701,21 +756,37 @@ mtk_wed_detach(struct mtk_wed_device *de
+@@ -700,21 +755,37 @@ mtk_wed_detach(struct mtk_wed_device *de
  	mutex_unlock(&hw_lock);
  }
  
@@ -362,7 +362,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  		wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
  			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
-@@ -723,19 +794,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -722,19 +793,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
  		/* pcie interrupt control: pola/source selection */
  		wed_set(dev, MTK_WED_PCIE_INT_CTRL,
  			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
@@ -385,7 +385,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		break;
  	}
  	case MTK_WED_BUS_AXI:
-@@ -773,18 +834,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -772,18 +833,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
  static void
  mtk_wed_hw_init_early(struct mtk_wed_device *dev)
  {
@@ -412,7 +412,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
  
  	if (mtk_wed_is_v1(dev->hw)) {
-@@ -932,11 +994,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
+@@ -931,11 +993,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
  	}
  
  	/* configure RX_ROUTE_QM */
@@ -436,7 +436,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	/* enable RX_ROUTE_QM */
  	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
  }
-@@ -949,22 +1018,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -948,22 +1017,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  
  	dev->init_done = true;
  	mtk_wed_set_ext_int(dev, false);
@@ -475,7 +475,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
  			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
  			MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -974,9 +1051,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,9 +1050,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  				   dev->tx_buf_ring.size / 128) |
  			FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
  				   dev->tx_buf_ring.size / 128));
@@ -485,7 +485,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
-@@ -986,26 +1060,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -985,26 +1059,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  
  	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
  
@@ -561,7 +561,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -1303,6 +1413,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1302,6 +1412,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
  					 dev->hw->soc->wdma_desc_size, true))
  		return -ENOMEM;
  
@@ -586,7 +586,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
  		 wdma->desc_phys);
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
-@@ -1368,6 +1496,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1367,6 +1495,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  
  		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
  	} else {
@@ -596,7 +596,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		/* initail tx interrupt trigger */
  		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
  			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1420,33 +1551,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1550,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
  {
  	int i;
  
@@ -668,7 +668,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
  		MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
  		MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
-@@ -1458,11 +1616,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1457,11 +1615,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
  		MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
  		MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
  
@@ -693,7 +693,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	for (i = 0; i < MTK_WED_RX_QUEUES; i++)
  		mtk_wed_check_wfdma_rx_fill(dev, i);
-@@ -1502,6 +1671,12 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1501,6 +1670,12 @@ mtk_wed_start(struct mtk_wed_device *dev
  		wed_r32(dev, MTK_WED_EXT_INT_MASK1);
  		wed_r32(dev, MTK_WED_EXT_INT_MASK2);
  
@@ -706,7 +706,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		if (mtk_wed_rro_cfg(dev))
  			return;
  	}
-@@ -1553,6 +1728,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1552,6 +1727,7 @@ mtk_wed_attach(struct mtk_wed_device *de
  	dev->irq = hw->irq;
  	dev->wdma_idx = hw->index;
  	dev->version = hw->version;
@@ -714,7 +714,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (hw->eth->dma_dev == hw->eth->dev &&
  	    of_dma_is_coherent(hw->eth->dev->of_node))
-@@ -1620,6 +1796,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -1619,6 +1795,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
  	ring->reg_base = MTK_WED_RING_TX(idx);
  	ring->wpdma = regs;
  
@@ -738,7 +738,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	/* WED -> WPDMA */
  	wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
  	wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
-@@ -1694,15 +1887,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
+@@ -1693,15 +1886,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
  static u32
  mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
  {
@@ -759,7 +759,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
  	wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
-@@ -1943,6 +2134,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1939,6 +2130,9 @@ void mtk_wed_add_hw(struct device_node *
  	case 2:
  		hw->soc = &mt7986_data;
  		break;
diff --git a/target/linux/generic/backport-6.6/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch b/target/linux/generic/backport-6.6/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch
index 5e12343de2..aa2f952b8a 100644
--- a/target/linux/generic/backport-6.6/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch
+++ b/target/linux/generic/backport-6.6/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch
@@ -56,7 +56,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -1546,6 +1537,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1545,6 +1536,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  	wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void
  mtk_wed_dma_enable(struct mtk_wed_device *dev)
  {
-@@ -1633,8 +1625,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1632,8 +1624,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
  		wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
  	}
  
diff --git a/target/linux/generic/backport-6.6/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch b/target/linux/generic/backport-6.6/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch
index f70886aa0d..4e72ea128a 100644
--- a/target/linux/generic/backport-6.6/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch
+++ b/target/linux/generic/backport-6.6/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch
@@ -248,7 +248,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
  {
  	u32 desc_size = dev->hw->soc->tx_ring_desc_size;
-@@ -709,6 +840,7 @@ __mtk_wed_detach(struct mtk_wed_device *
+@@ -708,6 +839,7 @@ __mtk_wed_detach(struct mtk_wed_device *
  
  	mtk_wdma_rx_reset(dev);
  	mtk_wed_reset(dev, MTK_WED_RESET_WED);
@@ -256,7 +256,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mtk_wed_free_tx_buffer(dev);
  	mtk_wed_free_tx_rings(dev);
  
-@@ -1129,23 +1261,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -1128,23 +1260,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
  	}
  }
  
@@ -280,7 +280,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int
  mtk_wed_rx_reset(struct mtk_wed_device *dev)
  {
-@@ -1692,6 +1807,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1691,6 +1806,7 @@ mtk_wed_start(struct mtk_wed_device *dev
  	}
  
  	mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
@@ -288,7 +288,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mtk_wed_dma_enable(dev);
  	dev->running = true;
-@@ -1748,6 +1864,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1747,6 +1863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
  	if (ret)
  		goto out;
  
diff --git a/target/linux/generic/backport-6.6/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch b/target/linux/generic/backport-6.6/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch
index 5c3015c338..f035f8fc06 100644
--- a/target/linux/generic/backport-6.6/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch
+++ b/target/linux/generic/backport-6.6/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch
@@ -173,7 +173,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -935,6 +1056,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -934,6 +1055,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
  static void
  mtk_wed_set_wpdma(struct mtk_wed_device *dev)
  {
@@ -182,7 +182,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	if (mtk_wed_is_v1(dev->hw)) {
  		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
  		return;
-@@ -952,6 +1075,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -951,6 +1074,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
  
  	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
  	wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
@@ -198,7 +198,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -1763,6 +1895,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1762,6 +1894,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
  }
  
  static void
@@ -364,7 +364,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
  {
  	int i;
-@@ -2216,6 +2507,10 @@ void mtk_wed_add_hw(struct device_node *
+@@ -2212,6 +2503,10 @@ void mtk_wed_add_hw(struct device_node *
  		.detach = mtk_wed_detach,
  		.ppe_check = mtk_wed_ppe_check,
  		.setup_tc = mtk_wed_setup_tc,
diff --git a/target/linux/generic/backport-6.6/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch b/target/linux/generic/backport-6.6/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
index 18aa4107db..7dad2102ae 100644
--- a/target/linux/generic/backport-6.6/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
+++ b/target/linux/generic/backport-6.6/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
@@ -205,7 +205,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
  	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
  
-@@ -1406,13 +1570,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  	if (ret)
  		return ret;
  
@@ -239,7 +239,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
  			MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
  			MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
-@@ -1440,23 +1624,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  		wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
  	}
  
@@ -298,7 +298,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
  
  	/* reset wed rx dma */
-@@ -1477,6 +1690,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  			  MTK_WED_CTRL_WED_RX_BM_BUSY);
  	mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
  
@@ -313,7 +313,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	/* wo change to enable state */
  	val = MTK_WED_WO_STATE_ENABLE;
  	ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
-@@ -1494,6 +1715,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  				   false);
  	}
  	mtk_wed_free_rx_buffer(dev);
@@ -321,7 +321,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return 0;
  }
-@@ -1527,15 +1749,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
  
  	/* 2. reset WDMA rx DMA */
  	busy = !!mtk_wdma_rx_reset(dev);
@@ -364,7 +364,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
  			MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
  		wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
-@@ -1551,8 +1799,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
  	wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
  
  	for (i = 0; i < 100; i++) {
@@ -380,7 +380,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  			break;
  	}
  
-@@ -1574,6 +1827,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
  		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
  		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
  		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
@@ -389,7 +389,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	} else {
  		wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
  			MTK_WED_WPDMA_RESET_IDX_TX |
-@@ -1590,7 +1845,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
  		wed_w32(dev, MTK_WED_RESET_IDX, 0);
  	}
  
@@ -405,7 +405,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static int
-@@ -1842,6 +2104,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
  			MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
  
  		wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
@@ -413,7 +413,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
-@@ -1905,6 +2168,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
+@@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
  	if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
  		return;
  
diff --git a/target/linux/generic/backport-6.6/752-21-v6.7-net-ethernet-mtk_wed-fix-firmware-loading-for-MT7986.patch b/target/linux/generic/backport-6.6/752-21-v6.7-net-ethernet-mtk_wed-fix-firmware-loading-for-MT7986.patch
new file mode 100644
index 0000000000..3b0795c536
--- /dev/null
+++ b/target/linux/generic/backport-6.6/752-21-v6.7-net-ethernet-mtk_wed-fix-firmware-loading-for-MT7986.patch
@@ -0,0 +1,113 @@
+From 52ea72ad0daa0f29535b4cef39257616c5a211d3 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 24 Oct 2023 00:00:19 +0200
+Subject: [PATCH 1/5] net: ethernet: mtk_wed: fix firmware loading for MT7986
+ SoC
+
+The WED mcu firmware does not contain all the memory regions defined in
+the dts reserved_memory node (e.g. MT7986 WED firmware does not contain
+cpu-boot region).
+Reverse the mtk_wed_mcu_run_firmware() logic to check all the fw
+sections are defined in the dts reserved_memory node.
+
+Fixes: c6d961aeaa77 ("net: ethernet: mtk_wed: move mem_region array out of mtk_wed_mcu_load_firmware")
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Link: https://lore.kernel.org/r/d983cbfe8ea562fef9264de8f0c501f7d5705bd5.1698098381.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 48 +++++++++++----------
+ 1 file changed, 25 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -258,16 +258,12 @@ mtk_wed_get_memory_region(struct mtk_wed
+ }
+ 
+ static int
+-mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
+-			 struct mtk_wed_wo_memory_region *region)
++mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw)
+ {
+ 	const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
+ 	const struct mtk_wed_fw_trailer *trailer;
+ 	const struct mtk_wed_fw_region *fw_region;
+ 
+-	if (!region->phy_addr || !region->size)
+-		return 0;
+-
+ 	trailer_ptr = fw->data + fw->size - sizeof(*trailer);
+ 	trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
+ 	region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
+@@ -275,33 +271,41 @@ mtk_wed_mcu_run_firmware(struct mtk_wed_
+ 
+ 	while (region_ptr < trailer_ptr) {
+ 		u32 length;
++		int i;
+ 
+ 		fw_region = (const struct mtk_wed_fw_region *)region_ptr;
+ 		length = le32_to_cpu(fw_region->len);
+-
+-		if (region->phy_addr != le32_to_cpu(fw_region->addr))
+-			goto next;
+-
+-		if (region->size < length)
+-			goto next;
+-
+ 		if (first_region_ptr < ptr + length)
+ 			goto next;
+ 
+-		if (region->shared && region->consumed)
+-			return 0;
++		for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
++			struct mtk_wed_wo_memory_region *region;
+ 
+-		if (!region->shared || !region->consumed) {
+-			memcpy_toio(region->addr, ptr, length);
+-			region->consumed = true;
+-			return 0;
++			region = &mem_region[i];
++			if (region->phy_addr != le32_to_cpu(fw_region->addr))
++				continue;
++
++			if (region->size < length)
++				continue;
++
++			if (region->shared && region->consumed)
++				break;
++
++			if (!region->shared || !region->consumed) {
++				memcpy_toio(region->addr, ptr, length);
++				region->consumed = true;
++				break;
++			}
+ 		}
++
++		if (i == ARRAY_SIZE(mem_region))
++			return -EINVAL;
+ next:
+ 		region_ptr += sizeof(*fw_region);
+ 		ptr += length;
+ 	}
+ 
+-	return -EINVAL;
++	return 0;
+ }
+ 
+ static int
+@@ -360,11 +364,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 	dev_info(wo->hw->dev, "MTK WED WO Chip ID %02x Region %d\n",
+ 		 trailer->chip_id, trailer->num_region);
+ 
+-	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+-		ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
+-		if (ret)
+-			goto out;
+-	}
++	ret = mtk_wed_mcu_run_firmware(wo, fw);
++	if (ret)
++		goto out;
+ 
+ 	/* set the start address */
+ 	if (!mtk_wed_is_v3_or_greater(wo->hw) && wo->hw->index)
diff --git a/target/linux/generic/backport-6.6/752-22-v6.7-net-ethernet-mtk_wed-remove-wo-pointer-in-wo_r32-wo_.patch b/target/linux/generic/backport-6.6/752-22-v6.7-net-ethernet-mtk_wed-remove-wo-pointer-in-wo_r32-wo_.patch
new file mode 100644
index 0000000000..c1bb3f5b02
--- /dev/null
+++ b/target/linux/generic/backport-6.6/752-22-v6.7-net-ethernet-mtk_wed-remove-wo-pointer-in-wo_r32-wo_.patch
@@ -0,0 +1,51 @@
+From 7aa8defd3495208289abcc629946af26a2af3391 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 24 Oct 2023 00:01:30 +0200
+Subject: [PATCH 2/5] net: ethernet: mtk_wed: remove wo pointer in
+ wo_r32/wo_w32 signature
+
+wo pointer is no longer used in wo_r32 and wo_w32 routines so get rid of
+it.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/530537db0872f7523deff21f0a5dfdd9b75fdc9d.1698098459.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -32,12 +32,12 @@ static struct mtk_wed_wo_memory_region m
+ 	},
+ };
+ 
+-static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
++static u32 wo_r32(u32 reg)
+ {
+ 	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+ 
+-static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
++static void wo_w32(u32 reg, u32 val)
+ {
+ 	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+@@ -373,13 +373,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 		boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
+ 	else
+ 		boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+-	wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
++	wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ 	/* wo firmware reset */
+-	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
++	wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+ 
+-	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++	val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
+ 	      MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+-	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
++	wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ 	release_firmware(fw);
+ 
diff --git a/target/linux/generic/backport-6.6/752-23-v6.8-net-ethernet-mtk_wed-rely-on-__dev_alloc_page-in-mtk.patch b/target/linux/generic/backport-6.6/752-23-v6.8-net-ethernet-mtk_wed-rely-on-__dev_alloc_page-in-mtk.patch
new file mode 100644
index 0000000000..7cbf6bd732
--- /dev/null
+++ b/target/linux/generic/backport-6.6/752-23-v6.8-net-ethernet-mtk_wed-rely-on-__dev_alloc_page-in-mtk.patch
@@ -0,0 +1,26 @@
+From 65aacd457eaf5d0c958ed8030ec46f99ea808dd9 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Fri, 17 Nov 2023 17:39:22 +0100
+Subject: [PATCH 3/5] net: ethernet: mtk_wed: rely on __dev_alloc_page in
+ mtk_wed_tx_buffer_alloc
+
+Simplify the code and use __dev_alloc_page() instead of __dev_alloc_pages()
+with order 0 in mtk_wed_tx_buffer_alloc routine
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -670,7 +670,7 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 		void *buf;
+ 		int s;
+ 
+-		page = __dev_alloc_pages(GFP_KERNEL, 0);
++		page = __dev_alloc_page(GFP_KERNEL);
+ 		if (!page)
+ 			return -ENOMEM;
+ 
diff --git a/target/linux/generic/backport-6.6/752-24-v6.8-net-ethernet-mtk_wed-add-support-for-devices-with-mo.patch b/target/linux/generic/backport-6.6/752-24-v6.8-net-ethernet-mtk_wed-add-support-for-devices-with-mo.patch
new file mode 100644
index 0000000000..b08f3aaadd
--- /dev/null
+++ b/target/linux/generic/backport-6.6/752-24-v6.8-net-ethernet-mtk_wed-add-support-for-devices-with-mo.patch
@@ -0,0 +1,91 @@
+From 5f5997322584b6257543d4d103f81484b8006d84 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Fri, 17 Nov 2023 17:42:59 +0100
+Subject: [PATCH 4/5] net: ethernet: mtk_wed: add support for devices with more
+ than 4GB of dram
+
+Introduce WED offloading support for boards with more than 4GB of
+memory.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/1c7efdf5d384ea7af3c0209723e40b2ee0f956bf.1700239272.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ drivers/net/ethernet/mediatek/mtk_wed.c     | 8 +++++---
+ drivers/net/ethernet/mediatek/mtk_wed_wo.c  | 3 ++-
+ 3 files changed, 11 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1158,15 +1158,18 @@ static int mtk_init_fq_dma(struct mtk_et
+ 	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
+ 
+ 	for (i = 0; i < cnt; i++) {
++		dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;
+ 		struct mtk_tx_dma_v2 *txd;
+ 
+ 		txd = eth->scratch_ring + i * soc->tx.desc_size;
+-		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
++		txd->txd1 = addr;
+ 		if (i < cnt - 1)
+ 			txd->txd2 = eth->phy_scratch_ring +
+ 				    (i + 1) * soc->tx.desc_size;
+ 
+ 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
++		if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
++			txd->txd3 |= TX_DMA_PREP_ADDR64(addr);
+ 		txd->txd4 = 0;
+ 		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			txd->txd5 = 0;
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 
+ 		for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
+ 			struct mtk_wdma_desc *desc = desc_ptr;
++			u32 ctrl;
+ 
+ 			desc->buf0 = cpu_to_le32(buf_phys);
+ 			if (!mtk_wed_is_v3_or_greater(dev->hw)) {
+-				u32 txd_size, ctrl;
++				u32 txd_size;
+ 
+ 				txd_size = dev->wlan.init_buf(buf, buf_phys,
+ 							      token++);
+@@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 					ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
+ 						FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
+ 							   MTK_WED_BUF_SIZE - txd_size);
+-				desc->ctrl = cpu_to_le32(ctrl);
+ 				desc->info = 0;
+ 			} else {
+-				desc->ctrl = cpu_to_le32(token << 16);
++				ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
+ 			}
++			desc->ctrl = cpu_to_le32(ctrl);
+ 
+ 			desc_ptr += desc_size;
+ 			buf += MTK_WED_BUF_SIZE;
+@@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_we
+ 		buf_phys = page_phys;
+ 		for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
+ 			desc->buf0 = cpu_to_le32(buf_phys);
++			desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
+ 			buf_phys += MTK_WED_PAGE_BUF_SIZE;
+ 			desc++;
+ 		}
+--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c
+@@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_w
+ 		dma_addr_t addr;
+ 		void *buf;
+ 
+-		buf = page_frag_alloc(&q->cache, q->buf_size, GFP_ATOMIC);
++		buf = page_frag_alloc(&q->cache, q->buf_size,
++				      GFP_ATOMIC | GFP_DMA32);
+ 		if (!buf)
+ 			break;
+ 
diff --git a/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch b/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch
new file mode 100644
index 0000000000..714ef49872
--- /dev/null
+++ b/target/linux/generic/backport-6.6/765-v6.9-net-phy-aquantia-add-support-for-AQR114C-PHY-ID.patch
@@ -0,0 +1,69 @@
+From c278ec644377249aba5b1e1ca2b5705fd1c0132c Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Mon, 1 Apr 2024 16:51:06 +0200
+Subject: [PATCH net-next v2] net: phy: aquantia: add support for AQR114C PHY ID  
+
+Add support for AQR114C PHY ID. This PHY advertise 10G speed:
+SPEED(0x04): 0x6031
+  capabilities: -400g +5g +2.5g -200g -25g -10g-xr -100g -40g -10g/1g -10
+                +100 +1000 -10-ts -2-tl +10g
+EXTABLE(0x0B): 0x40fc
+  capabilities: -10g-cx4 -10g-lrm +10g-t +10g-kx4 +10g-kr +1000-t +1000-kx
+                +100-tx -10-t -p2mp -40g/100g -1000/100-t1 -25g -200g/400g
+                +2.5g/5g -1000-h
+
+but supports only up to 5G speed (as with AQR111/111B0).
+AQR111 init config is used to set max speed 5G.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240401145114.1699451-1-frut3k7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -28,6 +28,7 @@
+ #define PHY_ID_AQR412	0x03a1b712
+ #define PHY_ID_AQR113	0x31c31c40
+ #define PHY_ID_AQR113C	0x31c31c12
++#define PHY_ID_AQR114C	0x31c31c22
+ #define PHY_ID_AQR813	0x31c31cb2
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+@@ -880,6 +881,25 @@ static struct phy_driver aqr_driver[] =
+ 	.link_change_notify = aqr107_link_change_notify,
+ },
+ {
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
++	.name           = "Aquantia AQR114C",
++	.probe          = aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init    = aqr111_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr    = aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status    = aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend        = aqr107_suspend,
++	.resume         = aqr107_resume,
++	.get_sset_count = aqr107_get_sset_count,
++	.get_strings    = aqr107_get_strings,
++	.get_stats      = aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+ 	.name		= "Aquantia AQR813",
+ 	.probe		= aqr107_probe,
+@@ -916,6 +936,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ 	{ }
+ };
diff --git a/target/linux/generic/backport-6.6/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch b/target/linux/generic/backport-6.6/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
index 3951715fc6..a7da409aeb 100644
--- a/target/linux/generic/backport-6.6/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
+++ b/target/linux/generic/backport-6.6/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
@@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3003,13 +3003,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2988,13 +2988,25 @@ static void stmmac_tx_timer_arm(struct s
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	u32 tx_coal_timer = priv->tx_coal_timer[queue];
diff --git a/target/linux/generic/backport-6.6/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch b/target/linux/generic/backport-6.6/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
index ce39895b45..60dfe4c035 100644
--- a/target/linux/generic/backport-6.6/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
+++ b/target/linux/generic/backport-6.6/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
@@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2551,9 +2551,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2536,9 +2536,13 @@ static void stmmac_bump_dma_threshold(st
   * @priv: driver private structure
   * @budget: napi budget limiting this functions packet handling
   * @queue: TX queue index
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
  	struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
-@@ -2713,7 +2717,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2698,7 +2702,7 @@ static int stmmac_tx_clean(struct stmmac
  
  	/* We still have pending packets, let's call for a new scheduling */
  	if (tx_q->dirty_tx != tx_q->cur_tx)
@@ -42,7 +42,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	u64_stats_update_begin(&txq_stats->napi_syncp);
  	u64_stats_add(&txq_stats->napi.tx_packets, tx_packets);
-@@ -5605,6 +5609,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5590,6 +5594,7 @@ static int stmmac_napi_poll_tx(struct na
  		container_of(napi, struct stmmac_channel, tx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
  	struct stmmac_txq_stats *txq_stats;
@@ -50,7 +50,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	u32 chan = ch->index;
  	int work_done;
  
-@@ -5613,7 +5618,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5598,7 +5603,7 @@ static int stmmac_napi_poll_tx(struct na
  	u64_stats_inc(&txq_stats->napi.poll);
  	u64_stats_update_end(&txq_stats->napi_syncp);
  
@@ -59,7 +59,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	work_done = min(work_done, budget);
  
  	if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5624,6 +5629,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5609,6 +5614,10 @@ static int stmmac_napi_poll_tx(struct na
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return work_done;
  }
  
-@@ -5632,6 +5641,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5617,6 +5626,7 @@ static int stmmac_napi_poll_rxtx(struct
  	struct stmmac_channel *ch =
  		container_of(napi, struct stmmac_channel, rxtx_napi);
  	struct stmmac_priv *priv = ch->priv_data;
@@ -78,7 +78,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	int rx_done, tx_done, rxtx_done;
  	struct stmmac_rxq_stats *rxq_stats;
  	struct stmmac_txq_stats *txq_stats;
-@@ -5647,7 +5657,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5632,7 +5642,7 @@ static int stmmac_napi_poll_rxtx(struct
  	u64_stats_inc(&txq_stats->napi.poll);
  	u64_stats_update_end(&txq_stats->napi_syncp);
  
@@ -87,7 +87,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	tx_done = min(tx_done, budget);
  
  	rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5672,6 +5682,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5657,6 +5667,10 @@ static int stmmac_napi_poll_rxtx(struct
  		spin_unlock_irqrestore(&ch->lock, flags);
  	}
  
diff --git a/target/linux/generic/backport-6.6/790-02-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch b/target/linux/generic/backport-6.6/790-02-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
index ff6c592e12..506024379e 100644
--- a/target/linux/generic/backport-6.6/790-02-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
+++ b/target/linux/generic/backport-6.6/790-02-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch
@@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3021,15 +3021,6 @@ static void mt753x_phylink_mac_link_down
+@@ -3037,15 +3037,6 @@ static void mt753x_phylink_mac_link_down
  	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
  }
  
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
  				       unsigned int mode,
  				       phy_interface_t interface,
-@@ -3117,8 +3108,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3133,8 +3124,6 @@ mt7531_cpu_port_config(struct dsa_switch
  		return ret;
  	mt7530_write(priv, MT7530_PMCR_P(port),
  		     PMCR_CPU_PORT_SETTING(priv->id));
diff --git a/target/linux/generic/backport-6.6/790-04-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch b/target/linux/generic/backport-6.6/790-04-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
index 46651e32df..74f6c1129c 100644
--- a/target/linux/generic/backport-6.6/790-04-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
+++ b/target/linux/generic/backport-6.6/790-04-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch
@@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2343,24 +2343,40 @@ mt7530_free_irq_common(struct mt7530_pri
+@@ -2345,24 +2345,40 @@ mt7530_free_irq_common(struct mt7530_pri
  static void
  mt7530_free_irq(struct mt7530_priv *priv)
  {
@@ -92,7 +92,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	bus->priv = priv;
  	bus->name = KBUILD_MODNAME "-mii";
  	snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
-@@ -2371,16 +2387,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2373,16 +2389,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  	bus->parent = dev;
  	bus->phy_mask = ~ds->phys_mii_mask;
  
diff --git a/target/linux/generic/backport-6.6/790-05-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch b/target/linux/generic/backport-6.6/790-05-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
index 108bbaba86..8c73ea94a1 100644
--- a/target/linux/generic/backport-6.6/790-05-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
+++ b/target/linux/generic/backport-6.6/790-05-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch
@@ -49,7 +49,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
  	 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
  	 * is affine to the inbound user port.
-@@ -3289,6 +3285,36 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3305,6 +3301,36 @@ static int mt753x_set_mac_eee(struct dsa
  	return 0;
  }
  
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  {
  	return 0;
-@@ -3344,6 +3370,7 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3360,6 +3386,7 @@ const struct dsa_switch_ops mt7530_switc
  	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
  	.get_mac_eee		= mt753x_get_mac_eee,
  	.set_mac_eee		= mt753x_set_mac_eee,
@@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -41,8 +41,8 @@ enum mt753x_id {
+@@ -45,8 +45,8 @@ enum mt753x_id {
  #define  UNU_FFP(x)			(((x) & 0xff) << 8)
  #define  UNU_FFP_MASK			UNU_FFP(~0)
  #define  CPU_EN				BIT(7)
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  #define  MIRROR_EN			BIT(3)
  #define  MIRROR_PORT(x)			((x) & 0x7)
  #define  MIRROR_MASK			0x7
-@@ -785,6 +785,7 @@ struct mt753x_info {
+@@ -790,6 +790,7 @@ struct mt753x_info {
   * @irq_domain:		IRQ domain of the switch irq_chip
   * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
   * @create_sgmii:	Pointer to function creating SGMII PCS instance(s)
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   */
  struct mt7530_priv {
  	struct device		*dev;
-@@ -811,6 +812,7 @@ struct mt7530_priv {
+@@ -816,6 +817,7 @@ struct mt7530_priv {
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
  	int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
diff --git a/target/linux/generic/backport-6.6/790-06-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch b/target/linux/generic/backport-6.6/790-06-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
index ea79de61f9..3956ae453e 100644
--- a/target/linux/generic/backport-6.6/790-06-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
+++ b/target/linux/generic/backport-6.6/790-06-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch
@@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -708,7 +708,7 @@ struct mt7530_port {
+@@ -713,7 +713,7 @@ struct mt7530_port {
  
  /* Port 5 interface select definitions */
  enum p5_interface_select {
@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	P5_INTF_SEL_PHY_P0,
  	P5_INTF_SEL_PHY_P4,
  	P5_INTF_SEL_GMAC5,
-@@ -801,7 +801,7 @@ struct mt7530_priv {
+@@ -806,7 +806,7 @@ struct mt7530_priv {
  	bool			mcm;
  	phy_interface_t		p6_interface;
  	phy_interface_t		p5_interface;
diff --git a/target/linux/generic/backport-6.6/790-07-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch b/target/linux/generic/backport-6.6/790-07-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
index 2d1a487c98..426a7bcc2f 100644
--- a/target/linux/generic/backport-6.6/790-07-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
+++ b/target/linux/generic/backport-6.6/790-07-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		return "unknown";
  	}
-@@ -2685,6 +2671,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2694,6 +2680,12 @@ mt7531_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
@@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	/* all MACs must be forced link-down before sw reset */
  	for (i = 0; i < MT7530_NUM_PORTS; i++)
  		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-@@ -2694,21 +2686,18 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2703,21 +2695,18 @@ mt7531_setup(struct dsa_switch *ds)
  		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
  		     SYS_CTRL_REG_RST);
  
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
  		   MT7531_GPIO0_INTERRUPT);
-@@ -2768,11 +2757,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2784,11 +2773,6 @@ static void mt7530_mac_port_get_caps(str
  	}
  }
  
@@ -153,7 +153,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
  				     struct phylink_config *config)
  {
-@@ -2785,7 +2769,7 @@ static void mt7531_mac_port_get_caps(str
+@@ -2801,7 +2785,7 @@ static void mt7531_mac_port_get_caps(str
  		break;
  
  	case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
@@ -162,7 +162,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			phy_interface_set_rgmii(config->supported_interfaces);
  			break;
  		}
-@@ -2852,7 +2836,7 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2868,7 +2852,7 @@ static int mt7531_rgmii_setup(struct mt7
  {
  	u32 val;
  
@@ -171,7 +171,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev_err(priv->dev, "RGMII mode is not available for port %d\n",
  			port);
  		return -EINVAL;
-@@ -3095,7 +3079,7 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3111,7 +3095,7 @@ mt7531_cpu_port_config(struct dsa_switch
  
  	switch (port) {
  	case 5:
@@ -180,7 +180,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			interface = PHY_INTERFACE_MODE_RGMII;
  		else
  			interface = PHY_INTERFACE_MODE_2500BASEX;
-@@ -3247,7 +3231,7 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3263,7 +3247,7 @@ mt753x_setup(struct dsa_switch *ds)
  		mt7530_free_irq_common(priv);
  
  	if (priv->create_sgmii) {
@@ -191,7 +191,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -712,7 +712,6 @@ enum p5_interface_select {
+@@ -717,7 +717,6 @@ enum p5_interface_select {
  	P5_INTF_SEL_PHY_P0,
  	P5_INTF_SEL_PHY_P4,
  	P5_INTF_SEL_GMAC5,
@@ -199,7 +199,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  };
  
  struct mt7530_priv;
-@@ -781,6 +780,8 @@ struct mt753x_info {
+@@ -786,6 +785,8 @@ struct mt753x_info {
   *			registers
   * @p6_interface	Holding the current port 6 interface
   * @p5_intf_sel:	Holding the current port 5 interface select
@@ -208,7 +208,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @irq:		IRQ number of the switch
   * @irq_domain:		IRQ domain of the switch irq_chip
   * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
-@@ -802,6 +803,7 @@ struct mt7530_priv {
+@@ -807,6 +808,7 @@ struct mt7530_priv {
  	phy_interface_t		p6_interface;
  	phy_interface_t		p5_interface;
  	enum p5_interface_select p5_intf_sel;
@@ -216,7 +216,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u8			mirror_rx;
  	u8			mirror_tx;
  	struct mt7530_port	ports[MT7530_NUM_PORTS];
-@@ -811,7 +813,7 @@ struct mt7530_priv {
+@@ -816,7 +818,7 @@ struct mt7530_priv {
  	int irq;
  	struct irq_domain *irq_domain;
  	u32 irq_enable;
diff --git a/target/linux/generic/backport-6.6/790-08-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch b/target/linux/generic/backport-6.6/790-08-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
index 5ad4e5bb70..3309e248c9 100644
--- a/target/linux/generic/backport-6.6/790-08-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
+++ b/target/linux/generic/backport-6.6/790-08-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch
@@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2735,12 +2735,14 @@ static void mt7530_mac_port_get_caps(str
+@@ -2751,12 +2751,14 @@ static void mt7530_mac_port_get_caps(str
  				     struct phylink_config *config)
  {
  	switch (port) {
@@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		phy_interface_set_rgmii(config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_MII,
  			  config->supported_interfaces);
-@@ -2748,7 +2750,8 @@ static void mt7530_mac_port_get_caps(str
+@@ -2764,7 +2766,8 @@ static void mt7530_mac_port_get_caps(str
  			  config->supported_interfaces);
  		break;
  
@@ -64,7 +64,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_RGMII,
  			  config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -2763,19 +2766,24 @@ static void mt7531_mac_port_get_caps(str
+@@ -2779,19 +2782,24 @@ static void mt7531_mac_port_get_caps(str
  	struct mt7530_priv *priv = ds->priv;
  
  	switch (port) {
@@ -92,7 +92,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		__set_bit(PHY_INTERFACE_MODE_SGMII,
  			  config->supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_1000BASEX,
-@@ -2794,11 +2802,13 @@ static void mt7988_mac_port_get_caps(str
+@@ -2810,11 +2818,13 @@ static void mt7988_mac_port_get_caps(str
  	phy_interface_zero(config->supported_interfaces);
  
  	switch (port) {
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	case 6:
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  config->supported_interfaces);
-@@ -2962,12 +2972,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2978,12 +2988,12 @@ mt753x_phylink_mac_config(struct dsa_swi
  	u32 mcr_cur, mcr_new;
  
  	switch (port) {
@@ -122,7 +122,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (priv->p5_interface == state->interface)
  			break;
  
-@@ -2977,7 +2987,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2993,7 +3003,7 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p5_intf_sel != P5_DISABLED)
  			priv->p5_interface = state->interface;
  		break;
diff --git a/target/linux/generic/backport-6.6/790-09-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch b/target/linux/generic/backport-6.6/790-09-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
index ec51e3f679..9d1b155d4a 100644
--- a/target/linux/generic/backport-6.6/790-09-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
+++ b/target/linux/generic/backport-6.6/790-09-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch
@@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2523,16 +2523,15 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2529,16 +2529,15 @@ mt7530_setup(struct dsa_switch *ds)
  		return ret;
  
  	/* Setup port 5 */
@@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for_each_child_of_node(dn, mac_np) {
  			if (!of_device_is_compatible(mac_np,
  						     "mediatek,eth-mac"))
-@@ -2563,6 +2562,8 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2569,6 +2568,8 @@ mt7530_setup(struct dsa_switch *ds)
  			of_node_put(phy_node);
  			break;
  		}
@@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  #ifdef CONFIG_GPIOLIB
-@@ -2573,8 +2574,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2579,8 +2580,6 @@ mt7530_setup(struct dsa_switch *ds)
  	}
  #endif /* CONFIG_GPIOLIB */
  
diff --git a/target/linux/generic/backport-6.6/790-11-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch b/target/linux/generic/backport-6.6/790-11-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
index 888261373b..4f93d37e96 100644
--- a/target/linux/generic/backport-6.6/790-11-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
+++ b/target/linux/generic/backport-6.6/790-11-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	default:
  		dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
  			priv->p5_intf_sel);
-@@ -2528,8 +2525,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2534,8 +2531,6 @@ mt7530_setup(struct dsa_switch *ds)
  		 * Set priv->p5_intf_sel to the appropriate value if PHY muxing
  		 * is detected.
  		 */
@@ -49,7 +49,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for_each_child_of_node(dn, mac_np) {
  			if (!of_device_is_compatible(mac_np,
  						     "mediatek,eth-mac"))
-@@ -2561,7 +2556,9 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2567,7 +2562,9 @@ mt7530_setup(struct dsa_switch *ds)
  			break;
  		}
  
diff --git a/target/linux/generic/backport-6.6/790-13-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch b/target/linux/generic/backport-6.6/790-13-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
index 1a3e28d836..8058257c53 100644
--- a/target/linux/generic/backport-6.6/790-13-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
+++ b/target/linux/generic/backport-6.6/790-13-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	switch (interface) {
  	case PHY_INTERFACE_MODE_RGMII:
  		trgint = 0;
-@@ -2456,6 +2449,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2458,6 +2451,12 @@ mt7530_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
diff --git a/target/linux/generic/backport-6.6/790-15-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch b/target/linux/generic/backport-6.6/790-15-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
index 5d79a7f3c4..330a92e7d4 100644
--- a/target/linux/generic/backport-6.6/790-15-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
+++ b/target/linux/generic/backport-6.6/790-15-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch
@@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return 0;
  }
  
-@@ -2810,11 +2814,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2826,11 +2830,10 @@ mt7530_mac_config(struct dsa_switch *ds,
  {
  	struct mt7530_priv *priv = ds->priv;
  
diff --git a/target/linux/generic/backport-6.6/790-16-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch b/target/linux/generic/backport-6.6/790-16-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
index 0c7d6132a2..dcf1afa16e 100644
--- a/target/linux/generic/backport-6.6/790-16-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
+++ b/target/linux/generic/backport-6.6/790-16-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch
@@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void
  mt7531_pll_setup(struct mt7530_priv *priv)
  {
-@@ -2801,14 +2789,6 @@ static void mt7988_mac_port_get_caps(str
+@@ -2817,14 +2805,6 @@ static void mt7988_mac_port_get_caps(str
  }
  
  static int
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2973,8 +2953,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2989,8 +2969,6 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p6_interface == state->interface)
  			break;
  
@@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (mt753x_mac_config(ds, port, mode, state) < 0)
  			goto unsupported;
  
-@@ -3291,11 +3269,6 @@ mt753x_conduit_state_change(struct dsa_s
+@@ -3307,11 +3285,6 @@ mt753x_conduit_state_change(struct dsa_s
  	mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
  }
  
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mt7988_setup(struct dsa_switch *ds)
  {
  	struct mt7530_priv *priv = ds->priv;
-@@ -3359,7 +3332,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3375,7 +3348,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7530_phy_write_c22,
  		.phy_read_c45 = mt7530_phy_read_c45,
  		.phy_write_c45 = mt7530_phy_write_c45,
@@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3371,7 +3343,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3387,7 +3359,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7530_phy_write_c22,
  		.phy_read_c45 = mt7530_phy_read_c45,
  		.phy_write_c45 = mt7530_phy_write_c45,
@@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.mac_port_get_caps = mt7530_mac_port_get_caps,
  		.mac_port_config = mt7530_mac_config,
  	},
-@@ -3383,7 +3354,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3399,7 +3370,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7531_ind_c22_phy_write,
  		.phy_read_c45 = mt7531_ind_c45_phy_read,
  		.phy_write_c45 = mt7531_ind_c45_phy_write,
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.cpu_port_config = mt7531_cpu_port_config,
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
-@@ -3396,7 +3366,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3412,7 +3382,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7531_ind_c22_phy_write,
  		.phy_read_c45 = mt7531_ind_c45_phy_read,
  		.phy_write_c45 = mt7531_ind_c45_phy_write,
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		.cpu_port_config = mt7988_cpu_port_config,
  		.mac_port_get_caps = mt7988_mac_port_get_caps,
  		.mac_port_config = mt7988_mac_config,
-@@ -3426,9 +3395,8 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3442,9 +3411,8 @@ mt7530_probe_common(struct mt7530_priv *
  	/* Sanity check if these required device operations are filled
  	 * properly.
  	 */
@@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -729,8 +729,6 @@ struct mt753x_pcs {
+@@ -734,8 +734,6 @@ struct mt753x_pcs {
   * @phy_write_c22:	Holding the way writing PHY port using C22
   * @phy_read_c45:	Holding the way reading PHY port using C45
   * @phy_write_c45:	Holding the way writing PHY port using C45
@@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @phy_mode_supported:	Check if the PHY type is being supported on a certain
   *			port
   * @mac_port_validate:	Holding the way to set addition validate type for a
-@@ -751,7 +749,6 @@ struct mt753x_info {
+@@ -756,7 +754,6 @@ struct mt753x_info {
  			    int regnum);
  	int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
  			     int regnum, u16 val);
diff --git a/target/linux/generic/backport-6.6/790-17-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch b/target/linux/generic/backport-6.6/790-17-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
index 19577a375b..f6c2919eaf 100644
--- a/target/linux/generic/backport-6.6/790-17-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
+++ b/target/linux/generic/backport-6.6/790-17-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch
@@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2774,7 +2774,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2790,7 +2790,7 @@ static void mt7988_mac_port_get_caps(str
  
  	switch (port) {
  	/* Ports which are connected to switch PHYs. There is no MII pinout. */
diff --git a/target/linux/generic/backport-6.6/790-18-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch b/target/linux/generic/backport-6.6/790-18-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
index 1b45cc50ce..66a9158507 100644
--- a/target/linux/generic/backport-6.6/790-18-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
+++ b/target/linux/generic/backport-6.6/790-18-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2770,8 +2770,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2786,8 +2786,6 @@ static void mt7531_mac_port_get_caps(str
  static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
  				     struct phylink_config *config)
  {
diff --git a/target/linux/generic/backport-6.6/790-19-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch b/target/linux/generic/backport-6.6/790-19-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
index 90cdf29d8f..abc1108116 100644
--- a/target/linux/generic/backport-6.6/790-19-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
+++ b/target/linux/generic/backport-6.6/790-19-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch
@@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2853,17 +2853,6 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2869,17 +2869,6 @@ static bool mt753x_is_mac_port(u32 port)
  }
  
  static int
@@ -51,7 +51,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2903,6 +2892,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2919,6 +2908,9 @@ mt753x_mac_config(struct dsa_switch *ds,
  {
  	struct mt7530_priv *priv = ds->priv;
  
@@ -61,7 +61,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	return priv->info->mac_port_config(ds, port, mode, state->interface);
  }
  
-@@ -3366,7 +3358,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3382,7 +3374,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c45 = mt7531_ind_c45_phy_write,
  		.cpu_port_config = mt7988_cpu_port_config,
  		.mac_port_get_caps = mt7988_mac_port_get_caps,
@@ -69,7 +69,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	},
  };
  EXPORT_SYMBOL_GPL(mt753x_table);
-@@ -3394,8 +3385,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3410,8 +3401,7 @@ mt7530_probe_common(struct mt7530_priv *
  	 * properly.
  	 */
  	if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
diff --git a/target/linux/generic/backport-6.6/790-20-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch b/target/linux/generic/backport-6.6/790-20-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
index 2d483ab403..d6eaaaf1d5 100644
--- a/target/linux/generic/backport-6.6/790-20-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
+++ b/target/linux/generic/backport-6.6/790-20-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2252,7 +2252,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2254,7 +2254,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
  	}
  
  	/* This register must be set for MT7530 to properly fire interrupts */
diff --git a/target/linux/generic/backport-6.6/790-21-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch b/target/linux/generic/backport-6.6/790-21-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
index 73519c3e2a..735775d97a 100644
--- a/target/linux/generic/backport-6.6/790-21-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
+++ b/target/linux/generic/backport-6.6/790-21-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch
@@ -22,7 +22,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2648,14 +2648,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2657,14 +2657,12 @@ mt7531_setup(struct dsa_switch *ds)
  	val = mt7530_read(priv, MT7531_TOP_SIG_SR);
  	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
  
diff --git a/target/linux/generic/backport-6.6/790-22-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch b/target/linux/generic/backport-6.6/790-22-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
index 0b2b3b5b33..c9159a1c68 100644
--- a/target/linux/generic/backport-6.6/790-22-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
+++ b/target/linux/generic/backport-6.6/790-22-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch
@@ -36,7 +36,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2784,7 +2784,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2800,7 +2800,7 @@ static void mt7988_mac_port_get_caps(str
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2794,22 +2794,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2810,22 +2810,14 @@ mt7530_mac_config(struct dsa_switch *ds,
  		mt7530_setup_port5(priv->ds, interface);
  	else if (port == 6)
  		mt7530_setup_port6(priv->ds, interface);
@@ -71,7 +71,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
  	val |= GP_CLK_EN;
  	val &= ~GP_MODE_MASK;
-@@ -2837,20 +2829,14 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2853,20 +2845,14 @@ static int mt7531_rgmii_setup(struct mt7
  		case PHY_INTERFACE_MODE_RGMII_ID:
  			break;
  		default:
@@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  		  phy_interface_t interface)
  {
-@@ -2858,42 +2844,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2874,42 +2860,21 @@ mt7531_mac_config(struct dsa_switch *ds,
  	struct phy_device *phydev;
  	struct dsa_port *dp;
  
@@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static struct phylink_pcs *
-@@ -2922,17 +2887,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2938,17 +2903,11 @@ mt753x_phylink_mac_config(struct dsa_swi
  	u32 mcr_cur, mcr_new;
  
  	switch (port) {
@@ -162,7 +162,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  		if (priv->p5_intf_sel != P5_DISABLED)
  			priv->p5_interface = state->interface;
-@@ -2941,16 +2900,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2957,16 +2916,10 @@ mt753x_phylink_mac_config(struct dsa_swi
  		if (priv->p6_interface == state->interface)
  			break;
  
@@ -180,7 +180,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
-@@ -3033,7 +2986,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3049,7 +3002,6 @@ mt7531_cpu_port_config(struct dsa_switch
  	struct mt7530_priv *priv = ds->priv;
  	phy_interface_t interface;
  	int speed;
@@ -188,7 +188,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	switch (port) {
  	case 5:
-@@ -3058,9 +3010,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3074,9 +3026,8 @@ mt7531_cpu_port_config(struct dsa_switch
  	else
  		speed = SPEED_1000;
  
@@ -202,7 +202,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -755,9 +755,9 @@ struct mt753x_info {
+@@ -760,9 +760,9 @@ struct mt753x_info {
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
  				  phy_interface_t interface,
  				  unsigned long *supported);
diff --git a/target/linux/generic/backport-6.6/790-23-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch b/target/linux/generic/backport-6.6/790-23-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
index 27f29beee1..c52cb0d5ea 100644
--- a/target/linux/generic/backport-6.6/790-23-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
+++ b/target/linux/generic/backport-6.6/790-23-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch
@@ -92,10 +92,10 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
 -	priv->p6_interface = PHY_INTERFACE_MODE_NA;
 -
- 	mt753x_trap_frames(priv);
+ 	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ 		mt7530_pll_setup(priv);
  
- 	/* Enable and reset MIB counters */
-@@ -2474,9 +2462,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2477,9 +2465,7 @@ mt7530_setup(struct dsa_switch *ds)
  		mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  
  		if (dsa_is_cpu_port(ds, i)) {
@@ -106,7 +106,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		} else {
  			mt7530_port_disable(ds, i);
  
-@@ -2580,9 +2566,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2586,9 +2572,7 @@ mt7531_setup_common(struct dsa_switch *d
  		mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
  
  		if (dsa_is_cpu_port(ds, i)) {
@@ -117,7 +117,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		} else {
  			mt7530_port_disable(ds, i);
  
-@@ -2671,10 +2655,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2680,10 +2664,6 @@ mt7531_setup(struct dsa_switch *ds)
  	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
  		   MT7531_GPIO0_INTERRUPT);
  
@@ -125,10 +125,10 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 -	priv->p5_interface = PHY_INTERFACE_MODE_NA;
 -	priv->p6_interface = PHY_INTERFACE_MODE_NA;
 -
- 	/* Enable PHY core PLL, since phy_device has not yet been created
- 	 * provided for phy_[read,write]_mmd_indirect is called, we provide
- 	 * our own mt7531_ind_mmd_phy_[read,write] to complete this
-@@ -2886,26 +2866,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ 	/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ 	 * phy_device has not yet been created provided for
+ 	 * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2902,26 +2882,9 @@ mt753x_phylink_mac_config(struct dsa_swi
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr_cur, mcr_new;
  
@@ -156,7 +156,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
  	mcr_new = mcr_cur;
  	mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -2941,17 +2904,10 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2957,17 +2920,10 @@ static void mt753x_phylink_mac_link_up(s
  
  	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
  
@@ -176,7 +176,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		mcr |= PMCR_FORCE_SPEED_1000;
  		break;
  	case SPEED_100:
-@@ -2969,6 +2925,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2985,6 +2941,7 @@ static void mt753x_phylink_mac_link_up(s
  	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
  		switch (speed) {
  		case SPEED_1000:
@@ -184,7 +184,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  			mcr |= PMCR_FORCE_EEE1G;
  			break;
  		case SPEED_100:
-@@ -2980,61 +2937,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2996,61 +2953,6 @@ static void mt753x_phylink_mac_link_up(s
  	mt7530_set(priv, MT7530_PMCR_P(port), mcr);
  }
  
@@ -246,7 +246,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
  				    struct phylink_config *config)
  {
-@@ -3293,7 +3195,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3309,7 +3211,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7531_ind_c22_phy_write,
  		.phy_read_c45 = mt7531_ind_c45_phy_read,
  		.phy_write_c45 = mt7531_ind_c45_phy_write,
@@ -254,7 +254,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		.mac_port_get_caps = mt7531_mac_port_get_caps,
  		.mac_port_config = mt7531_mac_config,
  	},
-@@ -3305,7 +3206,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3321,7 +3222,6 @@ const struct mt753x_info mt753x_table[]
  		.phy_write_c22 = mt7531_ind_c22_phy_write,
  		.phy_read_c45 = mt7531_ind_c45_phy_read,
  		.phy_write_c45 = mt7531_ind_c45_phy_write,
@@ -264,7 +264,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -336,13 +336,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
  					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
  					 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
  					 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
@@ -278,7 +278,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  #define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
  #define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
-@@ -749,7 +742,6 @@ struct mt753x_info {
+@@ -754,7 +747,6 @@ struct mt753x_info {
  			    int regnum);
  	int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
  			     int regnum, u16 val);
@@ -286,7 +286,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
  				  struct phylink_config *config);
  	void (*mac_port_validate)(struct dsa_switch *ds, int port,
-@@ -775,7 +767,6 @@ struct mt753x_info {
+@@ -780,7 +772,6 @@ struct mt753x_info {
   * @ports:		Holding the state among ports
   * @reg_mutex:		The lock for protecting among process accessing
   *			registers
@@ -294,7 +294,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
   * @p5_intf_sel:	Holding the current port 5 interface select
   * @p5_sgmii:		Flag for distinguishing if port 5 of the MT7531 switch
   *			has got SGMII
-@@ -797,8 +788,6 @@ struct mt7530_priv {
+@@ -802,8 +793,6 @@ struct mt7530_priv {
  	const struct mt753x_info *info;
  	unsigned int		id;
  	bool			mcm;
diff --git a/target/linux/generic/backport-6.6/790-24-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch b/target/linux/generic/backport-6.6/790-24-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
index 97b63b6df5..7fe77c506e 100644
--- a/target/linux/generic/backport-6.6/790-24-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
+++ b/target/linux/generic/backport-6.6/790-24-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch
@@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2831,16 +2831,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2847,16 +2847,6 @@ mt7531_mac_config(struct dsa_switch *ds,
  	}
  }
  
@@ -35,7 +35,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static struct phylink_pcs *
  mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
  			      phy_interface_t interface)
-@@ -2866,8 +2856,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2882,8 +2872,8 @@ mt753x_phylink_mac_config(struct dsa_swi
  	struct mt7530_priv *priv = ds->priv;
  	u32 mcr_cur, mcr_new;
  
diff --git a/target/linux/generic/backport-6.6/790-25-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch b/target/linux/generic/backport-6.6/790-25-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
index c130f2aaca..bd5c9b9772 100644
--- a/target/linux/generic/backport-6.6/790-25-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
+++ b/target/linux/generic/backport-6.6/790-25-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -3009,17 +3009,9 @@ static int
+@@ -3025,17 +3025,9 @@ static int
  mt753x_setup(struct dsa_switch *ds)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	if (ret)
  		return ret;
  
-@@ -3031,6 +3023,14 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3047,6 +3039,14 @@ mt753x_setup(struct dsa_switch *ds)
  	if (ret && priv->irq)
  		mt7530_free_irq_common(priv);
  
diff --git a/target/linux/generic/backport-6.6/790-26-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch b/target/linux/generic/backport-6.6/790-26-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
index f07c6bd575..348c35e1ac 100644
--- a/target/linux/generic/backport-6.6/790-26-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
+++ b/target/linux/generic/backport-6.6/790-26-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch
@@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mutex_unlock(&priv->reg_mutex);
  }
-@@ -2454,6 +2452,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2457,6 +2455,12 @@ mt7530_setup(struct dsa_switch *ds)
  	mt7530_mib_reset(ds);
  
  	for (i = 0; i < MT7530_NUM_PORTS; i++) {
@@ -53,7 +53,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		/* Disable forwarding by default on all ports */
  		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
  			   PCR_MATRIX_CLR);
-@@ -2556,6 +2560,12 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2562,6 +2566,12 @@ mt7531_setup_common(struct dsa_switch *d
  		     UNU_FFP_MASK);
  
  	for (i = 0; i < MT7530_NUM_PORTS; i++) {
diff --git a/target/linux/generic/backport-6.6/790-27-v6.9-net-dsa-mt7530-simplify-link-operations.patch b/target/linux/generic/backport-6.6/790-27-v6.9-net-dsa-mt7530-simplify-link-operations.patch
index 29536df9b8..54f5a59a64 100644
--- a/target/linux/generic/backport-6.6/790-27-v6.9-net-dsa-mt7530-simplify-link-operations.patch
+++ b/target/linux/generic/backport-6.6/790-27-v6.9-net-dsa-mt7530-simplify-link-operations.patch
@@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2864,23 +2864,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2880,23 +2880,13 @@ mt753x_phylink_mac_config(struct dsa_swi
  			  const struct phylink_link_state *state)
  {
  	struct mt7530_priv *priv = ds->priv;
@@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
 --- a/drivers/net/dsa/mt7530.h
 +++ b/drivers/net/dsa/mt7530.h
-@@ -329,8 +329,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
  					 MT7531_FORCE_DPX | \
  					 MT7531_FORCE_RX_FC | \
  					 MT7531_FORCE_TX_FC)
diff --git a/target/linux/generic/backport-6.6/790-28-v6.9-net-dsa-mt7530-disable-LEDs-before-reset.patch b/target/linux/generic/backport-6.6/790-28-v6.9-net-dsa-mt7530-disable-LEDs-before-reset.patch
index 9356a54c71..af39929dba 100644
--- a/target/linux/generic/backport-6.6/790-28-v6.9-net-dsa-mt7530-disable-LEDs-before-reset.patch
+++ b/target/linux/generic/backport-6.6/790-28-v6.9-net-dsa-mt7530-disable-LEDs-before-reset.patch
@@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2389,6 +2389,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,6 +2391,12 @@ mt7530_setup(struct dsa_switch *ds)
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.6/790-29-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch b/target/linux/generic/backport-6.6/790-29-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch
deleted file mode 100644
index b8124cad23..0000000000
--- a/target/linux/generic/backport-6.6/790-29-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From fa14c96eab3ec5b7cb44b06c0a54a851849a9810 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Wed, 20 Mar 2024 23:45:30 +0300
-Subject: [PATCH 29/30] net: dsa: mt7530: fix improper frames on all 25MHz and
- 40MHz XTAL MT7530
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530 switch after reset initialises with a core clock frequency that
-works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
-frequency must be set to 500MHz.
-
-The mt7530_pll_setup() function is responsible of setting the core clock
-frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
-causes MT7530 switch with 25MHz XTAL to egress and ingress frames
-improperly.
-
-Introduce a check to run it only on MT7530 with 40MHz XTAL.
-
-The core clock frequency is set by writing to a switch PHY's register.
-Access to the PHY's register is done via the MDIO bus the switch is also
-on. Therefore, it works only when the switch makes switch PHYs listen on
-the MDIO bus the switch is on. This is controlled either by the state of
-the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
-modifiable trap register.
-
-When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
-accessing PHY registers via the PHY indirect access control register of the
-switch.
-
-When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
-accessing PHY registers via the MDIO bus the switch is on.
-
-For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
-the core clock frequency won't be set to 500MHz, causing the switch to
-egress and ingress frames improperly.
-
-Run mt7530_pll_setup() after PHY direct access is set on the modifiable
-trap register.
-
-With these two changes, all MT7530 switches with 25MHz and 40MHz, and
-P1_LED_1 pulled high or low, will egress and ingress frames properly.
-
-Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/dsa/mt7530.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2435,8 +2435,6 @@ mt7530_setup(struct dsa_switch *ds)
- 		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- 		     SYS_CTRL_REG_RST);
- 
--	mt7530_pll_setup(priv);
--
- 	/* Lower Tx driving for TRGMII path */
- 	for (i = 0; i < NUM_TRGMII_CTRL; i++)
- 		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
-@@ -2452,6 +2450,9 @@ mt7530_setup(struct dsa_switch *ds)
- 	val |= MHWTRAP_MANUAL;
- 	mt7530_write(priv, MT7530_MHWTRAP, val);
- 
-+	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
-+		mt7530_pll_setup(priv);
-+
- 	mt753x_trap_frames(priv);
- 
- 	/* Enable and reset MIB counters */
diff --git a/target/linux/generic/backport-6.6/790-30-v6.9-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch b/target/linux/generic/backport-6.6/790-30-v6.9-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch
index 6c813ed3ff..c2eb3a2801 100644
--- a/target/linux/generic/backport-6.6/790-30-v6.9-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch
+++ b/target/linux/generic/backport-6.6/790-30-v6.9-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch
@@ -139,7 +139,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2389,12 +2389,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,12 +2391,6 @@ mt7530_setup(struct dsa_switch *ds)
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.6/790-31-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch b/target/linux/generic/backport-6.6/790-31-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch
deleted file mode 100644
index 9a4d4a918a..0000000000
--- a/target/linux/generic/backport-6.6/790-31-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 8 Apr 2024 10:08:53 +0300
-Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
- all boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
-enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
-(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
-the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
-SkyLake Huang (黃啟澤) from MediaTek for providing information on the
-internal EEE switch bit.
-
-There are existing boards that were not designed to pull the pin low.
-Because of that, the EEE status currently depends on the board design.
-
-The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
-used to control an LED. Once the bit is unset, the pin will be low. That
-will make the active low LED turn on. The pin is controlled by the switch
-PHY. It seems that the PHY controls the pin in the way that it inverts the
-pin state. That means depending on the wiring of the LED connected to
-LAN2LED0 on the board, the LED may be on without an active link.
-
-To not cause this unwanted behaviour whilst enabling EEE on all boards, set
-the internal EEE switch bit on the CORE_PLL_GROUP4 register.
-
-My testing on MT7531 shows a certain amount of traffic loss when EEE is
-enabled. That said, I haven't come across a board that enables EEE. So
-enable EEE on the switch MACs but disable EEE advertisement on the switch
-PHYs. This way, we don't change the behaviour of the majority of the boards
-that have this switch. The mediatek-ge PHY driver already disables EEE
-advertisement on the switch PHYs but my testing shows that it is somehow
-enabled afterwards. Disabling EEE advertisement before the PHY driver
-initialises keeps it off.
-
-With this change, EEE can now be enabled using ethtool.
-
-Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
- drivers/net/dsa/mt7530.h |  1 +
- 2 files changed, 13 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2666,18 +2666,25 @@ mt7531_setup(struct dsa_switch *ds)
- 	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- 		   MT7531_GPIO0_INTERRUPT);
- 
--	/* Enable PHY core PLL, since phy_device has not yet been created
--	 * provided for phy_[read,write]_mmd_indirect is called, we provide
--	 * our own mt7531_ind_mmd_phy_[read,write] to complete this
--	 * function.
-+	/* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
-+	 * phy_device has not yet been created provided for
-+	 * phy_[read,write]_mmd_indirect is called, we provide our own
-+	 * mt7531_ind_mmd_phy_[read,write] to complete this function.
- 	 */
- 	val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
- 				      MDIO_MMD_VEND2, CORE_PLL_GROUP4);
--	val |= MT7531_PHY_PLL_BYPASS_MODE;
-+	val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
- 	val &= ~MT7531_PHY_PLL_OFF;
- 	mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
- 				 CORE_PLL_GROUP4, val);
- 
-+	/* Disable EEE advertisement on the switch PHYs. */
-+	for (i = MT753X_CTRL_PHY_ADDR;
-+	     i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
-+		mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
-+					 0);
-+	}
-+
- 	mt7531_setup_common(ds);
- 
- 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -621,6 +621,7 @@ enum mt7531_clk_skew {
- #define  RG_SYSPLL_DDSFBK_EN		BIT(12)
- #define  RG_SYSPLL_BIAS_EN		BIT(11)
- #define  RG_SYSPLL_BIAS_LPF_EN		BIT(10)
-+#define  MT7531_RG_SYSPLL_DMY2		BIT(6)
- #define  MT7531_PHY_PLL_OFF		BIT(5)
- #define  MT7531_PHY_PLL_BYPASS_MODE	BIT(4)
- 
diff --git a/target/linux/generic/backport-6.6/790-33-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch b/target/linux/generic/backport-6.6/790-33-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch
index 7cbdc9e50d..5eade735ec 100644
--- a/target/linux/generic/backport-6.6/790-33-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch
+++ b/target/linux/generic/backport-6.6/790-33-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch
@@ -19,7 +19,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2850,28 +2850,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2858,28 +2858,34 @@ mt7531_mac_config(struct dsa_switch *ds,
  }
  
  static struct phylink_pcs *
@@ -60,7 +60,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if ((port == 5 || port == 6) && priv->info->mac_port_config)
  		priv->info->mac_port_config(ds, port, mode, state->interface);
-@@ -2881,23 +2887,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2889,23 +2895,25 @@ mt753x_phylink_mac_config(struct dsa_swi
  		mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
  }
  
@@ -92,7 +92,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	u32 mcr;
  
  	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
-@@ -2932,7 +2940,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2940,7 +2948,7 @@ static void mt753x_phylink_mac_link_up(s
  		}
  	}
  
@@ -101,7 +101,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
-@@ -3152,16 +3160,19 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3160,16 +3168,19 @@ const struct dsa_switch_ops mt7530_switc
  	.port_mirror_add	= mt753x_port_mirror_add,
  	.port_mirror_del	= mt753x_port_mirror_del,
  	.phylink_get_caps	= mt753x_phylink_get_caps,
@@ -125,7 +125,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  const struct mt753x_info mt753x_table[] = {
  	[ID_MT7621] = {
  		.id = ID_MT7621,
-@@ -3239,6 +3250,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3247,6 +3258,7 @@ mt7530_probe_common(struct mt7530_priv *
  	priv->dev = dev;
  	priv->ds->priv = priv;
  	priv->ds->ops = &mt7530_switch_ops;
diff --git a/target/linux/generic/backport-6.6/790-34-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch b/target/linux/generic/backport-6.6/790-34-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch
deleted file mode 100644
index 11f9a68cee..0000000000
--- a/target/linux/generic/backport-6.6/790-34-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From d4097ddef078a113643a6dcde01e99741f852adb Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 13 Apr 2024 16:01:39 +0300
-Subject: [PATCH 2/5] net: dsa: mt7530: fix mirroring frames received on local
- port
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This switch intellectual property provides a bit on the ARL global control
-register which controls allowing mirroring frames which are received on the
-local port (monitor port). This bit is unset after reset.
-
-This ability must be enabled to fully support the port mirroring feature on
-this switch intellectual property.
-
-Therefore, this patch fixes the traffic not being reflected on a port,
-which would be configured like below:
-
-  tc qdisc add dev swp0 clsact
-
-  tc filter add dev swp0 ingress matchall skip_sw \
-  action mirred egress mirror dev swp0
-
-As a side note, this configuration provides the hairpinning feature for a
-single port.
-
-Fixes: 37feab6076aa ("net: dsa: mt7530: add support for port mirroring")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 6 ++++++
- drivers/net/dsa/mt7530.h | 4 ++++
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2480,6 +2480,9 @@ mt7530_setup(struct dsa_switch *ds)
- 			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- 	}
- 
-+	/* Allow mirroring frames received on the local port (monitor port). */
-+	mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
- 	ret = mt7530_setup_vlan0(priv);
- 	if (ret)
-@@ -2591,6 +2594,9 @@ mt7531_setup_common(struct dsa_switch *d
- 			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
- 	}
- 
-+	/* Allow mirroring frames received on the local port (monitor port). */
-+	mt7530_set(priv, MT753X_AGC, LOCAL_EN);
-+
- 	/* Flush the FDB table */
- 	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
- 	if (ret < 0)
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -32,6 +32,10 @@ enum mt753x_id {
- #define SYSC_REG_RSTCTRL		0x34
- #define  RESET_MCM			BIT(2)
- 
-+/* Register for ARL global control */
-+#define MT753X_AGC			0xc
-+#define  LOCAL_EN			BIT(7)
-+
- /* Registers to mac forward control for unknown frames */
- #define MT7530_MFC			0x10
- #define  BC_FFP(x)			(((x) & 0xff) << 24)
diff --git a/target/linux/generic/backport-6.6/790-35-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch b/target/linux/generic/backport-6.6/790-35-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch
deleted file mode 100644
index d5ba8ef1c4..0000000000
--- a/target/linux/generic/backport-6.6/790-35-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 019a17a5e76940ea86114838d1d638d4dc8d3750 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 13 Apr 2024 16:01:40 +0300
-Subject: [PATCH 3/5] net: dsa: mt7530: fix port mirroring for MT7988 SoC
- switch
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
-v0.1" document shows bits 16 to 18 as the MIRROR_PORT field of the CPU
-forward control register. Currently, the MT7530 DSA subdriver configures
-bits 0 to 2 of the CPU forward control register which breaks the port
-mirroring feature for the MT7988 SoC switch.
-
-Fix this by using the MT7531_MIRROR_PORT_GET() and MT7531_MIRROR_PORT_SET()
-macros which utilise the correct bits.
-
-Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Acked-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 10 ++++++----
- 1 file changed, 6 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1883,14 +1883,16 @@ mt7530_port_vlan_del(struct dsa_switch *
- 
- static int mt753x_mirror_port_get(unsigned int id, u32 val)
- {
--	return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
--				   MIRROR_PORT(val);
-+	return (id == ID_MT7531 || id == ID_MT7988) ?
-+		       MT7531_MIRROR_PORT_GET(val) :
-+		       MIRROR_PORT(val);
- }
- 
- static int mt753x_mirror_port_set(unsigned int id, u32 val)
- {
--	return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
--				   MIRROR_PORT(val);
-+	return (id == ID_MT7531 || id == ID_MT7988) ?
-+		       MT7531_MIRROR_PORT_SET(val) :
-+		       MIRROR_PORT(val);
- }
- 
- static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
diff --git a/target/linux/generic/pending-6.6/745-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch b/target/linux/generic/backport-6.6/790-38-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
index 44cf60cf14..44cf60cf14 100644
--- a/target/linux/generic/pending-6.6/745-01-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
+++ b/target/linux/generic/backport-6.6/790-38-v6.10-net-dsa-mt7530-disable-EEE-abilities-on-failure-on-M.patch
diff --git a/target/linux/generic/pending-6.6/745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/backport-6.6/790-39-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
index 89fad45dd5..89fad45dd5 100644
--- a/target/linux/generic/pending-6.6/745-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
+++ b/target/linux/generic/backport-6.6/790-39-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
diff --git a/target/linux/generic/pending-6.6/745-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/backport-6.6/790-40-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
index 601171a594..601171a594 100644
--- a/target/linux/generic/pending-6.6/745-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
+++ b/target/linux/generic/backport-6.6/790-40-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
diff --git a/target/linux/generic/pending-6.6/745-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/backport-6.6/790-41-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
index 948baf58d0..948baf58d0 100644
--- a/target/linux/generic/pending-6.6/745-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
+++ b/target/linux/generic/backport-6.6/790-41-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
diff --git a/target/linux/generic/pending-6.6/745-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/backport-6.6/790-42-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
index a5d293b509..a5d293b509 100644
--- a/target/linux/generic/pending-6.6/745-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
+++ b/target/linux/generic/backport-6.6/790-42-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
diff --git a/target/linux/generic/pending-6.6/745-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/backport-6.6/790-43-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
index 1f66575f02..1f66575f02 100644
--- a/target/linux/generic/pending-6.6/745-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
+++ b/target/linux/generic/backport-6.6/790-43-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
diff --git a/target/linux/generic/pending-6.6/745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/backport-6.6/790-44-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
index f7802c02db..f7802c02db 100644
--- a/target/linux/generic/pending-6.6/745-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
+++ b/target/linux/generic/backport-6.6/790-44-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
diff --git a/target/linux/generic/pending-6.6/745-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/backport-6.6/790-45-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
index 2eaa77c8cf..2eaa77c8cf 100644
--- a/target/linux/generic/pending-6.6/745-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
+++ b/target/linux/generic/backport-6.6/790-45-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
diff --git a/target/linux/generic/pending-6.6/745-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/backport-6.6/790-46-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
index 9a592c759d..9a592c759d 100644
--- a/target/linux/generic/pending-6.6/745-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
+++ b/target/linux/generic/backport-6.6/790-46-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
diff --git a/target/linux/generic/pending-6.6/745-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/backport-6.6/790-47-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
index bc84ecb778..bc84ecb778 100644
--- a/target/linux/generic/pending-6.6/745-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
+++ b/target/linux/generic/backport-6.6/790-47-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
diff --git a/target/linux/generic/pending-6.6/745-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/backport-6.6/790-48-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
index e75db9ba30..e75db9ba30 100644
--- a/target/linux/generic/pending-6.6/745-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
+++ b/target/linux/generic/backport-6.6/790-48-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
diff --git a/target/linux/generic/pending-6.6/745-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch b/target/linux/generic/backport-6.6/790-49-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
index d083708548..d083708548 100644
--- a/target/linux/generic/pending-6.6/745-12-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
+++ b/target/linux/generic/backport-6.6/790-49-v6.10-net-dsa-mt7530-get-rid-of-mac_port_validate-member-o.patch
diff --git a/target/linux/generic/pending-6.6/745-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/backport-6.6/790-50-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
index f63d4d7705..f63d4d7705 100644
--- a/target/linux/generic/pending-6.6/745-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
+++ b/target/linux/generic/backport-6.6/790-50-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
diff --git a/target/linux/generic/pending-6.6/745-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/backport-6.6/790-51-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
index 9ba12b1269..9ba12b1269 100644
--- a/target/linux/generic/pending-6.6/745-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
+++ b/target/linux/generic/backport-6.6/790-51-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
diff --git a/target/linux/generic/pending-6.6/745-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/backport-6.6/790-52-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
index 58c3e0bc3c..58c3e0bc3c 100644
--- a/target/linux/generic/pending-6.6/745-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
+++ b/target/linux/generic/backport-6.6/790-52-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
diff --git a/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch
new file mode 100644
index 0000000000..cee3d01728
--- /dev/null
+++ b/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch
@@ -0,0 +1,45 @@
+From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sun, 28 Apr 2024 12:19:58 +0300
+Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is
+ being used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DSA initalises the ds->num_ports amount of ports in
+dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5
+won't be defined in the device tree. Because of this, the type member of
+the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED.
+The dsa_port_setup() function calls ds->ops->port_disable() when the port
+type is DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being
+used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1220,7 +1220,8 @@ mt7530_port_disable(struct dsa_switch *d
+ 	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ 		return;
+ 
+-	if (port == 5)
++	/* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */
++	if (port == 5 && priv->p5_mode == GMAC5)
+ 		mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ 	else if (port == 6)
+ 		mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
diff --git a/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch b/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch
new file mode 100644
index 0000000000..d369c4e05e
--- /dev/null
+++ b/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch
@@ -0,0 +1,45 @@
+From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 30 Apr 2024 08:01:33 +0300
+Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
+direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
+bus the switch listens on. The PHY muxing feature makes use of this.
+
+This is problematic as the PHY may be attached before the switch is
+initialised, in which case, the PHY will fail to be attached.
+
+Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
+of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of
+the switch on the device tree. Extend the check to detect PHY muxing when
+the PHY is defined on the MDIO bus of the switch on the device tree.
+
+When the PHY is described this way, the switch will be initialised first,
+then the switch MDIO bus will be registered. Only after these steps, the
+PHY will be attached.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2484,7 +2484,8 @@ mt7530_setup(struct dsa_switch *ds)
+ 			if (!phy_node)
+ 				continue;
+ 
+-			if (phy_node->parent == priv->dev->of_node->parent) {
++			if (phy_node->parent == priv->dev->of_node->parent ||
++			    phy_node->parent->parent == priv->dev->of_node) {
+ 				ret = of_get_phy_mode(mac_np, &interface);
+ 				if (ret && ret != -ENODEV) {
+ 					of_node_put(mac_np);
diff --git a/target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch b/target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch
new file mode 100644
index 0000000000..5b627cf449
--- /dev/null
+++ b/target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch
@@ -0,0 +1,1140 @@
+From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001
+From: Eric Woudstra <ericwouds@gmail.com>
+Date: Tue, 26 Mar 2024 17:23:05 +0100
+Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver
+
+Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports
+100/1000/2500 Mbps with auto negotiation only.
+
+The driver uses two firmware files, for which updated versions are added to
+linux-firmware already.
+
+Note: At phy-address + 8 there is another device on the mdio bus, that
+belongs to the EN881H. While the original driver writes to it, Airoha
+has confirmed this is not needed. Therefore, communication with this
+device is not included in this driver.
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/Makefile      |    1 +
+ drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1092 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -68,6 +68,11 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AIR_EN8811H_PHY
++	tristate "Airoha EN8811H 2.5 Gigabit PHY"
++	help
++	  Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,6 +34,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1086 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <linux/wordpart.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID		0x03a2a411
++
++#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM	0x00000000
++#define AIR_FW_ADDR_DSP	0x00100000
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS		0x1d
++#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
++#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
++#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
++#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
++
++#define AIR_EXT_PAGE_ACCESS		0x1f
++#define   AIR_PHY_PAGE_STANDARD			0x0000
++#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
++
++/* MII Registers Page 4*/
++#define AIR_BPBUS_MODE			0x10
++#define   AIR_BPBUS_MODE_ADDR_FIXED		0x0000
++#define   AIR_BPBUS_MODE_ADDR_INCR		BIT(15)
++#define AIR_BPBUS_WR_ADDR_HIGH		0x11
++#define AIR_BPBUS_WR_ADDR_LOW		0x12
++#define AIR_BPBUS_WR_DATA_HIGH		0x13
++#define AIR_BPBUS_WR_DATA_LOW		0x14
++#define AIR_BPBUS_RD_ADDR_HIGH		0x15
++#define AIR_BPBUS_RD_ADDR_LOW		0x16
++#define AIR_BPBUS_RD_DATA_HIGH		0x17
++#define AIR_BPBUS_RD_DATA_LOW		0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS		0x8009
++#define   EN8811H_PHY_READY			0x02
++
++#define AIR_PHY_MCU_CMD_1		0x800c
++#define AIR_PHY_MCU_CMD_1_MODE1			0x0
++#define AIR_PHY_MCU_CMD_2		0x800d
++#define AIR_PHY_MCU_CMD_2_MODE1			0x0
++#define AIR_PHY_MCU_CMD_3		0x800e
++#define AIR_PHY_MCU_CMD_3_MODE1			0x1101
++#define AIR_PHY_MCU_CMD_3_DOCMD			0x1100
++#define AIR_PHY_MCU_CMD_4		0x800f
++#define AIR_PHY_MCU_CMD_4_MODE1			0x0002
++#define AIR_PHY_MCU_CMD_4_INTCLR		0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR			0x021
++#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
++#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
++#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
++#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
++
++#define AIR_PHY_LED_DUR_ON		0x022
++
++#define AIR_PHY_LED_DUR_BLINK		0x023
++
++#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
++#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
++#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
++#define   AIR_PHY_LED_ON_LINK100		BIT(1)
++#define   AIR_PHY_LED_ON_LINK10			BIT(2)
++#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
++#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
++#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
++#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
++#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
++#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
++#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
++
++#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
++#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
++#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
++#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
++#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
++#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
++#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
++#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
++#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
++#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
++#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
++#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
++#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA		0x3b30
++#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
++
++#define EN8811H_FW_VERSION		0x3b3c
++
++#define EN8811H_POLARITY		0xca0f8
++#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
++#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
++
++#define EN8811H_GPIO_OUTPUT		0xcf8b8
++#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1		0x0f0018
++#define   EN8811H_FW_CTRL_1_START		0x0
++#define   EN8811H_FW_CTRL_1_FINISH		0x1
++#define EN8811H_FW_CTRL_2		0x800000
++#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
++
++/* Led definitions */
++#define EN8811H_LED_COUNT	3
++
++/* Default LED setup:
++ * GPIO5 <-> LED0  On: Link detected, blink Rx/Tx
++ * GPIO4 <-> LED1  On: Link detected at 2500 or 1000 Mbps
++ * GPIO3 <-> LED2  On: Link detected at 2500 or  100 Mbps
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK)      | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_1000))
++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_100))
++
++struct led {
++	unsigned long rules;
++	unsigned long state;
++};
++
++struct en8811h_priv {
++	u32		firmware_version;
++	bool		mcu_needs_restart;
++	struct led	led[EN8811H_LED_COUNT];
++};
++
++enum {
++	AIR_PHY_LED_STATE_FORCE_ON,
++	AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++	AIR_PHY_LED_DUR_BLINK_32MS,
++	AIR_PHY_LED_DUR_BLINK_64MS,
++	AIR_PHY_LED_DUR_BLINK_128MS,
++	AIR_PHY_LED_DUR_BLINK_256MS,
++	AIR_PHY_LED_DUR_BLINK_512MS,
++	AIR_PHY_LED_DUR_BLINK_1024MS,
++};
++
++enum {
++	AIR_LED_DISABLE,
++	AIR_LED_ENABLE,
++};
++
++enum {
++	AIR_ACTIVE_LOW,
++	AIR_ACTIVE_HIGH,
++};
++
++enum {
++	AIR_LED_MODE_DISABLE,
++	AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT	1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS)
++
++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++					      BIT(TRIGGER_NETDEV_LINK)        |
++					      BIT(TRIGGER_NETDEV_LINK_10)     |
++					      BIT(TRIGGER_NETDEV_LINK_100)    |
++					      BIT(TRIGGER_NETDEV_LINK_1000)   |
++					      BIT(TRIGGER_NETDEV_LINK_2500)   |
++					      BIT(TRIGGER_NETDEV_RX)          |
++					      BIT(TRIGGER_NETDEV_TX);
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++				    u32 pbus_address, u32 pbus_data)
++{
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++			  upper_16_bits(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++			  lower_16_bits(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++				  u32 pbus_address, u32 pbus_data)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_write(phydev, pbus_address,
++					       pbus_data);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++				   u32 pbus_address, u32 *pbus_data)
++{
++	int pbus_data_low, pbus_data_high;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	*pbus_data = pbus_data_low | (pbus_data_high << 16);
++	return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++				 u32 pbus_address, u32 *pbus_data)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_modify(struct phy_device *phydev,
++				     u32 pbus_address, u32 mask, u32 set)
++{
++	int pbus_data_low, pbus_data_high;
++	u32 pbus_data_old, pbus_data_new;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	pbus_data_old = pbus_data_low | (pbus_data_high << 16);
++	pbus_data_new = (pbus_data_old & ~mask) | set;
++	if (pbus_data_new == pbus_data_old)
++		return 0;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++			  upper_16_bits(pbus_data_new));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++			  lower_16_bits(pbus_data_new));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_modify(struct phy_device *phydev,
++				   u32 pbus_address, u32 mask, u32 set)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
++						set);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   pbus_address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++			   const struct firmware *fw)
++{
++	unsigned int offset;
++	int ret;
++	u16 val;
++
++	ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++			  upper_16_bits(address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++			  lower_16_bits(address));
++	if (ret < 0)
++		return ret;
++
++	for (offset = 0; offset < fw->size; offset += 4) {
++		val = get_unaligned_le16(&fw->data[offset + 2]);
++		ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);
++		if (ret < 0)
++			return ret;
++
++		val = get_unaligned_le16(&fw->data[offset]);
++		ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++			 const struct firmware *fw)
++{
++	int saved_page;
++	int ret = 0;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	if (saved_page >= 0) {
++		ret = __air_write_buf(phydev, address, fw);
++		if (ret < 0)
++			phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++				   address, ret);
++	}
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_wait_mcu_ready(struct phy_device *phydev)
++{
++	int ret, reg_value;
++
++	/* Because of mdio-lock, may have to wait for multiple loads */
++	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					EN8811H_PHY_FW_STATUS, reg_value,
++					reg_value == EN8811H_PHY_READY,
++					20000, 7500000, true);
++	if (ret) {
++		phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw1, *fw2;
++	int ret;
++
++	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++	if (ret < 0)
++		return ret;
++
++	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++	if (ret < 0)
++		goto en8811h_load_firmware_rel1;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++				      EN8811H_FW_CTRL_2_LOADING,
++				      EN8811H_FW_CTRL_2_LOADING);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++				      EN8811H_FW_CTRL_2_LOADING, 0);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = en8811h_wait_mcu_ready(phydev);
++
++	air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
++			      &priv->firmware_version);
++	phydev_info(phydev, "MD32 firmware version: %08x\n",
++		    priv->firmware_version);
++
++en8811h_load_firmware_out:
++	release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++	release_firmware(fw1);
++
++	if (ret < 0)
++		phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++	return ret;
++}
++
++static int en8811h_restart_mcu(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		return ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		return ret;
++
++	return en8811h_wait_mcu_ready(phydev);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (on)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++				      AIR_PHY_LED_ON(index),
++				      AIR_PHY_LED_ON_MASK,
++				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++	return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++				bool blinking)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (blinking)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++				     AIR_PHY_LED_BLINK(index),
++				     blinking ?
++				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++	else
++		return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++			     unsigned long *delay_on,
++			     unsigned long *delay_off)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool blinking = false;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++		blinking = true;
++		*delay_on = 50;
++		*delay_off = 50;
++	}
++
++	err = air_hw_led_blink_set(phydev, index, blinking);
++	if (err)
++		return err;
++
++	/* led-blink set, so switch led-on off */
++	err = air_hw_led_on_set(phydev, index, false);
++	if (err)
++		return err;
++
++	/* hw-control is off*/
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++				  enum led_brightness value)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* led-on set, so switch led-blink off */
++	err = air_hw_led_blink_set(phydev, index, false);
++	if (err)
++		return err;
++
++	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++	if (err)
++		return err;
++
++	/* hw-control is off */
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	*rules = priv->led[index].rules;
++
++	return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u16 on = 0, blink = 0;
++	int ret;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	priv->led[index].rules = rules;
++
++	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++		on |= AIR_PHY_LED_ON_FDX;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK10;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK100;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK1000;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++		on |= AIR_PHY_LED_ON_LINK2500;
++
++	if (rules & BIT(TRIGGER_NETDEV_RX)) {
++		blink |= AIR_PHY_LED_BLINK_10RX   |
++			 AIR_PHY_LED_BLINK_100RX  |
++			 AIR_PHY_LED_BLINK_1000RX |
++			 AIR_PHY_LED_BLINK_2500RX;
++	}
++
++	if (rules & BIT(TRIGGER_NETDEV_TX)) {
++		blink |= AIR_PHY_LED_BLINK_10TX   |
++			 AIR_PHY_LED_BLINK_100TX  |
++			 AIR_PHY_LED_BLINK_1000TX |
++			 AIR_PHY_LED_BLINK_2500TX;
++	}
++
++	if (blink || on) {
++		/* switch hw-control on, so led-on and led-blink are off */
++		clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++			  &priv->led[index].state);
++		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++			  &priv->led[index].state);
++	} else {
++		priv->led[index].rules = 0;
++	}
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_MASK, on);
++
++	if (ret < 0)
++		return ret;
++
++	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++			     blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++	int val = 0;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (state == AIR_LED_ENABLE)
++		val |= AIR_PHY_LED_ON_ENABLE;
++	else
++		val &= ~AIR_PHY_LED_ON_ENABLE;
++
++	if (pol == AIR_ACTIVE_HIGH)
++		val |= AIR_PHY_LED_ON_POLARITY;
++	else
++		val &= ~AIR_PHY_LED_ON_POLARITY;
++
++	err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_ENABLE |
++			     AIR_PHY_LED_ON_POLARITY, val);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int ret, i;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++			    dur);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++			    dur >> 1);
++	if (ret < 0)
++		return ret;
++
++	switch (mode) {
++	case AIR_LED_MODE_DISABLE:
++		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_MODE_MASK, 0);
++		if (ret < 0)
++			return ret;
++		break;
++	case AIR_LED_MODE_USER_DEFINE:
++		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_CLK_EN,
++				     AIR_PHY_LED_BCR_EXT_CTRL |
++				     AIR_PHY_LED_BCR_CLK_EN);
++		if (ret < 0)
++			return ret;
++		break;
++	default:
++		phydev_err(phydev, "LED mode %d is not supported\n", mode);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < num; ++i) {
++		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++		if (ret < 0) {
++			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++			return ret;
++		}
++		air_led_hw_control_set(phydev, i, priv->led[i].rules);
++	}
++
++	return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~en8811h_led_trig)
++		return -EOPNOTSUPP;
++
++	return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv;
++	int ret;
++
++	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++	phydev->priv = priv;
++
++	ret = en8811h_load_firmware(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* mcu has just restarted after firmware load */
++	priv->mcu_needs_restart = false;
++
++	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_DISABLE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to disable leds: %d\n", ret);
++		return ret;
++	}
++
++	/* Configure led gpio pins as output */
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
++				      EN8811H_GPIO_OUTPUT_345,
++				      EN8811H_GPIO_OUTPUT_345);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	u32 pbus_value;
++	int ret;
++
++	/* If restart happened in .probe(), no need to restart now */
++	if (priv->mcu_needs_restart) {
++		ret = en8811h_restart_mcu(phydev);
++		if (ret < 0)
++			return ret;
++	} else {
++		/* Next calls to .config_init() mcu needs to restart */
++		priv->mcu_needs_restart = true;
++	}
++
++	/* Select mode 1, the only mode supported.
++	 * Configures the SerDes for 2500Base-X with rate adaptation
++	 */
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
++			    AIR_PHY_MCU_CMD_1_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
++			    AIR_PHY_MCU_CMD_2_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++			    AIR_PHY_MCU_CMD_3_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++			    AIR_PHY_MCU_CMD_4_MODE1);
++	if (ret < 0)
++		return ret;
++
++	/* Serdes polarity */
++	pbus_value = 0;
++	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
++	else
++		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++	else
++		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
++	ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
++				      EN8811H_POLARITY_RX_REVERSE |
++				      EN8811H_POLARITY_TX_NORMAL, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_USER_DEFINE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++	linkmode_set_bit_array(phy_basic_ports_array,
++			       ARRAY_SIZE(phy_basic_ports_array),
++			       phydev->supported);
++
++	return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++				     phy_interface_t iface)
++{
++	return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	int ret;
++	u32 adv;
++
++	if (phydev->autoneg == AUTONEG_DISABLE) {
++		phydev_warn(phydev, "Disabling autoneg is not supported\n");
++		return -EINVAL;
++	}
++
++	adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
++	if (ret < 0)
++		return ret;
++	if (ret > 0)
++		changed = true;
++
++	return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u32 pbus_value;
++	int ret, val;
++
++	ret = genphy_update_link(phydev);
++	if (ret)
++		return ret;
++
++	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++	phydev->rate_matching = RATE_MATCH_PAUSE;
++
++	ret = genphy_read_master_slave(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_read_lpa(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Get link partner 2.5GBASE-T ability from vendor register */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++	if (ret < 0)
++		return ret;
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			 phydev->lp_advertising,
++			 pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++	if (phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	if (!phydev->link)
++		return 0;
++
++	/* Get real speed from vendor register */
++	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++	if (val < 0)
++		return val;
++	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++	case AIR_AUX_CTRL_STATUS_SPEED_2500:
++		phydev->speed = SPEED_2500;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_1000:
++		phydev->speed = SPEED_1000;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_100:
++		phydev->speed = SPEED_100;
++		break;
++	}
++
++	/* Firmware before version 24011202 has no vendor register 2P5G_LPA.
++	 * Assume link partner advertised it if connected at 2500Mbps.
++	 */
++	if (priv->firmware_version < 0x24011202) {
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 phydev->speed == SPEED_2500);
++	}
++
++	/* Only supports full duplex */
++	phydev->duplex = DUPLEX_FULL;
++
++	return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++			    AIR_PHY_MCU_CMD_3_DOCMD);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++			    AIR_PHY_MCU_CMD_4_INTCLR);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = en8811h_clear_intr(phydev);
++	if (ret < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++	.name			= "Airoha EN8811H",
++	.probe			= en8811h_probe,
++	.get_features		= en8811h_get_features,
++	.config_init		= en8811h_config_init,
++	.get_rate_matching	= en8811h_get_rate_matching,
++	.config_aneg		= en8811h_config_aneg,
++	.read_status		= en8811h_read_status,
++	.config_intr		= en8811h_clear_intr,
++	.handle_interrupt	= en8811h_handle_interrupt,
++	.led_hw_is_supported	= en8811h_led_hw_is_supported,
++	.read_page		= air_phy_read_page,
++	.write_page		= air_phy_write_page,
++	.led_blink_set		= air_led_blink_set,
++	.led_brightness_set	= air_led_brightness_set,
++	.led_hw_control_set	= air_led_hw_control_set,
++	.led_hw_control_get	= air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch b/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch
new file mode 100644
index 0000000000..1bd0eefe77
--- /dev/null
+++ b/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch
@@ -0,0 +1,47 @@
+From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Fri, 5 Apr 2024 13:08:59 +0300
+Subject: [PATCH] net: phy: air_en8811h: fix some error codes
+
+These error paths accidentally return "ret" which is zero/success
+instead of the correct error code.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/air_en8811h.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc
+ 
+ 	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ 	if (pbus_data_high < 0)
+-		return ret;
++		return pbus_data_high;
+ 
+ 	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ 	if (pbus_data_low < 0)
+-		return ret;
++		return pbus_data_low;
+ 
+ 	*pbus_data = pbus_data_low | (pbus_data_high << 16);
+ 	return 0;
+@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str
+ 
+ 	pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ 	if (pbus_data_high < 0)
+-		return ret;
++		return pbus_data_high;
+ 
+ 	pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ 	if (pbus_data_low < 0)
+-		return ret;
++		return pbus_data_low;
+ 
+ 	pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ 	pbus_data_new = (pbus_data_old & ~mask) | set;
diff --git a/target/linux/generic/backport-6.6/816-v6.7-0001-nvmem-qfprom-Mark-core-clk-as-optional.patch b/target/linux/generic/backport-6.6/816-v6.7-0001-nvmem-qfprom-Mark-core-clk-as-optional.patch
index 66d4028140..c83d4fc579 100644
--- a/target/linux/generic/backport-6.6/816-v6.7-0001-nvmem-qfprom-Mark-core-clk-as-optional.patch
+++ b/target/linux/generic/backport-6.6/816-v6.7-0001-nvmem-qfprom-Mark-core-clk-as-optional.patch
@@ -19,7 +19,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/drivers/nvmem/qfprom.c
 +++ b/drivers/nvmem/qfprom.c
-@@ -423,12 +423,12 @@ static int qfprom_probe(struct platform_
+@@ -424,12 +424,12 @@ static int qfprom_probe(struct platform_
  		if (IS_ERR(priv->vcc))
  			return PTR_ERR(priv->vcc);
  
diff --git a/target/linux/generic/backport-6.6/816-v6.7-0002-nvmem-add-explicit-config-option-to-read-old-syntax-.patch b/target/linux/generic/backport-6.6/816-v6.7-0002-nvmem-add-explicit-config-option-to-read-old-syntax-.patch
deleted file mode 100644
index 12c77c17af..0000000000
--- a/target/linux/generic/backport-6.6/816-v6.7-0002-nvmem-add-explicit-config-option-to-read-old-syntax-.patch
+++ /dev/null
@@ -1,330 +0,0 @@
-From 2cc3b37f5b6df8189d55d0e812d9658ce256dfec Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 20 Oct 2023 11:55:41 +0100
-Subject: [PATCH] nvmem: add explicit config option to read old syntax fixed OF
- cells
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Binding for fixed NVMEM cells defined directly as NVMEM device subnodes
-has been deprecated. It has been replaced by the "fixed-layout" NVMEM
-layout binding.
-
-New syntax is meant to be clearer and should help avoiding imprecise
-bindings.
-
-NVMEM subsystem already supports the new binding. It should be a good
-idea to limit support for old syntax to existing drivers that actually
-support & use it (we can't break backward compatibility!). That way we
-additionally encourage new bindings & drivers to ignore deprecated
-binding.
-
-It wasn't clear (to me) if rtc and w1 code actually uses old syntax
-fixed cells. I enabled them to don't risk any breakage.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-[for meson-{efuse,mx-efuse}.c]
-Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-[for mtk-efuse.c, nvmem/core.c, nvmem-provider.h]
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[MT8192, MT8195 Chromebooks]
-Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[for microchip-otpc.c]
-Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-[SAMA7G5-EK]
-Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-Link: https://lore.kernel.org/r/20231020105545.216052-3-srinivas.kandagatla@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mtd/mtdcore.c          | 2 ++
- drivers/nvmem/apple-efuses.c   | 1 +
- drivers/nvmem/core.c           | 8 +++++---
- drivers/nvmem/imx-ocotp-scu.c  | 1 +
- drivers/nvmem/imx-ocotp.c      | 1 +
- drivers/nvmem/meson-efuse.c    | 1 +
- drivers/nvmem/meson-mx-efuse.c | 1 +
- drivers/nvmem/microchip-otpc.c | 1 +
- drivers/nvmem/mtk-efuse.c      | 1 +
- drivers/nvmem/qcom-spmi-sdam.c | 1 +
- drivers/nvmem/qfprom.c         | 1 +
- drivers/nvmem/rave-sp-eeprom.c | 1 +
- drivers/nvmem/rockchip-efuse.c | 1 +
- drivers/nvmem/sc27xx-efuse.c   | 1 +
- drivers/nvmem/sec-qfprom.c     | 1 +
- drivers/nvmem/sprd-efuse.c     | 1 +
- drivers/nvmem/stm32-romem.c    | 1 +
- drivers/nvmem/sunplus-ocotp.c  | 1 +
- drivers/nvmem/sunxi_sid.c      | 1 +
- drivers/nvmem/uniphier-efuse.c | 1 +
- drivers/nvmem/zynqmp_nvmem.c   | 1 +
- drivers/rtc/nvmem.c            | 1 +
- drivers/w1/slaves/w1_ds250x.c  | 1 +
- include/linux/nvmem-provider.h | 2 ++
- 24 files changed, 30 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -552,6 +552,7 @@ static int mtd_nvmem_add(struct mtd_info
- 	config.dev = &mtd->dev;
- 	config.name = dev_name(&mtd->dev);
- 	config.owner = THIS_MODULE;
-+	config.add_legacy_fixed_of_cells = of_device_is_compatible(node, "nvmem-cells");
- 	config.reg_read = mtd_nvmem_reg_read;
- 	config.size = mtd->size;
- 	config.word_size = 1;
-@@ -898,6 +899,7 @@ static struct nvmem_device *mtd_otp_nvme
- 	config.name = compatible;
- 	config.id = NVMEM_DEVID_AUTO;
- 	config.owner = THIS_MODULE;
-+	config.add_legacy_fixed_of_cells = true;
- 	config.type = NVMEM_TYPE_OTP;
- 	config.root_only = true;
- 	config.ignore_wp = true;
---- a/drivers/nvmem/apple-efuses.c
-+++ b/drivers/nvmem/apple-efuses.c
-@@ -36,6 +36,7 @@ static int apple_efuses_probe(struct pla
- 	struct resource *res;
- 	struct nvmem_config config = {
- 		.dev = &pdev->dev,
-+		.add_legacy_fixed_of_cells = true,
- 		.read_only = true,
- 		.reg_read = apple_efuses_read,
- 		.stride = sizeof(u32),
---- a/drivers/nvmem/core.c
-+++ b/drivers/nvmem/core.c
-@@ -1003,9 +1003,11 @@ struct nvmem_device *nvmem_register(cons
- 	if (rval)
- 		goto err_remove_cells;
- 
--	rval = nvmem_add_cells_from_legacy_of(nvmem);
--	if (rval)
--		goto err_remove_cells;
-+	if (config->add_legacy_fixed_of_cells) {
-+		rval = nvmem_add_cells_from_legacy_of(nvmem);
-+		if (rval)
-+			goto err_remove_cells;
-+	}
- 
- 	rval = nvmem_add_cells_from_fixed_layout(nvmem);
- 	if (rval)
---- a/drivers/nvmem/imx-ocotp-scu.c
-+++ b/drivers/nvmem/imx-ocotp-scu.c
-@@ -220,6 +220,7 @@ static int imx_scu_ocotp_write(void *con
- 
- static struct nvmem_config imx_scu_ocotp_nvmem_config = {
- 	.name = "imx-scu-ocotp",
-+	.add_legacy_fixed_of_cells = true,
- 	.read_only = false,
- 	.word_size = 4,
- 	.stride = 1,
---- a/drivers/nvmem/imx-ocotp.c
-+++ b/drivers/nvmem/imx-ocotp.c
-@@ -615,6 +615,7 @@ static int imx_ocotp_probe(struct platfo
- 		return PTR_ERR(priv->clk);
- 
- 	priv->params = of_device_get_match_data(&pdev->dev);
-+	imx_ocotp_nvmem_config.add_legacy_fixed_of_cells = true;
- 	imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
- 	imx_ocotp_nvmem_config.dev = dev;
- 	imx_ocotp_nvmem_config.priv = priv;
---- a/drivers/nvmem/meson-efuse.c
-+++ b/drivers/nvmem/meson-efuse.c
-@@ -74,6 +74,7 @@ static int meson_efuse_probe(struct plat
- 
- 	econfig->dev = dev;
- 	econfig->name = dev_name(dev);
-+	econfig->add_legacy_fixed_of_cells = true;
- 	econfig->stride = 1;
- 	econfig->word_size = 1;
- 	econfig->reg_read = meson_efuse_read;
---- a/drivers/nvmem/meson-mx-efuse.c
-+++ b/drivers/nvmem/meson-mx-efuse.c
-@@ -210,6 +210,7 @@ static int meson_mx_efuse_probe(struct p
- 	efuse->config.owner = THIS_MODULE;
- 	efuse->config.dev = &pdev->dev;
- 	efuse->config.priv = efuse;
-+	efuse->config.add_legacy_fixed_of_cells = true;
- 	efuse->config.stride = drvdata->word_size;
- 	efuse->config.word_size = drvdata->word_size;
- 	efuse->config.size = SZ_512;
---- a/drivers/nvmem/microchip-otpc.c
-+++ b/drivers/nvmem/microchip-otpc.c
-@@ -261,6 +261,7 @@ static int mchp_otpc_probe(struct platfo
- 		return ret;
- 
- 	mchp_nvmem_config.dev = otpc->dev;
-+	mchp_nvmem_config.add_legacy_fixed_of_cells = true;
- 	mchp_nvmem_config.size = size;
- 	mchp_nvmem_config.priv = otpc;
- 	nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
---- a/drivers/nvmem/mtk-efuse.c
-+++ b/drivers/nvmem/mtk-efuse.c
-@@ -83,6 +83,7 @@ static int mtk_efuse_probe(struct platfo
- 		return PTR_ERR(priv->base);
- 
- 	pdata = device_get_match_data(dev);
-+	econfig.add_legacy_fixed_of_cells = true;
- 	econfig.stride = 1;
- 	econfig.word_size = 1;
- 	econfig.reg_read = mtk_reg_read;
---- a/drivers/nvmem/qcom-spmi-sdam.c
-+++ b/drivers/nvmem/qcom-spmi-sdam.c
-@@ -142,6 +142,7 @@ static int sdam_probe(struct platform_de
- 	sdam->sdam_config.name = "spmi_sdam";
- 	sdam->sdam_config.id = NVMEM_DEVID_AUTO;
- 	sdam->sdam_config.owner = THIS_MODULE;
-+	sdam->sdam_config.add_legacy_fixed_of_cells = true;
- 	sdam->sdam_config.stride = 1;
- 	sdam->sdam_config.word_size = 1;
- 	sdam->sdam_config.reg_read = sdam_read;
---- a/drivers/nvmem/qfprom.c
-+++ b/drivers/nvmem/qfprom.c
-@@ -357,6 +357,7 @@ static int qfprom_probe(struct platform_
- {
- 	struct nvmem_config econfig = {
- 		.name = "qfprom",
-+		.add_legacy_fixed_of_cells = true,
- 		.stride = 1,
- 		.word_size = 1,
- 		.id = NVMEM_DEVID_AUTO,
---- a/drivers/nvmem/rave-sp-eeprom.c
-+++ b/drivers/nvmem/rave-sp-eeprom.c
-@@ -328,6 +328,7 @@ static int rave_sp_eeprom_probe(struct p
- 	of_property_read_string(np, "zii,eeprom-name", &config.name);
- 	config.priv		= eeprom;
- 	config.dev		= dev;
-+	config.add_legacy_fixed_of_cells	= true;
- 	config.size		= size;
- 	config.reg_read		= rave_sp_eeprom_reg_read;
- 	config.reg_write	= rave_sp_eeprom_reg_write;
---- a/drivers/nvmem/rockchip-efuse.c
-+++ b/drivers/nvmem/rockchip-efuse.c
-@@ -205,6 +205,7 @@ static int rockchip_rk3399_efuse_read(vo
- 
- static struct nvmem_config econfig = {
- 	.name = "rockchip-efuse",
-+	.add_legacy_fixed_of_cells = true,
- 	.stride = 1,
- 	.word_size = 1,
- 	.read_only = true,
---- a/drivers/nvmem/sc27xx-efuse.c
-+++ b/drivers/nvmem/sc27xx-efuse.c
-@@ -247,6 +247,7 @@ static int sc27xx_efuse_probe(struct pla
- 	econfig.reg_read = sc27xx_efuse_read;
- 	econfig.priv = efuse;
- 	econfig.dev = &pdev->dev;
-+	econfig.add_legacy_fixed_of_cells = true;
- 	nvmem = devm_nvmem_register(&pdev->dev, &econfig);
- 	if (IS_ERR(nvmem)) {
- 		dev_err(&pdev->dev, "failed to register nvmem config\n");
---- a/drivers/nvmem/sec-qfprom.c
-+++ b/drivers/nvmem/sec-qfprom.c
-@@ -47,6 +47,7 @@ static int sec_qfprom_probe(struct platf
- {
- 	struct nvmem_config econfig = {
- 		.name = "sec-qfprom",
-+		.add_legacy_fixed_of_cells = true,
- 		.stride = 1,
- 		.word_size = 1,
- 		.id = NVMEM_DEVID_AUTO,
---- a/drivers/nvmem/sprd-efuse.c
-+++ b/drivers/nvmem/sprd-efuse.c
-@@ -408,6 +408,7 @@ static int sprd_efuse_probe(struct platf
- 	econfig.read_only = false;
- 	econfig.name = "sprd-efuse";
- 	econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
-+	econfig.add_legacy_fixed_of_cells = true;
- 	econfig.reg_read = sprd_efuse_read;
- 	econfig.reg_write = sprd_efuse_write;
- 	econfig.priv = efuse;
---- a/drivers/nvmem/stm32-romem.c
-+++ b/drivers/nvmem/stm32-romem.c
-@@ -207,6 +207,7 @@ static int stm32_romem_probe(struct plat
- 	priv->cfg.priv = priv;
- 	priv->cfg.owner = THIS_MODULE;
- 	priv->cfg.type = NVMEM_TYPE_OTP;
-+	priv->cfg.add_legacy_fixed_of_cells = true;
- 
- 	priv->lower = 0;
- 
---- a/drivers/nvmem/sunplus-ocotp.c
-+++ b/drivers/nvmem/sunplus-ocotp.c
-@@ -145,6 +145,7 @@ disable_clk:
- 
- static struct nvmem_config sp_ocotp_nvmem_config = {
- 	.name = "sp-ocotp",
-+	.add_legacy_fixed_of_cells = true,
- 	.read_only = true,
- 	.word_size = 1,
- 	.size = QAC628_OTP_SIZE,
---- a/drivers/nvmem/sunxi_sid.c
-+++ b/drivers/nvmem/sunxi_sid.c
-@@ -153,6 +153,7 @@ static int sunxi_sid_probe(struct platfo
- 	nvmem_cfg->dev = dev;
- 	nvmem_cfg->name = "sunxi-sid";
- 	nvmem_cfg->type = NVMEM_TYPE_OTP;
-+	nvmem_cfg->add_legacy_fixed_of_cells = true;
- 	nvmem_cfg->read_only = true;
- 	nvmem_cfg->size = cfg->size;
- 	nvmem_cfg->word_size = 1;
---- a/drivers/nvmem/uniphier-efuse.c
-+++ b/drivers/nvmem/uniphier-efuse.c
-@@ -52,6 +52,7 @@ static int uniphier_efuse_probe(struct p
- 	econfig.size = resource_size(res);
- 	econfig.priv = priv;
- 	econfig.dev = dev;
-+	econfig.add_legacy_fixed_of_cells = true;
- 	nvmem = devm_nvmem_register(dev, &econfig);
- 
- 	return PTR_ERR_OR_ZERO(nvmem);
---- a/drivers/nvmem/zynqmp_nvmem.c
-+++ b/drivers/nvmem/zynqmp_nvmem.c
-@@ -58,6 +58,7 @@ static int zynqmp_nvmem_probe(struct pla
- 
- 	priv->dev = dev;
- 	econfig.dev = dev;
-+	econfig.add_legacy_fixed_of_cells = true;
- 	econfig.reg_read = zynqmp_nvmem_read;
- 	econfig.priv = priv;
- 
---- a/drivers/rtc/nvmem.c
-+++ b/drivers/rtc/nvmem.c
-@@ -21,6 +21,7 @@ int devm_rtc_nvmem_register(struct rtc_d
- 
- 	nvmem_config->dev = dev;
- 	nvmem_config->owner = rtc->owner;
-+	nvmem_config->add_legacy_fixed_of_cells = true;
- 	nvmem = devm_nvmem_register(dev, nvmem_config);
- 	if (IS_ERR(nvmem))
- 		dev_err(dev, "failed to register nvmem device for RTC\n");
---- a/drivers/w1/slaves/w1_ds250x.c
-+++ b/drivers/w1/slaves/w1_ds250x.c
-@@ -168,6 +168,7 @@ static int w1_eprom_add_slave(struct w1_
- 	struct nvmem_device *nvmem;
- 	struct nvmem_config nvmem_cfg = {
- 		.dev = &sl->dev,
-+		.add_legacy_fixed_of_cells = true,
- 		.reg_read = w1_nvmem_read,
- 		.type = NVMEM_TYPE_OTP,
- 		.read_only = true,
---- a/include/linux/nvmem-provider.h
-+++ b/include/linux/nvmem-provider.h
-@@ -82,6 +82,7 @@ struct nvmem_cell_info {
-  * @owner:	Pointer to exporter module. Used for refcounting.
-  * @cells:	Optional array of pre-defined NVMEM cells.
-  * @ncells:	Number of elements in cells.
-+ * @add_legacy_fixed_of_cells:	Read fixed NVMEM cells from old OF syntax.
-  * @keepout:	Optional array of keepout ranges (sorted ascending by start).
-  * @nkeepout:	Number of elements in the keepout array.
-  * @type:	Type of the nvmem storage
-@@ -112,6 +113,7 @@ struct nvmem_config {
- 	struct module		*owner;
- 	const struct nvmem_cell_info	*cells;
- 	int			ncells;
-+	bool			add_legacy_fixed_of_cells;
- 	const struct nvmem_keepout *keepout;
- 	unsigned int		nkeepout;
- 	enum nvmem_type		type;
diff --git a/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch b/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
index fa2056b69a..07287206f6 100644
--- a/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
+++ b/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch
@@ -16,8 +16,8 @@ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -69,9 +69,9 @@ config SFP
- comment "MII PHY device drivers"
+@@ -74,9 +74,9 @@ config AIR_EN8811H_PHY
+ 	  Currently supports the Airoha EN8811H PHY.
  
  config AMD_PHY
 -	tristate "AMD PHYs"
diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15
index 50973e906d..cba00711ca 100644
--- a/target/linux/generic/config-5.15
+++ b/target/linux/generic/config-5.15
@@ -4328,6 +4328,7 @@ CONFIG_NF_CONNTRACK_PROCFS=y
 # CONFIG_NF_DUP_IPV4 is not set
 # CONFIG_NF_DUP_IPV6 is not set
 # CONFIG_NF_FLOW_TABLE is not set
+# CONFIG_NF_FLOW_TABLE_PROCFS is not set
 # CONFIG_NF_LOG_ARP is not set
 # CONFIG_NF_LOG_BRIDGE is not set
 # CONFIG_NF_LOG_IPV4 is not set
diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6
index c52b4f682f..00c7110d58 100644
--- a/target/linux/generic/config-6.6
+++ b/target/linux/generic/config-6.6
@@ -1,13 +1,11 @@
 # CONFIG_104_QUAD_8 is not set
 CONFIG_32BIT=y
-CONFIG_64BIT_TIME=y
 # CONFIG_6LOWPAN is not set
 # CONFIG_6LOWPAN_DEBUGFS is not set
 # CONFIG_6PACK is not set
 # CONFIG_8139CP is not set
 # CONFIG_8139TOO is not set
 # CONFIG_9P_FS is not set
-# CONFIG_AB3100_CORE is not set
 # CONFIG_AB8500_CORE is not set
 # CONFIG_ABP060MG is not set
 # CONFIG_ABX500_CORE is not set
@@ -60,7 +58,6 @@ CONFIG_64BIT_TIME=y
 # CONFIG_AD7091R5 is not set
 # CONFIG_AD7124 is not set
 # CONFIG_AD7150 is not set
-# CONFIG_AD7152 is not set
 # CONFIG_AD7192 is not set
 # CONFIG_AD7266 is not set
 # CONFIG_AD7280 is not set
@@ -94,7 +91,6 @@ CONFIG_64BIT_TIME=y
 # CONFIG_AD9834 is not set
 # CONFIG_ADA4250 is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_ADE7854 is not set
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
 # CONFIG_ADF4377 is not set
@@ -188,9 +184,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y
 # CONFIG_AMILO_RFKILL is not set
 # CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
 # CONFIG_AMT is not set
-# CONFIG_ANDROID is not set
 # CONFIG_ANDROID_BINDER_IPC is not set
-CONFIG_ANON_INODES=y
 # CONFIG_ANON_VMA_NAME is not set
 # CONFIG_APDS9300 is not set
 # CONFIG_APDS9802ALS is not set
@@ -208,7 +202,6 @@ CONFIG_ANON_INODES=y
 # CONFIG_AR8216_PHY is not set
 # CONFIG_AR8216_PHY_LEDS is not set
 # CONFIG_ARCH_ACTIONS is not set
-# CONFIG_ARCH_AGILEX is not set
 # CONFIG_ARCH_AIROHA is not set
 # CONFIG_ARCH_ALPINE is not set
 # CONFIG_ARCH_APPLE is not set
@@ -218,14 +211,12 @@ CONFIG_ANON_INODES=y
 # CONFIG_ARCH_AXXIA is not set
 # CONFIG_ARCH_BCM is not set
 # CONFIG_ARCH_BCM2835 is not set
-# CONFIG_ARCH_BCM4908 is not set
 # CONFIG_ARCH_BCMBCA is not set
 # CONFIG_ARCH_BCM_21664 is not set
 # CONFIG_ARCH_BCM_23550 is not set
 # CONFIG_ARCH_BCM_281XX is not set
 # CONFIG_ARCH_BCM_5301X is not set
 # CONFIG_ARCH_BCM_53573 is not set
-# CONFIG_ARCH_BCM_63XX is not set
 # CONFIG_ARCH_BCM_CYGNUS is not set
 # CONFIG_ARCH_BCM_HR2 is not set
 # CONFIG_ARCH_BCM_IPROC is not set
@@ -235,12 +226,10 @@ CONFIG_ARCH_BINFMT_ELF_STATE=y
 # CONFIG_ARCH_BITMAIN is not set
 # CONFIG_ARCH_BRCMSTB is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CNS3XXX is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_DIGICOLOR is not set
 # CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
 # CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_EXYNOS is not set
 CONFIG_ARCH_FLATMEM_ENABLE=y
@@ -253,14 +242,10 @@ CONFIG_ARCH_FORCE_MAX_ORDER=11
 # CONFIG_ARCH_HPE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_INTEL_SOCFPGA is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_K3 is not set
 # CONFIG_ARCH_KEEMBAY is not set
 # CONFIG_ARCH_KEYSTONE is not set
-# CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_LAYERSCAPE is not set
 # CONFIG_ARCH_LG1K is not set
 # CONFIG_ARCH_LPC32XX is not set
@@ -283,7 +268,6 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_MXS is not set
 # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
-# CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_NPCM is not set
 # CONFIG_ARCH_NSPIRE is not set
@@ -295,12 +279,8 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARCH_OMAP3 is not set
 # CONFIG_ARCH_OMAP4 is not set
 # CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_OXNAS is not set
-# CONFIG_ARCH_PICOXCELL is not set
-# CONFIG_ARCH_PRIMA2 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_QCOM is not set
-# CONFIG_ARCH_RANDOM is not set
 # CONFIG_ARCH_RDA is not set
 # CONFIG_ARCH_REALTEK is not set
 # CONFIG_ARCH_REALVIEW is not set
@@ -308,27 +288,21 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARCH_ROCKCHIP is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_S32 is not set
-# CONFIG_ARCH_S3C24XX is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_SEATTLE is not set
 # CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_SIRF is not set
-# CONFIG_ARCH_SOCFPGA is not set
 # CONFIG_ARCH_SPARX5 is not set
 # CONFIG_ARCH_SPRD is not set
 # CONFIG_ARCH_STI is not set
 # CONFIG_ARCH_STM32 is not set
-# CONFIG_ARCH_STRATIX10 is not set
 # CONFIG_ARCH_SUNPLUS is not set
 # CONFIG_ARCH_SUNXI is not set
 # CONFIG_ARCH_SYNQUACER is not set
-# CONFIG_ARCH_TANGO is not set
 # CONFIG_ARCH_TEGRA is not set
 # CONFIG_ARCH_THUNDER is not set
 # CONFIG_ARCH_THUNDER2 is not set
-# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_U8500 is not set
 # CONFIG_ARCH_UNIPHIER is not set
 # CONFIG_ARCH_VERSATILE is not set
@@ -336,14 +310,11 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARCH_VIRT is not set
 # CONFIG_ARCH_VISCONTI is not set
 # CONFIG_ARCH_VT8500 is not set
-# CONFIG_ARCH_VULCAN is not set
-# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_WANTS_THP_SWAP is not set
 # CONFIG_ARCH_WM8505 is not set
 # CONFIG_ARCH_WM8750 is not set
 # CONFIG_ARCH_WM8850 is not set
 # CONFIG_ARCH_XGENE is not set
-# CONFIG_ARCH_ZX is not set
 # CONFIG_ARCH_ZYNQ is not set
 # CONFIG_ARCH_ZYNQMP is not set
 # CONFIG_ARCNET is not set
@@ -353,7 +324,6 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARM64_64K_PAGES is not set
 # CONFIG_ARM64_AMU_EXTN is not set
 # CONFIG_ARM64_BTI is not set
-# CONFIG_ARM64_CRYPTO is not set
 # CONFIG_ARM64_E0PD is not set
 # CONFIG_ARM64_ERRATUM_1024718 is not set
 # CONFIG_ARM64_ERRATUM_1165522 is not set
@@ -386,37 +356,31 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
 # CONFIG_ARM64_ERRATUM_858921 is not set
 # CONFIG_ARM64_HW_AFDBM is not set
 # CONFIG_ARM64_LSE_ATOMICS is not set
-CONFIG_ARM64_MODULE_PLTS=y
 # CONFIG_ARM64_MTE is not set
 # CONFIG_ARM64_PAN is not set
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_PSEUDO_NMI is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
 # CONFIG_ARM64_PTR_AUTH is not set
-# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_RELOC_TEST is not set
 # CONFIG_ARM64_SME is not set
 # CONFIG_ARM64_SVE is not set
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_TLB_RANGE is not set
-# CONFIG_ARM64_UAO is not set
 # CONFIG_ARM64_USE_LSE_ATOMICS is not set
 # CONFIG_ARM64_VA_BITS_48 is not set
-# CONFIG_ARM64_VHE is not set
 # CONFIG_ARM_APPENDED_DTB is not set
 # CONFIG_ARM_ARCH_TIMER is not set
 # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
-# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
 # CONFIG_ARM_CCI is not set
 # CONFIG_ARM_CCI400_PMU is not set
 # CONFIG_ARM_CCI5xx_PMU is not set
 # CONFIG_ARM_CCI_PMU is not set
 # CONFIG_ARM_CCN is not set
 # CONFIG_ARM_CMN is not set
+# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
 # CONFIG_ARM_CPUIDLE is not set
 CONFIG_ARM_CPU_TOPOLOGY=y
-# CONFIG_ARM_CRYPTO is not set
 CONFIG_ARM_DMA_MEM_BUFFERABLE=y
 # CONFIG_ARM_DSU_PMU is not set
 # CONFIG_ARM_ERRATA_326103 is not set
@@ -465,6 +429,7 @@ CONFIG_ARM_MODULE_PLTS=y
 # CONFIG_ARM_SDE_INTERFACE is not set
 # CONFIG_ARM_SMCCC_SOC_ID is not set
 # CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_ARM_SMMU_V3_PMU is not set
 # CONFIG_ARM_SP805_WATCHDOG is not set
 # CONFIG_ARM_SPE_PMU is not set
 # CONFIG_ARM_THUMBEE is not set
@@ -517,7 +482,6 @@ CONFIG_ATA_SFF=y
 # CONFIG_ATMEL is not set
 # CONFIG_ATMEL_PIT is not set
 # CONFIG_ATMEL_SSC is not set
-# CONFIG_ATM_AMBASSADOR is not set
 # CONFIG_ATM_BR2684 is not set
 CONFIG_ATM_BR2684_IPFILTER=y
 # CONFIG_ATM_CLIP is not set
@@ -525,10 +489,8 @@ CONFIG_ATM_CLIP_NO_ICMP=y
 # CONFIG_ATM_DRIVERS is not set
 # CONFIG_ATM_DUMMY is not set
 # CONFIG_ATM_ENI is not set
-# CONFIG_ATM_FIRESTREAM is not set
 # CONFIG_ATM_FORE200E is not set
 # CONFIG_ATM_HE is not set
-# CONFIG_ATM_HORIZON is not set
 # CONFIG_ATM_IA is not set
 # CONFIG_ATM_IDT77252 is not set
 # CONFIG_ATM_LANAI is not set
@@ -537,13 +499,10 @@ CONFIG_ATM_CLIP_NO_ICMP=y
 # CONFIG_ATM_NICSTAR is not set
 # CONFIG_ATM_SOLOS is not set
 # CONFIG_ATM_TCP is not set
-# CONFIG_ATM_ZATM is not set
 # CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_ATP is not set
 # CONFIG_AUDIT is not set
 # CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
-# CONFIG_AURORA_NB8800 is not set
-# CONFIG_AUTOFS4_FS is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTO_ZRELADDR is not set
 # CONFIG_AUXDISPLAY is not set
@@ -570,21 +529,17 @@ CONFIG_ATM_CLIP_NO_ICMP=y
 # CONFIG_BACKLIGHT_ARCXCNN is not set
 # CONFIG_BACKLIGHT_BD6107 is not set
 # CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_GENERIC is not set
 # CONFIG_BACKLIGHT_GPIO is not set
 # CONFIG_BACKLIGHT_KTD253 is not set
 # CONFIG_BACKLIGHT_KTZ8866 is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 # CONFIG_BACKLIGHT_LED is not set
 # CONFIG_BACKLIGHT_LM3630A is not set
 # CONFIG_BACKLIGHT_LM3639 is not set
 # CONFIG_BACKLIGHT_LP855X is not set
 # CONFIG_BACKLIGHT_LV5207LP is not set
 # CONFIG_BACKLIGHT_PANDORA is not set
-# CONFIG_BACKLIGHT_PM8941_WLED is not set
 # CONFIG_BACKLIGHT_PWM is not set
 # CONFIG_BACKLIGHT_QCOM_WLED is not set
-# CONFIG_BACKLIGHT_RPI is not set
 # CONFIG_BACKLIGHT_SAHARA is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_BACKTRACE_VERBOSE is not set
@@ -614,7 +569,6 @@ CONFIG_BASE_SMALL=0
 # CONFIG_BAYCOM_SER_FDX is not set
 # CONFIG_BAYCOM_SER_HDX is not set
 # CONFIG_BCACHE is not set
-# CONFIG_BCM2712_MIP is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM54140_PHY is not set
 # CONFIG_BCM63XX is not set
@@ -644,7 +598,6 @@ CONFIG_BCMA_POSSIBLE=y
 # CONFIG_BIG_KEYS is not set
 # CONFIG_BIG_LITTLE is not set
 CONFIG_BINARY_PRINTF=y
-# CONFIG_BINFMT_AOUT is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_ELF_FDPIC is not set
 # CONFIG_BINFMT_FLAT is not set
@@ -654,89 +607,32 @@ CONFIG_BITREVERSE=y
 # CONFIG_BLK_CGROUP_IOCOST is not set
 # CONFIG_BLK_CGROUP_IOLATENCY is not set
 # CONFIG_BLK_CGROUP_IOPRIO is not set
-# CONFIG_BLK_CMDLINE_PARSER is not set
 # CONFIG_BLK_DEBUG_FS is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_BLK_DEV_4DRIVES is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI14XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-# CONFIG_BLK_DEV_ATIIXP is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_BSGLIB is not set
-# CONFIG_BLK_DEV_CMD640 is not set
-# CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_CS5535 is not set
-# CONFIG_BLK_DEV_CS5536 is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_DELKIN is not set
 # CONFIG_BLK_DEV_DM is not set
 # CONFIG_BLK_DEV_DRBD is not set
-# CONFIG_BLK_DEV_DTC2278 is not set
 # CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_GENERIC is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_HT6560B is not set
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDECS is not set
-# CONFIG_BLK_DEV_IDEPCI is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDE_AU1XXX is not set
-# CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_IT8172 is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 # CONFIG_BLK_DEV_MD is not set
 # CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_NULL_BLK is not set
 # CONFIG_BLK_DEV_NVME is not set
-# CONFIG_BLK_DEV_OFFBOARD is not set
-# CONFIG_BLK_DEV_OPTI621 is not set
 # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PIIX is not set
-# CONFIG_BLK_DEV_PLATFORM is not set
 # CONFIG_BLK_DEV_PMEM is not set
-# CONFIG_BLK_DEV_QD65XX is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
-# CONFIG_BLK_DEV_RZ1000 is not set
-# CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_SD is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SIS5513 is not set
-# CONFIG_BLK_DEV_SKD is not set
-# CONFIG_BLK_DEV_SL82C105 is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_SR is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
 # CONFIG_BLK_DEV_THROTTLING is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_UBLK is not set
-# CONFIG_BLK_DEV_UMC8672 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_ZONED is not set
 # CONFIG_BLK_INLINE_ENCRYPTION is not set
 # CONFIG_BLK_NVMEM is not set
@@ -865,7 +761,6 @@ CONFIG_BT_HCIUART_H4=y
 # CONFIG_BT_HCIUART_RTL is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_BT_HIDP is not set
-# CONFIG_BT_HS is not set
 # CONFIG_BT_LE is not set
 # CONFIG_BT_LEDS is not set
 CONFIG_BT_LE_L2CAP_ECRED=y
@@ -880,9 +775,7 @@ CONFIG_BT_RFCOMM_TTY=y
 # CONFIG_BT_VIRTIO is not set
 CONFIG_BUG=y
 # CONFIG_BUG_ON_DATA_CORRUPTION is not set
-CONFIG_BUILDTIME_EXTABLE_SORT=y
 CONFIG_BUILDTIME_TABLE_SORT=y
-# CONFIG_BUILD_BIN2C is not set
 CONFIG_BUILD_SALT=""
 # CONFIG_C2PORT is not set
 # CONFIG_CACHESTAT_SYSCALL is not set
@@ -919,12 +812,8 @@ CONFIG_CACHE_L2X0_PMU=y
 # CONFIG_CAN_UCAN is not set
 # CONFIG_CAN_VCAN is not set
 # CONFIG_CAN_VXCAN is not set
-# CONFIG_CAPI_AVM is not set
-# CONFIG_CAPI_EICON is not set
 # CONFIG_CAPI_TRACE is not set
 CONFIG_CARDBUS=y
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
 # CONFIG_CARL9170 is not set
 # CONFIG_CASSINI is not set
 # CONFIG_CAVIUM_CPT is not set
@@ -967,7 +856,6 @@ CONFIG_CFG80211_HEADERS=y
 # CONFIG_CHARGER_ISP1704 is not set
 # CONFIG_CHARGER_LP8727 is not set
 # CONFIG_CHARGER_LT3651 is not set
-# CONFIG_CHARGER_LTC3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_MANAGER is not set
 # CONFIG_CHARGER_MAX77976 is not set
@@ -981,35 +869,27 @@ CONFIG_CFG80211_HEADERS=y
 # CONFIG_CHARGER_SMB347 is not set
 # CONFIG_CHARGER_TWL4030 is not set
 # CONFIG_CHARGER_UCS1002 is not set
-# CONFIG_CHASH_SELFTEST is not set
-# CONFIG_CHASH_STATS is not set
 # CONFIG_CHECKPOINT_RESTORE is not set
 # CONFIG_CHELSIO_T1 is not set
 # CONFIG_CHELSIO_T3 is not set
 # CONFIG_CHELSIO_T4 is not set
 # CONFIG_CHELSIO_T4VF is not set
 # CONFIG_CHROME_PLATFORMS is not set
-# CONFIG_CHR_DEV_OSST is not set
 # CONFIG_CHR_DEV_SCH is not set
 # CONFIG_CHR_DEV_SG is not set
 # CONFIG_CHR_DEV_ST is not set
 # CONFIG_CICADA_PHY is not set
 # CONFIG_CIFS is not set
-# CONFIG_CIFS_ACL is not set
 CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
 # CONFIG_CIFS_DEBUG is not set
 # CONFIG_CIFS_DEBUG2 is not set
 # CONFIG_CIFS_FSCACHE is not set
 # CONFIG_CIFS_NFSD_EXPORT is not set
 CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_SMB2 is not set
-# CONFIG_CIFS_STATS is not set
 # CONFIG_CIFS_STATS2 is not set
 # CONFIG_CIFS_SWN_UPCALL is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
 CONFIG_CIFS_XATTR=y
 # CONFIG_CIO_DAC is not set
-# CONFIG_CLEANCACHE is not set
 # CONFIG_CLKSRC_PISTACHIO is not set
 # CONFIG_CLKSRC_VERSATILE is not set
 # CONFIG_CLK_GFM_LPASS_SM8250 is not set
@@ -1017,7 +897,6 @@ CONFIG_CIFS_XATTR=y
 # CONFIG_CLK_ICST is not set
 # CONFIG_CLK_QORIQ is not set
 # CONFIG_CLK_SP810 is not set
-# CONFIG_CLOCK_THERMAL is not set
 CONFIG_CLS_U32_MARK=y
 # CONFIG_CLS_U32_PERF is not set
 # CONFIG_CM32181 is not set
@@ -1060,8 +939,6 @@ CONFIG_CMDLINE=""
 # CONFIG_COMMON_CLK_PWM is not set
 # CONFIG_COMMON_CLK_PXA is not set
 # CONFIG_COMMON_CLK_QCOM is not set
-# CONFIG_COMMON_CLK_RP1 is not set
-# CONFIG_COMMON_CLK_RP1_SDIO  is not set
 # CONFIG_COMMON_CLK_RS9_PCIE is not set
 # CONFIG_COMMON_CLK_SI514 is not set
 # CONFIG_COMMON_CLK_SI521XX is not set
@@ -1105,7 +982,6 @@ CONFIG_CONSTRUCTORS=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 # CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
 # CONFIG_CPU_FREQ_THERMAL is not set
 # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
 # CONFIG_CPU_ICACHE_DISABLE is not set
@@ -1139,7 +1015,7 @@ CONFIG_CRC32_SARWATE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC_ITU_T is not set
 # CONFIG_CRC_T10DIF is not set
-CONFIG_CROSS_COMPILE=""
+# CONFIG_CROS_HPS_I2C is not set
 # CONFIG_CROSS_MEMORY_ATTACH is not set
 CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_842 is not set
@@ -1148,13 +1024,8 @@ CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 # CONFIG_CRYPTO_AEGIS128 is not set
-# CONFIG_CRYPTO_AEGIS128L is not set
-# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set
 # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set
-# CONFIG_CRYPTO_AEGIS256 is not set
-# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set
 CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_AES_586 is not set
 # CONFIG_CRYPTO_AES_ARM is not set
 # CONFIG_CRYPTO_AES_ARM64 is not set
 # CONFIG_CRYPTO_AES_ARM64_BS is not set
@@ -1220,14 +1091,14 @@ CONFIG_CRYPTO_CTR=y
 # CONFIG_CRYPTO_DEV_CCREE is not set
 # CONFIG_CRYPTO_DEV_FSL_CAAM is not set
 # CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
 # CONFIG_CRYPTO_DEV_HISI_SEC is not set
 # CONFIG_CRYPTO_DEV_HISI_ZIP is not set
 # CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
 # CONFIG_CRYPTO_DEV_MARVELL_CESA is not set
-# CONFIG_CRYPTO_DEV_MEDIATEK is not set
-# CONFIG_CRYPTO_DEV_MV_CESA is not set
-# CONFIG_CRYPTO_DEV_MXC_SCC is not set
 # CONFIG_CRYPTO_DEV_MXS_DCP is not set
 # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
 # CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set
@@ -1258,7 +1129,6 @@ CONFIG_CRYPTO_CTR=y
 # CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_GCM=y
-CONFIG_CRYPTO_GF128MUL=y
 CONFIG_CRYPTO_GHASH=y
 # CONFIG_CRYPTO_GHASH_ARM64_CE is not set
 # CONFIG_CRYPTO_GHASH_ARM_CE is not set
@@ -1289,22 +1159,14 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-# CONFIG_CRYPTO_MCRYPTD is not set
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_MORUS1280 is not set
-# CONFIG_CRYPTO_MORUS1280_AVX2 is not set
-# CONFIG_CRYPTO_MORUS1280_SSE2 is not set
-# CONFIG_CRYPTO_MORUS640 is not set
-# CONFIG_CRYPTO_MORUS640_SSE2 is not set
 # CONFIG_CRYPTO_NHPOLY1305_NEON is not set
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_NULL2=y
 # CONFIG_CRYPTO_OFB is not set
 # CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_PCOMP is not set
-# CONFIG_CRYPTO_PCOMP2 is not set
 CONFIG_CRYPTO_PCRYPT=y
 # CONFIG_CRYPTO_POLY1305 is not set
 # CONFIG_CRYPTO_POLY1305_ARM is not set
@@ -1349,7 +1211,6 @@ CONFIG_CRYPTO_SKCIPHER2=y
 # CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
 # CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
 # CONFIG_CRYPTO_SM4_GENERIC is not set
-# CONFIG_CRYPTO_SPECK is not set
 # CONFIG_CRYPTO_STATS is not set
 # CONFIG_CRYPTO_STREEBOG is not set
 # CONFIG_CRYPTO_TEA is not set
@@ -1369,7 +1230,6 @@ CONFIG_CRYPTO_SKCIPHER2=y
 # CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_XTS is not set
 # CONFIG_CRYPTO_XXHASH is not set
-# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_ZSTD is not set
 # CONFIG_CS5535_MFGPT is not set
 # CONFIG_CS89x0 is not set
@@ -1378,12 +1238,8 @@ CONFIG_CRYPTO_SKCIPHER2=y
 # CONFIG_CUSE is not set
 # CONFIG_CW1200 is not set
 # CONFIG_CXD2880_SPI_DRV is not set
-# CONFIG_CXL_AFU_DRIVER_OPS is not set
 # CONFIG_CXL_BASE is not set
 # CONFIG_CXL_BUS is not set
-# CONFIG_CXL_EEH is not set
-# CONFIG_CXL_KERNEL_API is not set
-# CONFIG_CXL_LIB is not set
 # CONFIG_CYPRESS_FIRMWARE is not set
 # CONFIG_DA280 is not set
 # CONFIG_DA311 is not set
@@ -1394,14 +1250,11 @@ CONFIG_CRYPTO_SKCIPHER2=y
 # CONFIG_DDR is not set
 # CONFIG_DEBUG_ALIGN_RODATA is not set
 # CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_CGROUP_REF is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_EFI is not set
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
 # CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
 # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 CONFIG_DEBUG_FS=y
@@ -1441,14 +1294,12 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_NET is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_NX_TEST is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_DEBUG_PAGEALLOC is not set
 # CONFIG_DEBUG_PAGE_REF is not set
 # CONFIG_DEBUG_PERF_USE_VMALLOC is not set
 # CONFIG_DEBUG_PER_CPU_MAPS is not set
 # CONFIG_DEBUG_PINCTRL is not set
-# CONFIG_DEBUG_PI_LIST is not set
 # CONFIG_DEBUG_PLIST is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_RODATA_TEST is not set
@@ -1463,12 +1314,10 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
 # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
 # CONFIG_DEBUG_TIMEKEEPING is not set
 # CONFIG_DEBUG_UART_8250_PALMCHIP is not set
 # CONFIG_DEBUG_UART_8250_WORD is not set
-# CONFIG_DEBUG_UART_BCM63XX is not set
 # CONFIG_DEBUG_UART_FLOW_CONTROL is not set
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_VIRTUAL is not set
@@ -1477,15 +1326,12 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_VM_PGFLAGS is not set
 # CONFIG_DEBUG_VM_PGTABLE is not set
 # CONFIG_DEBUG_VM_RB is not set
-# CONFIG_DEBUG_VM_VMACACHE is not set
 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
 # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
 # CONFIG_DEBUG_WX is not set
 # CONFIG_DEBUG_ZBOOT is not set
-# CONFIG_DECNET is not set
 # CONFIG_DEFAULT_CODEL is not set
 CONFIG_DEFAULT_CUBIC=y
-CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_FQ is not set
 CONFIG_DEFAULT_FQ_CODEL=y
 # CONFIG_DEFAULT_FQ_PIE is not set
@@ -1494,15 +1340,12 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
 CONFIG_DEFAULT_INIT=""
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_DEFAULT_NET_SCH="fq_codel"
-# CONFIG_DEFAULT_NOOP is not set
 # CONFIG_DEFAULT_PFIFO_FAST is not set
 # CONFIG_DEFAULT_RENO is not set
-CONFIG_DEFAULT_SECURITY=""
 CONFIG_DEFAULT_SECURITY_DAC=y
 # CONFIG_DEFAULT_SECURITY_SELINUX is not set
 # CONFIG_DEFAULT_SFQ is not set
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
 # CONFIG_DELL_LAPTOP is not set
 # CONFIG_DELL_RBTN is not set
@@ -1510,27 +1353,13 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 # CONFIG_DELL_SMO8800 is not set
 # CONFIG_DEPRECATED_PARAM_STRUCT is not set
 # CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_DEVKMEM is not set
 # CONFIG_DEVMEM is not set
 CONFIG_DEVPORT=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_DEVTMPFS is not set
 # CONFIG_DEVTMPFS_MOUNT is not set
 # CONFIG_DEVTMPFS_SAFE is not set
 # CONFIG_DEV_DAX is not set
-# CONFIG_DGAP is not set
-# CONFIG_DGNC is not set
 # CONFIG_DHT11 is not set
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set
-# CONFIG_DISPLAY_CONNECTOR_DVI is not set
-# CONFIG_DISPLAY_CONNECTOR_HDMI is not set
-# CONFIG_DISPLAY_ENCODER_TFP410 is not set
-# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set
-# CONFIG_DISPLAY_PANEL_DPI is not set
-# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set
-# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set
-# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set
 # CONFIG_DL2K is not set
 # CONFIG_DLHL60D is not set
 # CONFIG_DLM is not set
@@ -1547,7 +1376,6 @@ CONFIG_DEVPORT=y
 # CONFIG_DMARD06 is not set
 # CONFIG_DMARD09 is not set
 # CONFIG_DMARD10 is not set
-# CONFIG_DMASCC is not set
 # CONFIG_DMATEST is not set
 # CONFIG_DMA_API_DEBUG is not set
 CONFIG_DMA_COHERENT_POOL=y
@@ -1557,11 +1385,8 @@ CONFIG_DMA_DECLARE_COHERENT=y
 # CONFIG_DMA_JZ4780 is not set
 # CONFIG_DMA_MAP_BENCHMARK is not set
 CONFIG_DMA_NONCOHERENT_MMAP=y
-# CONFIG_DMA_NOOP_OPS is not set
-# CONFIG_DMA_PERNUMA_CMA is not set
 # CONFIG_DMA_RESTRICTED_POOL is not set
 # CONFIG_DMA_SHARED_BUFFER is not set
-# CONFIG_DMA_VIRT_OPS is not set
 # CONFIG_DM_CACHE is not set
 # CONFIG_DM_CLONE is not set
 # CONFIG_DM_DEBUG is not set
@@ -1573,7 +1398,6 @@ CONFIG_DMA_NONCOHERENT_MMAP=y
 # CONFIG_DM_INTEGRITY is not set
 # CONFIG_DM_LOG_USERSPACE is not set
 # CONFIG_DM_LOG_WRITES is not set
-# CONFIG_DM_MQ_DEFAULT is not set
 # CONFIG_DM_MULTIPATH is not set
 # CONFIG_DM_RAID is not set
 # CONFIG_DM_SWITCH is not set
@@ -1587,7 +1411,6 @@ CONFIG_DMA_NONCOHERENT_MMAP=y
 # CONFIG_DNET is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_DNS_RESOLVER is not set
-CONFIG_DOUBLEFAULT=y
 # CONFIG_DP83640_PHY is not set
 # CONFIG_DP83822_PHY is not set
 # CONFIG_DP83848_PHY is not set
@@ -1604,14 +1427,10 @@ CONFIG_DQL=y
 # CONFIG_DRM_ACCEL is not set
 # CONFIG_DRM_AMDGPU is not set
 # CONFIG_DRM_AMDGPU_CIK is not set
-# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
 # CONFIG_DRM_AMDGPU_SI is not set
 # CONFIG_DRM_AMDGPU_USERPTR is not set
 # CONFIG_DRM_AMDGPU_WERROR is not set
 # CONFIG_DRM_AMD_ACP is not set
-# CONFIG_DRM_AMD_DC_DCN2_0 is not set
-# CONFIG_DRM_AMD_DC_DCN3_0 is not set
-# CONFIG_DRM_AMD_DC_HDCP is not set
 # CONFIG_DRM_AMD_DC_SI is not set
 # CONFIG_DRM_AMD_SECURE_DISPLAY is not set
 # CONFIG_DRM_ANALOGIX_ANX6345 is not set
@@ -1630,11 +1449,9 @@ CONFIG_DQL=y
 # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
 # CONFIG_DRM_DEBUG_MM is not set
 # CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
 # CONFIG_DRM_DISPLAY_CONNECTOR is not set
 # CONFIG_DRM_DP_AUX_CHARDEV is not set
 # CONFIG_DRM_DP_CEC is not set
-# CONFIG_DRM_DUMB_VGA_DAC is not set
 # CONFIG_DRM_DW_HDMI_CEC is not set
 # CONFIG_DRM_ETNAVIV is not set
 # CONFIG_DRM_EXYNOS is not set
@@ -1668,7 +1485,6 @@ CONFIG_DQL=y
 # CONFIG_DRM_LONTIUM_LT9611UXC is not set
 # CONFIG_DRM_LOONGSON is not set
 # CONFIG_DRM_LVDS_CODEC is not set
-# CONFIG_DRM_LVDS_ENCODER is not set
 # CONFIG_DRM_MALI_DISPLAY is not set
 # CONFIG_DRM_MCDE is not set
 # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
@@ -1691,12 +1507,13 @@ CONFIG_DQL=y
 # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
 # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
 # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
 # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
 # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
-# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
 # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
 # CONFIG_DRM_PANEL_JDI_R63452 is not set
 # CONFIG_DRM_PANEL_KHADAS_TS050 is not set
@@ -1706,13 +1523,16 @@ CONFIG_DQL=y
 # CONFIG_DRM_PANEL_LG_LB035Q02 is not set
 # CONFIG_DRM_PANEL_LG_LG4573 is not set
 # CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
 # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
 # CONFIG_DRM_PANEL_MIPI_DBI is not set
 # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
 # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
 # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
@@ -1723,7 +1543,6 @@ CONFIG_DQL=y
 # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
 # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
 # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
-# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set
 # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
@@ -1746,17 +1565,18 @@ CONFIG_DQL=y
 # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
 # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
 # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
-# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
 # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
 # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
 # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
 # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
 # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
 # CONFIG_DRM_PANEL_TPO_TPG110 is not set
-# CONFIG_DRM_PANEL_TPO_Y17P is not set
 # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
+# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
 # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
-# CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
 # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
 # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
 # CONFIG_DRM_PANFROST is not set
@@ -1771,9 +1591,6 @@ CONFIG_DQL=y
 # CONFIG_DRM_RCAR_USE_LVDS is not set
 # CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
 # CONFIG_DRM_ROCKCHIP is not set
-# CONFIG_DRM_RP1_DPI is not set
-# CONFIG_DRM_RP1_DSI is not set
-# CONFIG_DRM_RP1_VEC is not set
 # CONFIG_DRM_SAMSUNG_DSIM is not set
 # CONFIG_DRM_SII902X is not set
 # CONFIG_DRM_SII9234 is not set
@@ -1787,7 +1604,6 @@ CONFIG_DQL=y
 # CONFIG_DRM_THINE_THC63LVD1024 is not set
 # CONFIG_DRM_TIDSS is not set
 # CONFIG_DRM_TILCDC is not set
-# CONFIG_DRM_TINYDRM is not set
 # CONFIG_DRM_TI_DLPC3433 is not set
 # CONFIG_DRM_TI_SN65DSI83 is not set
 # CONFIG_DRM_TI_SN65DSI86 is not set
@@ -2002,9 +1818,7 @@ CONFIG_EFI_PARTITION=y
 CONFIG_ELFCORE=y
 # CONFIG_ELF_CORE is not set
 # CONFIG_EMAC_ROCKCHIP is not set
-CONFIG_EMBEDDED=y
 # CONFIG_EM_TIMER_STI is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
 # CONFIG_ENA_ETHERNET is not set
 # CONFIG_ENC28J60 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -2032,14 +1846,12 @@ CONFIG_EXPORTFS=y
 CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT3_FS is not set
 # CONFIG_EXT4_DEBUG is not set
-# CONFIG_EXT4_ENCRYPTION is not set
 # CONFIG_EXT4_FS is not set
 # CONFIG_EXT4_FS_POSIX_ACL is not set
 # CONFIG_EXT4_FS_SECURITY is not set
 CONFIG_EXT4_USE_FOR_EXT2=y
 # CONFIG_EXTCON is not set
 # CONFIG_EXTCON_ADC_JACK is not set
-# CONFIG_EXTCON_ARIZONA is not set
 # CONFIG_EXTCON_AXP288 is not set
 # CONFIG_EXTCON_FSA9480 is not set
 # CONFIG_EXTCON_GPIO is not set
@@ -2054,19 +1866,16 @@ CONFIG_EXT4_USE_FOR_EXT2=y
 CONFIG_EXTRA_FIRMWARE=""
 CONFIG_EXTRA_TARGETS=""
 # CONFIG_EXYNOS_ADC is not set
-# CONFIG_EXYNOS_VIDEO is not set
 # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
 # CONFIG_EZX_PCAP is not set
 # CONFIG_F2FS_CHECK_FS is not set
 # CONFIG_F2FS_FAULT_INJECTION is not set
 # CONFIG_F2FS_FS is not set
 # CONFIG_F2FS_FS_COMPRESSION is not set
-# CONFIG_F2FS_FS_ENCRYPTION is not set
 # CONFIG_F2FS_FS_POSIX_ACL is not set
 # CONFIG_F2FS_FS_SECURITY is not set
 CONFIG_F2FS_FS_XATTR=y
 # CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_IO_TRACE is not set
 CONFIG_F2FS_STAT_FS=y
 # CONFIG_F2FS_UNFAIR_RWSEM is not set
 # CONFIG_FAILOVER is not set
@@ -2087,10 +1896,8 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_FB_ATMEL is not set
 # CONFIG_FB_ATY is not set
 # CONFIG_FB_ATY128 is not set
-# CONFIG_FB_AUO_K190X is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 # CONFIG_FB_BOTH_ENDIAN is not set
 # CONFIG_FB_BROADSHEET is not set
 # CONFIG_FB_CARMINE is not set
@@ -2103,7 +1910,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_FB_DA8XX is not set
 # CONFIG_FB_DDC is not set
 # CONFIG_FB_DEVICE is not set
-# CONFIG_FB_FLEX is not set
 # CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_FSL_DIU is not set
 # CONFIG_FB_GEODE is not set
@@ -2121,7 +1927,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_FB_MB862XX is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_MXS is not set
 # CONFIG_FB_N411 is not set
 # CONFIG_FB_NEOMAGIC is not set
 CONFIG_FB_NOTIFY=y
@@ -2135,7 +1940,6 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_PXA is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_RIVA is not set
-# CONFIG_FB_RPISENSE is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_S3 is not set
 # CONFIG_FB_SAVAGE is not set
@@ -2153,7 +1957,6 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_TFT is not set
 # CONFIG_FB_TFT_AGM1264K_FL is not set
 # CONFIG_FB_TFT_BD663474 is not set
-# CONFIG_FB_TFT_FBTFT_DEVICE is not set
 # CONFIG_FB_TFT_HX8340BN is not set
 # CONFIG_FB_TFT_HX8347D is not set
 # CONFIG_FB_TFT_HX8353D is not set
@@ -2174,7 +1977,6 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_TFT_SSD1289 is not set
 # CONFIG_FB_TFT_SSD1305 is not set
 # CONFIG_FB_TFT_SSD1306 is not set
-# CONFIG_FB_TFT_SSD1325 is not set
 # CONFIG_FB_TFT_SSD1331 is not set
 # CONFIG_FB_TFT_SSD1351 is not set
 # CONFIG_FB_TFT_ST7735R is not set
@@ -2184,9 +1986,7 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_TFT_UC1611 is not set
 # CONFIG_FB_TFT_UC1701 is not set
 # CONFIG_FB_TFT_UPD161704 is not set
-# CONFIG_FB_TFT_WATTEROTT is not set
 # CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_TMIO is not set
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_UDL is not set
 # CONFIG_FB_UVESA is not set
@@ -2195,12 +1995,10 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_VOODOO1 is not set
 # CONFIG_FB_VT8623 is not set
-# CONFIG_FB_XGI is not set
 # CONFIG_FCOE is not set
 # CONFIG_FCOE_FNIC is not set
 # CONFIG_FDDI is not set
 # CONFIG_FEALNX is not set
-# CONFIG_FENCE_TRACE is not set
 # CONFIG_FHANDLE is not set
 CONFIG_FIB_RULES=y
 # CONFIG_FIELDBUS_DEV is not set
@@ -2208,16 +2006,12 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIND_BIT_BENCHMARK is not set
 # CONFIG_FIREWIRE is not set
 # CONFIG_FIREWIRE_NOSY is not set
-# CONFIG_FIREWIRE_SERIAL is not set
 # CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
-CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_FM10K is not set
-# CONFIG_FMC is not set
 # CONFIG_FONTS is not set
 # CONFIG_FONT_6x8 is not set
 # CONFIG_FONT_TER16x32 is not set
@@ -2231,7 +2025,6 @@ CONFIG_FORTIFY_SOURCE=y
 # CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
 # CONFIG_FRAME_POINTER is not set
 # CONFIG_FREEZER is not set
-# CONFIG_FRONTSWAP is not set
 # CONFIG_FSCACHE is not set
 # CONFIG_FSI is not set
 # CONFIG_FSL_DPAA2_SWITCH is not set
@@ -2291,7 +2084,6 @@ CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
 CONFIG_GACT_PROB=y
 # CONFIG_GADGET_UAC1 is not set
 # CONFIG_GAMEPORT is not set
-# CONFIG_GATEWORKS_GW16083 is not set
 # CONFIG_GCC_PLUGINS is not set
 # CONFIG_GCOV is not set
 # CONFIG_GCOV_KERNEL is not set
@@ -2312,9 +2104,6 @@ CONFIG_GENERIC_VDSO_TIME_NS=y
 # CONFIG_GENEVE is not set
 # CONFIG_GENWQE is not set
 # CONFIG_GFS2_FS is not set
-# CONFIG_GIGASET_CAPI is not set
-# CONFIG_GIGASET_DEBUG is not set
-# CONFIG_GIGASET_DUMMYLL is not set
 # CONFIG_GLOB_SELFTEST is not set
 # CONFIG_GNSS is not set
 # CONFIG_GOLDFISH is not set
@@ -2334,7 +2123,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
 # CONFIG_GPIO_74X164 is not set
 # CONFIG_GPIO_74XX_MMIO is not set
 # CONFIG_GPIO_ADNP is not set
-# CONFIG_GPIO_ADP5588 is not set
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_ALTERA is not set
 # CONFIG_GPIO_AMD8111 is not set
@@ -2365,7 +2153,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
 # CONFIG_GPIO_IT87 is not set
 # CONFIG_GPIO_LATCH is not set
 # CONFIG_GPIO_LOGICVC is not set
-# CONFIG_GPIO_LYNXPOINT is not set
 # CONFIG_GPIO_MAX3191X is not set
 # CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX7301 is not set
@@ -2384,7 +2171,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
 # CONFIG_GPIO_PCI_IDIO_16 is not set
 # CONFIG_GPIO_PISOSR is not set
 # CONFIG_GPIO_PL061 is not set
-# CONFIG_GPIO_PWM is not set
 # CONFIG_GPIO_RCAR is not set
 # CONFIG_GPIO_RDC321X is not set
 # CONFIG_GPIO_SAMA5D2_PIOBU is not set
@@ -2392,7 +2178,6 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
 # CONFIG_GPIO_SCH311X is not set
 # CONFIG_GPIO_SIFIVE is not set
 # CONFIG_GPIO_SIM is not set
-# CONFIG_GPIO_SX150X is not set
 # CONFIG_GPIO_SYSCON is not set
 CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_TPIC2810 is not set
@@ -2407,24 +2192,17 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_GPIO_XILINX is not set
 # CONFIG_GPIO_XRA1403 is not set
 # CONFIG_GPIO_ZEVIO is not set
-# CONFIG_GPIO_ZX is not set
 # CONFIG_GP_PCI1XXXX is not set
 # CONFIG_GREENASIA_FF is not set
 # CONFIG_GREYBUS is not set
-# CONFIG_GS_FPGABOOT is not set
 # CONFIG_GTP is not set
-# CONFIG_GUP_BENCHMARK is not set
 # CONFIG_GUP_TEST is not set
 # CONFIG_GVE is not set
-# CONFIG_HABANA_AI is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_HAPPYMEAL is not set
 CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_FALLBACK is not set
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
 CONFIG_HARDEN_BRANCH_HISTORY=y
-CONFIG_HARDEN_EL2_VECTORS=y
 # CONFIG_HARDLOCKUP_DETECTOR is not set
 # CONFIG_HAVE_ARM_ARCH_TIMER is not set
 # CONFIG_HCALL_STATS is not set
@@ -2438,14 +2216,10 @@ CONFIG_HARDEN_EL2_VECTORS=y
 # CONFIG_HDLC_RAW_ETH is not set
 # CONFIG_HDMI_LPE_AUDIO is not set
 # CONFIG_HDQ_MASTER_OMAP is not set
-# CONFIG_HEADERS_CHECK is not set
 # CONFIG_HEADERS_INSTALL is not set
-# CONFIG_HEADER_TEST is not set
 # CONFIG_HERMES is not set
 # CONFIG_HFSPLUS_FS is not set
-# CONFIG_HFSPLUS_FS_POSIX_ACL is not set
 # CONFIG_HFS_FS is not set
-# CONFIG_HFS_FS_POSIX_ACL is not set
 # CONFIG_HI6421V600_IRQ is not set
 # CONFIG_HI8435 is not set
 # CONFIG_HIBERNATION is not set
@@ -2592,19 +2366,15 @@ CONFIG_HIGH_RES_TIMERS=y
 # CONFIG_HOTPLUG_CPU is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HP03 is not set
-# CONFIG_HP100 is not set
 # CONFIG_HP206C is not set
 CONFIG_HPET_MMAP_DEFAULT=y
 # CONFIG_HPFS_FS is not set
 # CONFIG_HP_ILO is not set
 # CONFIG_HP_WATCHDOG is not set
-# CONFIG_HP_WIRELESS is not set
 # CONFIG_HSA_AMD is not set
 # CONFIG_HSI is not set
 # CONFIG_HSR is not set
 # CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_HTC_PASIC3 is not set
 # CONFIG_HTE is not set
 # CONFIG_HTS221 is not set
 # CONFIG_HTU21 is not set
@@ -2644,8 +2414,6 @@ CONFIG_HW_RANDOM_TPM=y
 # CONFIG_HW_RANDOM_XIPHERA is not set
 # CONFIG_HX711 is not set
 # CONFIG_HYPERV is not set
-# CONFIG_HYPERV_TSCPAGE is not set
-# CONFIG_HYSDN is not set
 CONFIG_HZ=100
 CONFIG_HZ_100=y
 # CONFIG_HZ_1000 is not set
@@ -2722,7 +2490,6 @@ CONFIG_HZ_100=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_OCTEON is not set
 # CONFIG_I2C_PARPORT is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_PCA_ISA is not set
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_PCI1XXXX is not set
@@ -2771,12 +2538,7 @@ CONFIG_HZ_100=y
 # CONFIG_ICP10100 is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_ICS932S401 is not set
-# CONFIG_ICST is not set
-# CONFIG_IDE is not set
 # CONFIG_IDEAPAD_LAPTOP is not set
-# CONFIG_IDE_GD is not set
-# CONFIG_IDE_PROC_FS is not set
-# CONFIG_IDE_TASK_IOCTL is not set
 # CONFIG_IDLE_PAGE_TRACKING is not set
 # CONFIG_IEEE802154 is not set
 # CONFIG_IEEE802154_ADF7242 is not set
@@ -2793,7 +2555,6 @@ CONFIG_HZ_100=y
 # CONFIG_IIO_BUFFER_CB is not set
 # CONFIG_IIO_BUFFER_DMA is not set
 # CONFIG_IIO_BUFFER_DMAENGINE is not set
-# CONFIG_IIO_BUFFER_HDC2010 is not set
 # CONFIG_IIO_BUFFER_HW_CONSUMER is not set
 # CONFIG_IIO_CONFIGFS is not set
 CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
@@ -2802,7 +2563,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 # CONFIG_IIO_KX022A_I2C is not set
 # CONFIG_IIO_KX022A_SPI is not set
 # CONFIG_IIO_MUX is not set
-# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
 # CONFIG_IIO_RESCALE is not set
 # CONFIG_IIO_SIMPLE_DUMMY is not set
 # CONFIG_IIO_SSP_SENSORHUB is not set
@@ -2821,11 +2581,11 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 # CONFIG_IKCONFIG_PROC is not set
 # CONFIG_IKHEADERS is not set
 # CONFIG_IMA is not set
-# CONFIG_IMAGE_CMDLINE_HACK is not set
 # CONFIG_IMGPDC_WDT is not set
 # CONFIG_IMG_MDC_DMA is not set
 # CONFIG_IMX7D_ADC is not set
 # CONFIG_IMX8QXP_ADC is not set
+# CONFIG_IMX93_ADC is not set
 # CONFIG_IMX_IPUV3_CORE is not set
 # CONFIG_IMX_THERMAL is not set
 # CONFIG_INA2XX_ADC is not set
@@ -2842,7 +2602,6 @@ CONFIG_INET=y
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_ESPINTCP is not set
 # CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_LRO is not set
 CONFIG_INET_TABLE_PERTURB_ORDER=16
 # CONFIG_INET_TCP_DIAG is not set
 # CONFIG_INET_TUNNEL is not set
@@ -2891,11 +2650,9 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_INPUT_EVBUG is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_GP2A is not set
 # CONFIG_INPUT_GPIO_BEEPER is not set
 # CONFIG_INPUT_GPIO_DECODER is not set
 # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-# CONFIG_INPUT_GPIO_TILT_POLLED is not set
 # CONFIG_INPUT_GPIO_VIBRA is not set
 # CONFIG_INPUT_IBM_PANEL is not set
 # CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
@@ -2915,18 +2672,14 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_MMA8450 is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_MPU3050 is not set
-# CONFIG_INPUT_MSM_VIBRATOR is not set
 # CONFIG_INPUT_PALMAS_PWRBUTTON is not set
 # CONFIG_INPUT_PCF8574 is not set
 # CONFIG_INPUT_PCSPKR is not set
 # CONFIG_INPUT_PM8941_PWRKEY is not set
 # CONFIG_INPUT_PM8XXX_VIBRATOR is not set
-# CONFIG_INPUT_POLLDEV is not set
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_PWM_BEEPER is not set
 # CONFIG_INPUT_PWM_VIBRA is not set
-# CONFIG_INPUT_RASPBERRYPI_BUTTON is not set
 # CONFIG_INPUT_REGULATOR_HAPTIC is not set
 # CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
 # CONFIG_INPUT_SPARSEKMAP is not set
@@ -2945,7 +2698,6 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INTEGRITY_SIGNATURE is not set
 # CONFIG_INTEL_ATOMISP2_LED is not set
 # CONFIG_INTEL_ATOMISP2_PM is not set
-# CONFIG_INTEL_CHT_INT33FE is not set
 # CONFIG_INTEL_HID_EVENT is not set
 # CONFIG_INTEL_IDLE is not set
 # CONFIG_INTEL_IDMA64 is not set
@@ -2955,9 +2707,6 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INTEL_MEI is not set
 # CONFIG_INTEL_MEI_ME is not set
 # CONFIG_INTEL_MEI_TXE is not set
-# CONFIG_INTEL_MIC_CARD is not set
-# CONFIG_INTEL_MIC_HOST is not set
-# CONFIG_INTEL_MID_PTI is not set
 # CONFIG_INTEL_OAKTRAIL is not set
 # CONFIG_INTEL_PMC_CORE is not set
 # CONFIG_INTEL_PUNIT_IPC is not set
@@ -3042,7 +2791,6 @@ CONFIG_IPW2200_MONITOR=y
 # CONFIG_IPW2200_QOS is not set
 # CONFIG_IPW2200_RADIOTAP is not set
 # CONFIG_IPWIRELESS is not set
-# CONFIG_IPX is not set
 CONFIG_IP_ADVANCED_ROUTER=y
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_FIB_TRIE_STATS is not set
@@ -3062,7 +2810,6 @@ CONFIG_IP_MULTIPLE_TABLES=y
 # CONFIG_IP_NF_MATCH_TTL is not set
 # CONFIG_IP_NF_RAW is not set
 # CONFIG_IP_NF_SECURITY is not set
-# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
 # CONFIG_IP_NF_TARGET_ECN is not set
 # CONFIG_IP_NF_TARGET_MASQUERADE is not set
 # CONFIG_IP_NF_TARGET_NETMAP is not set
@@ -3082,10 +2829,8 @@ CONFIG_IP_ROUTE_VERBOSE=y
 # CONFIG_IP_VS_MH is not set
 CONFIG_IP_VS_MH_TAB_INDEX=10
 # CONFIG_IP_VS_TWOS is not set
-# CONFIG_IRDA is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_IRQ_ALL_CPUS is not set
-# CONFIG_IRQ_DOMAIN_DEBUG is not set
 # CONFIG_IRQ_POLL is not set
 # CONFIG_IRQ_TIME_ACCOUNTING is not set
 # CONFIG_IRSD200 is not set
@@ -3097,14 +2842,12 @@ CONFIG_IP_VS_MH_TAB_INDEX=10
 # CONFIG_IR_IMON is not set
 # CONFIG_IR_IMON_RAW is not set
 # CONFIG_IR_JVC_DECODER is not set
-# CONFIG_IR_LIRC_CODEC is not set
 # CONFIG_IR_MCEUSB is not set
 # CONFIG_IR_NEC_DECODER is not set
 # CONFIG_IR_RC5_DECODER is not set
 # CONFIG_IR_RC6_DECODER is not set
 # CONFIG_IR_REDRAT3 is not set
 # CONFIG_IR_SERIAL is not set
-# CONFIG_IR_SIR is not set
 # CONFIG_IR_SONY_DECODER is not set
 # CONFIG_IR_STREAMZAP is not set
 # CONFIG_IR_TOY is not set
@@ -3114,18 +2857,7 @@ CONFIG_IP_VS_MH_TAB_INDEX=10
 # CONFIG_ISCSI_BOOT_SYSFS is not set
 # CONFIG_ISCSI_TCP is not set
 CONFIG_ISDN=y
-# CONFIG_ISDN_AUDIO is not set
 # CONFIG_ISDN_CAPI is not set
-# CONFIG_ISDN_CAPI_CAPIDRV is not set
-# CONFIG_ISDN_DIVERSION is not set
-# CONFIG_ISDN_DRV_ACT2000 is not set
-# CONFIG_ISDN_DRV_GIGASET is not set
-# CONFIG_ISDN_DRV_HISAX is not set
-# CONFIG_ISDN_DRV_ICN is not set
-# CONFIG_ISDN_DRV_LOOP is not set
-# CONFIG_ISDN_DRV_PCBIT is not set
-# CONFIG_ISDN_DRV_SC is not set
-# CONFIG_ISDN_I4L is not set
 # CONFIG_ISL29003 is not set
 # CONFIG_ISL29020 is not set
 # CONFIG_ISL29125 is not set
@@ -3135,7 +2867,6 @@ CONFIG_ISDN=y
 # CONFIG_ITG3200 is not set
 # CONFIG_IWL3945 is not set
 # CONFIG_IWLWIFI is not set
-# CONFIG_IXGB is not set
 # CONFIG_IXGBE is not set
 # CONFIG_IXGBEVF is not set
 # CONFIG_JAILHOUSE_GUEST is not set
@@ -3168,7 +2899,6 @@ CONFIG_JOLIET=y
 # CONFIG_JSA1212 is not set
 # CONFIG_JUMP_LABEL is not set
 # CONFIG_JZ4740_WDT is not set
-# CONFIG_JZ4770_PHY is not set
 # CONFIG_KALLSYMS is not set
 # CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set
 # CONFIG_KALLSYMS_ALL is not set
@@ -3184,7 +2914,6 @@ CONFIG_KASAN_STACK=y
 CONFIG_KCOV_IRQ_AREA_SIZE=0x40000
 # CONFIG_KCSAN is not set
 # CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_CAT is not set
 # CONFIG_KERNEL_GZIP is not set
 # CONFIG_KERNEL_LZ4 is not set
 # CONFIG_KERNEL_LZMA is not set
@@ -3240,9 +2969,7 @@ CONFIG_KERNFS=y
 # CONFIG_KEY_DH_OPERATIONS is not set
 # CONFIG_KFENCE is not set
 # CONFIG_KGDB is not set
-# CONFIG_KMEMCHECK is not set
 # CONFIG_KMX61 is not set
-# CONFIG_KPC2000 is not set
 # CONFIG_KPROBES is not set
 # CONFIG_KPROBES_SANITY_TEST is not set
 # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
@@ -3269,25 +2996,20 @@ CONFIG_KUSER_HELPERS=y
 # CONFIG_L2TP_V3 is not set
 # CONFIG_LAN743X is not set
 # CONFIG_LAN966X_SWITCH is not set
-# CONFIG_LANMEDIA is not set
 # CONFIG_LANTIQ is not set
 # CONFIG_LAPB is not set
-# CONFIG_LASAT is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_LBDAF=y
 # CONFIG_LCD_AMS369FG06 is not set
 # CONFIG_LCD_CLASS_DEVICE is not set
 # CONFIG_LCD_HX8357 is not set
 # CONFIG_LCD_ILI922X is not set
 # CONFIG_LCD_ILI9320 is not set
 # CONFIG_LCD_L4F00242T03 is not set
-# CONFIG_LCD_LD9040 is not set
 # CONFIG_LCD_LMS283GF05 is not set
 # CONFIG_LCD_LMS501KF03 is not set
 # CONFIG_LCD_LTV350QV is not set
 # CONFIG_LCD_OTM3225A is not set
-# CONFIG_LCD_S6E63M0 is not set
 # CONFIG_LCD_TDO24M is not set
 # CONFIG_LCD_VGG2432A4 is not set
 CONFIG_LDISC_AUTOLOAD=y
@@ -3371,7 +3093,6 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 # CONFIG_LED_TRIGGER_PHY is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_LEGACY_TIOCSTI is not set
-# CONFIG_LGUEST is not set
 # CONFIG_LIB80211 is not set
 # CONFIG_LIB80211_CRYPT_CCMP is not set
 # CONFIG_LIB80211_CRYPT_TKIP is not set
@@ -3385,13 +3106,11 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 # CONFIG_LIBFCOE is not set
 # CONFIG_LIBIPW_DEBUG is not set
 # CONFIG_LIBNVDIMM is not set
-CONFIG_LIB_MEMNEQ=y
 # CONFIG_LIDAR_LITE_V2 is not set
 CONFIG_LINEAR_RANGES=y
 # CONFIG_LIQUIDIO is not set
 # CONFIG_LIQUIDIO_VF is not set
 # CONFIG_LIRC is not set
-# CONFIG_LIS3L02DQ is not set
 # CONFIG_LIST_HARDENED is not set
 # CONFIG_LITEX_LITEETH is not set
 # CONFIG_LITEX_SOC_CONTROLLER is not set
@@ -3401,7 +3120,6 @@ CONFIG_LLC=y
 # CONFIG_LLC2 is not set
 # CONFIG_LMK04832 is not set
 # CONFIG_LMP91000 is not set
-# CONFIG_LNET is not set
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_LOCKD is not set
@@ -3417,7 +3135,6 @@ CONFIG_LOCKD_V4=y
 CONFIG_LOCK_MM_AND_FIND_VMA=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_LOGFS is not set
 # CONFIG_LOGIG940_FF is not set
 # CONFIG_LOGIRUMBLEPAD2_FF is not set
 # CONFIG_LOGITECH_FF is not set
@@ -3445,10 +3162,8 @@ CONFIG_LSM_MMAP_MIN_ADDR=65536
 # CONFIG_LTC2983 is not set
 # CONFIG_LTE_GDM724X is not set
 CONFIG_LTO_NONE=y
-# CONFIG_LTPC is not set
 # CONFIG_LTR501 is not set
 # CONFIG_LTRF216A is not set
-# CONFIG_LUSTRE_FS is not set
 # CONFIG_LV0104CS is not set
 # CONFIG_LWTUNNEL is not set
 # CONFIG_LXT_PHY is not set
@@ -3475,12 +3190,8 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
 # CONFIG_MACH_LOONGSON64 is not set
 # CONFIG_MACH_NINTENDO64 is not set
 # CONFIG_MACH_PIC32 is not set
-# CONFIG_MACH_PISTACHIO is not set
 # CONFIG_MACH_REALTEK_RTL is not set
-# CONFIG_MACH_TX39XX is not set
 # CONFIG_MACH_TX49XX is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_MACH_XILFPGA is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 # CONFIG_MACSEC is not set
 # CONFIG_MACVLAN is not set
@@ -3494,7 +3205,6 @@ CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
 CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
 # CONFIG_MAILBOX is not set
 # CONFIG_MANAGER_SBS is not set
-# CONFIG_MANDATORY_FILE_LOCKING is not set
 # CONFIG_MANGLE_BOOTARGS is not set
 # CONFIG_MARVELL_10G_PHY is not set
 # CONFIG_MARVELL_88Q2XXX_PHY is not set
@@ -3526,7 +3236,6 @@ CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
 # CONFIG_MAXIM_THERMOCOUPLE is not set
 # CONFIG_MAXLINEAR_GPHY is not set
 CONFIG_MAX_SKB_FRAGS=17
-CONFIG_MAY_USE_DEVLINK=y
 # CONFIG_MB1232 is not set
 # CONFIG_MC3230 is not set
 # CONFIG_MCB is not set
@@ -3557,7 +3266,6 @@ CONFIG_MAY_USE_DEVLINK=y
 # CONFIG_MDIO_MVUSB is not set
 # CONFIG_MDIO_OCTEON is not set
 # CONFIG_MDIO_THUNDER is not set
-# CONFIG_MDIO_XPCS is not set
 # CONFIG_MDM_GCC_9607 is not set
 # CONFIG_MD_BITMAP_FILE is not set
 # CONFIG_MD_FAULTY is not set
@@ -3574,7 +3282,6 @@ CONFIG_MAY_USE_DEVLINK=y
 # CONFIG_MEDIA_PLATFORM_DRIVERS is not set
 # CONFIG_MEDIA_PLATFORM_SUPPORT is not set
 # CONFIG_MEDIA_RADIO_SUPPORT is not set
-# CONFIG_MEDIA_RC_SUPPORT is not set
 # CONFIG_MEDIA_SDR_SUPPORT is not set
 # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
 # CONFIG_MEDIA_SUPPORT is not set
@@ -3642,7 +3349,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_ARIZONA_SPI is not set
 # CONFIG_MFD_AS3711 is not set
 # CONFIG_MFD_AS3722 is not set
-# CONFIG_MFD_ASIC3 is not set
 # CONFIG_MFD_ATC260X_I2C is not set
 # CONFIG_MFD_ATMEL_FLEXCOM is not set
 # CONFIG_MFD_ATMEL_HLCDC is not set
@@ -3652,7 +3358,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_BD9571MWV is not set
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_CPCAP is not set
-# CONFIG_MFD_CROS_EC is not set
 # CONFIG_MFD_CS42L43_I2C is not set
 # CONFIG_MFD_CS5535 is not set
 # CONFIG_MFD_DA9052_I2C is not set
@@ -3666,7 +3371,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_GATEWORKS_GSC is not set
 # CONFIG_MFD_HI6421_PMIC is not set
 # CONFIG_MFD_INTEL_M10_BMC_SPI is not set
-# CONFIG_MFD_INTEL_PMT is not set
 # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
 # CONFIG_MFD_IQS62X is not set
 # CONFIG_MFD_JANZ_CMODIO is not set
@@ -3702,52 +3406,39 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_OMAP_USB_HOST is not set
 # CONFIG_MFD_PALMAS is not set
 # CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_PM8921_CORE is not set
 # CONFIG_MFD_PM8XXX is not set
 # CONFIG_MFD_QCOM_PM8008 is not set
-# CONFIG_MFD_RASPBERRYPI_POE_HAT is not set
 # CONFIG_MFD_RC5T583 is not set
 # CONFIG_MFD_RDC321X is not set
 # CONFIG_MFD_RETU is not set
-# CONFIG_MFD_RK808 is not set
 # CONFIG_MFD_RK8XX_I2C is not set
 # CONFIG_MFD_RK8XX_SPI is not set
 # CONFIG_MFD_RN5T618 is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
-# CONFIG_MFD_RP1 is not set
-# CONFIG_MFD_RPISENSE_CORE is not set
 # CONFIG_MFD_RSMU_I2C is not set
 # CONFIG_MFD_RSMU_SPI is not set
 # CONFIG_MFD_RT4831 is not set
 # CONFIG_MFD_RT5033 is not set
 # CONFIG_MFD_RT5120 is not set
-# CONFIG_MFD_RTSX_PCI is not set
-# CONFIG_MFD_RTSX_USB is not set
 # CONFIG_MFD_SEC_CORE is not set
 # CONFIG_MFD_SI476X_CORE is not set
 # CONFIG_MFD_SKY81452 is not set
 # CONFIG_MFD_SL28CPLD is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_SMPRO is not set
-# CONFIG_MFD_SMSC is not set
 # CONFIG_MFD_STMFX is not set
 # CONFIG_MFD_STMPE is not set
 # CONFIG_MFD_STPMIC1 is not set
 # CONFIG_MFD_SY7636A is not set
 # CONFIG_MFD_SYSCON is not set
-# CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
 # CONFIG_MFD_TIMBERDALE is not set
 # CONFIG_MFD_TI_AM335X_TSCADC is not set
 # CONFIG_MFD_TI_LMU is not set
 # CONFIG_MFD_TI_LP873X is not set
 # CONFIG_MFD_TI_LP87565 is not set
-# CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_TPS65086 is not set
 # CONFIG_MFD_TPS65090 is not set
 # CONFIG_MFD_TPS65217 is not set
@@ -3760,8 +3451,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_TPS65912_SPI is not set
 # CONFIG_MFD_TPS6594_I2C is not set
 # CONFIG_MFD_TPS6594_SPI is not set
-# CONFIG_MFD_TPS68470 is not set
-# CONFIG_MFD_TPS80031 is not set
 # CONFIG_MFD_TQMX86 is not set
 # CONFIG_MFD_VIPERBOARD is not set
 # CONFIG_MFD_VX855 is not set
@@ -3772,7 +3461,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8994 is not set
-# CONFIG_MG_DISK is not set
 # CONFIG_MHI_BUS is not set
 # CONFIG_MHI_BUS_DEBUG is not set
 # CONFIG_MHI_BUS_EP is not set
@@ -3782,7 +3470,6 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MHI_WWAN_MBIM is not set
 # CONFIG_MICREL_KS8995MA is not set
 # CONFIG_MICREL_PHY is not set
-# CONFIG_MICROCHIP_KSZ is not set
 # CONFIG_MICROCHIP_PHY is not set
 # CONFIG_MICROCHIP_PIT64B is not set
 # CONFIG_MICROCHIP_T1S_PHY is not set
@@ -3801,20 +3488,16 @@ CONFIG_MII=y
 # CONFIG_MIPS_CDMM is not set
 # CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
 # CONFIG_MIPS_CMDLINE_FROM_DTB is not set
-# CONFIG_MIPS_CMP is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MIPS_CPS is not set
 # CONFIG_MIPS_ELF_APPENDED_DTB is not set
-# CONFIG_MIPS_FPU_EMULATOR is not set
 # CONFIG_MIPS_FP_SUPPORT is not set
 # CONFIG_MIPS_GENERIC is not set
 # CONFIG_MIPS_GENERIC_KERNEL is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_O32_FP64_SUPPORT is not set
-# CONFIG_MIPS_PARAVIRT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_MIPS_RAW_APPENDED_DTB is not set
-# CONFIG_MIPS_SEAD3 is not set
 # CONFIG_MIPS_VA_BITS_48 is not set
 # CONFIG_MIPS_VPE_LOADER is not set
 # CONFIG_MISC_ALCOR_PCI is not set
@@ -3834,7 +3517,6 @@ CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_MLX4_EN is not set
 # CONFIG_MLX5_CORE is not set
-# CONFIG_MLX5_EN_MACSEC is not set
 # CONFIG_MLX5_MACSEC is not set
 # CONFIG_MLX5_SF is not set
 # CONFIG_MLX5_VFIO_PCI is not set
@@ -3842,7 +3524,6 @@ CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
 # CONFIG_MLX90632 is not set
 # CONFIG_MLXFW is not set
 # CONFIG_MLXSW_CORE is not set
-# CONFIG_MLX_CPLD_PLATFORM is not set
 # CONFIG_MLX_PLATFORM is not set
 # CONFIG_MMA7455_I2C is not set
 # CONFIG_MMA7455_SPI is not set
@@ -3855,7 +3536,6 @@ CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
 # CONFIG_MMC_ARMMMCI is not set
 # CONFIG_MMC_AU1X is not set
 # CONFIG_MMC_BLOCK is not set
-CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_BLOCK_MINORS=8
 # CONFIG_MMC_CAVIUM_THUNDERX is not set
 # CONFIG_MMC_CB710 is not set
@@ -3866,7 +3546,6 @@ CONFIG_MMC_BLOCK_MINORS=8
 # CONFIG_MMC_JZ4740 is not set
 # CONFIG_MMC_MTK is not set
 # CONFIG_MMC_MVSDIO is not set
-# CONFIG_MMC_S3C is not set
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_SDHCI_ACPI is not set
 # CONFIG_MMC_SDHCI_AM654 is not set
@@ -3905,7 +3584,6 @@ CONFIG_MMU_GATHER_TABLE_FREE=y
 CONFIG_MODPROBE_PATH="/sbin/modprobe"
 CONFIG_MODULES=y
 # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-# CONFIG_MODULE_COMPRESS is not set
 # CONFIG_MODULE_COMPRESS_GZIP is not set
 CONFIG_MODULE_COMPRESS_NONE=y
 # CONFIG_MODULE_COMPRESS_XZ is not set
@@ -3981,15 +3659,12 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_DOCG3 is not set
 CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_GPIO_ADDR is not set
 # CONFIG_MTD_HYPERBUS is not set
 # CONFIG_MTD_IMPA7 is not set
 # CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_JEDECPROBE is not set
-# CONFIG_MTD_LATCH_ADDR is not set
 # CONFIG_MTD_LPDDR is not set
 # CONFIG_MTD_LPDDR2_NVM is not set
-# CONFIG_MTD_M25P80 is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
@@ -3998,18 +3673,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
 # CONFIG_MTD_MCHP23K256 is not set
 # CONFIG_MTD_MCHP48L640 is not set
-# CONFIG_MTD_MT81xx_NOR is not set
 # CONFIG_MTD_MTDRAM is not set
 # CONFIG_MTD_MYLOADER_PARTS is not set
-# CONFIG_MTD_NAND is not set
 # CONFIG_MTD_NAND_AMS_DELTA is not set
-# CONFIG_MTD_NAND_AR934X is not set
-# CONFIG_MTD_NAND_AR934X_HW_ECC is not set
 # CONFIG_MTD_NAND_ARASAN is not set
 # CONFIG_MTD_NAND_ATMEL is not set
 # CONFIG_MTD_NAND_AU1550 is not set
-# CONFIG_MTD_NAND_BCH is not set
-# CONFIG_MTD_NAND_BF5XX is not set
 # CONFIG_MTD_NAND_BRCMNAND is not set
 # CONFIG_MTD_NAND_BRCMNAND_BCM63XX is not set
 # CONFIG_MTD_NAND_BRCMNAND_BCMBCA is not set
@@ -4017,19 +3686,14 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_NAND_BRCMNAND_IPROC is not set
 # CONFIG_MTD_NAND_CADENCE is not set
 # CONFIG_MTD_NAND_CAFE is not set
-# CONFIG_MTD_NAND_CM_X270 is not set
 # CONFIG_MTD_NAND_CS553X is not set
 # CONFIG_MTD_NAND_DAVINCI is not set
 # CONFIG_MTD_NAND_DENALI is not set
 # CONFIG_MTD_NAND_DENALI_DT is not set
 # CONFIG_MTD_NAND_DENALI_PCI is not set
-CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_DOCG4 is not set
 # CONFIG_MTD_NAND_ECC is not set
-# CONFIG_MTD_NAND_ECC_BCH is not set
 # CONFIG_MTD_NAND_ECC_MXIC is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_ECC_SW_BCH is not set
 # CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
 # CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
@@ -4040,9 +3704,7 @@ CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018
 # CONFIG_MTD_NAND_GPIO is not set
 # CONFIG_MTD_NAND_GPMI_NAND is not set
 # CONFIG_MTD_NAND_HISI504 is not set
-CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_INTEL_LGM is not set
-# CONFIG_MTD_NAND_JZ4740 is not set
 # CONFIG_MTD_NAND_MPC5121_NFC is not set
 # CONFIG_MTD_NAND_MTK is not set
 # CONFIG_MTD_NAND_MTK_BMT is not set
@@ -4050,22 +3712,16 @@ CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_MXIC is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_NDFC is not set
-# CONFIG_MTD_NAND_NUC900 is not set
 # CONFIG_MTD_NAND_OMAP2 is not set
 # CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set
 # CONFIG_MTD_NAND_ORION is not set
 # CONFIG_MTD_NAND_PASEMI is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_NAND_PXA3xx is not set
-# CONFIG_MTD_NAND_RB4XX is not set
-# CONFIG_MTD_NAND_RB750 is not set
-# CONFIG_MTD_NAND_RB91X is not set
 # CONFIG_MTD_NAND_RICOH is not set
 # CONFIG_MTD_NAND_S3C2410 is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
 # CONFIG_MTD_NAND_SH_FLCTL is not set
 # CONFIG_MTD_NAND_SOCRATES is not set
-# CONFIG_MTD_NAND_TMIO is not set
 # CONFIG_MTD_NAND_TXX9NDFMC is not set
 CONFIG_MTD_OF_PARTS=y
 # CONFIG_MTD_ONENAND is not set
@@ -4082,8 +3738,6 @@ CONFIG_MTD_OF_PARTS=y
 # CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
 # CONFIG_MTD_PHYSMAP_IXP4XX is not set
 CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set
-# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set
 # CONFIG_MTD_PHYSMAP_VERSATILE is not set
 # CONFIG_MTD_PLATRAM is not set
 # CONFIG_MTD_PMC551 is not set
@@ -4099,7 +3753,6 @@ CONFIG_MTD_ROOTFS_ROOT_DEV=y
 # CONFIG_MTD_SERCOMM_PARTS is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_SM_COMMON is not set
-# CONFIG_MTD_SPINAND_MT29F is not set
 # CONFIG_MTD_SPI_NAND is not set
 # CONFIG_MTD_SPI_NOR is not set
 # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
@@ -4135,10 +3788,8 @@ CONFIG_MTD_SPLIT_SUPPORT=y
 # CONFIG_MTD_UBI_FASTMAP is not set
 # CONFIG_MTD_UBI_GLUEBI is not set
 # CONFIG_MTD_UBI_NVMEM is not set
-# CONFIG_MTD_UIMAGE_SPLIT is not set
 # CONFIG_MTD_VIRT_CONCAT is not set
 # CONFIG_MTK_DEVAPC is not set
-# CONFIG_MTK_MMC is not set
 # CONFIG_MTK_MMSYS is not set
 # CONFIG_MTK_T7XX is not set
 # CONFIG_MTK_THERMAL is not set
@@ -4152,7 +3803,6 @@ CONFIG_MULTIUSER=y
 # CONFIG_MV643XX_ETH is not set
 # CONFIG_MVMDIO is not set
 # CONFIG_MVNETA_BM is not set
-# CONFIG_MVSW61XX_PHY is not set
 # CONFIG_MV_XOR_V2 is not set
 # CONFIG_MWAVE is not set
 # CONFIG_MWL8K is not set
@@ -4165,10 +3815,8 @@ CONFIG_MULTIUSER=y
 # CONFIG_NAU7802 is not set
 # CONFIG_NBPFAXI_DMA is not set
 # CONFIG_NCN26000_PHY is not set
-# CONFIG_NCP_FS is not set
 # CONFIG_NE2000 is not set
 # CONFIG_NE2K_PCI is not set
-# CONFIG_NEC_MARKEINS is not set
 CONFIG_NET=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETCONSOLE_EXTENDED_LOG is not set
@@ -4176,7 +3824,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_NETDEVSIM is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_NETFILTER_ADVANCED is not set
-# CONFIG_NETFILTER_DEBUG is not set
 # CONFIG_NETFILTER_EGRESS is not set
 # CONFIG_NETFILTER_INGRESS is not set
 # CONFIG_NETFILTER_NETLINK is not set
@@ -4262,7 +3909,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_NETFS_STATS is not set
 # CONFIG_NETLABEL is not set
 # CONFIG_NETLINK_DIAG is not set
-# CONFIG_NETLINK_MMAP is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NETROM is not set
 CONFIG_NETWORK_FILESYSTEMS=y
@@ -4288,7 +3934,6 @@ CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NET_ACT_SKBMOD is not set
 # CONFIG_NET_ACT_TUNNEL_KEY is not set
 # CONFIG_NET_ACT_VLAN is not set
-CONFIG_NET_CADENCE=y
 # CONFIG_NET_CALXEDA_XGMAC is not set
 CONFIG_NET_CLS=y
 # CONFIG_NET_CLS_ACT is not set
@@ -4297,11 +3942,8 @@ CONFIG_NET_CLS=y
 # CONFIG_NET_CLS_FLOW is not set
 # CONFIG_NET_CLS_FLOWER is not set
 # CONFIG_NET_CLS_FW is not set
-CONFIG_NET_CLS_IND=y
 # CONFIG_NET_CLS_MATCHALL is not set
 # CONFIG_NET_CLS_ROUTE4 is not set
-# CONFIG_NET_CLS_RSVP is not set
-# CONFIG_NET_CLS_RSVP6 is not set
 # CONFIG_NET_CLS_U32 is not set
 CONFIG_NET_CORE=y
 # CONFIG_NET_DEVLINK is not set
@@ -4311,22 +3953,14 @@ CONFIG_NET_CORE=y
 # CONFIG_NET_DSA_AR9331 is not set
 # CONFIG_NET_DSA_BCM_SF2 is not set
 # CONFIG_NET_DSA_LANTIQ_GSWIP is not set
-# CONFIG_NET_DSA_LEGACY is not set
 # CONFIG_NET_DSA_LOOP is not set
-# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
-# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
 # CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set
 # CONFIG_NET_DSA_MSCC_FELIX is not set
 # CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
 # CONFIG_NET_DSA_MSCC_SEVILLE is not set
 # CONFIG_NET_DSA_MT7530 is not set
 # CONFIG_NET_DSA_MV88E6060 is not set
-# CONFIG_NET_DSA_MV88E6123_61_65 is not set
-# CONFIG_NET_DSA_MV88E6131 is not set
-# CONFIG_NET_DSA_MV88E6171 is not set
-# CONFIG_NET_DSA_MV88E6352 is not set
 # CONFIG_NET_DSA_MV88E6XXX is not set
-# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
 # CONFIG_NET_DSA_MV88E6XXX_PTP is not set
 # CONFIG_NET_DSA_QCA8K is not set
 # CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT is not set
@@ -4335,7 +3969,6 @@ CONFIG_NET_CORE=y
 # CONFIG_NET_DSA_SJA1105 is not set
 # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
 # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
-# CONFIG_NET_DSA_TAG_8021Q is not set
 # CONFIG_NET_DSA_TAG_AR9331 is not set
 # CONFIG_NET_DSA_TAG_BRCM is not set
 # CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set
@@ -4390,7 +4023,6 @@ CONFIG_NET_IPGRE_BROADCAST=y
 # CONFIG_NET_NCSI is not set
 # CONFIG_NET_NSH is not set
 # CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_NET_PACKET_ENGINE is not set
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_NET_PTP_CLASSIFY is not set
@@ -4428,11 +4060,9 @@ CONFIG_NET_SCH_FQ_CODEL=y
 # CONFIG_NET_SCH_TAPRIO is not set
 # CONFIG_NET_SCH_TBF is not set
 # CONFIG_NET_SCH_TEQL is not set
-# CONFIG_NET_SCTPPROBE is not set
 # CONFIG_NET_SELFTESTS is not set
 CONFIG_NET_SOCK_MSG=y
 # CONFIG_NET_SWITCHDEV is not set
-# CONFIG_NET_TCPPROBE is not set
 # CONFIG_NET_TC_SKB_EXT is not set
 # CONFIG_NET_TEAM is not set
 # CONFIG_NET_TULIP is not set
@@ -4450,7 +4080,6 @@ CONFIG_NET_VENDOR_AQUANTIA=y
 CONFIG_NET_VENDOR_ARC=y
 # CONFIG_NET_VENDOR_ASIX is not set
 CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_NET_VENDOR_AURORA=y
 CONFIG_NET_VENDOR_BROADCOM=y
 CONFIG_NET_VENDOR_BROCADE=y
 CONFIG_NET_VENDOR_CADENCE=y
@@ -4464,7 +4093,6 @@ CONFIG_NET_VENDOR_DEC=y
 CONFIG_NET_VENDOR_DLINK=y
 CONFIG_NET_VENDOR_EMULEX=y
 # CONFIG_NET_VENDOR_ENGLEDER is not set
-CONFIG_NET_VENDOR_EXAR=y
 CONFIG_NET_VENDOR_EZCHIP=y
 CONFIG_NET_VENDOR_FARADAY=y
 CONFIG_NET_VENDOR_FREESCALE=y
@@ -4472,7 +4100,6 @@ CONFIG_NET_VENDOR_FUJITSU=y
 # CONFIG_NET_VENDOR_FUNGIBLE is not set
 CONFIG_NET_VENDOR_GOOGLE=y
 CONFIG_NET_VENDOR_HISILICON=y
-CONFIG_NET_VENDOR_HP=y
 CONFIG_NET_VENDOR_HUAWEI=y
 CONFIG_NET_VENDOR_I825XX=y
 CONFIG_NET_VENDOR_IBM=y
@@ -4526,7 +4153,6 @@ CONFIG_NEW_LEDS=y
 # CONFIG_NFSD is not set
 # CONFIG_NFSD_V2 is not set
 # CONFIG_NFSD_V2_ACL is not set
-CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
 # CONFIG_NFS_ACL_SUPPORT is not set
@@ -4550,11 +4176,8 @@ CONFIG_NFS_V3=y
 # CONFIG_NFT_FIB_IPV6 is not set
 # CONFIG_NFT_FIB_NETDEV is not set
 # CONFIG_NFT_FLOW_OFFLOAD is not set
-# CONFIG_NFT_OBJREF is not set
 # CONFIG_NFT_OSF is not set
 # CONFIG_NFT_REJECT_NETDEV is not set
-# CONFIG_NFT_RT is not set
-# CONFIG_NFT_SET_BITMAP is not set
 # CONFIG_NFT_SOCKET is not set
 # CONFIG_NFT_SYNPROXY is not set
 # CONFIG_NFT_TPROXY is not set
@@ -4572,7 +4195,6 @@ CONFIG_NFS_V3=y
 # CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
 # CONFIG_NF_CONNTRACK_PPTP is not set
 CONFIG_NF_CONNTRACK_PROCFS=y
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 # CONFIG_NF_CONNTRACK_SANE is not set
 # CONFIG_NF_CONNTRACK_SECMARK is not set
 # CONFIG_NF_CONNTRACK_SIP is not set
@@ -4594,18 +4216,14 @@ CONFIG_NF_CONNTRACK_PROCFS=y
 # CONFIG_NF_FLOW_TABLE is not set
 # CONFIG_NF_FLOW_TABLE_PROCFS is not set
 # CONFIG_NF_LOG_ARP is not set
-# CONFIG_NF_LOG_BRIDGE is not set
 # CONFIG_NF_LOG_IPV4 is not set
-# CONFIG_NF_LOG_NETDEV is not set
 # CONFIG_NF_LOG_SYSLOG is not set
 # CONFIG_NF_NAT is not set
 # CONFIG_NF_NAT_AMANDA is not set
 # CONFIG_NF_NAT_FTP is not set
 # CONFIG_NF_NAT_H323 is not set
 # CONFIG_NF_NAT_IRC is not set
-# CONFIG_NF_NAT_NEEDED is not set
 # CONFIG_NF_NAT_PPTP is not set
-# CONFIG_NF_NAT_PROTO_GRE is not set
 # CONFIG_NF_NAT_SIP is not set
 # CONFIG_NF_NAT_SNMP_BASIC is not set
 # CONFIG_NF_NAT_TFTP is not set
@@ -4620,11 +4238,9 @@ CONFIG_NF_TABLES_INET=y
 CONFIG_NF_TABLES_IPV4=y
 CONFIG_NF_TABLES_IPV6=y
 CONFIG_NF_TABLES_NETDEV=y
-# CONFIG_NF_TABLES_SET is not set
 # CONFIG_NF_TPROXY_IPV4 is not set
 # CONFIG_NF_TPROXY_IPV6 is not set
 # CONFIG_NGBE is not set
-# CONFIG_NI65 is not set
 # CONFIG_NI903X_WDT is not set
 # CONFIG_NIC7018_WDT is not set
 # CONFIG_NILFS2_FS is not set
@@ -4632,8 +4248,6 @@ CONFIG_NF_TABLES_NETDEV=y
 # CONFIG_NI_XGE_MANAGEMENT_ENET is not set
 CONFIG_NLATTR=y
 # CONFIG_NLMON is not set
-# CONFIG_NLM_XLP_BOARD is not set
-# CONFIG_NLM_XLR_BOARD is not set
 # CONFIG_NLS is not set
 # CONFIG_NLS_ASCII is not set
 # CONFIG_NLS_CODEPAGE_1250 is not set
@@ -4686,14 +4300,11 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_MAC_TURKISH is not set
 # CONFIG_NLS_UCS2_UTILS is not set
 # CONFIG_NLS_UTF8 is not set
-CONFIG_NMI_LOG_BUF_SHIFT=13
 # CONFIG_NOA1305 is not set
 # CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_NORTEL_HERMES is not set
 # CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
 # CONFIG_NOZOMI is not set
-# CONFIG_NO_BOOTMEM is not set
 # CONFIG_NO_HZ is not set
 # CONFIG_NO_HZ_FULL is not set
 # CONFIG_NO_HZ_IDLE is not set
@@ -4710,7 +4321,6 @@ CONFIG_NMI_LOG_BUF_SHIFT=13
 # CONFIG_NULL_TTY is not set
 # CONFIG_NUMA is not set
 # CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
-# CONFIG_NVM is not set
 # CONFIG_NVMEM is not set
 # CONFIG_NVMEM_BCM_OCOTP is not set
 # CONFIG_NVMEM_IMX_OCOTP is not set
@@ -4729,8 +4339,6 @@ CONFIG_NMI_LOG_BUF_SHIFT=13
 # CONFIG_NV_TCO is not set
 # CONFIG_NXP_C45_TJA11XX_PHY is not set
 # CONFIG_NXP_CBTX_PHY is not set
-# CONFIG_NXP_STB220 is not set
-# CONFIG_NXP_STB225 is not set
 # CONFIG_NXP_TJA11XX_PHY is not set
 # CONFIG_N_GSM is not set
 # CONFIG_OABI_COMPAT is not set
@@ -4751,11 +4359,8 @@ CONFIG_OF_RESERVED_MEM=y
 # CONFIG_OMFS_FS is not set
 # CONFIG_OPENVSWITCH is not set
 # CONFIG_OPEN_DICE is not set
-# CONFIG_OPROFILE is not set
-# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set
 # CONFIG_OPT3001 is not set
 # CONFIG_OPT4001 is not set
-CONFIG_OPTIMIZE_INLINING=y
 # CONFIG_ORANGEFS_FS is not set
 # CONFIG_ORION_WATCHDOG is not set
 # CONFIG_OSF_PARTITION is not set
@@ -4767,7 +4372,6 @@ CONFIG_OVERLAY_FS=y
 CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
 # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
 CONFIG_OVERLAY_FS_XINO_AUTO=y
-# CONFIG_OWL_LOADER is not set
 # CONFIG_P54_COMMON is not set
 # CONFIG_PA12203001 is not set
 CONFIG_PACKET=y
@@ -4796,7 +4400,6 @@ CONFIG_PANIC_TIMEOUT=1
 # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
 # CONFIG_PARPORT is not set
 # CONFIG_PARPORT_1284 is not set
-# CONFIG_PARPORT_AX88796 is not set
 # CONFIG_PARPORT_GSC is not set
 # CONFIG_PARPORT_PC is not set
 CONFIG_PARTITION_ADVANCED=y
@@ -4875,7 +4478,6 @@ CONFIG_PCIE_BUS_DEFAULT=y
 # CONFIG_PCIE_BUS_PERFORMANCE is not set
 # CONFIG_PCIE_BUS_SAFE is not set
 # CONFIG_PCIE_BUS_TUNE_OFF is not set
-# CONFIG_PCIE_BW is not set
 # CONFIG_PCIE_CADENCE_HOST is not set
 # CONFIG_PCIE_CADENCE_PLAT_HOST is not set
 # CONFIG_PCIE_DPC is not set
@@ -4946,7 +4548,6 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCS_MTK_USXGMII is not set
 # CONFIG_PCS_XPCS is not set
 # CONFIG_PD6729 is not set
-# CONFIG_PDA_POWER is not set
 # CONFIG_PDC_ADMA is not set
 # CONFIG_PDS_CORE is not set
 # CONFIG_PECI is not set
@@ -4962,7 +4563,6 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHYLIB_LEDS is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 # CONFIG_PHY_BRCM_USB is not set
-# CONFIG_PHY_CADENCE_DP is not set
 # CONFIG_PHY_CADENCE_DPHY is not set
 # CONFIG_PHY_CADENCE_DPHY_RX is not set
 # CONFIG_PHY_CADENCE_SALVO is not set
@@ -4986,7 +4586,6 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHY_PISTACHIO_USB is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
-# CONFIG_PHY_QCOM_DWC3 is not set
 # CONFIG_PHY_QCOM_USB_HS is not set
 # CONFIG_PHY_QCOM_USB_HSIC is not set
 # CONFIG_PHY_SAMSUNG_USB2 is not set
@@ -4999,11 +4598,9 @@ CONFIG_PINCONF=y
 # CONFIG_PINCTRL is not set
 # CONFIG_PINCTRL_AMD is not set
 # CONFIG_PINCTRL_AXP209 is not set
-# CONFIG_PINCTRL_BCM2712 is not set
 # CONFIG_PINCTRL_CEDARFORK is not set
 # CONFIG_PINCTRL_CY8C95X0 is not set
 # CONFIG_PINCTRL_EXYNOS is not set
-# CONFIG_PINCTRL_EXYNOS5440 is not set
 # CONFIG_PINCTRL_ICELAKE is not set
 # CONFIG_PINCTRL_INGENIC is not set
 # CONFIG_PINCTRL_LPASS_LPI is not set
@@ -5020,7 +4617,6 @@ CONFIG_PINCONF=y
 # CONFIG_PINCTRL_MTK_V2 is not set
 # CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_PISTACHIO is not set
-# CONFIG_PINCTRL_RP1 is not set
 # CONFIG_PINCTRL_SC7280 is not set
 # CONFIG_PINCTRL_SC8180X is not set
 # CONFIG_PINCTRL_SDX55 is not set
@@ -5046,7 +4642,6 @@ CONFIG_PINMUX=y
 # CONFIG_PLX_HERMES is not set
 # CONFIG_PM is not set
 # CONFIG_PMBUS is not set
-# CONFIG_PMC_MSP is not set
 # CONFIG_PMIC_ADP5520 is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMS7003 is not set
@@ -5058,7 +4653,6 @@ CONFIG_PINMUX=y
 # CONFIG_POSIX_MQUEUE is not set
 CONFIG_POSIX_TIMERS=y
 # CONFIG_POWERCAP is not set
-# CONFIG_POWER_AVS is not set
 # CONFIG_POWER_RESET is not set
 # CONFIG_POWER_RESET_BRCMKONA is not set
 # CONFIG_POWER_RESET_BRCMSTB is not set
@@ -5110,7 +4704,6 @@ CONFIG_PPP_MULTILINK=y
 # CONFIG_PPTP is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_PREEMPTIRQ_DELAY_TEST is not set
-# CONFIG_PREEMPTIRQ_EVENTS is not set
 # CONFIG_PREEMPT_DYNAMIC is not set
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_TRACER is not set
@@ -5121,12 +4714,9 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_PRINTK=y
 # CONFIG_PRINTK_CALLER is not set
 # CONFIG_PRINTK_INDEX is not set
-CONFIG_PRINTK_NMI=y
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
 # CONFIG_PRINTK_TIME is not set
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_PRISM2_USB is not set
-# CONFIG_PRISM54 is not set
 # CONFIG_PROC_CHILDREN is not set
 CONFIG_PROC_FS=y
 # CONFIG_PROC_KCORE is not set
@@ -5141,26 +4731,18 @@ CONFIG_PROC_SYSCTL=y
 # CONFIG_PROVE_RAW_LOCK_NESTING is not set
 # CONFIG_PROVE_RCU is not set
 # CONFIG_PROVE_RCU_LIST is not set
-# CONFIG_PROVE_RCU_REPEATEDLY is not set
 # CONFIG_PSAMPLE is not set
 # CONFIG_PSB6970_PHY is not set
 # CONFIG_PSE_CONTROLLER is not set
 # CONFIG_PSI is not set
 # CONFIG_PSTORE is not set
-# CONFIG_PSTORE_842_COMPRESS is not set
 # CONFIG_PSTORE_BLK is not set
 # CONFIG_PSTORE_COMPRESS is not set
 # CONFIG_PSTORE_CONSOLE is not set
 CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-# CONFIG_PSTORE_DEFLATE_COMPRESS is not set
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
 # CONFIG_PSTORE_FTRACE is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
-# CONFIG_PSTORE_LZ4_COMPRESS is not set
-# CONFIG_PSTORE_LZO_COMPRESS is not set
 # CONFIG_PSTORE_PMSG is not set
 # CONFIG_PSTORE_RAM is not set
-# CONFIG_PSTORE_ZSTD_COMPRESS is not set
 # CONFIG_PTDUMP_DEBUGFS is not set
 # CONFIG_PTP_1588_CLOCK is not set
 # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
@@ -5171,7 +4753,6 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
 # CONFIG_PTP_1588_CLOCK_OCP is not set
 # CONFIG_PTP_1588_CLOCK_PCH is not set
 # CONFIG_PTP_1588_CLOCK_VMW is not set
-# CONFIG_PUBLIC_KEY_ALGO_RSA is not set
 # CONFIG_PVPANIC is not set
 # CONFIG_PWM is not set
 # CONFIG_PWM_ATMEL_TCB is not set
@@ -5184,7 +4765,6 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
 # CONFIG_PWM_MEDIATEK is not set
 # CONFIG_PWM_PCA9685 is not set
 # CONFIG_PWM_RASPBERRYPI_POE is not set
-# CONFIG_PWM_RP1 is not set
 # CONFIG_PWM_XILINX is not set
 CONFIG_PWRSEQ_EMMC=y
 # CONFIG_PWRSEQ_SD8787 is not set
@@ -5225,18 +4805,14 @@ CONFIG_PWRSEQ_SIMPLE=y
 # CONFIG_QRTR_MHI is not set
 # CONFIG_QRTR_TUN is not set
 # CONFIG_QSEMI_PHY is not set
-# CONFIG_QUEUED_LOCK_STAT is not set
 # CONFIG_QUICC_ENGINE is not set
 # CONFIG_QUOTA is not set
 # CONFIG_QUOTACTL is not set
 # CONFIG_QUOTA_DEBUG is not set
 # CONFIG_QUOTA_NETLINK_INTERFACE is not set
-# CONFIG_R3964 is not set
 # CONFIG_R6040 is not set
 # CONFIG_R8169 is not set
-# CONFIG_R8188EU is not set
 # CONFIG_R8712U is not set
-# CONFIG_R8723AU is not set
 # CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_RADIO_AZTECH is not set
 # CONFIG_RADIO_CADET is not set
@@ -5258,29 +4834,22 @@ CONFIG_PWRSEQ_SIMPLE=y
 CONFIG_RANDOMIZE_KSTACK_OFFSET=y
 # CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
 # CONFIG_RANDOM_KMALLOC_CACHES is not set
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-CONFIG_RANDOM_TRUST_CPU=y
 # CONFIG_RANDSTRUCT_NONE is not set
 # CONFIG_RAPIDIO is not set
 # CONFIG_RAS is not set
-# CONFIG_RASPBERRYPI_GPIOMEM is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_RCU_BOOST is not set
 # CONFIG_RCU_CPU_STALL_CPUTIME is not set
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
 # CONFIG_RCU_EQS_DEBUG is not set
-# CONFIG_RCU_EXPEDITE_BOOT is not set
 # CONFIG_RCU_EXPERT is not set
 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
-CONFIG_RCU_KTHREAD_PRIO=0
 CONFIG_RCU_NEED_SEGCBLIST=y
-# CONFIG_RCU_PERF_TEST is not set
 # CONFIG_RCU_REF_SCALE_TEST is not set
 # CONFIG_RCU_SCALE_TEST is not set
 CONFIG_RCU_STALL_COMMON=y
 # CONFIG_RCU_STRICT_GRACE_PERIOD is not set
 # CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3
 # CONFIG_RCU_TRACE is not set
 # CONFIG_RC_ATI_REMOTE is not set
 # CONFIG_RC_CORE is not set
@@ -5410,7 +4979,6 @@ CONFIG_REISERFS_FS_XATTR=y
 # CONFIG_RESET_PISTACHIO is not set
 # CONFIG_RESET_SIMPLE is not set
 # CONFIG_RESET_SOCFPGA is not set
-# CONFIG_RESET_STM32 is not set
 # CONFIG_RESET_SUNXI is not set
 # CONFIG_RESET_TEGRA_BPMP is not set
 # CONFIG_RESET_TI_SYSCON is not set
@@ -5423,7 +4991,6 @@ CONFIG_RFKILL=y
 # CONFIG_RFKILL_GPIO is not set
 # CONFIG_RFKILL_INPUT is not set
 # CONFIG_RFKILL_LEDS is not set
-# CONFIG_RFKILL_REGULATOR is not set
 # CONFIG_RICHTEK_RTQ6056 is not set
 # CONFIG_RING_BUFFER_BENCHMARK is not set
 # CONFIG_RING_BUFFER_STARTUP_TEST is not set
@@ -5466,7 +5033,6 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
 # CONFIG_RTC_DRV_DS1307_CENTURY is not set
-# CONFIG_RTC_DRV_DS1307_HWMON is not set
 # CONFIG_RTC_DRV_DS1343 is not set
 # CONFIG_RTC_DRV_DS1347 is not set
 # CONFIG_RTC_DRV_DS1374 is not set
@@ -5478,7 +5044,6 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_DS2404 is not set
 # CONFIG_RTC_DRV_DS3232 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
 # CONFIG_RTC_DRV_EM3027 is not set
 # CONFIG_RTC_DRV_EP93XX is not set
 # CONFIG_RTC_DRV_FM3130 is not set
@@ -5489,7 +5054,6 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_HYM8563 is not set
 # CONFIG_RTC_DRV_ISL12022 is not set
 # CONFIG_RTC_DRV_ISL12026 is not set
-# CONFIG_RTC_DRV_ISL12057 is not set
 # CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_JZ4740 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
@@ -5519,13 +5083,11 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_PL030 is not set
 # CONFIG_RTC_DRV_PL031 is not set
 # CONFIG_RTC_DRV_PS3 is not set
-# CONFIG_RTC_DRV_PT7C4338 is not set
 # CONFIG_RTC_DRV_R7301 is not set
 # CONFIG_RTC_DRV_R9701 is not set
 # CONFIG_RTC_DRV_RP5C01 is not set
 # CONFIG_RTC_DRV_RS5C348 is not set
 # CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_RTC7301 is not set
 # CONFIG_RTC_DRV_RV3028 is not set
 # CONFIG_RTC_DRV_RV3029C2 is not set
 # CONFIG_RTC_DRV_RV3032 is not set
@@ -5542,7 +5104,6 @@ CONFIG_RTC_DRV_CMOS=y
 # CONFIG_RTC_DRV_SUN6I is not set
 # CONFIG_RTC_DRV_TEGRA is not set
 # CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_V3020 is not set
 # CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_XGENE is not set
 # CONFIG_RTC_DRV_ZYNQMP is not set
@@ -5571,10 +5132,8 @@ CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
 # CONFIG_RTL_CARDS is not set
 # CONFIG_RTS5208 is not set
 CONFIG_RT_MUTEXES=y
-# CONFIG_RUNTIME_DEBUG is not set
 CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_RV is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_RXKAD=y
 # CONFIG_RXPERF is not set
 # CONFIG_S2IO is not set
@@ -5624,11 +5183,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
 # CONFIG_SCHED_SMT is not set
 CONFIG_SCHED_STACK_END_CHECK=y
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_SCR24X is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_3W_9XXX is not set
 # CONFIG_SCSI_3W_SAS is not set
-# CONFIG_SCSI_7000FASST is not set
 # CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_ACARD is not set
 # CONFIG_SCSI_ADVANSYS is not set
@@ -5652,20 +5209,13 @@ CONFIG_SCHED_STACK_END_CHECK=y
 # CONFIG_SCSI_DH is not set
 CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_DTC3280 is not set
-# CONFIG_SCSI_EATA is not set
 # CONFIG_SCSI_ESAS2R is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_FDOMAIN_PCI is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GDTH is not set
 # CONFIG_SCSI_GENERIC_NCR5380 is not set
-# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
 # CONFIG_SCSI_HISI_SAS is not set
 # CONFIG_SCSI_HPSA is not set
 # CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_IN2000 is not set
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_IPR is not set
@@ -5680,17 +5230,13 @@ CONFIG_SCSI_MOD=y
 # CONFIG_SCSI_MPI3MR is not set
 # CONFIG_SCSI_MPT2SAS is not set
 # CONFIG_SCSI_MPT3SAS is not set
-# CONFIG_SCSI_MQ_DEFAULT is not set
 # CONFIG_SCSI_MVSAS is not set
 # CONFIG_SCSI_MVSAS_DEBUG is not set
 # CONFIG_SCSI_MVUMI is not set
 # CONFIG_SCSI_MYRB is not set
 # CONFIG_SCSI_MYRS is not set
-# CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_SCSI_NSP32 is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PM8001 is not set
 # CONFIG_SCSI_PMCRAID is not set
 CONFIG_SCSI_PROC_FS=y
@@ -5706,12 +5252,8 @@ CONFIG_SCSI_PROC_FS=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
 # CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_T128 is not set
-# CONFIG_SCSI_U14_34F is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_ULTRASTOR is not set
 # CONFIG_SCSI_VIRTIO is not set
 # CONFIG_SCSI_WD719X is not set
 # CONFIG_SC_CAMCC_7180 is not set
@@ -5745,10 +5287,8 @@ CONFIG_SECURITY_DMESG_RESTRICT=y
 # CONFIG_SECURITY_SAFESETID is not set
 # CONFIG_SECURITY_SELINUX_AVC_STATS is not set
 # CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
-CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
 # CONFIG_SECURITY_SELINUX_DEBUG is not set
 # CONFIG_SECURITY_SELINUX_DEVELOP is not set
-# CONFIG_SECURITY_SELINUX_DISABLE is not set
 # CONFIG_SECURITY_SMACK is not set
 # CONFIG_SECURITY_TOMOYO is not set
 # CONFIG_SECURITY_YAMA is not set
@@ -5774,7 +5314,6 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_ADM1266 is not set
 # CONFIG_SENSORS_ADM1275 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADS1015 is not set
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_ADS7871 is not set
 # CONFIG_SENSORS_ADT7310 is not set
@@ -5797,7 +5336,6 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_AXI_FAN_CONTROL is not set
 # CONFIG_SENSORS_BEL_PFE is not set
 # CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_BH1780 is not set
 # CONFIG_SENSORS_BPA_RS600 is not set
 # CONFIG_SENSORS_CORETEMP is not set
 # CONFIG_SENSORS_CORSAIR_CPRO is not set
@@ -5832,7 +5370,6 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_HMC5843_I2C is not set
 # CONFIG_SENSORS_HMC5843_SPI is not set
 # CONFIG_SENSORS_HS3001 is not set
-# CONFIG_SENSORS_HTU21 is not set
 # CONFIG_SENSORS_I5500 is not set
 # CONFIG_SENSORS_I5K_AMB is not set
 # CONFIG_SENSORS_IBM_CFFPS is not set
@@ -5944,7 +5481,6 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_Q54SJ108A2 is not set
 # CONFIG_SENSORS_RM3100_I2C is not set
 # CONFIG_SENSORS_RM3100_SPI is not set
-# CONFIG_SENSORS_RP1_ADC is not set
 # CONFIG_SENSORS_SBRMI is not set
 # CONFIG_SENSORS_SBTSI is not set
 # CONFIG_SENSORS_SCH5627 is not set
@@ -5956,7 +5492,6 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_SHT4x is not set
 # CONFIG_SENSORS_SHTC1 is not set
 # CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMM665 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_SMSC47M192 is not set
@@ -6022,7 +5557,6 @@ CONFIG_SERIAL_8250_DMA=y
 # CONFIG_SERIAL_8250_LPSS is not set
 # CONFIG_SERIAL_8250_MANY_PORTS is not set
 # CONFIG_SERIAL_8250_MID is not set
-# CONFIG_SERIAL_8250_MOXA is not set
 CONFIG_SERIAL_8250_NR_UARTS=2
 # CONFIG_SERIAL_8250_PCI is not set
 # CONFIG_SERIAL_8250_PCI1XXXX is not set
@@ -6045,13 +5579,11 @@ CONFIG_SERIAL_EARLYCON=y
 # CONFIG_SERIAL_FSL_LINFLEXUART is not set
 # CONFIG_SERIAL_FSL_LPUART is not set
 # CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
-# CONFIG_SERIAL_IFX6X60 is not set
 # CONFIG_SERIAL_JSM is not set
 # CONFIG_SERIAL_MAX3100 is not set
 # CONFIG_SERIAL_MAX310X is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_SERIAL_OF_PLATFORM is not set
-# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
 # CONFIG_SERIAL_PCH_UART is not set
 # CONFIG_SERIAL_RP2 is not set
 # CONFIG_SERIAL_SC16IS7XX is not set
@@ -6082,11 +5614,9 @@ CONFIG_SERIAL_EARLYCON=y
 # CONFIG_SFC is not set
 # CONFIG_SFC_FALCON is not set
 # CONFIG_SFC_SIENA is not set
-# CONFIG_SFI is not set
 # CONFIG_SFP is not set
 # CONFIG_SF_PDMA is not set
 # CONFIG_SGETMASK_SYSCALL is not set
-# CONFIG_SGI_IOC4 is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
 # CONFIG_SGI_IP28 is not set
@@ -6109,8 +5639,6 @@ CONFIG_SHMEM=y
 # CONFIG_SI7005 is not set
 # CONFIG_SI7020 is not set
 # CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
 # CONFIG_SIBYTE_CRHONE is not set
 # CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_RHONE is not set
@@ -6118,15 +5646,12 @@ CONFIG_SHMEM=y
 # CONFIG_SIBYTE_SWARM is not set
 CONFIG_SIGNALFD=y
 # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
-# CONFIG_SIMPLE_GPIO is not set
-# CONFIG_SIMPLE_PM_BUS is not set
 # CONFIG_SIOX is not set
 # CONFIG_SIS190 is not set
 # CONFIG_SIS900 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
 # CONFIG_SKY2_DEBUG is not set
-CONFIG_SLABINFO=y
 # CONFIG_SLAB_DEPRECATED is not set
 CONFIG_SLAB_FREELIST_HARDENED=y
 CONFIG_SLAB_FREELIST_RANDOM=y
@@ -6135,17 +5660,14 @@ CONFIG_SLAB_MERGE_DEFAULT=y
 # CONFIG_SLICOSS is not set
 # CONFIG_SLIMBUS is not set
 # CONFIG_SLIP is not set
-# CONFIG_SLOB is not set
 CONFIG_SLUB=y
 CONFIG_SLUB_CPU_PARTIAL=y
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
 # CONFIG_SLUB_STATS is not set
 # CONFIG_SLUB_TINY is not set
 # CONFIG_SMARTJOYPLUS_FF is not set
 # CONFIG_SMB_SERVER is not set
-# CONFIG_SMC911X is not set
 # CONFIG_SMC9194 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_SMP is not set
@@ -6184,7 +5706,6 @@ CONFIG_SLUB_CPU_PARTIAL=y
 # CONFIG_SND_AU8830 is not set
 # CONFIG_SND_AUDIO_GRAPH_CARD is not set
 # CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
-# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set
 # CONFIG_SND_AW2 is not set
 # CONFIG_SND_AZT2320 is not set
 # CONFIG_SND_AZT3328 is not set
@@ -6212,7 +5733,6 @@ CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_EDMA_SOC is not set
 # CONFIG_SND_EMU10K1 is not set
 # CONFIG_SND_EMU10K1X is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
@@ -6231,7 +5751,6 @@ CONFIG_SND_DRIVERS=y
 # CONFIG_SND_GUSMAX is not set
 # CONFIG_SND_HDA_CODEC_CS8409 is not set
 # CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDA_INTEL_DETECT_DMIC is not set
 # CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
 CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
 CONFIG_SND_HDA_PREALLOC_SIZE=64
@@ -6296,12 +5815,10 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
 # CONFIG_SND_PPC is not set
 CONFIG_SND_PROC_FS=y
 # CONFIG_SND_RAWMIDI is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
 # CONFIG_SND_RIPTIDE is not set
 # CONFIG_SND_RME32 is not set
 # CONFIG_SND_RME96 is not set
 # CONFIG_SND_RME9652 is not set
-# CONFIG_SND_RTCTIMER is not set
 # CONFIG_SND_SB16 is not set
 # CONFIG_SND_SB8 is not set
 # CONFIG_SND_SBAWE is not set
@@ -6312,7 +5829,6 @@ CONFIG_SND_PROC_FS=y
 # CONFIG_SND_SERIAL_GENERIC is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_SIMPLE_CARD is not set
-# CONFIG_SND_SIMPLE_SCU_CARD is not set
 # CONFIG_SND_SIS7019 is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SND_SOC_AC97_CODEC is not set
@@ -6381,7 +5897,6 @@ CONFIG_SND_PROC_FS=y
 # CONFIG_SND_SOC_CS53L30 is not set
 # CONFIG_SND_SOC_CX2072X is not set
 # CONFIG_SND_SOC_DA7213 is not set
-# CONFIG_SND_SOC_DIO2125 is not set
 # CONFIG_SND_SOC_DMIC is not set
 # CONFIG_SND_SOC_ES7134 is not set
 # CONFIG_SND_SOC_ES7241 is not set
@@ -6414,10 +5929,8 @@ CONFIG_SND_PROC_FS=y
 # CONFIG_SND_SOC_IMX_HDMI is not set
 # CONFIG_SND_SOC_IMX_RPMSG is not set
 # CONFIG_SND_SOC_IMX_SPDIF is not set
-# CONFIG_SND_SOC_IMX_WM8962 is not set
 # CONFIG_SND_SOC_INNO_RK3036 is not set
 # CONFIG_SND_SOC_INTEL_APL is not set
-# CONFIG_SND_SOC_INTEL_BAYTRAIL is not set
 # CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set
 # CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set
 # CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set
@@ -6426,8 +5939,6 @@ CONFIG_SND_PROC_FS=y
 # CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set
 # CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set
 # CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set
-# CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH is not set
-# CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH is not set
 # CONFIG_SND_SOC_INTEL_CATPT is not set
 # CONFIG_SND_SOC_INTEL_CFL is not set
 # CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set
@@ -6460,7 +5971,6 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
 # CONFIG_SND_SOC_LPASS_TX_MACRO is not set
 # CONFIG_SND_SOC_LPASS_VA_MACRO is not set
 # CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
-# CONFIG_SND_SOC_MA120X0P is not set
 # CONFIG_SND_SOC_MAX9759 is not set
 # CONFIG_SND_SOC_MAX98088 is not set
 # CONFIG_SND_SOC_MAX98090 is not set
@@ -6502,7 +6012,6 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
 # CONFIG_SND_SOC_NAU8824 is not set
 # CONFIG_SND_SOC_PCM1681 is not set
 # CONFIG_SND_SOC_PCM1789_I2C is not set
-# CONFIG_SND_SOC_PCM1792A is not set
 # CONFIG_SND_SOC_PCM179X_I2C is not set
 # CONFIG_SND_SOC_PCM179X_SPI is not set
 # CONFIG_SND_SOC_PCM186X_I2C is not set
@@ -6528,7 +6037,6 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
 # CONFIG_SND_SOC_SGTL5000 is not set
 # CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
 # CONFIG_SND_SOC_SIMPLE_MUX is not set
-# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
 # CONFIG_SND_SOC_SMA1303 is not set
 # CONFIG_SND_SOC_SOF_TOPLEVEL is not set
 # CONFIG_SND_SOC_SPDIF is not set
@@ -6603,7 +6111,6 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
 # CONFIG_SND_SOC_XILINX_SPDIF is not set
 # CONFIG_SND_SOC_XTFPGA_I2S is not set
 # CONFIG_SND_SOC_ZL38060 is not set
-# CONFIG_SND_SOC_ZX_AUD96P22 is not set
 # CONFIG_SND_SONICVIBES is not set
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_SSCAPE is not set
@@ -6645,7 +6152,6 @@ CONFIG_SND_X86=y
 # CONFIG_SOC_AM33XX is not set
 # CONFIG_SOC_AM43XX is not set
 # CONFIG_SOC_BRCMSTB is not set
-# CONFIG_SOC_CAMERA is not set
 # CONFIG_SOC_DRA7XX is not set
 # CONFIG_SOC_HAS_OMAP2_SDRC is not set
 # CONFIG_SOC_OMAP5 is not set
@@ -6659,13 +6165,11 @@ CONFIG_SND_X86=y
 # CONFIG_SOUNDWIRE is not set
 # CONFIG_SOUND_OSS_CORE is not set
 # CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
-# CONFIG_SOUND_PRIME is not set
 # CONFIG_SP5100_TCO is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_STATIC is not set
 # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 # CONFIG_SPARSE_IRQ is not set
-# CONFIG_SPARSE_RCU_POINTER is not set
 # CONFIG_SPEAKUP is not set
 # CONFIG_SPI is not set
 # CONFIG_SPINLOCK_TEST is not set
@@ -6677,6 +6181,7 @@ CONFIG_SND_X86=y
 # CONFIG_SPI_BCM2835 is not set
 # CONFIG_SPI_BCM63XX_HSSPI is not set
 # CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BCMBCA_HSSPI is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_SPI_BUTTERFLY is not set
 # CONFIG_SPI_CADENCE is not set
@@ -6688,7 +6193,6 @@ CONFIG_SND_X86=y
 # CONFIG_SPI_FSL_ESPI is not set
 # CONFIG_SPI_FSL_SPI is not set
 # CONFIG_SPI_GPIO is not set
-# CONFIG_SPI_GPIO_OLD is not set
 # CONFIG_SPI_IMG_SPFI is not set
 # CONFIG_SPI_LANTIQ_SSC is not set
 # CONFIG_SPI_LM70_LLP is not set
@@ -6699,7 +6203,6 @@ CONFIG_SND_X86=y
 # CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
 # CONFIG_SPI_MPC52xx is not set
 # CONFIG_SPI_MPC52xx_PSC is not set
-# CONFIG_SPI_MTK_QUADSPI is not set
 # CONFIG_SPI_MUX is not set
 # CONFIG_SPI_MXIC is not set
 # CONFIG_SPI_NXP_FLEXSPI is not set
@@ -6725,7 +6228,6 @@ CONFIG_SND_X86=y
 # CONFIG_SPI_TOPCLIFF_PCH is not set
 # CONFIG_SPI_XCOMM is not set
 # CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_XWAY is not set
 # CONFIG_SPI_ZYNQMP_GQSPI is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_SPMI is not set
@@ -6752,13 +6254,11 @@ CONFIG_SQUASHFS_XZ=y
 # CONFIG_SRF04 is not set
 # CONFIG_SRF08 is not set
 # CONFIG_SSB is not set
-# CONFIG_SSB_DEBUG is not set
 # CONFIG_SSB_DRIVER_GPIO is not set
 # CONFIG_SSB_HOST_SOC is not set
 # CONFIG_SSB_PCMCIAHOST is not set
 CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB_SDIOHOST is not set
-# CONFIG_SSB_SILENT is not set
 # CONFIG_SSFDC is not set
 # CONFIG_SSIF_IPMI_BMC is not set
 # CONFIG_STACKPROTECTOR is not set
@@ -6767,19 +6267,15 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_STACKTRACE is not set
 # CONFIG_STACKTRACE_BUILD_ID is not set
 CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_STACK_HASH_ORDER=20
 # CONFIG_STACK_TRACER is not set
 # CONFIG_STACK_VALIDATION is not set
 CONFIG_STAGING=y
 # CONFIG_STAGING_BOARD is not set
-# CONFIG_STAGING_GASKET_FRAMEWORK is not set
 # CONFIG_STAGING_MEDIA is not set
 CONFIG_STANDALONE=y
 # CONFIG_STATIC_KEYS_SELFTEST is not set
 # CONFIG_STATIC_USERMODEHELPER is not set
-CONFIG_STDBINUTILS=y
 # CONFIG_STE10XP is not set
-# CONFIG_STE_MODEM_RPROC is not set
 # CONFIG_STK3310 is not set
 # CONFIG_STK8312 is not set
 # CONFIG_STK8BA50 is not set
@@ -6807,18 +6303,15 @@ CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_SUNGEM is not set
 # CONFIG_SUNRPC is not set
 # CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y
 # CONFIG_SUNRPC_GSS is not set
 # CONFIG_SUNXI_SRAM is not set
 # CONFIG_SUN_PARTITION is not set
-# CONFIG_SURFACE_3_BUTTON is not set
 # CONFIG_SURFACE_PLATFORMS is not set
 # CONFIG_SUSPEND is not set
 # CONFIG_SUSPEND_SKIP_SYNC is not set
 CONFIG_SWAP=y
 # CONFIG_SWCONFIG is not set
 # CONFIG_SWCONFIG_B53 is not set
-# CONFIG_SWCONFIG_B53_MDIO_DRIVER is not set
 # CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
 # CONFIG_SWCONFIG_B53_SPI_DRIVER is not set
 # CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
@@ -6832,18 +6325,13 @@ CONFIG_SWAP=y
 # CONFIG_SX9500 is not set
 # CONFIG_SXGBE_ETH is not set
 CONFIG_SYMBOLIC_ERRNAME=y
-# CONFIG_SYNCLINK_CS is not set
 # CONFIG_SYNC_FILE is not set
-# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set
 # CONFIG_SYNTH_EVENTS is not set
 # CONFIG_SYNTH_EVENT_GEN_TEST is not set
 CONFIG_SYN_COOKIES=y
 # CONFIG_SYSCON_REBOOT_MODE is not set
 CONFIG_SYSCTL=y
-# CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SYSFS=y
-# CONFIG_SYSFS_DEPRECATED is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_SYSFS_SYSCALL is not set
 # CONFIG_SYSTEMPORT is not set
 # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
@@ -6866,7 +6354,6 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TCG_FTPM_TEE is not set
 # CONFIG_TCG_INFINEON is not set
 # CONFIG_TCG_NSC is not set
-# CONFIG_TCG_ST33_I2C is not set
 # CONFIG_TCG_TIS is not set
 # CONFIG_TCG_TIS_I2C is not set
 # CONFIG_TCG_TIS_I2C_ATMEL is not set
@@ -6906,7 +6393,6 @@ CONFIG_TCP_CONG_CUBIC=y
 # CONFIG_TEHUTI is not set
 # CONFIG_TERANETICS_PHY is not set
 # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
-# CONFIG_TEST_BITFIELD is not set
 # CONFIG_TEST_BITMAP is not set
 # CONFIG_TEST_BITOPS is not set
 # CONFIG_TEST_BLACKHOLE_DEV is not set
@@ -6918,10 +6404,8 @@ CONFIG_TCP_CONG_CUBIC=y
 # CONFIG_TEST_DYNAMIC_DEBUG is not set
 # CONFIG_TEST_FIRMWARE is not set
 # CONFIG_TEST_FREE_PAGES is not set
-# CONFIG_TEST_HASH is not set
 # CONFIG_TEST_HEXDUMP is not set
 # CONFIG_TEST_IDA is not set
-# CONFIG_TEST_KASAN_MODULE is not set
 # CONFIG_TEST_KMOD is not set
 # CONFIG_TEST_KSTRTOX is not set
 # CONFIG_TEST_LIST_SORT is not set
@@ -6931,18 +6415,14 @@ CONFIG_TCP_CONG_CUBIC=y
 # CONFIG_TEST_MEMCAT_P is not set
 # CONFIG_TEST_MEMINIT is not set
 # CONFIG_TEST_MIN_HEAP is not set
-# CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_POWER is not set
 # CONFIG_TEST_PRINTF is not set
 # CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_TEST_RHASHTABLE is not set
 # CONFIG_TEST_SCANF is not set
-# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_SORT is not set
-# CONFIG_TEST_STACKINIT is not set
 # CONFIG_TEST_STATIC_KEYS is not set
 # CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_STRSCPY is not set
 # CONFIG_TEST_SYSCTL is not set
 # CONFIG_TEST_UBSAN is not set
 # CONFIG_TEST_UDELAY is not set
@@ -6970,10 +6450,8 @@ CONFIG_TEXTSEARCH=y
 # CONFIG_THERMAL_STATISTICS is not set
 # CONFIG_THERMAL_WRITABLE_TRIPS is not set
 # CONFIG_THINKPAD_ACPI is not set
-CONFIG_THIN_ARCHIVES=y
 # CONFIG_THRUSTMASTER_FF is not set
 # CONFIG_THUMB2_KERNEL is not set
-# CONFIG_THUNDERBOLT is not set
 # CONFIG_THUNDER_NIC_BGX is not set
 # CONFIG_THUNDER_NIC_PF is not set
 # CONFIG_THUNDER_NIC_RGX is not set
@@ -6985,7 +6463,6 @@ CONFIG_TICK_ONESHOT=y
 # CONFIG_TIMB_DMA is not set
 CONFIG_TIMERFD=y
 # CONFIG_TIMERLAT_TRACER is not set
-# CONFIG_TIMER_STATS is not set
 # CONFIG_TIME_NS is not set
 # CONFIG_TINYDRM_HX8357D is not set
 # CONFIG_TINYDRM_ILI9163 is not set
@@ -7015,19 +6492,15 @@ CONFIG_TINY_RCU=y
 # CONFIG_TI_ADS8688 is not set
 # CONFIG_TI_AM335X_ADC is not set
 # CONFIG_TI_CPSW is not set
-# CONFIG_TI_CPSW_ALE is not set
 # CONFIG_TI_CPSW_PHY_SEL is not set
 # CONFIG_TI_CPTS is not set
 # CONFIG_TI_DAC082S085 is not set
 # CONFIG_TI_DAC5571 is not set
 # CONFIG_TI_DAC7311 is not set
-# CONFIG_TI_DAC7512 is not set
 # CONFIG_TI_DAC7612 is not set
-# CONFIG_TI_DAVINCI_CPDMA is not set
 # CONFIG_TI_DAVINCI_MDIO is not set
 # CONFIG_TI_LMP92064 is not set
 # CONFIG_TI_ST is not set
-# CONFIG_TI_SYSCON_RESET is not set
 # CONFIG_TI_TLC4541 is not set
 # CONFIG_TI_TMAG5273 is not set
 # CONFIG_TI_TSC2046 is not set
@@ -7119,12 +6592,9 @@ CONFIG_TMPFS_XATTR=y
 # CONFIG_TOUCHSCREEN_PCAP is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_PROPERTIES is not set
 # CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set
 # CONFIG_TOUCHSCREEN_RM_TS is not set
 # CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
-# CONFIG_TOUCHSCREEN_RPI_FT5406 is not set
-# CONFIG_TOUCHSCREEN_S3C2410 is not set
 # CONFIG_TOUCHSCREEN_S6SY761 is not set
 # CONFIG_TOUCHSCREEN_SILEAD is not set
 # CONFIG_TOUCHSCREEN_SIS_I2C is not set
@@ -7147,7 +6617,6 @@ CONFIG_TMPFS_XATTR=y
 # CONFIG_TOUCHSCREEN_TSC2007_IIO is not set
 # CONFIG_TOUCHSCREEN_TSC200X_CORE is not set
 # CONFIG_TOUCHSCREEN_TSC_SERIO is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_USB_3M is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_USB_DMC_TSC10 is not set
@@ -7167,7 +6636,6 @@ CONFIG_TMPFS_XATTR=y
 # CONFIG_TOUCHSCREEN_USB_NEXIO is not set
 # CONFIG_TOUCHSCREEN_USB_PANJIT is not set
 # CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_TOUCHSCREEN_WACOM_I2C is not set
 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
@@ -7177,7 +6645,6 @@ CONFIG_TMPFS_XATTR=y
 # CONFIG_TOUCHSCREEN_WM9713 is not set
 # CONFIG_TOUCHSCREEN_WM97XX is not set
 # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
-# CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE is not set
 # CONFIG_TOUCHSCREEN_ZET6223 is not set
 # CONFIG_TOUCHSCREEN_ZFORCE is not set
 # CONFIG_TOUCHSCREEN_ZINITIX is not set
@@ -7193,13 +6660,10 @@ CONFIG_TMPFS_XATTR=y
 # CONFIG_TRACE_EVENT_INJECT is not set
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_TRACE_MMIO_ACCESS is not set
-# CONFIG_TRACE_SINK is not set
-# CONFIG_TRACING_EVENTS_GPIO is not set
 CONFIG_TRACING_SUPPORT=y
 CONFIG_TRAD_SIGNALS=y
 # CONFIG_TRANSPARENT_HUGEPAGE is not set
 # CONFIG_TREE_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_TRIM_UNUSED_KSYMS is not set
 # CONFIG_TRUSTED_FOUNDATIONS is not set
 # CONFIG_TRUSTED_KEYS is not set
@@ -7209,7 +6673,6 @@ CONFIG_TRAD_SIGNALS=y
 # CONFIG_TSL2583 is not set
 # CONFIG_TSL2591 is not set
 # CONFIG_TSL2772 is not set
-# CONFIG_TSL2x7x is not set
 # CONFIG_TSL4531 is not set
 # CONFIG_TSNEP is not set
 # CONFIG_TSYS01 is not set
@@ -7234,7 +6697,6 @@ CONFIG_TTY=y
 # CONFIG_UBIFS_ATIME_SUPPORT is not set
 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
 # CONFIG_UBIFS_FS_AUTHENTICATION is not set
-# CONFIG_UBIFS_FS_ENCRYPTION is not set
 CONFIG_UBIFS_FS_LZO=y
 # CONFIG_UBIFS_FS_SECURITY is not set
 CONFIG_UBIFS_FS_XATTR=y
@@ -7245,11 +6707,8 @@ CONFIG_UBSAN_ALIGNMENT=y
 CONFIG_UBSAN_BOOL=y
 # CONFIG_UBSAN_DIV_ZERO is not set
 CONFIG_UBSAN_ENUM=y
-# CONFIG_UBSAN_MISC is not set
 CONFIG_UBSAN_SHIFT=y
 # CONFIG_UBSAN_UNREACHABLE is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_UCSI is not set
 # CONFIG_UDF_FS is not set
 # CONFIG_UDMABUF is not set
 CONFIG_UEVENT_HELPER=y
@@ -7262,15 +6721,11 @@ CONFIG_UID16=y
 # CONFIG_ULTRA is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_UNICODE is not set
-# CONFIG_UNISYSSPAR is not set
-# CONFIG_UNISYS_VISORBUS is not set
 CONFIG_UNIX=y
 CONFIG_UNIX98_PTYS=y
 # CONFIG_UNIXWARE_DISKLABEL is not set
 # CONFIG_UNIX_DIAG is not set
 CONFIG_UNIX_SCM=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_UNWINDER_FRAME_POINTER is not set
 # CONFIG_UPROBES is not set
 # CONFIG_UPROBE_EVENTS is not set
@@ -7336,13 +6791,11 @@ CONFIG_USB_DEFAULT_PERSIST=y
 # CONFIG_USB_DWC3_ULPI is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_EG20T is not set
-# CONFIG_USB_EHCI_ATH79 is not set
 # CONFIG_USB_EHCI_FSL is not set
 # CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_EHCI_HCD_AT91 is not set
 # CONFIG_USB_EHCI_HCD_OMAP is not set
 # CONFIG_USB_EHCI_HCD_PPC_OF is not set
-# CONFIG_USB_EHCI_MSM is not set
 # CONFIG_USB_EHCI_MV is not set
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
@@ -7356,7 +6809,6 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
 # CONFIG_USB_FOTG210_HCD is not set
 # CONFIG_USB_FOTG210_UDC is not set
 # CONFIG_USB_FSL_USB2 is not set
-# CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_FUNCTIONFS is not set
 # CONFIG_USB_FUSB300 is not set
 # CONFIG_USB_GADGET is not set
@@ -7435,9 +6887,7 @@ CONFIG_USB_GADGET_VBUS_DRAW=2
 # CONFIG_USB_HSIC_USB4604 is not set
 # CONFIG_USB_HSO is not set
 # CONFIG_USB_HUB_USB251XB is not set
-# CONFIG_USB_HWA_HCD is not set
 # CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_IMX21_HCD is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_IPHETH is not set
 # CONFIG_USB_ISIGHTFW is not set
@@ -7452,7 +6902,6 @@ CONFIG_USB_GADGET_VBUS_DRAW=2
 # CONFIG_USB_LAN78XX is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_LD is not set
-# CONFIG_USB_LED is not set
 # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
 # CONFIG_USB_LED_TRIG is not set
 # CONFIG_USB_LEGOTOWER is not set
@@ -7469,7 +6918,6 @@ CONFIG_USB_GADGET_VBUS_DRAW=2
 # CONFIG_USB_MON is not set
 # CONFIG_USB_MOUSE is not set
 # CONFIG_USB_MSI2500 is not set
-# CONFIG_USB_MSM_OTG is not set
 # CONFIG_USB_MTU3 is not set
 # CONFIG_USB_MUSB_GADGET is not set
 # CONFIG_USB_MUSB_HDRC is not set
@@ -7515,11 +6963,9 @@ CONFIG_USB_GADGET_VBUS_DRAW=2
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_ONBOARD_HUB is not set
 # CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
 # CONFIG_USB_OTG_FSM is not set
 # CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_PCI is not set
 # CONFIG_USB_PEGASUS is not set
@@ -7531,9 +6977,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_R8A66597 is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_RAW_GADGET is not set
-# CONFIG_USB_RCAR_PHY is not set
 # CONFIG_USB_RENESAS_USBHS is not set
-# CONFIG_USB_RIO500 is not set
 # CONFIG_USB_ROLES_INTEL_XHCI is not set
 # CONFIG_USB_ROLE_SWITCH is not set
 # CONFIG_USB_RTL8150 is not set
@@ -7563,19 +7007,7 @@ CONFIG_USB_SERIAL_GENERIC=y
 # CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN is not set
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
@@ -7605,7 +7037,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y
 # CONFIG_USB_SERIAL_VISOR is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_WISHBONE is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_XR is not set
 # CONFIG_USB_SERIAL_XSENS_MT is not set
 # CONFIG_USB_SEVSEG is not set
@@ -7614,7 +7045,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_SNP_UDC_PLAT is not set
 # CONFIG_USB_SPEEDTOUCH is not set
-# CONFIG_USB_STKWEBCAM is not set
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
@@ -7632,7 +7062,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STV06XX is not set
 # CONFIG_USB_SUPPORT is not set
-# CONFIG_USB_SWITCH_FSA9480 is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_TMC is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
@@ -7646,9 +7075,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y
 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 # CONFIG_USB_VL600 is not set
 # CONFIG_USB_WDM is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
 # CONFIG_USB_XEN_HCD is not set
 # CONFIG_USB_XHCI_DBGCAP is not set
 # CONFIG_USB_XHCI_HCD is not set
@@ -7658,7 +7084,6 @@ CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 # CONFIG_USB_YUREX is not set
 # CONFIG_USB_ZD1201 is not set
 # CONFIG_USB_ZERO is not set
-# CONFIG_USB_ZR364XX is not set
 # CONFIG_USELIB is not set
 # CONFIG_USERFAULTFD is not set
 # CONFIG_USERIO is not set
@@ -7666,7 +7091,6 @@ CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 # CONFIG_USER_EVENTS is not set
 # CONFIG_USE_OF is not set
 # CONFIG_UTS_NS is not set
-# CONFIG_UWB is not set
 # CONFIG_U_SERIAL_CONSOLE is not set
 # CONFIG_V4L_MEM2MEM_DRIVERS is not set
 # CONFIG_V4L_PLATFORM_DRIVERS is not set
@@ -7700,9 +7124,7 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VHOST_VSOCK is not set
 # CONFIG_VIA_RHINE is not set
 # CONFIG_VIA_VELOCITY is not set
-# CONFIG_VIDEO_AD5398 is not set
 # CONFIG_VIDEO_AD5820 is not set
-# CONFIG_VIDEO_AD9389B is not set
 # CONFIG_VIDEO_ADP1653 is not set
 # CONFIG_VIDEO_ADV7170 is not set
 # CONFIG_VIDEO_ADV7175 is not set
@@ -7719,20 +7141,15 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_AK881X is not set
 # CONFIG_VIDEO_AM437X_VPFE is not set
 # CONFIG_VIDEO_AR0521 is not set
-# CONFIG_VIDEO_ARDUCAM_64MP is not set
-# CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set
 # CONFIG_VIDEO_ASPEED is not set
 # CONFIG_VIDEO_ATMEL_ISC is not set
 # CONFIG_VIDEO_ATMEL_ISI is not set
 # CONFIG_VIDEO_AU0828 is not set
 # CONFIG_VIDEO_BCM2835 is not set
-# CONFIG_VIDEO_BCM2835_UNICAM is not set
 # CONFIG_VIDEO_BT819 is not set
 # CONFIG_VIDEO_BT848 is not set
 # CONFIG_VIDEO_BT856 is not set
 # CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_BU64754 is not set
-# CONFIG_VIDEO_CADENCE is not set
 # CONFIG_VIDEO_CADENCE_CSI2RX is not set
 # CONFIG_VIDEO_CADENCE_CSI2TX is not set
 # CONFIG_VIDEO_CAFE_CCIC is not set
@@ -7740,7 +7157,6 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_CCS is not set
 # CONFIG_VIDEO_COBALT is not set
 # CONFIG_VIDEO_CODA is not set
-# CONFIG_VIDEO_CODEC_BCM2835 is not set
 # CONFIG_VIDEO_CS3308 is not set
 # CONFIG_VIDEO_CS5345 is not set
 # CONFIG_VIDEO_CS53L32A is not set
@@ -7750,7 +7166,6 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_CX25840 is not set
 # CONFIG_VIDEO_CX88 is not set
 # CONFIG_VIDEO_DEV is not set
-# CONFIG_VIDEO_DM6446_CCDC is not set
 # CONFIG_VIDEO_DS90UB913 is not set
 # CONFIG_VIDEO_DS90UB953 is not set
 # CONFIG_VIDEO_DS90UB960 is not set
@@ -7783,45 +7198,38 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_IMX335 is not set
 # CONFIG_VIDEO_IMX355 is not set
 # CONFIG_VIDEO_IMX412 is not set
-# CONFIG_VIDEO_IMX477 is not set
-# CONFIG_VIDEO_IMX519 is not set
-# CONFIG_VIDEO_IMX708 is not set
+# CONFIG_VIDEO_IMX7_CSI is not set
+# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set
+# CONFIG_VIDEO_IMX8_ISI is not set
 # CONFIG_VIDEO_IMX8_JPEG is not set
 # CONFIG_VIDEO_IMX_MIPI_CSIS is not set
 # CONFIG_VIDEO_IMX_PXP is not set
-# CONFIG_VIDEO_IRS1125 is not set
 # CONFIG_VIDEO_IR_I2C is not set
 # CONFIG_VIDEO_ISL7998X is not set
-# CONFIG_VIDEO_ISP_BCM2835 is not set
 # CONFIG_VIDEO_IVTV is not set
 # CONFIG_VIDEO_KS0127 is not set
 # CONFIG_VIDEO_LM3560 is not set
 # CONFIG_VIDEO_LM3646 is not set
 # CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_M5MOLS is not set
 # CONFIG_VIDEO_MAX9286 is not set
 # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
 # CONFIG_VIDEO_ML86V7667 is not set
 # CONFIG_VIDEO_MSP3400 is not set
 # CONFIG_VIDEO_MT9M001 is not set
-# CONFIG_VIDEO_MT9M032 is not set
 # CONFIG_VIDEO_MT9M111 is not set
 # CONFIG_VIDEO_MT9P031 is not set
-# CONFIG_VIDEO_MT9T001 is not set
 # CONFIG_VIDEO_MT9T112 is not set
 # CONFIG_VIDEO_MT9V011 is not set
 # CONFIG_VIDEO_MT9V032 is not set
 # CONFIG_VIDEO_MT9V111 is not set
 # CONFIG_VIDEO_MUX is not set
 # CONFIG_VIDEO_MXB is not set
-# CONFIG_VIDEO_NOON010PC30 is not set
 # CONFIG_VIDEO_OG01A1B is not set
 # CONFIG_VIDEO_OMAP2_VOUT is not set
 # CONFIG_VIDEO_OV02A10 is not set
 # CONFIG_VIDEO_OV08D10 is not set
 # CONFIG_VIDEO_OV13858 is not set
 # CONFIG_VIDEO_OV13B10 is not set
-# CONFIG_VIDEO_OV2311 is not set
 # CONFIG_VIDEO_OV2640 is not set
 # CONFIG_VIDEO_OV2659 is not set
 # CONFIG_VIDEO_OV2680 is not set
@@ -7835,7 +7243,6 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_OV5675 is not set
 # CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
-# CONFIG_VIDEO_OV64A40 is not set
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV7640 is not set
@@ -7844,13 +7251,11 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_OV7740 is not set
 # CONFIG_VIDEO_OV8856 is not set
 # CONFIG_VIDEO_OV8865 is not set
-# CONFIG_VIDEO_OV9281 is not set
 # CONFIG_VIDEO_OV9282 is not set
 # CONFIG_VIDEO_OV9640 is not set
 # CONFIG_VIDEO_OV9650 is not set
 # CONFIG_VIDEO_OV9734 is not set
 # CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set
 # CONFIG_VIDEO_RCAR_CSI2 is not set
 # CONFIG_VIDEO_RCAR_ISP is not set
 # CONFIG_VIDEO_RCAR_VIN is not set
@@ -7858,12 +7263,9 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_RDACM21 is not set
 # CONFIG_VIDEO_RJ54N1 is not set
 # CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
-# CONFIG_VIDEO_RP1_CFE is not set
 # CONFIG_VIDEO_S5C73M3 is not set
-# CONFIG_VIDEO_S5K4ECGX is not set
 # CONFIG_VIDEO_S5K5BAF is not set
 # CONFIG_VIDEO_S5K6A3 is not set
-# CONFIG_VIDEO_S5K6AA is not set
 # CONFIG_VIDEO_SAA6588 is not set
 # CONFIG_VIDEO_SAA6752HS is not set
 # CONFIG_VIDEO_SAA7110 is not set
@@ -7873,13 +7275,9 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_SAA7164 is not set
 # CONFIG_VIDEO_SAA717X is not set
 # CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_VIDEO_SMIAPP is not set
 # CONFIG_VIDEO_SOLO6X10 is not set
 # CONFIG_VIDEO_SONY_BTF_MPX is not set
-# CONFIG_VIDEO_SR030PC30 is not set
 # CONFIG_VIDEO_STK1160 is not set
-# CONFIG_VIDEO_STK1160_COMMON is not set
 # CONFIG_VIDEO_ST_MIPID02 is not set
 # CONFIG_VIDEO_SUN4I_CSI is not set
 # CONFIG_VIDEO_SUN6I_CSI is not set
@@ -7893,9 +7291,7 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_TEA6420 is not set
 # CONFIG_VIDEO_THS7303 is not set
 # CONFIG_VIDEO_THS8200 is not set
-# CONFIG_VIDEO_TIMBERDALE is not set
 # CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_TM6000 is not set
 # CONFIG_VIDEO_TVAUDIO is not set
 # CONFIG_VIDEO_TVP514X is not set
 # CONFIG_VIDEO_TVP5150 is not set
@@ -7910,17 +7306,13 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_UPD64031A is not set
 # CONFIG_VIDEO_UPD64083 is not set
 # CONFIG_VIDEO_USBTV is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_VIDEO_V4L2 is not set
 # CONFIG_VIDEO_VP27SMPX is not set
 # CONFIG_VIDEO_VPX3220 is not set
-# CONFIG_VIDEO_VS6624 is not set
 # CONFIG_VIDEO_WM8739 is not set
 # CONFIG_VIDEO_WM8775 is not set
 # CONFIG_VIDEO_XILINX is not set
 # CONFIG_VIDEO_ZORAN is not set
 # CONFIG_VIRTIO_BALLOON is not set
-# CONFIG_VIRTIO_BLK_SCSI is not set
 # CONFIG_VIRTIO_CONSOLE is not set
 # CONFIG_VIRTIO_FS is not set
 # CONFIG_VIRTIO_INPUT is not set
@@ -7931,7 +7323,6 @@ CONFIG_VIRTIO_MENU=y
 # CONFIG_VIRTUALIZATION is not set
 # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
 # CONFIG_VIRT_DRIVERS is not set
-CONFIG_VIRT_TO_BUS=y
 # CONFIG_VITESSE_PHY is not set
 # CONFIG_VL53L0X_I2C is not set
 # CONFIG_VL6180 is not set
@@ -7950,7 +7341,6 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMWARE_VMCI is not set
 # CONFIG_VMXNET3 is not set
 # CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_VOP_BUS is not set
 # CONFIG_VORTEX is not set
 # CONFIG_VSOCKETS is not set
 # CONFIG_VSOCKETS_DIAG is not set
@@ -7958,12 +7348,10 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VT6655 is not set
 # CONFIG_VT6656 is not set
 # CONFIG_VXFS_FS is not set
-# CONFIG_VXGE is not set
 # CONFIG_VXLAN is not set
 # CONFIG_VZ89X is not set
 # CONFIG_W1 is not set
 # CONFIG_W1_CON is not set
-# CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_DS2482 is not set
 # CONFIG_W1_MASTER_DS2490 is not set
 # CONFIG_W1_MASTER_GPIO is not set
@@ -8009,12 +7397,9 @@ CONFIG_WATCHDOG_OPEN_TIMEOUT=0
 # CONFIG_WEXT_PRIV is not set
 # CONFIG_WEXT_PROC is not set
 # CONFIG_WEXT_SPY is not set
-CONFIG_WILINK_PLATFORM_DATA=y
-# CONFIG_WIMAX is not set
 # CONFIG_WIREGUARD is not set
 CONFIG_WIRELESS=y
 # CONFIG_WIRELESS_EXT is not set
-# CONFIG_WIRELESS_WDS is not set
 # CONFIG_WIZNET_W5100 is not set
 # CONFIG_WIZNET_W5300 is not set
 # CONFIG_WL1251 is not set
@@ -8051,7 +7436,6 @@ CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
 # CONFIG_X25 is not set
 # CONFIG_X509_CERTIFICATE_PARSER is not set
 # CONFIG_X86_PKG_TEMP_THERMAL is not set
-CONFIG_X86_SYSFB=y
 # CONFIG_X9250 is not set
 # CONFIG_XDP_SOCKETS is not set
 # CONFIG_XEN is not set
@@ -8136,4 +7520,3 @@ CONFIG_ZONE_DMA=y
 # CONFIG_ZSMALLOC is not set
 CONFIG_ZSMALLOC_CHAIN_SIZE=8
 # CONFIG_ZSWAP is not set
-# CONFIG_ZX_TDM is not set
diff --git a/target/linux/generic/files/drivers/mtd/parsers/routerbootpart.c b/target/linux/generic/files/drivers/mtd/parsers/routerbootpart.c
index f9bba0f3ba..aa786cd895 100644
--- a/target/linux/generic/files/drivers/mtd/parsers/routerbootpart.c
+++ b/target/linux/generic/files/drivers/mtd/parsers/routerbootpart.c
@@ -167,7 +167,7 @@ static void routerboot_find_dynparts(struct mtd_info *master)
 	while (offset < master->size) {
 		err = mtd_read(master, offset, sizeof(buf), &bytes_read, (u8 *)&buf);
 		if (err) {
-			pr_err("%s: mtd_read error while parsing (offset: 0x%X): %d\n",
+			pr_err("%s: mtd_read error while parsing (offset: 0x%zX): %d\n",
 			       master->name, offset, err);
 			continue;
 		}
diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367.c b/target/linux/generic/files/drivers/net/phy/rtl8367.c
index 7f0569d038..b14b63e036 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8367.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8367.c
@@ -1641,7 +1641,7 @@ static int rtl8367_switch_init(struct rtl8366_smi *smi)
 	int err;
 
 	dev->name = "RTL8367";
-	dev->cpu_port = RTL8367_CPU_PORT_NUM;
+	dev->cpu_port = smi->cpu_port;
 	dev->ports = RTL8367_NUM_PORTS;
 	dev->vlans = RTL8367_NUM_VIDS;
 	dev->ops = &rtl8367_sw_ops;
@@ -1722,6 +1722,11 @@ static int rtl8367_detect(struct rtl8366_smi *smi)
 	dev_info(smi->parent, "RTL%s ver. %u chip found\n",
 		 chip_name, rtl_ver & RTL8367_RTL_VER_MASK);
 
+	if (of_property_present(smi->parent->of_node, "realtek,extif1"))
+		smi->cpu_port = RTL8367_CPU_PORT_NUM - 1;
+
+	dev_info(smi->parent, "CPU port: %u\n", smi->cpu_port);
+
 	return 0;
 }
 
diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
index cd0d58cbfa..04c790e924 100644
--- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
@@ -1583,6 +1583,13 @@ static int rtl8367b_detect(struct rtl8366_smi *smi)
 
 	dev_info(smi->parent, "RTL%s chip found\n", chip_name);
 
+	if (of_property_present(smi->parent->of_node, "realtek,extif2"))
+		smi->cpu_port = RTL8367B_CPU_PORT_NUM + 2;
+	else if (of_property_present(smi->parent->of_node, "realtek,extif1") && (chip_ver != 0x1010)) /* for the RTL8367R-VB chip, extif1 corresponds to cpu_port 5 */ 
+		smi->cpu_port = RTL8367B_CPU_PORT_NUM + 1;
+
+	dev_info(smi->parent, "CPU port: %u\n", smi->cpu_port);
+
 	return 0;
 }
 
@@ -1621,9 +1628,7 @@ static int  rtl8367b_probe(struct platform_device *pdev)
 	smi->cmd_write = 0xb8;
 	smi->ops = &rtl8367b_smi_ops;
 	smi->num_ports = RTL8367B_NUM_PORTS;
-	if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
-	    || smi->cpu_port >= smi->num_ports)
-		smi->cpu_port = RTL8367B_CPU_PORT_NUM;
+	smi->cpu_port = RTL8367B_CPU_PORT_NUM;
 	smi->num_vlan_mc = RTL8367B_NUM_VLANS;
 	smi->mib_counters = rtl8367b_mib_counters;
 	smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
diff --git a/target/linux/generic/hack-5.15/250-netfilter_depends.patch b/target/linux/generic/hack-5.15/250-netfilter_depends.patch
index d9a2b81d74..1f8af6dbe8 100644
--- a/target/linux/generic/hack-5.15/250-netfilter_depends.patch
+++ b/target/linux/generic/hack-5.15/250-netfilter_depends.patch
@@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	depends on NETFILTER_ADVANCED
  	help
  	  H.323 is a VoIP signalling protocol from ITU-T. As one of the most
-@@ -1105,7 +1104,6 @@ config NETFILTER_XT_TARGET_SECMARK
+@@ -1114,7 +1113,6 @@ config NETFILTER_XT_TARGET_SECMARK
  
  config NETFILTER_XT_TARGET_TCPMSS
  	tristate '"TCPMSS" target support'
diff --git a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index ec887539d5..d22b9f909b 100644
--- a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
  	  This option adds the flow table core infrastructure.
  
-@@ -1010,6 +1009,15 @@ config NETFILTER_XT_TARGET_NOTRACK
+@@ -1019,6 +1018,15 @@ config NETFILTER_XT_TARGET_NOTRACK
  	depends on NETFILTER_ADVANCED
  	select NETFILTER_XT_TARGET_CT
  
@@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	depends on NETFILTER_ADVANCED
 --- a/net/netfilter/Makefile
 +++ b/net/netfilter/Makefile
-@@ -143,6 +143,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF
+@@ -144,6 +144,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF
  obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o
  obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o
  obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o
@@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,701 @@
+@@ -0,0 +1,702 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -163,7 +163,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +		proto = veth->h_vlan_encapsulated_proto;
 +		break;
 +	case htons(ETH_P_PPP_SES):
-+		proto = nf_flow_pppoe_proto(skb);
++		if (!nf_flow_pppoe_proto(skb, &proto))
++			return NF_ACCEPT;
 +		break;
 +	default:
 +		proto = skb->protocol;
diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
index 75c2e41fb6..b4ed6c9910 100644
--- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-6.1/221-module_exports.patch b/target/linux/generic/hack-6.1/221-module_exports.patch
index 967510bcb6..573eeb15d7 100644
--- a/target/linux/generic/hack-6.1/221-module_exports.patch
+++ b/target/linux/generic/hack-6.1/221-module_exports.patch
@@ -115,7 +115,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	.previous
 --- a/scripts/Makefile.build
 +++ b/scripts/Makefile.build
-@@ -388,7 +388,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa
+@@ -391,7 +391,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa
  # Linker scripts preprocessor (.lds.S -> .lds)
  # ---------------------------------------------------------------------------
  quiet_cmd_cpp_lds_S = LDS     $@
diff --git a/target/linux/generic/hack-6.1/600-net-enable-fraglist-GRO-by-default.patch b/target/linux/generic/hack-6.1/600-net-enable-fraglist-GRO-by-default.patch
new file mode 100644
index 0000000000..51f990039c
--- /dev/null
+++ b/target/linux/generic/hack-6.1/600-net-enable-fraglist-GRO-by-default.patch
@@ -0,0 +1,24 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES	NETIF_F_LRO
+ 
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+ 
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD)
+ 
+ #define NETIF_F_VLAN_FEATURES	(NETIF_F_HW_VLAN_CTAG_FILTER | \
+ 				 NETIF_F_HW_VLAN_CTAG_RX | \
diff --git a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index 6fdfc79207..0822b1a2dd 100644
--- a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -109,7 +109,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +		proto = veth->h_vlan_encapsulated_proto;
 +		break;
 +	case htons(ETH_P_PPP_SES):
-+		proto = nf_flow_pppoe_proto(skb);
++		if (!nf_flow_pppoe_proto(skb, &proto))
++			return NF_ACCEPT;
 +		break;
 +	default:
 +		proto = skb->protocol;
diff --git a/target/linux/generic/hack-6.1/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-6.1/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
index f09ad117b0..54f654ccab 100644
--- a/target/linux/generic/hack-6.1/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
+++ b/target/linux/generic/hack-6.1/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
@@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3488,6 +3488,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3500,6 +3500,9 @@ static int mv88e6xxx_setup_port(struct m
  	else
  		reg = 1 << port;
  
diff --git a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
index 8652e090e1..696a78e53e 100644
--- a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	const struct header_ops *header_ops;
  
  	unsigned char		operstate;
-@@ -2206,6 +2213,10 @@ struct net_device {
+@@ -2204,6 +2211,10 @@ struct net_device {
  	struct mctp_dev __rcu	*mctp_ptr;
  #endif
  
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
   */
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -3046,6 +3046,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3060,6 +3060,10 @@ static inline int pskb_trim(struct sk_bu
  	return (len < skb->len) ? __pskb_trim(skb, len) : 0;
  }
  
@@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /**
   *	pskb_trim_unique - remove end from a paged unique (not cloned) buffer
   *	@skb: buffer to alter
-@@ -3195,16 +3199,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3209,16 +3213,6 @@ static inline struct sk_buff *dev_alloc_
  }
  
  
@@ -152,7 +152,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
 --- a/net/ethernet/eth.c
 +++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
  	const struct ethhdr *eth;
  
  	skb->dev = dev;
diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
index dfbe88e8e6..2729a0ec38 100644
--- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
index ec71f9af4b..09b59478aa 100644
--- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  static void sock_def_write_space_wfree(struct sock *sk);
  static void sock_def_write_space(struct sock *sk);
-@@ -585,6 +587,18 @@ discard_and_relse:
+@@ -586,6 +588,18 @@ discard_and_relse:
  }
  EXPORT_SYMBOL(__sk_receive_skb);
  
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2188,9 +2202,11 @@ static void __sk_free(struct sock *sk)
+@@ -2189,9 +2203,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch
index a90169efc9..d9de0b4fec 100644
--- a/target/linux/generic/hack-6.1/902-debloat_proc.patch
+++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -4114,6 +4114,8 @@ static __net_initdata struct pernet_oper
+@@ -4115,6 +4115,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-6.6/200-tools_portability.patch b/target/linux/generic/hack-6.6/200-tools_portability.patch
new file mode 100644
index 0000000000..5d2b20dcb7
--- /dev/null
+++ b/target/linux/generic/hack-6.6/200-tools_portability.patch
@@ -0,0 +1,97 @@
+From a7ae4ed0a3951c45d4a59ee575951b64ae4a23fb Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 7 May 2024 12:22:15 +0200
+Subject: [PATCH] kernel: fix tools build breakage on macos with x86
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+--- a/tools/scripts/Makefile.include
++++ b/tools/scripts/Makefile.include
+@@ -72,8 +72,6 @@ $(call allow-override,CXX,$(CROSS_COMPIL
+ $(call allow-override,STRIP,$(CROSS_COMPILE)strip)
+ endif
+ 
+-CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
+-
+ ifneq ($(LLVM),)
+ HOSTAR  ?= $(LLVM_PREFIX)llvm-ar$(LLVM_SUFFIX)
+ HOSTCC  ?= $(LLVM_PREFIX)clang$(LLVM_SUFFIX)
+@@ -84,6 +82,9 @@ HOSTCC  ?= gcc
+ HOSTLD  ?= ld
+ endif
+ 
++CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
++HOSTCC_NO_CLANG := $(shell $(HOSTCC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
++
+ # Some tools require Clang, LLC and/or LLVM utils
+ CLANG		?= clang
+ LLC		?= llc
+@@ -92,8 +93,9 @@ LLVM_OBJCOPY	?= llvm-objcopy
+ LLVM_STRIP	?= llvm-strip
+ 
+ ifeq ($(CC_NO_CLANG), 1)
+-EXTRA_WARNINGS += -Wstrict-aliasing=3
+-
++  ifeq ($(HOSTCC_NO_CLANG), 1)
++    EXTRA_WARNINGS += -Wstrict-aliasing=3
++  endif
+ else ifneq ($(CROSS_COMPILE),)
+ # Allow userspace to override CLANG_CROSS_FLAGS to specify their own
+ # sysroots and flags or to avoid the GCC call in pure Clang builds.
+--- a/tools/include/linux/types.h
++++ b/tools/include/linux/types.h
+@@ -56,6 +56,7 @@ typedef __s8  s8;
+ #define __user
+ #endif
+ #define __must_check
++#undef __cold
+ #define __cold
+ 
+ typedef __u16 __bitwise __le16;
+--- a/tools/objtool/include/objtool/objtool.h
++++ b/tools/objtool/include/objtool/objtool.h
+@@ -12,6 +12,7 @@
+ 
+ #include <objtool/elf.h>
+ 
++#undef __weak
+ #define __weak __attribute__((weak))
+ 
+ struct pv_state {
+--- a/tools/include/asm-generic/bitops/fls.h
++++ b/tools/include/asm-generic/bitops/fls.h
+@@ -2,6 +2,8 @@
+ #ifndef _ASM_GENERIC_BITOPS_FLS_H_
+ #define _ASM_GENERIC_BITOPS_FLS_H_
+ 
++#include <string.h>
++
+ /**
+  * fls - find last (most-significant) bit set
+  * @x: the word to search
+@@ -10,6 +12,7 @@
+  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+  */
+ 
++#define fls __linux_fls
+ static __always_inline int fls(unsigned int x)
+ {
+ 	int r = 32;
+--- a/tools/lib/string.c
++++ b/tools/lib/string.c
+@@ -96,6 +96,7 @@ int strtobool(const char *s, bool *res)
+  * If libc has strlcpy() then that version will override this
+  * implementation:
+  */
++#ifndef __APPLE__
+ #ifdef __clang__
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wignored-attributes"
+@@ -114,6 +115,7 @@ size_t __weak strlcpy(char *dest, const
+ #ifdef __clang__
+ #pragma clang diagnostic pop
+ #endif
++#endif
+ 
+ /**
+  * skip_spaces - Removes leading whitespace from @str.
diff --git a/target/linux/generic/hack-6.6/221-module_exports.patch b/target/linux/generic/hack-6.6/221-module_exports.patch
deleted file mode 100644
index 294944a34b..0000000000
--- a/target/linux/generic/hack-6.6/221-module_exports.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 7 Jul 2017 17:05:53 +0200
-Subject: add an optional config option for stripping all unnecessary symbol exports from the kernel image
-
-lede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++---
- include/linux/export.h            |  9 ++++++++-
- scripts/Makefile.build            |  2 +-
- 3 files changed, 24 insertions(+), 5 deletions(-)
-
---- a/include/asm-generic/vmlinux.lds.h
-+++ b/include/asm-generic/vmlinux.lds.h
-@@ -81,6 +81,16 @@
- #define RO_EXCEPTION_TABLE
- #endif
- 
-+#ifndef SYMTAB_KEEP
-+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*)))
-+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*)))
-+#endif
-+
-+#ifndef SYMTAB_DISCARD
-+#define SYMTAB_DISCARD
-+#define SYMTAB_DISCARD_GPL
-+#endif
-+
- /* Align . function alignment. */
- #define ALIGN_FUNCTION()  . = ALIGN(CONFIG_FUNCTION_ALIGNMENT)
- 
-@@ -486,14 +496,14 @@
- 	/* Kernel symbol table: Normal symbols */			\
- 	__ksymtab         : AT(ADDR(__ksymtab) - LOAD_OFFSET) {		\
- 		__start___ksymtab = .;					\
--		KEEP(*(SORT(___ksymtab+*)))				\
-+		SYMTAB_KEEP						\
- 		__stop___ksymtab = .;					\
- 	}								\
- 									\
- 	/* Kernel symbol table: GPL-only symbols */			\
- 	__ksymtab_gpl     : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) {	\
- 		__start___ksymtab_gpl = .;				\
--		KEEP(*(SORT(___ksymtab_gpl+*)))				\
-+		SYMTAB_KEEP_GPL						\
- 		__stop___ksymtab_gpl = .;				\
- 	}								\
- 									\
-@@ -513,7 +523,7 @@
- 									\
- 	/* Kernel symbol table: strings */				\
-         __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) {	\
--		*(__ksymtab_strings)					\
-+		*(__ksymtab_strings+*)					\
- 	}								\
- 									\
- 	/* __*init sections */						\
-@@ -1000,6 +1010,8 @@
- #define COMMON_DISCARDS							\
- 	SANITIZER_DISCARDS						\
- 	PATCHABLE_DISCARDS						\
-+	SYMTAB_DISCARD							\
-+	SYMTAB_DISCARD_GPL						\
- 	*(.discard)							\
- 	*(.discard.*)							\
- 	*(.export_symbol)						\
---- a/include/linux/export-internal.h
-+++ b/include/linux/export-internal.h
-@@ -26,6 +26,12 @@
- #define __KSYM_REF(sym)		".long " #sym
- #endif
- 
-+#ifdef MODULE
-+#define __EXPORT_SUFFIX(sym)
-+#else
-+#define __EXPORT_SUFFIX(sym) "+" #sym
-+#endif
-+
- /*
-  * For every exported symbol, do the following:
-  *
-@@ -38,7 +44,7 @@
-  * former apparently works on all arches according to the binutils source.
-  */
- #define __KSYMTAB(name, sym, sec, ns)						\
--	asm("	.section \"__ksymtab_strings\",\"aMS\",%progbits,1"	"\n"	\
-+	asm("	.section \"__ksymtab_strings" __EXPORT_SUFFIX(sym) "\",\"aMS\",%progbits,1"	"\n"	\
- 	    "__kstrtab_" #name ":"					"\n"	\
- 	    "	.asciz \"" #name "\""					"\n"	\
- 	    "__kstrtabns_" #name ":"					"\n"	\
---- a/scripts/Makefile.build
-+++ b/scripts/Makefile.build
-@@ -366,7 +366,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa
- # Linker scripts preprocessor (.lds.S -> .lds)
- # ---------------------------------------------------------------------------
- quiet_cmd_cpp_lds_S = LDS     $@
--      cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
-+      cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \
- 	                     -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
- 
- $(obj)/%.lds: $(src)/%.lds.S FORCE
diff --git a/target/linux/generic/hack-6.6/259-regmap_dynamic.patch b/target/linux/generic/hack-6.6/259-regmap_dynamic.patch
index 8a799679bf..cb93c96da6 100644
--- a/target/linux/generic/hack-6.6/259-regmap_dynamic.patch
+++ b/target/linux/generic/hack-6.6/259-regmap_dynamic.patch
@@ -137,7 +137,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #include <linux/mutex.h>
  #include <linux/err.h>
  #include <linux/property.h>
-@@ -3433,3 +3434,5 @@ static int __init regmap_initcall(void)
+@@ -3470,3 +3471,5 @@ static int __init regmap_initcall(void)
  	return 0;
  }
  postcore_initcall(regmap_initcall);
diff --git a/target/linux/generic/hack-6.6/600-net-enable-fraglist-GRO-by-default.patch b/target/linux/generic/hack-6.6/600-net-enable-fraglist-GRO-by-default.patch
new file mode 100644
index 0000000000..51f990039c
--- /dev/null
+++ b/target/linux/generic/hack-6.6/600-net-enable-fraglist-GRO-by-default.patch
@@ -0,0 +1,24 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES	NETIF_F_LRO
+ 
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES	(NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+ 
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF	(NETIF_F_GRO_UDP_FWD)
+ 
+ #define NETIF_F_VLAN_FEATURES	(NETIF_F_HW_VLAN_CTAG_FILTER | \
+ 				 NETIF_F_HW_VLAN_CTAG_RX | \
diff --git a/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index 9735983212..eca611da7e 100644
--- a/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.6/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -109,7 +109,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +		proto = veth->h_vlan_encapsulated_proto;
 +		break;
 +	case htons(ETH_P_PPP_SES):
-+		proto = nf_flow_pppoe_proto(skb);
++		if (!nf_flow_pppoe_proto(skb, &proto))
++			return NF_ACCEPT;
 +		break;
 +	default:
 +		proto = skb->protocol;
diff --git a/target/linux/generic/hack-6.6/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-6.6/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
index 6a2c60107b..89c98f6fbc 100644
--- a/target/linux/generic/hack-6.6/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
+++ b/target/linux/generic/hack-6.6/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch
@@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3305,6 +3305,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3365,6 +3365,9 @@ static int mv88e6xxx_setup_port(struct m
  	else
  		reg = 1 << port;
  
diff --git a/target/linux/generic/hack-6.6/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-6.6/721-net-add-packet-mangeling.patch
index 8ef5faa3b1..b51a324027 100644
--- a/target/linux/generic/hack-6.6/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-6.6/721-net-add-packet-mangeling.patch
@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	const struct header_ops *header_ops;
  
  	unsigned char		operstate;
-@@ -2259,6 +2266,10 @@ struct net_device {
+@@ -2257,6 +2264,10 @@ struct net_device {
  	struct mctp_dev __rcu	*mctp_ptr;
  #endif
  
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
   */
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -3081,6 +3081,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3095,6 +3095,10 @@ static inline int pskb_trim(struct sk_bu
  	return (len < skb->len) ? __pskb_trim(skb, len) : 0;
  }
  
@@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /**
   *	pskb_trim_unique - remove end from a paged unique (not cloned) buffer
   *	@skb: buffer to alter
-@@ -3246,16 +3250,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3260,16 +3264,6 @@ static inline struct sk_buff *dev_alloc_
  }
  
  
@@ -152,7 +152,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
 --- a/net/ethernet/eth.c
 +++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
  	const struct ethhdr *eth;
  
  	skb->dev = dev;
diff --git a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
index 1232c664ed..b3fb3c5020 100644
--- a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@@ -15,9 +15,9 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -101,6 +101,29 @@
- #define AQR107_OP_IN_PROG_SLEEP		1000
- #define AQR107_OP_IN_PROG_TIMEOUT	100000
+@@ -127,6 +127,29 @@ struct aqr107_priv {
+ 	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+ };
  
 +/* registers in MDIO_MMD_VEND1 region */
 +#define AQUANTIA_VND1_GLOBAL_SC			0x000
@@ -42,10 +42,10 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 +#define AQUANTIA_VND1_GSYSCFG_5G		3
 +#define AQUANTIA_VND1_GSYSCFG_10G		4
 +
- struct aqr107_hw_stat {
- 	const char *name;
- 	int reg;
-@@ -232,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
+ static int aqr107_get_sset_count(struct phy_device *phydev)
+ {
+ 	return AQR107_SGMII_STAT_SZ;
+@@ -233,6 +256,51 @@ static int aqr_config_aneg(struct phy_de
  	return genphy_c45_check_and_restart_aneg(phydev, changed);
  }
  
@@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  static int aqr_config_intr(struct phy_device *phydev)
  {
  	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -809,7 +877,7 @@ static struct phy_driver aqr_driver[] =
+@@ -838,7 +906,7 @@ static struct phy_driver aqr_driver[] =
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
  	.name		= "Aquantia AQR112",
  	.probe		= aqr107_probe,
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  	.config_intr	= aqr_config_intr,
  	.handle_interrupt = aqr_handle_interrupt,
  	.get_tunable    = aqr107_get_tunable,
-@@ -827,7 +895,7 @@ static struct phy_driver aqr_driver[] =
+@@ -863,7 +931,7 @@ static struct phy_driver aqr_driver[] =
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
  	.name		= "Aquantia AQR412",
  	.probe		= aqr107_probe,
diff --git a/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
index 72a70ebc14..614003a5d8 100644
--- a/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-6.6/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@@ -14,7 +14,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -289,10 +289,16 @@ static int aqr_config_aneg_set_prot(stru
  	phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  		      aquantia_syscfg[if_type].start_rate);
  
diff --git a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
index ee7d0c57b0..c93a77d6a4 100644
--- a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@@ -12,18 +12,18 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/aquantia/aquantia_main.c
 +++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -29,6 +29,8 @@
- #define PHY_ID_AQR113	0x31c31c40
+@@ -30,6 +30,8 @@
  #define PHY_ID_AQR113C	0x31c31c12
+ #define PHY_ID_AQR114C	0x31c31c22
  #define PHY_ID_AQR813	0x31c31cb2
 +#define PHY_ID_AQR112C	0x03a1b790
 +#define PHY_ID_AQR112R	0x31c31d12
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -972,6 +974,30 @@ static struct phy_driver aqr_driver[] =
- 	.get_stats	= aqr107_get_stats,
- 	.link_change_notify = aqr107_link_change_notify,
+@@ -1062,6 +1064,30 @@ static struct phy_driver aqr_driver[] =
+ 	.led_polarity_set = aqr_phy_led_polarity_set,
+ #endif
  },
 +{
 +	PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
@@ -52,9 +52,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  };
  
  module_phy_driver(aqr_driver);
-@@ -991,6 +1017,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+@@ -1082,6 +1108,8 @@ static struct mdio_device_id __maybe_unu
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
diff --git a/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
index 9b2ecba1c3..d010231e49 100644
--- a/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-6.6/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.6/901-debloat_sock_diag.patch
index b0054da2eb..af000f76fc 100644
--- a/target/linux/generic/hack-6.6/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-6.6/901-debloat_sock_diag.patch
@@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  static void sock_def_write_space_wfree(struct sock *sk);
  static void sock_def_write_space(struct sock *sk);
-@@ -589,6 +591,21 @@ discard_and_relse:
+@@ -590,6 +592,21 @@ discard_and_relse:
  }
  EXPORT_SYMBOL(__sk_receive_skb);
  
@@ -83,7 +83,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2246,9 +2263,11 @@ static void __sk_free(struct sock *sk)
+@@ -2247,9 +2264,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-6.6/902-debloat_proc.patch b/target/linux/generic/hack-6.6/902-debloat_proc.patch
index 6b59fd674f..2a311d327a 100644
--- a/target/linux/generic/hack-6.6/902-debloat_proc.patch
+++ b/target/linux/generic/hack-6.6/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -4144,6 +4144,8 @@ static __net_initdata struct pernet_oper
+@@ -4145,6 +4145,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch
index 9968a79699..a64d3021d4 100644
--- a/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch
+++ b/target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch
@@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -204,6 +204,9 @@ static void __br_handle_local_finish(str
+@@ -209,6 +209,9 @@ static void __br_handle_local_finish(str
  /* note: already called with rcu_read_lock */
  static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
  {
@@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__br_handle_local_finish(skb);
  
  	/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -369,6 +372,17 @@ static rx_handler_result_t br_handle_fra
+@@ -376,6 +379,17 @@ static rx_handler_result_t br_handle_fra
  
  forward:
  	switch (p->state) {
diff --git a/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch
index b17196d3a9..8b1e70bd0e 100644
--- a/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch
+++ b/target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		for (i = sizeof(struct ipt_entry);
  		     i < e->target_offset;
  		     i += m->u.match_size) {
-@@ -1224,12 +1261,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1226,12 +1263,15 @@ compat_copy_entry_to_user(struct ipt_ent
  	compat_uint_t origsize;
  	const struct xt_entry_match *ematch;
  	int ret = 0;
diff --git a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 66fd6efed5..6eb72abaa7 100644
--- a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -136,14 +136,14 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /**
   * eth_type_trans - determine the packet's protocol ID.
   * @skb: received socket data
-@@ -173,6 +185,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- 		} else {
- 			skb->pkt_type = PACKET_OTHERHOST;
- 		}
-+
-+		if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+					 dev->local_addr_mask))
-+			skb->gro_skip = 1;
- 	}
+@@ -165,6 +177,10 @@ __be16 eth_type_trans(struct sk_buff *sk
+ 
+ 	eth_skb_pkt_type(skb, dev);
  
++	if (unlikely(!ether_addr_equal_64bits(eth->h_dest, dev->dev_addr)) &&
++	    eth_check_local_mask(eth->h_dest, dev->dev_addr, dev->local_addr_mask))
++		skb->gro_skip = 1;
++
  	/*
+ 	 * Some variants of DSA tagging don't have an ethertype field
+ 	 * at all, so we check here whether one of those tagging
diff --git a/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
index 8c75554033..ba75e4a0f1 100644
--- a/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
+++ b/target/linux/generic/pending-5.15/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
@@ -10,9 +10,9 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
 
 --- a/net/netfilter/nf_flow_table_core.c
 +++ b/net/netfilter/nf_flow_table_core.c
-@@ -606,13 +606,41 @@ void nf_flow_table_free(struct nf_flowta
- }
- EXPORT_SYMBOL_GPL(nf_flow_table_free);
+@@ -651,6 +651,23 @@ static struct pernet_operations nf_flow_
+ 	.exit_batch = nf_flow_table_pernet_exit,
+ };
  
 +static int nf_flow_table_netdev_event(struct notifier_block *this,
 +				      unsigned long event, void *ptr)
@@ -33,26 +33,30 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
 +
  static int __init nf_flow_table_module_init(void)
  {
--	return nf_flow_table_offload_init();
-+	int ret;
-+
-+	ret = nf_flow_table_offload_init();
-+	if (ret)
-+		return ret;
-+
+ 	int ret;
+@@ -663,8 +680,14 @@ static int __init nf_flow_table_module_i
+ 	if (ret)
+ 		goto out_offload;
+ 
 +	ret = register_netdevice_notifier(&flow_offload_netdev_notifier);
 +	if (ret)
-+		nf_flow_table_offload_exit();
++		goto out_offload_init;
 +
-+	return ret;
- }
+ 	return 0;
+ 
++out_offload_init:
++	nf_flow_table_offload_exit();
+ out_offload:
+ 	unregister_pernet_subsys(&nf_flow_table_net_ops);
+ 	return ret;
+@@ -672,6 +695,7 @@ out_offload:
  
  static void __exit nf_flow_table_module_exit(void)
  {
 +	unregister_netdevice_notifier(&flow_offload_netdev_notifier);
  	nf_flow_table_offload_exit();
+ 	unregister_pernet_subsys(&nf_flow_table_net_ops);
  }
- 
 --- a/net/netfilter/nft_flow_offload.c
 +++ b/net/netfilter/nft_flow_offload.c
 @@ -455,47 +455,14 @@ static struct nft_expr_type nft_flow_off
diff --git a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index 2f1b3ed793..3037a724bf 100644
--- a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7803,7 +7803,7 @@ static int nft_register_flowtable_net_ho
+@@ -7811,7 +7811,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
index bbbebefdd5..fd1b79cdfe 100644
--- a/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
+++ b/target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -326,6 +326,8 @@ static rx_handler_result_t br_handle_fra
+@@ -331,6 +331,8 @@ static rx_handler_result_t br_handle_fra
  		fwd_mask |= p->group_fwd_mask;
  		switch (dest[5]) {
  		case 0x00:	/* Bridge Group Address */
diff --git a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
index f10fa057d5..792135b0d2 100644
--- a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
+++ b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch
@@ -15,16 +15,7 @@ Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2467,7 +2467,7 @@ mt7531_setup(struct dsa_switch *ds)
- 	struct mt7530_priv *priv = ds->priv;
- 	struct mt7530_dummy_poll p;
- 	u32 val, id;
--	int ret;
-+	int ret, i;
- 
- 	/* Reset whole chip through gpio pin or memory-mapped registers for
- 	 * different type of hardware
-@@ -2499,6 +2499,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2680,6 +2680,10 @@ mt7531_setup(struct dsa_switch *ds)
  		return -ENODEV;
  	}
  
diff --git a/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
index b1e7a35a55..e3edfa47c6 100644
--- a/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
+++ b/target/linux/generic/pending-5.15/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
@@ -13,7 +13,15 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -744,6 +744,38 @@ static int rtl8226_match_phy_device(stru
+@@ -79,6 +79,7 @@
+ #define RTLGEN_SPEED_MASK			0x0630
+ 
+ #define RTL_GENERIC_PHYID			0x001cc800
++#define RTL_8221B_VB_CG_PHYID			0x001cc849
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -744,6 +745,38 @@ static int rtl8226_match_phy_device(stru
  	       rtlgen_supports_2_5gbps(phydev);
  }
  
@@ -46,13 +54,13 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		id |= val;
 +	}
 +
-+	return (id == 0x001cc849);
++	return (id == RTL_8221B_VB_CG_PHYID);
 +}
 +
  static int rtl822x_probe(struct phy_device *phydev)
  {
  	struct device *dev = &phydev->mdio.dev;
-@@ -1082,7 +1114,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1082,7 +1115,7 @@ static struct phy_driver realtek_drvs[]
  		.write_page     = rtl821x_write_page,
  		.soft_reset     = genphy_soft_reset,
  	}, {
diff --git a/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch
index bf0e0aa66d..07d46d8daa 100644
--- a/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch
+++ b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch
@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -971,6 +971,51 @@ static int rtl8221b_config_init(struct p
+@@ -972,6 +972,51 @@ static int rtl8221b_config_init(struct p
  	return 0;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1119,6 +1164,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1120,6 +1165,8 @@ static struct phy_driver realtek_drvs[]
  		.get_features   = rtl822x_get_features,
  		.config_init    = rtl8221b_config_init,
  		.config_aneg    = rtl822x_config_aneg,
diff --git a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
index b0c0185335..609e03d964 100644
--- a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
+++ b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch
@@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2174,10 +2174,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2356,10 +2356,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  {
  	struct dsa_switch *ds = priv->ds;
  	struct device *dev = priv->dev;
@@ -30,7 +30,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	bus = devm_mdiobus_alloc(dev);
  	if (!bus)
  		return -ENOMEM;
-@@ -2194,7 +2197,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2376,7 +2379,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
  	if (priv->irq)
  		mt7530_setup_mdio_irq(priv);
  
diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
index 0f97033db6..1697347b53 100644
--- a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
+++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -33,7 +33,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/dsa/mt7530.c
 +++ b/drivers/net/dsa/mt7530.c
-@@ -2877,8 +2877,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -3065,8 +3065,7 @@ static void mt753x_phylink_mac_link_up(s
  	/* MT753x MAC works in 1G full duplex mode for all up-clocked
  	 * variants.
  	 */
diff --git a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
index a8c084b980..b127d76e00 100644
--- a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
+++ b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
@@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  /*
   * We need to store the untouched command line for future reference.
   * We also need to store the touched command line since the parameter
-@@ -958,6 +981,7 @@ asmlinkage __visible void __init __no_sa
+@@ -960,6 +983,7 @@ asmlinkage __visible void __init __no_sa
  	pr_notice("%s", linux_banner);
  	early_security_init();
  	setup_arch(&command_line);
diff --git a/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch
index 93a2d146b5..ac4a3138a5 100644
--- a/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch
+++ b/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch
@@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -222,6 +222,9 @@ static void __br_handle_local_finish(str
+@@ -227,6 +227,9 @@ static void __br_handle_local_finish(str
  /* note: already called with rcu_read_lock */
  static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
  {
@@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__br_handle_local_finish(skb);
  
  	/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -390,6 +393,17 @@ forward:
+@@ -397,6 +400,17 @@ forward:
  		goto defer_stp_filtering;
  
  	switch (p->state) {
diff --git a/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch b/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch
new file mode 100644
index 0000000000..3bf7ae98bf
--- /dev/null
+++ b/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch
@@ -0,0 +1,74 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 13 Mar 2024 20:28:37 +0800
+Subject: [PATCH] mips: kernel: fix detect_memory_region() function
+
+1. Do not use memcmp() on unallocated memory, as the new introduced
+   fortify dynamic object size check[1] will report unexpected result.
+2. Use a fixed pattern instead of a random function pointer as the
+   magic value.
+3. Flip magic value and double check it.
+4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and
+   ralink CPUs are using it.
+
+[1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available")
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/include/asm/bootinfo.h |  2 ++
+ arch/mips/kernel/setup.c         | 17 ++++++++++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -93,7 +93,9 @@ const char *get_system_type(void);
+ 
+ extern unsigned long mips_machtype;
+ 
++#ifndef CONFIG_64BIT
+ extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min,  phys_addr_t sz_max);
++#endif
+ 
+ extern void prom_init(void);
+ extern void prom_free_prom_memory(void);
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -90,21 +90,27 @@ static struct resource bss_resource = {
+ unsigned long __kaslr_offset __ro_after_init;
+ EXPORT_SYMBOL(__kaslr_offset);
+ 
+-static void *detect_magic __initdata = detect_memory_region;
+-
+ #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
+ unsigned long ARCH_PFN_OFFSET;
+ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ #endif
+ 
++#ifndef CONFIG_64BIT
++static u32 detect_magic __initdata;
++#define MIPS_MEM_TEST_PATTERN		0xaa5555aa
++
+ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
+ {
+-	void *dm = &detect_magic;
++	void *dm = (void *)KSEG1ADDR(&detect_magic);
+ 	phys_addr_t size;
+ 
+ 	for (size = sz_min; size < sz_max; size <<= 1) {
+-		if (!memcmp(dm, dm + size, sizeof(detect_magic)))
+-			break;
++		__raw_writel(MIPS_MEM_TEST_PATTERN, dm);
++		if (__raw_readl(dm) == __raw_readl(dm + size)) {
++			__raw_writel(~MIPS_MEM_TEST_PATTERN, dm);
++			if (__raw_readl(dm) == __raw_readl(dm + size))
++				break;
++		}
+ 	}
+ 
+ 	pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
+@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad
+ 
+ 	memblock_add(start, size);
+ }
++#endif /* CONFIG_64BIT */
+ 
+ /*
+  * Manage initrd
diff --git a/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch
index 56d62ab8e2..0ab89564ee 100644
--- a/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch
+++ b/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		for (i = sizeof(struct ipt_entry);
  		     i < e->target_offset;
  		     i += m->u.match_size) {
-@@ -1225,12 +1262,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1227,12 +1264,15 @@ compat_copy_entry_to_user(struct ipt_ent
  	compat_uint_t origsize;
  	const struct xt_entry_match *ematch;
  	int ret = 0;
diff --git a/target/linux/generic/pending-6.1/655-increase_skb_pad.patch b/target/linux/generic/pending-6.1/655-increase_skb_pad.patch
index 8af331cb23..9d77ceaf93 100644
--- a/target/linux/generic/pending-6.1/655-increase_skb_pad.patch
+++ b/target/linux/generic/pending-6.1/655-increase_skb_pad.patch
@@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -3012,7 +3012,7 @@ static inline int pskb_network_may_pull(
+@@ -3027,7 +3027,7 @@ static inline int pskb_network_may_pull(
   * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
   */
  #ifndef NET_SKB_PAD
diff --git a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
deleted file mode 100644
index a589fca7a8..0000000000
--- a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h |  2 ++
- include/linux/skbuff.h    |  3 ++-
- net/core/dev.c            | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c        | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2157,6 +2157,8 @@ struct net_device {
- 	struct netdev_hw_addr_list	mc;
- 	struct netdev_hw_addr_list	dev_addrs;
- 
-+	unsigned char		local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- 	struct kset		*queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -967,6 +967,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- 	__u8			ndisc_nodetype:2;
- #endif
-+	__u8			gro_skip:1;
- 
- 	__u8			ipvs_property:1;
- 	__u8			inner_protocol_type:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -492,6 +492,9 @@ static enum gro_result dev_gro_receive(s
- 	int same_flow;
- 	int grow;
- 
-+	if (skb->gro_skip)
-+		goto normal;
-+
- 	if (netif_elide_gro(skb->dev))
- 		goto normal;
- 
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7628,6 +7628,48 @@ static void __netdev_adjacent_dev_unlink
- 					   &upper_dev->adj_list.lower);
- }
- 
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+			       struct net_device *dev)
-+{
-+	int i;
-+
-+	for (i = 0; i < dev->addr_len; i++)
-+		mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+				struct net_device *lower)
-+{
-+	struct net_device *cur;
-+	struct list_head *iter;
-+
-+	netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+		__netdev_addr_mask(mask, cur->dev_addr, lower);
-+		__netdev_upper_mask(mask, cur, lower);
-+	}
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+	unsigned char mask[MAX_ADDR_LEN];
-+	struct net_device *cur;
-+	struct list_head *iter;
-+
-+	memset(mask, 0, sizeof(mask));
-+	__netdev_upper_mask(mask, dev, dev);
-+	memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+	netdev_for_each_lower_dev(dev, cur, iter)
-+		__netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+	rcu_read_lock();
-+	__netdev_update_addr_mask(dev);
-+	rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- 				   struct net_device *upper_dev, bool master,
- 				   void *upper_priv, void *upper_info,
-@@ -7679,6 +7721,7 @@ static int __netdev_upper_dev_link(struc
- 	if (ret)
- 		return ret;
- 
-+	netdev_update_addr_mask(dev);
- 	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 					    &changeupper_info.info);
- 	ret = notifier_to_errno(ret);
-@@ -7775,6 +7818,7 @@ static void __netdev_upper_dev_unlink(st
- 
- 	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
- 
-+	netdev_update_addr_mask(dev);
- 	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 				      &changeupper_info.info);
- 
-@@ -8827,6 +8871,7 @@ int dev_set_mac_address(struct net_devic
- 	if (err)
- 		return err;
- 	dev->addr_assign_type = NET_ADDR_SET;
-+	netdev_update_addr_mask(dev);
- 	call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- 	add_device_randomness(dev->dev_addr, dev->addr_len);
- 	return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
- 
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+	const u16 *a1 = addr1;
-+	const u16 *a2 = addr2;
-+	const u16 *m = mask;
-+
-+	return (((a1[0] ^ a2[0]) & ~m[0]) |
-+		((a1[1] ^ a2[1]) & ~m[1]) |
-+		((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
-  * eth_type_trans - determine the packet's protocol ID.
-  * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- 		} else {
- 			skb->pkt_type = PACKET_OTHERHOST;
- 		}
-+
-+		if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+					 dev->local_addr_mask))
-+			skb->gro_skip = 1;
- 	}
- 
- 	/*
diff --git a/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch b/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch
new file mode 100644
index 0000000000..f52233fe90
--- /dev/null
+++ b/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch
@@ -0,0 +1,627 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on:  770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -424,6 +424,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+ 
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+ 
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+@@ -446,5 +447,48 @@ static inline void gro_normal_one(struct
+ 		gro_normal_list(napi);
+ }
+ 
++/* This function is the alternative of 'inet_iif' and 'inet_sdif'
++ * functions in case we can not rely on fields of IPCB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++	*iif = inet_iif(skb) ?: skb->dev->ifindex;
++	*sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++	if (netif_is_l3_slave(skb->dev)) {
++		struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++		*sdif = *iif;
++		*iif = master ? master->ifindex : 0;
++	}
++#endif
++}
++
++/* This function is the alternative of 'inet6_iif' and 'inet6_sdif'
++ * functions in case we can not rely on fields of IP6CB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet6_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++	/* using skb->dev->ifindex because skb_dst(skb) is not initialized */
++	*iif = skb->dev->ifindex;
++	*sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++	if (netif_is_l3_slave(skb->dev)) {
++		struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++		*sdif = *iif;
++		*iif = master ? master->ifindex : 0;
++	}
++#endif
++}
++
+ 
+ #endif /* _NET_IPV6_GRO_H */
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2057,7 +2057,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+ 
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ 				netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++				struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -290,6 +290,33 @@ done:
+ 	return 0;
+ }
+ 
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++	if (unlikely(p->len + skb->len >= 65536))
++		return -E2BIG;
++
++	if (NAPI_GRO_CB(p)->last == p)
++		skb_shinfo(p)->frag_list = skb;
++	else
++		NAPI_GRO_CB(p)->last->next = skb;
++
++	skb_pull(skb, skb_gro_offset(skb));
++
++	NAPI_GRO_CB(p)->last = skb;
++	NAPI_GRO_CB(p)->count++;
++	p->data_len += skb->len;
++
++	/* sk ownership - if any - completely transferred to the aggregated packet */
++	skb->destructor = NULL;
++	skb->sk = NULL;
++	p->truesize += skb->truesize;
++	p->len += skb->len;
++
++	NAPI_GRO_CB(skb)->same_flow = 1;
++
++	return 0;
++}
++
+ 
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -27,6 +27,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ 	}
+ }
+ 
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++				     __be32 *oldip, __be32 newip,
++				     __be16 *oldport, __be16 newport)
++{
++	struct tcphdr *th;
++	struct iphdr *iph;
++
++	if (*oldip == newip && *oldport == newport)
++		return;
++
++	th = tcp_hdr(seg);
++	iph = ip_hdr(seg);
++
++	inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++	inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++	*oldport = newport;
++
++	csum_replace4(&iph->check, *oldip, newip);
++	*oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++	const struct tcphdr *th;
++	const struct iphdr *iph;
++	struct sk_buff *seg;
++	struct tcphdr *th2;
++	struct iphdr *iph2;
++
++	seg = segs;
++	th = tcp_hdr(seg);
++	iph = ip_hdr(seg);
++	th2 = tcp_hdr(seg->next);
++	iph2 = ip_hdr(seg->next);
++
++	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	    iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++		return segs;
++
++	while ((seg = seg->next)) {
++		th2 = tcp_hdr(seg);
++		iph2 = ip_hdr(seg);
++
++		__tcpv4_gso_segment_csum(seg,
++					 &iph2->saddr, iph->saddr,
++					 &th2->source, th->source);
++		__tcpv4_gso_segment_csum(seg,
++					 &iph2->daddr, iph->daddr,
++					 &th2->dest, th->dest);
++	}
++
++	return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++					      netdev_features_t features)
++{
++	skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++	if (IS_ERR(skb))
++		return skb;
++
++	return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ 					netdev_features_t features)
+ {
+@@ -36,6 +100,9 @@ static struct sk_buff *tcp4_gso_segment(
+ 	if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ 		return ERR_PTR(-EINVAL);
+ 
++	if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++		return __tcp4_gso_segment_list(skb, features);
++
+ 	if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ 		const struct iphdr *iph = ip_hdr(skb);
+ 		struct tcphdr *th = tcp_hdr(skb);
+@@ -177,61 +244,76 @@ out:
+ 	return segs;
+ }
+ 
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+-	struct sk_buff *pp = NULL;
++	struct tcphdr *th2;
+ 	struct sk_buff *p;
++
++	list_for_each_entry(p, head, list) {
++		if (!NAPI_GRO_CB(p)->same_flow)
++			continue;
++
++		th2 = tcp_hdr(p);
++		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++			NAPI_GRO_CB(p)->same_flow = 0;
++			continue;
++		}
++
++		return p;
++	}
++
++	return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++	unsigned int thlen, hlen, off;
+ 	struct tcphdr *th;
+-	struct tcphdr *th2;
+-	unsigned int len;
+-	unsigned int thlen;
+-	__be32 flags;
+-	unsigned int mss = 1;
+-	unsigned int hlen;
+-	unsigned int off;
+-	int flush = 1;
+-	int i;
+ 
+ 	off = skb_gro_offset(skb);
+ 	hlen = off + sizeof(*th);
+ 	th = skb_gro_header(skb, hlen, off);
+ 	if (unlikely(!th))
+-		goto out;
++		return NULL;
+ 
+ 	thlen = th->doff * 4;
+ 	if (thlen < sizeof(*th))
+-		goto out;
++		return NULL;
+ 
+ 	hlen = off + thlen;
+ 	if (skb_gro_header_hard(skb, hlen)) {
+ 		th = skb_gro_header_slow(skb, hlen, off);
+ 		if (unlikely(!th))
+-			goto out;
++			return NULL;
+ 	}
+ 
+ 	skb_gro_pull(skb, thlen);
+ 
+-	len = skb_gro_len(skb);
+-	flags = tcp_flag_word(th);
+-
+-	list_for_each_entry(p, head, list) {
+-		if (!NAPI_GRO_CB(p)->same_flow)
+-			continue;
++	return th;
++}
+ 
+-		th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++				struct tcphdr *th)
++{
++	unsigned int thlen = th->doff * 4;
++	struct sk_buff *pp = NULL;
++	struct sk_buff *p;
++	struct tcphdr *th2;
++	unsigned int len;
++	__be32 flags;
++	unsigned int mss = 1;
++	int flush = 1;
++	int i;
+ 
+-		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+-			NAPI_GRO_CB(p)->same_flow = 0;
+-			continue;
+-		}
++	len = skb_gro_len(skb);
++	flags = tcp_flag_word(th);
+ 
+-		goto found;
+-	}
+-	p = NULL;
+-	goto out_check_final;
++	p = tcp_gro_lookup(head, th);
++	if (!p)
++		goto out_check_final;
+ 
+-found:
+ 	/* Include the IP ID check below from the inner most IP hdr */
++	th2 = tcp_hdr(p);
+ 	flush = NAPI_GRO_CB(p)->flush;
+ 	flush |= (__force int)(flags & TCP_FLAG_CWR);
+ 	flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -268,6 +350,19 @@ found:
+ 	flush |= p->decrypted ^ skb->decrypted;
+ #endif
+ 
++	if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++		flush |= (__force int)(flags ^ tcp_flag_word(th2));
++		flush |= skb->ip_summed != p->ip_summed;
++		flush |= skb->csum_level != p->csum_level;
++		flush |= !pskb_may_pull(skb, skb_gro_offset(skb));
++		flush |= NAPI_GRO_CB(p)->count >= 64;
++
++		if (flush || skb_gro_receive_list(p, skb))
++			mss = 1;
++
++		goto out_check_final;
++	}
++
+ 	if (flush || skb_gro_receive(p, skb)) {
+ 		mss = 1;
+ 		goto out_check_final;
+@@ -289,7 +384,6 @@ out_check_final:
+ 	if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ 		pp = p;
+ 
+-out:
+ 	NAPI_GRO_CB(skb)->flush |= (flush != 0);
+ 
+ 	return pp;
+@@ -315,18 +409,58 @@ int tcp_gro_complete(struct sk_buff *skb
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+ 
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++				    struct tcphdr *th)
++{
++	const struct iphdr *iph;
++	struct sk_buff *p;
++	struct sock *sk;
++	struct net *net;
++	int iif, sdif;
++
++	if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++		return;
++
++	p = tcp_gro_lookup(head, th);
++	if (p) {
++		NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++		return;
++	}
++
++	inet_get_iif_sdif(skb, &iif, &sdif);
++	iph = skb_gro_network_header(skb);
++	net = dev_net(skb->dev);
++	sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++				       iph->saddr, th->source,
++				       iph->daddr, ntohs(th->dest),
++				       iif, sdif);
++	NAPI_GRO_CB(skb)->is_flist = !sk;
++	if (sk)
++		sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++	struct tcphdr *th;
++
+ 	/* Don't bother verifying checksum if we're going to flush anyway. */
+ 	if (!NAPI_GRO_CB(skb)->flush &&
+ 	    skb_gro_checksum_validate(skb, IPPROTO_TCP,
+-				      inet_gro_compute_pseudo)) {
+-		NAPI_GRO_CB(skb)->flush = 1;
+-		return NULL;
+-	}
++				      inet_gro_compute_pseudo))
++		goto flush;
++
++	th = tcp_gro_pull_header(skb);
++	if (!th)
++		goto flush;
+ 
+-	return tcp_gro_receive(head, skb);
++	tcp4_check_fraglist_gro(head, skb, th);
++
++	return tcp_gro_receive(head, skb, th);
++
++flush:
++	NAPI_GRO_CB(skb)->flush = 1;
++	return NULL;
+ }
+ 
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -334,6 +468,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ 	const struct iphdr *iph = ip_hdr(skb);
+ 	struct tcphdr *th = tcp_hdr(skb);
+ 
++	if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++		skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++		skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++		__skb_incr_checksum_unnecessary(skb);
++
++		return 0;
++	}
++
+ 	th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ 				  iph->daddr, 0);
+ 	skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -425,33 +425,6 @@ out:
+ 	return segs;
+ }
+ 
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+-	if (unlikely(p->len + skb->len >= 65536))
+-		return -E2BIG;
+-
+-	if (NAPI_GRO_CB(p)->last == p)
+-		skb_shinfo(p)->frag_list = skb;
+-	else
+-		NAPI_GRO_CB(p)->last->next = skb;
+-
+-	skb_pull(skb, skb_gro_offset(skb));
+-
+-	NAPI_GRO_CB(p)->last = skb;
+-	NAPI_GRO_CB(p)->count++;
+-	p->data_len += skb->len;
+-
+-	/* sk ownership - if any - completely transferred to the aggregated packet */
+-	skb->destructor = NULL;
+-	skb->sk = NULL;
+-	p->truesize += skb->truesize;
+-	p->len += skb->len;
+-
+-	NAPI_GRO_CB(skb)->same_flow = 1;
+-
+-	return 0;
+-}
+-
+ 
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+  */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+ 
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++				    struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++	const struct ipv6hdr *hdr;
++	struct sk_buff *p;
++	struct sock *sk;
++	struct net *net;
++	int iif, sdif;
++
++	if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++		return;
++
++	p = tcp_gro_lookup(head, th);
++	if (p) {
++		NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++		return;
++	}
++
++	inet6_get_iif_sdif(skb, &iif, &sdif);
++	hdr = skb_gro_network_header(skb);
++	net = dev_net(skb->dev);
++	sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++					&hdr->saddr, th->source,
++					&hdr->daddr, ntohs(th->dest),
++					iif, sdif);
++	NAPI_GRO_CB(skb)->is_flist = !sk;
++	if (sk)
++		sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++	struct tcphdr *th;
++
+ 	/* Don't bother verifying checksum if we're going to flush anyway. */
+ 	if (!NAPI_GRO_CB(skb)->flush &&
+ 	    skb_gro_checksum_validate(skb, IPPROTO_TCP,
+-				      ip6_gro_compute_pseudo)) {
+-		NAPI_GRO_CB(skb)->flush = 1;
+-		return NULL;
+-	}
++				      ip6_gro_compute_pseudo))
++		goto flush;
+ 
+-	return tcp_gro_receive(head, skb);
++	th = tcp_gro_pull_header(skb);
++	if (!th)
++		goto flush;
++
++	tcp6_check_fraglist_gro(head, skb, th);
++
++	return tcp_gro_receive(head, skb, th);
++
++flush:
++	NAPI_GRO_CB(skb)->flush = 1;
++	return NULL;
+ }
+ 
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ 	const struct ipv6hdr *iph = ipv6_hdr(skb);
+ 	struct tcphdr *th = tcp_hdr(skb);
+ 
++	if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++		skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++		skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++		__skb_incr_checksum_unnecessary(skb);
++
++		return 0;
++	}
++
+ 	th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ 				  &iph->daddr, 0);
+ 	skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -39,6 +91,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ 	return tcp_gro_complete(skb);
+ }
+ 
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++				     __be16 *oldport, __be16 newport)
++{
++	struct tcphdr *th;
++
++	if (*oldport == newport)
++		return;
++
++	th = tcp_hdr(seg);
++	inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++	*oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++	const struct tcphdr *th;
++	const struct ipv6hdr *iph;
++	struct sk_buff *seg;
++	struct tcphdr *th2;
++	struct ipv6hdr *iph2;
++
++	seg = segs;
++	th = tcp_hdr(seg);
++	iph = ipv6_hdr(seg);
++	th2 = tcp_hdr(seg->next);
++	iph2 = ipv6_hdr(seg->next);
++
++	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	    ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++	    ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++		return segs;
++
++	while ((seg = seg->next)) {
++		th2 = tcp_hdr(seg);
++		iph2 = ipv6_hdr(seg);
++
++		iph2->saddr = iph->saddr;
++		iph2->daddr = iph->daddr;
++		__tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++		__tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++	}
++
++	return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++					      netdev_features_t features)
++{
++	skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++	if (IS_ERR(skb))
++		return skb;
++
++	return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ 					netdev_features_t features)
+ {
+@@ -50,6 +157,9 @@ static struct sk_buff *tcp6_gso_segment(
+ 	if (!pskb_may_pull(skb, sizeof(*th)))
+ 		return ERR_PTR(-EINVAL);
+ 
++	if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++		return __tcp6_gso_segment_list(skb, features);
++
+ 	if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ 		const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ 		struct tcphdr *th = tcp_hdr(skb);
diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index fb6eb73232..9f8c3d6ff5 100644
--- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7951,7 +7951,7 @@ static int nft_register_flowtable_net_ho
+@@ -7959,7 +7959,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
index 989aca8f35..367c41bff0 100644
--- a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
+++ b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -344,6 +344,8 @@ static rx_handler_result_t br_handle_fra
+@@ -349,6 +349,8 @@ static rx_handler_result_t br_handle_fra
  		fwd_mask |= p->group_fwd_mask;
  		switch (dest[5]) {
  		case 0x00:	/* Bridge Group Address */
@@ -134,7 +134,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		return -EMSGSIZE;
  
  	timerval = br_timer_value(&p->message_age_timer);
-@@ -878,6 +880,7 @@ static const struct nla_policy br_port_p
+@@ -879,6 +881,7 @@ static const struct nla_policy br_port_p
  	[IFLA_BRPORT_LOCKED] = { .type = NLA_U8 },
  	[IFLA_BRPORT_BACKUP_PORT] = { .type = NLA_U32 },
  	[IFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT] = { .type = NLA_U32 },
@@ -142,7 +142,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  /* Change the state of the port and notify spanning tree */
-@@ -943,6 +946,7 @@ static int br_setport(struct net_bridge_
+@@ -944,6 +947,7 @@ static int br_setport(struct net_bridge_
  	br_set_port_flag(p, tb, IFLA_BRPORT_NEIGH_SUPPRESS, BR_NEIGH_SUPPRESS);
  	br_set_port_flag(p, tb, IFLA_BRPORT_ISOLATED, BR_ISOLATED);
  	br_set_port_flag(p, tb, IFLA_BRPORT_LOCKED, BR_PORT_LOCKED);
diff --git a/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
index f5987109f6..05edcc8bf4 100644
--- a/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
+++ b/target/linux/generic/pending-6.1/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
@@ -13,7 +13,15 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -754,6 +754,38 @@ static int rtl8226_match_phy_device(stru
+@@ -80,6 +80,7 @@
+ 
+ #define RTL_GENERIC_PHYID			0x001cc800
+ #define RTL_8211FVD_PHYID			0x001cc878
++#define RTL_8221B_VB_CG_PHYID			0x001cc849
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -754,6 +755,38 @@ static int rtl8226_match_phy_device(stru
  	       rtlgen_supports_2_5gbps(phydev);
  }
  
@@ -46,13 +54,13 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		id |= val;
 +	}
 +
-+	return (id == 0x001cc849);
++	return (id == RTL_8221B_VB_CG_PHYID);
 +}
 +
  static int rtl822x_probe(struct phy_device *phydev)
  {
  	struct device *dev = &phydev->mdio.dev;
-@@ -1104,7 +1136,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1104,7 +1137,7 @@ static struct phy_driver realtek_drvs[]
  		.write_page     = rtl821x_write_page,
  		.soft_reset     = genphy_soft_reset,
  	}, {
diff --git a/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch b/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
index a7a4bafbb6..f3725bf7d3 100644
--- a/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
+++ b/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
@@ -17,7 +17,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2192,7 +2192,7 @@ struct net_device {
+@@ -2190,7 +2190,7 @@ struct net_device {
  #if IS_ENABLED(CONFIG_AX25)
  	void			*ax25_ptr;
  #endif
diff --git a/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
index 82cd419a7e..249ba5c496 100644
--- a/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
+++ b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -981,6 +981,51 @@ static int rtl8221b_config_init(struct p
+@@ -982,6 +982,51 @@ static int rtl8221b_config_init(struct p
  	return 0;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1141,6 +1186,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1142,6 +1187,8 @@ static struct phy_driver realtek_drvs[]
  		.get_features   = rtl822x_get_features,
  		.config_init    = rtl8221b_config_init,
  		.config_aneg    = rtl822x_config_aneg,
diff --git a/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch b/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch
new file mode 100644
index 0000000000..500567b4ed
--- /dev/null
+++ b/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch
@@ -0,0 +1,45 @@
+From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001
+Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 7 May 2024 22:43:30 +0100
+Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set
+ manually
+To: Andrew Lunn <andrew@lunn.ch>,
+    Heiner Kallweit <hkallweit1@gmail.com>,
+    Russell King <linux@armlinux.org.uk>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    SkyLake Huang <skylake.huang@mediatek.com>,
+    Eric Woudstra <ericwouds@gmail.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org
+
+Setting LED_OFF via the brightness_set should deactivate hw control,
+so make sure netdev trigger rules also get cleared in that case.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+This is basically a stop-gap measure until unified LED handling has
+been implemented accross all MediaTek and Airoha PHYs.
+See also
+https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/
+
+ drivers/net/phy/air_en8811h.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_
+ 
+ 	changed |= (priv->led[index].rules != 0);
+ 
++	/* clear netdev trigger rules in case LED_OFF has been set */
++	if (!on)
++		priv->led[index].rules = 0;
++
+ 	if (changed)
+ 		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
+ 				      AIR_PHY_LED_ON(index),
diff --git a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
deleted file mode 100644
index 1dfa1366eb..0000000000
--- a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
+++ /dev/null
@@ -1,1115 +0,0 @@
-From patchwork Tue Feb  6 19:47:51 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
-X-Patchwork-Id: 13547762
-X-Patchwork-Delegate: kuba@kernel.org
-From: Eric Woudstra <ericwouds@gmail.com>
-To: "David S. Miller" <davem@davemloft.net>,
-	Eric Dumazet <edumazet@google.com>,
-	Jakub Kicinski <kuba@kernel.org>,
-	Paolo Abeni <pabeni@redhat.com>,
-	Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Andrew Lunn <andrew@lunn.ch>,
-	Heiner Kallweit <hkallweit1@gmail.com>,
-	Russell King <linux@armlinux.org.uk>,
-	Matthias Brugger <matthias.bgg@gmail.com>,
-	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-	"Frank Wunderlich" <frank-w@public-files.de>,
-	Daniel Golle <daniel@makrotopia.org>,
-	Lucien Jheng  <lucien.jheng@airoha.com>,
-	Zhi-Jun You <hujy652@protonmail.com>
-Cc: netdev@vger.kernel.org,
-	devicetree@vger.kernel.org,
-	Eric Woudstra <ericwouds@gmail.com>
-Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
- PHY driver
-Date: Tue,  6 Feb 2024 20:47:51 +0100
-Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
-X-Mailer: git-send-email 2.42.1
-In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
-References: <20240206194751.1901802-1-ericwouds@gmail.com>
-Precedence: bulk
-X-Mailing-List: netdev@vger.kernel.org
-List-Id: <netdev.vger.kernel.org>
-List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
-List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
-MIME-Version: 1.0
-X-Patchwork-Delegate: kuba@kernel.org
-
-* Source originated from airoha's en8811h v1.2.1 driver
- * Moved air_en8811h.h to air_en8811h.c
- * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
- * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
- * Added .get_rate_matching()
- * Use generic phy_read/write() and phy_read/write_mmd()
- * Edited .get_features() to use generic C45 functions
- * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
- * Use led handling functions from mediatek-ge-soc.c
- * Simplified led handling by storing led rules
- * Cleanup macro definitions
- * Cleanup code to pass checkpatch.pl
- * General code cleanup
-
-Changes from original RFC patch:
-
- * Use the correct order in Kconfig and Makefile
- * Change some register naming to correspond with datasheet
- * Use phy_driver .read_page() and .write_page()
- * Use module_phy_driver()
- * Use get_unaligned_le16() instead of macro
- * In .config_aneg() and .read_status() use genphy_xxx() C22
- * Use another vendor register to read real speed
- * Load firmware only once and store firmware version
- * Apply 2.5G LPA work-around (firmware before 24011202)
- * Read 2.5G LPA from vendor register (firmware 24011202 and later)
-
-Changes to be committed:
-	modified:   drivers/net/phy/Kconfig
-	modified:   drivers/net/phy/Makefile
-	new file:   drivers/net/phy/air_en8811h.c
-
-Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
----
- drivers/net/phy/Kconfig       |    5 +
- drivers/net/phy/Makefile      |    1 +
- drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
- 3 files changed, 1012 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -69,6 +69,11 @@ config SFP
- 
- comment "MII PHY device drivers"
- 
-+config AIR_EN8811H_PHY
-+	tristate "Airoha EN8811H 2.5 Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8811H PHY.
-+
- config AMD_PHY
- 	tristate "AMD and Altima PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -32,6 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
- 
- obj-$(CONFIG_ADIN_PHY)		+= adin.o
- obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
-+obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
- obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
---- /dev/null
-+++ b/drivers/net/phy/air_en8811h.c
-@@ -0,0 +1,1006 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Driver for Airoha Ethernet PHYs
-+ *
-+ * Currently supporting the EN8811H.
-+ *
-+ * Limitations of the EN8811H:
-+ * - Only full duplex supported
-+ * - Forced speed (AN off) is not supported by hardware (100Mbps)
-+ *
-+ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
-+ *
-+ * Copyright (C) 2023 Airoha Technology Corp.
-+ */
-+
-+#include <linux/phy.h>
-+#include <linux/firmware.h>
-+#include <linux/property.h>
-+#include <asm/unaligned.h>
-+
-+#define EN8811H_PHY_ID		0x03a2a411
-+
-+#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
-+#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
-+
-+#define AIR_FW_ADDR_DM	0x00000000
-+#define AIR_FW_ADDR_DSP	0x00100000
-+
-+/* u32 (DWORD) component macros */
-+#define LOWORD(d) ((u16)(u32)(d))
-+#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
-+
-+/* MII Registers */
-+#define AIR_AUX_CTRL_STATUS	0x1d
-+#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
-+#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
-+#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
-+#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
-+
-+#define AIR_EXT_PAGE_ACCESS		0x1f
-+#define   AIR_PHY_PAGE_STANDARD			0x0000
-+#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
-+
-+/* MII Registers Page 4*/
-+#define AIR_PBUS_MODE			0x10
-+#define   AIR_PBUS_MODE_ADDR_FIXED		0x0000
-+#define   AIR_PBUS_MODE_ADDR_INCR		BIT(15)
-+#define AIR_PBUS_WR_ADDR_HIGH		0x11
-+#define AIR_PBUS_WR_ADDR_LOW		0x12
-+#define AIR_PBUS_WR_DATA_HIGH		0x13
-+#define AIR_PBUS_WR_DATA_LOW		0x14
-+#define AIR_PBUS_RD_ADDR_HIGH		0x15
-+#define AIR_PBUS_RD_ADDR_LOW		0x16
-+#define AIR_PBUS_RD_DATA_HIGH		0x17
-+#define AIR_PBUS_RD_DATA_LOW		0x18
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define EN8811H_PHY_FW_STATUS		0x8009
-+#define   EN8811H_PHY_READY			0x02
-+
-+#define AIR_PHY_HOST_CMD_1		0x800c
-+#define AIR_PHY_HOST_CMD_1_MODE1		0x0
-+#define AIR_PHY_HOST_CMD_2		0x800d
-+#define AIR_PHY_HOST_CMD_2_MODE1		0x0
-+#define AIR_PHY_HOST_CMD_3		0x800e
-+#define AIR_PHY_HOST_CMD_3_MODE1		0x1101
-+#define AIR_PHY_HOST_CMD_3_DOCMD		0x1100
-+#define AIR_PHY_HOST_CMD_4		0x800f
-+#define AIR_PHY_HOST_CMD_4_MODE1		0x0002
-+#define AIR_PHY_HOST_CMD_4_INTCLR		0x00e4
-+
-+/* Registers on MDIO_MMD_VEND2 */
-+#define AIR_PHY_LED_BCR			0x021
-+#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
-+#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
-+#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
-+#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
-+
-+#define AIR_PHY_LED_DUR_ON		0x022
-+
-+#define AIR_PHY_LED_DUR_BLINK		0x023
-+
-+#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
-+#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
-+#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
-+#define   AIR_PHY_LED_ON_LINK100		BIT(1)
-+#define   AIR_PHY_LED_ON_LINK10			BIT(2)
-+#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
-+#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
-+#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
-+#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
-+#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
-+#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
-+#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
-+
-+#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
-+#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
-+#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
-+#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
-+#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
-+#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
-+#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
-+#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
-+#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
-+#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
-+#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
-+#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
-+#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
-+
-+/* Registers on BUCKPBUS */
-+#define EN8811H_2P5G_LPA		0x3b30
-+#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
-+
-+#define EN8811H_FW_VERSION		0x3b3c
-+
-+#define EN8811H_POLARITY		0xca0f8
-+#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
-+#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
-+
-+#define EN8811H_GPIO_OUTPUT		0xcf8b8
-+#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
-+
-+#define EN8811H_FW_CTRL_1		0x0f0018
-+#define   EN8811H_FW_CTRL_1_START		0x0
-+#define   EN8811H_FW_CTRL_1_FINISH		0x1
-+#define EN8811H_FW_CTRL_2		0x800000
-+#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
-+
-+#define EN8811H_LED_COUNT	3
-+
-+/* GPIO5  <-> BASE_T_LED0
-+ * GPIO4  <-> BASE_T_LED1
-+ * GPIO3  <-> BASE_T_LED2
-+ *
-+ * Default setup suitable for 2 leds connected:
-+ *    100M link up triggers led0, only led0 blinking on traffic
-+ *   1000M link up triggers led1, only led1 blinking on traffic
-+ *   2500M link up triggers led0 and led1, both blinking on traffic
-+ * Also suitable for 1 led connected:
-+ *     any link up triggers led2
-+ */
-+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+				  BIT(TRIGGER_NETDEV_LINK_100)  | \
-+				  BIT(TRIGGER_NETDEV_RX)        | \
-+				  BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+				  BIT(TRIGGER_NETDEV_LINK_1000) | \
-+				  BIT(TRIGGER_NETDEV_RX)        | \
-+				  BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED2  BIT(TRIGGER_NETDEV_LINK)
-+
-+struct led {
-+	unsigned long rules;
-+	unsigned long state;
-+};
-+
-+struct en8811h_priv {
-+	u32		firmware_version;
-+	struct led	led[EN8811H_LED_COUNT];
-+};
-+
-+enum {
-+	AIR_PHY_LED_STATE_FORCE_ON,
-+	AIR_PHY_LED_STATE_FORCE_BLINK,
-+};
-+
-+enum {
-+	AIR_PHY_LED_DUR_BLINK_32M,
-+	AIR_PHY_LED_DUR_BLINK_64M,
-+	AIR_PHY_LED_DUR_BLINK_128M,
-+	AIR_PHY_LED_DUR_BLINK_256M,
-+	AIR_PHY_LED_DUR_BLINK_512M,
-+	AIR_PHY_LED_DUR_BLINK_1024M,
-+};
-+
-+enum {
-+	AIR_LED_DISABLE,
-+	AIR_LED_ENABLE,
-+};
-+
-+enum {
-+	AIR_ACTIVE_LOW,
-+	AIR_ACTIVE_HIGH,
-+};
-+
-+enum {
-+	AIR_LED_MODE_DISABLE,
-+	AIR_LED_MODE_USER_DEFINE,
-+};
-+
-+#define AIR_PHY_LED_DUR_UNIT	1024
-+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
-+
-+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+					       BIT(TRIGGER_NETDEV_LINK)        |
-+					       BIT(TRIGGER_NETDEV_LINK_10)     |
-+					       BIT(TRIGGER_NETDEV_LINK_100)    |
-+					       BIT(TRIGGER_NETDEV_LINK_1000)   |
-+					       BIT(TRIGGER_NETDEV_LINK_2500)   |
-+					       BIT(TRIGGER_NETDEV_RX)          |
-+					       BIT(TRIGGER_NETDEV_TX));
-+
-+static int air_phy_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-+}
-+
-+static int air_phy_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-+}
-+
-+static int __air_buckpbus_reg_write(struct phy_device *phydev,
-+				    u32 pbus_address, u32 pbus_data)
-+{
-+	int ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW,  LOWORD(pbus_data));
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int air_buckpbus_reg_write(struct phy_device *phydev,
-+				  u32 pbus_address, u32 pbus_data)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   pbus_address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+;
-+}
-+
-+static int __air_buckpbus_reg_read(struct phy_device *phydev,
-+				   u32 pbus_address, u32 *pbus_data)
-+{
-+	int pbus_data_low, pbus_data_high;
-+	int ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW,  LOWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
-+	if (pbus_data_high < 0)
-+		return ret;
-+
-+	pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
-+	if (pbus_data_low < 0)
-+		return ret;
-+
-+	*pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
-+	return 0;
-+}
-+
-+static int air_buckpbus_reg_read(struct phy_device *phydev,
-+				 u32 pbus_address, u32 *pbus_data)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   pbus_address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int __air_write_buf(struct phy_device *phydev, u32 address,
-+			   const struct firmware *fw)
-+{
-+	unsigned int offset;
-+	int ret;
-+	u16 val;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(address));
-+	if (ret < 0)
-+		return ret;
-+
-+	for (offset = 0; offset < fw->size; offset += 4) {
-+		val = get_unaligned_le16(&fw->data[offset + 2]);
-+		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
-+		if (ret < 0)
-+			return ret;
-+
-+		val = get_unaligned_le16(&fw->data[offset]);
-+		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int air_write_buf(struct phy_device *phydev, u32 address,
-+			 const struct firmware *fw)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_write_buf(phydev, address, fw);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int en8811h_load_firmware(struct phy_device *phydev)
-+{
-+	struct device *dev = &phydev->mdio.dev;
-+	const struct firmware *fw1, *fw2;
-+	u32 pbus_value;
-+	int ret;
-+
-+	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_rel1;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_START);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+	pbus_value |= EN8811H_FW_CTRL_2_LOADING;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+	pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_FINISH);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = 0;
-+
-+en8811h_load_firmware_out:
-+	release_firmware(fw2);
-+
-+en8811h_load_firmware_rel1:
-+	release_firmware(fw1);
-+
-+	if (ret < 0)
-+		phydev_err(phydev, "Load firmware failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int en8811h_restart_host(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_START);
-+	if (ret < 0)
-+		return ret;
-+
-+	return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_FINISH);
-+}
-+
-+static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (on)
-+		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+					    &priv->led[index].state);
-+	else
-+		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+					       &priv->led[index].state);
-+
-+	changed |= (priv->led[index].rules != 0);
-+
-+	if (changed)
-+		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
-+				      AIR_PHY_LED_ON(index),
-+				      AIR_PHY_LED_ON_MASK,
-+				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
-+
-+	return 0;
-+}
-+
-+static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+				bool blinking)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (blinking)
-+		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+					    &priv->led[index].state);
-+	else
-+		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+					       &priv->led[index].state);
-+
-+	changed |= (priv->led[index].rules != 0);
-+
-+	if (changed)
-+		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
-+				     AIR_PHY_LED_BLINK(index),
-+				     blinking ?
-+				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
-+	else
-+		return 0;
-+}
-+
-+static int air_led_blink_set(struct phy_device *phydev, u8 index,
-+			     unsigned long *delay_on,
-+			     unsigned long *delay_off)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool blinking = false;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+		blinking = true;
-+		*delay_on = 50;
-+		*delay_off = 50;
-+	}
-+
-+	err = air_hw_led_blink_set(phydev, index, blinking);
-+	if (err)
-+		return err;
-+
-+	/* led-blink set, so switch led-on off */
-+	err = air_hw_led_on_set(phydev, index, false);
-+	if (err)
-+		return err;
-+
-+	/* hw-control is off*/
-+	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
-+		priv->led[index].rules = 0;
-+
-+	return 0;
-+}
-+
-+static int air_led_brightness_set(struct phy_device *phydev, u8 index,
-+				  enum led_brightness value)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	/* led-on set, so switch led-blink off */
-+	err = air_hw_led_blink_set(phydev, index, false);
-+	if (err)
-+		return err;
-+
-+	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
-+	if (err)
-+		return err;
-+
-+	/* hw-control is off */
-+	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
-+		priv->led[index].rules = 0;
-+
-+	return 0;
-+}
-+
-+static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
-+				  unsigned long *rules)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	*rules = priv->led[index].rules;
-+
-+	return 0;
-+};
-+
-+static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
-+				  unsigned long rules)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	u16 on = 0, blink = 0;
-+	int ret;
-+
-+	priv->led[index].rules = rules;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_10)   | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK10;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_10RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_10TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_100)  | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK100;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_100RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_100TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK1000;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_1000RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_1000TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK2500;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_2500RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_2500TX;
-+	}
-+
-+	if (on == 0) {
-+		if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+			blink |= AIR_PHY_LED_BLINK_10RX   |
-+				 AIR_PHY_LED_BLINK_100RX  |
-+				 AIR_PHY_LED_BLINK_1000RX |
-+				 AIR_PHY_LED_BLINK_2500RX;
-+		}
-+		if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+			blink |= AIR_PHY_LED_BLINK_10TX   |
-+				 AIR_PHY_LED_BLINK_100TX  |
-+				 AIR_PHY_LED_BLINK_1000TX |
-+				 AIR_PHY_LED_BLINK_2500TX;
-+		}
-+	}
-+
-+	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+		on |= AIR_PHY_LED_ON_FDX;
-+
-+	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+		on |= AIR_PHY_LED_ON_HDX;
-+
-+	if (blink || on) {
-+		/* switch hw-control on, so led-on and led-blink are off */
-+		clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
-+		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
-+	} else {
-+		priv->led[index].rules = 0;
-+	}
-+
-+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+			     AIR_PHY_LED_ON_MASK, on);
-+
-+	if (ret < 0)
-+		return ret;
-+
-+	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
-+			     blink);
-+};
-+
-+static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
-+{
-+	int cl45_data;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
-+	if (cl45_data < 0)
-+		return cl45_data;
-+
-+	if (state == AIR_LED_ENABLE)
-+		cl45_data |= AIR_PHY_LED_ON_ENABLE;
-+	else
-+		cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
-+
-+	if (pol == AIR_ACTIVE_HIGH)
-+		cl45_data |= AIR_PHY_LED_ON_POLARITY;
-+	else
-+		cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
-+
-+	err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+			    cl45_data);
-+	if (err < 0)
-+		return err;
-+
-+	return 0;
-+}
-+
-+static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	int cl45_data = dur;
-+	int ret, i;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
-+			    cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	cl45_data >>= 1;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
-+			    cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
-+	if (cl45_data < 0)
-+		return cl45_data;
-+
-+	switch (mode) {
-+	case AIR_LED_MODE_DISABLE:
-+		cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
-+		cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
-+		break;
-+	case AIR_LED_MODE_USER_DEFINE:
-+		cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
-+		cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
-+		break;
-+	default:
-+		phydev_err(phydev, "LED mode %d is not supported\n", mode);
-+		return -EINVAL;
-+	}
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	for (i = 0; i < num; ++i) {
-+		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
-+		if (ret < 0) {
-+			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
-+			return ret;
-+		}
-+		air_led_hw_control_set(phydev, i, priv->led[i].rules);
-+	}
-+
-+	return 0;
-+}
-+
-+static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+				       unsigned long rules)
-+{
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	/* All combinations of the supported triggers are allowed */
-+	if (rules & ~en8811h_led_trig)
-+		return -EOPNOTSUPP;
-+
-+	return 0;
-+};
-+
-+static int en8811h_probe(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv;
-+
-+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
-+			    GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
-+	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
-+	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
-+
-+	phydev->priv = priv;
-+
-+	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
-+	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-+
-+	return 0;
-+}
-+
-+static int en8811h_config_init(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	struct device *dev = &phydev->mdio.dev;
-+	int ret, pollret, reg_value;
-+	u32 pbus_value;
-+
-+	if (!priv->firmware_version)
-+		ret = en8811h_load_firmware(phydev);
-+	else
-+		ret = en8811h_restart_host(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Because of mdio-lock, may have to wait for multiple loads */
-+	pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+					    EN8811H_PHY_FW_STATUS, reg_value,
-+					    reg_value == EN8811H_PHY_READY,
-+					    20000, 7500000, true);
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (pollret || !pbus_value) {
-+		phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
-+		return -ENODEV;
-+	}
-+
-+	if (!priv->firmware_version) {
-+		phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
-+		priv->firmware_version = pbus_value;
-+	}
-+
-+	/* Select mode 1, the only mode supported */
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
-+			    AIR_PHY_HOST_CMD_1_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
-+			    AIR_PHY_HOST_CMD_2_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+			    AIR_PHY_HOST_CMD_3_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+			    AIR_PHY_HOST_CMD_4_MODE1);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Serdes polarity */
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
-+		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
-+	else
-+		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
-+	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
-+		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
-+	else
-+		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
-+			    AIR_LED_MODE_USER_DEFINE);
-+	if (ret < 0) {
-+		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	pbus_value |= EN8811H_GPIO_OUTPUT_345;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int en8811h_get_features(struct phy_device *phydev)
-+{
-+	linkmode_set_bit_array(phy_basic_ports_array,
-+			       ARRAY_SIZE(phy_basic_ports_array),
-+			       phydev->supported);
-+
-+	return genphy_c45_pma_read_abilities(phydev);
-+}
-+
-+static int en8811h_get_rate_matching(struct phy_device *phydev,
-+				     phy_interface_t iface)
-+{
-+	return RATE_MATCH_PAUSE;
-+}
-+
-+static int en8811h_config_aneg(struct phy_device *phydev)
-+{
-+	bool changed = false;
-+	int err, val;
-+
-+	val = 0;
-+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+			      phydev->advertising))
-+		val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
-+	err =  phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-+				      MDIO_AN_10GBT_CTRL_ADV2_5G, val);
-+	if (err < 0)
-+		return err;
-+	if (err > 0)
-+		changed = true;
-+
-+	return __genphy_config_aneg(phydev, changed);
-+}
-+
-+static int en8811h_read_status(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	u32 pbus_value;
-+	int ret, val;
-+
-+	ret = genphy_update_link(phydev);
-+	if (ret)
-+		return ret;
-+
-+	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
-+	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
-+	phydev->speed = SPEED_UNKNOWN;
-+	phydev->duplex = DUPLEX_UNKNOWN;
-+	phydev->pause = 0;
-+	phydev->asym_pause = 0;
-+
-+	ret = genphy_read_master_slave(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = genphy_read_lpa(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Get link partner 2.5GBASE-T ability from vendor register */
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+			 phydev->lp_advertising,
-+			 pbus_value & EN8811H_2P5G_LPA_2P5G);
-+
-+	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
-+		phy_resolve_aneg_pause(phydev);
-+
-+	if (!phydev->link)
-+		return 0;
-+
-+	/* Get real speed from vendor register */
-+	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
-+	if (val < 0)
-+		return val;
-+	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
-+	case AIR_AUX_CTRL_STATUS_SPEED_2500:
-+		phydev->speed = SPEED_2500;
-+		break;
-+	case AIR_AUX_CTRL_STATUS_SPEED_1000:
-+		phydev->speed = SPEED_1000;
-+		break;
-+	case AIR_AUX_CTRL_STATUS_SPEED_100:
-+		phydev->speed = SPEED_100;
-+		break;
-+	}
-+
-+	/* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
-+	 * Firmware before version 24011202 has no vendor register 2P5G_LPA.
-+	 * Assume link partner advertised it if connected at 2500Mbps.
-+	 */
-+	if (priv->firmware_version < 0x24011202) {
-+		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+				 phydev->lp_advertising,
-+				 phydev->speed == SPEED_2500);
-+	}
-+
-+	/* Only supports full duplex */
-+	phydev->duplex = DUPLEX_FULL;
-+
-+	return 0;
-+}
-+
-+static int en8811h_clear_intr(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+			    AIR_PHY_HOST_CMD_3_DOCMD);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+			    AIR_PHY_HOST_CMD_4_INTCLR);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = en8811h_clear_intr(phydev);
-+	if (ret < 0) {
-+		phy_error(phydev);
-+		return IRQ_NONE;
-+	}
-+
-+	phy_trigger_machine(phydev);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static struct phy_driver en8811h_driver[] = {
-+{
-+	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
-+	.name			= "Airoha EN8811H",
-+	.probe			= en8811h_probe,
-+	.get_features		= en8811h_get_features,
-+	.config_init		= en8811h_config_init,
-+	.get_rate_matching	= en8811h_get_rate_matching,
-+	.config_aneg		= en8811h_config_aneg,
-+	.read_status		= en8811h_read_status,
-+	.config_intr		= en8811h_clear_intr,
-+	.handle_interrupt	= en8811h_handle_interrupt,
-+	.led_hw_is_supported	= en8811h_led_hw_is_supported,
-+	.read_page		= air_phy_read_page,
-+	.write_page		= air_phy_write_page,
-+	.led_blink_set		= air_led_blink_set,
-+	.led_brightness_set	= air_led_brightness_set,
-+	.led_hw_control_set	= air_led_hw_control_set,
-+	.led_hw_control_get	= air_led_hw_control_get,
-+} };
-+
-+module_phy_driver(en8811h_driver);
-+
-+static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
-+	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
-+MODULE_FIRMWARE(EN8811H_MD32_DM);
-+MODULE_FIRMWARE(EN8811H_MD32_DSP);
-+
-+MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
-+MODULE_AUTHOR("Airoha");
-+MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
index 2df5e6b28c..6ccc3eb389 100644
--- a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /**
   *	napi_disable - prevent NAPI from scheduling
-@@ -3152,6 +3153,7 @@ struct softnet_data {
+@@ -3150,6 +3151,7 @@ struct softnet_data {
  	unsigned int		processed;
  	unsigned int		time_squeeze;
  	unsigned int		received_rps;
@@ -157,7 +157,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
  			   int (*poll)(struct napi_struct *, int), int weight)
  {
-@@ -11171,6 +11242,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11126,6 +11197,9 @@ static int dev_cpu_dead(unsigned int old
  	raise_softirq_irqoff(NET_TX_SOFTIRQ);
  	local_irq_enable();
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11483,6 +11557,7 @@ static int __init net_dev_init(void)
+@@ -11438,6 +11512,7 @@ static int __init net_dev_init(void)
  		INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
  		spin_lock_init(&sd->defer_lock);
  
@@ -177,15 +177,15 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		sd->backlog.weight = weight_p;
 --- a/net/core/sysctl_net_core.c
 +++ b/net/core/sysctl_net_core.c
-@@ -29,6 +29,7 @@ static int int_3600 = 3600;
- static int min_sndbuf = SOCK_MIN_SNDBUF;
+@@ -30,6 +30,7 @@ static int min_sndbuf = SOCK_MIN_SNDBUF;
  static int min_rcvbuf = SOCK_MIN_RCVBUF;
  static int max_skb_frags = MAX_SKB_FRAGS;
+ static int min_mem_pcpu_rsv = SK_MEMORY_PCPU_RESERVE;
 +static int backlog_threaded;
  
  static int net_msg_warn;	/* Unused, but still a sysctl */
  
-@@ -112,6 +113,23 @@ static int rps_sock_flow_sysctl(struct c
+@@ -113,6 +114,23 @@ static int rps_sock_flow_sysctl(struct c
  }
  #endif /* CONFIG_RPS */
  
@@ -209,7 +209,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_NET_FLOW_LIMIT
  static DEFINE_MUTEX(flow_limit_update_mutex);
  
-@@ -473,6 +491,15 @@ static struct ctl_table net_core_table[]
+@@ -482,6 +500,15 @@ static struct ctl_table net_core_table[]
  		.proc_handler	= rps_sock_flow_sysctl
  	},
  #endif
diff --git a/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
index 9556c90b57..1d4b18653e 100644
--- a/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
+++ b/target/linux/generic/pending-6.1/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
@@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -7025,6 +7025,7 @@ static int mv88e6xxx_register_switch(str
+@@ -7037,6 +7037,7 @@ static int mv88e6xxx_register_switch(str
  	ds->ops = &mv88e6xxx_switch_ops;
  	ds->ageing_time_min = chip->info->age_time_coeff;
  	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
diff --git a/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch b/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch
deleted file mode 100644
index a2c0edcbbf..0000000000
--- a/target/linux/generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4a44a52f16ccd3d03e0cb5fb437a5eb31a5f9f05 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Mon, 26 Feb 2024 21:39:34 +0100
-Subject: [PATCH] net l2tp: drop flow hash on forward
-
-Drop the flow-hash of the skb when forwarding to the L2TP netdev.
-
-This avoids the L2TP qdisc from using the flow-hash from the outer
-packet, which is identical for every flow within the tunnel.
-
-This does not affect every platform but is specific for the ethernet
-driver. It depends on the platform including L4 information in the
-flow-hash.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- net/l2tp/l2tp_eth.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/net/l2tp/l2tp_eth.c
-+++ b/net/l2tp/l2tp_eth.c
-@@ -136,6 +136,9 @@ static void l2tp_eth_dev_recv(struct l2t
- 	/* checksums verified by L2TP */
- 	skb->ip_summed = CHECKSUM_NONE;
- 
-+	/* drop outer flow-hash */
-+	skb_clear_hash(skb);
-+
- 	skb_dst_drop(skb);
- 	nf_reset_ct(skb);
- 
diff --git a/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
deleted file mode 100644
index 3cbd62e929..0000000000
--- a/target/linux/generic/pending-6.1/795-02-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch
+++ /dev/null
@@ -1,200 +0,0 @@
-From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:09 +0300
-Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
-MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
-for MT7530 only. Add MT7530 prefix to the definition for bit 15.
-
-Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
-
-Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
-follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
-"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
-Generation Router Platform: Datasheet (Open Version) v0.1" documents.
-
-These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
-with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
-
-Remove PMCR_SPEED_MASK which doesn't have a use.
-
-Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
-end for the mask that includes all force mode definitions.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 24 ++++++++---------
- drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
- 2 files changed, 42 insertions(+), 40 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds
- 		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
- 
- 		/* Setup the MAC by default for the cpu port */
--		mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
-+		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
- 		break;
- 	case P5_INTF_SEL_GMAC5:
- 		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
-@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds)
- 		/* Clear link settings and enable force mode to force link down
- 		 * on all ports until they're enabled later.
- 		 */
--		mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
--			   PMCR_FORCE_MODE, PMCR_FORCE_MODE);
-+		mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
-+			   MT7530_FORCE_MODE, MT7530_FORCE_MODE);
- 
- 		/* Disable forwarding by default on all ports */
- 		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d
- 		/* Clear link settings and enable force mode to force link down
- 		 * on all ports until they're enabled later.
- 		 */
--		mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
--			   MT7531_FORCE_MODE, MT7531_FORCE_MODE);
-+		mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
-+			   MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
- 
- 		/* Disable forwarding by default on all ports */
- 		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds)
- 
- 	/* Force link down on all ports before internal reset */
- 	for (i = 0; i < MT7530_NUM_PORTS; i++)
--		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-+		mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
- 
- 	/* Reset the switch through internal reset */
- 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
-@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink
- 
- 	/* Are we connected to external phy */
- 	if (port == 5 && dsa_is_user_port(ds, 5))
--		mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
-+		mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
- }
- 
- static void mt753x_phylink_mac_link_down(struct phylink_config *config,
-@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down
- 	struct dsa_port *dp = dsa_phylink_to_port(config);
- 	struct mt7530_priv *priv = dp->ds->priv;
- 
--	mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
-+	mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
- }
- 
- static void mt753x_phylink_mac_link_up(struct phylink_config *config,
-@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s
- 	struct mt7530_priv *priv = dp->ds->priv;
- 	u32 mcr;
- 
--	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
-+	mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
- 
- 	switch (speed) {
- 	case SPEED_1000:
-@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s
- 	if (duplex == DUPLEX_FULL) {
- 		mcr |= PMCR_FORCE_FDX;
- 		if (tx_pause)
--			mcr |= PMCR_TX_FC_EN;
-+			mcr |= PMCR_FORCE_TX_FC_EN;
- 		if (rx_pause)
--			mcr |= PMCR_RX_FC_EN;
-+			mcr |= PMCR_FORCE_RX_FC_EN;
- 	}
- 
- 	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
-@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s
- 		}
- 	}
- 
--	mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
-+	mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
- }
- 
- static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
- #define  G0_PORT_VID_DEF		G0_PORT_VID(0)
- 
- /* Register for port MAC control register */
--#define MT7530_PMCR_P(x)		(0x3000 + ((x) * 0x100))
--#define  PMCR_IFG_XMIT(x)		(((x) & 0x3) << 18)
-+#define MT753X_PMCR_P(x)		(0x3000 + ((x) * 0x100))
-+#define  PMCR_IFG_XMIT_MASK		GENMASK(19, 18)
-+#define  PMCR_IFG_XMIT(x)		FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
- #define  PMCR_EXT_PHY			BIT(17)
- #define  PMCR_MAC_MODE			BIT(16)
--#define  PMCR_FORCE_MODE		BIT(15)
--#define  PMCR_TX_EN			BIT(14)
--#define  PMCR_RX_EN			BIT(13)
-+#define  MT7530_FORCE_MODE		BIT(15)
-+#define  PMCR_MAC_TX_EN			BIT(14)
-+#define  PMCR_MAC_RX_EN			BIT(13)
- #define  PMCR_BACKOFF_EN		BIT(9)
- #define  PMCR_BACKPR_EN			BIT(8)
- #define  PMCR_FORCE_EEE1G		BIT(7)
- #define  PMCR_FORCE_EEE100		BIT(6)
--#define  PMCR_TX_FC_EN			BIT(5)
--#define  PMCR_RX_FC_EN			BIT(4)
-+#define  PMCR_FORCE_RX_FC_EN		BIT(5)
-+#define  PMCR_FORCE_TX_FC_EN		BIT(4)
- #define  PMCR_FORCE_SPEED_1000		BIT(3)
- #define  PMCR_FORCE_SPEED_100		BIT(2)
- #define  PMCR_FORCE_FDX			BIT(1)
- #define  PMCR_FORCE_LNK			BIT(0)
--#define  PMCR_SPEED_MASK		(PMCR_FORCE_SPEED_100 | \
--					 PMCR_FORCE_SPEED_1000)
--#define  MT7531_FORCE_LNK		BIT(31)
--#define  MT7531_FORCE_SPD		BIT(30)
--#define  MT7531_FORCE_DPX		BIT(29)
--#define  MT7531_FORCE_RX_FC		BIT(28)
--#define  MT7531_FORCE_TX_FC		BIT(27)
--#define  MT7531_FORCE_EEE100		BIT(26)
--#define  MT7531_FORCE_EEE1G		BIT(25)
--#define  MT7531_FORCE_MODE		(MT7531_FORCE_LNK | \
--					 MT7531_FORCE_SPD | \
--					 MT7531_FORCE_DPX | \
--					 MT7531_FORCE_RX_FC | \
--					 MT7531_FORCE_TX_FC | \
--					 MT7531_FORCE_EEE100 | \
--					 MT7531_FORCE_EEE1G)
--#define  PMCR_LINK_SETTINGS_MASK	(PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
--					 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
--					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--					 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
--					 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
-+#define  MT7531_FORCE_MODE_LNK		BIT(31)
-+#define  MT7531_FORCE_MODE_SPD		BIT(30)
-+#define  MT7531_FORCE_MODE_DPX		BIT(29)
-+#define  MT7531_FORCE_MODE_RX_FC	BIT(28)
-+#define  MT7531_FORCE_MODE_TX_FC	BIT(27)
-+#define  MT7531_FORCE_MODE_EEE100	BIT(26)
-+#define  MT7531_FORCE_MODE_EEE1G	BIT(25)
-+#define  MT7531_FORCE_MODE_MASK		(MT7531_FORCE_MODE_LNK | \
-+					 MT7531_FORCE_MODE_SPD | \
-+					 MT7531_FORCE_MODE_DPX | \
-+					 MT7531_FORCE_MODE_RX_FC | \
-+					 MT7531_FORCE_MODE_TX_FC | \
-+					 MT7531_FORCE_MODE_EEE100 | \
-+					 MT7531_FORCE_MODE_EEE1G)
-+#define  PMCR_LINK_SETTINGS_MASK	(PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
-+					 PMCR_FORCE_EEE1G | \
-+					 PMCR_FORCE_EEE100 | \
-+					 PMCR_FORCE_RX_FC_EN | \
-+					 PMCR_FORCE_TX_FC_EN | \
-+					 PMCR_FORCE_SPEED_1000 | \
-+					 PMCR_FORCE_SPEED_100 | \
-+					 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
- 
- #define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
- #define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
diff --git a/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
deleted file mode 100644
index 9697e7eb4f..0000000000
--- a/target/linux/generic/pending-6.1/795-03-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch
+++ /dev/null
@@ -1,185 +0,0 @@
-From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:10 +0300
-Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
- MT7530 switch
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The p5_intf_sel pointer is used to store the information of whether PHY
-muxing is used or not. PHY muxing is a feature specific to port 5 of the
-MT7530 switch. Do not use it for other switch models.
-
-Rename the pointer to p5_mode to store the mode the port is being used in.
-Rename the p5_interface_select enum to mt7530_p5_mode, the string
-representation to mt7530_p5_mode_str, and the enum elements.
-
-If PHY muxing is not detected, the default mode, GMAC5, will be used.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
- drivers/net/dsa/mt7530.h | 15 +++++-----
- 2 files changed, 33 insertions(+), 44 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -850,19 +850,15 @@ mt7530_set_ageing_time(struct dsa_switch
- 	return 0;
- }
- 
--static const char *p5_intf_modes(unsigned int p5_interface)
-+static const char *mt7530_p5_mode_str(unsigned int mode)
- {
--	switch (p5_interface) {
--	case P5_DISABLED:
--		return "DISABLED";
--	case P5_INTF_SEL_PHY_P0:
--		return "PHY P0";
--	case P5_INTF_SEL_PHY_P4:
--		return "PHY P4";
--	case P5_INTF_SEL_GMAC5:
--		return "GMAC5";
-+	switch (mode) {
-+	case MUX_PHY_P0:
-+		return "MUX PHY P0";
-+	case MUX_PHY_P4:
-+		return "MUX PHY P4";
- 	default:
--		return "unknown";
-+		return "GMAC5";
- 	}
- }
- 
-@@ -879,23 +875,23 @@ static void mt7530_setup_port5(struct ds
- 	val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
- 	val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
- 
--	switch (priv->p5_intf_sel) {
--	case P5_INTF_SEL_PHY_P0:
--		/* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
-+	switch (priv->p5_mode) {
-+	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
-+	case MUX_PHY_P0:
- 		val |= MHWTRAP_PHY0_SEL;
- 		fallthrough;
--	case P5_INTF_SEL_PHY_P4:
--		/* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
-+
-+	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
-+	case MUX_PHY_P4:
- 		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
- 
- 		/* Setup the MAC by default for the cpu port */
- 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
- 		break;
--	case P5_INTF_SEL_GMAC5:
--		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
--		val &= ~MHWTRAP_P5_DIS;
--		break;
-+
-+	/* GMAC5: P5 -> SoC MAC or external PHY */
- 	default:
-+		val &= ~MHWTRAP_P5_DIS;
- 		break;
- 	}
- 
-@@ -923,8 +919,8 @@ static void mt7530_setup_port5(struct ds
- 
- 	mt7530_write(priv, MT7530_MHWTRAP, val);
- 
--	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
--		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
-+	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
-+		mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
- 
- 	mutex_unlock(&priv->reg_mutex);
- }
-@@ -2467,13 +2463,11 @@ mt7530_setup(struct dsa_switch *ds)
- 	if (ret)
- 		return ret;
- 
--	/* Setup port 5 */
--	if (!dsa_is_unused_port(ds, 5)) {
--		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
--	} else {
-+	/* Check for PHY muxing on port 5 */
-+	if (dsa_is_unused_port(ds, 5)) {
- 		/* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
--		 * Set priv->p5_intf_sel to the appropriate value if PHY muxing
--		 * is detected.
-+		 * Set priv->p5_mode to the appropriate value if PHY muxing is
-+		 * detected.
- 		 */
- 		for_each_child_of_node(dn, mac_np) {
- 			if (!of_device_is_compatible(mac_np,
-@@ -2497,17 +2491,16 @@ mt7530_setup(struct dsa_switch *ds)
- 				}
- 				id = of_mdio_parse_addr(ds->dev, phy_node);
- 				if (id == 0)
--					priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
-+					priv->p5_mode = MUX_PHY_P0;
- 				if (id == 4)
--					priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
-+					priv->p5_mode = MUX_PHY_P4;
- 			}
- 			of_node_put(mac_np);
- 			of_node_put(phy_node);
- 			break;
- 		}
- 
--		if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
--		    priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
-+		if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
- 			mt7530_setup_port5(ds, interface);
- 	}
- 
-@@ -2645,9 +2638,6 @@ mt7531_setup(struct dsa_switch *ds)
- 			   MT7531_EXT_P_MDIO_12);
- 	}
- 
--	if (!dsa_is_unused_port(ds, 5))
--		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
--
- 	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- 		   MT7531_GPIO0_INTERRUPT);
- 
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -708,12 +708,11 @@ struct mt7530_port {
- 	struct phylink_pcs *sgmii_pcs;
- };
- 
--/* Port 5 interface select definitions */
--enum p5_interface_select {
--	P5_DISABLED,
--	P5_INTF_SEL_PHY_P0,
--	P5_INTF_SEL_PHY_P4,
--	P5_INTF_SEL_GMAC5,
-+/* Port 5 mode definitions of the MT7530 switch */
-+enum mt7530_p5_mode {
-+	GMAC5,
-+	MUX_PHY_P0,
-+	MUX_PHY_P4,
- };
- 
- struct mt7530_priv;
-@@ -769,7 +768,7 @@ struct mt753x_info {
-  * @ports:		Holding the state among ports
-  * @reg_mutex:		The lock for protecting among process accessing
-  *			registers
-- * @p5_intf_sel:	Holding the current port 5 interface select
-+ * @p5_mode:		Holding the current mode of port 5 of the MT7530 switch
-  * @p5_sgmii:		Flag for distinguishing if port 5 of the MT7531 switch
-  *			has got SGMII
-  * @irq:		IRQ number of the switch
-@@ -791,7 +790,7 @@ struct mt7530_priv {
- 	const struct mt753x_info *info;
- 	unsigned int		id;
- 	bool			mcm;
--	enum p5_interface_select p5_intf_sel;
-+	enum mt7530_p5_mode	p5_mode;
- 	bool			p5_sgmii;
- 	u8			mirror_rx;
- 	u8			mirror_tx;
diff --git a/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
deleted file mode 100644
index 77a2df8586..0000000000
--- a/target/linux/generic/pending-6.1/795-04-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch
+++ /dev/null
@@ -1,169 +0,0 @@
-From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:11 +0300
-Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
- mt753x_to_cpu_fw
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The mt753x_bpdu_port_fw enum is globally used for manipulating the process
-of deciding the forwardable ports, specifically concerning the CPU port(s).
-Therefore, rename it and the values in it to mt753x_to_cpu_fw.
-
-Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
- drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
- 2 files changed, 56 insertions(+), 64 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p
- 	 * VLAN-untagged.
- 	 */
- 	mt7530_rmw(priv, MT753X_BPC,
--		   MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
--			   MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
--			   MT753X_BPDU_PORT_FW_MASK,
--		   MT753X_PAE_BPDU_FR |
--			   MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--			   MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_BPDU_CPU_ONLY);
-+		   PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
-+			   BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
-+		   PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
-+			   BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   TO_CPU_FW_CPU_ONLY);
- 
- 	/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
- 	 * them VLAN-untagged.
- 	 */
- 	mt7530_rmw(priv, MT753X_RGAC1,
--		   MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
--			   MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
--			   MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
--		   MT753X_R02_BPDU_FR |
--			   MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--			   MT753X_R01_BPDU_FR |
--			   MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_BPDU_CPU_ONLY);
-+		   R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
-+			   R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
-+		   R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
-+			   R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   TO_CPU_FW_CPU_ONLY);
- 
- 	/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
- 	 * them VLAN-untagged.
- 	 */
- 	mt7530_rmw(priv, MT753X_RGAC2,
--		   MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
--			   MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
--			   MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
--		   MT753X_R0E_BPDU_FR |
--			   MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
--			   MT753X_R03_BPDU_FR |
--			   MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
--			   MT753X_BPDU_CPU_ONLY);
-+		   R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
-+			   R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
-+		   R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
-+			   R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+			   TO_CPU_FW_CPU_ONLY);
- }
- 
- static void
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -67,47 +67,47 @@ enum mt753x_id {
- #define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
- 					 MT7531_MIRROR_MASK : MIRROR_MASK)
- 
--/* Registers for BPDU and PAE frame control*/
-+/* Register for BPDU and PAE frame control */
- #define MT753X_BPC			0x24
--#define  MT753X_PAE_BPDU_FR		BIT(25)
--#define  MT753X_PAE_EG_TAG_MASK		GENMASK(24, 22)
--#define  MT753X_PAE_EG_TAG(x)		FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
--#define  MT753X_PAE_PORT_FW_MASK	GENMASK(18, 16)
--#define  MT753X_PAE_PORT_FW(x)		FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
--#define  MT753X_BPDU_EG_TAG_MASK	GENMASK(8, 6)
--#define  MT753X_BPDU_EG_TAG(x)		FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
--#define  MT753X_BPDU_PORT_FW_MASK	GENMASK(2, 0)
-+#define  PAE_BPDU_FR			BIT(25)
-+#define  PAE_EG_TAG_MASK		GENMASK(24, 22)
-+#define  PAE_EG_TAG(x)			FIELD_PREP(PAE_EG_TAG_MASK, x)
-+#define  PAE_PORT_FW_MASK		GENMASK(18, 16)
-+#define  PAE_PORT_FW(x)			FIELD_PREP(PAE_PORT_FW_MASK, x)
-+#define  BPDU_EG_TAG_MASK		GENMASK(8, 6)
-+#define  BPDU_EG_TAG(x)			FIELD_PREP(BPDU_EG_TAG_MASK, x)
-+#define  BPDU_PORT_FW_MASK		GENMASK(2, 0)
- 
--/* Register for :01 and :02 MAC DA frame control */
-+/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
- #define MT753X_RGAC1			0x28
--#define  MT753X_R02_BPDU_FR		BIT(25)
--#define  MT753X_R02_EG_TAG_MASK		GENMASK(24, 22)
--#define  MT753X_R02_EG_TAG(x)		FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
--#define  MT753X_R02_PORT_FW_MASK	GENMASK(18, 16)
--#define  MT753X_R02_PORT_FW(x)		FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
--#define  MT753X_R01_BPDU_FR		BIT(9)
--#define  MT753X_R01_EG_TAG_MASK		GENMASK(8, 6)
--#define  MT753X_R01_EG_TAG(x)		FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
--#define  MT753X_R01_PORT_FW_MASK	GENMASK(2, 0)
-+#define  R02_BPDU_FR			BIT(25)
-+#define  R02_EG_TAG_MASK		GENMASK(24, 22)
-+#define  R02_EG_TAG(x)			FIELD_PREP(R02_EG_TAG_MASK, x)
-+#define  R02_PORT_FW_MASK		GENMASK(18, 16)
-+#define  R02_PORT_FW(x)			FIELD_PREP(R02_PORT_FW_MASK, x)
-+#define  R01_BPDU_FR			BIT(9)
-+#define  R01_EG_TAG_MASK		GENMASK(8, 6)
-+#define  R01_EG_TAG(x)			FIELD_PREP(R01_EG_TAG_MASK, x)
-+#define  R01_PORT_FW_MASK		GENMASK(2, 0)
- 
--/* Register for :03 and :0E MAC DA frame control */
-+/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
- #define MT753X_RGAC2			0x2c
--#define  MT753X_R0E_BPDU_FR		BIT(25)
--#define  MT753X_R0E_EG_TAG_MASK		GENMASK(24, 22)
--#define  MT753X_R0E_EG_TAG(x)		FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
--#define  MT753X_R0E_PORT_FW_MASK	GENMASK(18, 16)
--#define  MT753X_R0E_PORT_FW(x)		FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
--#define  MT753X_R03_BPDU_FR		BIT(9)
--#define  MT753X_R03_EG_TAG_MASK		GENMASK(8, 6)
--#define  MT753X_R03_EG_TAG(x)		FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
--#define  MT753X_R03_PORT_FW_MASK	GENMASK(2, 0)
-+#define  R0E_BPDU_FR			BIT(25)
-+#define  R0E_EG_TAG_MASK		GENMASK(24, 22)
-+#define  R0E_EG_TAG(x)			FIELD_PREP(R0E_EG_TAG_MASK, x)
-+#define  R0E_PORT_FW_MASK		GENMASK(18, 16)
-+#define  R0E_PORT_FW(x)			FIELD_PREP(R0E_PORT_FW_MASK, x)
-+#define  R03_BPDU_FR			BIT(9)
-+#define  R03_EG_TAG_MASK		GENMASK(8, 6)
-+#define  R03_EG_TAG(x)			FIELD_PREP(R03_EG_TAG_MASK, x)
-+#define  R03_PORT_FW_MASK		GENMASK(2, 0)
- 
--enum mt753x_bpdu_port_fw {
--	MT753X_BPDU_FOLLOW_MFC,
--	MT753X_BPDU_CPU_EXCLUDE = 4,
--	MT753X_BPDU_CPU_INCLUDE = 5,
--	MT753X_BPDU_CPU_ONLY = 6,
--	MT753X_BPDU_DROP = 7,
-+enum mt753x_to_cpu_fw {
-+	TO_CPU_FW_SYSTEM_DEFAULT,
-+	TO_CPU_FW_CPU_EXCLUDE = 4,
-+	TO_CPU_FW_CPU_INCLUDE = 5,
-+	TO_CPU_FW_CPU_ONLY = 6,
-+	TO_CPU_FW_DROP = 7,
- };
- 
- /* Registers for address table access */
diff --git a/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
deleted file mode 100644
index 95cdfac02e..0000000000
--- a/target/linux/generic/pending-6.1/795-05-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:12 +0300
-Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
- add MT7531_QRY_FFP
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
-SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
-MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
-IGMP/MLD Query Frame Flooding Ports mask for MT7531.
-
-Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
-
-Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
-macros.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 38 ++++++++--------------
- drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
- 2 files changed, 57 insertions(+), 50 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1140,7 +1140,7 @@ mt753x_cpu_port_enable(struct dsa_switch
- 		     PORT_SPEC_TAG);
- 
- 	/* Enable flooding on the CPU port */
--	mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
-+	mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
- 		   UNU_FFP(BIT(port)));
- 
- 	/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
-@@ -1304,15 +1304,15 @@ mt7530_port_bridge_flags(struct dsa_swit
- 			   flags.val & BR_LEARNING ? 0 : SA_DIS);
- 
- 	if (flags.mask & BR_FLOOD)
--		mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
-+		mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
- 			   flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
- 
- 	if (flags.mask & BR_MCAST_FLOOD)
--		mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
-+		mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
- 			   flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
- 
- 	if (flags.mask & BR_BCAST_FLOOD)
--		mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
-+		mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
- 			   flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
- 
- 	return 0;
-@@ -1848,20 +1848,6 @@ mt7530_port_vlan_del(struct dsa_switch *
- 	return 0;
- }
- 
--static int mt753x_mirror_port_get(unsigned int id, u32 val)
--{
--	return (id == ID_MT7531 || id == ID_MT7988) ?
--		       MT7531_MIRROR_PORT_GET(val) :
--		       MIRROR_PORT(val);
--}
--
--static int mt753x_mirror_port_set(unsigned int id, u32 val)
--{
--	return (id == ID_MT7531 || id == ID_MT7988) ?
--		       MT7531_MIRROR_PORT_SET(val) :
--		       MIRROR_PORT(val);
--}
--
- static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
- 				  struct dsa_mall_mirror_tc_entry *mirror,
- 				  bool ingress, struct netlink_ext_ack *extack)
-@@ -1877,14 +1863,14 @@ static int mt753x_port_mirror_add(struct
- 	val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
- 
- 	/* MT7530 only supports one monitor port */
--	monitor_port = mt753x_mirror_port_get(priv->id, val);
-+	monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
- 	if (val & MT753X_MIRROR_EN(priv->id) &&
- 	    monitor_port != mirror->to_local_port)
- 		return -EEXIST;
- 
- 	val |= MT753X_MIRROR_EN(priv->id);
--	val &= ~MT753X_MIRROR_MASK(priv->id);
--	val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
-+	val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
-+	val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
- 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
- 
- 	val = mt7530_read(priv, MT7530_PCR_P(port));
-@@ -2524,7 +2510,7 @@ mt7531_setup_common(struct dsa_switch *d
- 	mt7530_mib_reset(ds);
- 
- 	/* Disable flooding on all ports */
--	mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
-+	mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
- 		     UNU_FFP_MASK);
- 
- 	for (i = 0; i < MT7530_NUM_PORTS; i++) {
-@@ -3086,10 +3072,12 @@ mt753x_conduit_state_change(struct dsa_s
- 	else
- 		priv->active_cpu_ports &= ~mask;
- 
--	if (priv->active_cpu_ports)
--		val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
-+	if (priv->active_cpu_ports) {
-+		val = MT7530_CPU_EN |
-+		      MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
-+	}
- 
--	mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
-+	mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
- }
- 
- static int mt7988_setup(struct dsa_switch *ds)
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -36,36 +36,55 @@ enum mt753x_id {
- #define MT753X_AGC			0xc
- #define  LOCAL_EN			BIT(7)
- 
--/* Registers to mac forward control for unknown frames */
--#define MT7530_MFC			0x10
--#define  BC_FFP(x)			(((x) & 0xff) << 24)
--#define  BC_FFP_MASK			BC_FFP(~0)
--#define  UNM_FFP(x)			(((x) & 0xff) << 16)
--#define  UNM_FFP_MASK			UNM_FFP(~0)
--#define  UNU_FFP(x)			(((x) & 0xff) << 8)
--#define  UNU_FFP_MASK			UNU_FFP(~0)
--#define  CPU_EN				BIT(7)
--#define  CPU_PORT_MASK			GENMASK(6, 4)
--#define  CPU_PORT(x)			FIELD_PREP(CPU_PORT_MASK, x)
--#define  MIRROR_EN			BIT(3)
--#define  MIRROR_PORT(x)			((x) & 0x7)
--#define  MIRROR_MASK			0x7
-+/* Register for MAC forward control */
-+#define MT753X_MFC			0x10
-+#define  BC_FFP_MASK			GENMASK(31, 24)
-+#define  BC_FFP(x)			FIELD_PREP(BC_FFP_MASK, x)
-+#define  UNM_FFP_MASK			GENMASK(23, 16)
-+#define  UNM_FFP(x)			FIELD_PREP(UNM_FFP_MASK, x)
-+#define  UNU_FFP_MASK			GENMASK(15, 8)
-+#define  UNU_FFP(x)			FIELD_PREP(UNU_FFP_MASK, x)
-+#define  MT7530_CPU_EN			BIT(7)
-+#define  MT7530_CPU_PORT_MASK		GENMASK(6, 4)
-+#define  MT7530_CPU_PORT(x)		FIELD_PREP(MT7530_CPU_PORT_MASK, x)
-+#define  MT7530_MIRROR_EN		BIT(3)
-+#define  MT7530_MIRROR_PORT_MASK	GENMASK(2, 0)
-+#define  MT7530_MIRROR_PORT_GET(x)	FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
-+#define  MT7530_MIRROR_PORT_SET(x)	FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
-+#define  MT7531_QRY_FFP_MASK		GENMASK(7, 0)
-+#define  MT7531_QRY_FFP(x)		FIELD_PREP(MT7531_QRY_FFP_MASK, x)
- 
--/* Registers for CPU forward control */
-+/* Register for CPU forward control */
- #define MT7531_CFC			0x4
- #define  MT7531_MIRROR_EN		BIT(19)
--#define  MT7531_MIRROR_MASK		(MIRROR_MASK << 16)
--#define  MT7531_MIRROR_PORT_GET(x)	(((x) >> 16) & MIRROR_MASK)
--#define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
-+#define  MT7531_MIRROR_PORT_MASK	GENMASK(18, 16)
-+#define  MT7531_MIRROR_PORT_GET(x)	FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
-+#define  MT7531_MIRROR_PORT_SET(x)	FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
- #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
- #define  MT7531_CPU_PMAP(x)		FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
- 
--#define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
--					 MT7531_CFC : MT7530_MFC)
--#define MT753X_MIRROR_EN(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
--					 MT7531_MIRROR_EN : MIRROR_EN)
--#define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
--					 MT7531_MIRROR_MASK : MIRROR_MASK)
-+#define MT753X_MIRROR_REG(id)		((id == ID_MT7531 || \
-+					  id == ID_MT7988) ? \
-+					 MT7531_CFC : MT753X_MFC)
-+
-+#define MT753X_MIRROR_EN(id)		((id == ID_MT7531 || \
-+					  id == ID_MT7988) ? \
-+					 MT7531_MIRROR_EN : MT7530_MIRROR_EN)
-+
-+#define MT753X_MIRROR_PORT_MASK(id)	((id == ID_MT7531 || \
-+					  id == ID_MT7988) ? \
-+					 MT7531_MIRROR_PORT_MASK : \
-+					 MT7530_MIRROR_PORT_MASK)
-+
-+#define MT753X_MIRROR_PORT_GET(id, val)	((id == ID_MT7531 || \
-+					  id == ID_MT7988) ? \
-+					 MT7531_MIRROR_PORT_GET(val) : \
-+					 MT7530_MIRROR_PORT_GET(val))
-+
-+#define MT753X_MIRROR_PORT_SET(id, val)	((id == ID_MT7531 || \
-+					  id == ID_MT7988) ? \
-+					 MT7531_MIRROR_PORT_SET(val) : \
-+					 MT7530_MIRROR_PORT_SET(val))
- 
- /* Register for BPDU and PAE frame control */
- #define MT753X_BPC			0x24
diff --git a/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
deleted file mode 100644
index d2497d5c90..0000000000
--- a/target/linux/generic/pending-6.1/795-06-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch
+++ /dev/null
@@ -1,257 +0,0 @@
-From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:13 +0300
-Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
- MT7530_MHWTRAP
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
-It's called hardware trap on MT7530, software trap on MT7531. That's
-because some bits of the trap on MT7530 cannot be modified by software
-whilst all bits of the trap on MT7531 can. Rename the definitions for them
-to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
-definitions specific to the switch model.
-
-Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
-
-Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
-par with the "MT7621 Giga Switch Programming Guide v0.3" document.
-
-Make an enumaration for the XTAL frequency. Set the data type of the xtal
-variable on mt7531_pll_setup() to it.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
- drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
- 2 files changed, 54 insertions(+), 55 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -403,23 +403,23 @@ mt7530_setup_port6(struct dsa_switch *ds
- 
- 	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
- 
--	xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
-+	xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
- 
--	if (xtal == HWTRAP_XTAL_25MHZ)
-+	if (xtal == MT7530_XTAL_25MHZ)
- 		ssc_delta = 0x57;
- 	else
- 		ssc_delta = 0x87;
- 
- 	if (priv->id == ID_MT7621) {
- 		/* PLL frequency: 125MHz: 1.0GBit */
--		if (xtal == HWTRAP_XTAL_40MHZ)
-+		if (xtal == MT7530_XTAL_40MHZ)
- 			ncpo1 = 0x0640;
--		if (xtal == HWTRAP_XTAL_25MHZ)
-+		if (xtal == MT7530_XTAL_25MHZ)
- 			ncpo1 = 0x0a00;
- 	} else { /* PLL frequency: 250MHz: 2.0Gbit */
--		if (xtal == HWTRAP_XTAL_40MHZ)
-+		if (xtal == MT7530_XTAL_40MHZ)
- 			ncpo1 = 0x0c80;
--		if (xtal == HWTRAP_XTAL_25MHZ)
-+		if (xtal == MT7530_XTAL_25MHZ)
- 			ncpo1 = 0x1400;
- 	}
- 
-@@ -442,19 +442,20 @@ mt7530_setup_port6(struct dsa_switch *ds
- static void
- mt7531_pll_setup(struct mt7530_priv *priv)
- {
-+	enum mt7531_xtal_fsel xtal;
- 	u32 top_sig;
- 	u32 hwstrap;
--	u32 xtal;
- 	u32 val;
- 
- 	val = mt7530_read(priv, MT7531_CREV);
- 	top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
--	hwstrap = mt7530_read(priv, MT7531_HWTRAP);
-+	hwstrap = mt7530_read(priv, MT753X_TRAP);
- 	if ((val & CHIP_REV_M) > 0)
--		xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
--						    HWTRAP_XTAL_FSEL_25MHZ;
-+		xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
-+						    MT7531_XTAL_FSEL_25MHZ;
- 	else
--		xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
-+		xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
-+						   MT7531_XTAL_FSEL_40MHZ;
- 
- 	/* Step 1 : Disable MT7531 COREPLL */
- 	val = mt7530_read(priv, MT7531_PLLGP_EN);
-@@ -483,13 +484,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
- 	usleep_range(25, 35);
- 
- 	switch (xtal) {
--	case HWTRAP_XTAL_FSEL_25MHZ:
-+	case MT7531_XTAL_FSEL_25MHZ:
- 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
- 		val &= ~RG_COREPLL_SDM_PCW_M;
- 		val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
- 		mt7530_write(priv, MT7531_PLLGP_CR0, val);
- 		break;
--	case HWTRAP_XTAL_FSEL_40MHZ:
-+	case MT7531_XTAL_FSEL_40MHZ:
- 		val = mt7530_read(priv, MT7531_PLLGP_CR0);
- 		val &= ~RG_COREPLL_SDM_PCW_M;
- 		val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
-@@ -870,20 +871,20 @@ static void mt7530_setup_port5(struct ds
- 
- 	mutex_lock(&priv->reg_mutex);
- 
--	val = mt7530_read(priv, MT7530_MHWTRAP);
-+	val = mt7530_read(priv, MT753X_MTRAP);
- 
--	val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
--	val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
-+	val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
-+	val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
- 
- 	switch (priv->p5_mode) {
- 	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
- 	case MUX_PHY_P0:
--		val |= MHWTRAP_PHY0_SEL;
-+		val |= MT7530_P5_PHY0_SEL;
- 		fallthrough;
- 
- 	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
- 	case MUX_PHY_P4:
--		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
-+		val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
- 
- 		/* Setup the MAC by default for the cpu port */
- 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
-@@ -891,13 +892,13 @@ static void mt7530_setup_port5(struct ds
- 
- 	/* GMAC5: P5 -> SoC MAC or external PHY */
- 	default:
--		val &= ~MHWTRAP_P5_DIS;
-+		val &= ~MT7530_P5_DIS;
- 		break;
- 	}
- 
- 	/* Setup RGMII settings */
- 	if (phy_interface_mode_is_rgmii(interface)) {
--		val |= MHWTRAP_P5_RGMII_MODE;
-+		val |= MT7530_P5_RGMII_MODE;
- 
- 		/* P5 RGMII RX Clock Control: delay setting for 1000M */
- 		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
-@@ -917,7 +918,7 @@ static void mt7530_setup_port5(struct ds
- 			     P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
- 	}
- 
--	mt7530_write(priv, MT7530_MHWTRAP, val);
-+	mt7530_write(priv, MT753X_MTRAP, val);
- 
- 	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
- 		mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
-@@ -2356,7 +2357,7 @@ mt7530_setup(struct dsa_switch *ds)
- 	}
- 
- 	/* Waiting for MT7530 got to stable */
--	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
-+	INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
- 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
- 				 20, 1000000);
- 	if (ret < 0) {
-@@ -2371,7 +2372,7 @@ mt7530_setup(struct dsa_switch *ds)
- 		return -ENODEV;
- 	}
- 
--	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
-+	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
- 		dev_err(priv->dev,
- 			"MT7530 with a 20MHz XTAL is not supported!\n");
- 		return -EINVAL;
-@@ -2392,12 +2393,12 @@ mt7530_setup(struct dsa_switch *ds)
- 			   RD_TAP_MASK, RD_TAP(16));
- 
- 	/* Enable port 6 */
--	val = mt7530_read(priv, MT7530_MHWTRAP);
--	val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
--	val |= MHWTRAP_MANUAL;
--	mt7530_write(priv, MT7530_MHWTRAP, val);
-+	val = mt7530_read(priv, MT753X_MTRAP);
-+	val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
-+	val |= MT7530_CHG_TRAP;
-+	mt7530_write(priv, MT753X_MTRAP, val);
- 
--	if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
-+	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
- 		mt7530_pll_setup(priv);
- 
- 	mt753x_trap_frames(priv);
-@@ -2577,7 +2578,7 @@ mt7531_setup(struct dsa_switch *ds)
- 	}
- 
- 	/* Waiting for MT7530 got to stable */
--	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
-+	INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
- 	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
- 				 20, 1000000);
- 	if (ret < 0) {
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
- 	MT7531_CLK_SKEW_REVERSE = 3,
- };
- 
--/* Register for hw trap status */
--#define MT7530_HWTRAP			0x7800
--#define  HWTRAP_XTAL_MASK		(BIT(10) | BIT(9))
--#define  HWTRAP_XTAL_25MHZ		(BIT(10) | BIT(9))
--#define  HWTRAP_XTAL_40MHZ		(BIT(10))
--#define  HWTRAP_XTAL_20MHZ		(BIT(9))
-+/* Register for trap status */
-+#define MT753X_TRAP			0x7800
-+#define  MT7530_XTAL_MASK		(BIT(10) | BIT(9))
-+#define  MT7530_XTAL_25MHZ		(BIT(10) | BIT(9))
-+#define  MT7530_XTAL_40MHZ		BIT(10)
-+#define  MT7530_XTAL_20MHZ		BIT(9)
-+#define  MT7531_XTAL25			BIT(7)
- 
--#define MT7531_HWTRAP			0x7800
--#define  HWTRAP_XTAL_FSEL_MASK		BIT(7)
--#define  HWTRAP_XTAL_FSEL_25MHZ		BIT(7)
--#define  HWTRAP_XTAL_FSEL_40MHZ		0
--/* Unique fields of (M)HWSTRAP for MT7531 */
--#define  XTAL_FSEL_S			7
--#define  XTAL_FSEL_M			BIT(7)
--#define  PHY_EN				BIT(6)
--#define  CHG_STRAP			BIT(8)
-+/* Register for trap modification */
-+#define MT753X_MTRAP			0x7804
-+#define  MT7530_P5_PHY0_SEL		BIT(20)
-+#define  MT7530_CHG_TRAP		BIT(16)
-+#define  MT7530_P5_MAC_SEL		BIT(13)
-+#define  MT7530_P6_DIS			BIT(8)
-+#define  MT7530_P5_RGMII_MODE		BIT(7)
-+#define  MT7530_P5_DIS			BIT(6)
-+#define  MT7530_PHY_INDIRECT_ACCESS	BIT(5)
-+#define  MT7531_CHG_STRAP		BIT(8)
-+#define  MT7531_PHY_EN			BIT(6)
- 
--/* Register for hw trap modification */
--#define MT7530_MHWTRAP			0x7804
--#define  MHWTRAP_PHY0_SEL		BIT(20)
--#define  MHWTRAP_MANUAL			BIT(16)
--#define  MHWTRAP_P5_MAC_SEL		BIT(13)
--#define  MHWTRAP_P6_DIS			BIT(8)
--#define  MHWTRAP_P5_RGMII_MODE		BIT(7)
--#define  MHWTRAP_P5_DIS			BIT(6)
--#define  MHWTRAP_PHY_ACCESS		BIT(5)
-+enum mt7531_xtal_fsel {
-+	MT7531_XTAL_FSEL_25MHZ,
-+	MT7531_XTAL_FSEL_40MHZ,
-+};
- 
- /* Register for TOP signal control */
- #define MT7530_TOP_SIG_CTRL		0x7808
diff --git a/target/linux/generic/pending-6.1/795-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/pending-6.1/795-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
deleted file mode 100644
index e7da939588..0000000000
--- a/target/linux/generic/pending-6.1/795-07-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:14 +0300
-Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
- MT7530
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-On MT7530, the media-independent interfaces of port 5 and 6 are controlled
-by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
-these bits only when the relevant port is being enabled or disabled. This
-ensures that these ports will be disabled when they are not in use.
-
-Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
-done on mt7530_setup().
-
-Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
-on the appropriate case.
-
-If PHY muxing is detected, clear MT7530_P5_DIS before calling
-mt7530_setup_port5().
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
- 1 file changed, 27 insertions(+), 11 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -873,8 +873,7 @@ static void mt7530_setup_port5(struct ds
- 
- 	val = mt7530_read(priv, MT753X_MTRAP);
- 
--	val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
--	val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
-+	val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
- 
- 	switch (priv->p5_mode) {
- 	/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
-@@ -884,15 +883,13 @@ static void mt7530_setup_port5(struct ds
- 
- 	/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
- 	case MUX_PHY_P4:
--		val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
--
- 		/* Setup the MAC by default for the cpu port */
- 		mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
- 		break;
- 
- 	/* GMAC5: P5 -> SoC MAC or external PHY */
- 	default:
--		val &= ~MT7530_P5_DIS;
-+		val |= MT7530_P5_MAC_SEL;
- 		break;
- 	}
- 
-@@ -1186,6 +1183,14 @@ mt7530_port_enable(struct dsa_switch *ds
- 
- 	mutex_unlock(&priv->reg_mutex);
- 
-+	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
-+		return 0;
-+
-+	if (port == 5)
-+		mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
-+	else if (port == 6)
-+		mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
-+
- 	return 0;
- }
- 
-@@ -1204,6 +1209,14 @@ mt7530_port_disable(struct dsa_switch *d
- 		   PCR_MATRIX_CLR);
- 
- 	mutex_unlock(&priv->reg_mutex);
-+
-+	if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
-+		return;
-+
-+	if (port == 5)
-+		mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
-+	else if (port == 6)
-+		mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
- }
- 
- static int
-@@ -2392,11 +2405,11 @@ mt7530_setup(struct dsa_switch *ds)
- 		mt7530_rmw(priv, MT7530_TRGMII_RD(i),
- 			   RD_TAP_MASK, RD_TAP(16));
- 
--	/* Enable port 6 */
--	val = mt7530_read(priv, MT753X_MTRAP);
--	val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
--	val |= MT7530_CHG_TRAP;
--	mt7530_write(priv, MT753X_MTRAP, val);
-+	/* Allow modifying the trap and directly access PHY registers via the
-+	 * MDIO bus the switch is on.
-+	 */
-+	mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
-+		   MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
- 
- 	if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
- 		mt7530_pll_setup(priv);
-@@ -2479,8 +2492,11 @@ mt7530_setup(struct dsa_switch *ds)
- 			break;
- 		}
- 
--		if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
-+		if (priv->p5_mode == MUX_PHY_P0 ||
-+		    priv->p5_mode == MUX_PHY_P4) {
-+			mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
- 			mt7530_setup_port5(ds, interface);
-+		}
- 	}
- 
- #ifdef CONFIG_GPIOLIB
diff --git a/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
deleted file mode 100644
index 7cc145327c..0000000000
--- a/target/linux/generic/pending-6.1/795-08-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:15 +0300
-Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
- mt7531_setup_common on error
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The mt7530_setup_mdio() and mt7531_setup_common() functions should be
-checked for errors. Return if the functions return a non-zero value.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2658,7 +2658,9 @@ mt7531_setup(struct dsa_switch *ds)
- 					 0);
- 	}
- 
--	mt7531_setup_common(ds);
-+	ret = mt7531_setup_common(ds);
-+	if (ret)
-+		return ret;
- 
- 	/* Setup VLAN ID 0 for VLAN-unaware bridges */
- 	ret = mt7530_setup_vlan0(priv);
-@@ -3017,6 +3019,8 @@ mt753x_setup(struct dsa_switch *ds)
- 	ret = mt7530_setup_mdio(priv);
- 	if (ret && priv->irq)
- 		mt7530_free_irq_common(priv);
-+	if (ret)
-+		return ret;
- 
- 	/* Initialise the PCS devices */
- 	for (i = 0; i < priv->ds->num_ports; i++) {
diff --git a/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
deleted file mode 100644
index f4d19db274..0000000000
--- a/target/linux/generic/pending-6.1/795-09-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:16 +0300
-Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
- switch model
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-With the support of the MT7988 SoC switch, the MAC speed capabilities
-defined on mt753x_phylink_get_caps() won't apply to all switch models
-anymore. Move them to more appropriate locations instead of overwriting
-config->mac_capabilities.
-
-Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
-the support of MT7531 and MT7988 SoC switch.
-
-Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 15 ++++++++++-----
- 1 file changed, 10 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2676,6 +2676,8 @@ mt7531_setup(struct dsa_switch *ds)
- static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
- 				     struct phylink_config *config)
- {
-+	config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
-+
- 	switch (port) {
- 	/* Ports which are connected to switch PHYs. There is no MII pinout. */
- 	case 0 ... 4:
-@@ -2707,6 +2709,8 @@ static void mt7531_mac_port_get_caps(str
- {
- 	struct mt7530_priv *priv = ds->priv;
- 
-+	config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
-+
- 	switch (port) {
- 	/* Ports which are connected to switch PHYs. There is no MII pinout. */
- 	case 0 ... 4:
-@@ -2746,14 +2750,17 @@ static void mt7988_mac_port_get_caps(str
- 	case 0 ... 3:
- 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
- 			  config->supported_interfaces);
-+
-+		config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
- 		break;
- 
- 	/* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
- 	case 6:
- 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
- 			  config->supported_interfaces);
--		config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
--					   MAC_10000FD;
-+
-+		config->mac_capabilities |= MAC_10000FD;
-+		break;
- 	}
- }
- 
-@@ -2923,9 +2930,7 @@ static void mt753x_phylink_get_caps(stru
- {
- 	struct mt7530_priv *priv = ds->priv;
- 
--	/* This switch only supports full-duplex at 1Gbps */
--	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
--				   MAC_10 | MAC_100 | MAC_1000FD;
-+	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
- 
- 	/* This driver does not make use of the speed, duplex, pause or the
- 	 * advertisement in its mac_config, so it is safe to mark this driver
diff --git a/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
deleted file mode 100644
index 5bb7756c51..0000000000
--- a/target/linux/generic/pending-6.1/795-10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:17 +0300
-Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Get rid of checking whether functions are filled properly. priv->info which
-is an mt753x_info structure is filled and checked for before this check.
-It's unnecessary checking whether it's filled properly.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 7 -------
- 1 file changed, 7 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3220,13 +3220,6 @@ mt7530_probe_common(struct mt7530_priv *
- 	if (!priv->info)
- 		return -EINVAL;
- 
--	/* Sanity check if these required device operations are filled
--	 * properly.
--	 */
--	if (!priv->info->sw_setup || !priv->info->phy_read ||
--	    !priv->info->phy_write || !priv->info->mac_port_get_caps)
--		return -EINVAL;
--
- 	priv->id = priv->info->id;
- 	priv->dev = dev;
- 	priv->ds->priv = priv;
diff --git a/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
deleted file mode 100644
index f8147b6412..0000000000
--- a/target/linux/generic/pending-6.1/795-11-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:18 +0300
-Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
-MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
-FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
-SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c |  8 ++++----
- drivers/net/dsa/mt7530.h | 13 +++++++------
- 2 files changed, 11 insertions(+), 10 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3048,10 +3048,10 @@ static int mt753x_get_mac_eee(struct dsa
- 			      struct ethtool_eee *e)
- {
- 	struct mt7530_priv *priv = ds->priv;
--	u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
-+	u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
- 
- 	e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
--	e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
-+	e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
- 
- 	return 0;
- }
-@@ -3065,11 +3065,11 @@ static int mt753x_set_mac_eee(struct dsa
- 	if (e->tx_lpi_timer > 0xFFF)
- 		return -EINVAL;
- 
--	set = SET_LPI_THRESH(e->tx_lpi_timer);
-+	set = LPI_THRESH_SET(e->tx_lpi_timer);
- 	if (!e->tx_lpi_enabled)
- 		/* Force LPI Mode without a delay */
- 		set |= LPI_MODE_EN;
--	mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
-+	mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
- 
- 	return 0;
- }
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
- 					 PMCR_FORCE_SPEED_100 | \
- 					 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
- 
--#define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
--#define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
--#define  WAKEUP_TIME_100(x)		(((x) & 0xFF) << 16)
-+#define MT753X_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
-+#define  WAKEUP_TIME_1000_MASK		GENMASK(31, 24)
-+#define  WAKEUP_TIME_1000(x)		FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
-+#define  WAKEUP_TIME_100_MASK		GENMASK(23, 16)
-+#define  WAKEUP_TIME_100(x)		FIELD_PREP(WAKEUP_TIME_100_MASK, x)
- #define  LPI_THRESH_MASK		GENMASK(15, 4)
--#define  LPI_THRESH_SHT			4
--#define  SET_LPI_THRESH(x)		(((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
--#define  GET_LPI_THRESH(x)		(((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
-+#define  LPI_THRESH_GET(x)		FIELD_GET(LPI_THRESH_MASK, x)
-+#define  LPI_THRESH_SET(x)		FIELD_PREP(LPI_THRESH_MASK, x)
- #define  LPI_MODE_EN			BIT(0)
- 
- #define MT7530_PMSR_P(x)		(0x3008 + (x) * 0x100)
diff --git a/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
deleted file mode 100644
index 0037f97499..0000000000
--- a/target/linux/generic/pending-6.1/795-13-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:20 +0300
-Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
- MT7530_NUM_PORTS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Use priv->ds->num_ports on all for loops which configure the switch
-registers. In the future, the value of MT7530_NUM_PORTS will depend on
-priv->id. Therefore, this change prepares the subdriver for a simpler
-implementation.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1404,7 +1404,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
- 	mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
- 		   G0_PORT_VID_DEF);
- 
--	for (i = 0; i < MT7530_NUM_PORTS; i++) {
-+	for (i = 0; i < priv->ds->num_ports; i++) {
- 		if (dsa_is_user_port(ds, i) &&
- 		    dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
- 			all_user_ports_removed = false;
-@@ -2419,7 +2419,7 @@ mt7530_setup(struct dsa_switch *ds)
- 	/* Enable and reset MIB counters */
- 	mt7530_mib_reset(ds);
- 
--	for (i = 0; i < MT7530_NUM_PORTS; i++) {
-+	for (i = 0; i < priv->ds->num_ports; i++) {
- 		/* Clear link settings and enable force mode to force link down
- 		 * on all ports until they're enabled later.
- 		 */
-@@ -2530,7 +2530,7 @@ mt7531_setup_common(struct dsa_switch *d
- 	mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
- 		     UNU_FFP_MASK);
- 
--	for (i = 0; i < MT7530_NUM_PORTS; i++) {
-+	for (i = 0; i < priv->ds->num_ports; i++) {
- 		/* Clear link settings and enable force mode to force link down
- 		 * on all ports until they're enabled later.
- 		 */
-@@ -2617,7 +2617,7 @@ mt7531_setup(struct dsa_switch *ds)
- 	priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
- 
- 	/* Force link down on all ports before internal reset */
--	for (i = 0; i < MT7530_NUM_PORTS; i++)
-+	for (i = 0; i < priv->ds->num_ports; i++)
- 		mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
- 
- 	/* Reset the switch through internal reset */
diff --git a/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
deleted file mode 100644
index ee8e13ea70..0000000000
--- a/target/linux/generic/pending-6.1/795-14-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:21 +0300
-Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
- mt7531_rgmii_setup()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The mt7531_rgmii_setup() function does not use the port variable, do not
-pass the variable to it.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2776,7 +2776,7 @@ mt7530_mac_config(struct dsa_switch *ds,
- 		mt7530_setup_port6(priv->ds, interface);
- }
- 
--static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
-+static void mt7531_rgmii_setup(struct mt7530_priv *priv,
- 			       phy_interface_t interface,
- 			       struct phy_device *phydev)
- {
-@@ -2827,7 +2827,7 @@ mt7531_mac_config(struct dsa_switch *ds,
- 	if (phy_interface_mode_is_rgmii(interface)) {
- 		dp = dsa_to_port(ds, port);
- 		phydev = dp->slave->phydev;
--		mt7531_rgmii_setup(priv, port, interface, phydev);
-+		mt7531_rgmii_setup(priv, interface, phydev);
- 	}
- }
- 
diff --git a/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
deleted file mode 100644
index 666bcb75e8..0000000000
--- a/target/linux/generic/pending-6.1/795-15-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 22 Apr 2024 10:15:22 +0300
-Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
- better
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
-Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
-expose the MDIO bus of the switch. Replace the comment with a better
-explanation.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2626,7 +2626,10 @@ mt7531_setup(struct dsa_switch *ds)
- 	if (!priv->p5_sgmii) {
- 		mt7531_pll_setup(priv);
- 	} else {
--		/* Let ds->slave_mii_bus be able to access external phy. */
-+		/* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
-+		 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
-+		 * to expose the MDIO bus of the switch.
-+		 */
- 		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
- 			   MT7531_EXT_P_MDC_11);
- 		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
diff --git a/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch
index 98ea4c06d9..fcb77e5174 100644
--- a/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch
+++ b/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static struct amd_chipset_info {
  	struct pci_dev	*nb_dev;
  	struct pci_dev	*smbus_dev;
-@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device
+@@ -631,6 +633,10 @@ bool usb_amd_pt_check_port(struct device
  }
  EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
  
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /*
   * Make sure the controller is completely inactive, unable to
   * generate interrupts or do DMA.
-@@ -712,8 +718,17 @@ reset_needed:
+@@ -710,8 +716,17 @@ reset_needed:
  	uhci_reset_hc(pdev, base);
  	return 1;
  }
@@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
  {
  	u16 cmd;
-@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru
+@@ -1283,3 +1298,4 @@ static void quirk_usb_early_handoff(stru
  }
  DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  			PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
@@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
 --- a/include/linux/usb/hcd.h
 +++ b/include/linux/usb/hcd.h
-@@ -483,7 +483,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
  extern void usb_hcd_pci_remove(struct pci_dev *dev);
  extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
  
diff --git a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
index 76e3f2544d..ca36d0ccab 100644
--- a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
+++ b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch
@@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  /*
   * We need to store the untouched command line for future reference.
   * We also need to store the touched command line since the parameter
-@@ -959,6 +982,7 @@ asmlinkage __visible void __init __no_sa
+@@ -961,6 +984,7 @@ asmlinkage __visible void __init __no_sa
  	pr_notice("%s", linux_banner);
  	early_security_init();
  	setup_arch(&command_line);
diff --git a/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch
index b23cae1f5e..d8fd9cdf42 100644
--- a/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch
+++ b/target/linux/generic/pending-6.6/150-bridge_allow_receiption_on_disabled_port.patch
@@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -239,6 +239,9 @@ static void __br_handle_local_finish(str
+@@ -244,6 +244,9 @@ static void __br_handle_local_finish(str
  /* note: already called with rcu_read_lock */
  static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
  {
@@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__br_handle_local_finish(skb);
  
  	/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -408,6 +411,17 @@ forward:
+@@ -415,6 +418,17 @@ forward:
  		goto defer_stp_filtering;
  
  	switch (p->state) {
diff --git a/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch b/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch
new file mode 100644
index 0000000000..d504a74fde
--- /dev/null
+++ b/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch
@@ -0,0 +1,217 @@
+From patchwork Sun Apr 21 07:39:52 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: INAGAKI Hiroshi <musashino.open@gmail.com>
+X-Patchwork-Id: 13637306
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+To: axboe@kernel.dk
+Cc: yang.yang29@zte.com,
+	justinstitt@google.com,
+	xu.panda@zte.com.cn,
+	linux-block@vger.kernel.org,
+	linux-kernel@vger.kernel.org,
+	INAGAKI Hiroshi <musashino.open@gmail.com>,
+	Naohiro Aota <naota@elisp.net>
+Subject: [PATCH] block: fix and simplify blkdevparts= cmdline parsing
+Date: Sun, 21 Apr 2024 16:39:52 +0900
+Message-ID: <20240421074005.565-1-musashino.open@gmail.com>
+X-Mailer: git-send-email 2.42.0.windows.2
+Precedence: bulk
+X-Mailing-List: linux-block@vger.kernel.org
+List-Id: <linux-block.vger.kernel.org>
+List-Subscribe: <mailto:linux-block+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:linux-block+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+
+Fix the cmdline parsing of the "blkdevparts=" parameter using strsep(),
+which makes the code simpler.
+
+Before commit 146afeb235cc ("block: use strscpy() to instead of
+strncpy()"), we used a strncpy() to copy a block device name and partition
+names. The commit simply replaced a strncpy() and NULL termination with
+a strscpy(). It did not update calculations of length passed to strscpy().
+While the length passed to strncpy() is just a length of valid characters
+without NULL termination ('\0'), strscpy() takes it as a length of the
+destination buffer, including a NULL termination.
+
+Since the source buffer is not necessarily NULL terminated, the current
+code copies "length - 1" characters and puts a NULL character in the
+destination buffer. It replaces the last character with NULL and breaks
+the parsing.
+
+As an example, that buffer will be passed to parse_parts() and breaks
+parsing sub-partitions due to the missing ')' at the end, like the
+following.
+
+example (Check Point V-80 & OpenWrt):
+
+- Linux Kernel 6.6
+
+  [    0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4
+  ...
+  [    0.884016] mmc1: new HS200 MMC card at address 0001
+  [    0.889951] mmcblk1: mmc1:0001 004GA0 3.69 GiB
+  [    0.895043] cmdline partition format is invalid.
+  [    0.895704]  mmcblk1: p1
+  [    0.903447] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB
+  [    0.908667] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB
+  [    0.913765] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0)
+
+  1. "48M@10M(kernel-1),..." is passed to strscpy() with length=17
+     from parse_parts()
+  2. strscpy() returns -E2BIG and the destination buffer has
+     "48M@10M(kernel-1\0"
+  3. "48M@10M(kernel-1\0" is passed to parse_subpart()
+  4. parse_subpart() fails to find ')' when parsing a partition name,
+     and returns error
+
+- Linux Kernel 6.1
+
+  [    0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4
+  ...
+  [    0.953142] mmc1: new HS200 MMC card at address 0001
+  [    0.959114] mmcblk1: mmc1:0001 004GA0 3.69 GiB
+  [    0.964259]  mmcblk1: p1(kernel-1) p2(dtb-1) p3(rootfs-1) p4(kernel-2) p5(dtb-2) 6(rootfs-2) p7(default_sw) p8(logs) p9(preset_cfg) p10(adsl) p11(storage)
+  [    0.979174] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB
+  [    0.984674] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB
+  [    0.989926] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0
+
+By the way, strscpy() takes a length of destination buffer and it is
+often confusing when copying characters with a specified length. Using
+strsep() helps to separate the string by the specified character. Then,
+we can use strscpy() naturally with the size of the destination buffer.
+
+Separating the string on the fly is also useful to omit the redundant
+string copy, reducing memory usage and improve the code readability.
+
+Fixes: 146afeb235cc ("block: use strscpy() to instead of strncpy()")
+Suggested-by: Naohiro Aota <naota@elisp.net>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/partitions/cmdline.c | 49 ++++++++++----------------------------
+ 1 file changed, 12 insertions(+), 37 deletions(-)
+
+--- a/block/partitions/cmdline.c
++++ b/block/partitions/cmdline.c
+@@ -70,8 +70,8 @@ static int parse_subpart(struct cmdline_
+ 	}
+ 
+ 	if (*partdef == '(') {
+-		int length;
+-		char *next = strchr(++partdef, ')');
++		partdef++;
++		char *next = strsep(&partdef, ")");
+ 
+ 		if (!next) {
+ 			pr_warn("cmdline partition format is invalid.");
+@@ -79,11 +79,7 @@ static int parse_subpart(struct cmdline_
+ 			goto fail;
+ 		}
+ 
+-		length = min_t(int, next - partdef,
+-			       sizeof(new_subpart->name) - 1);
+-		strscpy(new_subpart->name, partdef, length);
+-
+-		partdef = ++next;
++		strscpy(new_subpart->name, next, sizeof(new_subpart->name));
+ 	} else
+ 		new_subpart->name[0] = '\0';
+ 
+@@ -117,14 +113,12 @@ static void free_subpart(struct cmdline_
+ 	}
+ }
+ 
+-static int parse_parts(struct cmdline_parts **parts, const char *bdevdef)
++static int parse_parts(struct cmdline_parts **parts, char *bdevdef)
+ {
+ 	int ret = -EINVAL;
+ 	char *next;
+-	int length;
+ 	struct cmdline_subpart **next_subpart;
+ 	struct cmdline_parts *newparts;
+-	char buf[BDEVNAME_SIZE + 32 + 4];
+ 
+ 	*parts = NULL;
+ 
+@@ -132,28 +126,19 @@ static int parse_parts(struct cmdline_pa
+ 	if (!newparts)
+ 		return -ENOMEM;
+ 
+-	next = strchr(bdevdef, ':');
++	next = strsep(&bdevdef, ":");
+ 	if (!next) {
+ 		pr_warn("cmdline partition has no block device.");
+ 		goto fail;
+ 	}
+ 
+-	length = min_t(int, next - bdevdef, sizeof(newparts->name) - 1);
+-	strscpy(newparts->name, bdevdef, length);
++	strscpy(newparts->name, next, sizeof(newparts->name));
+ 	newparts->nr_subparts = 0;
+ 
+ 	next_subpart = &newparts->subpart;
+ 
+-	while (next && *(++next)) {
+-		bdevdef = next;
+-		next = strchr(bdevdef, ',');
+-
+-		length = (!next) ? (sizeof(buf) - 1) :
+-			min_t(int, next - bdevdef, sizeof(buf) - 1);
+-
+-		strscpy(buf, bdevdef, length);
+-
+-		ret = parse_subpart(next_subpart, buf);
++	while ((next = strsep(&bdevdef, ","))) {
++		ret = parse_subpart(next_subpart, next);
+ 		if (ret)
+ 			goto fail;
+ 
+@@ -199,24 +184,17 @@ static int cmdline_parts_parse(struct cm
+ 
+ 	*parts = NULL;
+ 
+-	next = pbuf = buf = kstrdup(cmdline, GFP_KERNEL);
++	pbuf = buf = kstrdup(cmdline, GFP_KERNEL);
+ 	if (!buf)
+ 		return -ENOMEM;
+ 
+ 	next_parts = parts;
+ 
+-	while (next && *pbuf) {
+-		next = strchr(pbuf, ';');
+-		if (next)
+-			*next = '\0';
+-
+-		ret = parse_parts(next_parts, pbuf);
++	while ((next = strsep(&pbuf, ";"))) {
++		ret = parse_parts(next_parts, next);
+ 		if (ret)
+ 			goto fail;
+ 
+-		if (next)
+-			pbuf = ++next;
+-
+ 		next_parts = &(*next_parts)->next_parts;
+ 	}
+ 
+@@ -250,7 +228,6 @@ static struct cmdline_parts *bdev_parts;
+ static int add_part(int slot, struct cmdline_subpart *subpart,
+ 		struct parsed_partitions *state)
+ {
+-	int label_min;
+ 	struct partition_meta_info *info;
+ 	char tmp[sizeof(info->volname) + 4];
+ 
+@@ -262,9 +239,7 @@ static int add_part(int slot, struct cmd
+ 
+ 	info = &state->parts[slot].info;
+ 
+-	label_min = min_t(int, sizeof(info->volname) - 1,
+-			  sizeof(subpart->name));
+-	strscpy(info->volname, subpart->name, label_min);
++	strscpy(info->volname, subpart->name, sizeof(info->volname));
+ 
+ 	snprintf(tmp, sizeof(tmp), "(%s)", info->volname);
+ 	strlcat(state->pp_buf, tmp, PAGE_SIZE);
diff --git a/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch b/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch
index 4654bc14ef..3bf7ae98bf 100644
--- a/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch
+++ b/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch
@@ -7,35 +7,45 @@ Subject: [PATCH] mips: kernel: fix detect_memory_region() function
 2. Use a fixed pattern instead of a random function pointer as the
    magic value.
 3. Flip magic value and double check it.
+4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and
+   ralink CPUs are using it.
 
 [1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available")
 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
 ---
- arch/mips/kernel/setup.c | 16 +++++++++++-----
- 1 file changed, 11 insertions(+), 5 deletions(-)
+ arch/mips/include/asm/bootinfo.h |  2 ++
+ arch/mips/kernel/setup.c         | 17 ++++++++++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
 
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -93,7 +93,9 @@ const char *get_system_type(void);
+ 
+ extern unsigned long mips_machtype;
+ 
++#ifndef CONFIG_64BIT
+ extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min,  phys_addr_t sz_max);
++#endif
+ 
+ extern void prom_init(void);
+ extern void prom_free_prom_memory(void);
 --- a/arch/mips/kernel/setup.c
 +++ b/arch/mips/kernel/setup.c
-@@ -46,6 +46,8 @@
- #include <asm/prom.h>
- #include <asm/fw/fw.h>
- 
-+#define MIPS_MEM_TEST_PATTERN		0xaa5555aa
-+
- #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
- char __section(".appended_dtb") __appended_dtb[0x100000];
- #endif /* CONFIG_MIPS_ELF_APPENDED_DTB */
-@@ -90,7 +92,7 @@ static struct resource bss_resource = {
+@@ -90,21 +90,27 @@ static struct resource bss_resource = {
  unsigned long __kaslr_offset __ro_after_init;
  EXPORT_SYMBOL(__kaslr_offset);
  
 -static void *detect_magic __initdata = detect_memory_region;
-+static u32 detect_magic __initdata;
- 
+-
  #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
  unsigned long ARCH_PFN_OFFSET;
-@@ -99,12 +101,16 @@ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ #endif
  
++#ifndef CONFIG_64BIT
++static u32 detect_magic __initdata;
++#define MIPS_MEM_TEST_PATTERN		0xaa5555aa
++
  void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
  {
 -	void *dm = &detect_magic;
@@ -54,3 +64,11 @@ Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
  	}
  
  	pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
+@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad
+ 
+ 	memblock_add(start, size);
+ }
++#endif /* CONFIG_64BIT */
+ 
+ /*
+  * Manage initrd
diff --git a/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch b/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch
new file mode 100644
index 0000000000..0f28834d48
--- /dev/null
+++ b/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch
@@ -0,0 +1,26 @@
+From ecb8f9a7d69698ce20fc6f4d107718d56fa861df Mon Sep 17 00:00:00 2001
+From: Tony Ambardar <Tony.Ambardar@gmail.com>
+Date: Sat, 9 Mar 2024 16:44:53 -0800
+Subject: [PATCH] selftests/bpf: Improve portability of unprivileged tests
+
+The addition of general support for unprivileged tests in test_loader.c
+breaks building test_verifier on non-glibc (e.g. musl) systems, due to the
+inclusion of glibc extension '<error.h>' in 'unpriv_helpers.c'. However,
+the header is actually not needed, so remove it to restore building.
+
+Fixes: 1d56ade032a4 ("selftests/bpf: Unprivileged tests for test_loader.c")
+Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
+---
+ tools/testing/selftests/bpf/unpriv_helpers.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/tools/testing/selftests/bpf/unpriv_helpers.c
++++ b/tools/testing/selftests/bpf/unpriv_helpers.c
+@@ -2,7 +2,6 @@
+ 
+ #include <stdbool.h>
+ #include <stdlib.h>
+-#include <error.h>
+ #include <stdio.h>
+ 
+ #include "unpriv_helpers.h"
diff --git a/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch b/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch
deleted file mode 100644
index d9d15a4048..0000000000
--- a/target/linux/generic/pending-6.6/440-mtd-don-t-look-for-OTP-legacy-NVMEM-cells-if-proper-.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 27 Mar 2024 23:18:51 +0100
-Subject: [PATCH] mtd: don't look for OTP legacy NVMEM cells if proper node
- doesn't exist
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If node with "user-otp" / "factory-otp" compatible doesn't exist it's
-important to prevent NVMEM core from looking for legacy NVMEM cells.
-Otherwise it would look for them in the device node.
-
-This fixes treating NAND controller attached chips as NVMEM cell.
-Problem example:
-[    0.410107] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xdc
-[    0.416531] nand: Macronix MX30LF4G18AC
-[    0.420409] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
-[    0.428022] iproc_nand 18028000.nand-controller: detected 512MiB total, 128KiB blocks, 2KiB pages, 16B OOB, 8-bit, BCH-8
-[    0.438991] Scanning device for bad blocks
-(...)
-[    2.848418] nvmem user-otp1: nvmem: invalid reg on /nand-controller@18028000/nand@0
-[    2.856126] iproc_nand 18028000.nand-controller: error -EINVAL: Failed to register OTP NVMEM device
-
-This long standing issue was exposed by the support for Macronix OTP.
-
-Reported-by: Christian Marangi <ansuelsmth@gmail.com>
-Fixes: 4b361cfa8624 ("mtd: core: add OTP nvmem provider support")
-Fixes: e87161321a40 ("mtd: rawnand: macronix: OTP access for MX30LFxG18AC")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/mtd/mtdcore.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -931,7 +931,7 @@ static struct nvmem_device *mtd_otp_nvme
- 	config.name = compatible;
- 	config.id = NVMEM_DEVID_AUTO;
- 	config.owner = THIS_MODULE;
--	config.add_legacy_fixed_of_cells = true;
-+	config.add_legacy_fixed_of_cells = !!np;
- 	config.type = NVMEM_TYPE_OTP;
- 	config.root_only = true;
- 	config.ignore_wp = true;
diff --git a/target/linux/generic/pending-6.6/655-increase_skb_pad.patch b/target/linux/generic/pending-6.6/655-increase_skb_pad.patch
index 31a40f1cdf..ce7db566e5 100644
--- a/target/linux/generic/pending-6.6/655-increase_skb_pad.patch
+++ b/target/linux/generic/pending-6.6/655-increase_skb_pad.patch
@@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -3047,7 +3047,7 @@ static inline int pskb_network_may_pull(
+@@ -3062,7 +3062,7 @@ static inline int pskb_network_may_pull(
   * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
   */
  #ifndef NET_SKB_PAD
diff --git a/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
deleted file mode 100644
index 0859e217cd..0000000000
--- a/target/linux/generic/pending-6.6/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h |  2 ++
- include/linux/skbuff.h    |  3 ++-
- net/core/dev.c            | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c        | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2210,6 +2210,8 @@ struct net_device {
- 	struct netdev_hw_addr_list	mc;
- 	struct netdev_hw_addr_list	dev_addrs;
- 
-+	unsigned char		local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- 	struct kset		*queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -959,6 +959,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- 	__u8			ndisc_nodetype:2;
- #endif
-+	__u8			gro_skip:1;
- 
- #if IS_ENABLED(CONFIG_IP_VS)
- 	__u8			ipvs_property:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -446,6 +446,9 @@ static enum gro_result dev_gro_receive(s
- 	enum gro_result ret;
- 	int same_flow;
- 
-+	if (skb->gro_skip)
-+		goto normal;
-+
- 	if (netif_elide_gro(skb->dev))
- 		goto normal;
- 
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7689,6 +7689,48 @@ static void __netdev_adjacent_dev_unlink
- 					   &upper_dev->adj_list.lower);
- }
- 
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+			       struct net_device *dev)
-+{
-+	int i;
-+
-+	for (i = 0; i < dev->addr_len; i++)
-+		mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+				struct net_device *lower)
-+{
-+	struct net_device *cur;
-+	struct list_head *iter;
-+
-+	netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+		__netdev_addr_mask(mask, cur->dev_addr, lower);
-+		__netdev_upper_mask(mask, cur, lower);
-+	}
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+	unsigned char mask[MAX_ADDR_LEN];
-+	struct net_device *cur;
-+	struct list_head *iter;
-+
-+	memset(mask, 0, sizeof(mask));
-+	__netdev_upper_mask(mask, dev, dev);
-+	memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+	netdev_for_each_lower_dev(dev, cur, iter)
-+		__netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+	rcu_read_lock();
-+	__netdev_update_addr_mask(dev);
-+	rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- 				   struct net_device *upper_dev, bool master,
- 				   void *upper_priv, void *upper_info,
-@@ -7740,6 +7782,7 @@ static int __netdev_upper_dev_link(struc
- 	if (ret)
- 		return ret;
- 
-+	netdev_update_addr_mask(dev);
- 	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 					    &changeupper_info.info);
- 	ret = notifier_to_errno(ret);
-@@ -7836,6 +7879,7 @@ static void __netdev_upper_dev_unlink(st
- 
- 	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
- 
-+	netdev_update_addr_mask(dev);
- 	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 				      &changeupper_info.info);
- 
-@@ -8892,6 +8936,7 @@ int dev_set_mac_address(struct net_devic
- 			return err;
- 	}
- 	dev->addr_assign_type = NET_ADDR_SET;
-+	netdev_update_addr_mask(dev);
- 	call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- 	add_device_randomness(dev->dev_addr, dev->addr_len);
- 	return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
- 
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+	const u16 *a1 = addr1;
-+	const u16 *a2 = addr2;
-+	const u16 *m = mask;
-+
-+	return (((a1[0] ^ a2[0]) & ~m[0]) |
-+		((a1[1] ^ a2[1]) & ~m[1]) |
-+		((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
-  * eth_type_trans - determine the packet's protocol ID.
-  * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- 		} else {
- 			skb->pkt_type = PACKET_OTHERHOST;
- 		}
-+
-+		if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+					 dev->local_addr_mask))
-+			skb->gro_skip = 1;
- 	}
- 
- 	/*
diff --git a/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch
new file mode 100644
index 0000000000..cd77626677
--- /dev/null
+++ b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch
@@ -0,0 +1,578 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on:  770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -439,6 +439,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+ 
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+ 
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2082,7 +2082,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+ 
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ 				netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++				struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -233,6 +233,33 @@ done:
+ 	return 0;
+ }
+ 
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++	if (unlikely(p->len + skb->len >= 65536))
++		return -E2BIG;
++
++	if (NAPI_GRO_CB(p)->last == p)
++		skb_shinfo(p)->frag_list = skb;
++	else
++		NAPI_GRO_CB(p)->last->next = skb;
++
++	skb_pull(skb, skb_gro_offset(skb));
++
++	NAPI_GRO_CB(p)->last = skb;
++	NAPI_GRO_CB(p)->count++;
++	p->data_len += skb->len;
++
++	/* sk ownership - if any - completely transferred to the aggregated packet */
++	skb->destructor = NULL;
++	skb->sk = NULL;
++	p->truesize += skb->truesize;
++	p->len += skb->len;
++
++	NAPI_GRO_CB(skb)->same_flow = 1;
++
++	return 0;
++}
++
+ 
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -28,6 +28,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ 	}
+ }
+ 
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++				     __be32 *oldip, __be32 newip,
++				     __be16 *oldport, __be16 newport)
++{
++	struct tcphdr *th;
++	struct iphdr *iph;
++
++	if (*oldip == newip && *oldport == newport)
++		return;
++
++	th = tcp_hdr(seg);
++	iph = ip_hdr(seg);
++
++	inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++	inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++	*oldport = newport;
++
++	csum_replace4(&iph->check, *oldip, newip);
++	*oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++	const struct tcphdr *th;
++	const struct iphdr *iph;
++	struct sk_buff *seg;
++	struct tcphdr *th2;
++	struct iphdr *iph2;
++
++	seg = segs;
++	th = tcp_hdr(seg);
++	iph = ip_hdr(seg);
++	th2 = tcp_hdr(seg->next);
++	iph2 = ip_hdr(seg->next);
++
++	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	    iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++		return segs;
++
++	while ((seg = seg->next)) {
++		th2 = tcp_hdr(seg);
++		iph2 = ip_hdr(seg);
++
++		__tcpv4_gso_segment_csum(seg,
++					 &iph2->saddr, iph->saddr,
++					 &th2->source, th->source);
++		__tcpv4_gso_segment_csum(seg,
++					 &iph2->daddr, iph->daddr,
++					 &th2->dest, th->dest);
++	}
++
++	return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++					      netdev_features_t features)
++{
++	skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++	if (IS_ERR(skb))
++		return skb;
++
++	return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ 					netdev_features_t features)
+ {
+@@ -37,6 +101,9 @@ static struct sk_buff *tcp4_gso_segment(
+ 	if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ 		return ERR_PTR(-EINVAL);
+ 
++	if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++		return __tcp4_gso_segment_list(skb, features);
++
+ 	if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ 		const struct iphdr *iph = ip_hdr(skb);
+ 		struct tcphdr *th = tcp_hdr(skb);
+@@ -178,61 +245,76 @@ out:
+ 	return segs;
+ }
+ 
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+-	struct sk_buff *pp = NULL;
++	struct tcphdr *th2;
+ 	struct sk_buff *p;
++
++	list_for_each_entry(p, head, list) {
++		if (!NAPI_GRO_CB(p)->same_flow)
++			continue;
++
++		th2 = tcp_hdr(p);
++		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++			NAPI_GRO_CB(p)->same_flow = 0;
++			continue;
++		}
++
++		return p;
++	}
++
++	return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++	unsigned int thlen, hlen, off;
+ 	struct tcphdr *th;
+-	struct tcphdr *th2;
+-	unsigned int len;
+-	unsigned int thlen;
+-	__be32 flags;
+-	unsigned int mss = 1;
+-	unsigned int hlen;
+-	unsigned int off;
+-	int flush = 1;
+-	int i;
+ 
+ 	off = skb_gro_offset(skb);
+ 	hlen = off + sizeof(*th);
+ 	th = skb_gro_header(skb, hlen, off);
+ 	if (unlikely(!th))
+-		goto out;
++		return NULL;
+ 
+ 	thlen = th->doff * 4;
+ 	if (thlen < sizeof(*th))
+-		goto out;
++		return NULL;
+ 
+ 	hlen = off + thlen;
+ 	if (skb_gro_header_hard(skb, hlen)) {
+ 		th = skb_gro_header_slow(skb, hlen, off);
+ 		if (unlikely(!th))
+-			goto out;
++			return NULL;
+ 	}
+ 
+ 	skb_gro_pull(skb, thlen);
+ 
+-	len = skb_gro_len(skb);
+-	flags = tcp_flag_word(th);
+-
+-	list_for_each_entry(p, head, list) {
+-		if (!NAPI_GRO_CB(p)->same_flow)
+-			continue;
++	return th;
++}
+ 
+-		th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++				struct tcphdr *th)
++{
++	unsigned int thlen = th->doff * 4;
++	struct sk_buff *pp = NULL;
++	struct sk_buff *p;
++	struct tcphdr *th2;
++	unsigned int len;
++	__be32 flags;
++	unsigned int mss = 1;
++	int flush = 1;
++	int i;
+ 
+-		if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+-			NAPI_GRO_CB(p)->same_flow = 0;
+-			continue;
+-		}
++	len = skb_gro_len(skb);
++	flags = tcp_flag_word(th);
+ 
+-		goto found;
+-	}
+-	p = NULL;
+-	goto out_check_final;
++	p = tcp_gro_lookup(head, th);
++	if (!p)
++		goto out_check_final;
+ 
+-found:
+ 	/* Include the IP ID check below from the inner most IP hdr */
++	th2 = tcp_hdr(p);
+ 	flush = NAPI_GRO_CB(p)->flush;
+ 	flush |= (__force int)(flags & TCP_FLAG_CWR);
+ 	flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -269,6 +351,19 @@ found:
+ 	flush |= p->decrypted ^ skb->decrypted;
+ #endif
+ 
++	if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++		flush |= (__force int)(flags ^ tcp_flag_word(th2));
++		flush |= skb->ip_summed != p->ip_summed;
++		flush |= skb->csum_level != p->csum_level;
++		flush |= !pskb_may_pull(skb, skb_gro_offset(skb));
++		flush |= NAPI_GRO_CB(p)->count >= 64;
++
++		if (flush || skb_gro_receive_list(p, skb))
++			mss = 1;
++
++		goto out_check_final;
++	}
++
+ 	if (flush || skb_gro_receive(p, skb)) {
+ 		mss = 1;
+ 		goto out_check_final;
+@@ -290,7 +385,6 @@ out_check_final:
+ 	if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ 		pp = p;
+ 
+-out:
+ 	NAPI_GRO_CB(skb)->flush |= (flush != 0);
+ 
+ 	return pp;
+@@ -314,18 +408,58 @@ void tcp_gro_complete(struct sk_buff *sk
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+ 
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++				    struct tcphdr *th)
++{
++	const struct iphdr *iph;
++	struct sk_buff *p;
++	struct sock *sk;
++	struct net *net;
++	int iif, sdif;
++
++	if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++		return;
++
++	p = tcp_gro_lookup(head, th);
++	if (p) {
++		NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++		return;
++	}
++
++	inet_get_iif_sdif(skb, &iif, &sdif);
++	iph = skb_gro_network_header(skb);
++	net = dev_net(skb->dev);
++	sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++				       iph->saddr, th->source,
++				       iph->daddr, ntohs(th->dest),
++				       iif, sdif);
++	NAPI_GRO_CB(skb)->is_flist = !sk;
++	if (sk)
++		sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++	struct tcphdr *th;
++
+ 	/* Don't bother verifying checksum if we're going to flush anyway. */
+ 	if (!NAPI_GRO_CB(skb)->flush &&
+ 	    skb_gro_checksum_validate(skb, IPPROTO_TCP,
+-				      inet_gro_compute_pseudo)) {
+-		NAPI_GRO_CB(skb)->flush = 1;
+-		return NULL;
+-	}
++				      inet_gro_compute_pseudo))
++		goto flush;
++
++	th = tcp_gro_pull_header(skb);
++	if (!th)
++		goto flush;
+ 
+-	return tcp_gro_receive(head, skb);
++	tcp4_check_fraglist_gro(head, skb, th);
++
++	return tcp_gro_receive(head, skb, th);
++
++flush:
++	NAPI_GRO_CB(skb)->flush = 1;
++	return NULL;
+ }
+ 
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -333,6 +467,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ 	const struct iphdr *iph = ip_hdr(skb);
+ 	struct tcphdr *th = tcp_hdr(skb);
+ 
++	if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++		skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++		skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++		__skb_incr_checksum_unnecessary(skb);
++
++		return 0;
++	}
++
+ 	th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ 				  iph->daddr, 0);
+ 	skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -433,33 +433,6 @@ out:
+ 	return segs;
+ }
+ 
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+-	if (unlikely(p->len + skb->len >= 65536))
+-		return -E2BIG;
+-
+-	if (NAPI_GRO_CB(p)->last == p)
+-		skb_shinfo(p)->frag_list = skb;
+-	else
+-		NAPI_GRO_CB(p)->last->next = skb;
+-
+-	skb_pull(skb, skb_gro_offset(skb));
+-
+-	NAPI_GRO_CB(p)->last = skb;
+-	NAPI_GRO_CB(p)->count++;
+-	p->data_len += skb->len;
+-
+-	/* sk ownership - if any - completely transferred to the aggregated packet */
+-	skb->destructor = NULL;
+-	skb->sk = NULL;
+-	p->truesize += skb->truesize;
+-	p->len += skb->len;
+-
+-	NAPI_GRO_CB(skb)->same_flow = 1;
+-
+-	return 0;
+-}
+-
+ 
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+  */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+ 
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++				    struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++	const struct ipv6hdr *hdr;
++	struct sk_buff *p;
++	struct sock *sk;
++	struct net *net;
++	int iif, sdif;
++
++	if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++		return;
++
++	p = tcp_gro_lookup(head, th);
++	if (p) {
++		NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++		return;
++	}
++
++	inet6_get_iif_sdif(skb, &iif, &sdif);
++	hdr = skb_gro_network_header(skb);
++	net = dev_net(skb->dev);
++	sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++					&hdr->saddr, th->source,
++					&hdr->daddr, ntohs(th->dest),
++					iif, sdif);
++	NAPI_GRO_CB(skb)->is_flist = !sk;
++	if (sk)
++		sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++	struct tcphdr *th;
++
+ 	/* Don't bother verifying checksum if we're going to flush anyway. */
+ 	if (!NAPI_GRO_CB(skb)->flush &&
+ 	    skb_gro_checksum_validate(skb, IPPROTO_TCP,
+-				      ip6_gro_compute_pseudo)) {
+-		NAPI_GRO_CB(skb)->flush = 1;
+-		return NULL;
+-	}
++				      ip6_gro_compute_pseudo))
++		goto flush;
+ 
+-	return tcp_gro_receive(head, skb);
++	th = tcp_gro_pull_header(skb);
++	if (!th)
++		goto flush;
++
++	tcp6_check_fraglist_gro(head, skb, th);
++
++	return tcp_gro_receive(head, skb, th);
++
++flush:
++	NAPI_GRO_CB(skb)->flush = 1;
++	return NULL;
+ }
+ 
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ 	const struct ipv6hdr *iph = ipv6_hdr(skb);
+ 	struct tcphdr *th = tcp_hdr(skb);
+ 
++	if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++		skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++		skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++		__skb_incr_checksum_unnecessary(skb);
++
++		return 0;
++	}
++
+ 	th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ 				  &iph->daddr, 0);
+ 	skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -40,6 +92,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ 	return 0;
+ }
+ 
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++				     __be16 *oldport, __be16 newport)
++{
++	struct tcphdr *th;
++
++	if (*oldport == newport)
++		return;
++
++	th = tcp_hdr(seg);
++	inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++	*oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++	const struct tcphdr *th;
++	const struct ipv6hdr *iph;
++	struct sk_buff *seg;
++	struct tcphdr *th2;
++	struct ipv6hdr *iph2;
++
++	seg = segs;
++	th = tcp_hdr(seg);
++	iph = ipv6_hdr(seg);
++	th2 = tcp_hdr(seg->next);
++	iph2 = ipv6_hdr(seg->next);
++
++	if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++	    ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++	    ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++		return segs;
++
++	while ((seg = seg->next)) {
++		th2 = tcp_hdr(seg);
++		iph2 = ipv6_hdr(seg);
++
++		iph2->saddr = iph->saddr;
++		iph2->daddr = iph->daddr;
++		__tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++		__tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++	}
++
++	return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++					      netdev_features_t features)
++{
++	skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++	if (IS_ERR(skb))
++		return skb;
++
++	return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ 					netdev_features_t features)
+ {
+@@ -51,6 +158,9 @@ static struct sk_buff *tcp6_gso_segment(
+ 	if (!pskb_may_pull(skb, sizeof(*th)))
+ 		return ERR_PTR(-EINVAL);
+ 
++	if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++		return __tcp6_gso_segment_list(skb, features);
++
+ 	if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ 		const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ 		struct tcphdr *th = tcp_hdr(skb);
diff --git a/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index e54dcdadbb..07e923b69e 100644
--- a/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-6.6/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -8260,7 +8260,7 @@ static int nft_register_flowtable_net_ho
+@@ -8268,7 +8268,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index e73cf9a899..ca5fe771d1 100644
--- a/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-6.6/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4981,6 +4981,8 @@ static int mtk_probe(struct platform_dev
+@@ -4984,6 +4984,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
index 05711780f5..2e5d956437 100644
--- a/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
+++ b/target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
 --- a/net/bridge/br_input.c
 +++ b/net/bridge/br_input.c
-@@ -362,6 +362,8 @@ static rx_handler_result_t br_handle_fra
+@@ -367,6 +367,8 @@ static rx_handler_result_t br_handle_fra
  		fwd_mask |= p->group_fwd_mask;
  		switch (dest[5]) {
  		case 0x00:	/* Bridge Group Address */
@@ -134,7 +134,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		return -EMSGSIZE;
  
  	timerval = br_timer_value(&p->message_age_timer);
-@@ -901,6 +903,7 @@ static const struct nla_policy br_port_p
+@@ -902,6 +904,7 @@ static const struct nla_policy br_port_p
  	[IFLA_BRPORT_MCAST_MAX_GROUPS] = { .type = NLA_U32 },
  	[IFLA_BRPORT_NEIGH_VLAN_SUPPRESS] = NLA_POLICY_MAX(NLA_U8, 1),
  	[IFLA_BRPORT_BACKUP_NHID] = { .type = NLA_U32 },
@@ -142,7 +142,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  /* Change the state of the port and notify spanning tree */
-@@ -969,6 +972,7 @@ static int br_setport(struct net_bridge_
+@@ -970,6 +973,7 @@ static int br_setport(struct net_bridge_
  	br_set_port_flag(p, tb, IFLA_BRPORT_MAB, BR_PORT_MAB);
  	br_set_port_flag(p, tb, IFLA_BRPORT_NEIGH_VLAN_SUPPRESS,
  			 BR_NEIGH_VLAN_SUPPRESS);
diff --git a/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
index 1d30a19654..0e9affd16a 100644
--- a/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
+++ b/target/linux/generic/pending-6.6/730-net-phy-realtek-detect-early-version-of-RTL8221B.patch
@@ -1,4 +1,4 @@
-From e52faf1564a8bcaf866f9a6c7bf0e8a8748afb15 Mon Sep 17 00:00:00 2001
+From 0de82310d2b32e78ff79d42c08b1122a6ede3778 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
 Date: Sun, 30 Apr 2023 00:15:41 +0100
 Subject: [PATCH] net: phy: realtek: detect early version of RTL8221B
@@ -10,9 +10,6 @@ Implement custom identify function using the PKGID instead of iterating
 over the implemented MMDs.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/realtek.c | 50 ++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 49 insertions(+), 1 deletion(-)
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
@@ -20,12 +17,12 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define RTL_GENERIC_PHYID			0x001cc800
  #define RTL_8211FVD_PHYID			0x001cc878
-+#define RTL_8221B_VB_CG				0x001cc849
++#define RTL_8221B_VB_CG_PHYID			0x001cc849
  
  MODULE_DESCRIPTION("Realtek PHY driver");
  MODULE_AUTHOR("Johnson Leung");
-@@ -801,6 +802,54 @@ static int rtl822x_probe(struct phy_devi
- 	return 0;
+@@ -782,6 +783,38 @@ static int rtl8226_match_phy_device(stru
+ 	       rtlgen_supports_2_5gbps(phydev);
  }
  
 +static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev)
@@ -33,14 +30,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	int val;
 +	u32 id;
 +
-+	if (phydev->is_c45) {
-+		if (phydev->c45_ids.device_ids[1])
-+			return phydev->c45_ids.device_ids[1] == RTL_8221B_VB_CG;
-+	} else {
-+		if (phydev->phy_id)
-+			return phydev->phy_id == RTL_8221B_VB_CG;
-+	}
-+
 +	if (phydev->mdio.bus->read_c45) {
 +		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PKGID1);
 +		if (val < 0)
@@ -65,21 +54,13 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		id |= val;
 +	}
 +
-+	if (id != RTL_8221B_VB_CG)
-+		return 0;
-+
-+	if (phydev->is_c45)
-+		phydev->c45_ids.device_ids[1] = id;
-+	else
-+		phydev->phy_id = id;
-+
-+	return 1;
++	return (id == RTL_8221B_VB_CG_PHYID);
 +}
 +
- static int rtlgen_resume(struct phy_device *phydev)
+ static int rtl822x_probe(struct phy_device *phydev)
  {
- 	int ret = genphy_resume(phydev);
-@@ -1134,7 +1183,7 @@ static struct phy_driver realtek_drvs[]
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -1134,7 +1167,7 @@ static struct phy_driver realtek_drvs[]
  		.write_page     = rtl821x_write_page,
  		.soft_reset     = genphy_soft_reset,
  	}, {
diff --git a/target/linux/generic/pending-6.6/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch b/target/linux/generic/pending-6.6/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
index f92f60f349..1f07c0f62c 100644
--- a/target/linux/generic/pending-6.6/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
+++ b/target/linux/generic/pending-6.6/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
@@ -17,7 +17,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2245,7 +2245,7 @@ struct net_device {
+@@ -2243,7 +2243,7 @@ struct net_device {
  #if IS_ENABLED(CONFIG_AX25)
  	void			*ax25_ptr;
  #endif
diff --git a/target/linux/generic/pending-6.6/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch b/target/linux/generic/pending-6.6/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch
index decf647bce..36abf45798 100644
--- a/target/linux/generic/pending-6.6/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch
+++ b/target/linux/generic/pending-6.6/732-00-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch
@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1326,6 +1326,22 @@ struct mtk_mac {
+@@ -1329,6 +1329,22 @@ struct mtk_mac {
  /* the struct describing the SoC. these are declared in the soc_xyz.c files */
  extern const struct of_device_id of_mtk_match[];
  
@@ -34,7 +34,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
  {
  	return eth->soc->version == 1;
-@@ -1340,6 +1356,7 @@ static inline bool mtk_is_netsys_v3_or_g
+@@ -1343,6 +1359,7 @@ static inline bool mtk_is_netsys_v3_or_g
  {
  	return eth->soc->version > 2;
  }
diff --git a/target/linux/generic/pending-6.6/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-6.6/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index a64561bf92..438f83953a 100644
--- a/target/linux/generic/pending-6.6/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-6.6/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -24,7 +24,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #include <net/page_pool/helpers.h>
  
  #include "mtk_eth_soc.h"
-@@ -1578,12 +1579,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1581,12 +1582,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -53,7 +53,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1605,6 +1622,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1608,6 +1625,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -72,7 +72,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1620,8 +1649,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1623,8 +1652,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.6/733-01-net-ethernet-mtk_eth_soc-use-napi_build_skb.patch b/target/linux/generic/pending-6.6/733-01-net-ethernet-mtk_eth_soc-use-napi_build_skb.patch
new file mode 100644
index 0000000000..1fe291fce9
--- /dev/null
+++ b/target/linux/generic/pending-6.6/733-01-net-ethernet-mtk_eth_soc-use-napi_build_skb.patch
@@ -0,0 +1,30 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Mon, 20 May 2024 14:29:58 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: use napi_build_skb()
+
+The napi_build_skb() can reuse the skb in skb cache per CPU or
+can allocate skbs in bulk, which helps improve the performance.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -2123,7 +2123,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			if (ret != XDP_PASS)
+ 				goto skip_rx;
+ 
+-			skb = build_skb(data, PAGE_SIZE);
++			skb = napi_build_skb(data, PAGE_SIZE);
+ 			if (unlikely(!skb)) {
+ 				page_pool_put_full_page(ring->page_pool,
+ 							page, true);
+@@ -2161,7 +2161,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
+ 					 ring->buf_size, DMA_FROM_DEVICE);
+ 
+-			skb = build_skb(data, ring->frag_size);
++			skb = napi_build_skb(data, ring->frag_size);
+ 			if (unlikely(!skb)) {
+ 				netdev->stats.rx_dropped++;
+ 				skb_free_frag(data);
diff --git a/target/linux/generic/pending-6.6/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.6/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
index aedeedece9..ba7699ecad 100644
--- a/target/linux/generic/pending-6.6/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
+++ b/target/linux/generic/pending-6.6/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -490,7 +490,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	.mac_finish = mtk_mac_finish,
  	.mac_link_down = mtk_mac_link_down,
  	.mac_link_up = mtk_mac_link_up,
-@@ -3390,6 +3531,9 @@ static int mtk_open(struct net_device *d
+@@ -3393,6 +3534,9 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -500,7 +500,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
  		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3519,6 +3663,9 @@ static int mtk_stop(struct net_device *d
+@@ -3522,6 +3666,9 @@ static int mtk_stop(struct net_device *d
  	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
  		mtk_ppe_stop(eth->ppe[i]);
  
@@ -510,7 +510,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return 0;
  }
  
-@@ -4516,6 +4663,7 @@ static const struct net_device_ops mtk_n
+@@ -4519,6 +4666,7 @@ static const struct net_device_ops mtk_n
  static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  {
  	const __be32 *_id = of_get_property(np, "reg", NULL);
@@ -518,7 +518,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phy_interface_t phy_mode;
  	struct phylink *phylink;
  	struct mtk_mac *mac;
-@@ -4552,16 +4700,41 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4555,16 +4703,41 @@ static int mtk_add_mac(struct mtk_eth *e
  	mac->id = id;
  	mac->hw = eth;
  	mac->of_node = np;
@@ -568,7 +568,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
-@@ -4644,8 +4817,21 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4647,8 +4820,21 @@ static int mtk_add_mac(struct mtk_eth *e
  		phy_interface_zero(mac->phylink_config.supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  mac->phylink_config.supported_interfaces);
@@ -590,7 +590,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4696,6 +4882,26 @@ free_netdev:
+@@ -4699,6 +4885,26 @@ free_netdev:
  	return err;
  }
  
@@ -617,7 +617,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
  {
  	struct net_device *dev, *tmp;
-@@ -4842,7 +5048,8 @@ static int mtk_probe(struct platform_dev
+@@ -4845,7 +5051,8 @@ static int mtk_probe(struct platform_dev
  			regmap_write(cci, 0, 3);
  	}
  
@@ -627,7 +627,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		err = mtk_sgmii_init(eth);
  
  		if (err)
-@@ -4953,6 +5160,24 @@ static int mtk_probe(struct platform_dev
+@@ -4956,6 +5163,24 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
@@ -652,7 +652,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
  		err = devm_request_irq(eth->dev, eth->irq[0],
  				       mtk_handle_irq, 0,
-@@ -5055,6 +5280,11 @@ static int mtk_remove(struct platform_de
+@@ -5058,6 +5283,11 @@ static int mtk_remove(struct platform_de
  		mtk_stop(eth->netdev[i]);
  		mac = netdev_priv(eth->netdev[i]);
  		phylink_disconnect_phy(mac->phylink);
@@ -893,7 +893,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  struct mtk_tx_dma_desc_info {
  	dma_addr_t	addr;
-@@ -1314,6 +1371,9 @@ struct mtk_mac {
+@@ -1317,6 +1374,9 @@ struct mtk_mac {
  	struct device_node		*of_node;
  	struct phylink			*phylink;
  	struct phylink_config		phylink_config;
@@ -903,7 +903,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	struct mtk_eth			*hw;
  	struct mtk_hw_stats		*hw_stats;
  	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
-@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1440,6 +1500,19 @@ static inline u32 mtk_get_ib2_multicast_
  	return MTK_FOE_IB2_MULTICAST;
  }
  
@@ -923,7 +923,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* read the hardware status register */
  void mtk_stats_update_mac(struct mtk_mac *mac);
  
-@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1448,8 +1521,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
  u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
  
  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
diff --git a/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
index e4fbf1f870..726f66cf64 100644
--- a/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
+++ b/target/linux/generic/pending-6.6/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch
@@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -1026,6 +1026,51 @@ static int rtl8221b_config_init(struct p
+@@ -1010,6 +1010,51 @@ static int rtl8221b_config_init(struct p
  	return 0;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
  static struct phy_driver realtek_drvs[] = {
  	{
  		PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1188,6 +1233,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1172,6 +1217,8 @@ static struct phy_driver realtek_drvs[]
  		.get_features   = rtl822x_get_features,
  		.config_init    = rtl8221b_config_init,
  		.config_aneg    = rtl822x_config_aneg,
diff --git a/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch b/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch
new file mode 100644
index 0000000000..500567b4ed
--- /dev/null
+++ b/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch
@@ -0,0 +1,45 @@
+From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001
+Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 7 May 2024 22:43:30 +0100
+Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set
+ manually
+To: Andrew Lunn <andrew@lunn.ch>,
+    Heiner Kallweit <hkallweit1@gmail.com>,
+    Russell King <linux@armlinux.org.uk>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    SkyLake Huang <skylake.huang@mediatek.com>,
+    Eric Woudstra <ericwouds@gmail.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org
+
+Setting LED_OFF via the brightness_set should deactivate hw control,
+so make sure netdev trigger rules also get cleared in that case.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+This is basically a stop-gap measure until unified LED handling has
+been implemented accross all MediaTek and Airoha PHYs.
+See also
+https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/
+
+ drivers/net/phy/air_en8811h.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_
+ 
+ 	changed |= (priv->led[index].rules != 0);
+ 
++	/* clear netdev trigger rules in case LED_OFF has been set */
++	if (!on)
++		priv->led[index].rules = 0;
++
+ 	if (changed)
+ 		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
+ 				      AIR_PHY_LED_ON(index),
diff --git a/target/linux/generic/pending-6.6/743-net-phy-aquantia-add-support-for-PHY-LEDs.patch b/target/linux/generic/pending-6.6/743-net-phy-aquantia-add-support-for-PHY-LEDs.patch
new file mode 100644
index 0000000000..ca3a2b5c87
--- /dev/null
+++ b/target/linux/generic/pending-6.6/743-net-phy-aquantia-add-support-for-PHY-LEDs.patch
@@ -0,0 +1,368 @@
+From c6a1759365fc35463138a7d9e335ee53f384b8df Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 10 May 2024 02:53:52 +0100
+Subject: [PATCH] net: phy: aquantia: add support for PHY LEDs
+
+Aquantia Ethernet PHYs got 3 LED output pins which are typically used
+to indicate link status and activity.
+Add a minimal LED controller driver supporting the most common uses
+with the 'netdev' trigger as well as software-driven forced control of
+the LEDs.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/aquantia/Makefile        |   3 +
+ drivers/net/phy/aquantia/aquantia.h      |  84 +++++++++++++
+ drivers/net/phy/aquantia/aquantia_leds.c | 152 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 127 +++++++++++++------
+ 4 files changed, 329 insertions(+), 37 deletions(-)
+ create mode 100644 drivers/net/phy/aquantia/aquantia_leds.c
+
+--- a/drivers/net/phy/aquantia/Makefile
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -3,4 +3,7 @@ aquantia-objs			+= aquantia_main.o aquan
+ ifdef CONFIG_HWMON
+ aquantia-objs			+= aquantia_hwmon.o
+ endif
++ifdef CONFIG_PHYLIB_LEDS
++aquantia-objs			+= aquantia_leds.o
++endif
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -62,6 +62,26 @@
+ #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
+ #define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
++
++#define AQR_NUM_LEDS				3
++
++#define VEND1_GLOBAL_LED_PROV			0xc430
++#define AQR_LED_PROV(x)				(VEND1_GLOBAL_LED_PROV + x)
++#define VEND1_GLOBAL_LED_PROV_ACT_STRETCH	GENMASK(0, 1)
++#define VEND1_GLOBAL_LED_PROV_TX_ACT		BIT(2)
++#define VEND1_GLOBAL_LED_PROV_RX_ACT		BIT(3)
++#define VEND1_GLOBAL_LED_PROV_LINK_MASK		(GENMASK(15, 14) | GENMASK(8, 5))
++#define VEND1_GLOBAL_LED_PROV_LINK100		BIT(5)
++#define VEND1_GLOBAL_LED_PROV_LINK1000		BIT(6)
++#define VEND1_GLOBAL_LED_PROV_LINK10000		BIT(7)
++#define VEND1_GLOBAL_LED_PROV_FORCE_ON		BIT(8)
++#define VEND1_GLOBAL_LED_PROV_LINK2500		BIT(14)
++#define VEND1_GLOBAL_LED_PROV_LINK5000		BIT(15)
++
++#define VEND1_GLOBAL_LED_DRIVE			0xc438
++#define VEND1_GLOBAL_LED_DRIVE_VDD		BIT(1)
++#define AQR_LED_DRIVE(x)			(VEND1_GLOBAL_LED_DRIVE + x)
++
+ #define VEND1_THERMAL_STAT1			0xc820
+ #define VEND1_THERMAL_STAT2			0xc821
+ #define VEND1_THERMAL_STAT2_VALID		BIT(0)
+@@ -115,3 +135,23 @@ static inline int aqr_hwmon_probe(struct
+ #endif
+ 
+ int aqr_firmware_load(struct phy_device *phydev);
++
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index,
++			 unsigned long *delay_on,
++			 unsigned long *delay_off);
++
++int aqr_phy_led_brightness_set(struct phy_device *phydev,
++			       u8 index, enum led_brightness value);
++
++int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				unsigned long rules);
++
++int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++			       unsigned long *rules);
++
++int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++			       unsigned long rules);
++
++int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes);
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_leds.c
+@@ -0,0 +1,140 @@
++// SPDX-License-Identifier: GPL-2.0
++/* LED driver for Aquantia PHY
++ *
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/phy.h>
++
++#include "aquantia.h"
++
++int aqr_phy_led_brightness_set(struct phy_device *phydev,
++			       u8 index, enum led_brightness value)
++{
++	if (index > 2)
++		return -EINVAL;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), VEND1_GLOBAL_LED_PROV_LINK_MASK |
++						    VEND1_GLOBAL_LED_PROV_FORCE_ON |
++						    VEND1_GLOBAL_LED_PROV_RX_ACT |
++						    VEND1_GLOBAL_LED_PROV_TX_ACT,
++						    value ? VEND1_GLOBAL_LED_PROV_FORCE_ON : 0);
++}
++
++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK)        |
++						 BIT(TRIGGER_NETDEV_LINK_100)    |
++						 BIT(TRIGGER_NETDEV_LINK_1000)   |
++						 BIT(TRIGGER_NETDEV_LINK_2500)   |
++						 BIT(TRIGGER_NETDEV_LINK_5000)   |
++						 BIT(TRIGGER_NETDEV_LINK_10000)  |
++						 BIT(TRIGGER_NETDEV_RX)          |
++						 BIT(TRIGGER_NETDEV_TX));
++
++int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				unsigned long rules)
++{
++	if (index >= AQR_NUM_LEDS)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~supported_triggers)
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++			       unsigned long *rules)
++{
++	int val;
++
++	if (index >= AQR_NUM_LEDS)
++		return -EINVAL;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index));
++	if (val < 0)
++		return val;
++
++	*rules = 0;
++	if (val & VEND1_GLOBAL_LED_PROV_LINK100)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++	if (val & VEND1_GLOBAL_LED_PROV_LINK1000)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++	if (val & VEND1_GLOBAL_LED_PROV_LINK2500)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_2500);
++
++	if (val & VEND1_GLOBAL_LED_PROV_LINK5000)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_5000);
++
++	if (val & VEND1_GLOBAL_LED_PROV_LINK10000)
++		*rules |= BIT(TRIGGER_NETDEV_LINK_10000);
++
++	if (val & VEND1_GLOBAL_LED_PROV_RX_ACT)
++		*rules |= BIT(TRIGGER_NETDEV_RX);
++
++	if (val & VEND1_GLOBAL_LED_PROV_TX_ACT)
++		*rules |= BIT(TRIGGER_NETDEV_TX);
++
++	return 0;
++}
++
++int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++			       unsigned long rules)
++{
++	u16 val = 0;
++
++	if (index >= AQR_NUM_LEDS)
++		return -EINVAL;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++		val |= VEND1_GLOBAL_LED_PROV_LINK100;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++		val |= VEND1_GLOBAL_LED_PROV_LINK1000;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++		val |= VEND1_GLOBAL_LED_PROV_LINK2500;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_5000) | BIT(TRIGGER_NETDEV_LINK)))
++		val |= VEND1_GLOBAL_LED_PROV_LINK5000;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10000) | BIT(TRIGGER_NETDEV_LINK)))
++		val |= VEND1_GLOBAL_LED_PROV_LINK10000;
++
++	if (rules & BIT(TRIGGER_NETDEV_RX))
++		val |= VEND1_GLOBAL_LED_PROV_RX_ACT;
++
++	if (rules & BIT(TRIGGER_NETDEV_TX))
++		val |= VEND1_GLOBAL_LED_PROV_TX_ACT;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
++						    VEND1_GLOBAL_LED_PROV_LINK_MASK |
++						    VEND1_GLOBAL_LED_PROV_FORCE_ON |
++						    VEND1_GLOBAL_LED_PROV_RX_ACT |
++						    VEND1_GLOBAL_LED_PROV_TX_ACT, val);
++}
++
++int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes)
++{
++	bool active_low = false;
++	u32 mode;
++
++	if (index >= AQR_NUM_LEDS)
++		return -EINVAL;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++		return -EINVAL;
++		}
++	}
++
++	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
++			      VEND1_GLOBAL_LED_DRIVE_VDD,
++			      active_low ? VEND1_GLOBAL_LED_DRIVE_VDD : 0);
++}
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -740,6 +740,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+@@ -759,6 +766,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
+@@ -778,6 +792,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
+@@ -797,6 +818,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+@@ -823,6 +851,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
+@@ -841,6 +876,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
+@@ -860,6 +902,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings    = aqr107_get_strings,
+ 	.get_stats      = aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+@@ -879,6 +928,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings    = aqr107_get_strings,
+ 	.get_stats      = aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
+@@ -898,6 +954,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings    = aqr107_get_strings,
+ 	.get_stats      = aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+@@ -917,6 +980,13 @@ static struct phy_driver aqr_driver[] =
+ 	.get_strings	= aqr107_get_strings,
+ 	.get_stats	= aqr107_get_stats,
+ 	.link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++	.led_brightness_set = aqr_phy_led_brightness_set,
++	.led_hw_is_supported = aqr_phy_led_hw_is_supported,
++	.led_hw_control_set = aqr_phy_led_hw_control_set,
++	.led_hw_control_get = aqr_phy_led_hw_control_get,
++	.led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ };
+ 
diff --git a/target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
deleted file mode 100644
index c811e40d49..0000000000
--- a/target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
+++ /dev/null
@@ -1,1115 +0,0 @@
-From patchwork Tue Feb  6 19:47:51 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
-X-Patchwork-Id: 13547762
-X-Patchwork-Delegate: kuba@kernel.org
-From: Eric Woudstra <ericwouds@gmail.com>
-To: "David S. Miller" <davem@davemloft.net>,
-	Eric Dumazet <edumazet@google.com>,
-	Jakub Kicinski <kuba@kernel.org>,
-	Paolo Abeni <pabeni@redhat.com>,
-	Rob Herring <robh+dt@kernel.org>,
-	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
-	Conor Dooley <conor+dt@kernel.org>,
-	Andrew Lunn <andrew@lunn.ch>,
-	Heiner Kallweit <hkallweit1@gmail.com>,
-	Russell King <linux@armlinux.org.uk>,
-	Matthias Brugger <matthias.bgg@gmail.com>,
-	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-	"Frank Wunderlich" <frank-w@public-files.de>,
-	Daniel Golle <daniel@makrotopia.org>,
-	Lucien Jheng  <lucien.jheng@airoha.com>,
-	Zhi-Jun You <hujy652@protonmail.com>
-Cc: netdev@vger.kernel.org,
-	devicetree@vger.kernel.org,
-	Eric Woudstra <ericwouds@gmail.com>
-Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
- PHY driver
-Date: Tue,  6 Feb 2024 20:47:51 +0100
-Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
-X-Mailer: git-send-email 2.42.1
-In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
-References: <20240206194751.1901802-1-ericwouds@gmail.com>
-Precedence: bulk
-X-Mailing-List: netdev@vger.kernel.org
-List-Id: <netdev.vger.kernel.org>
-List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
-List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
-MIME-Version: 1.0
-X-Patchwork-Delegate: kuba@kernel.org
-
-* Source originated from airoha's en8811h v1.2.1 driver
- * Moved air_en8811h.h to air_en8811h.c
- * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
- * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
- * Added .get_rate_matching()
- * Use generic phy_read/write() and phy_read/write_mmd()
- * Edited .get_features() to use generic C45 functions
- * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
- * Use led handling functions from mediatek-ge-soc.c
- * Simplified led handling by storing led rules
- * Cleanup macro definitions
- * Cleanup code to pass checkpatch.pl
- * General code cleanup
-
-Changes from original RFC patch:
-
- * Use the correct order in Kconfig and Makefile
- * Change some register naming to correspond with datasheet
- * Use phy_driver .read_page() and .write_page()
- * Use module_phy_driver()
- * Use get_unaligned_le16() instead of macro
- * In .config_aneg() and .read_status() use genphy_xxx() C22
- * Use another vendor register to read real speed
- * Load firmware only once and store firmware version
- * Apply 2.5G LPA work-around (firmware before 24011202)
- * Read 2.5G LPA from vendor register (firmware 24011202 and later)
-
-Changes to be committed:
-	modified:   drivers/net/phy/Kconfig
-	modified:   drivers/net/phy/Makefile
-	new file:   drivers/net/phy/air_en8811h.c
-
-Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
----
- drivers/net/phy/Kconfig       |    5 +
- drivers/net/phy/Makefile      |    1 +
- drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
- 3 files changed, 1012 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -68,6 +68,11 @@ config SFP
- 
- comment "MII PHY device drivers"
- 
-+config AIR_EN8811H_PHY
-+	tristate "Airoha EN8811H 2.5 Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8811H PHY.
-+
- config AMD_PHY
- 	tristate "AMD and Altima PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -34,6 +34,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
- 
- obj-$(CONFIG_ADIN_PHY)		+= adin.o
- obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
-+obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
- obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
---- /dev/null
-+++ b/drivers/net/phy/air_en8811h.c
-@@ -0,0 +1,1006 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Driver for Airoha Ethernet PHYs
-+ *
-+ * Currently supporting the EN8811H.
-+ *
-+ * Limitations of the EN8811H:
-+ * - Only full duplex supported
-+ * - Forced speed (AN off) is not supported by hardware (100Mbps)
-+ *
-+ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
-+ *
-+ * Copyright (C) 2023 Airoha Technology Corp.
-+ */
-+
-+#include <linux/phy.h>
-+#include <linux/firmware.h>
-+#include <linux/property.h>
-+#include <asm/unaligned.h>
-+
-+#define EN8811H_PHY_ID		0x03a2a411
-+
-+#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
-+#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
-+
-+#define AIR_FW_ADDR_DM	0x00000000
-+#define AIR_FW_ADDR_DSP	0x00100000
-+
-+/* u32 (DWORD) component macros */
-+#define LOWORD(d) ((u16)(u32)(d))
-+#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
-+
-+/* MII Registers */
-+#define AIR_AUX_CTRL_STATUS	0x1d
-+#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
-+#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
-+#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
-+#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
-+
-+#define AIR_EXT_PAGE_ACCESS		0x1f
-+#define   AIR_PHY_PAGE_STANDARD			0x0000
-+#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
-+
-+/* MII Registers Page 4*/
-+#define AIR_PBUS_MODE			0x10
-+#define   AIR_PBUS_MODE_ADDR_FIXED		0x0000
-+#define   AIR_PBUS_MODE_ADDR_INCR		BIT(15)
-+#define AIR_PBUS_WR_ADDR_HIGH		0x11
-+#define AIR_PBUS_WR_ADDR_LOW		0x12
-+#define AIR_PBUS_WR_DATA_HIGH		0x13
-+#define AIR_PBUS_WR_DATA_LOW		0x14
-+#define AIR_PBUS_RD_ADDR_HIGH		0x15
-+#define AIR_PBUS_RD_ADDR_LOW		0x16
-+#define AIR_PBUS_RD_DATA_HIGH		0x17
-+#define AIR_PBUS_RD_DATA_LOW		0x18
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define EN8811H_PHY_FW_STATUS		0x8009
-+#define   EN8811H_PHY_READY			0x02
-+
-+#define AIR_PHY_HOST_CMD_1		0x800c
-+#define AIR_PHY_HOST_CMD_1_MODE1		0x0
-+#define AIR_PHY_HOST_CMD_2		0x800d
-+#define AIR_PHY_HOST_CMD_2_MODE1		0x0
-+#define AIR_PHY_HOST_CMD_3		0x800e
-+#define AIR_PHY_HOST_CMD_3_MODE1		0x1101
-+#define AIR_PHY_HOST_CMD_3_DOCMD		0x1100
-+#define AIR_PHY_HOST_CMD_4		0x800f
-+#define AIR_PHY_HOST_CMD_4_MODE1		0x0002
-+#define AIR_PHY_HOST_CMD_4_INTCLR		0x00e4
-+
-+/* Registers on MDIO_MMD_VEND2 */
-+#define AIR_PHY_LED_BCR			0x021
-+#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
-+#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
-+#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
-+#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
-+
-+#define AIR_PHY_LED_DUR_ON		0x022
-+
-+#define AIR_PHY_LED_DUR_BLINK		0x023
-+
-+#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
-+#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
-+#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
-+#define   AIR_PHY_LED_ON_LINK100		BIT(1)
-+#define   AIR_PHY_LED_ON_LINK10			BIT(2)
-+#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
-+#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
-+#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
-+#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
-+#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
-+#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
-+#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
-+
-+#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
-+#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
-+#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
-+#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
-+#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
-+#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
-+#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
-+#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
-+#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
-+#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
-+#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
-+#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
-+#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
-+
-+/* Registers on BUCKPBUS */
-+#define EN8811H_2P5G_LPA		0x3b30
-+#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
-+
-+#define EN8811H_FW_VERSION		0x3b3c
-+
-+#define EN8811H_POLARITY		0xca0f8
-+#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
-+#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
-+
-+#define EN8811H_GPIO_OUTPUT		0xcf8b8
-+#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
-+
-+#define EN8811H_FW_CTRL_1		0x0f0018
-+#define   EN8811H_FW_CTRL_1_START		0x0
-+#define   EN8811H_FW_CTRL_1_FINISH		0x1
-+#define EN8811H_FW_CTRL_2		0x800000
-+#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
-+
-+#define EN8811H_LED_COUNT	3
-+
-+/* GPIO5  <-> BASE_T_LED0
-+ * GPIO4  <-> BASE_T_LED1
-+ * GPIO3  <-> BASE_T_LED2
-+ *
-+ * Default setup suitable for 2 leds connected:
-+ *    100M link up triggers led0, only led0 blinking on traffic
-+ *   1000M link up triggers led1, only led1 blinking on traffic
-+ *   2500M link up triggers led0 and led1, both blinking on traffic
-+ * Also suitable for 1 led connected:
-+ *     any link up triggers led2
-+ */
-+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+				  BIT(TRIGGER_NETDEV_LINK_100)  | \
-+				  BIT(TRIGGER_NETDEV_RX)        | \
-+				  BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+				  BIT(TRIGGER_NETDEV_LINK_1000) | \
-+				  BIT(TRIGGER_NETDEV_RX)        | \
-+				  BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED2  BIT(TRIGGER_NETDEV_LINK)
-+
-+struct led {
-+	unsigned long rules;
-+	unsigned long state;
-+};
-+
-+struct en8811h_priv {
-+	u32		firmware_version;
-+	struct led	led[EN8811H_LED_COUNT];
-+};
-+
-+enum {
-+	AIR_PHY_LED_STATE_FORCE_ON,
-+	AIR_PHY_LED_STATE_FORCE_BLINK,
-+};
-+
-+enum {
-+	AIR_PHY_LED_DUR_BLINK_32M,
-+	AIR_PHY_LED_DUR_BLINK_64M,
-+	AIR_PHY_LED_DUR_BLINK_128M,
-+	AIR_PHY_LED_DUR_BLINK_256M,
-+	AIR_PHY_LED_DUR_BLINK_512M,
-+	AIR_PHY_LED_DUR_BLINK_1024M,
-+};
-+
-+enum {
-+	AIR_LED_DISABLE,
-+	AIR_LED_ENABLE,
-+};
-+
-+enum {
-+	AIR_ACTIVE_LOW,
-+	AIR_ACTIVE_HIGH,
-+};
-+
-+enum {
-+	AIR_LED_MODE_DISABLE,
-+	AIR_LED_MODE_USER_DEFINE,
-+};
-+
-+#define AIR_PHY_LED_DUR_UNIT	1024
-+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
-+
-+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+					       BIT(TRIGGER_NETDEV_LINK)        |
-+					       BIT(TRIGGER_NETDEV_LINK_10)     |
-+					       BIT(TRIGGER_NETDEV_LINK_100)    |
-+					       BIT(TRIGGER_NETDEV_LINK_1000)   |
-+					       BIT(TRIGGER_NETDEV_LINK_2500)   |
-+					       BIT(TRIGGER_NETDEV_RX)          |
-+					       BIT(TRIGGER_NETDEV_TX));
-+
-+static int air_phy_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-+}
-+
-+static int air_phy_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-+}
-+
-+static int __air_buckpbus_reg_write(struct phy_device *phydev,
-+				    u32 pbus_address, u32 pbus_data)
-+{
-+	int ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW,  LOWORD(pbus_data));
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int air_buckpbus_reg_write(struct phy_device *phydev,
-+				  u32 pbus_address, u32 pbus_data)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   pbus_address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+;
-+}
-+
-+static int __air_buckpbus_reg_read(struct phy_device *phydev,
-+				   u32 pbus_address, u32 *pbus_data)
-+{
-+	int pbus_data_low, pbus_data_high;
-+	int ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW,  LOWORD(pbus_address));
-+	if (ret < 0)
-+		return ret;
-+
-+	pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
-+	if (pbus_data_high < 0)
-+		return ret;
-+
-+	pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
-+	if (pbus_data_low < 0)
-+		return ret;
-+
-+	*pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
-+	return 0;
-+}
-+
-+static int air_buckpbus_reg_read(struct phy_device *phydev,
-+				 u32 pbus_address, u32 *pbus_data)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   pbus_address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int __air_write_buf(struct phy_device *phydev, u32 address,
-+			   const struct firmware *fw)
-+{
-+	unsigned int offset;
-+	int ret;
-+	u16 val;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(address));
-+	if (ret < 0)
-+		return ret;
-+
-+	for (offset = 0; offset < fw->size; offset += 4) {
-+		val = get_unaligned_le16(&fw->data[offset + 2]);
-+		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
-+		if (ret < 0)
-+			return ret;
-+
-+		val = get_unaligned_le16(&fw->data[offset]);
-+		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int air_write_buf(struct phy_device *phydev, u32 address,
-+			 const struct firmware *fw)
-+{
-+	int ret, saved_page;
-+
-+	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+	ret = __air_write_buf(phydev, address, fw);
-+	if (ret < 0)
-+		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+			   address, ret);
-+
-+	return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int en8811h_load_firmware(struct phy_device *phydev)
-+{
-+	struct device *dev = &phydev->mdio.dev;
-+	const struct firmware *fw1, *fw2;
-+	u32 pbus_value;
-+	int ret;
-+
-+	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_rel1;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_START);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+	pbus_value |= EN8811H_FW_CTRL_2_LOADING;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+	pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_FINISH);
-+	if (ret < 0)
-+		goto en8811h_load_firmware_out;
-+
-+	ret = 0;
-+
-+en8811h_load_firmware_out:
-+	release_firmware(fw2);
-+
-+en8811h_load_firmware_rel1:
-+	release_firmware(fw1);
-+
-+	if (ret < 0)
-+		phydev_err(phydev, "Load firmware failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int en8811h_restart_host(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_START);
-+	if (ret < 0)
-+		return ret;
-+
-+	return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+				     EN8811H_FW_CTRL_1_FINISH);
-+}
-+
-+static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (on)
-+		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+					    &priv->led[index].state);
-+	else
-+		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+					       &priv->led[index].state);
-+
-+	changed |= (priv->led[index].rules != 0);
-+
-+	if (changed)
-+		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
-+				      AIR_PHY_LED_ON(index),
-+				      AIR_PHY_LED_ON_MASK,
-+				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
-+
-+	return 0;
-+}
-+
-+static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+				bool blinking)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (blinking)
-+		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+					    &priv->led[index].state);
-+	else
-+		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+					       &priv->led[index].state);
-+
-+	changed |= (priv->led[index].rules != 0);
-+
-+	if (changed)
-+		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
-+				     AIR_PHY_LED_BLINK(index),
-+				     blinking ?
-+				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
-+	else
-+		return 0;
-+}
-+
-+static int air_led_blink_set(struct phy_device *phydev, u8 index,
-+			     unsigned long *delay_on,
-+			     unsigned long *delay_off)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	bool blinking = false;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+		blinking = true;
-+		*delay_on = 50;
-+		*delay_off = 50;
-+	}
-+
-+	err = air_hw_led_blink_set(phydev, index, blinking);
-+	if (err)
-+		return err;
-+
-+	/* led-blink set, so switch led-on off */
-+	err = air_hw_led_on_set(phydev, index, false);
-+	if (err)
-+		return err;
-+
-+	/* hw-control is off*/
-+	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
-+		priv->led[index].rules = 0;
-+
-+	return 0;
-+}
-+
-+static int air_led_brightness_set(struct phy_device *phydev, u8 index,
-+				  enum led_brightness value)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	/* led-on set, so switch led-blink off */
-+	err = air_hw_led_blink_set(phydev, index, false);
-+	if (err)
-+		return err;
-+
-+	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
-+	if (err)
-+		return err;
-+
-+	/* hw-control is off */
-+	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
-+		priv->led[index].rules = 0;
-+
-+	return 0;
-+}
-+
-+static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
-+				  unsigned long *rules)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	*rules = priv->led[index].rules;
-+
-+	return 0;
-+};
-+
-+static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
-+				  unsigned long rules)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	u16 on = 0, blink = 0;
-+	int ret;
-+
-+	priv->led[index].rules = rules;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_10)   | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK10;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_10RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_10TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_100)  | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK100;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_100RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_100TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK1000;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_1000RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_1000TX;
-+	}
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
-+		on |= AIR_PHY_LED_ON_LINK2500;
-+		if (rules & BIT(TRIGGER_NETDEV_RX))
-+			blink |= AIR_PHY_LED_BLINK_2500RX;
-+		if (rules & BIT(TRIGGER_NETDEV_TX))
-+			blink |= AIR_PHY_LED_BLINK_2500TX;
-+	}
-+
-+	if (on == 0) {
-+		if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+			blink |= AIR_PHY_LED_BLINK_10RX   |
-+				 AIR_PHY_LED_BLINK_100RX  |
-+				 AIR_PHY_LED_BLINK_1000RX |
-+				 AIR_PHY_LED_BLINK_2500RX;
-+		}
-+		if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+			blink |= AIR_PHY_LED_BLINK_10TX   |
-+				 AIR_PHY_LED_BLINK_100TX  |
-+				 AIR_PHY_LED_BLINK_1000TX |
-+				 AIR_PHY_LED_BLINK_2500TX;
-+		}
-+	}
-+
-+	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+		on |= AIR_PHY_LED_ON_FDX;
-+
-+	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+		on |= AIR_PHY_LED_ON_HDX;
-+
-+	if (blink || on) {
-+		/* switch hw-control on, so led-on and led-blink are off */
-+		clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
-+		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
-+	} else {
-+		priv->led[index].rules = 0;
-+	}
-+
-+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+			     AIR_PHY_LED_ON_MASK, on);
-+
-+	if (ret < 0)
-+		return ret;
-+
-+	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
-+			     blink);
-+};
-+
-+static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
-+{
-+	int cl45_data;
-+	int err;
-+
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
-+	if (cl45_data < 0)
-+		return cl45_data;
-+
-+	if (state == AIR_LED_ENABLE)
-+		cl45_data |= AIR_PHY_LED_ON_ENABLE;
-+	else
-+		cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
-+
-+	if (pol == AIR_ACTIVE_HIGH)
-+		cl45_data |= AIR_PHY_LED_ON_POLARITY;
-+	else
-+		cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
-+
-+	err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+			    cl45_data);
-+	if (err < 0)
-+		return err;
-+
-+	return 0;
-+}
-+
-+static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	int cl45_data = dur;
-+	int ret, i;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
-+			    cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	cl45_data >>= 1;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
-+			    cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
-+	if (cl45_data < 0)
-+		return cl45_data;
-+
-+	switch (mode) {
-+	case AIR_LED_MODE_DISABLE:
-+		cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
-+		cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
-+		break;
-+	case AIR_LED_MODE_USER_DEFINE:
-+		cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
-+		cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
-+		break;
-+	default:
-+		phydev_err(phydev, "LED mode %d is not supported\n", mode);
-+		return -EINVAL;
-+	}
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
-+	if (ret < 0)
-+		return ret;
-+
-+	for (i = 0; i < num; ++i) {
-+		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
-+		if (ret < 0) {
-+			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
-+			return ret;
-+		}
-+		air_led_hw_control_set(phydev, i, priv->led[i].rules);
-+	}
-+
-+	return 0;
-+}
-+
-+static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+				       unsigned long rules)
-+{
-+	if (index >= EN8811H_LED_COUNT)
-+		return -EINVAL;
-+
-+	/* All combinations of the supported triggers are allowed */
-+	if (rules & ~en8811h_led_trig)
-+		return -EOPNOTSUPP;
-+
-+	return 0;
-+};
-+
-+static int en8811h_probe(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv;
-+
-+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
-+			    GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
-+	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
-+	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
-+
-+	phydev->priv = priv;
-+
-+	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
-+	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-+
-+	return 0;
-+}
-+
-+static int en8811h_config_init(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	struct device *dev = &phydev->mdio.dev;
-+	int ret, pollret, reg_value;
-+	u32 pbus_value;
-+
-+	if (!priv->firmware_version)
-+		ret = en8811h_load_firmware(phydev);
-+	else
-+		ret = en8811h_restart_host(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Because of mdio-lock, may have to wait for multiple loads */
-+	pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+					    EN8811H_PHY_FW_STATUS, reg_value,
-+					    reg_value == EN8811H_PHY_READY,
-+					    20000, 7500000, true);
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (pollret || !pbus_value) {
-+		phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
-+		return -ENODEV;
-+	}
-+
-+	if (!priv->firmware_version) {
-+		phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
-+		priv->firmware_version = pbus_value;
-+	}
-+
-+	/* Select mode 1, the only mode supported */
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
-+			    AIR_PHY_HOST_CMD_1_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
-+			    AIR_PHY_HOST_CMD_2_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+			    AIR_PHY_HOST_CMD_3_MODE1);
-+	if (ret < 0)
-+		return ret;
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+			    AIR_PHY_HOST_CMD_4_MODE1);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Serdes polarity */
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
-+		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
-+	else
-+		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
-+	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
-+		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
-+	else
-+		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
-+			    AIR_LED_MODE_USER_DEFINE);
-+	if (ret < 0) {
-+		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	pbus_value |= EN8811H_GPIO_OUTPUT_345;
-+	ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int en8811h_get_features(struct phy_device *phydev)
-+{
-+	linkmode_set_bit_array(phy_basic_ports_array,
-+			       ARRAY_SIZE(phy_basic_ports_array),
-+			       phydev->supported);
-+
-+	return genphy_c45_pma_read_abilities(phydev);
-+}
-+
-+static int en8811h_get_rate_matching(struct phy_device *phydev,
-+				     phy_interface_t iface)
-+{
-+	return RATE_MATCH_PAUSE;
-+}
-+
-+static int en8811h_config_aneg(struct phy_device *phydev)
-+{
-+	bool changed = false;
-+	int err, val;
-+
-+	val = 0;
-+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+			      phydev->advertising))
-+		val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
-+	err =  phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-+				      MDIO_AN_10GBT_CTRL_ADV2_5G, val);
-+	if (err < 0)
-+		return err;
-+	if (err > 0)
-+		changed = true;
-+
-+	return __genphy_config_aneg(phydev, changed);
-+}
-+
-+static int en8811h_read_status(struct phy_device *phydev)
-+{
-+	struct en8811h_priv *priv = phydev->priv;
-+	u32 pbus_value;
-+	int ret, val;
-+
-+	ret = genphy_update_link(phydev);
-+	if (ret)
-+		return ret;
-+
-+	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
-+	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
-+	phydev->speed = SPEED_UNKNOWN;
-+	phydev->duplex = DUPLEX_UNKNOWN;
-+	phydev->pause = 0;
-+	phydev->asym_pause = 0;
-+
-+	ret = genphy_read_master_slave(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = genphy_read_lpa(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Get link partner 2.5GBASE-T ability from vendor register */
-+	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
-+	if (ret < 0)
-+		return ret;
-+	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+			 phydev->lp_advertising,
-+			 pbus_value & EN8811H_2P5G_LPA_2P5G);
-+
-+	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
-+		phy_resolve_aneg_pause(phydev);
-+
-+	if (!phydev->link)
-+		return 0;
-+
-+	/* Get real speed from vendor register */
-+	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
-+	if (val < 0)
-+		return val;
-+	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
-+	case AIR_AUX_CTRL_STATUS_SPEED_2500:
-+		phydev->speed = SPEED_2500;
-+		break;
-+	case AIR_AUX_CTRL_STATUS_SPEED_1000:
-+		phydev->speed = SPEED_1000;
-+		break;
-+	case AIR_AUX_CTRL_STATUS_SPEED_100:
-+		phydev->speed = SPEED_100;
-+		break;
-+	}
-+
-+	/* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
-+	 * Firmware before version 24011202 has no vendor register 2P5G_LPA.
-+	 * Assume link partner advertised it if connected at 2500Mbps.
-+	 */
-+	if (priv->firmware_version < 0x24011202) {
-+		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+				 phydev->lp_advertising,
-+				 phydev->speed == SPEED_2500);
-+	}
-+
-+	/* Only supports full duplex */
-+	phydev->duplex = DUPLEX_FULL;
-+
-+	return 0;
-+}
-+
-+static int en8811h_clear_intr(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+			    AIR_PHY_HOST_CMD_3_DOCMD);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+			    AIR_PHY_HOST_CMD_4_INTCLR);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = en8811h_clear_intr(phydev);
-+	if (ret < 0) {
-+		phy_error(phydev);
-+		return IRQ_NONE;
-+	}
-+
-+	phy_trigger_machine(phydev);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static struct phy_driver en8811h_driver[] = {
-+{
-+	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
-+	.name			= "Airoha EN8811H",
-+	.probe			= en8811h_probe,
-+	.get_features		= en8811h_get_features,
-+	.config_init		= en8811h_config_init,
-+	.get_rate_matching	= en8811h_get_rate_matching,
-+	.config_aneg		= en8811h_config_aneg,
-+	.read_status		= en8811h_read_status,
-+	.config_intr		= en8811h_clear_intr,
-+	.handle_interrupt	= en8811h_handle_interrupt,
-+	.led_hw_is_supported	= en8811h_led_hw_is_supported,
-+	.read_page		= air_phy_read_page,
-+	.write_page		= air_phy_write_page,
-+	.led_blink_set		= air_led_blink_set,
-+	.led_brightness_set	= air_led_brightness_set,
-+	.led_hw_control_set	= air_led_hw_control_set,
-+	.led_hw_control_get	= air_led_hw_control_get,
-+} };
-+
-+module_phy_driver(en8811h_driver);
-+
-+static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
-+	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
-+MODULE_FIRMWARE(EN8811H_MD32_DM);
-+MODULE_FIRMWARE(EN8811H_MD32_DSP);
-+
-+MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
-+MODULE_AUTHOR("Airoha");
-+MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.6/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.6/760-net-core-add-optional-threading-for-backlog-processi.patch
index a918ba31d5..5372171b42 100644
--- a/target/linux/generic/pending-6.6/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-6.6/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /**
   *	napi_disable - prevent NAPI from scheduling
-@@ -3238,6 +3239,7 @@ struct softnet_data {
+@@ -3236,6 +3237,7 @@ struct softnet_data {
  	/* stats */
  	unsigned int		processed;
  	unsigned int		time_squeeze;
@@ -157,7 +157,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
  			   int (*poll)(struct napi_struct *, int), int weight)
  {
-@@ -11351,6 +11422,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11306,6 +11377,9 @@ static int dev_cpu_dead(unsigned int old
  	raise_softirq_irqoff(NET_TX_SOFTIRQ);
  	local_irq_enable();
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11666,6 +11740,7 @@ static int __init net_dev_init(void)
+@@ -11621,6 +11695,7 @@ static int __init net_dev_init(void)
  		INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
  		spin_lock_init(&sd->defer_lock);
  
@@ -182,10 +182,10 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int min_rcvbuf = SOCK_MIN_RCVBUF;
  static int max_skb_frags = MAX_SKB_FRAGS;
 +static int backlog_threaded;
+ static int min_mem_pcpu_rsv = SK_MEMORY_PCPU_RESERVE;
  
  static int net_msg_warn;	/* Unused, but still a sysctl */
- 
-@@ -188,6 +189,23 @@ static int rps_sock_flow_sysctl(struct c
+@@ -189,6 +190,23 @@ static int rps_sock_flow_sysctl(struct c
  }
  #endif /* CONFIG_RPS */
  
@@ -209,7 +209,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_NET_FLOW_LIMIT
  static DEFINE_MUTEX(flow_limit_update_mutex);
  
-@@ -532,6 +550,15 @@ static struct ctl_table net_core_table[]
+@@ -541,6 +559,15 @@ static struct ctl_table net_core_table[]
  		.proc_handler	= rps_sock_flow_sysctl
  	},
  #endif
diff --git a/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
index d11e0eda66..ea3c6c8fe9 100644
--- a/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
+++ b/target/linux/generic/pending-6.6/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch
@@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz <tobias@waldekranz.com>
 
 --- a/drivers/net/dsa/mv88e6xxx/chip.c
 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -6887,6 +6887,7 @@ static int mv88e6xxx_register_switch(str
+@@ -6947,6 +6947,7 @@ static int mv88e6xxx_register_switch(str
  	ds->ops = &mv88e6xxx_switch_ops;
  	ds->ageing_time_min = chip->info->age_time_coeff;
  	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
diff --git a/target/linux/generic/pending-6.6/778-net-l2tp-drop-flow-hash-on-forward.patch b/target/linux/generic/pending-6.6/778-net-l2tp-drop-flow-hash-on-forward.patch
deleted file mode 100644
index a2c0edcbbf..0000000000
--- a/target/linux/generic/pending-6.6/778-net-l2tp-drop-flow-hash-on-forward.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4a44a52f16ccd3d03e0cb5fb437a5eb31a5f9f05 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Mon, 26 Feb 2024 21:39:34 +0100
-Subject: [PATCH] net l2tp: drop flow hash on forward
-
-Drop the flow-hash of the skb when forwarding to the L2TP netdev.
-
-This avoids the L2TP qdisc from using the flow-hash from the outer
-packet, which is identical for every flow within the tunnel.
-
-This does not affect every platform but is specific for the ethernet
-driver. It depends on the platform including L4 information in the
-flow-hash.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- net/l2tp/l2tp_eth.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/net/l2tp/l2tp_eth.c
-+++ b/net/l2tp/l2tp_eth.c
-@@ -136,6 +136,9 @@ static void l2tp_eth_dev_recv(struct l2t
- 	/* checksums verified by L2TP */
- 	skb->ip_summed = CHECKSUM_NONE;
- 
-+	/* drop outer flow-hash */
-+	skb_clear_hash(skb);
-+
- 	skb_dst_drop(skb);
- 	nf_reset_ct(skb);
- 
diff --git a/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch
index 4c271a7bd8..e91d1ef6b2 100644
--- a/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch
+++ b/target/linux/generic/pending-6.6/811-pci_disable_usb_common_quirks.patch
@@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
 --- a/include/linux/usb/hcd.h
 +++ b/include/linux/usb/hcd.h
-@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -485,7 +485,14 @@ extern int usb_hcd_pci_probe(struct pci_
  extern void usb_hcd_pci_remove(struct pci_dev *dev);
  extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
  
diff --git a/target/linux/generic/pending-6.6/920-mangle_bootargs.patch b/target/linux/generic/pending-6.6/920-mangle_bootargs.patch
index 519d0b76da..75f626579e 100644
--- a/target/linux/generic/pending-6.6/920-mangle_bootargs.patch
+++ b/target/linux/generic/pending-6.6/920-mangle_bootargs.patch
@@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  /*
   * We need to store the untouched command line for future reference.
   * We also need to store the touched command line since the parameter
-@@ -896,6 +919,7 @@ void start_kernel(void)
+@@ -898,6 +921,7 @@ void start_kernel(void)
  	pr_notice("%s", linux_banner);
  	early_security_init();
  	setup_arch(&command_line);
diff --git a/target/linux/generic/pending-6.6/999-net-phy-move-LED-polarity-to-phy_init_hw.patch b/target/linux/generic/pending-6.6/999-net-phy-move-LED-polarity-to-phy_init_hw.patch
new file mode 100644
index 0000000000..22c4776827
--- /dev/null
+++ b/target/linux/generic/pending-6.6/999-net-phy-move-LED-polarity-to-phy_init_hw.patch
@@ -0,0 +1,100 @@
+From 6e6fff51ae5e54092611d174fa45fa78c237a415 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 21 May 2024 20:01:46 +0200
+Subject: [PATCH] net: phy: move LED polarity to phy_init_hw
+
+Some PHY reset the polarity on reset and this cause the LED to
+malfunction as LED polarity is configured only when LED is
+registered.
+
+To better handle this, move the LED polarity configuration in
+phy_init_hw to reconfigure it after PHY reset.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/net/phy/phy_device.c | 53 +++++++++++++++++++++++++-----------
+ 1 file changed, 37 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1223,6 +1223,37 @@ static int phy_poll_reset(struct phy_dev
+ 	return 0;
+ }
+ 
++static int of_phy_led_init(struct phy_device *phydev)
++{
++	struct phy_led *phyled;
++
++	list_for_each_entry(phyled, &phydev->leds, list) {
++		struct led_classdev *cdev = &phyled->led_cdev;
++		struct device_node *np = cdev->dev->of_node;
++		unsigned long modes = 0;
++		int err;
++
++		if (of_property_read_bool(np, "active-low"))
++			set_bit(PHY_LED_ACTIVE_LOW, &modes);
++		if (of_property_read_bool(np, "inactive-high-impedance"))
++			set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
++
++		if (!modes)
++			continue;
++
++		/* Return error if asked to set polarity modes but not supported */
++		if (!phydev->drv->led_polarity_set)
++			return -EINVAL;
++
++		err = phydev->drv->led_polarity_set(phydev, phyled->index,
++						    modes);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
+ int phy_init_hw(struct phy_device *phydev)
+ {
+ 	int ret = 0;
+@@ -1259,6 +1290,12 @@ int phy_init_hw(struct phy_device *phyde
+ 			return ret;
+ 	}
+ 
++	if (IS_ENABLED(CONFIG_PHYLIB_LEDS)) {
++		ret = of_phy_led_init(phydev);
++		if (ret < 0)
++			return ret;
++	}
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL(phy_init_hw);
+@@ -3204,7 +3241,6 @@ static int of_phy_led(struct phy_device
+ 	struct device *dev = &phydev->mdio.dev;
+ 	struct led_init_data init_data = {};
+ 	struct led_classdev *cdev;
+-	unsigned long modes = 0;
+ 	struct phy_led *phyled;
+ 	u32 index;
+ 	int err;
+@@ -3222,21 +3258,6 @@ static int of_phy_led(struct phy_device
+ 	if (index > U8_MAX)
+ 		return -EINVAL;
+ 
+-	if (of_property_read_bool(led, "active-low"))
+-		set_bit(PHY_LED_ACTIVE_LOW, &modes);
+-	if (of_property_read_bool(led, "inactive-high-impedance"))
+-		set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
+-
+-	if (modes) {
+-		/* Return error if asked to set polarity modes but not supported */
+-		if (!phydev->drv->led_polarity_set)
+-			return -EINVAL;
+-
+-		err = phydev->drv->led_polarity_set(phydev, index, modes);
+-		if (err)
+-			return err;
+-	}
+-
+ 	phyled->index = index;
+ 	if (phydev->drv->led_brightness_set)
+ 		cdev->brightness_set_blocking = phy_led_set_brightness;
diff --git a/target/linux/imx/Makefile b/target/linux/imx/Makefile
index 4f70933d18..2d3f35e4b4 100644
--- a/target/linux/imx/Makefile
+++ b/target/linux/imx/Makefile
@@ -10,6 +10,7 @@ FEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubif
 SUBTARGETS:=cortexa7 cortexa9 cortexa53
 
 KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/imx/config-6.6 b/target/linux/imx/config-6.6
new file mode 100644
index 0000000000..6edc3560b4
--- /dev/null
+++ b/target/linux/imx/config-6.6
@@ -0,0 +1,497 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_814220=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_IMX6Q_CPUFREQ is not set
+# CONFIG_ARM_IMX_CPUFREQ_DT is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+# CONFIG_ATA_SFF is not set
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_CLK_IMX8MM is not set
+# CONFIG_CLK_IMX8MN is not set
+# CONFIG_CLK_IMX8MP is not set
+# CONFIG_CLK_IMX8MQ is not set
+# CONFIG_CLK_IMX8ULP is not set
+# CONFIG_CLK_IMX93 is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32_ARM_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+# CONFIG_DRM_FSL_LDB is not set
+# CONFIG_DRM_IMX8QM_LDB is not set
+# CONFIG_DRM_IMX8QXP_LDB is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_IMX_LCDC is not set
+# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
+# CONFIG_VIDEO_IMX_MIPI_CSIS is not set
+# CONFIG_VIDEO_IMX8_ISI is not set
+# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set
+# CONFIG_VIDEO_DW100 is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+# CONFIG_VIDEO_HANTRO is not set
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FEC=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FSL_DPAA2_SWITCH is not set
+CONFIG_FSL_GUTS=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_VF610=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_IMX_LPI2C is not set
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_IMX2_WDT=y
+# CONFIG_IMX7ULP_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+# CONFIG_IMX93_ADC is not set
+CONFIG_IMX_DMA=y
+# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MU_MSI=m
+CONFIG_IMX_SDMA=y
+CONFIG_IMX_THERMAL=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_INPUT_BBNSM_PWRKEY is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KEYS=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPILIB=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_CLK=y
+CONFIG_MXS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+# CONFIG_NET_DSA_MICROCHIP_KSZ_PTP is not set
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_DSA_COMMON=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+CONFIG_NVMEM_IMX_OCOTP=y
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMX93 is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX1 is not set
+CONFIG_PWM_IMX27=y
+# CONFIG_PWM_IMX_TPM is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_BBNSM is not set
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SLL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_IMX7ULP is not set
+# CONFIG_SOC_IMX8M is not set
+# CONFIG_SOC_IMX9 is not set
+# CONFIG_SOC_LS1021A is not set
+# CONFIG_SOC_VF610 is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MASTER=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+CONFIG_STMP_DEVICE=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USE_OF=y
+# CONFIG_VIDEO_IMX7_CSI is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/imx/image/cortexa7.mk b/target/linux/imx/image/cortexa7.mk
index d5a23fc6e9..3f89a99a83 100644
--- a/target/linux/imx/image/cortexa7.mk
+++ b/target/linux/imx/image/cortexa7.mk
@@ -10,6 +10,9 @@ define Device/Default
   KERNEL_NAME := zImage
   KERNEL := kernel-bin | uImage none
   KERNEL_LOADADDR := 0x80008000
+ifdef CONFIG_LINUX_6_6
+  DTS_DIR := $(DTS_DIR)/nxp/imx
+endif
   IMAGES :=
 endef
 
diff --git a/target/linux/imx/image/cortexa9.mk b/target/linux/imx/image/cortexa9.mk
index 2321469cc8..1ff5bcb8a7 100644
--- a/target/linux/imx/image/cortexa9.mk
+++ b/target/linux/imx/image/cortexa9.mk
@@ -84,6 +84,9 @@ define Device/Default
   KERNEL_NAME := zImage
   KERNEL := kernel-bin | uImage none
   KERNEL_LOADADDR := 0x10008000
+ifdef CONFIG_LINUX_6_6
+  DTS_DIR := $(DTS_DIR)/nxp/imx
+endif
   IMAGES :=
 endef
 
diff --git a/target/linux/imx/patches-6.1/001-6.2-phy-freescale-imx8m-pcie-Refine-register-definitions.patch b/target/linux/imx/patches-6.1/001-6.2-phy-freescale-imx8m-pcie-Refine-register-definitions.patch
index 0af479aae9..01731755df 100644
--- a/target/linux/imx/patches-6.1/001-6.2-phy-freescale-imx8m-pcie-Refine-register-definitions.patch
+++ b/target/linux/imx/patches-6.1/001-6.2-phy-freescale-imx8m-pcie-Refine-register-definitions.patch
@@ -20,7 +20,7 @@ Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
 
 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
 +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
-@@ -31,12 +31,10 @@
+@@ -32,12 +32,10 @@
  #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
  #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
  #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
@@ -35,8 +35,8 @@ Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
  
  #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
  #define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
-@@ -131,9 +129,8 @@ static int imx8_pcie_phy_power_on(struct
- 	reset_control_deassert(imx8_phy->reset);
+@@ -152,9 +150,8 @@ static int imx8_pcie_phy_power_on(struct
+ 	}
  
  	/* Polling to check the phy is ready or not. */
 -	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
diff --git a/target/linux/imx/patches-6.1/002-6.2-phy-freescale-imx8m-pcie-Refine-i.MX8MM-PCIe-PHY-dri.patch b/target/linux/imx/patches-6.1/002-6.2-phy-freescale-imx8m-pcie-Refine-i.MX8MM-PCIe-PHY-dri.patch
deleted file mode 100644
index c2264c0bb4..0000000000
--- a/target/linux/imx/patches-6.1/002-6.2-phy-freescale-imx8m-pcie-Refine-i.MX8MM-PCIe-PHY-dri.patch
+++ /dev/null
@@ -1,197 +0,0 @@
-From fb681544808b85c0cdf41a627401e5d470633914 Mon Sep 17 00:00:00 2001
-From: Richard Zhu <hongxing.zhu@nxp.com>
-Date: Thu, 13 Oct 2022 09:47:01 +0800
-Subject: [PATCH 2/3] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY
- driver
-
-To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
-driver.
-- Use gpr compatible string to avoid the codes duplications when add
-  another platform PCIe PHY support.
-- Re-arrange the codes to let it more flexible and easy to expand.
-No functional change. Re-arrange the TX tuning, since internal registers
-can be wrote through APB interface before assertion of CMN_RST.
-
-Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
-Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-Tested-by: Marek Vasut <marex@denx.de>
-Tested-by: Richard Leitner <richard.leitner@skidata.com>
-Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
-Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
-Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
----
- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106 +++++++++++++--------
- 1 file changed, 66 insertions(+), 40 deletions(-)
-
---- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
-+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
-@@ -11,6 +11,7 @@
- #include <linux/mfd/syscon.h>
- #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
- #include <linux/module.h>
-+#include <linux/of_device.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-@@ -45,6 +46,15 @@
- #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
- #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
- 
-+enum imx8_pcie_phy_type {
-+	IMX8MM,
-+};
-+
-+struct imx8_pcie_phy_drvdata {
-+	const	char			*gpr;
-+	enum	imx8_pcie_phy_type	variant;
-+};
-+
- struct imx8_pcie_phy {
- 	void __iomem		*base;
- 	struct clk		*clk;
-@@ -55,6 +65,7 @@ struct imx8_pcie_phy {
- 	u32			tx_deemph_gen1;
- 	u32			tx_deemph_gen2;
- 	bool			clkreq_unused;
-+	const struct imx8_pcie_phy_drvdata	*drvdata;
- };
- 
- static int imx8_pcie_phy_power_on(struct phy *phy)
-@@ -66,31 +77,17 @@ static int imx8_pcie_phy_power_on(struct
- 	reset_control_assert(imx8_phy->reset);
- 
- 	pad_mode = imx8_phy->refclk_pad_mode;
--	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
--			   imx8_phy->clkreq_unused ?
--			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_AUX_EN,
--			   IMX8MM_GPR_PCIE_AUX_EN);
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_SSC_EN, 0);
--
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
--			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
--			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
--			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
--	usleep_range(100, 200);
--
--	/* Do the PHY common block reset */
--	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
--			   IMX8MM_GPR_PCIE_CMN_RST,
--			   IMX8MM_GPR_PCIE_CMN_RST);
--	usleep_range(200, 500);
-+	switch (imx8_phy->drvdata->variant) {
-+	case IMX8MM:
-+		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
-+		if (imx8_phy->tx_deemph_gen1)
-+			writel(imx8_phy->tx_deemph_gen1,
-+			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
-+		if (imx8_phy->tx_deemph_gen2)
-+			writel(imx8_phy->tx_deemph_gen2,
-+			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
-+		break;
-+	}
- 
- 	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
- 	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
-@@ -118,15 +115,37 @@ static int imx8_pcie_phy_power_on(struct
- 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
- 	}
- 
--	/* Tune PHY de-emphasis setting to pass PCIe compliance. */
--	if (imx8_phy->tx_deemph_gen1)
--		writel(imx8_phy->tx_deemph_gen1,
--		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
--	if (imx8_phy->tx_deemph_gen2)
--		writel(imx8_phy->tx_deemph_gen2,
--		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
-+	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
-+			   imx8_phy->clkreq_unused ?
-+			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_AUX_EN,
-+			   IMX8MM_GPR_PCIE_AUX_EN);
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_SSC_EN, 0);
- 
--	reset_control_deassert(imx8_phy->reset);
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
-+			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
-+			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
-+			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
-+	usleep_range(100, 200);
-+
-+	/* Do the PHY common block reset */
-+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-+			   IMX8MM_GPR_PCIE_CMN_RST,
-+			   IMX8MM_GPR_PCIE_CMN_RST);
-+
-+	switch (imx8_phy->drvdata->variant) {
-+	case IMX8MM:
-+		reset_control_deassert(imx8_phy->reset);
-+		usleep_range(200, 500);
-+		break;
-+	}
- 
- 	/* Polling to check the phy is ready or not. */
- 	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
-@@ -157,6 +176,17 @@ static const struct phy_ops imx8_pcie_ph
- 	.owner		= THIS_MODULE,
- };
- 
-+static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
-+	.gpr = "fsl,imx8mm-iomuxc-gpr",
-+	.variant = IMX8MM,
-+};
-+
-+static const struct of_device_id imx8_pcie_phy_of_match[] = {
-+	{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-+
- static int imx8_pcie_phy_probe(struct platform_device *pdev)
- {
- 	struct phy_provider *phy_provider;
-@@ -169,6 +199,8 @@ static int imx8_pcie_phy_probe(struct pl
- 	if (!imx8_phy)
- 		return -ENOMEM;
- 
-+	imx8_phy->drvdata = of_device_get_match_data(dev);
-+
- 	/* get PHY refclk pad mode */
- 	of_property_read_u32(np, "fsl,refclk-pad-mode",
- 			     &imx8_phy->refclk_pad_mode);
-@@ -194,7 +226,7 @@ static int imx8_pcie_phy_probe(struct pl
- 
- 	/* Grab GPR config register range */
- 	imx8_phy->iomuxc_gpr =
--		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-+		 syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
- 	if (IS_ERR(imx8_phy->iomuxc_gpr)) {
- 		dev_err(dev, "unable to find iomuxc registers\n");
- 		return PTR_ERR(imx8_phy->iomuxc_gpr);
-@@ -222,12 +254,6 @@ static int imx8_pcie_phy_probe(struct pl
- 	return PTR_ERR_OR_ZERO(phy_provider);
- }
- 
--static const struct of_device_id imx8_pcie_phy_of_match[] = {
--	{.compatible = "fsl,imx8mm-pcie-phy",},
--	{ },
--};
--MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
--
- static struct platform_driver imx8_pcie_phy_driver = {
- 	.probe	= imx8_pcie_phy_probe,
- 	.driver = {
diff --git a/target/linux/imx/patches-6.1/003-6.3-phy-freescale-imx8m-pcie-Add-i.MX8MP-PCIe-PHY-suppor.patch b/target/linux/imx/patches-6.1/003-6.3-phy-freescale-imx8m-pcie-Add-i.MX8MP-PCIe-PHY-suppor.patch
index 03b41e4153..dbcfd40e57 100644
--- a/target/linux/imx/patches-6.1/003-6.3-phy-freescale-imx8m-pcie-Add-i.MX8MP-PCIe-PHY-suppor.patch
+++ b/target/linux/imx/patches-6.1/003-6.3-phy-freescale-imx8m-pcie-Add-i.MX8MP-PCIe-PHY-suppor.patch
@@ -57,7 +57,7 @@ Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
  	}
  
  	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
-@@ -141,6 +145,9 @@ static int imx8_pcie_phy_power_on(struct
+@@ -143,6 +147,9 @@ static int imx8_pcie_phy_power_on(struct
  			   IMX8MM_GPR_PCIE_CMN_RST);
  
  	switch (imx8_phy->drvdata->variant) {
@@ -67,7 +67,7 @@ Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
  	case IMX8MM:
  		reset_control_deassert(imx8_phy->reset);
  		usleep_range(200, 500);
-@@ -181,8 +188,14 @@ static const struct imx8_pcie_phy_drvdat
+@@ -183,8 +190,14 @@ static const struct imx8_pcie_phy_drvdat
  	.variant = IMX8MM,
  };
  
@@ -82,7 +82,7 @@ Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
  	{ },
  };
  MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-@@ -238,6 +251,14 @@ static int imx8_pcie_phy_probe(struct pl
+@@ -240,6 +253,14 @@ static int imx8_pcie_phy_probe(struct pl
  		return PTR_ERR(imx8_phy->reset);
  	}
  
diff --git a/target/linux/imx/patches-6.6/100-bootargs.patch b/target/linux/imx/patches-6.6/100-bootargs.patch
new file mode 100644
index 0000000000..7afcebecb0
--- /dev/null
+++ b/target/linux/imx/patches-6.6/100-bootargs.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts
+@@ -16,4 +16,8 @@
+ 		device_type = "memory";
+ 		reg = <0x10000000 0x40000000>;
+ 	};
++
++	chosen {
++		bootargs = "console=ttymxc0,115200";
++	};
+ };
diff --git a/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch b/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
new file mode 100644
index 0000000000..5a8e9550fd
--- /dev/null
+++ b/target/linux/imx/patches-6.6/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch
@@ -0,0 +1,96 @@
+From 68604e89335ccb3e893b5a05b2c0d5cd2eaaf6ec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Tue, 3 Mar 2020 15:14:40 +0100
+Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: add status LEDs aliases
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 16 ++++++++++------
+ arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts      | 12 ++++++++----
+ 2 files changed, 18 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts
+@@ -24,6 +24,10 @@
+ 		i2c2 = &i2c2;
+ 		rtc0 = &rtc_i2c;
+ 		rtc1 = &snvs_rtc;
++		led-boot = &led_boot;
++		led-failsafe = &led_failsafe;
++		led-running = &led_running;
++		led-upgrade = &led_upgrade;
+ 	};
+ 
+ 	chosen {
+@@ -35,22 +39,22 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_leds_ixora>;
+ 
+-		led4-green {
++		led_running: led4-green {
+ 			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_4_GREEN";
+ 		};
+ 
+-		led4-red {
++		led_upgrade: led4-red {
+ 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_4_RED";
+ 		};
+ 
+-		led5-green {
++		led_boot: led5-green {
+ 			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_GREEN";
+ 		};
+ 
+-		led5-red {
++		led_failsafe: led5-red {
+ 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_RED";
+ 		};
+--- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts
+@@ -24,6 +24,10 @@
+ 		i2c2 = &i2c2;
+ 		rtc0 = &rtc_i2c;
+ 		rtc1 = &snvs_rtc;
++		led-boot = &led_boot;
++		led-failsafe = &led_failsafe;
++		led-running = &led_running;
++		led-upgrade = &led_upgrade;
+ 	};
+ 
+ 	chosen {
+@@ -36,22 +40,22 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_leds_ixora>;
+ 
+-		led4-green {
+-			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
++		led_running: led4-green {
++			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_4_GREEN";
+ 		};
+ 
+-		led4-red {
+-			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
++		led_upgrade: led4-red {
++			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_4_RED";
+ 		};
+ 
+-		led5-green {
++		led_boot: led5-green {
+ 			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_GREEN";
+ 		};
+ 
+-		led5-red {
++		led_failsafe: led5-red {
+ 			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ 			label = "LED_5_RED";
+ 		};
diff --git a/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch b/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
new file mode 100644
index 0000000000..0a3b696128
--- /dev/null
+++ b/target/linux/imx/patches-6.6/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch
@@ -0,0 +1,78 @@
+From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Tue, 3 Mar 2020 15:15:57 +0100
+Subject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-
+ arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts      | 15 ++++++++++++++-
+ 2 files changed, 28 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts
+@@ -59,6 +59,17 @@
+ 			label = "LED_5_RED";
+ 		};
+ 	};
++
++	gpio-keys {
++		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
++
++		reset {
++			label = "reset";
++			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_RESTART>;
++			debounce-interval = <10>;
++		};
++	};
+ };
+ 
+ &can1 {
+@@ -183,4 +194,10 @@
+ 			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ 		>;
+ 	};
++
++	pinctrl_switch3_ixora: switch3ixora {
++		fsl,pins = <
++			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++		>;
++	};
+ };
+--- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts
+@@ -61,6 +61,17 @@
+ 		};
+ 	};
+ 
++	gpio-keys {
++		pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
++
++		reset {
++			label = "reset";
++			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_RESTART>;
++			debounce-interval = <10>;
++		};
++	};
++
+ 	reg_3v3_vmmc: regulator-3v3-vmmc {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -264,6 +275,12 @@
+ 		>;
+ 	};
+ 
++	pinctrl_switch3_ixora: switch3ixora {
++		fsl,pins = <
++			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++		>;
++	};
++
+ 	pinctrl_mmc_cd_sleep: mmccdslpgrp {
+ 		fsl,pins = <
+ 			 /* MMC1 CD */
diff --git a/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch b/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
new file mode 100644
index 0000000000..d71787b3ac
--- /dev/null
+++ b/target/linux/imx/patches-6.6/310-ARM-dts-imx7d-pico-pi-set-aliases.patch
@@ -0,0 +1,24 @@
+--- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts
+@@ -8,12 +8,20 @@
+ 	model = "TechNexion PICO-IMX7D Board and PI baseboard";
+ 	compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
+ 
++	aliases {
++		led-boot = &led_system;
++		led-failsafe = &led_system;
++		led-running = &led_system;
++		led-upgrade = &led_system;
++		label-mac-device = &fec1;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_gpio_leds>;
+ 
+-		led {
++		led_system: led {
+ 			label = "gpio-led";
+ 			gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ 		};
diff --git a/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch b/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
new file mode 100644
index 0000000000..244b7595ae
--- /dev/null
+++ b/target/linux/imx/patches-6.6/311-ARM-imx7d-pico-pi.dts-add-default-stdout-path.patch
@@ -0,0 +1,23 @@
+From 6e8e5ccfbee7a531b035ffce3f95f3901946fa9d Mon Sep 17 00:00:00 2001
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Wed, 9 Jan 2019 14:33:24 -0600
+Subject: [PATCH] ARM: imx7d-pico-pi.dts: add default stdout-path
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts
++++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts
+@@ -16,6 +16,10 @@
+ 		label-mac-device = &fec1;
+ 	};
+ 
++	chosen {
++		stdout-path = "serial4:115200n8";
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 		pinctrl-names = "default";
diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile
index be48e4be52..30091e5d29 100644
--- a/target/linux/ipq40xx/Makefile
+++ b/target/linux/ipq40xx/Makefile
@@ -8,8 +8,7 @@ CPU_TYPE:=cortex-a7
 CPU_SUBTYPE:=neon-vfpv4
 SUBTARGETS:=generic chromium mikrotik
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 KERNELNAME:=zImage Image dtbs
 
diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network
index 02059580a1..7a2874a6e4 100644
--- a/target/linux/ipq40xx/base-files/etc/board.d/02_network
+++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network
@@ -37,6 +37,7 @@ ipq40xx_setup_interfaces()
 	glinet,gl-ap1300|\
 	glinet,gl-b2200|\
 	google,wifi|\
+	linksys,whw03|\
 	linksys,whw03v2|\
 	luma,wrtq-329acn|\
 	mikrotik,cap-ac|\
@@ -51,6 +52,7 @@ ipq40xx_setup_interfaces()
 	aruba,ap-365|\
 	avm,fritzrepeater-1200|\
 	dlink,dap-2610|\
+	engenius,eap1300|\
 	extreme-networks,ws-ap3915i|\
 	meraki,mr33|\
 	meraki,mr74|\
@@ -168,11 +170,6 @@ ipq40xx_setup_macs()
 	asus,rt-ac42u)
 		label_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)
 		;;
-	asus,rt-ac58u)
-		wan_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)
-		lan_mac=$(mtd_get_mac_binary_ubi Factory 0x5006)
-		label_mac=$wan_mac
-		;;
 	avm,fritzbox-7530)
 		local tffsdev=$(find_mtd_chardev "nand-tffs")
 		wan_mac=$(/usr/bin/fritz_tffs_nand -b -d $tffsdev -n macdsl)
@@ -215,6 +212,10 @@ ipq40xx_setup_macs()
 		wan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		;;
+	linksys,whw03)
+		wan_mac=$(mmc_get_mac_ascii devinfo hw_mac_addr)
+		lan_mac="$wan_mac"
+		;;
 	mikrotik,cap-ac |\
 	mikrotik,hap-ac2|\
 	mikrotik,hap-ac3|\
diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
index 654be2697a..4a1a0ff311 100644
--- a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@@ -40,6 +40,10 @@ case "$FIRMWARE" in
 		# OEM assigns 4 sequential MACs
 		ath10k_patch_mac $(macaddr_setbit_la $(macaddr_add "$(cat /sys/class/net/eth0/address)" 4))
 		;;
+	linksys,whw03)
+		caldata_extract_mmc "0:ART" 0x9000 0x2f20
+		ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 3)
+		;;
 	netgear,rbr40|\
 	netgear,rbs40|\
 	netgear,rbr50|\
@@ -54,8 +58,7 @@ case "$FIRMWARE" in
 "ath10k/pre-cal-ahb-a000000.wifi.bin")
 	case "$board" in
 	asus,map-ac2200|\
-	asus,rt-ac42u|\
-	asus,rt-ac58u)
+	asus,rt-ac42u)
 		caldata_extract_ubi "Factory" 0x1000 0x2f20
 		;;
 	avm,fritzbox-4040)
@@ -104,6 +107,10 @@ case "$FIRMWARE" in
 		caldata_extract "ART" 0x1000 0x2f20
 		ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 2)
 		;;
+	linksys,whw03)
+		caldata_extract_mmc "0:ART" 0x1000 0x2f20
+		ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 1)
+		;;
 	meraki,mr33 |\
 	meraki,mr74)
 		caldata_extract_ubi "ART" 0x1000 0x2f20
@@ -150,8 +157,7 @@ case "$FIRMWARE" in
 	;;
 "ath10k/pre-cal-ahb-a800000.wifi.bin")
 	case "$board" in
-	asus,map-ac2200|\
-	asus,rt-ac58u)
+	asus,map-ac2200)
 		caldata_extract_ubi "Factory" 0x5000 0x2f20
 		;;
 	avm,fritzbox-4040)
@@ -200,6 +206,10 @@ case "$FIRMWARE" in
 		caldata_extract "ART" 0x5000 0x2f20
 		ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 3)
 		;;
+	linksys,whw03)
+		caldata_extract_mmc "0:ART" 0x5000 0x2f20
+		ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 2)
+		;;
 	meraki,mr33 |\
 	meraki,mr74)
 		caldata_extract_ubi "ART" 0x5000 0x2f20
diff --git a/target/linux/ipq40xx/base-files/etc/init.d/bootcount b/target/linux/ipq40xx/base-files/etc/init.d/bootcount
index df656c9b85..0120f78cfe 100755
--- a/target/linux/ipq40xx/base-files/etc/init.d/bootcount
+++ b/target/linux/ipq40xx/base-files/etc/init.d/bootcount
@@ -2,6 +2,35 @@
 
 START=99
 
+mmc_resetbc() {
+	local part_label="$1"
+
+	. /lib/functions.sh
+
+	local part_device="$(find_mmc_part "$part_label")"
+	if [ "$part_device" = "" ]; then
+		>&2 echo "mmc_resetbc: Unknown partition label: $part_label"
+		return 1
+	fi
+
+	local magic_number="$(hexdump -e '"0x%02x\n"' -n 4 "$part_device")"
+	if [ "$magic_number" != "0x20110811" ]; then
+		>&2 echo "mmc_resetbc: Unexpected partition magic: $magic_number"
+		return 1
+	fi
+
+	local last_count=$(hexdump -e '"0x%02x\n"' -n 4 -s 4 "$part_device")
+	if [ "$last_count" != "0x00" ]; then
+		printf "\x00" | dd of="$part_device" bs=4 seek=1 count=1 conv=notrunc 2>/dev/null
+
+		last_count=$(hexdump -e '"0x%02x\n"' -n 4 -s 4 "$part_device")
+		if [ "$last_count" != "0x00" ]; then
+			>&2 echo "mmc_resetbc: Unable to reset boot counter"
+			return 1
+		fi
+	fi
+}
+
 boot() {
 	case $(board_name) in
 	alfa-network,ap120c-ac)
@@ -15,6 +44,9 @@ boot() {
 	linksys,whw03v2)
 		mtd resetbc s_env || true
 		;;
+	linksys,whw03)
+		mmc_resetbc s_env || true
+		;;
 	netgear,wac510)
 		fw_setenv boot_cnt=0
 		;;
diff --git a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh
index 96e70f62a9..1ede544aac 100644
--- a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh
+++ b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh
@@ -30,6 +30,12 @@ preinit_set_mac_address() {
 		ip link set dev lan1 address $(macaddr_add "$base_mac" 1)
 		ip link set dev eth0 address $(macaddr_setbit "$base_mac" 7)
 		;;
+	linksys,whw03)
+		base_mac=$(mmc_get_mac_ascii devinfo hw_mac_addr)
+		ip link set dev eth0 address "$base_mac"
+		ip link set dev lan address "$base_mac"
+		ip link set dev wan address "$base_mac"
+		;;
 	mikrotik,wap-ac|\
 	mikrotik,wap-ac-lte|\
 	mikrotik,wap-r-ac)
diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh b/target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh
index 18366fc622..860c3fd2de 100644
--- a/target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh
+++ b/target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh
@@ -123,3 +123,71 @@ platform_do_upgrade_linksys() {
 		get_image "$1" | mtd -e "$part_label" write - "$part_label"
 	}
 }
+
+linksys_get_cmdline_rootfs_device() {
+	if read cmdline < /proc/cmdline; then
+		case "$cmdline" in
+		*root=*)
+			local str="${cmdline##*root=}"
+			echo "${str%% *}"
+			return
+			;;
+		esac
+	fi
+	return 1
+}
+
+linksys_get_current_boot_part_emmc() {
+	local boot_part="$(fw_printenv -n boot_part)"
+	if [ "$boot_part" = 1 ] || [ "$boot_part" = 2 ]; then
+		v "Current boot_part=$boot_part selected from bootloader environment"
+	else
+		local rootfs_device="$(linksys_get_cmdline_rootfs_device)"
+		if [ "$rootfs_device" = "$(find_mmc_part "rootfs")" ]; then
+			boot_part=1
+		elif [ "$rootfs_device" = "$(find_mmc_part "alt_rootfs")" ]; then
+			boot_part=2
+		else
+			v "Could not determine current boot_part"
+			return 1
+		fi
+		v "Current boot_part=$boot_part selected from cmdline rootfs=$rootfs_device"
+	fi
+	echo $boot_part
+}
+
+linksys_set_target_partitions_emmc() {
+	local current_boot_part="$1"
+
+	if [ "$current_boot_part" = 1 ]; then
+		CI_KERNPART="alt_kernel"
+		CI_ROOTPART="alt_rootfs"
+		fw_setenv -s - <<-EOF
+			boot_part 2
+			auto_recovery yes
+		EOF
+	elif [ "$current_boot_part" = 2 ]; then
+		CI_KERNPART="kernel"
+		CI_ROOTPART="rootfs"
+		fw_setenv -s - <<-EOF
+			boot_part 1
+			auto_recovery yes
+		EOF
+	else
+		v "Could not set target eMMC partitions"
+		return 1
+	fi
+
+	v "Target eMMC partitions: $CI_KERNPART, $CI_ROOTPART"
+}
+
+platform_do_upgrade_linksys_emmc() {
+	local file="$1"
+
+	mkdir -p /var/lock
+	local current_boot_part="$(linksys_get_current_boot_part_emmc)"
+	linksys_set_target_partitions_emmc "$current_boot_part" || exit 1
+	touch /var/lock/fw_printenv.lock
+
+	emmc_do_upgrade "$file"
+}
diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
index e934326849..53a9561148 100644
--- a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
@@ -175,6 +175,9 @@ platform_do_upgrade() {
 	linksys,whw03v2)
 		platform_do_upgrade_linksys "$1"
 		;;
+	linksys,whw03)
+		platform_do_upgrade_linksys_emmc "$1"
+		;;
 	meraki,mr33 |\
 	meraki,mr74)
 		CI_KERNPART="part.safe"
@@ -236,7 +239,8 @@ platform_do_upgrade() {
 platform_copy_config() {
 	case "$(board_name)" in
 	glinet,gl-b2200 |\
-	google,wifi)
+	google,wifi |\
+	linksys,whw03)
 		emmc_copy_config
 		;;
 	esac
diff --git a/target/linux/ipq40xx/config-6.1 b/target/linux/ipq40xx/config-6.1
deleted file mode 100644
index f14dd0a474..0000000000
--- a/target/linux/ipq40xx/config-6.1
+++ /dev/null
@@ -1,540 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-# CONFIG_ARCH_MSM8960 is not set
-# CONFIG_ARCH_MSM8974 is not set
-# CONFIG_ARCH_MSM8X60 is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPUIDLE=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCH=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_QCE=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXTCON=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OPTEE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-CONFIG_IPQ_GCC_4019=y
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-# CONFIG_KPSS_XCC is not set
-# CONFIG_KRAITCC is not set
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LEDS_LP5523=y
-CONFIG_LEDS_LP5562=y
-CONFIG_LEDS_LP55XX_COMMON=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MSM_GCC_8660 is not set
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-# CONFIG_MTD_QCOMSMEM_PARTS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K_IPQ4019=y
-CONFIG_NET_DSA_TAG_OOB=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OPTEE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-CONFIG_PHY_QCOM_IPQ4019_USB=y
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA807X_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-CONFIG_QCOM_A53PLL=y
-# CONFIG_QCOM_ADM is not set
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-CONFIG_QCOM_IPQ4019_ESS_EDMA=y
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-# CONFIG_QCOM_SOCINFO is not set
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-# CONFIG_QCOM_TSENS is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_REGULATOR_VCTRL=y
-CONFIG_REGULATOR_VQMMC_IPQ4019=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_OPTEE is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SKB_EXTENSIONS=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TEE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ipq40xx/config-6.6 b/target/linux/ipq40xx/config-6.6
index 22101d7df0..3049efc3d6 100644
--- a/target/linux/ipq40xx/config-6.6
+++ b/target/linux/ipq40xx/config-6.6
@@ -309,6 +309,7 @@ CONFIG_MTD_SPLIT_WRGG_FW=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_NVMEM=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -330,6 +331,7 @@ CONFIG_NVMEM=y
 CONFIG_NVMEM_QCOM_QFPROM=y
 # CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
 # CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_U_BOOT_ENV=y
 CONFIG_NVMEM_SYSFS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-a42.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-a42.dts
deleted file mode 100644
index f43c4b8000..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-a42.dts
+++ /dev/null
@@ -1,240 +0,0 @@
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "OpenMesh A42";
-	compatible = "openmesh,a42";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &led_status_green;
-		led-failsafe = &led_status_green;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_green;
-		label-mac-device = &swport5;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		status_red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_green: status_green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	watchdog {
-		compatible = "linux,wdt-gpio";
-		gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-		hw_algo = "toggle";
-		/* hw_margin_ms is actually 300s but driver limits it to 60s */
-		hw_margin_ms = <60000>;
-		always-running;
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		/* partitions are passed via bootloader */
-		partitions {
-			partition-art {
-				label = "0:ART";
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "ethernet2";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
-	status = "okay";
-	label = "ethernet1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "OM-A42";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "OM-A42";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
deleted file mode 100644
index ceaa1edd45..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "ALFA Network AP120C-AC";
-	compatible = "alfa-network,ap120c-ac";
-
-	aliases {
-		led-boot = &status;
-		led-failsafe = &status;
-		led-running = &status;
-		led-upgrade = &status;
-		ethernet1 = &swport5;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		status: status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "red:wlan5g";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-
-	tpm@29 {
-		compatible = "atmel,at97sc3204t";
-		reg = <0x29>;
-	};
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm  4 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-			};
-
-			partition@f0000 {
-				label = "APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@180000 {
-				label = "priv_data1";
-				reg = <0x00180000 0x00010000>;
-				read-only;
-			};
-
-			partition@190000 {
-				label = "priv_data2";
-				reg = <0x00190000 0x00010000>;
-				read-only;
-			};
-		};
-	};
-
-	nand@1 {
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs1";
-				reg = <0x00000000 0x04000000>;
-			};
-
-			partition@4000000 {
-				label = "rootfs2";
-				reg = <0x04000000 0x04000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial0_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&ethphy4 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&tlmm {
-	i2c0_pins: i2c0_pinmux {
-		mux_i2c {
-			function = "blsp_i2c0";
-			pins = "gpio58", "gpio59";
-			drive-strength = <16>;
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_mdio {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_mdc {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial0_pins: serial0_pinmux {
-		mux_uart {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi0_pins: spi0_pinmux {
-		mux_spi {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio4";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts
deleted file mode 100644
index 388b2dd590..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts
+++ /dev/null
@@ -1,255 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MikroTik cAP ac";
-	compatible = "mikrotik,cap-ac";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x08000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_user;
-		led-failsafe = &led_user;
-		led-running = &led_user;
-		led-upgrade = &led_user;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		mode {
-			label = "mode";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_LIGHTS_TOGGLE>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		led_user: user {
-			label = "green:user";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		eth1 {
-			label = "green:eth1";
-			gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		eth2 {
-			label = "green:eth2";
-			gpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@100000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&ethphy3 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&ethphy4 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
deleted file mode 100644
index c388ceca27..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts
+++ /dev/null
@@ -1,296 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EZVIZ CS-W3-WD1200G EUP";
-	compatible = "ezviz,cs-w3-wd1200g-eup";
-
-	aliases {
-		led-boot = &led_status_green;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_green;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <5000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_red: status_red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-		};
-
-		led_status_green: status_green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
-		};
-
-		led_status_blue: status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition5@E0000 {
-				label = "APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-
-			partition6@F0000 {
-				label = "APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition7@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition9@580000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x00180000 0x00e80000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-	label = "wan";
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
deleted file mode 100644
index fef549035d..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "D-Link DAP 2610";
-	compatible = "dlink,dap-2610";
-
-	aliases {
-		led-boot = &led_red;
-		led-failsafe = &led_red;
-		led-running = &led_green;
-		led-upgrade = &led_red;
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		rng@22000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_red: red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-		};
-
-		led_green: green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "fixed-partitions";
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-			};
-			partition@180000 {
-				compatible = "wrg";
-				label = "firmware";
-				reg = <0x180000 0xdc0000>;
-			};
-			partition@fb0000 {
-				label = "rgbd";
-				reg = <0xfb0000 0x10000>;
-				read-only;
-			};
-			partition@fc0000 {
-				label = "bdcfg";
-				reg = <0xfc0000 0x10000>;
-				read-only;
-			};
-			partition@fd0000 {
-				label = "langpack";
-				reg = <0xfd0000 0x20000>;
-				read-only;
-			};
-			partition@ff0000 {
-				label = "certificate";
-				reg = <0xff0000 0x10000>;
-				read-only;
-			};
-			partition@f40000 {
-				label = "captival";
-				reg = <0xf40000 0x70000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
deleted file mode 100644
index 50e7f3d4e0..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts
+++ /dev/null
@@ -1,312 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Linksys EA6350v3";
-	compatible = "linksys,ea6350v3";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			SBL1@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			MBIB@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			QSEE@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			CDT@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			APPSBLENV@d0000 {
-				label = "APPSBLENV";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			APPSBL@e0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000e0000 0x00080000>;
-				read-only;
-			};
-			ART@160000 {
-				label = "ART";
-				reg = <0x00160000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			u_env@170000 {
-				label = "u_env";
-				reg = <0x00170000 0x00020000>;
-			};
-			s_env@190000 {
-				label = "s_env";
-				reg = <0x00190000 0x00020000>;
-			};
-			devinfo@1b0000 {
-				label = "devinfo";
-				reg = <0x001b0000 0x00010000>;
-			};
-			/* 0x001c0000 - 0x00200000 unused */
-		};
-	};
-
-	flash@1 {
-		status = "okay";
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			kernel@0 {
-				label = "kernel";
-				reg = <0x00000000 0x02800000>;
-			};
-			rootfs@500000 {
-				label = "rootfs";
-				reg = <0x00500000 0x02300000>;
-			};
-			alt_kernel@2800000 {
-				label = "alt_kernel";
-				reg = <0x02800000 0x02800000>;
-			};
-			alt_rootfs@2d00000 {
-				label = "alt_rootfs";
-				reg = <0x02d00000 0x02300000>;
-			};
-			sysdiag@5000000 {
-				label = "sysdiag";
-				reg = <0x05000000 0x00100000>;
-			};
-			syscfg@5100000 {
-				label = "syscfg";
-				reg = <0x05100000 0x02F00000>;
-			};
-			/* 0x00000000 - 0x08000000: 128 MiB */
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
deleted file mode 100644
index e9d4775fd8..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EnGenius EAP1300";
-	compatible = "engenius,eap1300";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: orange {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-		};
-
-		lan {
-			function = LED_FUNCTION_LAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		mesh {
-			label = "blue:mesh";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g {
-			label = "blue:wlan2g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "yellow:wlan5g";
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio54", "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	m25p80@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x00090000>;
-				read-only;
-			};
-			partition7@180000 {
-				label = "0:ART";
-				reg = <0x00180000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition8@190000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x190000 0x1dc0000>;
-			};
-			partition9@1f50000 {
-				label = "u-boot-env";
-				reg = <0x01f50000 0x00010000>;
-			};
-			partition10@1f60000 {
-				label = "userconfig";
-				reg = <0x01f60000 0x000a0000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts
deleted file mode 100644
index e74d110b3d..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts
+++ /dev/null
@@ -1,334 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Edgecore ECW5211";
-	compatible = "edgecore,ecw5211";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-		ethernet0 = &swport5;
-		ethernet1 = &gmac;
-	};
-
-	chosen {
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_YELLOW>;
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_mdio {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_mdc {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi0_pins: spi0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio4";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	i2c0_pins: i2c0_pinmux {
-		mux_i2c {
-			function = "blsp_i2c0";
-			pins = "gpio58", "gpio59";
-			drive-strength = <16>;
-			bias-disable;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV"; /* uboot env */
-				reg = <0x000e0000 0x00010000>;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-
-	flash@1 {
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs";
-				reg = <0x00000000 0x04000000>;
-			};
-		};
-	};
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-
-	tpm@29 {
-		compatible = "atmel,at97sc3204t";
-		reg = <0x29>;
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emd1.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
deleted file mode 100644
index bca85cf4ab..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emd1.dts
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EnGenius EMD1";
-	compatible = "engenius,emd1";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g {
-			label = "red:wlan2g";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "blue:wlan5g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		mesh {
-			label = "orange:mesh";
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio54", "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition7@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-			partition8@180000 {
-				label = "userconfig";
-				reg = <0x00180000 0x00080000>;
-				read-only;
-			};
-			partition9@200000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x200000 0x01e00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts
deleted file mode 100644
index 701dc936f1..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EnGenius EMR3500";
-	compatible = "engenius,emr3500";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2_hs_phy: hsphy@a8000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-
-		blue {
-			label = "blue";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		red {
-			label = "red";
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		orange {
-			label = "orange";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio54", "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	m25p80@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-			partition@180000 {
-				label = "userconfig";
-				reg = <0x00180000 0x00080000>;
-				read-only;
-			};
-			partition@200000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x200000 0x1e00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
deleted file mode 100644
index 17bac82bfe..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EnGenius ENS620EXT";
-	compatible = "engenius,ens620ext";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		/*
-		 * Disable the broken restart as a workaround for the buggy
-		 * 3.0.0/3.0.1 U-boots that ship with the device.
-		 * Note: The watchdog is now used to restart this device.
-		 */
-		restart@4ab000 {
-			status = "disabled";
-		};
-	};
-
-	buttons {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-		};
-
-		lan1 {
-			label = "green:lan1";
-			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
-		};
-
-		lan2 {
-			label = "green:lan2";
-			gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00090000>;
-				read-only;
-			};
-			partition@180000 {
-				label = "ART";
-				reg = <0x00180000 0x00010000>;
-				read-only;
-			};
-			partition@190000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x00190000 0x14d0000>;
-			};
-			partition@1660000 {
-				label = "failsafe";
-				reg = <0x01660000 0x008F0000>;
-				read-only;
-			};
-			partition@1f50000 {
-				label = "u-boot-env";
-				reg = <0x01f50000 0x00010000>;
-				read-only;
-			};
-			partition@1f60000 {
-				label = "userconfig";
-				reg = <0x01f60000 0x000a0000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts
deleted file mode 100644
index 1495c64da9..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
-	model = "Netgear EX6100v2";
-	compatible = "netgear,ex6100v2";
-};
-
-&wifi0 {
-	qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
-
-&wifi1 {
-	qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts
deleted file mode 100644
index ce24466e54..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
-	model = "Netgear EX6150v2";
-	compatible = "netgear,ex6150v2";
-};
-
-&wifi0 {
-	qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
-
-&wifi1 {
-	qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
deleted file mode 100644
index 918224607a..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi
+++ /dev/null
@@ -1,348 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Netgear EX61X0v2";
-	compatible = "netgear,ex61x0v2";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	aliases {
-		led-boot = &power_amber;
-		led-failsafe = &power_amber;
-		led-running = &power_green;
-		led-upgrade = &power_amber;
-		label-mac-device = &gmac;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	led_spi {
-		compatible = "spi-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		num-chipselects = <0>;
-
-		led_gpio: led_gpio@0 {
-			compatible = "fairchild,74hc595";
-			reg = <0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			registers-number = <1>;
-			spi-max-frequency = <1000000>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_amber: power_amber {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
-		};
-
-		power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
-		};
-
-		right {
-			label = "blue:right";
-			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
-		};
-
-		left {
-			label = "blue:left";
-			gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
-		};
-
-		client_green {
-			label = "green:client";
-			gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
-		};
-
-		client_red {
-			label = "red:client";
-			gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
-		};
-
-		router_green {
-			label = "green:router";
-			gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
-		};
-
-		router_red {
-			label = "red:router";
-			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	mx25l12805d@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <45000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition5@E0000 {
-				label = "APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-
-			partition6@F0000 {
-				label = "APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition7@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition8@180000 {
-				label = "config";
-				reg = <0x00180000 0x00010000>;
-				read-only;
-			};
-
-			partition9@190000 {
-				label = "pot";
-				reg = <0x00190000 0x00010000>;
-				read-only;
-			};
-
-			partition10@1a0000 {
-				label = "dnidata";
-				reg = <0x001a0000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_dnidata_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_dnidata_c: macaddr@c {
-						reg = <0xc 0x6>;
-					};
-				};
-			};
-
-			partition11@1b0000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x001b0000 0x00e10000>;
-			};
-
-			partition12@fc0000 {
-				label = "language";
-				reg = <0x00fc0000 0x00040000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
deleted file mode 100644
index 524bcbcb2b..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "AVM FRITZ!Box 4040";
-	compatible = "avm,fritzbox-4040";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &flash;
-		led-running = &power;
-		led-upgrade = &flash;
-		label-mac-device = &gmac;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wlan {
-			label = "wlan";
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	switch-leds {
-		compatible = "gpio-leds";
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&ethphy0 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		panic: info_red {
-			label = "red:info";
-			gpios = <&ethphy0 1 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&ethphy1 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&ethphy2 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan {
-			function = LED_FUNCTION_LAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&ethphy3 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		flash: info_amber {
-			label = "amber:info";
-			gpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		status = "okay";
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "APPSBLENV"; /* uboot env - empty */
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "urlader"; /* APPSBL */
-				reg = <0x000f0000 0x0002dc000>;
-				read-only;
-			};
-			partition7@11dc00 {
-				/* make a backup of this partition! */
-				label = "urlader_config";
-				reg = <0x0011dc00 0x00002400>;
-				read-only;
-			};
-			partition8@120000 {
-				label = "tffs1";
-				reg = <0x00120000 0x00080000>;
-				read-only;
-			};
-			partition9@1a0000 {
-				label = "tffs2";
-				reg = <0x001a0000 0x00080000>;
-				read-only;
-			};
-			partition10@220000 {
-				label = "uboot";
-				reg = <0x00220000 0x00080000>;
-				read-only;
-			};
-			partition11@2A0000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x002a0000 0x01c60000>;
-			};
-			partition12@1f00000 {
-				label = "jffs2";
-				reg = <0x01f00000 0x00100000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&ethphy0 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&ethphy1 {
-	gpio-controller;
-	#gpio-cells = <2>;
-
-	enable-usb-power {
-		gpio-hog;
-		line-name = "enable USB3 power";
-		gpios = <1 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-};
-
-&ethphy2 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&ethphy3 {
-	gpio-controller;
-	#gpio-cells = <2>;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts
deleted file mode 100644
index cdb0093217..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-a1300.dts
+++ /dev/null
@@ -1,343 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-A1300";
-	compatible = "glinet,gl-a1300", "qcom,ipq4019";
-
-	aliases {
-		led-boot = &led_run;
-		led-failsafe = &led_run;
-		led-running = &led_run;
-		led-upgrade = &led_run;
-		label-mac-device = &swport4;
-	};
-
-	chosen {
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		switch {
-			label = "switch-button";
-			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_SETUP>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_run: blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		white {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	gpio_export {
-		compatible = "gpio-export";
-
-		usb {
-			gpio-export,name = "usb_power";
-			gpio-export,output = <1>;
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-			};
-
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@180000 {
-				label = "log";
-				reg = <0x00180000 0x00020000>;
-			};
-		};
-	};
-
-	spi-nand@1 {
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x08000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		pinmux {
-			pins = "gpio58", "gpio59";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	spi0_pins: spi0_pinmux {
-		mux_spi {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio5";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
-	status = "okay";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "GL-A1300";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "GL-A1300";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts
deleted file mode 100644
index 5fc97d7bb2..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts
+++ /dev/null
@@ -1,308 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-AP1300";
-	compatible = "glinet,gl-ap1300";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		status = "okay";
-
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-			};
-
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: mac-address@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: mac-address@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-
-	spi-nand@1 {
-		status = "okay";
-
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x08000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi0_pins: spi0_pinmux {
-		mux_spi {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio5";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan";
-
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
-	status = "okay";
-	label = "wan";
-
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "GL-AP1300";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "GL-AP1300";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts
deleted file mode 100644
index fa3ed8b054..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts
+++ /dev/null
@@ -1,298 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MikroTik hAP ac2";
-	compatible = "mikrotik,hap-ac2";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x08000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_user;
-		led-failsafe = &led_user;
-		led-running = &led_user;
-		led-upgrade = &led_user;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		mode {
-			label = "mode";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-			panic-indicator;
-		};
-
-		led_user: user {
-			label = "green:user";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	enable-usb-power {
-		gpio-hog;
-		gpios = <2 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable USB power";
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-					size = <0x2000>;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@100000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&ethphy0 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy1 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy2 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy3 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy4 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
deleted file mode 100644
index 988b86b68d..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
-	model = "8devices Jalapeno";
-	compatible = "8dev,jalapeno";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi
deleted file mode 100644
index bb293bb57e..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi
+++ /dev/null
@@ -1,279 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	aliases {
-		ethernet1 = &swport5;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		pinmux_1 {
-			pins = "gpio53";
-			function = "mdio";
-		};
-
-		pinmux_2 {
-			pins = "gpio52";
-			function = "mdc";
-		};
-
-		pinconf {
-			pins = "gpio52", "gpio53";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		status = "okay";
-
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-
-	spi-nand@1 {
-		status = "okay";
-
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x08000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts
deleted file mode 100644
index 501aed5467..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "devolo Magic 2 WiFi next";
-	compatible = "devolo,magic-2-wifi-next";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		gpio_export {
-			compatible = "gpio-export";
-			#size-cells = <0>;
-
-			plc {
-				gpio-export,name = "plc-enable";
-				gpio-export,output = <1>;
-				gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
-			};
-		};
-
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wlan {
-			label = "WLAN";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "Reset";
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		status_dlan {
-			label = "white:dlan";
-			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		status_wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		error_dlan {
-			label = "red:dlan";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-	};
-};
-
-&tlmm {
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio61", "gpio60";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	button_pins: button_pinmux {
-		mux {
-			function = "gpio";
-			pins = "gpio0", "gpio5";
-			bias-disable;
-			input;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		linux,modalias = "n25q128a11";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-			};
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-			firmware@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x00180000 0x01a80000>;
-			};
-		};
-	};
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "ghn";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
deleted file mode 100644
index cab34b5a6c..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
- * Author: Robert Marko <robert@meshpoint.me>
- */
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
-	model = "Crisis Innovation Lab MeshPoint.One";
-	compatible = "cilab,meshpoint-one";
-
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-	};
-
-	soc {
-		i2c-gpio {
-			status = "okay";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			compatible = "i2c-gpio";
-			gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
-					 &tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
-					>;
-
-			bme280@76 {
-				status = "okay";
-
-				compatible = "bosch,bme280";
-				reg = <0x76>;
-			};
-
-			pcf2129@51 {
-				status = "okay";
-
-				compatible = "nxp,pcf2129";
-				reg = <0x51>;
-			};
-
-			ina230@40 {
-				status = "okay";
-
-				compatible = "ti,ina230";
-				reg = <0x40>;
-				shunt-resistor = <2000>;
-			};
-
-			ina230@44 {
-				status = "okay";
-
-				compatible = "ti,ina230";
-				reg = <0x44>;
-				shunt-resistor = <2000>;
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART >;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status: status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287.dts
deleted file mode 100644
index fc4bae6937..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
-	model = "ZTE MF287";
-	compatible = "zte,mf287";
-};
-
-&gpio_modem_reset {
-	gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
-	gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
-	gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
-	gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-
-	spi-nand@1 { /* flash@1 ? */
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0x140000>;
-				read-only;
-			};
-
-			partition@140000 {
-				label = "ART";
-				reg = <0x140000 0x140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@280000 {
-				label = "mac";
-				reg = <0x280000 0x140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mac_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@3c0000 {
-				label = "cfg-param";
-				reg = <0x3c0000 0x600000>;
-				read-only;
-			};
-
-			partition@9c0000 {
-				label = "oops";
-				reg = <0x9c0000 0x140000>;
-			};
-
-			partition@b00000 {
-				label = "web";
-				reg = <0xb00000 0x800000>;
-			};
-
-			partition@1300000 {
-				label = "rootfs";
-				reg = <0x1300000 0x2200000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x3200000>;
-			};
-		};
-	};
-
-	zigbee@2 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "silabs,em3581";
-		reg = <2>;
-		spi-max-frequency = <12000000>;
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59", "gpio1";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&wifi0 {
-	qcom,ath10k-calibration-variant = "zte,mf287";
-};
-
-&wifi1{
-	qcom,ath10k-calibration-variant = "zte,mf287";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
deleted file mode 100644
index 3784e62d0b..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287_common.dtsi
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-	};
-
-	chosen {
-		/*
-		 * bootargs forced by u-boot bootipq command:
-		 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
-		 */
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status: led-0 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-		};
-	};
-
-	gpio_export {
-		compatible = "gpio-export";
-		#size-cells = <0>;
-
-		gpio_modem_reset: modem {
-			gpio-export,name = "modem-reset";
-			gpio-export,output = <0>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		key_reset: key-reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-		};
-
-		key_wps: key-wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_mac_0 2>;
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 0>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 1>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287plus.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287plus.dts
deleted file mode 100644
index 8eb8ce8503..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287plus.dts
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
-	model = "ZTE MF287Plus";
-	compatible = "zte,mf287plus";
-};
-
-&gpio_modem_reset {
-	gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
-	gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
-	gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
-	gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-
-	spi-nand@1 { /* flash@1 ? */
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0x140000>;
-				read-only;
-			};
-
-			partition@140000 {
-				label = "ART";
-				reg = <0x140000 0x140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@280000 {
-				label = "mac";
-				reg = <0x280000 0x140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mac_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@3c0000 {
-				label = "cfg-param";
-				reg = <0x3c0000 0x600000>;
-				read-only;
-			};
-
-			partition@9c0000 {
-				label = "oops";
-				reg = <0x9c0000 0x140000>;
-			};
-
-			partition@b00000 {
-				label = "web";
-				reg = <0xb00000 0x800000>;
-			};
-
-			partition@1300000 {
-				label = "rootfs";
-				reg = <0x1300000 0x2200000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x3200000>;
-			};
-		};
-	};
-
-	zigbee@2 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "silabs,em3581";
-		reg = <2>;
-		spi-max-frequency = <12000000>;
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59", "gpio1";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&wifi0 {
-	qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-&wifi1{
-	qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287pro.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287pro.dts
deleted file mode 100644
index b4b9451cb2..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-mf287pro.dts
+++ /dev/null
@@ -1,276 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
-	model = "ZTE MF287Pro";
-	compatible = "zte,mf287pro";
-
-	regulator-usb-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "USB_VBUS";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-		gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&gpio_modem_reset {
-	gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
-	gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
-	gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
-	gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <2000>;
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
-				<&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-
-	spi-nand@1 { /* flash@1 ? */
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0xa0000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "ART";
-				reg = <0xa0000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@120000 {
-				label = "mac";
-				reg = <0x120000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mac_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1a0000 {
-				label = "reserved2";
-				reg = <0x1a0000 0xc0000>;
-			};
-
-			partition@260000 {
-				label = "cfg-param";
-				reg = <0x260000 0x400000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "log";
-				reg = <0x660000 0x400000>;
-			};
-
-			partition@a60000 {
-				label = "oops";
-				reg = <0xa60000 0xa0000>;
-			};
-
-			partition@b00000 {
-				label = "reserved3";
-				reg = <0xb00000 0x500000>;
-			};
-
-			partition@1000000 {
-				label = "web";
-				reg = <0x1000000 0x800000>;
-			};
-
-			partition@1800000 {
-				label = "rootfs";
-				reg = <0x1800000 0x1d00000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x3200000>;
-			};
-		};
-	};
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio12", "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12", "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi0 {
-	qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi1{
-	qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
deleted file mode 100644
index a9e9683592..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts
+++ /dev/null
@@ -1,365 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "ZyXEL NBG6617";
-	compatible = "zyxel,nbg6617";
-
-	chosen {
-		/*
-		 * the vendor u-boot adds root and mtdparts cmdline parameters
-		 * which we don't want... but we have to overwrite them or else
-		 * the kernel will take them at face value.
-		 */
-		bootargs-append = " mtdparts= root=31:13";
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wlan {
-			label = "wlan";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			linux,code = <KEY_RFKILL>;
-			linux,input-type = <EV_SW>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
-			linux,default-trigger = "usbport";
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-low;
-		};
-	};
-	led_pins: led_pinmux {
-		mux {
-			pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
-			drive-strength = <0x8>;
-			bias-disable;
-			output-low;
-		};
-	};
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		status = "okay";
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "APPSBL"; /* u-boot */
-				reg = <0x000e0000 0x00080000>;
-				/* U-Boot Standalone App "zloader" is located at 0x64000 */
-				read-only;
-			};
-			partition6@160000 {
-				label = "APPSBLENV"; /* u-boot env */
-				reg = <0x00160000 0x00010000>;
-			};
-			partition7@170000 {
-				/* make a backup of this partition! */
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-			partition8@180000 {
-				label = "kernel";
-				reg = <0x00180000 0x00400000>;
-			};
-			partition9@580000 {
-				label = "dualflag";
-				reg = <0x00580000 0x00010000>;
-				read-only;
-			};
-			partition10@590000 {
-				label = "header";
-				reg = <0x00590000 0x00010000>;
-			};
-			partition11@5a0000 {
-				label = "romd";
-				reg = <0x005a0000 0x00100000>;
-				read-only;
-			};
-			partition12@6a0000 {
-				label = "not_root_data";
-				/*
-				 * for some strange reason, someone at ZyXEL
-				 * had the "great" idea to put the rootfs_data
-				 * in front of rootfs... Don't do that!
-				 * As a result this one, full MebiByte remains
-				 * unused.
-				 */
-				reg = <0x006a0000 0x00100000>;
-			};
-			partition13@7a0000 {
-				label = "rootfs";
-				reg = <0x007a0000 0x01860000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts
deleted file mode 100644
index f23b58a3f4..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Plasma Cloud PA1200";
-	compatible = "plasmacloud,pa1200";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &led_status_purple;
-		led-failsafe = &led_status_yellow;
-		led-running = &led_status_cyan;
-		led-upgrade = &led_status_yellow;
-		label-mac-device = &swport5;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_cyan: status_cyan {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_CYAN>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_purple: status_purple {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_PURPLE>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_yellow: status_yellow {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_YELLOW>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		/* partitions are passed via bootloader */
-		partitions {
-			partition-art {
-				label = "0:ART";
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "ethernet2";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
-	status = "okay";
-	label = "ethernet1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts
deleted file mode 100644
index 38158fbfa7..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ASUS RT-AC58U";
-	compatible = "asus,rt-ac58u";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x8000000>;
-	};
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: led-0 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WAN;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-			/*
-			 * linux,default-trigger = "90000.mdio-1:04:link";
-			 * sadly still lacks rx+tx
-			 */
-		};
-
-		led-2 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <2>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led-3 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <5>;
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led-4 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_USB;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			trigger-sources = <&usb3_port1>, <&usb3_port2>;
-			linux,default-trigger = "usbport";
-		};
-
-		led-5 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		/*
-		 * U-boot looks for "n25q128a11" node,
-		 * if we don't have it, it will spit out the following warning:
-		 * "ipq: fdt fixup unable to find compatible node".
-		 */
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
-		spi-max-frequency = <30000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-			/* 0x00180000 - 0x00200000 unused */
-		};
-	};
-
-	spi-nand@1 {
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <30000000>;
-
-		/*
-		 * U-boot looks for "spinand,mt29f" node,
-		 * if we don't have it, it will spit out the following warning:
-		 * "ipq: fdt fixup unable to find compatible node".
-		 */
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x08000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "RT-AC58U";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "RT-AC58U";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi
deleted file mode 100644
index 737e7365a6..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi
+++ /dev/null
@@ -1,324 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	aliases {
-		serial0 = &blsp1_uart1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		keys {
-			compatible = "gpio-keys";
-
-			reset {
-				label = "reset";
-				gpios = <&tlmm 4 1>;
-				linux,code = <KEY_RESTART>;
-			};
-		};
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54";
-		};
-		pinconf {
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio58", "gpio59";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
-	num-cs = <2>;
-	status = "okay";
-
-	xt25f128b@0 {
-		/*
-		 * Factory U-boot looks in 0:BOOTCONFIG partition for active
-		 * partitions settings and mangles the partition config so
-		 * 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and  0:APPSBL/0:APPSBL_1 pairs
-		 * can be swaped. It isn't a problem but we never can be sure where
-		 * OFW put factory images. "n25q128a11" is required for proper nor
-		 * recognition in u-boot.
-		 */
-		compatible = "jedec,spi-nor", "n25q128a11";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x60000 0x20000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x80000 0x20000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "0:QSEE";
-				reg = <0xa0000 0x60000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "0:QSEE_1";
-				reg = <0x100000 0x60000>;
-				read-only;
-			};
-
-			partition@160000 {
-				label = "0:CDT";
-				reg = <0x160000 0x10000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:CDT_1";
-				reg = <0x170000 0x10000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "0:DDRPARAMS";
-				reg = <0x180000 0x10000>;
-				read-only;
-			};
-
-			partition@190000 {
-				label = "0:APPSBLENV";
-				reg = <0x190000 0x10000>;
-				read-only;
-			};
-
-			partition@1a0000 {
-				label = "0:APPSBL";
-				reg = <0x1a0000 0xa0000>;
-				read-only;
-			};
-
-			partition@240000 {
-				label = "0:APPSBL_1";
-				reg = <0x240000 0xa0000>;
-				read-only;
-			};
-
-			partition@2e0000 {
-				label = "0:ART";
-				reg = <0x2e0000 0x10000>;
-				read-only;
-			};
-
-			config: partition@2f0000 {
-				label = "0:CONFIG";
-				reg = <0x2f0000 0x10000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "0:CONFIG_RW";
-				reg = <0x300000 0x10000>;
-				read-only;
-			};
-
-			partition@310000 {
-				label = "0:EVENTSLOG";
-				reg = <0x310000 0x90000>;
-				read-only;
-			};
-		};
-	};
-
-	xt26g02a@1 {
-		/*
-		 * Factory U-boot looks in 0:BOOTCONFIG partition for active
-		 * partitions settings and mangles the partition config so
-		 * rootfs/rootfs_1 pairs can be swaped.
-		 * It isn't a problem but we never can be sure where OFW put
-		 * factory images. "spinand,mt29f" value is required for proper
-		 * nand recognition in u-boot.
-		 */
-		compatible = "spi-nand", "spinand,mt29f";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs_1";
-				reg = <0x00000000 0x08000000>;
-			};
-
-			partition@8000000 {
-				label = "rootfs";
-				reg = <0x08000000 0x08000000>;
-			};
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	phy-reset-gpio = <&tlmm 62 0>;
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts
deleted file mode 100644
index 8fc976a11b..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
-	model = "Teltonika RUTX10";
-	compatible = "teltonika,rutx10";
-
-	soc {
-		leds {
-			compatible = "gpio-leds";
-
-			wifi2g {
-				label = "green:wifi2g";
-				gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "phy0tpt";
-			};
-
-			wifi5g {
-				label = "green:wifi5g";
-				gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "phy1tpt";
-			};
-		};
-
-		gpio_export {
-			compatible = "gpio-export";
-			#size-cells = <0>;
-
-			gpio_out {
-				gpio-export,name = "gpio_out";
-				gpio-export,output = <0>;
-				gpio-export,direction_may_change = <0>;
-				gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
-			};
-
-			gpio_in {
-				gpio-export,name = "gpio_in";
-				gpio-export,input = <0>;
-				gpio-export,direction_may_change = <0>;
-				gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
-			};
-		};
-	};
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <400000>;
-
-	stm32_io: stm32@74 {
-		compatible = "tlt,stm32v1";
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		gpio-controller;
-		interrupt-controller;
-		interrupt-parent = <&tlmm>;
-		interrupts = <5 2>;
-		reg = <0x74>;
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts
deleted file mode 100644
index ea2102f7d6..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-rutx50.dts
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
-	model = "Teltonika RUTX50";
-	compatible = "teltonika,rutx50";
-
-	aliases {
-		led-boot = &led_rssi0;
-		led-failsafe = &led_rssi0;
-		led-running = &led_rssi0;
-		led-upgrade = &led_rssi0;
-		label-mac-device = &gmac;
-	};
-
-	soc {
-		gpio-export {
-			compatible = "gpio-export";
-			#size-cells = <0>;
-
-			gpio_modem_reset {
-				gpio-export,name = "modem_reset";
-				gpio-export,output = <0>;
-				gpios = <&shift_io 8 GPIO_ACTIVE_HIGH>;
-			};
-
-			gpio_modem_power {
-				gpio-export,name = "modem_power";
-				gpio-export,output = <0>;
-				gpios = <&shift_io 9 GPIO_ACTIVE_HIGH>;
-			};
-
-			gpio_out_1 {
-				gpio-export,name = "sim-select";
-				/* 0 = SIM1 ; 1 = SIM2 */
-				gpio-export,output = <0>;
-				gpios = <&shift_io 10 GPIO_ACTIVE_HIGH>;
-			};
-
-			gpio_in_1 {
-				gpio-export,name = "sim-detect";
-				gpio-export,input = <0>;
-				gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			};
-		};
-
-		leds {
-			compatible = "gpio-leds";
-
-			led-0 {
-				label = "green:sim1";
-				gpios = <&shift_io 14 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-1 {
-				label = "green:sim2";
-				gpios = <&shift_io 15 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-2 {
-				label = "green:eth";
-				gpios = <&shift_io 6 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-3 {
-				label = "green:wifi";
-				gpios = <&shift_io 7 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-4 {
-				label = "green:3g";
-				gpios = <&shift_io 5 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-5 {
-				label = "green:4g";
-				gpios = <&shift_io 4 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-6 {
-				label = "green:5g";
-				gpios = <&shift_io 3 GPIO_ACTIVE_HIGH>;
-			};
-
-			led_rssi0: led-7 {
-				label = "green:rssi0";
-				gpios = <&shift_io 0 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-8 {
-				label = "green:rssi1";
-				gpios = <&shift_io 1 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-9 {
-				label = "green:rssi2";
-				gpios = <&shift_io 2 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-10 {
-				label = "green:wifi2g";
-				gpios = <&shift_io 12 GPIO_ACTIVE_HIGH>;
-			};
-
-			led-11 {
-				label = "green:wifi5g";
-				gpios = <&shift_io 13 GPIO_ACTIVE_HIGH>;
-			};
-		};
-
-		spi-gpio {
-			compatible = "spi-gpio";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gpio-sck = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-			gpio-mosi = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			num-chipselects = <1>;
-
-			shift_io: shift_io@0 {
-				compatible = "fairchild,74hc595";
-				reg = <0>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				/* Attn: This is specific to RUTX50 in Teltonika GPL */
-				registers-number = <2>;
-				spi-max-frequency = <10000000>;
-			};
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "wan";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts
deleted file mode 100644
index 252f9ad71a..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MikroTik SXTsq 5 ac (RBSXTsqG-5acD)";
-	compatible = "mikrotik,sxtsq-5-ac";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_user;
-		led-failsafe = &led_user;
-		led-running = &led_user;
-		led-upgrade = &led_user;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII4>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-			panic-indicator;
-		};
-
-		led_user: user {
-			label = "green:user";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		rssilow {
-			label = "green:rssilow";
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		rssimediumlow {
-			label = "green:rssimediumlow";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		rssimedium {
-			label = "green:rssimedium";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		rssimediumhigh {
-			label = "green:rssimediumhigh";
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-
-		rssihigh {
-			label = "green:rssihigh";
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@100000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-SXTsq-5-ac";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-
-	/delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-	phy-mode = "rgmii";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wac510.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wac510.dts
deleted file mode 100644
index 9bcfab4487..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wac510.dts
+++ /dev/null
@@ -1,385 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Netgear WAC510";
-	compatible = "netgear,wac510";
-
-	aliases {
-		led-boot = &led_power_amber;
-		led-failsafe = &led_power_amber;
-		led-running = &led_power_green;
-		led-upgrade = &led_power_amber;
-		ethernet1 = &swport5;
-	};
-
-	chosen {
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	led_spi {
-		compatible = "spi-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		num-chipselects = <0>;
-
-		ssr: ssr@0 {
-			compatible = "fairchild,74hc595";
-			reg = <0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			registers-number = <1>;
-			spi-max-frequency = <1000000>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power_amber: led-0 {
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
-			panic-indicator;
-		};
-
-		led_power_green: led-1 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
-		};
-
-		led-2 {
-			/* 2.4GHz blue - activity */
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <0>;
-			gpios = <&ssr 4 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led-3 {
-			/* 2.4GHz green - link */
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <0>;
-			gpios = <&ssr 3 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0radio";
-		};
-
-		led-4 {
-			/* 5GHz blue - activity */
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <1>;
-			gpios = <&ssr 2 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led-5 {
-			/* 5GHz green - link */
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <1>;
-			gpios = <&ssr 1 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1radio";
-		};
-
-		led-6 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_ACTIVITY;
-			gpios = <&ssr 0 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x000f0000>;
-				read-only;
-			};
-
-			partition@1e0000 {
-				label = "0:MANUDATA";
-				reg = <0x001e0000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_manudata_6: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1f0000 {
-				label = "0:ART";
-				reg = <0x001f0000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-
-	nand@1 {
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <48000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs";
-				reg = <0x00000000 0x03800000>;
-			};
-
-			partition@3800000 {
-				label = "rootfs_1";
-				reg = <0x03800000 0x03800000>;
-			};
-
-			partition@7000000 {
-				label = "var_config";
-				reg = <0x07000000 0x00f00000>;
-				read-only;
-			};
-
-			partition@7f00000 {
-				label = "Oops_log";
-				reg = <0x07f00000 0x000c0000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <2000>;
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_manudata_6 0>;
-	qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_manudata_6 16>;
-	qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac-lte.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac-lte.dts
deleted file mode 100644
index 8ff18d92b7..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac-lte.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
-	model = "MikroTik wAP ac LTE";
-	compatible = "mikrotik,wap-ac-lte";
-
-	soc {
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-	};
-};
-
-&tlmm {
-	enable-usb-power {
-		gpio-hog;
-		gpios = <2 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable USB power";
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dts
deleted file mode 100644
index 1bfcbf1e33..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dts
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
-	model = "MikroTik wAP ac";
-	compatible = "mikrotik,wap-ac";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi
deleted file mode 100644
index 2b357a1f03..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-ac.dtsi
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x08000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_user;
-		led-failsafe = &led_user;
-		led-running = &led_user;
-		led-upgrade = &led_user;
-	};
-
-	soc {
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		led_user: user {
-			label = "green:user";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <2>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-					size = <0x2000>;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@100000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "sw-eth2";
-};
-
-&swport5 {
-	status = "okay";
-	label = "sw-eth1";
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-r-ac.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-r-ac.dts
deleted file mode 100644
index e7f28f23cf..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wap-r-ac.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
-	model = "MikroTik wAP R ac";
-	compatible = "mikrotik,wap-r-ac";
-
-	soc {
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-	};
-};
-
-&tlmm {
-	enable-usb-power {
-		gpio-hog;
-		gpios = <2 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable USB power";
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-whw01.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-whw01.dts
deleted file mode 100644
index 1f26db5869..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-whw01.dts
+++ /dev/null
@@ -1,338 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Linksys WHW01";
-	compatible = "linksys,whw01";
-
-	aliases {
-		serial0 = &blsp1_uart1;
-		led-boot = &led_system_blue;
-		led-running = &led_system_blue;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs-append = " root=/dev/ubiblock0_0";
-	};
-
-	soc {
-		keys {
-			compatible = "gpio-keys";
-
-			reset {
-				label = "reset";
-				gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-				linux,code = <KEY_RESTART>;
-			};
-		};
-
-		ess_tcsr@1953000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-1 = <&i2c_0_pins>;
-	pinctrl-names = "i2c_active", "i2c_sleep";
-
-	leds@62 {
-		compatible = "nxp,pca9633";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x62>;
-
-		/* RGB? */
-		led@0 {
-			reg = <0>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led@1 {
-			reg = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led_system_blue: led@2 {
-			reg = <2>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-			linux,default-trigger = "default-on";
-		};
-	};
-};
-
-&blsp1_spi1 {
-	status = "okay";
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
-	nor@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "APPSBL";
-				reg = <0xd0000 0xa0000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@180000 {
-				label = "u_env";
-				reg = <0x180000 0x40000>;
-			};
-
-			partition@1c0000 {
-				label = "s_env";
-				reg = <0x1c0000 0x20000>;
-			};
-
-			partition@1e0000 {
-				label = "devinfo";
-				reg = <0x1e0000 0x20000>;
-				read-only;
-			};
-		};
-	};
-
-	nand@1 {
-		reg = <1>;
-		compatible = "spi-nand";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "kernel";
-				reg = <0x0000000 0x5000000>;
-			};
-
-			partition@600000 {
-				label = "rootfs";
-				reg = <0x0600000 0x4a00000>;
-			};
-
-			partition@5000000 {
-				label = "alt_kernel";
-				reg = <0x5000000 0x5000000>;
-			};
-
-			partition@5600000 {
-				label = "alt_rootfs";
-				reg = <0x5600000 0x4a00000>;
-			};
-
-			partition@a000000 {
-				label = "sysdiag";
-				reg = <0xa000000 0x0200000>;
-				read-only;
-			};
-
-			partition@a200000 {
-				label = "syscfg";
-				reg = <0xa200000 0x5e00000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	phy-reset-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_mdio {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_mdc {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio4";
-		};
-
-		pinconf {
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinconf_cs {
-			pins = "gpio54", "gpio4";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			function = "blsp_i2c0";
-			pins = "gpio58", "gpio59";
-			bias-disable;
-		};
-	};
-
-	reset_pinmux {
-		mux {
-			pins = "gpio63";
-			bias-pull-up;
-		};
-	};
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "linksys-whw01-v1";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "linksys-whw01-v1";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "eth1";
-};
-
-&swport5 {
-	status = "okay";
-	label = "eth2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts
deleted file mode 100644
index dd56cb215e..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts
+++ /dev/null
@@ -1,289 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Pakedge WR-1";
-	compatible = "pakedge,wr-1";
-
-	aliases {
-		label-mac-device = &gmac;
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&key_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power: power {
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		wlan2g {
-			gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x0040000 0x0020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x0060000 0x0060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0x00c0000 0x0010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x00d0000 0x0010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x00e0000 0x0010000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0x00f0000 0x0080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x0170000 0x0010000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "firmware";
-				reg = <0x0180000 0x1e80000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&tlmm {
-	key_pins: key_pinmux {
-		mux {
-			function = "gpio";
-			pins = "gpio59";
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pinmux {
-		mux {
-			function = "gpio";
-			pins = "gpio0", "gpio1", "gpio2";
-			bias-none;
-			drive-strength = <2>;
-			output-low;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			function = "blsp_uart0";
-			pins = "gpio60", "gpio61";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			bias-disable;
-			drive-strength = <12>;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			bias-disable;
-			drive-strength = <2>;
-			output-high;
-		};
-	};
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
deleted file mode 100644
index 7ce0b9e359..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts
+++ /dev/null
@@ -1,255 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "ZyXEL WRE6606";
-	compatible = "zyxel,wre6606";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	chosen {
-		bootargs-append = " mtdparts=";
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g_green {
-			label = "green:wlan5g";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g_red {
-			label = "red:wlan5g";
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_red {
-			label = "red:wlan2g";
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_green {
-			label = "green:wlan2g";
-			gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	mx25l12805d@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition5@E0000 {
-				label = "APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-
-			partition6@F0000 {
-				label = "APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition7@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-			};
-
-			partition8@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x00180000 0x00ce0000>;
-			};
-
-			partition9@e60000 {
-				label = "manufacture";
-				reg = <0x00e60000 0x00050000>;
-				read-only;
-			};
-
-			partition10@eb0000 {
-				label = "storage";
-				reg = <0x00eb0000 0x00150000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts
deleted file mode 100644
index f3c6f34bf4..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts
+++ /dev/null
@@ -1,305 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Luma Home WRTQ-329ACN";
-	compatible = "luma,wrtq-329acn";
-
-	i2c-gpio {
-		compatible = "i2c-gpio";
-		sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-		scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* No driver exists */
-		led_ring@48 {
-			compatible = "ti,msp430";
-			reg = <0x48>;
-		};
-
-		eeprom@50 {
-			compatible = "atmel,24c16";
-			reg = <0x50>;
-			pagesize = <16>;
-			read-only;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-
-&blsp1_spi1 {
-	status = "okay";
-
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 59 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&spi0_pins>;
-	pinctrl-names = "default";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x000000 0x040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x040000 0x020000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x060000 0x060000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0x0c0000 0x010000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x0d0000 0x010000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x0e0000 0x010000>;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0x0f0000 0x080000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0{
-						reg = <0x0000 0x0006>;
-					};
-
-					macaddr_art_6: macaddr@6{
-						reg = <0x0006 0x0006>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-
-	flash@1 {
-		status = "okay";
-
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x0000000 0x8000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial0_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	status = "disabled";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_art_6>;
-};
-
-&swport5 {
-	status = "okay";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_art_0>;
-};
-
-&tlmm {
-	serial0_pins: serial0_pinmux {
-		mux {
-			function = "blsp_uart0";
-			pins = "gpio60", "gpio61";
-			bias-disable;
-		};
-	};
-
-	spi0_pins: spi0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			bias-disable;
-			drive-strength = <12>;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			bias-disable;
-			drive-strength = <2>;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-a62.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-a62.dts
deleted file mode 100644
index 39a52a7c48..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-a62.dts
+++ /dev/null
@@ -1,276 +0,0 @@
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "OpenMesh A62";
-	compatible = "openmesh,a62";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART >;
-		};
-	};
-
-	aliases {
-		led-boot = &led_status_green;
-		led-failsafe = &led_status_green;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_green;
-		label-mac-device = &swport4;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		status_red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_green: status_green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-		};
-
-		status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	watchdog {
-		compatible = "linux,wdt-gpio";
-		gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-		hw_algo = "toggle";
-		/* hw_margin_ms is actually 300s but driver limits it to 60s */
-		hw_margin_ms = <60000>;
-		always-running;
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	enable-usb-power {
-		gpio-hog;
-		gpios = <58 GPIO_ACTIVE_HIGH>;
-		output-low;
-		line-name = "enable USB2 power";
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		/* partitions are passed via bootloader */
-		partitions {
-			partition-art {
-				label = "0:ART";
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "OM-A62";
-			ieee80211-freq-limit = <5170000 5350000>;
-
-			nvmem-cell-names = "pre-calibration";
-			nvmem-cells = <&precal_art_9000>;
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "ethernet1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
-	status = "okay";
-	label = "ethernet2";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "OM-A62";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "OM-A62";
-	ieee80211-freq-limit = <5470000 5875000>;
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts
deleted file mode 100644
index d1c8d798f9..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts
+++ /dev/null
@@ -1,393 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MobiPromo CM520-79F";
-	compatible = "mobipromo,cm520-79f";
-
-	aliases {
-		led-boot = &led_sys;
-		led-failsafe = &led_sys;
-		led-running = &led_sys;
-		led-upgrade = &led_sys;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <1000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	led_spi {
-		compatible = "spi-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-		mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
-		num-chipselects = <0>;
-
-		led_gpio: led_gpio@0 {
-			compatible = "fairchild,74hc595";
-			reg = <0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			registers-number = <1>;
-			spi-max-frequency = <1000000>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
-		};
-
-		led_sys: can {
-			label = "blue:can";
-			gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
-		};
-
-		lan1 {
-			label = "blue:lan1";
-			gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
-		};
-
-		lan2 {
-			label = "blue:lan2";
-			gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g {
-			label = "blue:wlan2g";
-			gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "blue:wlan5g";
-			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x100000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "MIBIB";
-				reg = <0x100000 0x100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "BOOTCONFIG";
-				reg = <0x200000 0x100000>;
-			};
-
-			partition@300000 {
-				label = "QSEE";
-				reg = <0x300000 0x100000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "QSEE_1";
-				reg = <0x400000 0x100000>;
-				read-only;
-			};
-
-			partition@500000 {
-				label = "CDT";
-				reg = <0x500000 0x80000>;
-				read-only;
-			};
-
-			partition@580000 {
-				label = "CDT_1";
-				reg = <0x580000 0x80000>;
-				read-only;
-			};
-
-			partition@600000 {
-				label = "BOOTCONFIG1";
-				reg = <0x600000 0x80000>;
-			};
-
-			partition@680000 {
-				label = "APPSBLENV";
-				reg = <0x680000 0x80000>;
-			};
-
-			partition@700000 {
-				label = "APPSBL";
-				reg = <0x700000 0x200000>;
-				read-only;
-			};
-
-			partition@900000 {
-				label = "APPSBL_1";
-				reg = <0x900000 0x200000>;
-				read-only;
-			};
-
-			art: partition@b00000 {
-				label = "ART";
-				reg = <0xb00000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					macaddr_art_1006: macaddr@1006 {
-						reg = <0x1006 0x6>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					macaddr_art_5006: macaddr@5006 {
-						reg = <0x5006 0x6>;
-					};
-				};
-			};
-
-			partition@b80000 {
-				label = "ubi";
-				reg = <0xb80000 0x7480000>;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_1006>;
-	nvmem-cell-names = "mac-address";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-
-	nvmem-cells = <&macaddr_art_5006>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "CM520-79F";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "CM520-79F";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts
deleted file mode 100644
index 243d19fb03..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Qxwlan E2600AC c1";
-	compatible = "qxwlan,e2600ac-c1";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0x1e80000>;
-			};
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "sw-eth1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "sw-eth2";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts
deleted file mode 100644
index 9300568986..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts
+++ /dev/null
@@ -1,182 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Qxwlan E2600AC c2";
-	compatible = "qxwlan,e2600ac-c2";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x04000000>;
-			};
-		};
-	};
-};
-
-&tlmm {
-	nand_pins: nand-pins {
-
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-	label = "sw-eth1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport4 {
-	status = "okay";
-	label = "sw-eth2";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "sw-eth3";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
deleted file mode 100644
index d226611311..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi
+++ /dev/null
@@ -1,246 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-
-	model = "Qxwlan E2600AC";
-	compatible = "qcom,ipq4019";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256MB */
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		serial@78af000 {
-			pinctrl-0 = <&serial_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		i2c@78b7000 { /* BLSP1 QUP2 */
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-
-			status = "okay";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		leds {
-			compatible = "gpio-leds";
-
-			led1 {
-				label = "green:wlan0";
-				gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-			};
-
-			led2 {
-				label = "green:wlan1";
-				gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
-			};
-
-			led3 {
-				function = LED_FUNCTION_USB;
-				color = <LED_COLOR_ID_GREEN>;
-				gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-				trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
-				linux,default-trigger = "usbport";
-			};
-
-			led4 {
-				label = "green:ctrl1";
-				gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
-			};
-
-			led5 {
-				label = "green:ctrl2";
-				gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
-			};
-
-			led6 {
-				label = "green:ctrl3";
-				gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
-			};
-		};
-
-		keys {
-			compatible = "gpio-keys";
-
-			reset {
-				label = "reset";
-				gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-				linux,code = <KEY_RESTART>;
-			};
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	i2c_0_pins: i2c-0-pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
deleted file mode 100644
index 1b9276ede2..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
-	model = "Linksys EA8300 (Dallas)";
-	compatible = "linksys,ea8300", "qcom,ipq4019";
-
-
-	aliases {
-		led-boot = &led_wps_amber;
-		led-failsafe = &led_wps;
-		led-running = &led_linksys;
-		led-upgrade = &led_world;
-		serial0 = &blsp1_uart1;
-	};
-
-
-	leds {
-		compatible = "gpio-leds";
-
-		// Retain node names from running OEM on EA8300
-
-		// Front panel LEDs, top to bottom
-
-		led_plug: diag {
-			label = "amber:plug";
-			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_world: internet {
-			label = "amber:world";
-			gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_wps: wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_wps_amber: wps_amber {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_linksys: pwr {
-			label = "white:linksys";
-			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-		};
-
-		// On back panel, above USB socket
-
-		led_usb: usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			trigger-sources = <&usb3_port1>, <&usb3_port2>,
-					  <&usb2_port1>;
-			linux,default-trigger = "usbport";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi1 {
-	status = "okay";
-	ieee80211-freq-limit = <5170000 5330000>;
-	qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi2 {
-	status = "okay";
-	ieee80211-freq-limit = <5490000 5835000>;
-	qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts
deleted file mode 100644
index 000acd196c..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts
+++ /dev/null
@@ -1,291 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "EnGenius EAP2200";
-	compatible = "engenius,eap2200";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-		};
-
-		lan1 {
-			label = "blue:lan1";
-			gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
-		};
-
-		lan2 {
-			label = "blue:lan2";
-			gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g {
-			label = "blue:wlan2g";
-			gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "yellow:wlan5g";
-			gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		wlan5g2 {
-			label = "yellow:wlan5g2";
-			gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy2tpt";
-		};
-
-		mode {
-			label = "blue:mode";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition7@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs1";
-				reg = <0x00000000 0x04000000>;
-			};
-			partition@40000000 {
-				label = "ubi";
-				reg = <0x04000000 0x04000000>;
-			};
-
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-			nvmem-cell-names = "pre-calibration";
-			nvmem-cells = <&precal_art_9000>;
-			ieee80211-freq-limit = <5470000 5875000>;
-			qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
-
-&wifi1 {
-	status = "okay";
-	ieee80211-freq-limit = <5170000 5350000>;
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
deleted file mode 100644
index a118bdf26b..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts
+++ /dev/null
@@ -1,325 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "AVM FRITZ!Box 7530";
-	compatible = "avm,fritzbox-7530";
-
-	chosen {
-		bootargs-append = " coherent_pool=4M";
-	};
-
-	aliases {
-		led-boot = &power_green;
-		led-failsafe = &info_red;
-		led-running = &power_green;
-		led-upgrade = &info_red;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wlan {
-			label = "wlan";
-			gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		dect {
-			label = "dect";
-			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_PHONE>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		info_red: info_red {
-			label = "red:info";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-		};
-
-		info {
-			label = "green:info";
-			gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
-		};
-
-		fon {
-			label = "green:fon";
-			gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-		};
-
-		power_green: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	usb-power {
-		line-name = "enable USB3 power";
-		gpios = <49 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		/delete-property/ nand-ecc-strength;
-		/delete-property/ nand-ecc-step-size;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x000000 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "MIBIB";
-				reg = <0x080000 0x80000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "QSEE";
-				reg = <0x100000 0x80000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "CDT";
-				reg = <0x180000 0x40000>;
-				read-only;
-			};
-
-			partition@1c0000 {
-				label = "QSEE_B";
-				reg = <0x1c0000 0x80000>;
-				read-only;
-			};
-
-			partition@240000 {
-				label = "urlader0";
-				reg = <0x240000 0x40000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "urlader1";
-				reg = <0x280000 0x40000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "nand-tffs";
-				reg = <0x2c0000 0x840000>;
-				read-only;
-			};
-
-			partition@b00000 {
-				/* 'kernel1' in AVM firmware */
-				label = "uboot0";
-				reg = <0xb00000 0x400000>;
-			};
-
-			partition@f00000 {
-				/* 'kernel2' in AVM firmware */
-				label = "uboot1";
-				reg = <0xf00000 0x400000>;
-			};
-
-			partition@1300000 {
-				label = "ubi";
-				reg = <0x1300000 0x6d00000>;
-			};
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		dsl@1,0 {
-			compatible = "intel,vrx518";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
deleted file mode 100644
index 7d683cdf65..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts
+++ /dev/null
@@ -1,294 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "AVM FRITZ!Repeater 1200";
-	compatible = "avm,fritzrepeater-1200";
-
-	aliases {
-		led-boot = &power_green;
-		led-failsafe = &power_red;
-		led-running = &power_green;
-		led-upgrade = &power_red;
-		label-mac-device = &wifi0;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			ethphy: ethernet-phy@0 {
-				reg = <0x0>;
-			};
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	key {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "WPS button";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_red: power_red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-
-		power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_yellow {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_YELLOW>;
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	phy-reset {
-		line-name = "PHY-reset";
-		gpios = <19 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-
-	phy-reset-2 {
-		line-name = "PHY-reset-2";
-		gpios = <47 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "MIBIB";
-				reg = <0x80000 0x80000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "QSEE";
-				reg = <0x100000 0x80000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "CDT";
-				reg = <0x180000 0x40000>;
-				read-only;
-			};
-
-			partition@1c0000 {
-				label = "QSEE_B";
-				reg = <0x1c0000 0x80000>;
-				read-only;
-			};
-
-			partition@240000 {
-				label = "urlader0";
-				reg = <0x240000 0x40000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "urlader1";
-				reg = <0x280000 0x40000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "nand-tffs";
-				reg = <0x2c0000 0x840000>;
-				read-only;
-			};
-
-			partition@b00000 {
-				/* 'kernel1' in AVM firmware */
-				label = "uboot0";
-				reg = <0xb00000 0x400000>;
-			};
-
-			partition@f00000 {
-				/* 'kernel2' in AVM firmware */
-				label = "uboot1";
-				reg = <0xf00000 0x400000>;
-			};
-
-			partition@1300000 {
-				label = "ubi";
-				reg = <0x1300000 0x6d00000>;
-			};
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-
-	/delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-	phy-handle = <&ethphy>;
-	phy-mode = "rgmii-id";
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	status = "disabled";
-};
-
-&ethphy4 {
-	status = "disabled";
-};
-
-&psgmiiphy {
-	status = "disabled";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
deleted file mode 100644
index 2555984384..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts
+++ /dev/null
@@ -1,274 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "AVM FRITZ!Repeater 3000";
-	compatible = "avm,fritzrepeater-3000";
-
-	aliases {
-		led-boot = &power_led;
-		led-failsafe = &power_led;
-		led-running = &power_led;
-		led-upgrade = &power_led;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	key {
-		compatible = "gpio-keys";
-
-		connect {
-			label = "Connect";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		connect_red {
-			label = "red:connect";
-			gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
-		};
-
-		connect_green {
-			label = "green:connect";
-			gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
-		};
-
-		connect_blue {
-			label = "blue:connect";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-		};
-
-		power_led: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		/delete-property/ nand-ecc-strength;
-		/delete-property/ nand-ecc-step-size;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x000000 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "MIBIB";
-				reg = <0x080000 0x80000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "QSEE";
-				reg = <0x100000 0x80000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "CDT";
-				reg = <0x180000 0x40000>;
-				read-only;
-			};
-
-			partition@1c0000 {
-				label = "QSEE_B";
-				reg = <0x1c0000 0x80000>;
-				read-only;
-			};
-
-			partition@240000 {
-				label = "urlader0";
-				reg = <0x240000 0x40000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "urlader1";
-				reg = <0x280000 0x40000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "nand-tffs";
-				reg = <0x2c0000 0x840000>;
-				read-only;
-			};
-
-			partition@b00000 {
-				/* 'kernel1' in AVM firmware */
-				label = "uboot0";
-				reg = <0xb00000 0x400000>;
-			};
-
-			partition@f00000 {
-				/* 'kernel2' in AVM firmware */
-				label = "uboot1";
-				reg = <0xf00000 0x400000>;
-			};
-
-			partition@1300000 {
-				label = "ubi";
-				reg = <0x1300000 0x6d00000>;
-			};
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
-	qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&wifi1 {
-	status = "okay";
-	ieee80211-freq-limit = <5170000 5350000>;
-	/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
-	qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			/* QCA9984 */
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			ieee80211-freq-limit = <5470000 5875000>;
-			/* Uses the reference BDF */
-		};
-	};
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts
deleted file mode 100644
index 9f645dd657..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts
+++ /dev/null
@@ -1,392 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-B2200";
-	compatible = "glinet,gl-b2200", "qcom,ipq4019";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
-	};
-
-	aliases {
-		ethernet1 = &swport4;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			linux,input-type = <1>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			linux,input-type = <1>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_blue {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-		internet_blue {
-			label = "blue:internet";
-			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
-		};
-		power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-		};
-		internet_white {
-			label = "white:internet";
-			gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_spi2 {
-	pinctrl-0 = <&spi_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	spidev1: spi@0 {
-		compatible = "silabs,si3210";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9",
-				"gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-		};
-		pinconf {
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	spi_1_pins: spi_1_pinmux {
-		mux {
-			pins = "gpio44", "gpio46", "gpio47";
-			function = "blsp_spi1";
-			bias-disable;
-		};
-		cs {
-			pins = "gpio45";
-			function = "gpio";
-			bias-pull-up;
-		};
-		reset {
-			pins = "gpio43";
-			function = "gpio";
-			output-high;
-		};
-		mux_2 {
-			pins = "gpio35";
-			function = "gpio";
-			output-high;
-		};
-		host_int {
-			pins = "gpio2";
-			function = "gpio";
-			input;
-		};
-		wake {
-			pins = "gpio48";
-			function = "gpio";
-			output-high;
-		};
-	};
-
-	sd_pins: sd_pins {
-		pinmux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio29", "gpio30", "gpio31", "gpio32";
-			drive-strength = <10>;
-		};
-
-		pinmux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-
-		pinmux_sd7 {
-			function = "sdio";
-			pins = "gpio28";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			status = "okay";
-			/* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-			nvmem-cell-names = "pre-calibration";
-			nvmem-cells = <&precal_art_9000>;
-			qcom,ath10k-calibration-variant = "GL-B2200";
-			ieee80211-freq-limit = <5450000 5900000>;
-		};
-	};
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "wan";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "GL-B2200";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "GL-B2200";
-	ieee80211-freq-limit = <5100000 5400000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts
deleted file mode 100644
index 26e9941a9f..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts
+++ /dev/null
@@ -1,392 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "8devices Habanero DVK";
-	compatible = "8dev,habanero-dvk";
-
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_upgrade;
-		ethernet1 = &swport5;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status: status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_upgrade: upgrade {
-			label = "green:upgrade";
-			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =  "gpio52", "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56", "gpio57",
-				"gpio60", "gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67", "gpio68",
-				"gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	sd_pins: sd_pins {
-		pinmux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio28", "gpio29", "gpio30", "gpio31";
-			drive-strength = <10>;
-		};
-
-		pinmux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-
-		pinmux_sd7 {
-			function = "sdio";
-			pins = "gpio32";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-		reg = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "APPSBLENV"; /* uboot env */
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition@180000 {
-				label = "cfg";
-				reg = <0x00180000 0x00040000>;
-			};
-			partition@1c0000 {
-				label = "firmware";
-				compatible = "denx,fit";
-				reg = <0x001c0000 0x01e40000>;
-			};
-		};
-	};
-};
-
-/* Some DVK boards ship without NAND */
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	/* Free slot for use */
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-	};
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts
deleted file mode 100644
index 52af1f125e..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3-lte6-kit.dts
+++ /dev/null
@@ -1,318 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MikroTik hAP ac3 LTE6 kit";
-	compatible = "mikrotik,hap-ac3-lte6-kit";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_status_blue;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_red;
-	};
-
-	soc {
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_blue: status-blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_red: status-red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_status_green: status-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		ethernet {
-			label = "green:ethernet";
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan1 {
-			label = "green:lan1";
-			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan2 {
-			label = "green:lan2";
-			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan3 {
-			label = "green:lan3";
-			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan4 {
-			label = "green:lan4";
-			gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	enable-usb-power {
-		gpio-hog;
-		gpios = <44 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable USB power";
-	};
-
-	enable-mpcie-power {
-		gpio-hog;
-		gpios = <51 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable mPCI-E power";
-	};
-
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <10000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-
-		partitions {
-			compatible = "fixed-partitions";
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					size = <0x2000>;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@110000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x110000 0xef0000>;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-};
-
-&wifi1 {
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts
deleted file mode 100644
index 4e2b4574d3..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts
+++ /dev/null
@@ -1,357 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "MikroTik hAP ac3";
-	compatible = "mikrotik,hap-ac3";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &led_status_blue;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_red;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		mode {
-			label = "mode";
-			gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-
-		led {
-			label = "led";
-			gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_blue: status-blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_red: status-red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_status_green: status-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		ethernet {
-			label = "green:ethernet";
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan1 {
-			label = "green:lan1";
-			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan2 {
-			label = "green:lan2";
-			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan3 {
-			label = "green:lan3";
-			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan4 {
-			label = "green:lan4";
-			gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-		};
-
-		poe {
-			label = "red:poe";
-			gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio55", "gpio56", "gpio57", "gpio60",
-				   "gpio62", "gpio63", "gpio64", "gpio65",
-				   "gpio66", "gpio67", "gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	enable-usb-power {
-		gpio-hog;
-		gpios = <44 GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "enable USB power";
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-					size = <0x2000>;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "kernel";
-				reg = <0x0 0xa00000>;
-			};
-
-			partition@a00000 {
-				label = "ubi";
-				reg = <0xa00000 0x7600000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts
deleted file mode 100644
index 4e5497cbc3..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lbr20.dts
+++ /dev/null
@@ -1,516 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Netgear LBR20";
-	compatible = "netgear,lbr20";
-
-	chosen {
-		bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
-	};
-
-	aliases {
-		led-boot = &led_backlight_white;
-		led-failsafe = &led_status_green;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_red;
-		label-mac-device = &gmac;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_green: led-status-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		led_status_red: led-status-red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_export {
-		compatible = "gpio-export";
-		#size-cells = <0>;
-
-		lte_rst {
-			gpio-export,name = "lte_rst";
-			gpio-export,output = <1>;
-			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-		};
-
-		lte_pwrkey {
-			gpio-export,name = "lte_pwrkey";
-			gpio-export,output = <1>;
-			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
-		};
-
-		lte_usb_boot {
-			gpio-export,name = "lte_usb_boot";
-			gpio-export,output = <0>;
-			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
-		};
-
-		lte_pwm {
-			gpio-export,name = "lte_pwm";
-			gpio-export,output = <1>;
-			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
-		};
-
-	};
-
-	soc {
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-		
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio-pinmux {
-		mux_mdio {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_mdc {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial-pinmux {
-		function = "blsp_uart0";
-		pins = "gpio16", "gpio17";
-		bias-disable;
-	};
-
-	nand_pins: nand-pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00100000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "0:MIBIB";
-				reg = <0x00100000 0x00100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x00200000 0x00100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "0:QSEE";
-				reg = <0x00300000 0x00100000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "0:QSEE_1";
-				reg = <0x00400000 0x00100000>;
-				read-only;
-			};
-
-			partition@500000 {
-				label = "0:CDT";
-				reg = <0x00500000 0x00080000>;
-				read-only;
-			};
-
-			partition@580000 {
-				label = "0:CDT_1";
-				reg = <0x00580000 0x00080000>;
-				read-only;
-			};
-
-			partition@600000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x00600000 0x00080000>;
-				read-only;
-			};
-
-			partition@680000 {
-				label = "0:APPSBLENV";
-				reg = <0x00680000 0x00080000>;
-			};
-
-			partition@700000 {
-				label = "0:APPSBL";
-				reg = <0x00700000 0x00200000>;
-				read-only;
-			};
-
-			partition@900000 {
-				label = "0:APPSBL_1";
-				reg = <0x00900000 0x00200000>;
-				read-only;
-			};
-
-			partition@b00000 {
-				label = "0:ART";
-				reg = <0x00b00000 0x00080000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-
-				};
-			};
-
-			partition@b80000 {
-				label = "0:ART.bak";
-				reg = <0x00b80000 0x00080000>;
-				read-only;
-			};
-
-			partition@c00000 {
-				label = "config";
-				reg = <0x00c00000 0x00100000>;
-				read-only;
-			};
-
-			partition@d00000 {
-				label = "boarddata1";
-				reg = <0x00d00000 0x00080000>;
-				read-only;
-				
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					mac_address_lan: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					mac_address_wan: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					mac_address_wlan_5g: macaddr@c {
-						compatible = "mac-base";
-						reg = <0xc 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					mac_address_wlan_2nd5g: macaddr@12 {
-						compatible = "mac-base";
-						reg = <0x12 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-				};
-			};
-
-			partition@d80000 {
-				label = "boarddata2";
-				reg = <0x00d80000 0x00040000>;
-				read-only;
-			};
-
-			partition@dc0000 {
-				label = "pot";
-				reg = <0x00dc0000 0x00100000>;
-				read-only;
-			};
-
-			partition@ec0000 {
-				label = "boarddata1.bak";
-				reg = <0x00ec0000 0x00080000>;
-				read-only;
-			};
-
-			partition@f40000 {
-				label = "boarddata2.bak";
-				reg = <0x00f40000 0x00040000>;
-				read-only;
-			};
-
-			partition@f80000 {
-				label = "language";
-				reg = <0x00f80000 0x00300000>;
-				read-only;
-			};
-
-			partition@1280000 {
-				label = "cert";
-				reg = <0x01280000 0x00080000>;
-				read-only;
-			};
-
-			partition@1300000 {
-				label = "ntgrdata";
-				reg = <0x01300000 0x09300000>;
-			};
-
-			partition@a600000 {
-				label = "kernel";
-				reg = <0x0a600000 0x00700000>;
-			};
-
-			partition@a9c0000 {
-				label = "ubi";
-				reg = <0x0ad00000 0x05300000>;
-			};
-
-		};
-	};
-};
-
-&blsp1_i2c3 {
-	status = "okay";
-
-	led-controller {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "ti,tlc59108"; /* really is tlc59208f */
-		reg = <0x27>;
-
-		led_backlight_green: led-backlight-green {
-			function = LED_FUNCTION_BACKLIGHT;
-			color = <LED_COLOR_ID_GREEN>;
-			reg = <0x0>;
-			linux,default-trigger = "default-off";
-		};
-
-		led_backlight_red: led-backlight-red {
-			function = LED_FUNCTION_BACKLIGHT;
-			color = <LED_COLOR_ID_RED>;
-			reg = <0x1>;
-			linux,default-trigger = "default-off";
-		};
-
-		led_backlight_blue: led-backlight-blue {
-			function = LED_FUNCTION_BACKLIGHT;
-			color = <LED_COLOR_ID_BLUE>;
-			reg = <0x2>;
-			linux,default-trigger = "default-off";
-		};
-
-		led_backlight_white: led-backlight-white {
-			function = LED_FUNCTION_BACKLIGHT;
-			color = <LED_COLOR_ID_WHITE>;
-			reg = <0x3>;
-			linux,default-trigger = "default-off";
-		};
-
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&mac_address_lan 0>;
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-	label = "lan2";
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			ieee80211-freq-limit = <5170000 5350000>;
-			nvmem-cell-names = "pre-calibration", "mac-address";
-			nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
-			qcom,ath10k-calibration-variant = "Netgear-LBR20";
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
-	qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
-
-&wifi1 {
-	status = "okay";
-	ieee80211-freq-limit = <5470000 5815000>;
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
-	qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-le1.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-le1.dts
deleted file mode 100644
index c4e7d0b207..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-le1.dts
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "YYeTs LE1";
-	compatible = "yyets,le1";
-
-	aliases {
-		led-boot = &led_usb;
-		led-failsafe = &led_usb;
-		led-upgrade = &led_usb;
-
-		ethernet0 = &swport5;
-		ethernet1 = &gmac;
-		label-mac-device = &gmac;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_usb: usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
-		};
-
-		wlan2g {
-			label = "green:wlan2g";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "green:wlan5g";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0x1e80000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&mdio {
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2 {
-	status = "okay";
-
-	dwc3@6000000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		usb2_port1: port@1 {
-			reg = <1>;
-			#trigger-source-cells = <0>;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-
-	dwc3@8a00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		usb3_port1: port@1 {
-			reg = <1>;
-			#trigger-source-cells = <0>;
-		};
-
-		usb3_port2: port@2 {
-			reg = <2>;
-			#trigger-source-cells = <0>;
-		};
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cells = <&precal_art_1000>;
-	nvmem-cell-names = "pre-calibration";
-	qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cells = <&precal_art_5000>;
-	nvmem-cell-names = "pre-calibration";
-	qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts
deleted file mode 100644
index 4f0eaa625b..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts
+++ /dev/null
@@ -1,284 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Robert Marko <robimarko@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Mikrotik Wireless Wire Dish LHGG-60ad";
-	compatible = "mikrotik,lhgg-60ad";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		led-boot = &user;
-		led-failsafe = &user;
-		led-running = &user;
-		led-upgrade = &user;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-			panic-indicator;
-		};
-
-		user: user {
-			label = "yellow:user";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		align-left {
-			label = "green:align-left";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		align-right {
-			label = "green:align-right";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan-rx {
-			label = "green:align-down";
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan-tx {
-			label = "green:align-up";
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi-0-pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-
-	m25p80@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "Qualcomm";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "mikrotik,routerboot-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				label = "RouterBoot";
-				reg = <0x80000 0x80000>;
-
-				hard_config {
-					read-only;
-					size = <0x2000>;
-				};
-
-				dtb_config {
-					read-only;
-				};
-
-				soft_config {
-				};
-			};
-
-			partition@100000 {
-				compatible = "mikrotik,minor";
-				label = "firmware";
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		/* wil6210 802.11ad card */
-		wifi: wifi@1,0 {
-			status = "okay";
-			/* wil6210 driver has no compatible */
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	status = "disabled";
-};
-
-&ethphy4 {
-	status = "disabled";
-};
-
-&psgmiiphy {
-	status = "disabled";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-
-	/delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-	phy-handle = <&ethphy0>;
-	phy-mode = "rgmii-id";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts
deleted file mode 100644
index 32f0473fb1..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts
+++ /dev/null
@@ -1,363 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ASUS Lyra MAP-AC2200";
-	compatible = "asus,map-ac2200";
-
-	aliases {
-		led-boot = &led_blue0;
-		led-failsafe = &led_red0;
-		led-running = &led_blue0;
-		led-upgrade = &led_red0;
-		ethernet1 = &swport4;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x80000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "MIBIB";
-				reg = <0x80000 0x80000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "QSEE";
-				reg = <0x100000 0x100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "CDT";
-				reg = <0x200000 0x80000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "APPSBL";
-				reg = <0x280000 0x140000>;
-				read-only;
-			};
-
-			partition@3c0000 {
-				label = "APPSBLENV";
-				reg = <0x3c0000 0x40000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "ubi";
-				reg = <0x400000 0x7c00000>;
-			};
-		};
-	};
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		pinmux {
-			function = "blsp_i2c0";
-			pins = "gpio20", "gpio21";
-			drive-strength = <16>;
-			bias-disable;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-	enable_ext_pa_high {
-		gpio-hog;
-		gpios = <44 GPIO_ACTIVE_HIGH>,
-			<46 GPIO_ACTIVE_HIGH>;
-		output-high;
-		bias-pull-down;
-		line-name = "enable external PA output-high";
-	};
-	enable_ext_pa_low {
-		gpio-hog;
-		gpios = <45 GPIO_ACTIVE_HIGH>,
-			<47 GPIO_ACTIVE_HIGH>;
-		output-low;
-		bias-pull-down;
-		line-name = "enable external PA output-low";
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
-	ieee80211-freq-limit = <5470000 5875000>;
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
-			ieee80211-freq-limit = <5170000 5350000>;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	/* Bluetooth module attached via USB */
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	led-controller@32 {
-		/* 9-channel RGB LED controller */
-		compatible = "national,lp5523";
-		reg = <0x32>;
-		clock-mode = /bits/ 8 <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/*
-		 * There is only one single extremely bright RGB-LED.
-		 * The RGB-color channels are running in parallel to
-		 * increase the current delivery capabilities beyond
-		 * what a single PWM-output of the controller can do.
-		 */
-
-		led_blue0: led@0 {
-			chan-name = "blue-0";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <0>;
-			color = <LED_COLOR_ID_BLUE>;
-			function-enumerator = <0>;
-		};
-
-		led@1 {
-			chan-name = "blue-1";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <1>;
-			color = <LED_COLOR_ID_BLUE>;
-			function-enumerator = <1>;
-		};
-
-		led@2 {
-			chan-name = "blue-2";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <2>;
-			color = <LED_COLOR_ID_BLUE>;
-			function-enumerator = <2>;
-		};
-
-		led_green0: led@3 {
-			chan-name = "green-0";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <3>;
-			color = <LED_COLOR_ID_GREEN>;
-			function-enumerator = <0>;
-		};
-
-		led@4 {
-			chan-name = "green-1";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <4>;
-			color = <LED_COLOR_ID_GREEN>;
-			function-enumerator = <1>;
-		};
-
-		led@5 {
-			chan-name = "green-2";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <5>;
-			color = <LED_COLOR_ID_GREEN>;
-			function-enumerator = <2>;
-		};
-
-		led_red0: led@6 {
-			chan-name = "red-0";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <6>;
-			color = <LED_COLOR_ID_RED>;
-			function-enumerator = <0>;
-		};
-
-		led@7 {
-			chan-name = "red-1";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <7>;
-			color = <LED_COLOR_ID_RED>;
-			function-enumerator = <1>;
-		};
-
-		led@8 {
-			chan-name = "red-2";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-			reg = <8>;
-			color = <LED_COLOR_ID_RED>;
-			function-enumerator = <2>;
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "wan";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts
deleted file mode 100644
index 6987515720..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf18a.dts
+++ /dev/null
@@ -1,490 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Marcin Gajda <mgajda@o2.pl>.
-
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ZTE MF18A";
-	compatible = "zte,mf18a";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	chosen {
-		/*
-		 * bootargs forced by u-boot bootipq command:
-		 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
-		 */
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	gpio-restart {
-		compatible = "gpio-restart";
-		gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_internal: led-0 {
-			label = "blue:internal";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		led_power: led-1 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		led-2 {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led-3 {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		led-4 {
-			function = LED_FUNCTION_WLAN;
-			label = "blue:smart";
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led-5 {
-			label = "red:smart";
-			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		resetzwave {
-			label = "resetzwave";
-			gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		/* u-boot is looking for "n25q128a11" property */
-		compatible = "jedec,spi-nor", "n25q128a11";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-				};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "wan";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0xa0000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "ART";
-				reg = <0xa0000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-
-			partition@120000 {
-				label = "mac";
-				reg = <0x120000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_config_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1a0000 {
-				label = "reserved2";
-				reg = <0x1a0000 0xc0000>;
-				read-only;
-			};
-
-			partition@260000 {
-				label = "cfg-param";
-				reg = <0x260000 0x400000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "log";
-				reg = <0x660000 0x400000>;
-			};
-
-			partition@a60000 {
-				label = "oops";
-				reg = <0xa60000 0xa0000>;
-			};
-
-			partition@b00000 {
-				label = "reserved3";
-				reg = <0xb00000 0x500000>;
-				read-only;
-			};
-
-			partition@1000000 {
-				label = "web";
-				reg = <0x1000000 0x800000>;
-			};
-
-			partition@1800000 {
-				label = "rootfs";
-				reg = <0x1800000 0x1d00000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x2800000>;
-
-			};
-			partition@7600000 {
-				label = "iot-db";
-				reg = <0x7600000 0xa00000>;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
-	qcom,ath10k-calibration-variant = "ZTE-MF18A";
-};
-
-//* This node is used for 5Ghz on QCA9982 */
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
-	clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "pci168c,0040";
-			nvmem-cell-names = "pre-calibration", "mac-address";
-			nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
-			qcom,ath10k-calibration-variant = "ZTE-MF18A";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf282plus.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf282plus.dts
deleted file mode 100644
index 54353cac58..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf282plus.dts
+++ /dev/null
@@ -1,454 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ZTE MF282Plus";
-	compatible = "zte,mf282plus";
-
-	aliases {
-		led-boot = &led_internal;
-		led-failsafe = &led_internal;
-		led-running = &led_internal;
-		led-upgrade = &led_internal;
-	};
-
-	chosen {
-		/*
-		 * bootargs forced by u-boot bootipq command:
-		 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
-		 */
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	gpio_export {
-		compatible = "gpio-export";
-		#size-cells = <0>;
-
-		modem {
-			gpio-export,name = "modem-reset";
-			gpio-export,output = <0>;
-			gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_internal: led-0 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			label = "blue:internal_led";
-			default-state = "keep";
-		};
-
-		led-1 {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wifi {
-			label = "wifi";
-			linux,code = <KEY_RFKILL>;
-			gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
-		};
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		/* u-boot is looking for "n25q128a11" property */
-		compatible = "jedec,spi-nor", "n25q128a11";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-				};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0xa0000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "ART";
-				reg = <0xa0000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@120000 {
-				label = "mac";
-				reg = <0x120000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_config_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1a0000 {
-				label = "reserved2";
-				reg = <0x1a0000 0xc0000>;
-				read-only;
-			};
-
-			partition@260000 {
-				label = "cfg-param";
-				reg = <0x260000 0x400000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "log";
-				reg = <0x660000 0x400000>;
-			};
-
-			partition@a60000 {
-				label = "oops";
-				reg = <0xa60000 0xa0000>;
-			};
-
-			partition@b00000 {
-				label = "reserved3";
-				reg = <0xb00000 0x500000>;
-				read-only;
-			};
-
-			partition@1000000 {
-				label = "web";
-				reg = <0x1000000 0x800000>;
-			};
-
-			partition@1800000 {
-				label = "rootfs";
-				reg = <0x1800000 0x1d00000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x2800000>;
-			};
-
-			partition@7600000 {
-				label = "extra-cfg";
-				reg = <0x7600000 0xa00000>;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 1>;
-	qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 1>;
-	qcom,ath10k-calibration-variant = "zte,mf286d";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf286d.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf286d.dts
deleted file mode 100644
index 61cbdba0d1..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf286d.dts
+++ /dev/null
@@ -1,453 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ZTE MF286D";
-	compatible = "zte,mf286d";
-
-	aliases {
-		led-boot = &led_internal;
-		led-failsafe = &led_internal;
-		led-running = &led_internal;
-		led-upgrade = &led_internal;
-	};
-
-	chosen {
-		/*
-		 * bootargs forced by u-boot bootipq command:
-		 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
-		 */
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	gpio-restart {
-		compatible = "gpio-restart";
-		gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_internal: led-0 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			label = "blue:internal_led";
-			default-state = "keep";
-		};
-
-		led-1 {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wifi {
-			label = "wifi";
-			linux,code = <KEY_RFKILL>;
-			gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
-		};
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		/* u-boot is looking for "n25q128a11" property */
-		compatible = "jedec,spi-nor", "n25q128a11";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-				};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0xa0000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "ART";
-				reg = <0xa0000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@120000 {
-				label = "mac";
-				reg = <0x120000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_config_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1a0000 {
-				label = "reserved2";
-				reg = <0x1a0000 0xc0000>;
-				read-only;
-			};
-
-			partition@260000 {
-				label = "cfg-param";
-				reg = <0x260000 0x400000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "log";
-				reg = <0x660000 0x400000>;
-			};
-
-			partition@a60000 {
-				label = "oops";
-				reg = <0xa60000 0xa0000>;
-			};
-
-			partition@b00000 {
-				label = "reserved3";
-				reg = <0xb00000 0x500000>;
-				read-only;
-			};
-
-			partition@1000000 {
-				label = "web";
-				reg = <0x1000000 0x800000>;
-			};
-
-			partition@1800000 {
-				label = "rootfs";
-				reg = <0x1800000 0x1d00000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x3200000>;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport5 {
-	status = "okay";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =	"gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins =	"gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
-	qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 3>;
-	qcom,ath10k-calibration-variant = "zte,mf286d";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts
deleted file mode 100644
index 7c0194ccc0..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mf289f.dts
+++ /dev/null
@@ -1,443 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ZTE MF289F";
-	compatible = "zte,mf289f";
-
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-	};
-
-	chosen {
-		/*
-		 * bootargs forced by u-boot bootipq command:
-		 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
-		 */
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	/*
-	 * This node is used to restart modem module to avoid anomalous
-	 * behaviours on initial communication.
-	 */
-	gpio-restart {
-		compatible = "gpio-restart";
-		gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status: led-0 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-		};
-
-		led-1 {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		key-reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-
-		key-wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <2000>;
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
-		   <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0xc0000>;
-				read-only;
-			};
-
-			partition@1b0000 {
-				label = "0:reserved1";
-				reg = <0x1b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-
-	spi-nand@1 { /* flash@1 ? */
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "fota-flag";
-				reg = <0x0 0xa0000>;
-				read-only;
-			};
-
-			partition@a0000 {
-				label = "ART";
-				reg = <0xa0000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@120000 {
-				label = "mac";
-				reg = <0x120000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mac_0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1a0000 {
-				label = "reserved2";
-				reg = <0x1a0000 0xc0000>;
-				read-only;
-			};
-
-			partition@260000 {
-				label = "cfg-param";
-				reg = <0x260000 0x400000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "log";
-				reg = <0x660000 0x400000>;
-			};
-
-			partition@a60000 {
-				label = "oops";
-				reg = <0xa60000 0xa0000>;
-			};
-
-			partition@b00000 {
-				label = "reserved3";
-				reg = <0xb00000 0x500000>;
-				read-only;
-			};
-
-			partition@1000000 {
-				label = "web";
-				reg = <0x1000000 0x800000>;
-			};
-
-			partition@1800000 {
-				label = "rootfs";
-				reg = <0x1800000 0x1d00000>;
-			};
-
-			partition@3500000 {
-				label = "data";
-				reg = <0x3500000 0x1900000>;
-			};
-
-			partition@4e00000 {
-				label = "fota";
-				reg = <0x4e00000 0x3200000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_mac_0 0>;
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "wan";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_mac_0 1>;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12", "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 2>;
-	qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT2 version for 5Ghz on IPQ4019 with board-id=21 */
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 3>;
-	qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT1 version for 5Ghz on QCA9984 */
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
-	clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			nvmem-cell-names = "mac-address";
-			nvmem-cells = <&macaddr_mac_0 4>;
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "zte,mf289f";
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts
deleted file mode 100644
index ab9a05c788..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
-	model = "Linksys MR8300 (Dallas)";
-	compatible = "linksys,mr8300", "qcom,ipq4019";
-
-	aliases {
-		led-boot = &led_blue;
-		led-failsafe = &led_red;
-		led-running = &led_blue;
-		led-upgrade = &led_amber;
-		serial0 = &blsp1_uart1;
-	};
-
-	// Top panel LEDs, above Linksys logo
-	leds {
-		compatible = "gpio-leds";
-
-		led_red: red {
-			function = LED_FUNCTION_ALARM;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_amber: amber {
-			function = LED_FUNCTION_PROGRAMMING;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_blue: blue {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-		};
-
-		// On back panel, above USB socket
-
-		led_usb: usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			trigger-sources = <&usb3_port1>, <&usb3_port2>,
-					  <&usb2_port1>;
-			linux,default-trigger = "usbport";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi1 {
-	status = "okay";
-	ieee80211-freq-limit = <5170000 5330000>;
-	qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi2 {
-	status = "okay";
-	ieee80211-freq-limit = <5490000 5835000>;
-	qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts
deleted file mode 100644
index ea27defea3..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-ncp-hg100-cellular.dts
+++ /dev/null
@@ -1,635 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Sony NCP-HG100/Cellular";
-	compatible = "sony,ncp-hg100-cellular";
-
-	aliases {
-		led-boot = &led_cloud_green;
-		led-failsafe = &led_cloud_red;
-		led-running = &led_cloud_green;
-		led-upgrade = &led_cloud_green;
-		label-mac-device = &gmac;
-	};
-
-	chosen {
-		bootargs = "console=ttyMSM0,115200n8 root=/dev/mmcblk0p15 rootfstype=squashfs,ext4";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>;
-	};
-
-	soc {
-		tcsr@1949000 {
-			status = "okay";
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			status = "okay";
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			status = "okay";
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		dma@7984000 {
-			status = "okay";
-		};
-	};
-
-	keys-repeat {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&keys_pins>;
-		pinctrl-names = "default";
-		autorepeat;
-
-		key-volup {
-			label = "volume up";
-			linux,code = <KEY_VOLUMEUP>;
-			gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
-			linux,input-type = <EV_KEY>;
-		};
-
-		key-voldown {
-			label = "volume down";
-			linux,code = <KEY_VOLUMEDOWN>;
-			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-			linux,input-type = <EV_KEY>;
-		};
-
-		key-alexatrigger {
-			label = "alexa trigger";
-			linux,code = <BTN_0>;
-			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-			linux,input-type = <EV_KEY>;
-		};
-
-		key-mute {
-			label = "mic mute";
-			linux,code = <BTN_1>;
-			gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_SW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		key-reset {
-			label = "reset";
-			gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		key-wps {
-			label = "setup";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-};
-
-&tlmm {
-	pinctrl-0 = <&bt_pins>, <&aud_pins>, <&mcu_pins>;
-	pinctrl-names = "default";
-
-	/*
-	 * uart0 is shared for debug console and Z-Wave,
-	 * use only for debug console in OpenWrt.
-	 *
-	 * 1: debug console
-	 * 0: Z-Wave
-	 */
-	uart0_ctrl_pins: uart0_ctrl_pinmux {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			output-high;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	/*
-	 * reset pin for Z-Wave
-	 * active-low, >= 20ns
-	 */
-	zwave_pins: zwave_pinmux {
-		mux {
-			pins = "gpio59";
-			function = "gpio";
-			output-high;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9",
-				"gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	bt_pins: bt_pinmux {
-		mux_reset {
-			pins = "gpio66";
-			function = "gpio";
-			output-high;
-		};
-
-		mux_pwr {
-			pins = "gpio68";
-			function = "gpio";
-			output-high;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	i2c_1_pins: i2c_1_pinmux {
-		mux {
-			pins = "gpio12", "gpio13";
-			function = "blsp_i2c1";
-			bias-disable;
-		};
-	};
-
-	keys_pins: keys_pinmux {
-		mux_1 {
-			pins = "gpio39", "gpio40", "gpio42", "gpio47";
-			function = "gpio";
-			bias-disable;
-		};
-
-		mux_2 {
-			pins = "gpio2";
-			function = "gpio";
-			input;
-		};
-	};
-
-	sd_pins: sd_pins {
-		mux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio28", "gpio29", "gpio30", "gpio31";
-			drive-strength = <4>;
-		};
-
-		mux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-
-		mux_sd7 {
-			function = "sdio";
-			pins = "gpio32";
-			drive-strength = <4>;
-			bias-disable;
-		};
-	};
-
-	aud_pins: aud_pinmux {
-		mux {
-			pins = "gpio48", "gpio49", "gpio50", "gpio51";
-			function = "aud_pin";
-		};
-	};
-
-	alc1304_pins: alc1304_pinmux {
-		mux_1 {
-			pins = "gpio44";
-			function = "gpio";
-			bias-disable;
-		};
-
-		mux_2 {
-			pins = "gpio45";
-			function = "gpio";
-			bias-disable;
-		};
-	};
-
-	cx2902x_reset: cx2902x_pinmux {
-		mux_1 {
-			pins = "gpio64";
-			function = "gpio";
-			bias-disable;
-		};
-
-		mux_2 {
-			pins = "gpio65";
-			function = "gpio";
-			bias-disable;
-		};
-	};
-
-	lte_pins: lte_pinmux {
-		mux_en {
-			pins = "gpio20";
-			function = "gpio";
-			output-high;
-		};
-
-		mux_reset {
-			pins = "gpio35";
-			function = "gpio";
-			input;
-		};
-	};
-
-	usb3_pins: usb3_pinmux {
-		mux_en {
-			pins = "gpio36";
-			function = "gpio";
-			output-high;
-		};
-
-		mux_flt {
-			pins = "gpio4";
-			function = "gpio";
-			input;
-		};
-	};
-
-	mcu_pins: mcu_pinmux {
-		mux_boot {
-			pins = "gpio38";
-			function = "gpio";
-			output-low;
-		};
-
-		mux_reset {
-			pins = "gpio5";
-			function = "gpio";
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_i2c4 {
-	/*
-	 * There is no driver for the following devices:
-	 * - CY8C4014LQI@14	: Touch-Sensor for buttons on top
-	 * - MINI54FDE@15	: MCU for Fan/RGB LED/Thermal control
-	 * - ALC5629@18		: I2S/PCM Audio DAC
-	 * - CX20924@41		: Voice Input Processor
-	 */
-	pinctrl-0 = <&i2c_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	led-controller@32 {
-		compatible = "ti,lp55231";
-		reg = <0x32>;
-		clock-mode = /bits/ 8 <0>;
-		enable-gpio = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led@0 {
-			chan-name = "green:wan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x0>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WAN;
-		};
-
-		led@1 {
-			chan-name = "blue:wan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x1>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WAN;
-		};
-
-		led@2 {
-			chan-name = "green:lan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x2>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_LAN;
-		};
-
-		led@3 {
-			chan-name = "blue:lan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x3>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-		};
-
-		led@4 {
-			chan-name = "green:wlan-2";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x4>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <2>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led@5 {
-			chan-name = "blue:wlan-2";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x5>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <2>;
-		};
-
-		led@6 {
-			chan-name = "red:wan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x6>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WAN;
-		};
-
-		led@7 {
-			chan-name = "red:lan";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x7>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_LAN;
-		};
-
-		led@8 {
-			chan-name = "red:wlan-2";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x8>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <2>;
-		};
-	};
-
-	led-controller@33 {
-		compatible = "ti,lp55231";
-		reg = <0x33>;
-		clock-mode = /bits/ 8 <0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led@0 {
-			chan-name = "green:wlan-5";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x0>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN;
-			linux,default-trigger = "phy1tpt";
-			function-enumerator = <5>;
-		};
-
-		led@1 {
-			chan-name = "blue:wlan-5";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x1>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <5>;
-		};
-
-		led@2 {
-			chan-name = "green:wan-4";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x2>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
-			function-enumerator = <4>; /* WWAN/LTE/4G */
-		};
-
-		led@3 {
-			chan-name = "blue:wan-4";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x3>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
-			function-enumerator = <4>; /* WWAN/LTE/4G */
-		};
-
-		led_cloud_green: led@4 {
-			chan-name = "green:power";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x4>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led@5 {
-			chan-name = "blue:power";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x5>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led@6 {
-			chan-name = "red:wlan-5";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x6>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <5>;
-		};
-
-		led@7 {
-			chan-name = "red:wan-4";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x7>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
-			function-enumerator = <4>; /* WWAN/LTE/4G */
-		};
-
-		led_cloud_red: led@8 {
-			chan-name = "red:power";
-			led-cur = /bits/ 8 <50>;
-			max-cur = /bits/ 8 <100>;
-			reg = <0x8>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_POWER;
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>, <&uart0_ctrl_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-};
-
-&prng {
-	status = "okay";
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	vqmmc-supply = <&vqmmc>;
-	non-removable;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	emmc@0 {
-		compatible = "mmc-card";
-		reg = <0>;
-	};
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-
-	pinctrl-0 = <&usb3_pins>, <&lte_pins>;
-	pinctrl-names = "default";
-
-	dwc3@8a00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		device@1 {
-			compatible = "usb1bc7,1900";
-			reg = <1>;
-		};
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-	label = "wan";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&watchdog {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-oap100.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-oap100.dts
deleted file mode 100644
index 2080a34e2f..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-oap100.dts
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "EdgeCore OAP-100";
-	compatible = "edgecore,oap100";
-
-	aliases {
-		led-boot = &led_system;
-		led-failsafe = &led_system;
-		led-running = &led_system;
-		led-upgrade = &led_system;
-	};
-
-	chosen {
-		bootargs-append = " root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	key {
-		compatible = "gpio-keys";
-
-		button@1 {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,input-type = <1>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_system: led_system {
-			label = "green:system";
-			gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_2g {
-			label = "blue:wlan2g";
-			gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_5g {
-			label = "blue:wlan5g";
-			gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	gpio_export {
-		compatible = "gpio-export";
-		#size-cells = <0>;
-
-		usb {
-			gpio-export,name = "usb-power";
-			gpio-export,output = <1>;
-			gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
-		};
-
-		poe {
-			gpio-export,name = "poe-power";
-			gpio-export,output = <0>;
-			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		linux,modalias = "m25p80", "gd25q256";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "0:APPSBL";
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition7@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "rootfs";
-				reg = <0x00000000 0x4000000>;
-			};
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi
deleted file mode 100644
index 849df64201..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	aliases {
-		led-boot = &led_status_white;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_blue;
-		label-mac-device = &gmac;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led-0 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led-1 {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_status_green: led-2 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_red: led-3 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_blue: led-4 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_white: led-5 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		pinmux {
-			function = "blsp_i2c0";
-			pins = "gpio58", "gpio59";
-			bias-disable;
-		};
-	};
-
-	sd_pins: sd_pins {
-		pinmux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio28", "gpio29", "gpio30", "gpio31";
-			drive-strength = <10>;
-		};
-
-		pinmux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-
-		pinmux_sd7 {
-			function = "sdio";
-			pins = "gpio32";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	led-controller@27 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "ti,tlc59108"; /* really is tlc59208f */
-		reg = <0x27>;
-
-		led0@0 {
-			label = "rgb:led0";
-			reg = <0x0>;
-			linux,default-trigger = "default-on";
-		};
-
-		led1@1 {
-			label = "rgb:led1";
-			reg = <0x1>;
-			linux,default-trigger = "default-on";
-		};
-
-		led2@2 {
-			label = "rgb:led2";
-			reg = <0x2>;
-			linux,default-trigger = "default-on";
-		};
-
-		led3@3 {
-			label = "rgb:led3";
-			reg = <0x3>;
-			linux,default-trigger = "default-on";
-		};
-
-		led4@4 {
-			label = "rgb:led4";
-			reg = <0x4>;
-			linux,default-trigger = "default-on";
-		};
-
-		led5@5 {
-			label = "rgb:led5";
-			reg = <0x5>;
-			linux,default-trigger = "default-on";
-		};
-
-		led6@6 {
-			label = "rgb:led6";
-			reg = <0x6>;
-			linux,default-trigger = "default-on";
-		};
-
-		led7@7 {
-			label = "rgb:led7";
-			reg = <0x7>;
-			linux,default-trigger = "default-on";
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-
-	label = "wan";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&ethphy4 {
-	status = "disabled";
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			ieee80211-freq-limit = <5470000 5875000>;
-			qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
-
-&wifi1 {
-	status = "okay";
-
-	qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts
deleted file mode 100644
index ed333c4990..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Plasma Cloud PA2200";
-	compatible = "plasmacloud,pa2200";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART >;
-		};
-	};
-
-	aliases {
-		led-boot = &led_power_orange;
-		led-failsafe = &led_status_blue;
-		led-running = &led_power_orange;
-		led-upgrade = &led_status_blue;
-		label-mac-device = &swport4;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power_orange: power_orange {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-		};
-
-		2g_blue {
-			label = "blue:2g";
-			gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		2g_green {
-			label = "green:5g1";
-			gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		5g2_green {
-			label = "green:5g2";
-			gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy2tpt";
-		};
-
-		led_status_blue: status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		/* partitions are passed via bootloader */
-		partitions {
-			partition-art {
-				label = "0:ART";
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
-			ieee80211-freq-limit = <5170000 5350000>;
-
-			nvmem-cell-names = "pre-calibration";
-			nvmem-cells = <&precal_art_9000>;
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "ethernet1";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
-	status = "okay";
-	label = "ethernet2";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
-	ieee80211-freq-limit = <5470000 5875000>;
-
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-128m.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-128m.dts
deleted file mode 100644
index 0896374ab2..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-128m.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
-	model = "P&W R619AC 128M";
-	compatible = "p2w,r619ac-128m";
-};
-
-&nand_rootfs {
-	/*
-	 * Watch out: stock MIBIB is set up for a 64MiB chip.
-	 * If a 128MiB flash chip is used, make sure to have
-	 * the right values in MIBIB or the device might not
-	 * boot.
-	 */
-	reg = <0x0 0x8000000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-64m.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-64m.dts
deleted file mode 100644
index 6c8821a90e..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac-64m.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
-	model = "P&W R619AC 64M";
-	compatible = "p2w,r619ac-64m";
-};
-
-&nand_rootfs {
-	reg = <0x0 0x4000000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
deleted file mode 100644
index 90e5455b25..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi
+++ /dev/null
@@ -1,387 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	chosen {
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	aliases {
-		led-boot = &led_sys;
-		led-failsafe = &led_sys;
-		led-running = &led_sys;
-		led-upgrade = &led_sys;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_sys: led-0 {
-			gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led-1 {
-			gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <0>;
-		};
-
-		led-2 {
-			gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <1>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			nand_rootfs: partition@0 {
-				label = "ubi";
-				/* reg defined in 64M/128M variant dts. */
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-
-	/* Free slot for use */
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&sdhci {
-	pinctrl-0 = <&sd_0_pins>;
-	pinctrl-names = "default";
-	vqmmc-supply = <&vqmmc>;
-	status = "okay";
-};
-
-&tlmm {
-	pcie_pins: pcie_pinmux {
-		mux {
-			pins = "gpio2";
-			function = "gpio";
-			output-low;
-			bias-pull-down;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	sd_0_pins: sd_0_pinmux {
-		mux_1 {
-			pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
-			function = "sdio";
-			drive-strength = <10>;
-		};
-
-		mux_2 {
-			pins = "gpio27";
-			function = "sdio";
-			drive-strength = <16>;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-};
-
-&ethphy0 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy1 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy2 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy3 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&ethphy4 {
-	qcom,single-led-1000;
-	qcom,single-led-100;
-	qcom,single-led-10;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-
-	label = "lan4";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr40.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr40.dts
deleted file mode 100644
index 26e87b808c..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr40.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR RBR40";
-	compatible = "netgear,rbr40";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr50.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr50.dts
deleted file mode 100644
index a803999804..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbr50.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR RBR50";
-	compatible = "netgear,rbr50";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-
-	soc {
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs40.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs40.dts
deleted file mode 100644
index 2dfa0c9654..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs40.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR RBS40";
-	compatible = "netgear,rbs40";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs50.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs50.dts
deleted file mode 100644
index 4d0a9132c6..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rbs50.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR RBS50";
-	compatible = "netgear,rbs50";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-
-	soc {
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-	};
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts
deleted file mode 100644
index 70849d71d6..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts
+++ /dev/null
@@ -1,324 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "ASUS RT-AC42U";
-	compatible = "asus,rt-ac42u";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256MB */
-	};
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: led-0 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_STATUS;
-			gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
-		};
-
-		led-1 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WAN;
-			gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "90000.mdio-1:04:link";
-		};
-
-		led-2 {
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WAN;
-			gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "none";
-		};
-
-		led-3 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <0>;
-			gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led-4 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_WLAN;
-			function-enumerator = <1>;
-			gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led-5 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-			function-enumerator = <1>;
-			gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
-		};
-
-		led-6 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-			function-enumerator = <2>;
-			gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-		};
-
-		led-7 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-			function-enumerator = <3>;
-			gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
-		};
-
-		led-8 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_LAN;
-			function-enumerator = <4>;
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	serial_0_pins: serial0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio55", "gpio56", "gpio57", "gpio60",
-				"gpio62", "gpio63", "gpio64", "gpio65",
-				"gpio66", "gpio67", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00080000>;
-				read-only;
-			};
-			partition@80000 {
-				label = "MIBIB";
-				reg = <0x00080000 0x00080000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "QSEE";
-				reg = <0x00100000 0x00100000>;
-				read-only;
-			};
-			partition@200000 {
-				label = "CDT";
-				reg = <0x00200000 0x00080000>;
-				read-only;
-			};
-			partition@280000 {
-				label = "APPSBL";
-				reg = <0x00280000 0x00140000>;
-				read-only;
-			};
-			partition@3C0000 {
-				label = "APPSBLENV";
-				reg = <0x003C0000 0x00040000>;
-				read-only;
-			};
-			partition@400000 {
-				label = "ubi";
-				reg = <0x00400000 0x07C00000>;
-			};
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-	clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-
-			qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts
deleted file mode 100644
index e2df1d1997..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts
+++ /dev/null
@@ -1,397 +0,0 @@
-// SPDX-License-Identifier: ISC
-// Copyright (c) 2015, The Linux Foundation. All rights reserved.
-// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
-// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Cell C RTL30VW";
-	compatible = "cellc,rtl30vw";
-
-	aliases {
-		led-boot = &led_power_blue;
-		led-failsafe = &led_power_red;
-		led-running = &led_power_blue;
-		led-upgrade = &led_power_red;
-	};
-
-	chosen {
-		bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
-	};
-
-	led_spi {
-		compatible = "spi-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		num-chipselects = <1>;
-
-		mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-		cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
-		sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-
-		led_gpio: led_gpio@0 {
-			compatible = "fairchild,74hc595";
-			reg = <0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			registers-number = <2>;
-			spi-max-frequency = <1000000>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power_blue: power_blue {
-			gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			default-state = "on";
-		};
-
-		led_power_red: power_red {
-			gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-		};
-
-		tp28 {
-			gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
-			label = "ext:tp28";
-			default-state = "keep";
-		};
-
-		tp27 {
-			gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
-			label = "ext:tp27";
-			default-state = "keep";
-		};
-
-		wlan2g {
-			gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
-			label = "blue:wlan2g";
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
-			label = "blue:wlan5g";
-			linux,default-trigger = "phy1tpt";
-		};
-
-		wps {
-			gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_BLUE>;
-		};
-
-		voip {
-			gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
-			label = "blue:voip";
-		};
-
-		s1 {
-			gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
-			label = "blue:s1";
-		};
-
-		s2 {
-			gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
-			label = "blue:s2";
-		};
-
-		s3 {
-			gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
-			label = "blue:s3";
-		};
-
-		s4 {
-			gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
-			label = "blue:s4";
-		};
-
-		signal {
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-			label = "red:signal";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-		};
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		/*"n25q128a11" is required for proper nand recognition in u-boot. */
-		compatible = "jedec,spi-nor", "n25q128a11";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-				};
-
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x180000 0x10000>;
-				read-only;
-			};
-		};
-	};
-
-	flash@1 {
-		/*
-		 * Factory U-boot looks in 0:BOOTCONFIG partition for active
-		 * partitions settings and mangle partition config. So kernel
-		 * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
-		 * It isn't a problem but we never can be sure where OFW put
-		 * factory images. "spinand,mt29f" value is required for proper
-		 * nand recognition in u-boot.
-		 */
-		compatible = "spi-nand","spinand,mt29f";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "kernel";
-				reg = <0x0 0x400000>;
-			};
-
-			partition@400000 {
-				label = "rootfs";
-				reg = <0x400000 0x2000000>;
-			};
-
-			partition@2400000 {
-				label = "kernel_1";
-				reg = <0x2400000 0x400000>;
-			};
-
-			partition@2800000 {
-				label = "rootfs_1";
-				reg = <0x2800000 0x2000000>;
-			};
-
-			partition@4800000 {
-				label = "ubifs";
-				reg = <0x4800000 0x3800000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan2";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srr60.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srr60.dts
deleted file mode 100644
index 80bcb2e204..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srr60.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR SRR60";
-	compatible = "netgear,srr60";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srs60.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srs60.dts
deleted file mode 100644
index 65bb7ac397..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-srs60.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
-	model = "NETGEAR SRS60";
-	compatible = "netgear,srs60";
-
-	chosen {
-		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts
deleted file mode 100644
index 08c55d0c27..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-u4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Unielec U4019 (32M)";
-	compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-		broken-flash-reset;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-			partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0x1e80000>;
-			};
-		};
-	};
-};
-
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi
deleted file mode 100644
index c7439b87ec..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi
+++ /dev/null
@@ -1,216 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	compatible = "unielec,u4019","qcom,ipq4019";
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		aliases {
-			led-boot = &led_status;
-			led-failsafe = &led_status;
-			led-running = &led_status;
-			led-upgrade = &led_status;
-			serial0 = &blsp1_uart1;
-			serial1 = &blsp1_uart2;
-		};
-
-		leds {
-			compatible = "gpio-leds";
-			pinctrl-0 = <&led_pins>;
-			pinctrl-names = "default";
-
-			led_status: led2 {
-				label = "green:led2";
-				gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-			};
-		};
-
-		keys {
-			compatible = "gpio-keys";
-
-			reset {
-				label = "reset";
-				gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-				linux,code = <KEY_RESTART>;
-			};
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	led_pins: led_pinmux {
-		mux {
-			function = "gpio";
-			pins = "gpio68";
-			bias-disabled;
-			output-low;
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts
deleted file mode 100644
index b76c52cd0a..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-whw03v2.dts
+++ /dev/null
@@ -1,514 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Linksys WHW03 V2 (Velop)";
-	compatible = "linksys,whw03v2", "qcom,ipq4019";
-
-	aliases {
-		led-boot = &led_blue;
-		led-failsafe = &led_red;
-		led-running = &led_blue;
-		led-upgrade = &led_red;
-	};
-
-	// The arguments rootfstype and ro are needed
-	// to override the default bootargs
-	chosen {
-		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
-		stdout-path = &blsp1_uart1;
-	};
-
-	soc {
-		ess-tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-
-&tlmm {
-	mdio_pins: mdio-pinmux {
-		mux-1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux-2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	i2c_0_pins: i2c-0-pinmux {
-		mux {
-			function = "blsp_i2c0";
-			pins = "gpio20", "gpio21";
-			bias-disable;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1-pinmux {
-		mux {
-			pins = "gpio8", "gpio9", "gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi-0-pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux-cs {
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	spi_1_pins: spi-1-pinmux {
-		mux-1 {
-			function = "blsp_spi1";
-			pins = "gpio44", "gpio46","gpio47";
-			bias-disable;
-		};
-
-		mux-2 {
-			pins = "gpio31", "gpio45", "gpio49";
-			function = "gpio";
-			bias-pull-up;
-			output-high;
-		};
-
-		host-interrupt {
-			pins = "gpio42";
-			function = "gpio";
-			input;
-		};
-	};
-
-	wifi_0_pins: wifi0-pinmux {
-		btcoexist {
-			bias-pull-up;
-			drive-strength = <6>;
-			function = "gpio";
-			output-high;
-			pins = "gpio52";
-		};
-	};
-
-	zigbee-0 {
-		gpio-hog;
-		gpios = <29 GPIO_ACTIVE_HIGH>;
-		bias-disable;
-		output-low;
-	};
-
-	zigbee-1 {
-		gpio-hog;
-		gpios = <50 GPIO_ACTIVE_HIGH>;
-		bias-disable;
-		input;
-	};
-
-	bluetooth-enable {
-		gpio-hog;
-		gpios = <32 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	reg = <0x1b>;
-};
-
-&ethphy4 {
-	reg = <0x1c>;
-};
-
-&psgmiiphy {
-	reg = <0x1d>;
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	num-channels = <4>;
-	qcom,num-ees = <2>;
-
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
-	status = "okay";
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-
-	bluetooth {
-		compatible = "csr,8811";
-
-		enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&blsp1_spi2 {
-	pinctrl-0 = <&spi_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
-	zigbee@0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "silabs,em3581";
-		reg = <0>;
-		spi-max-frequency = <12000000>;
-	};
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	// RGB LEDs
-	pca9633: led-controller@62 {
-		compatible = "nxp,pca9633";
-		nxp,hw-blink;
-		reg = <0x62>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led_red: red@0 {
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <0>;
-		};
-
-		led_green: green@1 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <1>;
-		};
-
-		led_blue: blue@2 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <2>;
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x100000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "MIBIB";
-				reg = <0x100000 0x100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "QSEE";
-				reg = <0x200000 0x100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "CDT";
-				reg = <0x300000 0x80000>;
-				read-only;
-			};
-
-			partition@380000 {
-				label = "APPSBL";
-				reg = <0x380000 0x200000>;
-				read-only;
-			};
-
-			partition@580000 {
-				label = "ART";
-				reg = <0x580000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x9000 0x2f20>;
-					};
-				};
-			};
-
-			partition@600000 {
-				label = "u_env";
-				reg = <0x600000 0x80000>;
-			};
-
-			partition@680000 {
-				label = "s_env";
-				reg = <0x680000 0x40000>;
-			};
-
-			partition@6c0000 {
-				label = "devinfo";
-				reg = <0x6c0000 0x40000>;
-				read-only;
-			};
-
-			partition@700000 {
-				label = "kernel";
-				reg = <0x700000 0xa100000>;
-			};
-
-			partition@d00000 {
-				label = "rootfs";
-				reg = <0xd00000 0x9b00000>;
-			};
-
-			partition@a800000 {
-				label = "alt_kernel";
-				reg = <0xa800000 0xa100000>;
-			};
-
-			partition@ae00000 {
-				label = "alt_rootfs";
-				reg = <0xae00000 0x9b00000>;
-			};
-
-			partition@14900000 {
-				label = "sysdiag";
-				reg = <0x14900000 0x200000>;
-				read-only;
-			};
-
-			partition@14b00000 {
-				label = "syscfg";
-				reg = <0x14b00000 0xb500000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
-	clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
-	status = "okay";
-	label = "wan";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&wifi0 {
-	pinctrl-0 = <&wifi_0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	qcom,coexist-support = <1>;
-	qcom,coexist-gpio-pin = <0x34>;
-
-	qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_gmac0 1>;
-};
-
-&wifi1 {
-	status = "okay";
-
-	ieee80211-freq-limit = <5170000 5330000>;
-	qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_gmac0 2>;
-};
-
-&wifi2 {
-	status = "okay";
-
-	ieee80211-freq-limit = <5490000 5835000>;
-	qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_9000>, <&macaddr_gmac0 3>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wifi.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wifi.dts
deleted file mode 100644
index f2e39c87ae..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wifi.dts
+++ /dev/null
@@ -1,451 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2016, 2018 The Linux Foundation. All rights reserved.
- * Copyright (c) 2016 Google, Inc
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Google WiFi (Gale)";
-	compatible = "google,wifi", "google,gale-v2", "qcom,ipq4019";
-
-	aliases {
-		label-mac-device = &gmac0;
-		led-boot = &led0_blue;
-		led-failsafe = &led0_red;
-		led-running = &led0_blue;
-		led-upgrade = &led0_red;
-	};
-
-	chosen {
-		/*
-		 * rootwait: in case we're booting from slow/async USB storage.
-		 */
-		bootargs-append = " rootwait";
-		stdout-path = &blsp1_uart1;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>; /* 512MB */
-	};
-
-	soc {
-		edma@c080000 {
-			/*
-			 * Factory bootloader (depthcharge) will fail to boot
-			 * if this exact path (soc/edma@c080000/gmac0) doesn't
-			 * exist.
-			 */
-			gmac0: gmac0 {
-			};
-
-			/*
-			 * Factory bootloader (depthcharge) will fail to boot
-			 * if this exact path (soc/edma@c080000/gmac1) doesn't
-			 * exist.
-			 */
-			gmac1 {
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&fw_pinmux>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&scm {
-	qcom,sdi-enabled;
-};
-
-&tlmm {
-	fw_pinmux: fw_pinmux {
-		wp {
-			pins = "gpio53";
-			output-low;
-		};
-		recovery {
-			pins = "gpio57";
-			function = "gpio";
-			bias-none;
-		};
-		developer {
-			pins = "gpio41";
-			bias-none;
-		};
-	};
-
-	reset802_15_4 {
-		pins = "gpio60";
-	};
-
-	led_reset {
-		pins = "gpio22";
-		output-high;
-	};
-
-	sys_reset {
-		pins = "gpio19";
-		output-high;
-	};
-
-	rx_active {
-		pins = "gpio43";
-		bias-pull,down;
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14","gpio15";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-		};
-		pinconf {
-			pins = "gpio13", "gpio14","gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	spi_1_pins: spi_1_pinmux {
-		pinmux {
-			function = "blsp_spi1";
-			pins = "gpio44", "gpio46","gpio47";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio45";
-		};
-		pinconf {
-			pins = "gpio44", "gpio46","gpio47";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio45";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	serial_0_pins: serial0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9", "gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			drive-open-drain;
-		};
-	};
-
-	i2c_1_pins: i2c_1_pinmux {
-		mux {
-			pins = "gpio34", "gpio35";
-			function = "blsp_i2c1";
-			drive-open-drain;
-		};
-	};
-
-	sd_0_pins: sd_0_pinmux {
-		sd0 {
-			pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32";
-			function = "sdio";
-			drive-strength = <10>;
-			bias-pull-up;
-			pull-up-res = <0>;
-		};
-		sdclk {
-			pins = "gpio27";
-			function = "sdio";
-			drive-strength = <2>;
-			bias-pull-up;
-			pull-up-res = <0>;
-		};
-		sdcmd {
-			pins = "gpio28";
-			function = "sdio";
-			drive-strength = <10>;
-			bias-pull-up;
-			pull-up-res = <0>;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-disable;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-disable;
-		};
-		mux_3 {
-			pins = "gpio40";
-			function = "gpio";
-			bias-disable;
-			output-high;
-		};
-	};
-
-	wifi1_1_pins: wifi2_pinmux {
-		mux {
-			pins = "gpio58";
-			output-low;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	tpm@20 {
-		compatible = "infineon,slb9645tt";
-		reg = <0x20>;
-		powered-while-suspended;
-	};
-};
-
-&blsp1_i2c4 {
-	pinctrl-0 = <&i2c_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	led-controller@32 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "national,lp5523";
-		reg = <0x32>;
-		clock-mode = /bits/ 8 <1>;
-
-#if 1
-		led0_red: led@0 {
-			reg = <0>;
-			chan-name = "LED0_Red";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_FAULT;
-		};
-
-		led@1 {
-			reg = <1>;
-			chan-name = "LED0_Green";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-			color = <LED_COLOR_ID_GREEN>;
-		};
-
-		led0_blue: led@2 {
-			reg = <2>;
-			chan-name = "LED0_Blue";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_POWER;
-		};
-#else
-		/*
-		 * openwrt isn't ready to handle multi-intensity leds yet
-		 * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
-		 * # echo 255 > /sys/class/leds/tricolor/brightness
-		 */
-		multi-led@2 {
-			function = LED_FUNCTION_POWER;
-			reg = <2>;
-			color = <LED_COLOR_ID_RGB>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			led@0 {
-				reg = <0>;
-				chan-name = "tricolor";
-				led-cur = /bits/ 8 <0x64>;
-				max-cur = /bits/ 8 <0x78>;
-				color = <LED_COLOR_ID_RED>;
-			};
-
-			led@1 {
-				reg = <1>;
-				chan-name = "tricolor";
-				led-cur = /bits/ 8 <0x64>;
-				max-cur = /bits/ 8 <0x78>;
-				color = <LED_COLOR_ID_GREEN>;
-			};
-
-			led@2 {
-				reg = <2>;
-				chan-name = "tricolor";
-				led-cur = /bits/ 8 <0x64>;
-				max-cur = /bits/ 8 <0x78>;
-				color = <LED_COLOR_ID_BLUE>;
-			};
-		};
-#endif
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-	};
-};
-
-&blsp1_spi2 {
-	pinctrl-0 = <&spi_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
-	/*
-	 * This "spidev" was included in the manufacturer device tree. I
-	 * suspect it's the (unused; and removed from later HW spins) Zigbee
-	 * radio -- SiliconLabs EM3581 Zigbee? There's no driver or binding for
-	 * this at the moment.
-	 */
-	spidev@0 {
-		compatible = "spidev";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-};
-
-&prng {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-	pinctrl-0 = <&sd_0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <192000000>;
-	vqmmc-supply = <&vqmmc>;
-	non-removable;
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "GO_GALE";
-};
-
-&wifi1 {
-	status = "okay";
-	pinctrl-0 = <&wifi1_1_pins>;
-	pinctrl-names = "default";
-	qcom,ath10k-calibration-variant = "GO_GALE";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts
deleted file mode 100644
index 2dc4544433..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts
+++ /dev/null
@@ -1,373 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Compex WPJ419";
-	compatible = "compex,wpj419", "qcom,ipq4019";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	reserved-memory {
-		ranges;
-		rsvd1@87000000 {
-			/* Reserved for other subsystem */
-			reg = <0x87000000 0x500000>;
-			no-map;
-		};
-		wifi_dump@87500000 {
-			reg = <0x87500000 0x600000>;
-			no-map;
-		};
-
-		rsvd2@87B00000 {
-			/* Reserved for other subsystem */
-			reg = <0x87B00000 0x500000>;
-			no-map;
-		};
-	};
-
-	chosen {
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		pinctrl@1000000 {
-			mdio_pins: mdio_pinmux {
-				mux_1 {
-					pins = "gpio6";
-					function = "mdio";
-					bias-pull-up;
-				};
-
-				mux_2 {
-					pins = "gpio7";
-					function = "mdc";
-					bias-pull-up;
-				};
-			};
-
-			serial_0_pins: serial_pinmux {
-				mux {
-					pins = "gpio16", "gpio17";
-					function = "blsp_uart0";
-					bias-disable;
-				};
-			};
-
-			serial_1_pins: serial1_pinmux {
-				mux {
-					pins = "gpio8", "gpio9", "gpio10", "gpio11";
-					function = "blsp_uart1";
-					bias-disable;
-				};
-			};
-
-			spi_0_pins: spi_0_pinmux {
-				pinmux {
-					function = "blsp_spi0";
-					pins = "gpio13", "gpio14", "gpio15";
-					bias-disable;
-				};
-
-				pinmux_cs {
-					function = "gpio";
-					pins = "gpio12";
-					bias-disable;
-					output-high;
-				};
-			};
-
-			i2c_0_pins: i2c_0_pinmux {
-				mux {
-					pins = "gpio20", "gpio21";
-					function = "blsp_i2c0";
-					bias-disable;
-				};
-			};
-
-			nand_pins: nand_pins {
-				pullups {
-					pins = "gpio52", "gpio53", "gpio58", "gpio59";
-					function = "qpic";
-					bias-pull-up;
-				};
-
-				pulldowns {
-					pins = "gpio54", "gpio55", "gpio56",
-					"gpio57", "gpio60", "gpio61",
-					"gpio62", "gpio63", "gpio64",
-					"gpio65", "gpio66", "gpio67",
-					"gpio68", "gpio69";
-					function = "qpic";
-					bias-pull-down;
-				};
-			};
-
-			led_0_pins: led0_pinmux {
-				mux_1 {
-					pins = "gpio36";
-					function = "led0";
-					bias-pull-down;
-				};
-				mux_2 {
-					pins = "gpio40";
-					function = "led4";
-					bias-pull-down;
-				};
-			};
-		};
-
-		blsp_dma: dma@7884000 {
-			status = "okay";
-		};
-
-		spi_0: spi@78b5000 {
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-			cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
-			num-cs = <2>;
-
-			flash0@0 {
-				reg = <0>;
-				compatible = "jedec,spi-nor";
-				spi-max-frequency = <24000000>;
-				broken-flash-reset;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "0:SBL1";
-						reg = <0x000000 0x040000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "0:MIBIB";
-						reg = <0x040000 0x020000>;
-						read-only;
-					};
-
-					partition@60000 {
-						label = "0:QSEE";
-						reg = <0x060000 0x060000>;
-						read-only;
-					};
-
-					partition@c0000 {
-						label = "0:CDT";
-						reg = <0x0c0000 0x010000>;
-						read-only;
-					};
-
-					partition@d0000 {
-						label = "0:DDRPARAMS";
-						reg = <0x0d0000 0x010000>;
-						read-only;
-					};
-
-					partition@e0000 {
-						label = "u-boot-env";
-						reg = <0x0e0000 0x010000>;
-					};
-
-					partition@f0000 {
-						label = "u-boot";
-						reg = <0x0f0000 0x080000>;
-						read-only;
-					};
-
-					partition@170000 {
-						label = "0:ART";
-						reg = <0x170000 0x010000>;
-						read-only;
-
-						nvmem-layout {
-							compatible = "fixed-layout";
-							#address-cells = <1>;
-							#size-cells = <1>;
-
-							precal_art_1000: precal@1000 {
-								reg = <0x1000 0x2f20>;
-							};
-
-							precal_art_5000: precal@5000 {
-								reg = <0x5000 0x2f20>;
-							};
-						};
-					};
-				};
-			};
-
-			nand@1 {
-				reg = <1>;
-				status = "okay";
-				compatible = "spi-nand";
-				spi-max-frequency = <24000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					/* The device has 128MB, but we can only address
-					 * 64MB because of the bootloader's default settings.
-					 * This is due to the old mt29f driver,
-					 * which detected the deivce with only 64MB
-					 */
-					partition@0 {
-						label = "ubi";
-						reg = <0x0000000 0x4000000>;
-					};
-				};
-			};
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <5000>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		serial@78af000 {
-			pinctrl-0 = <&serial_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		usb3_ss_phy: ssphy@9a000 {
-			status = "okay";
-		};
-
-		usb3_hs_phy: hsphy@a6000 {
-			status = "okay";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "okay";
-		};
-
-		usb2_hs_phy: hsphy@a8000 {
-			status = "okay";
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		cryptobam: dma@8e04000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		qpic_bam: dma@7984000 {
-			status = "okay";
-		};
-
-		pcie0: pci@40000000 {
-			status = "okay";
-			perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-			wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts
deleted file mode 100644
index 00b5897b7d..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts
+++ /dev/null
@@ -1,472 +0,0 @@
-// SPDX-License-Identifier: ISC
-/*
- * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
- * Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Buffalo WTR-M2133HP";
-	compatible = "buffalo,wtr-m2133hp", "qcom,ipq4019";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>;
-	};
-
-	chosen {
-		/*
-		 * U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs" to
-		 * kernel command line. But we use different partition names,
-		 * so we have to set correct parameters.
-		 */
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	aliases {
-		led-boot = &led_power_blue;
-		led-failsafe = &led_power_orange;
-		led-running = &led_power_white;
-		led-upgrade = &led_power_blue;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power_white: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_power_orange: power_orange {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_power_blue: power_blue {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
-		};
-
-		router_white {
-			label = "white:router";
-			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-		};
-
-		router_orange {
-			label = "orange:router";
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-		};
-
-		internet_white {
-			label = "white:internet";
-			gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
-		};
-
-		internet_orange {
-			label = "orange:internet";
-			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-		};
-
-		wireless_white {
-			label = "white:wireless";
-			gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		wireless_orange {
-			label = "orange:wireless";
-			gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		auto_mode {
-			label = "auto_mode";
-			gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			linux,input-type = <EV_SW>;
-		};
-
-		router_mode {
-			label = "router_mode";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_1>;
-			linux,input-type = <EV_SW>;
-		};
-
-		ap_mode {
-			label = "ap_mode";
-			gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_2>;
-			linux,input-type = <EV_SW>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "AOSS Button";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-};
-
-&tlmm {
-	serial_0_pins: serial0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	usb_power {
-		line-name = "USB power";
-		gpios = <34 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@0,0 {
-			compatible = "qcom,ath10k";
-			reg = <0 0 0 0 0>;
-			nvmem-cell-names = "pre-calibration", "mac-address";
-			nvmem-cells = <&precal_art_9000>, <&macaddr_orgdata_32>;
-			qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0000000 0x0100000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "MIBIB";
-				reg = <0x0100000 0x0100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "BOOTCONFIG";
-				reg = <0x0200000 0x0100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "QSEE";
-				reg = <0x0300000 0x0100000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "QSEE_1";
-				reg = <0x0400000 0x0100000>;
-				read-only;
-			};
-
-			partition@500000 {
-				label = "CDT";
-				reg = <0x0500000 0x0080000>;
-				read-only;
-			};
-
-			partition@580000 {
-				label = "CDT_1";
-				reg = <0x0580000 0x0080000>;
-				read-only;
-			};
-
-			partition@600000 {
-				label = "BOOTCONFIG1";
-				reg = <0x0600000 0x0080000>;
-				read-only;
-			};
-
-			partition@680000 {
-				label = "APPSBLENV";
-				reg = <0x0680000 0x0080000>;
-			};
-
-			partition@700000 {
-				label = "APPSBL";
-				reg = <0x0700000 0x0200000>;
-				read-only;
-			};
-
-			partition@900000 {
-				label = "APPSBL_1";
-				reg = <0x0900000 0x0200000>;
-				read-only;
-			};
-
-			partition@b00000 {
-				label = "ART";
-				reg = <0x0b00000 0x0080000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					precal_art_9000: precal@9000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@b80000 {
-				label = "ART_1";
-				reg = <0x0b80000 0x0080000>;
-				read-only;
-			};
-
-			orgdata: partition@c00000 {
-				label = "ORGDATA";
-				reg = <0x0c00000 0x0080000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_orgdata_20: macaddr@20 {
-						reg = <0x20 0x6>;
-					};
-					macaddr_orgdata_26: macaddr@26 {
-						reg = <0x26 0x6>;
-					};
-					macaddr_orgdata_2c: macaddr@2c {
-						reg = <0x2c 0x6>;
-					};
-					macaddr_orgdata_32: macaddr@32 {
-						reg = <0x32 0x6>;
-					};
-				};
-			};
-
-			partition@c80000 {
-				label = "ORGDATA_1";
-				reg = <0x0c80000 0x0080000>;
-				read-only;
-			};
-
-			partition@d00000 {
-				label = "ubi";
-				reg = <0x0d00000 0x2900000>;
-			};
-
-			partition@3600000 {
-				label = "rootfs_recover";
-				reg = <0x3600000 0x2900000>;
-				read-only;
-			};
-
-			partition@5f00000 {
-				label = "user_property";
-				reg = <0x5f00000 0x1a20000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_orgdata_26>;
-	qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
-	ieee80211-freq-limit = <2400000 2483000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_orgdata_2c>;
-	qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-	label = "lan3";
-};
-
-&swport3 {
-	status = "okay";
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-};
-
-&swport5 {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_orgdata_20>;
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dts
deleted file mode 100644
index 3d71593e86..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include "qcom-ipq4019-x1pro.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Telco X1 Pro";
-	compatible = "tel,x1pro","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-		broken-flash-reset;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-			partition@60000 {
-				label = "0:QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-			partition@c0000 {
-				label = "0:CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-			partition@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-			partition@e0000 {
-				label = "0:APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-			partition@f0000 {
-				label = "0:APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-			art: partition@170000 {
-				label = "0:ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0x1e80000>;
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi
deleted file mode 100644
index fe3650ca58..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi
+++ /dev/null
@@ -1,218 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	compatible = "tel,x1pro","qcom,ipq4019";
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-		serial0 = &blsp1_uart1;
-		serial1 = &blsp1_uart2;
-	};
-
-	soc {
-
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		leds {
-			compatible = "gpio-leds";
-			pinctrl-0 = <&led_pins>;
-			pinctrl-names = "default";
-
-			led_status: status {
-				function = LED_FUNCTION_STATUS;
-				color = <LED_COLOR_ID_GREEN>;
-				gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-			};
-		};
-
-		keys {
-			compatible = "gpio-keys";
-
-			reset {
-				label = "reset";
-				gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-				linux,code = <KEY_RESTART>;
-			};
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	led_pins: led_pinmux {
-		mux {
-			function = "gpio";
-			pins = "gpio68";
-			bias-disabled;
-			output-low;
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-xx8300.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-xx8300.dtsi
deleted file mode 100644
index 141ea60442..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4019-xx8300.dtsi
+++ /dev/null
@@ -1,326 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/*
- * Device Tree Source for Linksys xx8300 (Dallas)
- *
- * Copyright (C) 2019, 2022 Jeff Kletsky
- * Updated 2020 Hans Geiblinger
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-	//
-	// OEM U-Boot provides either
-	// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
-	//                 root=ubi0:ubifs rootwait rw
-	// or the same with ubi.mtd=13,2048
-	//
-
-/ {
-	chosen {
-		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
-	};
-
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	regulator-usb-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "USB_VBUS";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-		gpio = <&tlmm 68 GPIO_ACTIVE_LOW>;
-	};
-};
-
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x0 0x100000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "mibib";
-				reg = <0x100000 0x100000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "qsee";
-				reg = <0x200000 0x100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "cdt";
-				reg = <0x300000 0x80000>;
-				read-only;
-			};
-
-			partition@380000 {
-				label = "appsblenv";
-				reg = <0x380000 0x80000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "ART";
-				reg = <0x400000 0x80000>;
-				read-only;
-			};
-
-			partition@480000 {
-				label = "appsbl";
-				reg = <0x480000 0x200000>;
-				read-only;
-			};
-
-			partition@680000 {
-				label = "u_env";
-				reg = <0x680000 0x80000>;
-				// writable -- U-Boot environment
-			};
-
-			partition@700000 {
-				label = "s_env";
-				reg = <0x700000 0x40000>;
-				// writable -- Boot counter records
-			};
-
-			partition@740000 {
-				label = "devinfo";
-				reg = <0x740000 0x40000>;
-				read-only;
-			};
-
-			partition@780000 {
-				label = "kernel";
-				reg = <0x780000 0x5800000>;
-			};
-
-			partition@c80000 {
-				label = "rootfs";
-				reg = <0xc80000 0x5300000>;
-			};
-
-			partition@5f80000 {
-				label = "alt_kernel";
-				reg = <0x5f80000 0x5800000>;
-			};
-
-			partition@6480000 {
-				label = "alt_rootfs";
-				reg = <0x6480000 0x5300000>;
-			};
-
-			partition@b780000 {
-				label = "sysdiag";
-				reg = <0xb780000 0x100000>;
-				read-only;
-			};
-
-			partition@b880000 {
-				label = "syscfg";
-				reg = <0xb880000 0x4680000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	serial_0_pins: serial0-pinmux {
-		pins = "gpio16", "gpio17";
-		function = "blsp_uart0";
-		bias-disable;
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		// gpio61 controls led_usb
-
-		pulldowns {
-			pins =  "gpio55", "gpio56", "gpio57",
-				"gpio60", "gpio62", "gpio63",
-				"gpio64", "gpio65", "gpio66",
-				"gpio67", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts
deleted file mode 100644
index 4b61bbb5ac..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Compex WPJ428";
-	compatible = "compex,wpj428";
-
-	chosen {
-		/*
-		 * There's a chance that SPI reads fail even though the data itself is alright.
-		 * The read result is cached and squashfs can't recover.
-		 * Just panic when that happens and hope that next time it doesn't.
-		 */
-		bootargs-append = " rootflags=errors=panic";
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2: usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &status;
-		led-failsafe = &status;
-		led-upgrade = &status;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		status: rss4 {
-			label = "green:rss4";
-			gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-		};
-
-		rss3 {
-			label = "green:rss3";
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	beeper: beeper {
-		compatible = "gpio-beeper";
-		gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio53";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux_2 {
-			pins = "gpio52";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	m25p80@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "0:APPSBLENV"; /* uboot env*/
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition5@f0000 {
-				label = "0:APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-			partition5@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_e010: mac-address@e010 {
-						reg = <0xe010 0x6>;
-					};
-
-					macaddr_art_e018: mac-address@e018 {
-						reg = <0xe018 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			partition6@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x00180000 0x01e80000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "lan1";
-
-	nvmem-cells = <&macaddr_art_e018>;
-	nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
-	status = "okay";
-	label = "lan2";
-
-	nvmem-cells = <&macaddr_art_e010>;
-	nvmem-cell-names = "mac-address";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts
deleted file mode 100644
index 7e484db1b5..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts
+++ /dev/null
@@ -1,204 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Aruba AP-303";
-	compatible = "aruba,ap-303";
-
-	aliases {
-		led-boot = &led_system_green;
-		led-failsafe = &led_system_red;
-		led-running = &led_system_green;
-		led-upgrade = &led_system_red;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		wifi_green {
-			label = "green:wifi";
-			gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wifi_amber {
-			label = "amber:wifi";
-			gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led_system_red: system_red {
-			label = "red:system";
-			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_system_green: system_green {
-			label = "green:system";
-			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	/*
-	 * In addition to the Pins listed below,
-	 * the following GPIOs have "features":
-	 * 54 - out - active low to force HW reset
-	 * 41 - out - active low to reset TPM
-	 * 43 - out - active low to reset BLE radio
-	 * 19 - in  - active high when DC powered
-	 */
-
-	phy-reset {
-		line-name = "PHY-reset";
-		gpios = <42 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			/*
-			 * There is no partition map for the NOR flash
-			 * in the stock firmware.
-			 *
-			 * All partitions here are based on offsets
-			 * found in the U-Boot GPL code and information
-			 * from smem.
-			 */
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "mibib";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "qsee";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "cdt";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "ddrparams";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "ART";
-				reg = <0xe0000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@f0000 {
-				label = "appsbl";
-				reg = <0xf0000 0xf0000>;
-				read-only;
-			};
-
-			partition@1e0000 {
-				label = "mfginfo";
-				reg = <0x1e0000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mfginfo_1d: macaddr@1d {
-						compatible = "mac-base";
-						reg = <0x1d 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@1f0000 {
-				label = "apcd";
-				reg = <0x1f0000 0x10000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "osss";
-				reg = <0x200000 0x180000>;
-				read-only;
-			};
-
-			partition@380000 {
-				label = "appsblenv";
-				reg = <0x380000 0x10000>;
-			};
-
-			partition@390000 {
-				label = "pds";
-				reg = <0x390000 0x10000>;
-				read-only;
-			};
-
-			partition@3a0000 {
-				label = "fcache";
-				reg = <0x3a0000 0x10000>;
-				read-only;
-			};
-
-			partition@3b0000 {
-				/* Called osss1 in smem */
-				label = "u-boot-env-bak";
-				reg = <0x3b0000 0x10000>;
-				read-only;
-			};
-
-			partition@3f0000 {
-				label = "u-boot-env";
-				reg = <0x3f0000 0x10000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts
deleted file mode 100644
index 41b42e8f58..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts
+++ /dev/null
@@ -1,479 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Aruba AP-303H";
-	compatible = "aruba,ap-303h";
-
-	aliases {
-		led-boot = &led_system_green;
-		led-failsafe = &led_system_red;
-		led-running = &led_system_green;
-		led-upgrade = &led_system_amber;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			tpm@29 {
-				/* No Driver */
-				compatible = "atmel,at97sc3203";
-				reg = <0x29>;
-				read-only;
-			};
-
-			power-monitor@40 {
-				/* No driver */
-				compatible = "isl,isl28022";
-				reg = <0x40>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		wifi_green {
-			label = "green:wifi";
-			gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wifi_amber {
-			label = "amber:wifi";
-			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		pse {
-			label = "green:pse";
-			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_system_red: system_red {
-			label = "red:system";
-			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_system_green: system_green {
-			label = "green:system";
-			gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_system_amber: system_amber {
-			label = "amber:system";
-			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "Reset button";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	/* Texas Instruments CC2540T BLE radio */
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	/*
-	 * In addition to the Pins listed below,
-	 * the following GPIOs have "features":
-	 * 39 - out - active low to force HW reset
-	 * 32 - out - active low to reset TPM
-	 * 43 - out - active low to reset BLE radio
-	 * 41 - out - pulse to set warm reset status
-	 * 34 - out - active low to enable PSE port
-	 * 22 - in  - active low when 802.3at powered
-	 * 29 - in  - active high when DC powered
-	 * 40 - in  - active low when reset due to cold HW reset
-	 * 30 - in  - active low when USB overcurrent detected
-	 * 35 - in  - interrupt line for power monitor chip
-	 * 31 - in  - active low when PSE port active
-	 */
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12", "gpio59";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio20", "gpio21";
-			function = "blsp_i2c0";
-			drive-strength = <4>;
-			bias-disable;
-		};
-	};
-
-	serial_0_pins: serial_0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial_1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	usb-power {
-		line-name = "USB-power";
-		gpios = <23 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			/*
-			 * There is no partition map for the NOR flash
-			 * in the stock firmware.
-			 *
-			 * All partitions here are based on offsets
-			 * found in the U-Boot GPL code and information
-			 * from smem.
-			 */
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "mibib";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "qsee";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "cdt";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "ddrparams";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "appsblenv";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "appsbl";
-				reg = <0xf0000 0x100000>;
-				read-only;
-			};
-
-			partition@1e0000 {
-				label = "ART";
-				reg = <0x1f0000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@1f0000 {
-				label = "osss";
-				reg = <0x200000 0x170000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "pds";
-				reg = <0x370000 0x10000>;
-				read-only;
-			};
-
-			partition@380000 {
-				label = "apcd";
-				reg = <0x380000 0x10000>;
-				read-only;
-			};
-
-			partition@390000 {
-				label = "mfginfo";
-				reg = <0x390000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mfginfo_1d: macaddr@1d {
-						reg = <0x1d 0x6>;
-					};
-
-					macaddr_mfginfo_45: macaddr@45 {
-						compatible = "mac-base";
-						reg = <0x45 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@3a0000 {
-				label = "fcache";
-				reg = <0x3a0000 0x10000>;
-				read-only;
-			};
-
-			partition@3b0000 {
-				/* Called osss1 in smem */
-				label = "u-boot-env-bak";
-				reg = <0x3b0000 0x10000>;
-				read-only;
-			};
-
-			partition@3f0000 {
-				label = "u-boot-env";
-				reg = <0x3c0000 0x40000>;
-				read-only;
-			};
-		};
-	};
-
-	flash@1 {
-		status = "okay";
-
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				/* 'aos0' in Aruba firmware */
-				label = "aos0";
-				reg = <0x0 0x2000000>;
-				read-only;
-			};
-
-			partition@2000000 {
-				/* 'aos1' in Aruba firmware */
-				label = "ubi";
-				reg = <0x2000000 0x2000000>;
-			};
-
-			partition@4000000 {
-				label = "aruba-ubifs";
-				reg = <0x4000000 0x4000000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport2 {
-	status = "okay";
-
-	label = "lan1";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan3";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "wan";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
-	qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
-	qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts
deleted file mode 100644
index 3477dace72..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts
+++ /dev/null
@@ -1,227 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Aruba AP-365";
-	compatible = "aruba,ap-365";
-
-	aliases {
-		led-boot = &led_system_green;
-		led-failsafe = &led_system_red;
-		led-running = &led_system_green;
-		led-upgrade = &led_system_red;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_system_red: system_red {
-			label = "red:system";
-			gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
-		};
-
-		led_system_green: system_green {
-			label = "green:system";
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-		};
-
-		system_amber {
-			label = "amber:system";
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	watchdog {
-		compatible = "linux,wdt-gpio";
-		gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-		hw_algo = "toggle";
-		hw_margin_ms = <1000>;
-		always-running;
-	};
-};
-
-&tlmm {
-	/*
-	 * In addition to the Pins listed below,
-	 * the following GPIOs have "features":
-	 * 39 - out - pulse low to reset watchdog status flipflop
-	 * 40 - out - active high to enable watchdog
-	 * 41 - out - watchdog poke
-	 * 42 - out - active low to reset BLE radio
-	 * 43 - out - active low to reset TPM
-	 * 47 - out - pulse low to reset warm reset status
-	 * 54 - out - active low to force HW reset
-	 * 18 - in  - PHY interrupt line
-	 * 45 - in  - power monitor interrupt
-	 * 48 - in  - active low when cold reset
-	 * 52 - in  - active high when watchdog reset
-	 */
-
-	phy-reset {
-		line-name = "PHY-reset";
-		gpios = <42 GPIO_ACTIVE_HIGH>;
-		gpio-hog;
-		output-high;
-	};
-};
-
-&i2c_0 {
-	power-monitor@40 {
-		/* No driver */
-		compatible = "isl,isl28022";
-		reg = <0x40>;
-	};
-
-	temperature-sensor@48 {
-		compatible = "adi,ad7416";
-		reg = <0x48>;
-	};
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			/*
-			 * There is no partition map for the NOR flash
-			 * in the stock firmware.
-			 *
-			 * All partitions here are based on offsets
-			 * found in the U-Boot GPL code and information
-			 * from smem.
-			 */
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "mibib";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "qsee";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			partition@c0000 {
-				label = "cdt";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			partition@d0000 {
-				label = "ddrparams";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			partition@e0000 {
-				label = "u-boot-env";
-				reg = <0xe0000 0x10000>;
-			};
-
-			partition@f0000 {
-				label = "appsbl";
-				reg = <0xf0000 0x100000>;
-				read-only;
-			};
-
-			partition@1f0000 {
-				label = "ART";
-				reg = <0x1f0000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@200000 {
-				label = "osss";
-				reg = <0x200000 0x170000>;
-				read-only;
-			};
-
-			partition@370000 {
-				label = "pds";
-				reg = <0x370000 0x10000>;
-				read-only;
-			};
-
-			partition@380000 {
-				label = "apcd";
-				reg = <0x380000 0x10000>;
-				read-only;
-			};
-
-			partition@390000 {
-				label = "mfginfo";
-				reg = <0x390000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_mfginfo_1d: macaddr@1d {
-						compatible = "mac-base";
-						reg = <0x1d 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@3a0000 {
-				label = "fcache";
-				reg = <0x3a0000 0x10000>;
-				read-only;
-			};
-
-			partition@3b0000 {
-				label = "osss1";
-				reg = <0x3b0000 0x50000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&wifi0 {
-	qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
-&wifi1 {
-	qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi
deleted file mode 100644
index 4b3b682260..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi
+++ /dev/null
@@ -1,271 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			ethphy: ethernet-phy@5 {
-				reg = <0x5>;
-			};
-		};
-
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			tpm@29 {
-				/* No Driver */
-				compatible = "atmel,at97sc3203";
-				reg = <0x29>;
-				read-only;
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "Reset button";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	/* Texas Instruments CC2540T BLE radio */
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins = "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		mux {
-			pins = "gpio10", "gpio11";
-			function = "blsp_i2c0";
-			drive-strength = <4>;
-			bias-disable;
-		};
-	};
-
-	serial_0_pins: serial_0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial_1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				/* 'aos0' in Aruba firmware */
-				label = "aos0";
-				reg = <0x0 0x2000000>;
-				read-only;
-			};
-
-			partition@2000000 {
-				/* 'aos1' in Aruba firmware */
-				label = "ubi";
-				reg = <0x2000000 0x2000000>;
-			};
-
-			partition@4000000 {
-				label = "aruba-ubifs";
-				reg = <0x4000000 0x4000000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-
-	/delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-	phy-handle = <&ethphy>;
-	phy-mode = "rgmii-id";
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	status = "disabled";
-};
-
-&ethphy4 {
-	status = "disabled";
-};
-
-&psgmiiphy {
-	status = "disabled";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d 0>;
-	qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d 1>;
-	qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
deleted file mode 100644
index 13ed26d5d6..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts
+++ /dev/null
@@ -1,329 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-B1300";
-	compatible = "glinet,gl-b1300";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-		label-mac-device = &swport4;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		mesh {
-			label = "green:mesh";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
-	mx25l25635f@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			SBL1@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			MIBIB@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			QSEE@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			CDT@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			DDRPARAMS@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			APPSBLENV@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			APPSBL@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			ART@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_gmac0: macaddr@0 {
-						compatible = "mac-base";
-						reg = <0x0 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					macaddr_gmac1: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			firmware@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0x1e80000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio54";
-		};
-		pinconf {
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport3 {
-	status = "okay";
-
-	label = "lan2";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
-	status = "okay";
-
-	label = "lan1";
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
-	status = "okay";
-
-	nvmem-cell-names = "mac-address";
-	nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "GL-B1300";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "GL-B1300";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts
deleted file mode 100644
index e7236824aa..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts
+++ /dev/null
@@ -1,363 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-S1300";
-	compatible = "glinet,gl-s1300";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "okay";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		mesh {
-			label = "green:mesh";
-			gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan {
-			function = LED_FUNCTION_WLAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-	};
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			SBL1@0 {
-				label = "SBL1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			MIBIB@40000 {
-				label = "MIBIB";
-				reg = <0x40000 0x20000>;
-				read-only;
-			};
-
-			QSEE@60000 {
-				label = "QSEE";
-				reg = <0x60000 0x60000>;
-				read-only;
-			};
-
-			CDT@c0000 {
-				label = "CDT";
-				reg = <0xc0000 0x10000>;
-				read-only;
-			};
-
-			DDRPARAMS@d0000 {
-				label = "DDRPARAMS";
-				reg = <0xd0000 0x10000>;
-				read-only;
-			};
-
-			APPSBLENV@e0000 {
-				label = "APPSBLENV";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			APPSBL@f0000 {
-				label = "APPSBL";
-				reg = <0xf0000 0x80000>;
-				read-only;
-			};
-
-			ART@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			firmware@180000 {
-				compatible = "denx,fit";
-				label = "firmware";
-				reg = <0x180000 0xe80000>;
-			};
-		};
-	};
-};
-
-&blsp1_spi2 {
-	pinctrl-0 = <&spi_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	spidev1: spi@0 {
-		compatible = "silabs,si3210";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-	};
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9",
-				"gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-		};
-		pinconf {
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinconf_cs {
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	spi_1_pins: spi_1_pinmux {
-		mux {
-			pins = "gpio44", "gpio46", "gpio47";
-			function = "blsp_spi1";
-			bias-disable;
-		};
-		host_int {
-			pins = "gpio42";
-			function = "gpio";
-			input;
-		};
-		cs {
-			pins = "gpio45";
-			function = "gpio";
-			bias-pull-up;
-		};
-		wake {
-			pins = "gpio40";
-			function = "gpio";
-			output-high;
-		};
-		reset {
-			pins = "gpio49";
-			function = "gpio";
-			output-high;
-		};
-	};
-
-	sd_pins: sd_pins {
-		pinmux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio28", "gpio29", "gpio30", "gpio31";
-			drive-strength = <10>;
-		};
-
-		pinmux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-
-		pinmux_sd7 {
-			function = "sdio";
-			pins = "gpio32";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
-	qcom,ath10k-calibration-variant = "GL-S1300";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
-	qcom,ath10k-calibration-variant = "GL-S1300";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi
deleted file mode 100644
index 2b9f73eb24..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-insect-common.dtsi
+++ /dev/null
@@ -1,444 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for Meraki "Insect" series
- *
- * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
- * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
- *
- * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	aliases {
-		led-boot = &status_green;
-		led-failsafe = &status_red;
-		led-running = &status_green;
-		led-upgrade = &power_orange;
-	};
-
-	/* Do we really need this defined? */
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		/* It is a 56-bit counter that supplies the count to the ARM arch
-		   timers and without upstream driver */
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			bluetooth {
-				compatible = "ti,cc2650";
-				enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		power_orange: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-			panic-indicator;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	eeprom@50 {
-		compatible = "atmel,24c64";
-		pagesize = <32>;
-		reg = <0x50>;
-		read-only; /* This holds our MAC & Meraki board-data */
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		mac_address: mac-address@66 {
-			compatible = "mac-base";
-			reg = <0x66 0x6>;
-			#nvmem-cell-cells = <1>;
-		};
-	};
-};
-
-&blsp1_i2c4 {
-	pinctrl-0 = <&i2c_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	tricolor: led-controller@30 {
-		compatible = "ti,lp5562";
-		reg = <0x30>;
-		clock-mode = /bits/8 <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* RGB led */
-		status_red: chan@0 {
-			chan-name = "red:status";
-			led-cur = /bits/ 8 <0x20>;
-			max-cur = /bits/ 8 <0x60>;
-			reg = <0>;
-			color = <LED_COLOR_ID_RED>;
-		};
-
-		status_green: chan@1 {
-			chan-name = "green:status";
-			led-cur = /bits/ 8 <0x20>;
-			max-cur = /bits/ 8 <0x60>;
-			reg = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-		};
-
-		chan@2 {
-			chan-name = "blue:status";
-			led-cur = /bits/ 8 <0x20>;
-			max-cur = /bits/ 8 <0x60>;
-			reg = <2>;
-			color = <LED_COLOR_ID_BLUE>;
-		};
-
-		chan@3 {
-			chan-name = "white:status";
-			led-cur = /bits/ 8 <0x20>;
-			max-cur = /bits/ 8 <0x60>;
-			reg = <3>;
-			color = <LED_COLOR_ID_WHITE>;
-		};
-	};
-};
-
-&nand {
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x00000000 0x00100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "mibib";
-				reg = <0x00100000 0x00100000>;
-				read-only;
-			};
-			partition@200000 {
-				label = "bootconfig";
-				reg = <0x00200000 0x00100000>;
-				read-only;
-			};
-			partition@300000 {
-				label = "qsee";
-				reg = <0x00300000 0x00100000>;
-				read-only;
-			};
-			partition@400000 {
-				label = "qsee_alt";
-				reg = <0x00400000 0x00100000>;
-				read-only;
-			};
-			partition@500000 {
-				label = "cdt";
-				reg = <0x00500000 0x00080000>;
-				read-only;
-			};
-			partition@580000 {
-				label = "cdt_alt";
-				reg = <0x00580000 0x00080000>;
-				read-only;
-			};
-			partition@600000 {
-				label = "ddrparams";
-				reg = <0x00600000 0x00080000>;
-				read-only;
-			};
-			partition@700000 {
-				label = "u-boot";
-				reg = <0x00700000 0x00200000>;
-				read-only;
-			};
-			partition@900000 {
-				label = "u-boot-backup";
-				reg = <0x00900000 0x00200000>;
-				read-only;
-			};
-			partition@b00000 {
-				label = "ART";
-				reg = <0x00b00000 0x00080000>;
-				read-only;
-			};
-			partition@c00000 {
-				label = "ubi";
-				reg = <0x00c00000 0x07000000>;
-				/*
-				 * Do not try to allocate the remaining
-				 * 4 MiB to this ubi partition. It will
-				 * confuse the u-boot and it might not
-				 * find the kernel partition anymore.
-				 */
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			nvmem-cells = <&mac_address 1>;
-			nvmem-cell-names = "mac-address";
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&tlmm {
-	/*
-	 * GPIO43 should be 0/1 whenever the unit is
-	 * powered through PoE or AC-Adapter.
-	 * That said, playing with this seems to
-	 * reset the AP.
-	 */
-
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial_0_pins: serial_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1_pinmux {
-		mux {
-			/* We use the i2c-0 pins for serial_1 */
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	i2c_0_pins: i2c_0_pinmux {
-		pinmux {
-			function = "blsp_i2c0";
-			pins = "gpio20", "gpio21";
-		};
-		pinconf {
-			pins = "gpio20", "gpio21";
-			drive-strength = <16>;
-			bias-disable;
-		};
-	};
-
-	i2c_1_pins: i2c_1_pinmux {
-		pinmux {
-			function = "blsp_i2c1";
-			pins = "gpio34", "gpio35";
-		};
-		pinconf {
-			pins = "gpio34", "gpio35";
-			drive-strength = <16>;
-			bias-disable;
-		};
-	};
-
-	nand_pins: nand_pins {
-		/*
-		 * There are 18 pins. 15 pins are common between LCD and NAND.
-		 * The QPIC controller arbitrates between LCD and NAND. Of the
-		 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
-		 *
-		 * The meraki source hints that the bluetooth module claims
-		 * pin 52 as well. But sadly, there's no data whenever this
-		 * is a NAND or LCD exclusive pin or not.
-		 */
-
-		pullups {
-			pins = "gpio52", "gpio53", "gpio58",
-				"gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56",
-				"gpio57", "gpio60", "gpio61",
-				"gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67",
-				"gpio68", "gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Meraki-MR33";
-	nvmem-cells = <&mac_address 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Meraki-MR33";
-	nvmem-cells = <&mac_address 3>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac {
-	status = "okay";
-	nvmem-cells = <&mac_address 0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&switch {
-	status = "okay";
-
-	/delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-	phy-handle = <&ethphy1>;
-	phy-mode = "rgmii-rxid";
-};
-
-&ethphy0 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
-};
-
-&ethphy3 {
-	status = "disabled";
-};
-
-&ethphy4 {
-	status = "disabled";
-};
-
-&psgmiiphy {
-	status = "disabled";
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr33.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr33.dts
deleted file mode 100644
index 8c8b1b3150..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr33.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR33 (Stinkbug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
-	model = "Meraki MR33 Access Point";
-	compatible = "meraki,mr33";
-};
-
-&tricolor {
-	enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr74.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr74.dts
deleted file mode 100644
index 904f724652..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-mr74.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR74 (Ladybug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
-	model = "Meraki MR74 Access Point";
-	compatible = "meraki,mr74";
-};
-
-&tricolor {
-	enable-gpio = <&tlmm 14 GPIO_ACTIVE_LOW>;
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts
deleted file mode 100644
index 8794d839a8..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Extreme Networks WS-AP3915i";
-	compatible = "extreme-networks,ws-ap3915i";
-
-	aliases {
-		led-boot = &led_system_green;
-		led-failsafe = &led_system_amber;
-		led-running = &led_system_green;
-		led-upgrade = &led_system_amber;
-	};
-
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_system_green: system_green {
-			label = "green:system";
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-		};
-
-		led_system_amber: system_amber {
-			label = "amber:system";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-
-		led_wlan24_green: wlan24_green {
-			label = "green:wlan24";
-			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led_wlan24_amber: wlan24_amber {
-			label = "amber:wlan24";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-		};
-
-		led_wlan5_green: wlan5_green {
-			label = "green:wlan5";
-			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led_wlan5_amber: wlan5_amber {
-			label = "amber:wlan5";
-			gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
-		};
-
-		iot {
-			label = "blue:iot";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART >;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport5 {
-	status = "okay";
-
-	label = "lan";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	serial_pins: serial_0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			/* Layout for 0x0 - 0xe0000 unknown */
-
-			partition@e0000 {
-				label = "CFG1";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "BootBAK";
-				reg = <0xf0000 0x70000>;
-				read-only;
-			};
-
-			partition@160000 {
-				label = "WINGCFG1";
-				reg = <0x160000 0x10000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "BootPRI";
-				reg = <0x180000 0x70000>;
-				read-only;
-			};
-
-			partition@1f0000 {
-				label = "WINGCFG2";
-				reg = <0x1f0000 0x10000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "FS";
-				reg = <0x200000 0x80000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "firmware";
-				reg = <0x280000 0x1d60000>;
-			};
-
-			partition@1fe0000 {
-				label = "CFG2";
-				reg = <0x1fe0000 0x10000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts
deleted file mode 100644
index 04b55b1abf..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts
+++ /dev/null
@@ -1,344 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Extreme Networks WS-AP391x";
-	compatible = "extreme-networks,ws-ap391x";
-
-	aliases {
-		led-boot = &led_system_green;
-		led-failsafe = &led_system_red;
-		led-running = &led_system_green;
-		led-upgrade = &led_system_red;
-	};
-
-	soc {
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_system_green: system_green {
-			label = "system:green";
-			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
-		};
-
-		/*
-		 * system:amber ==> AP3917
-		 * system:red ==> AP3916
-		 * */
-		led_system_red: system_red {
-			label = "system:red_or_system:amber";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-		};
-
-		led_wlan24_green: wlan24_green {
-			label = "wlan24:green";
-			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		/*
-		 * wlan24:amber ==> AP3915/AP3917
-		 * pse:green ==> AP3912
-		 * */
-		led_wlan24_amber: wlan24_amber {
-			label = "wlan24:amber_or_pse:green";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-		};
-
-		led_wlan5_green: wlan5_green {
-			label = "wlan5:green";
-			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		/* iot:blue ==>  AP3917 */
-		led_iot_green: iot_green {
-			label = "iot:green_or_iot:blue";
-			gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
-		};
-
-		/* eth:green ==> only AP3912/AP3916 */
-		led_eth_green: eth_green {
-			label = "eth:green";
-			gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-		};
-
-		/*
-		 * eth:amber ==> only AP3912/AP3916
-		 * usb_enable ==> only AP3915e
-		 */
-		led_eth_amber: eth_amber {
-			label = "eth:amber_or_usb_enable";
-			gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
-		};
-
-		/*
-		 * wlan5:amber ==> AP3915/AP3917
-		 * cam:green ==> only AP3916
-		 */
-		led_wlan5_amber: wlan5_amber {
-			label = "wlan5:amber_or_cam:green";
-			gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
-		};
-
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART >;
-		};
-	};
-};
-
-&prng {
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	pinctrl-0 = <&serial_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&cryptobam {
-	status = "okay";
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport1 {
-	status = "okay";
-	label = "sw-eth1";
-};
-
-&swport2 {
-	status = "okay";
-	label = "sw-eth2";
-};
-
-&swport3 {
-	status = "okay";
-	label = "sw-eth3";
-};
-
-/* "GE2" on AP3917/AP3916/WiNG-AP7662 */
-&swport4 {
-	status = "okay";
-	label = "sw-eth4";
-};
-
-/*
- * "GE1" on AP3917/AP3916/AP3915/AP7662
- * "LAN1" on EXTR-AP3912
- */
-&swport5 {
-	status = "okay";
-	label = "sw-eth5";
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pin {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pin_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	serial_pins: serial_0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-};
-
-&wifi0 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
-	status = "okay";
-	qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			/* Layout for 0x0 - 0xe0000 unknown */
-
-			partition@e0000 {
-				label = "CFG1";
-				compatible = "u-boot,env-redundant-bool";
-				reg = <0xe0000 0x10000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "BootBAK";
-				reg = <0xf0000 0x70000>;
-				read-only;
-			};
-
-			partition@160000 {
-				label = "WINGCFG1";
-				reg = <0x160000 0x10000>;
-				read-only;
-			};
-
-			partition@170000 {
-				label = "ART";
-				reg = <0x170000 0x10000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "BootPRI";
-				reg = <0x180000 0x70000>;
-				read-only;
-			};
-
-			partition@1f0000 {
-				label = "WINGCFG2";
-				reg = <0x1f0000 0x10000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "FS";
-				reg = <0x200000 0x80000>;
-				read-only;
-			};
-
-			partition@280000 {
-				label = "firmware";
-				reg = <0x280000 0xeb0000>;
-			};
-
-			partition@1130000 {
-				label = "firmware2";
-				reg = <0x1130000 0xeb0000>;
-			};
-
-			partition@1fe0000 {
-				label = "CFG2";
-				compatible = "u-boot,env-redundant-bool";
-				reg = <0x1fe0000 0x10000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq40x9-dr40x9.dts b/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq40x9-dr40x9.dts
deleted file mode 100644
index 271a972092..0000000000
--- a/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq40x9-dr40x9.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Wallystech DR40X9";
-	compatible = "wallys,dr40x9";
-
-	chosen {
-		bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
-	};
-
-	soc {
-		counter@4a1000 {
-			compatible = "qcom,qca-gcnt";
-			reg = <0x4a1000 0x4>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			status = "okay";
-
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		wlan2g {
-			label = "dr4029:green:wlan2g";
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g {
-			label = "dr4029:green:wlan5g";
-			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		wlan2g-strength {
-			label = "dr4029:green:wlan2g-strength";
-			gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan5g-strength {
-			label = "dr4029:green:wlan5g-strength";
-			gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&tlmm {
-	mdio_pins: mdio_pinmux {
-		mux_1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
-	serial0_pins: serial0_pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial1_pins: serial1_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "blsp_uart1";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		pinmux {
-			function = "blsp_spi0";
-			pins = "gpio13", "gpio14", "gpio15";
-			drive-strength = <12>;
-			bias-disable;
-		};
-		pinmux_cs {
-			function = "gpio";
-			pins = "gpio12";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	nand_pins: nand_pins {
-		pullups {
-			pins =  "gpio52", "gpio53", "gpio58", "gpio59";
-			function = "qpic";
-			bias-pull-up;
-		};
-
-		pulldowns {
-			pins = "gpio54", "gpio55", "gpio56", "gpio57",
-				"gpio60", "gpio62", "gpio63", "gpio64",
-				"gpio65", "gpio66", "gpio67", "gpio68",
-				"gpio69";
-			function = "qpic";
-			bias-pull-down;
-		};
-	};
-
-	sd_pins: sd_pins {
-		pinmux {
-			function = "sdio";
-			pins = "gpio23", "gpio24", "gpio25", "gpio26",
-				"gpio28", "gpio29", "gpio30", "gpio31";
-			drive-strength = <10>;
-		};
-		pinmux_sd_clk {
-			function = "sdio";
-			pins = "gpio27";
-			drive-strength = <16>;
-		};
-		pinmux_sd7 {
-			function = "sdio";
-			pins = "gpio32";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&blsp1_spi1 {
-	status = "okay";
-
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-
-	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <24000000>;
-		reg = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "0:SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-
-			partition1@40000 {
-				label = "0:MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-
-			partition2@60000 {
-				label = "0:QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-
-			partition3@c0000 {
-				label = "0:CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-
-			partition4@d0000 {
-				label = "0:DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-
-			partition5@e0000 {
-				label = "0:APPSBLENV"; /* uboot env */
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-
-			partition6@f0000 {
-				label = "0:APPSBL"; /* uboot */
-				reg = <0x000f0000 0x00080000>;
-				read-only;
-			};
-
-			partition7@170000 {
-				label = "0:ART";
-				reg = <0x00170000 0x00010000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: mac-address@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: mac-address@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					macaddr_art_1006: mac-address@1006 {
-						reg = <0x1006 0x6>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-
-					macaddr_art_5006: mac-address@5006 {
-						reg = <0x5006 0x6>;
-					};
-				};
-			};
-
-			partition8@180000 {
-				label = "0:CONFIG";
-				reg = <0x00180000 0x00010000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi";
-				reg = <0x00000000 0x04000000>;
-			};
-		};
-	};
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial0_pins>;
-	pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
-	status = "okay";
-	pinctrl-0 = <&serial1_pins>;
-	pinctrl-names = "default";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&cryptobam {
-	num-channels = <4>;
-	qcom,num-ees = <2>;
-	status = "okay";
-};
-
-&mdio {
-	status = "okay";
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-	reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <2000>;
-};
-
-&pcie0 {
-	status = "okay";
-
-	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
-
-	/* Unpolulated slot */
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-	};
-};
-
-&vqmmc {
-	status = "okay";
-};
-
-&sdhci {
-	status = "okay";
-	pinctrl-0 = <&sd_pins>;
-	pinctrl-names = "default";
-	cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
-	vqmmc-supply = <&vqmmc>;
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&swport4 {
-	status = "okay";
-	label = "wan";
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
-	status = "okay";
-	label = "lan";
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
-	status = "okay";
-	nvmem-cells = <&precal_art_1000>, <&macaddr_art_1006>;
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&wifi1 {
-	status = "okay";
-	nvmem-cell-names = "pre-calibration", "mac-address";
-	nvmem-cells = <&precal_art_5000>, <&macaddr_art_5006>;
-	qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb2_hs_phy {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb3_ss_phy {
-	status = "okay";
-};
-
-&usb3_hs_phy {
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-a42.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-a42.dts
index 8ce530dbd5..c117a90538 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-a42.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-a42.dts
@@ -14,10 +14,6 @@
 	compatible = "openmesh,a42";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@194b000 {
 			/* select hostmode */
 			compatible = "qcom,tcsr";
@@ -43,14 +39,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -103,6 +91,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts
index ceaa1edd45..f2e2ed3f7f 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts
@@ -58,17 +58,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -97,28 +86,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -323,10 +303,30 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cap-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cap-ac.dts
index 388b2dd590..b061428bb3 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cap-ac.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cap-ac.dts
@@ -28,10 +28,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -54,14 +50,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -118,6 +106,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cs-w3-wd1200g-eup.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cs-w3-wd1200g-eup.dts
index c388ceca27..8d09bfd0b7 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cs-w3-wd1200g-eup.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-cs-w3-wd1200g-eup.dts
@@ -18,18 +18,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <5000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -53,14 +41,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -96,6 +76,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -245,6 +237,14 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <5000>;
+};
+
 &gmac {
 	status = "okay";
 	nvmem-cells = <&macaddr_art_0>;
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-dap-2610.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-dap-2610.dts
index fef549035d..df5d9331a1 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-dap-2610.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-dap-2610.dts
@@ -35,18 +35,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		rng@22000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -76,6 +64,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp1_spi1 {
 	pinctrl-0 = <&spi_0_pins>;
 	pinctrl-names = "default";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts
index 50e7f3d4e0..e80a540244 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts
@@ -18,14 +18,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -49,22 +41,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -94,6 +70,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp1_uart1 {
 	pinctrl-0 = <&serial_pins>;
 	pinctrl-names = "default";
@@ -104,6 +92,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
@@ -307,6 +299,14 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&usb2 {
+	status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts
index e9d4775fd8..52a96eae98 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts
@@ -11,14 +11,6 @@
 	compatible = "engenius,eap1300";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -36,14 +28,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -95,6 +79,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -200,8 +196,13 @@
 				reg = <0x190000 0x1dc0000>;
 			};
 			partition9@1f50000 {
+				compatible = "u-boot,env";
 				label = "u-boot-env";
 				reg = <0x01f50000 0x00010000>;
+
+				macaddr_ubootenv_ethaddr: ethaddr {
+					#nvmem-cell-cells = <1>;
+				};
 			};
 			partition10@1f60000 {
 				label = "userconfig";
@@ -221,16 +222,39 @@
 	status = "okay";
 };
 
+&switch {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
+&swport5 {
+	status = "okay";
+	label = "lan";
+	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
+};
+
+&gmac {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_1000>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
+	nvmem-cells = <&precal_art_1000>, <&macaddr_ubootenv_ethaddr 1>;
 	qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
 };
 
 &wifi1 {
 	status = "okay";
-	nvmem-cell-names = "pre-calibration";
-	nvmem-cells = <&precal_art_5000>;
+	nvmem-cell-names = "pre-calibration", "mac-address";
+	nvmem-cells = <&precal_art_5000>, <&macaddr_ubootenv_ethaddr 2>;
 	qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts
index e74d110b3d..777788c59a 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts
@@ -56,10 +56,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -88,28 +84,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &tlmm {
@@ -325,10 +312,23 @@
 	qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
 };
 
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
 
-&usb2_hs_phy {
+&usb3 {
 	status = "okay";
 };
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emd1.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emd1.dts
index bca85cf4ab..1ef63bdc98 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emd1.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emd1.dts
@@ -18,14 +18,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -43,14 +35,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -91,6 +75,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -201,6 +197,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	qcom,ath10k-calibration-variant = "EnGenius-EMD1";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts
index 701dc936f1..9d70501cb7 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts
@@ -11,14 +11,6 @@
 	compatible = "engenius,emr3500";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -36,18 +28,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2_hs_phy: hsphy@a8000 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -93,6 +73,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -206,6 +198,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ens620ext.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ens620ext.dts
index 17bac82bfe..8b75a57074 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ens620ext.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ens620ext.dts
@@ -23,10 +23,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -45,14 +41,6 @@
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
 		/*
 		 * Disable the broken restart as a workaround for the buggy
 		 * 3.0.0/3.0.1 U-boots that ship with the device.
@@ -104,6 +92,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &cryptobam {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ex61x0v2.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ex61x0v2.dtsi
index 918224607a..ca064837c8 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ex61x0v2.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ex61x0v2.dtsi
@@ -26,14 +26,6 @@
 	compatible = "netgear,ex61x0v2";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -51,14 +43,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	aliases {
@@ -157,6 +141,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -334,6 +330,10 @@
 	nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts
index 524bcbcb2b..b3617eb45e 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts
@@ -19,14 +19,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -50,22 +42,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -124,6 +100,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -252,6 +240,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &ethphy0 {
 	gpio-controller;
 	#gpio-cells = <2>;
@@ -315,10 +307,18 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts
index 5fc97d7bb2..bb197c2742 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts
@@ -27,14 +27,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -60,22 +52,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -106,10 +82,22 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
 
+&crypto {
+	status = "okay";
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -261,6 +249,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
@@ -269,6 +261,14 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts
index fa3ed8b054..07ad4d3d52 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts
@@ -28,10 +28,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -62,23 +58,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -115,6 +94,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -219,6 +210,15 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
+
 &mdio {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dtsi
index 581b939ae6..9828b4b34e 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dtsi
@@ -12,17 +12,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -53,15 +42,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
 };
 
 &tlmm {
@@ -226,6 +219,12 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-magic-2-wifi-next.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-magic-2-wifi-next.dts
index 501aed5467..293bf3d20a 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-magic-2-wifi-next.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-magic-2-wifi-next.dts
@@ -15,26 +15,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
 		gpio_export {
 			compatible = "gpio-export";
 			#size-cells = <0>;
@@ -88,6 +68,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	spi_0_pins: spi_0_pinmux {
 		mux {
@@ -234,6 +226,14 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-mf287_common.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-mf287_common.dtsi
index 3784e62d0b..961b4be56b 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-mf287_common.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-mf287_common.dtsi
@@ -59,10 +59,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -95,6 +91,10 @@
 	status = "okay";
 };
 
+&prng {
+	status = "okay";
+};
+
 &watchdog {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts
index a9e9683592..f8e24ca53d 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts
@@ -28,14 +28,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -59,47 +51,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -162,6 +113,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -306,6 +269,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
@@ -360,6 +327,39 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_port1: port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-pa1200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-pa1200.dts
index cb847e7558..a353c7f9f3 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-pa1200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-pa1200.dts
@@ -14,10 +14,6 @@
 	compatible = "plasmacloud,pa1200";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@194b000 {
 			/* select hostmode */
 			compatible = "qcom,tcsr";
@@ -43,14 +39,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -95,6 +83,18 @@
 
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts
index 38158fbfa7..e58b3378d5 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts
@@ -20,17 +20,10 @@
 		led-failsafe = &led_power;
 		led-running = &led_power;
 		led-upgrade = &led_power;
+		label-mac-device = &swport5;
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -54,33 +47,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -151,6 +117,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -270,13 +248,44 @@
 			#size-cells = <1>;
 
 			partition@0 {
-				label = "ubi";
+				compatible = "linux,ubi";
 				reg = <0x00000000 0x08000000>;
+				label = "ubi";
+
+				volumes {
+					ubi_factory: ubi-volume-factory {
+						volname = "Factory";
+					};
+				};
 			};
 		};
 	};
 };
 
+&ubi_factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		precal_factory_1000: precal@1000 {
+			reg = <0x1000 0x2f20>;
+		};
+
+		macaddr_factory_1006: macaddr@1006 {
+			reg = <0x1006 0x6>;
+		};
+
+		precal_factory_5000: precal@5000 {
+			reg = <0x5000 0x2f20>;
+		};
+
+		macaddr_factory_5006: macaddr@5006 {
+			reg = <0x5006 0x6>;
+		};
+	};
+};
+
 &blsp1_uart1 {
 	pinctrl-0 = <&serial_pins>;
 	pinctrl-names = "default";
@@ -291,8 +300,33 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
+	nvmem-cells = <&macaddr_factory_5006>;
+	nvmem-cell-names = "mac-address";
 };
 
 &switch {
@@ -317,14 +351,20 @@
 
 &swport5 {
 	status = "okay";
+	nvmem-cells = <&macaddr_factory_1006>;
+	nvmem-cell-names = "mac-address";
 };
 
 &wifi0 {
 	status = "okay";
+	nvmem-cell-names = "pre-calibration";
+	nvmem-cells = <&precal_factory_1000>;
 	qcom,ath10k-calibration-variant = "RT-AC58U";
 };
 
 &wifi1 {
 	status = "okay";
+	nvmem-cell-names = "pre-calibration";
+	nvmem-cells = <&precal_factory_5000>;
 	qcom,ath10k-calibration-variant = "RT-AC58U";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-sxtsq-5-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-sxtsq-5-ac.dts
index 252f9ad71a..23e9457f02 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-sxtsq-5-ac.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-sxtsq-5-ac.dts
@@ -28,14 +28,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -58,14 +50,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -121,6 +105,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wac510.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wac510.dts
index 9bcfab4487..f895e2c110 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wac510.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wac510.dts
@@ -24,10 +24,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -50,14 +46,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -149,6 +137,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &qpic_bam {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts
index 8ff18d92b7..5cb103b321 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts
@@ -15,15 +15,6 @@
 			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
 			status = "okay";
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
 	};
 };
 
@@ -43,3 +34,8 @@
 &usb3 {
 	status = "okay";
 };
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts
index e7f28f23cf..bf50ebfc54 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts
@@ -15,15 +15,6 @@
 			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
 			status = "okay";
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				phys = <&usb3_hs_phy>;
-				phy-names = "usb2-phy";
-			};
-		};
 	};
 };
 
@@ -43,3 +34,8 @@
 &usb3 {
 	status = "okay";
 };
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wre6606.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wre6606.dts
index 7ce0b9e359..d59c41fab1 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wre6606.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wre6606.dts
@@ -37,14 +37,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -62,14 +54,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -119,6 +103,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -244,6 +240,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts
index f3c6f34bf4..fc5a7a94aa 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts
@@ -41,10 +41,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -68,23 +64,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -282,6 +274,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
@@ -290,6 +286,10 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-a62.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-a62.dts
index 463e1e171e..d8249236f0 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-a62.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-a62.dts
@@ -14,10 +14,6 @@
 	compatible = "openmesh,a62";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@194b000 {
 			/* select hostmode */
 			compatible = "qcom,tcsr";
@@ -43,14 +39,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -103,6 +91,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts
index d1c8d798f9..3569d6e53a 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts
@@ -18,18 +18,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <1000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -53,47 +41,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	led_spi {
@@ -171,6 +118,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -344,10 +303,51 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_port1: port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <1000>;
+};
+
 &gmac {
 	status = "okay";
 
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi
index 9216a7c9f8..119ba4b7fe 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi
@@ -21,16 +21,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -57,33 +47,6 @@
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
 
-		serial@78af000 {
-			pinctrl-0 = <&serial_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
-
-		i2c@78b7000 { /* BLSP1 QUP2 */
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
 		leds {
 			compatible = "gpio-leds";
 
@@ -133,10 +96,22 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
 
+&crypto {
+	status = "okay";
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -200,22 +175,40 @@
 	};
 };
 
+&blsp1_uart1 {
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&serial_1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_i2c3 { /* BLSP1 QUP2 */
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &usb3 {
 	status = "okay";
+};
 
-	dwc3@8a00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
 
-		usb3_port1: port@1 {
-			reg = <1>;
-			#trigger-source-cells = <0>;
-		};
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
 
-		usb3_port2: port@2 {
-			reg = <2>;
-			#trigger-source-cells = <0>;
-		};
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
 	};
 };
 
@@ -230,7 +223,7 @@
 &usb2 {
 	status = "okay";
 
-	dwc3@6000000 {
+	usb@6000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
@@ -244,3 +237,9 @@
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-eap2200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-eap2200.dts
index 000acd196c..8bf86d40cd 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-eap2200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-eap2200.dts
@@ -68,24 +68,18 @@
 			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
 		};
 	};
+};
 
-	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -275,6 +269,10 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts
index a118bdf26b..2344ae7bf8 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts
@@ -22,14 +22,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -53,18 +45,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -127,6 +107,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_0_pins: serial_pinmux {
 		mux {
@@ -266,10 +258,18 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &qpic_bam {
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts
index 7d683cdf65..106c8031e3 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts
@@ -19,20 +19,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			ethphy: ethernet-phy@0 {
-				reg = <0x0>;
-			};
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -50,14 +36,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	key {
@@ -93,6 +71,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_0_pins: serial_pinmux {
 		mux {
@@ -255,6 +245,16 @@
 	qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+
+	ethphy: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
 &gmac {
 	status = "okay";
 };
@@ -273,6 +273,10 @@
 	phy-mode = "rgmii-id";
 };
 
+&qca807x {
+	status = "disabled";
+};
+
 &ethphy1 {
 	status = "disabled";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-3000.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-3000.dts
index 2555984384..e8daef63f1 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-3000.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-3000.dts
@@ -18,14 +18,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -43,14 +35,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	key {
@@ -89,6 +73,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_0_pins: serial_pinmux {
 		mux {
@@ -253,6 +249,10 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-gl-b2200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-gl-b2200.dts
index 9f645dd657..89ba523e57 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-gl-b2200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-gl-b2200.dts
@@ -24,14 +24,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -57,10 +49,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -106,6 +94,14 @@
 	};
 };
 
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &vqmmc {
 	status = "okay";
 };
@@ -356,6 +352,10 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-habanero-dvk.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-habanero-dvk.dts
index 86daa58a3f..c25b9ecf5b 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-habanero-dvk.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-habanero-dvk.dts
@@ -20,17 +20,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -61,14 +50,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -110,6 +91,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &vqmmc {
 	status = "okay";
 };
@@ -329,6 +322,12 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-hap-ac3.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-hap-ac3.dts
index 836ad44210..4a3a323b5f 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-hap-ac3.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-hap-ac3.dts
@@ -28,10 +28,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -62,14 +58,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -160,6 +148,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts
index c4e7d0b207..1577ed58bb 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts
@@ -269,7 +269,7 @@
 &usb2 {
 	status = "okay";
 
-	dwc3@6000000 {
+	usb@6000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
@@ -286,20 +286,20 @@
 
 &usb3 {
 	status = "okay";
+};
 
-	dwc3@8a00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
 
-		usb3_port1: port@1 {
-			reg = <1>;
-			#trigger-source-cells = <0>;
-		};
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
 
-		usb3_port2: port@2 {
-			reg = <2>;
-			#trigger-source-cells = <0>;
-		};
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
 	};
 };
 
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts
index 4f0eaa625b..a5b55ff421 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-lhgg-60ad.dts
@@ -42,14 +42,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -72,14 +64,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -136,6 +120,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
@@ -245,6 +241,22 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+
+	ar8035: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&qca807x {
+	status = "disabled";
+};
+
+&ethphy0 {
+	status = "disabled";
+};
+
 &ethphy1 {
 	status = "disabled";
 };
@@ -279,6 +291,6 @@
 	status = "okay";
 
 	label = "lan";
-	phy-handle = <&ethphy0>;
+	phy-handle = <&ar8035>;
 	phy-mode = "rgmii-id";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts
index 32f0473fb1..7ec3c6a9ae 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts
@@ -19,14 +19,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -44,18 +36,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -75,6 +55,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &nand {
 	pinctrl-0 = <&nand_pins>;
 	pinctrl-names = "default";
@@ -233,6 +225,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &blsp1_i2c3 {
 	pinctrl-0 = <&i2c_0_pins>;
 	pinctrl-names = "default";
@@ -342,6 +338,10 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts
index 6987515720..7c0260ec3c 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts
@@ -97,18 +97,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -134,23 +122,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -237,6 +221,14 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
 	nvmem-cell-names = "mac-address";
@@ -449,6 +441,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_ss_phy {
 	status = "okay";
 };
@@ -457,6 +453,10 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration", "mac-address";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts
index 54353cac58..a4606dd21c 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts
@@ -80,18 +80,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -117,23 +105,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -220,6 +204,14 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
 	nvmem-cell-names = "mac-address";
@@ -423,6 +415,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_ss_phy {
 	status = "okay";
 };
@@ -431,6 +427,10 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 /*
  * The MD5 sum of the board file of the MF286D is identical to the board
  * file in the OEM firmware
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts
index 61cbdba0d1..06d65b8944 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts
@@ -73,18 +73,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -110,23 +98,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -213,6 +197,14 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
 	nvmem-cell-names = "mac-address";
@@ -430,6 +422,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_ss_phy {
 	status = "okay";
 };
@@ -438,6 +434,10 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration", "mac-address";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts
index ea27defea3..e115c211aa 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts
@@ -56,10 +56,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		dma@7984000 {
-			status = "okay";
-		};
 	};
 
 	keys-repeat {
@@ -582,15 +578,15 @@
 
 	pinctrl-0 = <&usb3_pins>, <&lte_pins>;
 	pinctrl-names = "default";
+};
 
-	dwc3@8a00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
 
-		device@1 {
-			compatible = "usb1bc7,1900";
-			reg = <1>;
-		};
+	device@1 {
+		compatible = "usb1bc7,1900";
+		reg = <1>;
 	};
 };
 
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts
index 2080a34e2f..752d714393 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts
@@ -21,12 +21,6 @@
 	};
 
 	soc {
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -52,47 +46,6 @@
 			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
 			status = "okay";
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	key {
@@ -143,6 +96,10 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
 &tlmm {
 	serial_0_pins: serial_pinmux {
 		mux {
@@ -315,6 +272,12 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
@@ -337,6 +300,40 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_port1: port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-orbi.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-orbi.dtsi
index 849df64201..bd7565ac02 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-orbi.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-orbi.dtsi
@@ -16,17 +16,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -57,14 +46,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -126,6 +107,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &vqmmc {
 	status = "okay";
 };
@@ -274,6 +267,12 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-pa2200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-pa2200.dts
index ed333c4990..f87ab07416 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-pa2200.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-pa2200.dts
@@ -14,10 +14,6 @@
 	compatible = "plasmacloud,pa2200";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -35,14 +31,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -98,6 +86,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_pins: serial_pinmux {
 		mux {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi
index 90e5455b25..0463c61236 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi
@@ -19,16 +19,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -52,22 +42,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -107,6 +81,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -290,6 +276,12 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &ethphy0 {
 	qcom,single-led-1000;
 	qcom,single-led-100;
@@ -364,10 +356,18 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &vqmmc {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts
index a803999804..f83f75b464 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts
@@ -9,22 +9,20 @@
 	chosen {
 		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
 	};
-
-	soc {
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-	};
 };
 
 &usb3_hs_phy {
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&usb2 {
+	status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts
index 4d0a9132c6..9151c5d33c 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts
@@ -9,22 +9,20 @@
 	chosen {
 		bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
 	};
-
-	soc {
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-	};
 };
 
 &usb3_hs_phy {
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
+
+&usb2 {
+	status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts
index 70849d71d6..3cd8997a92 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts
@@ -23,14 +23,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -54,33 +46,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -168,6 +133,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -269,6 +246,29 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts
index e2df1d1997..7a13241b66 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts
@@ -138,14 +138,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -171,23 +163,19 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
+};
 
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
+&watchdog {
+	status = "okay";
+};
 
-		crypto@8e3a000 {
-			status = "okay";
-		};
+&prng {
+	status = "okay";
+};
 
-		watchdog@b017000 {
-			status = "okay";
-		};
-	};
+&crypto {
+	status = "okay";
 };
 
 &blsp_dma {
@@ -358,6 +346,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_ss_phy {
 	status = "okay";
 };
@@ -366,6 +358,10 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	qcom,ath10k-calibration-variant = "cellc,rtl30vw";
@@ -376,6 +372,10 @@
 	qcom,ath10k-calibration-variant = "cellc,rtl30vw";
 };
 
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi
index c7439b87ec..67d9f21f71 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi
@@ -9,18 +9,6 @@
 	compatible = "unielec,u4019","qcom,ipq4019";
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -46,43 +34,6 @@
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
 
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
 		aliases {
 			led-boot = &led_status;
 			led-failsafe = &led_status;
@@ -115,6 +66,14 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -199,10 +158,52 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+
 &usb2_hs_phy {
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_port1: port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dts
new file mode 100644
index 0000000000..70c3b561c0
--- /dev/null
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019-whw03.dtsi"
+
+/ {
+	model = "Linksys WHW03 (Velop)";
+	compatible = "linksys,whw03", "qcom,ipq4019";
+
+	// Default bootargs include rootfstype=ext4 and need to be overriden.
+	chosen {
+		bootargs-append = " rootfstype=squashfs";
+	};
+};
+
+&tlmm {
+	sd_pins: sd-pinmux {
+		pins = "gpio23", "gpio24", "gpio25", "gpio26",
+			"gpio27", "gpio28", "gpio29", "gpio30",
+			"gpio31", "gpio32";
+		function = "sdio";
+	};
+
+	i2c_0_pins: i2c-0-pinmux {
+		pins = "gpio58", "gpio59";
+		function = "blsp_i2c0";
+		bias-disable;
+	};
+
+	spi_0_pins: spi-0-pinmux {
+		pins = "gpio12", "gpio13", "gpio14", "gpio15";
+		function = "blsp_spi0";
+		bias-disable;
+	};
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+
+	reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+};
+
+&vqmmc {
+	status = "okay";
+};
+
+&sdhci {
+	status = "okay";
+	pinctrl-0 = <&sd_pins>;
+	pinctrl-names = "default";
+
+	cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+	sd-ldo-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+
+	vqmmc-supply = <&vqmmc>;
+};
+
+&wifi0 {
+	qcom,ath10k-calibration-variant = "linksys-whw03";
+};
+
+&wifi1 {
+	qcom,ath10k-calibration-variant = "linksys-whw03";
+};
+
+&wifi2 {
+	reg = <0x00000000 0 0 0 0>;
+
+	qcom,ath10k-calibration-variant = "linksys-whw03";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dtsi
new file mode 100644
index 0000000000..ce8d66680a
--- /dev/null
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03.dtsi
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		led-boot = &led_blue;
+		led-failsafe = &led_red;
+		led-running = &led_blue;
+		led-upgrade = &led_red;
+	};
+
+	soc {
+		ess-tcsr@1953000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1953000 0x1000>;
+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+		};
+
+
+		tcsr@1949000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1949000 0x100>;
+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+		};
+
+		tcsr@194b000 {
+			compatible = "qcom,tcsr";
+			reg = <0x194b000 0x100>;
+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+		};
+
+		tcsr@1957000 {
+			compatible = "qcom,tcsr";
+			reg = <0x1957000 0x100>;
+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pinmux {
+		mux-1 {
+			pins = "gpio6";
+			function = "mdio";
+			bias-pull-up;
+		};
+
+		mux-2 {
+			pins = "gpio7";
+			function = "mdc";
+			bias-pull-up;
+		};
+	};
+
+	serial_0_pins: serial0-pinmux {
+		pins = "gpio16", "gpio17";
+		function = "blsp_uart0";
+		bias-disable;
+	};
+
+	serial_1_pins: serial1-pinmux {
+		pins = "gpio8", "gpio9", "gpio10", "gpio11";
+		function = "blsp_uart1";
+		bias-disable;
+	};
+
+	spi_1_pins: spi-1-pinmux {
+		mux-1 {
+			pins = "gpio44", "gpio46", "gpio47";
+			function = "blsp_spi1";
+			bias-disable;
+		};
+
+		mux-2 {
+			pins = "gpio45", "gpio49";
+			function = "gpio";
+			bias-pull-up;
+			output-high;
+		};
+
+		host-interrupt {
+			pins = "gpio42";
+			function = "gpio";
+			input;
+		};
+	};
+
+	wifi_0_pins: wifi0-pinmux {
+		pins = "gpio52";
+		function = "gpio";
+		drive-strength = <6>;
+		bias-pull-up;
+		output-high;
+	};
+
+	zigbee-0 {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_HIGH>;
+		bias-disable;
+		output-low;
+	};
+
+	zigbee-1 {
+		gpio-hog;
+		gpios = <50 GPIO_ACTIVE_HIGH>;
+		bias-disable;
+		input;
+	};
+
+	bluetooth-enable {
+		gpio-hog;
+		gpios = <32 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&ethphy0 {
+	status = "disabled";
+};
+
+&ethphy1 {
+	status = "disabled";
+};
+
+&ethphy2 {
+	status = "disabled";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&blsp_dma {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+	num-channels = <4>;
+	qcom,num-ees = <2>;
+};
+
+&crypto {
+	status = "okay";
+};
+
+&blsp1_uart1 {
+	status = "okay";
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+};
+
+&blsp1_uart2 {
+	status = "okay";
+	pinctrl-0 = <&serial_1_pins>;
+	pinctrl-names = "default";
+
+	bluetooth {
+		compatible = "csr,8811";
+
+		enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&blsp1_spi2 {
+	status = "okay";
+	pinctrl-0 = <&spi_1_pins>;
+	pinctrl-names = "default";
+
+	cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+
+	zigbee@0 {
+		compatible = "silabs,em3581";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <12000000>;
+	};
+};
+
+&blsp1_i2c3 {
+	status = "okay";
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+
+	// RGB LEDs
+	pca9633: led-controller@62 {
+		compatible = "nxp,pca9633";
+		nxp,hw-blink;
+		reg = <0x62>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led_red: red@0 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_INDICATOR;
+			reg = <0>;
+		};
+
+		led_green: green@1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			reg = <1>;
+		};
+
+		led_blue: blue@2 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_INDICATOR;
+			reg = <2>;
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
+	clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi2: wifi@1,0 {
+			compatible = "qcom,ath10k";
+		};
+	};
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&gmac {
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+};
+
+&swport4 {
+	status = "okay";
+	label = "lan";
+};
+
+&swport5 {
+	status = "okay";
+	label = "wan";
+};
+
+&wifi0 {
+	status = "okay";
+	pinctrl-0 = <&wifi_0_pins>;
+	pinctrl-names = "default";
+
+	qcom,coexist-support = <1>;
+	qcom,coexist-gpio-pin = <52>;
+};
+
+&wifi1 {
+	status = "okay";
+
+	ieee80211-freq-limit = <5170000 5330000>;
+};
+
+&wifi2 {
+	status = "okay";
+
+	ieee80211-freq-limit = <5490000 5835000>;
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03v2.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03v2.dts
index b76c52cd0a..d6aaf93b29 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03v2.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-whw03v2.dts
@@ -1,112 +1,29 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
+#include "qcom-ipq4019-whw03.dtsi"
 
 / {
 	model = "Linksys WHW03 V2 (Velop)";
 	compatible = "linksys,whw03v2", "qcom,ipq4019";
 
-	aliases {
-		led-boot = &led_blue;
-		led-failsafe = &led_red;
-		led-running = &led_blue;
-		led-upgrade = &led_red;
-	};
-
-	// The arguments rootfstype and ro are needed
-	// to override the default bootargs
+	// Default bootargs include rootfstype=ext4 and need to be overriden.
 	chosen {
 		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
 		stdout-path = &blsp1_uart1;
 	};
-
-	soc {
-		ess-tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-	};
-
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
 };
 
-
 &tlmm {
-	mdio_pins: mdio-pinmux {
-		mux-1 {
-			pins = "gpio6";
-			function = "mdio";
-			bias-pull-up;
-		};
-
-		mux-2 {
-			pins = "gpio7";
-			function = "mdc";
-			bias-pull-up;
-		};
-	};
-
 	i2c_0_pins: i2c-0-pinmux {
-		mux {
-			function = "blsp_i2c0";
-			pins = "gpio20", "gpio21";
-			bias-disable;
-		};
-	};
-
-	serial_0_pins: serial0-pinmux {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	serial_1_pins: serial1-pinmux {
-		mux {
-			pins = "gpio8", "gpio9", "gpio10", "gpio11";
-			function = "blsp_uart1";
-			bias-disable;
-		};
+		pins = "gpio20", "gpio21";
+		function = "blsp_i2c0";
+		bias-disable;
 	};
 
 	spi_0_pins: spi-0-pinmux {
 		mux {
-			function = "blsp_spi0";
 			pins = "gpio13", "gpio14", "gpio15";
+			function = "blsp_spi0";
 			drive-strength = <12>;
 			bias-disable;
 		};
@@ -118,55 +35,13 @@
 			output-high;
 		};
 	};
+};
 
-	spi_1_pins: spi-1-pinmux {
-		mux-1 {
-			function = "blsp_spi1";
-			pins = "gpio44", "gpio46","gpio47";
-			bias-disable;
-		};
-
-		mux-2 {
-			pins = "gpio31", "gpio45", "gpio49";
-			function = "gpio";
-			bias-pull-up;
-			output-high;
-		};
-
-		host-interrupt {
-			pins = "gpio42";
-			function = "gpio";
-			input;
-		};
-	};
-
-	wifi_0_pins: wifi0-pinmux {
-		btcoexist {
-			bias-pull-up;
-			drive-strength = <6>;
-			function = "gpio";
-			output-high;
-			pins = "gpio52";
-		};
-	};
-
-	zigbee-0 {
-		gpio-hog;
-		gpios = <29 GPIO_ACTIVE_HIGH>;
-		bias-disable;
-		output-low;
-	};
-
-	zigbee-1 {
-		gpio-hog;
-		gpios = <50 GPIO_ACTIVE_HIGH>;
-		bias-disable;
-		input;
-	};
-
-	bluetooth-enable {
-		gpio-hog;
-		gpios = <32 GPIO_ACTIVE_HIGH>;
+&spi_1_pins {
+	mux-wake {
+		pins = "gpio31";
+		function = "gpio";
+		bias-pull-up;
 		output-high;
 	};
 };
@@ -175,19 +50,8 @@
 	status = "okay";
 	pinctrl-0 = <&mdio_pins>;
 	pinctrl-names = "default";
-	phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-};
-
-&ethphy0 {
-	status = "disabled";
-};
 
-&ethphy1 {
-	status = "disabled";
-};
-
-&ethphy2 {
-	status = "disabled";
+	phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
 };
 
 &ethphy3 {
@@ -202,98 +66,6 @@
 	reg = <0x1d>;
 };
 
-&watchdog {
-	status = "okay";
-};
-
-&prng {
-	status = "okay";
-};
-
-&blsp_dma {
-	status = "okay";
-};
-
-&cryptobam {
-	num-channels = <4>;
-	qcom,num-ees = <2>;
-
-	status = "okay";
-};
-
-&crypto {
-	status = "okay";
-};
-
-&blsp1_uart1 {
-	status = "okay";
-	pinctrl-0 = <&serial_0_pins>;
-	pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
-	status = "okay";
-	pinctrl-0 = <&serial_1_pins>;
-	pinctrl-names = "default";
-
-	bluetooth {
-		compatible = "csr,8811";
-
-		enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&blsp1_spi2 {
-	pinctrl-0 = <&spi_1_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
-	zigbee@0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "silabs,em3581";
-		reg = <0>;
-		spi-max-frequency = <12000000>;
-	};
-};
-
-&blsp1_i2c3 {
-	pinctrl-0 = <&i2c_0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	// RGB LEDs
-	pca9633: led-controller@62 {
-		compatible = "nxp,pca9633";
-		nxp,hw-blink;
-		reg = <0x62>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led_red: red@0 {
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <0>;
-		};
-
-		led_green: green@1 {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <1>;
-		};
-
-		led_blue: blue@2 {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_INDICATOR;
-			reg = <2>;
-		};
-	};
-};
-
 &usb3_ss_phy {
 	status = "okay";
 };
@@ -430,63 +202,17 @@
 	};
 };
 
-&pcie0 {
-	status = "okay";
-
-	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
-	wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
-	clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&qpic_bam {
-	status = "okay";
-};
-
-&gmac {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
 &swport4 {
-	status = "okay";
-	label = "lan";
-
 	nvmem-cell-names = "mac-address";
 	nvmem-cells = <&macaddr_gmac1>;
 };
 
 &swport5 {
-	status = "okay";
-	label = "wan";
-
 	nvmem-cell-names = "mac-address";
 	nvmem-cells = <&macaddr_gmac0 0>;
 };
 
 &wifi0 {
-	pinctrl-0 = <&wifi_0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	qcom,coexist-support = <1>;
-	qcom,coexist-gpio-pin = <0x34>;
-
 	qcom,ath10k-calibration-variant = "linksys-whw03v2";
 
 	nvmem-cell-names = "pre-calibration", "mac-address";
@@ -494,9 +220,6 @@
 };
 
 &wifi1 {
-	status = "okay";
-
-	ieee80211-freq-limit = <5170000 5330000>;
 	qcom,ath10k-calibration-variant = "linksys-whw03v2";
 
 	nvmem-cell-names = "pre-calibration", "mac-address";
@@ -504,9 +227,8 @@
 };
 
 &wifi2 {
-	status = "okay";
+	reg = <0x00010000 0 0 0 0>;
 
-	ieee80211-freq-limit = <5490000 5835000>;
 	qcom,ath10k-calibration-variant = "linksys-whw03v2";
 
 	nvmem-cell-names = "pre-calibration", "mac-address";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts
index 2dc4544433..40819fd603 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts
@@ -53,209 +53,6 @@
 	};
 
 	soc {
-		pinctrl@1000000 {
-			mdio_pins: mdio_pinmux {
-				mux_1 {
-					pins = "gpio6";
-					function = "mdio";
-					bias-pull-up;
-				};
-
-				mux_2 {
-					pins = "gpio7";
-					function = "mdc";
-					bias-pull-up;
-				};
-			};
-
-			serial_0_pins: serial_pinmux {
-				mux {
-					pins = "gpio16", "gpio17";
-					function = "blsp_uart0";
-					bias-disable;
-				};
-			};
-
-			serial_1_pins: serial1_pinmux {
-				mux {
-					pins = "gpio8", "gpio9", "gpio10", "gpio11";
-					function = "blsp_uart1";
-					bias-disable;
-				};
-			};
-
-			spi_0_pins: spi_0_pinmux {
-				pinmux {
-					function = "blsp_spi0";
-					pins = "gpio13", "gpio14", "gpio15";
-					bias-disable;
-				};
-
-				pinmux_cs {
-					function = "gpio";
-					pins = "gpio12";
-					bias-disable;
-					output-high;
-				};
-			};
-
-			i2c_0_pins: i2c_0_pinmux {
-				mux {
-					pins = "gpio20", "gpio21";
-					function = "blsp_i2c0";
-					bias-disable;
-				};
-			};
-
-			nand_pins: nand_pins {
-				pullups {
-					pins = "gpio52", "gpio53", "gpio58", "gpio59";
-					function = "qpic";
-					bias-pull-up;
-				};
-
-				pulldowns {
-					pins = "gpio54", "gpio55", "gpio56",
-					"gpio57", "gpio60", "gpio61",
-					"gpio62", "gpio63", "gpio64",
-					"gpio65", "gpio66", "gpio67",
-					"gpio68", "gpio69";
-					function = "qpic";
-					bias-pull-down;
-				};
-			};
-
-			led_0_pins: led0_pinmux {
-				mux_1 {
-					pins = "gpio36";
-					function = "led0";
-					bias-pull-down;
-				};
-				mux_2 {
-					pins = "gpio40";
-					function = "led4";
-					bias-pull-down;
-				};
-			};
-		};
-
-		blsp_dma: dma@7884000 {
-			status = "okay";
-		};
-
-		spi_0: spi@78b5000 {
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-			cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
-			num-cs = <2>;
-
-			flash0@0 {
-				reg = <0>;
-				compatible = "jedec,spi-nor";
-				spi-max-frequency = <24000000>;
-				broken-flash-reset;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "0:SBL1";
-						reg = <0x000000 0x040000>;
-						read-only;
-					};
-
-					partition@40000 {
-						label = "0:MIBIB";
-						reg = <0x040000 0x020000>;
-						read-only;
-					};
-
-					partition@60000 {
-						label = "0:QSEE";
-						reg = <0x060000 0x060000>;
-						read-only;
-					};
-
-					partition@c0000 {
-						label = "0:CDT";
-						reg = <0x0c0000 0x010000>;
-						read-only;
-					};
-
-					partition@d0000 {
-						label = "0:DDRPARAMS";
-						reg = <0x0d0000 0x010000>;
-						read-only;
-					};
-
-					partition@e0000 {
-						label = "u-boot-env";
-						reg = <0x0e0000 0x010000>;
-					};
-
-					partition@f0000 {
-						label = "u-boot";
-						reg = <0x0f0000 0x080000>;
-						read-only;
-					};
-
-					partition@170000 {
-						label = "0:ART";
-						reg = <0x170000 0x010000>;
-						read-only;
-
-						nvmem-layout {
-							compatible = "fixed-layout";
-							#address-cells = <1>;
-							#size-cells = <1>;
-
-							precal_art_1000: precal@1000 {
-								reg = <0x1000 0x2f20>;
-							};
-
-							precal_art_5000: precal@5000 {
-								reg = <0x5000 0x2f20>;
-							};
-						};
-					};
-				};
-			};
-
-			nand@1 {
-				reg = <1>;
-				status = "okay";
-				compatible = "spi-nand";
-				spi-max-frequency = <24000000>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					/* The device has 128MB, but we can only address
-					 * 64MB because of the bootloader's default settings.
-					 * This is due to the old mt29f driver,
-					 * which detected the deivce with only 64MB
-					 */
-					partition@0 {
-						label = "ubi";
-						reg = <0x0000000 0x4000000>;
-					};
-				};
-			};
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <5000>;
-		};
-
 		tcsr@194b000 {
 			/* select hostmode */
 			compatible = "qcom,tcsr";
@@ -281,85 +78,288 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
+	};
 
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-		};
+	keys {
+		compatible = "gpio-keys";
 
-		serial@78af000 {
-			pinctrl-0 = <&serial_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
+		reset {
+			label = "reset";
+			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
 		};
+	};
+};
 
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
+&tlmm {
+	mdio_pins: mdio_pinmux {
+		mux_1 {
+			pins = "gpio6";
+			function = "mdio";
+			bias-pull-up;
 		};
 
-		usb3_ss_phy: ssphy@9a000 {
-			status = "okay";
+		mux_2 {
+			pins = "gpio7";
+			function = "mdc";
+			bias-pull-up;
 		};
+	};
 
-		usb3_hs_phy: hsphy@a6000 {
-			status = "okay";
+	serial_0_pins: serial_pinmux {
+		mux {
+			pins = "gpio16", "gpio17";
+			function = "blsp_uart0";
+			bias-disable;
 		};
+	};
 
-		usb3: usb3@8af8800 {
-			status = "okay";
+	serial_1_pins: serial1_pinmux {
+		mux {
+			pins = "gpio8", "gpio9", "gpio10", "gpio11";
+			function = "blsp_uart1";
+			bias-disable;
 		};
+	};
 
-		usb2_hs_phy: hsphy@a8000 {
-			status = "okay";
+	spi_0_pins: spi_0_pinmux {
+		pinmux {
+			function = "blsp_spi0";
+			pins = "gpio13", "gpio14", "gpio15";
+			bias-disable;
 		};
 
-		usb2: usb2@60f8800 {
-			status = "okay";
+		pinmux_cs {
+			function = "gpio";
+			pins = "gpio12";
+			bias-disable;
+			output-high;
 		};
+	};
 
-		cryptobam: dma@8e04000 {
-			status = "okay";
+	i2c_0_pins: i2c_0_pinmux {
+		mux {
+			pins = "gpio20", "gpio21";
+			function = "blsp_i2c0";
+			bias-disable;
 		};
+	};
 
-		crypto@8e3a000 {
-			status = "okay";
+	nand_pins: nand_pins {
+		pullups {
+			pins = "gpio52", "gpio53", "gpio58", "gpio59";
+			function = "qpic";
+			bias-pull-up;
 		};
 
-		watchdog@b017000 {
-			status = "okay";
+		pulldowns {
+			pins = "gpio54", "gpio55", "gpio56",
+			"gpio57", "gpio60", "gpio61",
+			"gpio62", "gpio63", "gpio64",
+			"gpio65", "gpio66", "gpio67",
+			"gpio68", "gpio69";
+			function = "qpic";
+			bias-pull-down;
 		};
+	};
 
-		qpic_bam: dma@7984000 {
-			status = "okay";
+	led_0_pins: led0_pinmux {
+		mux_1 {
+			pins = "gpio36";
+			function = "led0";
+			bias-pull-down;
 		};
-
-		pcie0: pci@40000000 {
-			status = "okay";
-			perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
-			wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+		mux_2 {
+			pins = "gpio40";
+			function = "led4";
+			bias-pull-down;
 		};
 	};
+};
 
-	keys {
-		compatible = "gpio-keys";
+&blsp_dma {
+	status = "okay";
+};
 
-		reset {
-			label = "reset";
-			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
+&blsp1_uart1 {
+	pinctrl-0 = <&serial_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&serial_1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_i2c3 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&blsp1_spi1 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
+	num-cs = <2>;
+
+	flash0@0 {
+		reg = <0>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <24000000>;
+		broken-flash-reset;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:SBL1";
+				reg = <0x000000 0x040000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "0:MIBIB";
+				reg = <0x040000 0x020000>;
+				read-only;
+			};
+
+			partition@60000 {
+				label = "0:QSEE";
+				reg = <0x060000 0x060000>;
+				read-only;
+			};
+
+			partition@c0000 {
+				label = "0:CDT";
+				reg = <0x0c0000 0x010000>;
+				read-only;
+			};
+
+			partition@d0000 {
+				label = "0:DDRPARAMS";
+				reg = <0x0d0000 0x010000>;
+				read-only;
+			};
+
+			partition@e0000 {
+				label = "u-boot-env";
+				reg = <0x0e0000 0x010000>;
+			};
+
+			partition@f0000 {
+				label = "u-boot";
+				reg = <0x0f0000 0x080000>;
+				read-only;
+			};
+
+			partition@170000 {
+				label = "0:ART";
+				reg = <0x170000 0x010000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					precal_art_1000: precal@1000 {
+						reg = <0x1000 0x2f20>;
+					};
+
+					precal_art_5000: precal@5000 {
+						reg = <0x5000 0x2f20>;
+					};
+				};
+			};
+		};
+	};
+
+	nand@1 {
+		reg = <1>;
+		status = "okay";
+		compatible = "spi-nand";
+		spi-max-frequency = <24000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* The device has 128MB, but we can only address
+			 * 64MB because of the bootloader's default settings.
+			 * This is due to the old mt29f driver,
+			 * which detected the deivce with only 64MB
+			 */
+			partition@0 {
+				label = "ubi";
+				reg = <0x0000000 0x4000000>;
+			};
 		};
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&usb3_ss_phy {
+	status = "okay";
+};
+
+&usb3_hs_phy {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb2_hs_phy {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
 &nand {
 	pinctrl-0 = <&nand_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };
 
+&pcie0 {
+	status = "okay";
+	perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <5000>;
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts
index 00b5897b7d..ab985dfce1 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts
@@ -36,10 +36,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -64,18 +60,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -168,6 +152,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	serial_0_pins: serial0_pinmux {
 		mux {
@@ -470,3 +466,7 @@
 &usb3_hs_phy {
 	status = "okay";
 };
+
+&usb3 {
+	status = "okay";
+};
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi
index fe3650ca58..b494d0ab1c 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi
@@ -18,19 +18,6 @@
 	};
 
 	soc {
-
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -56,43 +43,6 @@
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
 
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
 		leds {
 			compatible = "gpio-leds";
 			pinctrl-0 = <&led_pins>;
@@ -117,6 +67,14 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -201,10 +159,51 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
 &usb2_hs_phy {
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi
index 141ea60442..ae2d88da93 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi
@@ -27,14 +27,6 @@
 
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -58,47 +50,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-
-			dwc3@6000000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb2_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-
-			dwc3@8a00000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				usb3_port1: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <0>;
-				};
-
-				usb3_port2: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <0>;
-				};
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	regulator-usb-vbus {
@@ -112,6 +63,17 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
 
 &blsp_dma {
 	status = "okay";
@@ -289,6 +251,20 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+
+	usb@6000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb2_port1: port@1 {
+			reg = <1>;
+			#trigger-source-cells = <0>;
+		};
+	};
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
@@ -297,6 +273,29 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	usb3_port1: port@1 {
+		reg = <1>;
+		#trigger-source-cells = <0>;
+	};
+
+	usb3_port2: port@2 {
+		reg = <2>;
+		#trigger-source-cells = <0>;
+	};
+};
+
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4028-wpj428.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4028-wpj428.dts
index 88bcbb3101..517d691d10 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4028-wpj428.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4028-wpj428.dts
@@ -35,18 +35,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		tcsr@194b000 {
 			/* select hostmode */
 			compatible = "qcom,tcsr";
@@ -72,14 +60,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -118,6 +98,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &tlmm {
 	mdio_pins: mdio_pinmux {
 		mux_1 {
@@ -259,6 +251,14 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts
index 41b42e8f58..823431dcf1 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts
@@ -22,19 +22,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <2000>;
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -63,37 +50,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			tpm@29 {
-				/* No Driver */
-				compatible = "atmel,at97sc3203";
-				reg = <0x29>;
-				read-only;
-			};
-
-			power-monitor@40 {
-				/* No driver */
-				compatible = "isl,isl28022";
-				reg = <0x40>;
-			};
-		};
 	};
 
 	leds {
@@ -143,6 +99,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -218,7 +186,7 @@
 			pins = "gpio20", "gpio21";
 			function = "blsp_i2c0";
 			drive-strength = <4>;
-			bias-disable;
+			bias-pull-up;
 		};
 	};
 
@@ -246,6 +214,28 @@
 	};
 };
 
+&blsp1_i2c3 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tpm@29 {
+		/* No Driver */
+		compatible = "atmel,at97sc3203";
+		reg = <0x29>;
+		read-only;
+	};
+
+	power-monitor@40 {
+		/* No driver */
+		/* Device also replies on address 0x3f, see   */
+		/* ISL28022 datasheet, "Broadcast Addressing" */
+		compatible = "isl,isl28022";
+		reg = <0x40>;
+	};
+};
+
 &blsp1_spi1 {
 	pinctrl-0 = <&spi_0_pins>;
 	pinctrl-names = "default";
@@ -362,7 +352,9 @@
 					#size-cells = <1>;
 
 					macaddr_mfginfo_1d: macaddr@1d {
+						compatible = "mac-base";
 						reg = <0x1d 0x6>;
+						#nvmem-cell-cells = <1>;
 					};
 
 					macaddr_mfginfo_45: macaddr@45 {
@@ -428,12 +420,33 @@
 	};
 };
 
-&usb2_hs_phy {
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc {
+	phys = <&usb3_hs_phy>;
+	phy-names = "usb2-phy";
+};
+
+&usb3_hs_phy {
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+
+	reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2000>;
+};
+
 &gmac {
 	status = "okay";
+
+	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_mfginfo_1d 1>;
 };
 
 &switch {
@@ -462,6 +475,8 @@
 	status = "okay";
 
 	label = "wan";
+	nvmem-cell-names = "mac-address";
+	nvmem-cells = <&macaddr_mfginfo_1d 0>;
 };
 
 &wifi0 {
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-365.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-365.dts
index 3477dace72..6df788a745 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-365.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-365.dts
@@ -67,7 +67,7 @@
 	};
 };
 
-&i2c_0 {
+&blsp1_i2c3 {
 	power-monitor@40 {
 		/* No driver */
 		compatible = "isl,isl28022";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi
index 4b3b682260..7f8f9be795 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-aruba-glenmorangie.dtsi
@@ -12,20 +12,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-
-			ethphy: ethernet-phy@5 {
-				reg = <0x5>;
-			};
-		};
-
 		counter@4a1000 {
 			compatible = "qcom,qca-gcnt";
 			reg = <0x4a1000 0x4>;
@@ -48,27 +34,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
-
-		i2c_0: i2c@78b7000 {
-			pinctrl-0 = <&i2c_0_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			tpm@29 {
-				/* No Driver */
-				compatible = "atmel,at97sc3203";
-				reg = <0x29>;
-				read-only;
-			};
-		};
 	};
 
 	keys {
@@ -82,6 +47,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -99,6 +76,19 @@
 	status = "okay";
 };
 
+&blsp1_i2c3 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	tpm@29 {
+		/* No Driver */
+		compatible = "atmel,at97sc3203";
+		reg = <0x29>;
+		read-only;
+	};
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -214,6 +204,16 @@
 	};
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+
+	ethphy: ethernet-phy@5 {
+		reg = <0x5>;
+	};
+};
+
 &gmac {
 	status = "okay";
 };
@@ -232,6 +232,10 @@
 	phy-mode = "rgmii-id";
 };
 
+&qca807x {
+	status = "disabled";
+};
+
 &ethphy0 {
 	status = "disabled";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts
index 13ed26d5d6..dfb639e2bb 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts
@@ -38,14 +38,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -71,22 +63,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -128,6 +104,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -275,6 +263,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
@@ -283,6 +275,14 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts
index e7236824aa..e6d74da864 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts
@@ -23,14 +23,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -56,22 +48,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		usb2@60f8800 {
-			status = "okay";
-		};
-
-		usb3@8af8800 {
-			status = "okay";
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -114,6 +90,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &vqmmc {
 	status = "okay";
 };
@@ -340,6 +328,10 @@
 	status = "okay";
 };
 
+&usb2 {
+	status = "okay";
+};
+
 &usb3_hs_phy {
 	status = "okay";
 };
@@ -348,6 +340,14 @@
 	status = "okay";
 };
 
+&usb3 {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
 &wifi0 {
 	status = "okay";
 	nvmem-cell-names = "pre-calibration";
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi
index 2b9f73eb24..3637b96d24 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi
@@ -33,16 +33,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		/* It is a 56-bit counter that supplies the count to the ARM arch
 		   timers and without upstream driver */
 		counter@4a1000 {
@@ -67,25 +57,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		serial@78b0000 {
-			pinctrl-0 = <&serial_1_pins>;
-			pinctrl-names = "default";
-			status = "okay";
-
-			bluetooth {
-				compatible = "ti,cc2650";
-				enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-			};
-		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	keys {
@@ -110,6 +81,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -120,6 +103,17 @@
 	status = "okay";
 };
 
+&blsp1_uart2 {
+	pinctrl-0 = <&serial_1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "ti,cc2650";
+		enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &cryptobam {
 	status = "okay";
 };
@@ -403,6 +397,16 @@
 	nvmem-cell-names = "mac-address";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+
+	ar8035: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
 &gmac {
 	status = "okay";
 	nvmem-cells = <&mac_address 0>;
@@ -419,14 +423,22 @@
 	status = "okay";
 
 	label = "lan";
-	phy-handle = <&ethphy1>;
+	phy-handle = <&ar8035>;
 	phy-mode = "rgmii-rxid";
 };
 
+&qca807x {
+	status = "disabled";
+};
+
 &ethphy0 {
 	status = "disabled";
 };
 
+&ethphy1 {
+	status = "disabled";
+};
+
 &ethphy2 {
 	status = "disabled";
 };
diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ws-ap3915i.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ws-ap3915i.dts
index 8794d839a8..3bf9f8c42b 100644
--- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ws-ap3915i.dts
+++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ws-ap3915i.dts
@@ -17,16 +17,6 @@
 	};
 
 	soc {
-		rng@22000 {
-			status = "okay";
-		};
-
-		mdio@90000 {
-			status = "okay";
-			pinctrl-0 = <&mdio_pins>;
-			pinctrl-names = "default";
-		};
-
 		tcsr@1949000 {
 			compatible = "qcom,tcsr";
 			reg = <0x1949000 0x100>;
@@ -44,14 +34,6 @@
 			reg = <0x1957000 0x100>;
 			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
 		};
-
-		crypto@8e3a000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "okay";
-		};
 	};
 
 	leds {
@@ -106,6 +88,18 @@
 	};
 };
 
+&watchdog {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
 &blsp_dma {
 	status = "okay";
 };
@@ -124,6 +118,12 @@
 	status = "okay";
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+};
+
 &gmac {
 	status = "okay";
 };
diff --git a/target/linux/ipq40xx/image/Makefile b/target/linux/ipq40xx/image/Makefile
index fe99d05ccb..4928e47ef6 100644
--- a/target/linux/ipq40xx/image/Makefile
+++ b/target/linux/ipq40xx/image/Makefile
@@ -5,7 +5,7 @@ define Device/Default
 	PROFILES := Default
 	KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
 	KERNEL_LOADADDR := 0x80208000
-	DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+	DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
 	DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
 	DEVICE_DTS_CONFIG := config@1
 	IMAGES := sysupgrade.bin
diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk
index 3b6d111905..5f8082c99f 100644
--- a/target/linux/ipq40xx/image/generic.mk
+++ b/target/linux/ipq40xx/image/generic.mk
@@ -3,6 +3,11 @@ DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
 DEVICE_VARS += RAS_BOARD RAS_ROOTFS_SIZE RAS_VERSION
 DEVICE_VARS += WRGG_DEVNAME WRGG_SIGNATURE
 
+define Build/netgear-fit-padding
+	./netgear-fit-padding.py $@ $@.new
+	mv $@.new $@
+endef
+
 define Device/FitImage
 	KERNEL_SUFFIX := -uImage.itb
 	KERNEL = kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb
@@ -33,8 +38,8 @@ define Device/DniImage
 	NETGEAR_BOARD_ID :=
 	NETGEAR_HW_ID :=
 	IMAGES += factory.img
-	IMAGE/factory.img := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | append-rootfs | pad-rootfs | netgear-dni
-	IMAGE/sysupgrade.bin := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | \
+	IMAGE/factory.img := append-kernel | netgear-fit-padding | append-uImage-fakehdr filesystem | append-rootfs | pad-rootfs | netgear-dni
+	IMAGE/sysupgrade.bin := append-kernel | netgear-fit-padding | append-uImage-fakehdr filesystem | \
 		append-rootfs | pad-rootfs | check-size | append-metadata
 endef
 
@@ -447,6 +452,8 @@ define Device/engenius_eap1300
 	$(call Device/FitImage)
 	DEVICE_VENDOR := EnGenius
 	DEVICE_MODEL := EAP1300
+	DEVICE_ALT0_VENDOR := EnGenius
+	DEVICE_ALT0_MODEL := EAP1300EXT
 	DEVICE_DTS_CONFIG := config@4
 	BOARD_NAME := eap1300
 	SOC := qcom-ipq4018
@@ -454,8 +461,7 @@ define Device/engenius_eap1300
 	IMAGE_SIZE := 25344k
 	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
 endef
-# Missing DSA Setup
-#TARGET_DEVICES += engenius_eap1300
+TARGET_DEVICES += engenius_eap1300
 
 define Device/engenius_eap2200
 	$(call Device/FitImage)
@@ -723,6 +729,20 @@ define Device/linksys_mr8300
 endef
 TARGET_DEVICES += linksys_mr8300
 
+define Device/linksys_whw03
+	$(call Device/FitzImage)
+	DEVICE_VENDOR := Linksys
+	DEVICE_MODEL := WHW03
+	SOC := qcom-ipq4019
+	KERNEL_SIZE := 8192k
+	IMAGE_SIZE := 131072k
+	IMAGES += factory.bin
+	IMAGE/factory.bin  := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | linksys-image type=WHW03
+	DEVICE_PACKAGES := ath10k-firmware-qca9888-ct kmod-leds-pca963x kmod-spi-dev kmod-bluetooth \
+		kmod-fs-ext4 e2fsprogs kmod-fs-f2fs mkf2fs losetup
+endef
+TARGET_DEVICES += linksys_whw03
+
 define Device/linksys_whw03v2
 	$(call Device/FitzImage)
 	DEVICE_VENDOR := Linksys
diff --git a/target/linux/ipq40xx/image/mikrotik.mk b/target/linux/ipq40xx/image/mikrotik.mk
index f0e1f1aad3..8c2c6fa08e 100644
--- a/target/linux/ipq40xx/image/mikrotik.mk
+++ b/target/linux/ipq40xx/image/mikrotik.mk
@@ -5,7 +5,7 @@ define Device/mikrotik_nor
 	KERNEL_NAME := vmlinux
 	KERNEL := kernel-bin | append-dtb-elf
 	IMAGES = sysupgrade.bin
-	IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 | \
+	IMAGE/sysupgrade.bin := append-kernel | yaffs-filesystem -L | \
 		pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
 		check-size | append-metadata
 endef
diff --git a/target/linux/ipq40xx/image/netgear-fit-padding.py b/target/linux/ipq40xx/image/netgear-fit-padding.py
new file mode 100755
index 0000000000..87c0854b5a
--- /dev/null
+++ b/target/linux/ipq40xx/image/netgear-fit-padding.py
@@ -0,0 +1,89 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: MIT
+# -*- coding: utf-8 -*-
+
+# NETGEAR EX6150v2 padding tool
+# (c) 2024 David Bauer <mail@david-bauer.net>
+
+import math
+import sys
+
+FLASH_BLOCK_SIZE = 64 * 1024
+
+
+def read_field(data, offset):
+    return data[offset + 3] | data[offset + 2] << 8 | data[offset + 1] << 16 | data[offset] << 24
+
+
+if __name__ == '__main__':
+    if len(sys.argv) != 3:
+        print('Usage: {} <input-image> <output-image>'.format(sys.argv[0]))
+        sys.exit(1)
+
+    with open(sys.argv[1], 'rb') as f:
+        data = f.read()
+
+    file_len = len(data)
+
+    # File-len in fdt header at offset 0x4
+    file_len_hdr = read_field(data, 0x4)
+    # String offset in fdt header at offset 0xc
+    str_off = read_field(data, 0xc)
+
+    print("file_len={} hdr_file_len={} str_off={}".format(file_len, file_len_hdr, str_off))
+
+    # Off to NETGEAR calculations - Taken from u-boot source (cmd_dni.c:2145)
+    #
+    # rootfs_addr = (ntohl(hdr->ih_size)/CONFIG_SYS_FLASH_SECTOR_SIZE+1) * CONFIG_SYS_FLASH_SECTOR_SIZE +
+    #               2*sizeof(image_header_t)-sizeof(image_header_t);
+    # rootfs_addr = rootfs_addr - (0x80 - mem_addr);
+
+    # NETGEAR did fuck up badly. The image uses a FIT header, while the calculation is done on a legacy header
+    # assumption. 'ih_size' matches 'off_dt_strings' of a fdt_header.
+    # From my observations, this seems to be fixed on newer bootloader versions.
+    # However, we need to be compatible with both.
+
+    # This presents a challenge: FDT_STR might end short of a block boundary, colliding with the rootfs_addr
+    #
+    # Our dirty solution:
+    #  - Move the string_table to match a block_boundary.
+    #  - Update the total file_len to end on 50% of a block boundary.
+    #
+    # This ensures all netgear calculations will be correct, regardless whether they are done based on the
+    # 'off_dt_strings' or 'totalsize' fields of a fdt header.
+
+    new_dt_strings = int((math.floor(file_len / FLASH_BLOCK_SIZE) + 2) * FLASH_BLOCK_SIZE)
+    new_image_len = int(new_dt_strings + (FLASH_BLOCK_SIZE / 2))
+    new_file_len = int(new_dt_strings + FLASH_BLOCK_SIZE - 64)
+    print(f"new_file_len={new_file_len} new_hdr_file_len={new_image_len} new_str_offset={new_dt_strings}")
+
+    # Convert data to bytearray
+    data = bytearray(data)
+
+    # Enlarge byte-array to new size
+    data.extend(bytearray(new_file_len - file_len))
+
+    # Assert that the new and old string-tables are at least 256 bytes apart.
+    # We pad by two blocks, but let's be extra sure.
+    assert new_dt_strings - str_off >= 256
+
+    # Move the string table to the new offset
+    for i in range(0, 256):
+        data[new_dt_strings + i] = data[str_off + i]
+        data[str_off + i] = 0
+
+    # Update the string offset in the header
+    data[0xc] = (new_dt_strings >> 24) & 0xFF
+    data[0xd] = (new_dt_strings >> 16) & 0xFF
+    data[0xe] = (new_dt_strings >> 8) & 0xFF
+    data[0xf] = new_dt_strings & 0xFF
+
+    # Update the file length in the header
+    data[0x4] = (new_image_len >> 24) & 0xFF
+    data[0x5] = (new_image_len >> 16) & 0xFF
+    data[0x6] = (new_image_len >> 8) & 0xFF
+    data[0x7] = new_image_len & 0xFF
+
+    # Write the new file
+    with open(sys.argv[1] + '.new', 'wb') as f:
+        f.write(data)
diff --git a/target/linux/ipq40xx/patches-6.1/001-v6.6-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch b/target/linux/ipq40xx/patches-6.1/001-v6.6-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch
deleted file mode 100644
index 87feaf79f8..0000000000
--- a/target/linux/ipq40xx/patches-6.1/001-v6.6-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From be59072c6eeb7535bf9a339fb9d5a8bfae17ac22 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:23 +0200
-Subject: [PATCH] dt-bindings: clock: qcom: ipq4019: add missing networking
- resets
-
-Add bindings for the missing networking resets found in IPQ4019 GCC.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-@@ -165,5 +165,11 @@
- #define GCC_QDSS_BCR					69
- #define GCC_MPM_BCR					70
- #define GCC_SPDM_BCR					71
-+#define ESS_MAC1_ARES					72
-+#define ESS_MAC2_ARES					73
-+#define ESS_MAC3_ARES					74
-+#define ESS_MAC4_ARES					75
-+#define ESS_MAC5_ARES					76
-+#define ESS_PSGMII_ARES					77
- 
- #endif
diff --git a/target/linux/ipq40xx/patches-6.1/002-v6.6-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch b/target/linux/ipq40xx/patches-6.1/002-v6.6-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch
deleted file mode 100644
index 70b278c803..0000000000
--- a/target/linux/ipq40xx/patches-6.1/002-v6.6-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 20014461691efc9e274c3870357152db7f091820 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:24 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq4019: add missing networking resets
-
-IPQ4019 has more networking related resets that will be required for future
-wired networking support, so lets add them.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i
- 	[GCC_TCSR_BCR] = {0x22000, 0},
- 	[GCC_MPM_BCR] = {0x24000, 0},
- 	[GCC_SPDM_BCR] = {0x25000, 0},
-+	[ESS_MAC1_ARES] = {0x1200C, 0},
-+	[ESS_MAC2_ARES] = {0x1200C, 1},
-+	[ESS_MAC3_ARES] = {0x1200C, 2},
-+	[ESS_MAC4_ARES] = {0x1200C, 3},
-+	[ESS_MAC5_ARES] = {0x1200C, 4},
-+	[ESS_PSGMII_ARES] = {0x1200C, 5},
- };
- 
- static const struct regmap_config gcc_ipq4019_regmap_config = {
diff --git a/target/linux/ipq40xx/patches-6.1/004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch b/target/linux/ipq40xx/patches-6.1/004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch
deleted file mode 100644
index ae7e9f97c0..0000000000
--- a/target/linux/ipq40xx/patches-6.1/004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Aug 2023 18:45:39 +0200
-Subject: [PATCH] firmware: qcom_scm: disable SDI if required
-
-IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
-means that WDT being asserted or just trying to reboot will hang the board
-in the debug mode and only pulling the power and repowering will help.
-Some IPQ4019 boards like Google WiFI have it enabled as well.
-
-Luckily, SDI can be disabled via an SCM call.
-
-So, lets use the boolean DT property to identify boards that have SDI
-enabled by default and use the SCM call to disable SDI during SCM probe.
-It is important to disable it as soon as possible as we might have a WDT
-assertion at any time which would then leave the board in debug mode,
-thus disabling it during SCM removal is not enough.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
-Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++
- drivers/firmware/qcom_scm.h |  1 +
- 2 files changed, 31 insertions(+)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -407,6 +407,29 @@ int qcom_scm_set_remote_state(u32 state,
- }
- EXPORT_SYMBOL(qcom_scm_set_remote_state);
- 
-+static int qcom_scm_disable_sdi(void)
-+{
-+	int ret;
-+	struct qcom_scm_desc desc = {
-+		.svc = QCOM_SCM_SVC_BOOT,
-+		.cmd = QCOM_SCM_BOOT_SDI_CONFIG,
-+		.args[0] = 1, /* Disable watchdog debug */
-+		.args[1] = 0, /* Disable SDI */
-+		.arginfo = QCOM_SCM_ARGS(2),
-+		.owner = ARM_SMCCC_OWNER_SIP,
-+	};
-+	struct qcom_scm_res res;
-+
-+	ret = qcom_scm_clk_enable();
-+	if (ret)
-+		return ret;
-+	ret = qcom_scm_call(__scm->dev, &desc, &res);
-+
-+	qcom_scm_clk_disable();
-+
-+	return ret ? : res.result[0];
-+}
-+
- static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
- {
- 	struct qcom_scm_desc desc = {
-@@ -1411,6 +1434,13 @@ static int qcom_scm_probe(struct platfor
- 
- 	__get_convention();
- 
-+
-+	/*
-+	 * Disable SDI if indicated by DT that it is enabled by default.
-+	 */
-+	if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled"))
-+		qcom_scm_disable_sdi();
-+
- 	/*
- 	 * If requested enable "download mode", from this point on warmboot
- 	 * will cause the boot stages to enter download mode, unless
---- a/drivers/firmware/qcom_scm.h
-+++ b/drivers/firmware/qcom_scm.h
-@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
- #define QCOM_SCM_SVC_BOOT		0x01
- #define QCOM_SCM_BOOT_SET_ADDR		0x01
- #define QCOM_SCM_BOOT_TERMINATE_PC	0x02
-+#define QCOM_SCM_BOOT_SDI_CONFIG	0x09
- #define QCOM_SCM_BOOT_SET_DLOAD_MODE	0x10
- #define QCOM_SCM_BOOT_SET_ADDR_MC	0x11
- #define QCOM_SCM_BOOT_SET_REMOTE_STATE	0x0a
diff --git a/target/linux/ipq40xx/patches-6.1/100-ARM-dts-qcom-ipq4019-add-label-to-SCM.patch b/target/linux/ipq40xx/patches-6.1/100-ARM-dts-qcom-ipq4019-add-label-to-SCM.patch
deleted file mode 100644
index 8b9352e6f1..0000000000
--- a/target/linux/ipq40xx/patches-6.1/100-ARM-dts-qcom-ipq4019-add-label-to-SCM.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From ea9fba16d972becc84cd2a82d25030975dc609a5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 30 Sep 2023 13:09:27 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add label to SCM
-
-Some IPQ4019 boards require SDI to be disabled by adding a property to the
-SCM node, so lets make that easy by adding a label to the SCM node.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -155,7 +155,7 @@
- 	};
- 
- 	firmware {
--		scm {
-+		scm: scm {
- 			compatible = "qcom,scm-ipq4019", "qcom,scm";
- 		};
- 	};
diff --git a/target/linux/ipq40xx/patches-6.1/104-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-6.1/104-clk-fix-apss-cpu-overclocking.patch
deleted file mode 100644
index 2de03f7ae0..0000000000
--- a/target/linux/ipq40xx/patches-6.1/104-clk-fix-apss-cpu-overclocking.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Sun, 11 Mar 2018 14:41:31 +0100
-Subject: [PATCH 2/2] clk: fix apss cpu overclocking
-
-There's an interaction issue between the clk changes:"
-clk: qcom: ipq4019: Add the apss cpu pll divider clock node
-clk: qcom: ipq4019: remove fixed clocks and add pll clocks
-" and the cpufreq-dt.
-
-cpufreq-dt is now spamming the kernel-log with the following:
-
-[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
-for freq 761142857 (-34)
-
-This only happens on certain devices like the Compex WPJ428
-and AVM FritzBox!4040. However, other devices like the Asus
-RT-AC58U and Meraki MR33 work just fine.
-
-The issue stem from the fact that all higher CPU-Clocks
-are achieved by switching the clock-parent to the P_DDRPLLAPSS
-(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
-as part of the DDR calibration.
-
-For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
-at round 533 MHz (ddrpllsdcc = 190285714 Hz).
-
-whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
-clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
-
-This patch attempts to fix the issue by modifying
-clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
-to use a new qcom_find_freq_close() function, which returns the closest
-matching frequency, instead of the next higher. This way, the SoC in
-the FB4040 (with its max clock speed of 710.4 MHz) will no longer
-try to overclock to 761 MHz.
-
-Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
- 1 file changed, 31 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
- 	.reg = 0x2f020,
- };
- 
-+
-+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
-+					     unsigned long rate)
-+{
-+	const struct freq_tbl *last = NULL;
-+
-+	for ( ; f->freq; f++) {
-+		if (rate == f->freq)
-+			return f;
-+
-+		if (f->freq > rate) {
-+			if (!last ||
-+			   (f->freq - rate) < (rate - last->freq))
-+				return f;
-+			else
-+				return last;
-+		}
-+		last = f;
-+	}
-+
-+	return last;
-+}
-+
- /*
-  * Round rate function for APSS CPU PLL Clock divider.
-  * It looks up the frequency table and returns the next higher frequency
-@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
- 	struct clk_hw *p_hw;
- 	const struct freq_tbl *f;
- 
--	f = qcom_find_freq(pll->freq_tbl, rate);
-+	f = qcom_find_freq_close(pll->freq_tbl, rate);
- 	if (!f)
- 		return -EINVAL;
- 
-@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c
- 	const struct freq_tbl *f;
- 	u32 mask;
- 
--	f = qcom_find_freq(pll->freq_tbl, rate);
-+	f = qcom_find_freq_close(pll->freq_tbl, rate);
- 	if (!f)
- 		return -EINVAL;
- 
-@@ -1304,6 +1327,7 @@ static unsigned long
- clk_cpu_div_recalc_rate(struct clk_hw *hw,
- 			unsigned long parent_rate)
- {
-+	const struct freq_tbl *f;
- 	struct clk_fepll *pll = to_clk_fepll(hw);
- 	u32 cdiv, pre_div;
- 	u64 rate;
-@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
- 	rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
- 	do_div(rate, pre_div);
- 
--	return rate;
-+	f = qcom_find_freq_close(pll->freq_tbl, rate);
-+	if (!f)
-+		return rate;
-+
-+	return f->freq;
- };
- 
- static const struct clk_ops clk_regmap_cpu_div_ops = {
diff --git a/target/linux/ipq40xx/patches-6.1/301-arm-compressed-add-appended-DTB-section.patch b/target/linux/ipq40xx/patches-6.1/301-arm-compressed-add-appended-DTB-section.patch
deleted file mode 100644
index 0448574e7e..0000000000
--- a/target/linux/ipq40xx/patches-6.1/301-arm-compressed-add-appended-DTB-section.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 30 Oct 2020 13:36:31 +0100
-Subject: [PATCH] arm: compressed: add appended DTB section
-
-This adds a appended_dtb section to the ARM decompressor
-linker script.
-
-This allows using the existing ARM zImage appended DTB support for
-appending a DTB to the raw ELF kernel.
-
-Its size is set to 1MB max to match the zImage appended DTB size limit.
-
-To use it to pass the DTB to the kernel, objcopy is used:
-
-objcopy --set-section-flags=.appended_dtb=alloc,contents \
-	--update-section=.appended_dtb=<target>.dtb vmlinux
-
-This is based off the following patch:
-https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/compressed/vmlinux.lds.S
-+++ b/arch/arm/boot/compressed/vmlinux.lds.S
-@@ -103,6 +103,13 @@ SECTIONS
- 
-   _edata = .;
- 
-+  .appended_dtb : {
-+    /* leave space for appended DTB */
-+    . += 0x100000;
-+  }
-+
-+  _edata_dtb = .;
-+
-   /*
-    * The image_end section appears after any additional loadable sections
-    * that the linker may decide to insert in the binary image.  Having
-@@ -140,4 +147,4 @@ SECTIONS
- 
-   ARM_ASSERTS
- }
--ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
-+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
diff --git a/target/linux/ipq40xx/patches-6.1/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch b/target/linux/ipq40xx/patches-6.1/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch
deleted file mode 100644
index 4939c56470..0000000000
--- a/target/linux/ipq40xx/patches-6.1/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
-From: John Thomson <git@johnthomson.fastmail.com.au>
-Date: Fri, 23 Oct 2020 19:42:36 +1000
-Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
-
-For IPQ40XX systems where the SoC watchdog is activated before linux,
-the watchdog timer may be too small for linux to finish uncompress,
-boot, and watchdog management start.
-If the watchdog is enabled, set the timeout for it to 30 seconds.
-The functionality and offsets were copied from:
-drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
-The watchdog memory address was taken from:
-arch/arm/boot/dts/qcom-ipq4019.dtsi
-
-This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
-RouterBoot bootloader.
-
-Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
----
- arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -620,6 +620,41 @@ not_relocated:	mov	r0, #0
- 		bic	r4, r4, #1
- 		blne	cache_on
- 
-+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
-+ * if it is enabled, so that there is time for kernel
-+ * to decompress, boot, and take over the watchdog.
-+ * data and functionality from drivers/watchdog/qcom-wdt.c
-+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
-+ */
-+#ifdef CONFIG_ARCH_IPQ40XX
-+watchdog_set:
-+		/* offsets:
-+		 * 0x04 reset	(=1 resets countdown)
-+		 * 0x08 enable	(=0 disables)
-+		 * 0x0c status	(=1 when SoC was reset by watchdog)
-+		 * 0x10 bark	(=timeout warning in ticks)
-+		 * 0x14 bite	(=timeout reset in ticks)
-+		 * clock rate is 1<<15 hertz
-+		 */
-+		.equ watchdog, 0x0b017000	@Store watchdog base address
-+		movw r0, #:lower16:watchdog
-+		movt r0, #:upper16:watchdog
-+		ldr r1, [r0, #0x08]	@Get enabled?
-+		cmp r1, #1		@If not enabled, do not change
-+		bne watchdog_finished
-+		mov r1, #0
-+		str r1, [r0, #0x08]	@Disable the watchdog
-+		mov r1, #1
-+		str r1, [r0, #0x04]	@Pet the watchdog
-+		mov r1, #30		@30 seconds timeout
-+		lsl r1, r1, #15		@converted to ticks
-+		str r1, [r0, #0x10]	@Set the bark timeout
-+		str r1, [r0, #0x14]	@Set the bite timeout
-+		mov r1, #1
-+		str r1, [r0, #0x08]	@Enable the watchdog
-+watchdog_finished:
-+#endif /* CONFIG_ARCH_IPQ40XX */
-+
- /*
-  * The C runtime environment should now be setup sufficiently.
-  * Set up some pointers, and start decompressing.
diff --git a/target/linux/ipq40xx/patches-6.1/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch b/target/linux/ipq40xx/patches-6.1/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch
deleted file mode 100644
index bf36164aed..0000000000
--- a/target/linux/ipq40xx/patches-6.1/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Dec 2020 13:35:35 +0100
-Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
-
-When using sdhci_msm_set_clock clock setting will fail, so lets
-use the generic sdhci_set_clock.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mmc/host/sdhci-msm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2451,7 +2451,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
- 
- static const struct sdhci_ops sdhci_msm_ops = {
- 	.reset = sdhci_msm_reset,
--	.set_clock = sdhci_msm_set_clock,
-+	.set_clock = sdhci_set_clock,
- 	.get_min_clock = sdhci_msm_get_min_clock,
- 	.get_max_clock = sdhci_msm_get_max_clock,
- 	.set_bus_width = sdhci_set_bus_width,
diff --git a/target/linux/ipq40xx/patches-6.1/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch b/target/linux/ipq40xx/patches-6.1/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch
deleted file mode 100644
index b297600171..0000000000
--- a/target/linux/ipq40xx/patches-6.1/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 9 May 2023 01:57:17 +0200
-Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
-
-comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
-current problem, we are forced to use sdhci_set_clock.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
- 1 file changed, 43 insertions(+), 43 deletions(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
- 	return SDHCI_MSM_MIN_CLOCK;
- }
- 
--/*
-- * __sdhci_msm_set_clock - sdhci_msm clock control.
-- *
-- * Description:
-- * MSM controller does not use internal divider and
-- * instead directly control the GCC clock as per
-- * HW recommendation.
-- **/
--static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
--	u16 clk;
--
--	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
--
--	if (clock == 0)
--		return;
--
--	/*
--	 * MSM controller do not use clock divider.
--	 * Thus read SDHCI_CLOCK_CONTROL and only enable
--	 * clock with no divider value programmed.
--	 */
--	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
--	sdhci_enable_clk(host, clk);
--}
--
--/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
--static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
--	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
--	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
--
--	if (!clock) {
--		host->mmc->actual_clock = msm_host->clk_rate = 0;
--		goto out;
--	}
--
--	sdhci_msm_hc_select_mode(host);
--
--	msm_set_clock_rate_for_bus_mode(host, clock);
--out:
--	__sdhci_msm_set_clock(host, clock);
--}
-+// /*
-+//  * __sdhci_msm_set_clock - sdhci_msm clock control.
-+//  *
-+//  * Description:
-+//  * MSM controller does not use internal divider and
-+//  * instead directly control the GCC clock as per
-+//  * HW recommendation.
-+//  **/
-+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// 	u16 clk;
-+
-+// 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+// 	if (clock == 0)
-+// 		return;
-+
-+// 	/*
-+// 	 * MSM controller do not use clock divider.
-+// 	 * Thus read SDHCI_CLOCK_CONTROL and only enable
-+// 	 * clock with no divider value programmed.
-+// 	 */
-+// 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-+// 	sdhci_enable_clk(host, clk);
-+// }
-+
-+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
-+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+// 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
-+
-+// 	if (!clock) {
-+// 		host->mmc->actual_clock = msm_host->clk_rate = 0;
-+// 		goto out;
-+// 	}
-+
-+// 	sdhci_msm_hc_select_mode(host);
-+
-+// 	msm_set_clock_rate_for_bus_mode(host, clock);
-+// out:
-+// 	__sdhci_msm_set_clock(host, clock);
-+// }
- 
- /*****************************************************************************\
-  *                                                                           *
diff --git a/target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch b/target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch
deleted file mode 100644
index cb06ff353c..0000000000
--- a/target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
-From: Brian Norris <computersforpeace@gmail.com>
-Date: Fri, 28 Jul 2023 12:06:23 +0200
-Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
-
-This effectively reverts upstream Linux commit 13e77747800e ("firmware:
-qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
-firmwares don't support the atomic variant.
-
-This fixes SMP support for Google WiFi.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
- drivers/firmware/qcom_scm.c        | 11 ++++++
- 2 files changed, 63 insertions(+), 10 deletions(-)
-
---- a/drivers/firmware/qcom_scm-legacy.c
-+++ b/drivers/firmware/qcom_scm-legacy.c
-@@ -13,6 +13,9 @@
- #include <linux/arm-smccc.h>
- #include <linux/dma-mapping.h>
- 
-+#include <asm/cacheflush.h>
-+#include <asm/outercache.h>
-+
- #include "qcom_scm.h"
- 
- static DEFINE_MUTEX(qcom_scm_lock);
-@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
- 	} while (res->a0 == QCOM_SCM_INTERRUPTED);
- }
- 
-+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
-+{
-+	u32 cacheline_size, ctr;
-+
-+	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
-+	cacheline_size = 4 << ((ctr >> 16) & 0xf);
-+
-+	start = round_down(start, cacheline_size);
-+	end = round_up(end, cacheline_size);
-+	outer_inv_range(start, end);
-+	while (start < end) {
-+		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
-+		     : "memory");
-+		start += cacheline_size;
-+	}
-+	dsb();
-+	isb();
-+}
-+
- /**
-  * scm_legacy_call() - Sends a command to the SCM and waits for the command to
-  * finish processing.
-@@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
- 
- 	rsp = scm_legacy_command_to_response(cmd);
- 
--	cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
--	if (dma_mapping_error(dev, cmd_phys)) {
--		kfree(cmd);
--		return -ENOMEM;
-+	if (dev) {
-+		cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-+		if (dma_mapping_error(dev, cmd_phys)) {
-+			kfree(cmd);
-+			return -ENOMEM;
-+		}
-+	} else {
-+		cmd_phys = virt_to_phys(cmd);
-+		__cpuc_flush_dcache_area(cmd, alloc_len);
-+		outer_flush_range(cmd_phys, cmd_phys + alloc_len);
- 	}
- 
- 	smc.args[0] = 1;
-@@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
- 		goto out;
- 
- 	do {
--		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
--					sizeof(*rsp), DMA_FROM_DEVICE);
-+		if (dev) {
-+			dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
-+						cmd_len, sizeof(*rsp),
-+						DMA_FROM_DEVICE);
-+		} else {
-+			unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
-+					      cmd_len;
-+			qcom_scm_inv_range(start, start + sizeof(*rsp));
-+		}
- 	} while (!rsp->is_complete);
- 
--	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
--				le32_to_cpu(rsp->buf_offset),
--				resp_len, DMA_FROM_DEVICE);
-+	if (dev) {
-+		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-+					le32_to_cpu(rsp->buf_offset),
-+					resp_len, DMA_FROM_DEVICE);
-+	} else {
-+		unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
-+				      le32_to_cpu(rsp->buf_offset);
-+		qcom_scm_inv_range(start, start + resp_len);
-+	}
- 
- 	if (res) {
- 		res_buf = scm_legacy_get_response_buffer(rsp);
-@@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
- 			res->result[i] = le32_to_cpu(res_buf[i]);
- 	}
- out:
--	dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
-+	if (dev)
-+		dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
- 	kfree(cmd);
- 	return ret;
- }
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -312,6 +312,17 @@ static int qcom_scm_set_boot_addr(void *
- 	desc.args[0] = flags;
- 	desc.args[1] = virt_to_phys(entry);
- 
-+	/*
-+	 * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
-+	 * require ugly DMA invalidation support that was dropped upstream a
-+	 * while ago. For more info, see:
-+	 *
-+	 *  [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
-+	 *  https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
-+	 */
-+	if (of_machine_is_compatible("google,wifi"))
-+		return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
-+
- 	return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
- }
- 
diff --git a/target/linux/ipq40xx/patches-6.1/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch b/target/linux/ipq40xx/patches-6.1/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch
deleted file mode 100644
index 91919b2894..0000000000
--- a/target/linux/ipq40xx/patches-6.1/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
-Date: Wed, 20 Apr 2022 12:08:38 +0200
-Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
- NAND flash
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
-has 128 bytes OOB. This adds a static NAND ID entry to correct this.
-
-Tested on FRITZ!Box 7530 flashed with OpenWrt.
-
-Signed-off-by: Andreas Böhler <dev@aboehler.at>
-(changed id_len to 8, added comment about possible counterfeits)
----
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
- 	{"TC58NVG0S3E 1G 3.3V 8-bit",
- 		{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
- 		  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
-+	{"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
-+		{ .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
-+		  SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
- 	{"TC58NVG2S0F 4G 3.3V 8-bit",
- 		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
- 		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
diff --git a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
deleted file mode 100644
index be12bfcd21..0000000000
--- a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
+++ /dev/null
@@ -1,2025 +0,0 @@
-From 76e25c1f46456416ba5358be8a0677f1ab8196b6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:48 +0100
-Subject: [PATCH] net: ipqess: introduce the Qualcomm IPQESS driver
-
-The Qualcomm IPQESS controller is a simple 1G Ethernet controller found
-on the IPQ4019 chip. This controller has some specificities, in that the
-IPQ4019 platform that includes that controller also has an internal
-switch, based on the QCA8K IP.
-
-It is connected to that switch through an internal link, and doesn't
-expose directly any external interface, hence it only supports the
-PHY_INTERFACE_MODE_INTERNAL for now.
-
-It has 16 RX and TX queues, with a very basic RSS fanout configured at
-init time.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- MAINTAINERS                                   |    7 +
- drivers/net/ethernet/qualcomm/Kconfig         |   11 +
- drivers/net/ethernet/qualcomm/Makefile        |    2 +
- drivers/net/ethernet/qualcomm/ipqess/Makefile |    8 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 1246 +++++++++++++++++
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h |  518 +++++++
- .../ethernet/qualcomm/ipqess/ipqess_ethtool.c |  164 +++
- 7 files changed, 1956 insertions(+)
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/Makefile
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.c
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.h
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17075,6 +17075,13 @@ L:	netdev@vger.kernel.org
- S:	Maintained
- F:	drivers/net/ethernet/qualcomm/emac/
- 
-+QUALCOMM IPQESS ETHERNET DRIVER
-+M:	Maxime Chevallier <maxime.chevallier@bootlin.com>
-+L:	netdev@vger.kernel.org
-+S:	Maintained
-+F:	Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
-+F:	drivers/net/ethernet/qualcomm/ipqess/
-+
- QUALCOMM ETHQOS ETHERNET DRIVER
- M:	Vinod Koul <vkoul@kernel.org>
- R:	Bhupesh Sharma <bhupesh.sharma@linaro.org>
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -60,6 +60,17 @@ config QCOM_EMAC
- 	  low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- 	  Precision Clock Synchronization Protocol.
- 
-+config QCOM_IPQ4019_ESS_EDMA
-+	tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
-+	depends on (OF && ARCH_QCOM) || COMPILE_TEST
-+	select PHYLINK
-+	help
-+	  This driver supports the Qualcomm Atheros IPQ40xx built-in
-+	  ESS EDMA ethernet controller.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called ipqess.
-+
- source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
- 
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -11,4 +11,6 @@ qcauart-objs := qca_uart.o
- 
- obj-y += emac/
- 
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipqess/
-+
- obj-$(CONFIG_RMNET) += rmnet/
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+#
-+# Makefile for the IPQ ESS driver
-+#
-+
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
-+
-+ipq_ess-objs := ipqess.o ipqess_ethtool.o
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -0,0 +1,1246 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2014 - 2017, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/if_vlan.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/phylink.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/skbuff.h>
-+#include <linux/vmalloc.h>
-+#include <net/checksum.h>
-+#include <net/ip6_checksum.h>
-+
-+#include "ipqess.h"
-+
-+#define IPQESS_RRD_SIZE		16
-+#define IPQESS_NEXT_IDX(X, Y)  (((X) + 1) & ((Y) - 1))
-+#define IPQESS_TX_DMA_BUF_LEN	0x3fff
-+
-+static void ipqess_w32(struct ipqess *ess, u32 reg, u32 val)
-+{
-+	writel(val, ess->hw_addr + reg);
-+}
-+
-+static u32 ipqess_r32(struct ipqess *ess, u16 reg)
-+{
-+	return readl(ess->hw_addr + reg);
-+}
-+
-+static void ipqess_m32(struct ipqess *ess, u32 mask, u32 val, u16 reg)
-+{
-+	u32 _val = ipqess_r32(ess, reg);
-+
-+	_val &= ~mask;
-+	_val |= val;
-+
-+	ipqess_w32(ess, reg, _val);
-+}
-+
-+void ipqess_update_hw_stats(struct ipqess *ess)
-+{
-+	u32 *p;
-+	u32 stat;
-+	int i;
-+
-+	lockdep_assert_held(&ess->stats_lock);
-+
-+	p = (u32 *)&ess->ipqess_stats;
-+	for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+		stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_PKT_Q(i));
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+		stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_BYTE_Q(i));
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+		stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_PKT_Q(i));
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+		stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_BYTE_Q(i));
-+		*p += stat;
-+		p++;
-+	}
-+}
-+
-+static int ipqess_tx_ring_alloc(struct ipqess *ess)
-+{
-+	struct device *dev = &ess->pdev->dev;
-+	int i;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		struct ipqess_tx_ring *tx_ring = &ess->tx_ring[i];
-+		size_t size;
-+		u32 idx;
-+
-+		tx_ring->ess = ess;
-+		tx_ring->ring_id = i;
-+		tx_ring->idx = i * 4;
-+		tx_ring->count = IPQESS_TX_RING_SIZE;
-+		tx_ring->nq = netdev_get_tx_queue(ess->netdev, i);
-+
-+		size = sizeof(struct ipqess_buf) * IPQESS_TX_RING_SIZE;
-+		tx_ring->buf = devm_kzalloc(dev, size, GFP_KERNEL);
-+		if (!tx_ring->buf)
-+			return -ENOMEM;
-+
-+		size = sizeof(struct ipqess_tx_desc) * IPQESS_TX_RING_SIZE;
-+		tx_ring->hw_desc = dmam_alloc_coherent(dev, size, &tx_ring->dma,
-+						       GFP_KERNEL);
-+		if (!tx_ring->hw_desc)
-+			return -ENOMEM;
-+
-+		ipqess_w32(ess, IPQESS_REG_TPD_BASE_ADDR_Q(tx_ring->idx),
-+			   (u32)tx_ring->dma);
-+
-+		idx = ipqess_r32(ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+		idx >>= IPQESS_TPD_CONS_IDX_SHIFT; /* need u32 here */
-+		idx &= 0xffff;
-+		tx_ring->head = idx;
-+		tx_ring->tail = idx;
-+
-+		ipqess_m32(ess, IPQESS_TPD_PROD_IDX_MASK << IPQESS_TPD_PROD_IDX_SHIFT,
-+			   idx, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+		ipqess_w32(ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx), idx);
-+		ipqess_w32(ess, IPQESS_REG_TPD_RING_SIZE, IPQESS_TX_RING_SIZE);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ipqess_tx_unmap_and_free(struct device *dev, struct ipqess_buf *buf)
-+{
-+	int len = 0;
-+
-+	if (buf->flags & IPQESS_DESC_SINGLE)
-+		dma_unmap_single(dev, buf->dma,	buf->length, DMA_TO_DEVICE);
-+	else if (buf->flags & IPQESS_DESC_PAGE)
-+		dma_unmap_page(dev, buf->dma, buf->length, DMA_TO_DEVICE);
-+
-+	if (buf->flags & IPQESS_DESC_LAST) {
-+		len = buf->skb->len;
-+		dev_kfree_skb_any(buf->skb);
-+	}
-+
-+	buf->flags = 0;
-+
-+	return len;
-+}
-+
-+static void ipqess_tx_ring_free(struct ipqess *ess)
-+{
-+	int i;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		int j;
-+
-+		if (ess->tx_ring[i].hw_desc)
-+			continue;
-+
-+		for (j = 0; j < IPQESS_TX_RING_SIZE; j++) {
-+			struct ipqess_buf *buf = &ess->tx_ring[i].buf[j];
-+
-+			ipqess_tx_unmap_and_free(&ess->pdev->dev, buf);
-+		}
-+
-+		ess->tx_ring[i].buf = NULL;
-+	}
-+}
-+
-+static int ipqess_rx_buf_prepare(struct ipqess_buf *buf,
-+				 struct ipqess_rx_ring *rx_ring)
-+{
-+	memset(buf->skb->data, 0, sizeof(struct ipqess_rx_desc));
-+
-+	buf->dma = dma_map_single(rx_ring->ppdev, buf->skb->data,
-+				  IPQESS_RX_HEAD_BUFF_SIZE, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(rx_ring->ppdev, buf->dma)) {
-+		dev_kfree_skb_any(buf->skb);
-+		buf->skb = NULL;
-+		return -EFAULT;
-+	}
-+
-+	buf->length = IPQESS_RX_HEAD_BUFF_SIZE;
-+	rx_ring->hw_desc[rx_ring->head] = (struct ipqess_rx_desc *)buf->dma;
-+	rx_ring->head = (rx_ring->head + 1) % IPQESS_RX_RING_SIZE;
-+
-+	ipqess_m32(rx_ring->ess, IPQESS_RFD_PROD_IDX_BITS,
-+		   (rx_ring->head + IPQESS_RX_RING_SIZE - 1) % IPQESS_RX_RING_SIZE,
-+		   IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+
-+	return 0;
-+}
-+
-+/* locking is handled by the caller */
-+static int ipqess_rx_buf_alloc_napi(struct ipqess_rx_ring *rx_ring)
-+{
-+	struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+	buf->skb = napi_alloc_skb(&rx_ring->napi_rx, IPQESS_RX_HEAD_BUFF_SIZE);
-+	if (!buf->skb)
-+		return -ENOMEM;
-+
-+	return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static int ipqess_rx_buf_alloc(struct ipqess_rx_ring *rx_ring)
-+{
-+	struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+	buf->skb = netdev_alloc_skb_ip_align(rx_ring->ess->netdev,
-+					     IPQESS_RX_HEAD_BUFF_SIZE);
-+
-+	if (!buf->skb)
-+		return -ENOMEM;
-+
-+	return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static void ipqess_refill_work(struct work_struct *work)
-+{
-+	struct ipqess_rx_ring_refill *rx_refill = container_of(work,
-+		struct ipqess_rx_ring_refill, refill_work);
-+	struct ipqess_rx_ring *rx_ring = rx_refill->rx_ring;
-+	int refill = 0;
-+
-+	/* don't let this loop by accident. */
-+	while (atomic_dec_and_test(&rx_ring->refill_count)) {
-+		napi_disable(&rx_ring->napi_rx);
-+		if (ipqess_rx_buf_alloc(rx_ring)) {
-+			refill++;
-+			dev_dbg(rx_ring->ppdev,
-+				"Not all buffers were reallocated");
-+		}
-+		napi_enable(&rx_ring->napi_rx);
-+	}
-+
-+	if (atomic_add_return(refill, &rx_ring->refill_count))
-+		schedule_work(&rx_refill->refill_work);
-+}
-+
-+static int ipqess_rx_ring_alloc(struct ipqess *ess)
-+{
-+	int i;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		int j;
-+
-+		ess->rx_ring[i].ess = ess;
-+		ess->rx_ring[i].ppdev = &ess->pdev->dev;
-+		ess->rx_ring[i].ring_id = i;
-+		ess->rx_ring[i].idx = i * 2;
-+
-+		ess->rx_ring[i].buf = devm_kzalloc(&ess->pdev->dev,
-+						   sizeof(struct ipqess_buf) * IPQESS_RX_RING_SIZE,
-+						   GFP_KERNEL);
-+
-+		if (!ess->rx_ring[i].buf)
-+			return -ENOMEM;
-+
-+		ess->rx_ring[i].hw_desc =
-+			dmam_alloc_coherent(&ess->pdev->dev,
-+					    sizeof(struct ipqess_rx_desc) * IPQESS_RX_RING_SIZE,
-+					    &ess->rx_ring[i].dma, GFP_KERNEL);
-+
-+		if (!ess->rx_ring[i].hw_desc)
-+			return -ENOMEM;
-+
-+		for (j = 0; j < IPQESS_RX_RING_SIZE; j++)
-+			if (ipqess_rx_buf_alloc(&ess->rx_ring[i]) < 0)
-+				return -ENOMEM;
-+
-+		ess->rx_refill[i].rx_ring = &ess->rx_ring[i];
-+		INIT_WORK(&ess->rx_refill[i].refill_work, ipqess_refill_work);
-+
-+		ipqess_w32(ess, IPQESS_REG_RFD_BASE_ADDR_Q(ess->rx_ring[i].idx),
-+			   (u32)(ess->rx_ring[i].dma));
-+	}
-+
-+	ipqess_w32(ess, IPQESS_REG_RX_DESC0,
-+		   (IPQESS_RX_HEAD_BUFF_SIZE << IPQESS_RX_BUF_SIZE_SHIFT) |
-+		   (IPQESS_RX_RING_SIZE << IPQESS_RFD_RING_SIZE_SHIFT));
-+
-+	return 0;
-+}
-+
-+static void ipqess_rx_ring_free(struct ipqess *ess)
-+{
-+	int i;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		int j;
-+
-+		cancel_work_sync(&ess->rx_refill[i].refill_work);
-+		atomic_set(&ess->rx_ring[i].refill_count, 0);
-+
-+		for (j = 0; j < IPQESS_RX_RING_SIZE; j++) {
-+			dma_unmap_single(&ess->pdev->dev,
-+					 ess->rx_ring[i].buf[j].dma,
-+					 ess->rx_ring[i].buf[j].length,
-+					 DMA_FROM_DEVICE);
-+			dev_kfree_skb_any(ess->rx_ring[i].buf[j].skb);
-+		}
-+	}
-+}
-+
-+static struct net_device_stats *ipqess_get_stats(struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	spin_lock(&ess->stats_lock);
-+	ipqess_update_hw_stats(ess);
-+	spin_unlock(&ess->stats_lock);
-+
-+	return &ess->stats;
-+}
-+
-+static int ipqess_rx_poll(struct ipqess_rx_ring *rx_ring, int budget)
-+{
-+	u32 length = 0, num_desc, tail, rx_ring_tail;
-+	int done = 0;
-+
-+	rx_ring_tail = rx_ring->tail;
-+
-+	tail = ipqess_r32(rx_ring->ess, IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+	tail >>= IPQESS_RFD_CONS_IDX_SHIFT;
-+	tail &= IPQESS_RFD_CONS_IDX_MASK;
-+
-+	while (done < budget) {
-+		struct ipqess_rx_desc *rd;
-+		struct sk_buff *skb;
-+
-+		if (rx_ring_tail == tail)
-+			break;
-+
-+		dma_unmap_single(rx_ring->ppdev,
-+				 rx_ring->buf[rx_ring_tail].dma,
-+				 rx_ring->buf[rx_ring_tail].length,
-+				 DMA_FROM_DEVICE);
-+
-+		skb = xchg(&rx_ring->buf[rx_ring_tail].skb, NULL);
-+		rd = (struct ipqess_rx_desc *)skb->data;
-+		rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+
-+		/* Check if RRD is valid */
-+		if (!(rd->rrd7 & cpu_to_le16(IPQESS_RRD_DESC_VALID))) {
-+			num_desc = 1;
-+			dev_kfree_skb_any(skb);
-+			goto skip;
-+		}
-+
-+		num_desc = le16_to_cpu(rd->rrd1) & IPQESS_RRD_NUM_RFD_MASK;
-+		length = le16_to_cpu(rd->rrd6) & IPQESS_RRD_PKT_SIZE_MASK;
-+
-+		skb_reserve(skb, IPQESS_RRD_SIZE);
-+		if (num_desc > 1) {
-+			struct sk_buff *skb_prev = NULL;
-+			int size_remaining;
-+			int i;
-+
-+			skb->data_len = 0;
-+			skb->tail += (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+			skb->len = length;
-+			skb->truesize = length;
-+			size_remaining = length - (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+
-+			for (i = 1; i < num_desc; i++) {
-+				struct sk_buff *skb_temp = rx_ring->buf[rx_ring_tail].skb;
-+
-+				dma_unmap_single(rx_ring->ppdev,
-+						 rx_ring->buf[rx_ring_tail].dma,
-+						 rx_ring->buf[rx_ring_tail].length,
-+						 DMA_FROM_DEVICE);
-+
-+				skb_put(skb_temp, min(size_remaining, IPQESS_RX_HEAD_BUFF_SIZE));
-+				if (skb_prev)
-+					skb_prev->next = rx_ring->buf[rx_ring_tail].skb;
-+				else
-+					skb_shinfo(skb)->frag_list = rx_ring->buf[rx_ring_tail].skb;
-+				skb_prev = rx_ring->buf[rx_ring_tail].skb;
-+				rx_ring->buf[rx_ring_tail].skb->next = NULL;
-+
-+				skb->data_len += rx_ring->buf[rx_ring_tail].skb->len;
-+				size_remaining -= rx_ring->buf[rx_ring_tail].skb->len;
-+
-+				rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+			}
-+
-+		} else {
-+			skb_put(skb, length);
-+		}
-+
-+		skb->dev = rx_ring->ess->netdev;
-+		skb->protocol = eth_type_trans(skb, rx_ring->ess->netdev);
-+		skb_record_rx_queue(skb, rx_ring->ring_id);
-+
-+		if (rd->rrd6 & cpu_to_le16(IPQESS_RRD_CSUM_FAIL_MASK))
-+			skb_checksum_none_assert(skb);
-+		else
-+			skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+		if (rd->rrd7 & cpu_to_le16(IPQESS_RRD_CVLAN))
-+			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
-+					       le16_to_cpu(rd->rrd4));
-+		else if (rd->rrd1 & cpu_to_le16(IPQESS_RRD_SVLAN))
-+			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
-+					       le16_to_cpu(rd->rrd4));
-+
-+		napi_gro_receive(&rx_ring->napi_rx, skb);
-+
-+		rx_ring->ess->stats.rx_packets++;
-+		rx_ring->ess->stats.rx_bytes += length;
-+
-+		done++;
-+skip:
-+
-+		num_desc += atomic_xchg(&rx_ring->refill_count, 0);
-+		while (num_desc) {
-+			if (ipqess_rx_buf_alloc_napi(rx_ring)) {
-+				num_desc = atomic_add_return(num_desc,
-+							     &rx_ring->refill_count);
-+				if (num_desc >= DIV_ROUND_UP(IPQESS_RX_RING_SIZE * 4, 7))
-+					schedule_work(&rx_ring->ess->rx_refill[rx_ring->ring_id].refill_work);
-+				break;
-+			}
-+			num_desc--;
-+		}
-+	}
-+
-+	ipqess_w32(rx_ring->ess, IPQESS_REG_RX_SW_CONS_IDX_Q(rx_ring->idx),
-+		   rx_ring_tail);
-+	rx_ring->tail = rx_ring_tail;
-+
-+	return done;
-+}
-+
-+static int ipqess_tx_complete(struct ipqess_tx_ring *tx_ring, int budget)
-+{
-+	int total = 0, ret;
-+	int done = 0;
-+	u32 tail;
-+
-+	tail = ipqess_r32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+	tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
-+	tail &= IPQESS_TPD_CONS_IDX_MASK;
-+
-+	do {
-+		ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
-+					       &tx_ring->buf[tx_ring->tail]);
-+		tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+
-+		total += ret;
-+	} while ((++done < budget) && (tx_ring->tail != tail));
-+
-+	ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
-+		   tx_ring->tail);
-+
-+	if (netif_tx_queue_stopped(tx_ring->nq)) {
-+		netdev_dbg(tx_ring->ess->netdev, "waking up tx queue %d\n",
-+			   tx_ring->idx);
-+		netif_tx_wake_queue(tx_ring->nq);
-+	}
-+
-+	netdev_tx_completed_queue(tx_ring->nq, done, total);
-+
-+	return done;
-+}
-+
-+static int ipqess_tx_napi(struct napi_struct *napi, int budget)
-+{
-+	struct ipqess_tx_ring *tx_ring = container_of(napi, struct ipqess_tx_ring,
-+						    napi_tx);
-+	int work_done = 0;
-+	u32 tx_status;
-+
-+	tx_status = ipqess_r32(tx_ring->ess, IPQESS_REG_TX_ISR);
-+	tx_status &= BIT(tx_ring->idx);
-+
-+	work_done = ipqess_tx_complete(tx_ring, budget);
-+
-+	ipqess_w32(tx_ring->ess, IPQESS_REG_TX_ISR, tx_status);
-+
-+	if (likely(work_done < budget)) {
-+		if (napi_complete_done(napi, work_done))
-+			ipqess_w32(tx_ring->ess,
-+				   IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+	}
-+
-+	return work_done;
-+}
-+
-+static int ipqess_rx_napi(struct napi_struct *napi, int budget)
-+{
-+	struct ipqess_rx_ring *rx_ring = container_of(napi, struct ipqess_rx_ring,
-+						    napi_rx);
-+	struct ipqess *ess = rx_ring->ess;
-+	u32 rx_mask = BIT(rx_ring->idx);
-+	int remaining_budget = budget;
-+	int rx_done;
-+	u32 status;
-+
-+	do {
-+		ipqess_w32(ess, IPQESS_REG_RX_ISR, rx_mask);
-+		rx_done = ipqess_rx_poll(rx_ring, remaining_budget);
-+		remaining_budget -= rx_done;
-+
-+		status = ipqess_r32(ess, IPQESS_REG_RX_ISR);
-+	} while (remaining_budget > 0 && (status & rx_mask));
-+
-+	if (remaining_budget <= 0)
-+		return budget;
-+
-+	if (napi_complete_done(napi, budget - remaining_budget))
-+		ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx), 0x1);
-+
-+	return budget - remaining_budget;
-+}
-+
-+static irqreturn_t ipqess_interrupt_tx(int irq, void *priv)
-+{
-+	struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
-+
-+	if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
-+		__napi_schedule(&tx_ring->napi_tx);
-+		ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
-+			   0x0);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t ipqess_interrupt_rx(int irq, void *priv)
-+{
-+	struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
-+
-+	if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
-+		__napi_schedule(&rx_ring->napi_rx);
-+		ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
-+			   0x0);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void ipqess_irq_enable(struct ipqess *ess)
-+{
-+	int i;
-+
-+	ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+	ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 1);
-+		ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 1);
-+	}
-+}
-+
-+static void ipqess_irq_disable(struct ipqess *ess)
-+{
-+	int i;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 0);
-+		ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 0);
-+	}
-+}
-+
-+static int __init ipqess_init(struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	struct device_node *of_node = ess->pdev->dev.of_node;
-+	int ret;
-+
-+	ret = of_get_ethdev_address(of_node, netdev);
-+	if (ret)
-+		eth_hw_addr_random(netdev);
-+
-+	return phylink_of_phy_connect(ess->phylink, of_node, 0);
-+}
-+
-+static void ipqess_uninit(struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	phylink_disconnect_phy(ess->phylink);
-+}
-+
-+static int ipqess_open(struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	int i, err;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		int qid;
-+
-+		qid = ess->tx_ring[i].idx;
-+		err = devm_request_irq(&netdev->dev, ess->tx_irq[qid],
-+				       ipqess_interrupt_tx, 0,
-+				       ess->tx_irq_names[qid],
-+				       &ess->tx_ring[i]);
-+		if (err)
-+			return err;
-+
-+		qid = ess->rx_ring[i].idx;
-+		err = devm_request_irq(&netdev->dev, ess->rx_irq[qid],
-+				       ipqess_interrupt_rx, 0,
-+				       ess->rx_irq_names[qid],
-+				       &ess->rx_ring[i]);
-+		if (err)
-+			return err;
-+
-+		napi_enable(&ess->tx_ring[i].napi_tx);
-+		napi_enable(&ess->rx_ring[i].napi_rx);
-+	}
-+
-+	ipqess_irq_enable(ess);
-+	phylink_start(ess->phylink);
-+	netif_tx_start_all_queues(netdev);
-+
-+	return 0;
-+}
-+
-+static int ipqess_stop(struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	int i;
-+
-+	netif_tx_stop_all_queues(netdev);
-+	phylink_stop(ess->phylink);
-+	ipqess_irq_disable(ess);
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		napi_disable(&ess->tx_ring[i].napi_tx);
-+		napi_disable(&ess->rx_ring[i].napi_rx);
-+	}
-+
-+	return 0;
-+}
-+
-+static int ipqess_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	return phylink_mii_ioctl(ess->phylink, ifr, cmd);
-+}
-+
-+static u16 ipqess_tx_desc_available(struct ipqess_tx_ring *tx_ring)
-+{
-+	u16 count = 0;
-+
-+	if (tx_ring->tail <= tx_ring->head)
-+		count = IPQESS_TX_RING_SIZE;
-+
-+	count += tx_ring->tail - tx_ring->head - 1;
-+
-+	return count;
-+}
-+
-+static int ipqess_cal_txd_req(struct sk_buff *skb)
-+{
-+	int tpds;
-+
-+	/* one TPD for the header, and one for each fragments */
-+	tpds = 1 + skb_shinfo(skb)->nr_frags;
-+	if (skb_is_gso(skb) && skb_is_gso_v6(skb)) {
-+		/* for LSOv2 one extra TPD is needed */
-+		tpds++;
-+	}
-+
-+	return tpds;
-+}
-+
-+static struct ipqess_buf *ipqess_get_tx_buffer(struct ipqess_tx_ring *tx_ring,
-+					       struct ipqess_tx_desc *desc)
-+{
-+	return &tx_ring->buf[desc - tx_ring->hw_desc];
-+}
-+
-+static struct ipqess_tx_desc *ipqess_tx_desc_next(struct ipqess_tx_ring *tx_ring)
-+{
-+	struct ipqess_tx_desc *desc;
-+
-+	desc = &tx_ring->hw_desc[tx_ring->head];
-+	tx_ring->head = IPQESS_NEXT_IDX(tx_ring->head, tx_ring->count);
-+
-+	return desc;
-+}
-+
-+static void ipqess_rollback_tx(struct ipqess *eth,
-+			       struct ipqess_tx_desc *first_desc, int ring_id)
-+{
-+	struct ipqess_tx_ring *tx_ring = &eth->tx_ring[ring_id];
-+	struct ipqess_tx_desc *desc = NULL;
-+	struct ipqess_buf *buf;
-+	u16 start_index, index;
-+
-+	start_index = first_desc - tx_ring->hw_desc;
-+
-+	index = start_index;
-+	while (index != tx_ring->head) {
-+		desc = &tx_ring->hw_desc[index];
-+		buf = &tx_ring->buf[index];
-+		ipqess_tx_unmap_and_free(&eth->pdev->dev, buf);
-+		memset(desc, 0, sizeof(*desc));
-+		if (++index == tx_ring->count)
-+			index = 0;
-+	}
-+	tx_ring->head = start_index;
-+}
-+
-+static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
-+				  struct sk_buff *skb)
-+{
-+	struct ipqess_tx_desc *desc = NULL, *first_desc = NULL;
-+	u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;
-+	struct platform_device *pdev = tx_ring->ess->pdev;
-+	struct ipqess_buf *buf = NULL;
-+	u16 len;
-+	int i;
-+
-+	if (skb_is_gso(skb)) {
-+		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
-+			lso_word1 |= IPQESS_TPD_IPV4_EN;
-+			ip_hdr(skb)->check = 0;
-+			tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
-+								 ip_hdr(skb)->daddr,
-+								 0, IPPROTO_TCP, 0);
-+		} else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
-+			lso_word1 |= IPQESS_TPD_LSO_V2_EN;
-+			ipv6_hdr(skb)->payload_len = 0;
-+			tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
-+							       &ipv6_hdr(skb)->daddr,
-+							       0, IPPROTO_TCP, 0);
-+		}
-+
-+		lso_word1 |= IPQESS_TPD_LSO_EN |
-+			     ((skb_shinfo(skb)->gso_size & IPQESS_TPD_MSS_MASK) <<
-+							   IPQESS_TPD_MSS_SHIFT) |
-+			     (skb_transport_offset(skb) << IPQESS_TPD_HDR_SHIFT);
-+	} else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-+		u8 css, cso;
-+
-+		cso = skb_checksum_start_offset(skb);
-+		css = cso + skb->csum_offset;
-+
-+		word1 |= (IPQESS_TPD_CUSTOM_CSUM_EN);
-+		word1 |= (cso >> 1) << IPQESS_TPD_HDR_SHIFT;
-+		word1 |= ((css >> 1) << IPQESS_TPD_CUSTOM_CSUM_SHIFT);
-+	}
-+
-+	if (skb_vlan_tag_present(skb)) {
-+		switch (skb->vlan_proto) {
-+		case htons(ETH_P_8021Q):
-+			word3 |= BIT(IPQESS_TX_INS_CVLAN);
-+			word3 |= skb_vlan_tag_get(skb) << IPQESS_TX_CVLAN_TAG_SHIFT;
-+			break;
-+		case htons(ETH_P_8021AD):
-+			word1 |= BIT(IPQESS_TX_INS_SVLAN);
-+			svlan_tag = skb_vlan_tag_get(skb);
-+			break;
-+		default:
-+			dev_err(&pdev->dev, "no ctag or stag present\n");
-+			goto vlan_tag_error;
-+		}
-+	}
-+
-+	if (eth_type_vlan(skb->protocol))
-+		word1 |= IPQESS_TPD_VLAN_TAGGED;
-+
-+	if (skb->protocol == htons(ETH_P_PPP_SES))
-+		word1 |= IPQESS_TPD_PPPOE_EN;
-+
-+	len = skb_headlen(skb);
-+
-+	first_desc = ipqess_tx_desc_next(tx_ring);
-+	desc = first_desc;
-+	if (lso_word1 & IPQESS_TPD_LSO_V2_EN) {
-+		desc->addr = cpu_to_le32(skb->len);
-+		desc->word1 = cpu_to_le32(word1 | lso_word1);
-+		desc->svlan_tag = cpu_to_le16(svlan_tag);
-+		desc->word3 = cpu_to_le32(word3);
-+		desc = ipqess_tx_desc_next(tx_ring);
-+	}
-+
-+	buf = ipqess_get_tx_buffer(tx_ring, desc);
-+	buf->length = len;
-+	buf->dma = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
-+
-+	if (dma_mapping_error(&pdev->dev, buf->dma))
-+		goto dma_error;
-+
-+	desc->addr = cpu_to_le32(buf->dma);
-+	desc->len  = cpu_to_le16(len);
-+
-+	buf->flags |= IPQESS_DESC_SINGLE;
-+	desc->word1 = cpu_to_le32(word1 | lso_word1);
-+	desc->svlan_tag = cpu_to_le16(svlan_tag);
-+	desc->word3 = cpu_to_le32(word3);
-+
-+	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
-+		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-+
-+		len = skb_frag_size(frag);
-+		desc = ipqess_tx_desc_next(tx_ring);
-+		buf = ipqess_get_tx_buffer(tx_ring, desc);
-+		buf->length = len;
-+		buf->flags |= IPQESS_DESC_PAGE;
-+		buf->dma = skb_frag_dma_map(&pdev->dev, frag, 0, len,
-+					    DMA_TO_DEVICE);
-+
-+		if (dma_mapping_error(&pdev->dev, buf->dma))
-+			goto dma_error;
-+
-+		desc->addr = cpu_to_le32(buf->dma);
-+		desc->len  = cpu_to_le16(len);
-+		desc->svlan_tag = cpu_to_le16(svlan_tag);
-+		desc->word1 = cpu_to_le32(word1 | lso_word1);
-+		desc->word3 = cpu_to_le32(word3);
-+	}
-+	desc->word1 |= cpu_to_le32(1 << IPQESS_TPD_EOP_SHIFT);
-+	buf->skb = skb;
-+	buf->flags |= IPQESS_DESC_LAST;
-+
-+	return 0;
-+
-+dma_error:
-+	ipqess_rollback_tx(tx_ring->ess, first_desc, tx_ring->ring_id);
-+	dev_err(&pdev->dev, "TX DMA map failed\n");
-+
-+vlan_tag_error:
-+	return -ENOMEM;
-+}
-+
-+static void ipqess_kick_tx(struct ipqess_tx_ring *tx_ring)
-+{
-+	/* Ensure that all TPDs has been written completely */
-+	dma_wmb();
-+
-+	/* update software producer index */
-+	ipqess_w32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx),
-+		   tx_ring->head);
-+}
-+
-+static netdev_tx_t ipqess_xmit(struct sk_buff *skb, struct net_device *netdev)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	struct ipqess_tx_ring *tx_ring;
-+	int avail;
-+	int tx_num;
-+	int ret;
-+
-+	tx_ring = &ess->tx_ring[skb_get_queue_mapping(skb)];
-+	tx_num = ipqess_cal_txd_req(skb);
-+	avail = ipqess_tx_desc_available(tx_ring);
-+	if (avail < tx_num) {
-+		netdev_dbg(netdev,
-+			   "stopping tx queue %d, avail=%d req=%d im=%x\n",
-+			   tx_ring->idx, avail, tx_num,
-+			   ipqess_r32(tx_ring->ess,
-+				      IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx)));
-+		netif_tx_stop_queue(tx_ring->nq);
-+		ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+		ipqess_kick_tx(tx_ring);
-+		return NETDEV_TX_BUSY;
-+	}
-+
-+	ret = ipqess_tx_map_and_fill(tx_ring, skb);
-+	if (ret) {
-+		dev_kfree_skb_any(skb);
-+		ess->stats.tx_errors++;
-+		goto err_out;
-+	}
-+
-+	ess->stats.tx_packets++;
-+	ess->stats.tx_bytes += skb->len;
-+	netdev_tx_sent_queue(tx_ring->nq, skb->len);
-+
-+	if (!netdev_xmit_more() || netif_xmit_stopped(tx_ring->nq))
-+		ipqess_kick_tx(tx_ring);
-+
-+err_out:
-+	return NETDEV_TX_OK;
-+}
-+
-+static int ipqess_set_mac_address(struct net_device *netdev, void *p)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	const char *macaddr = netdev->dev_addr;
-+	int ret = eth_mac_addr(netdev, p);
-+
-+	if (ret)
-+		return ret;
-+
-+	ipqess_w32(ess, IPQESS_REG_MAC_CTRL1, (macaddr[0] << 8) | macaddr[1]);
-+	ipqess_w32(ess, IPQESS_REG_MAC_CTRL0,
-+		   (macaddr[2] << 24) | (macaddr[3] << 16) | (macaddr[4] << 8) |
-+		    macaddr[5]);
-+
-+	return 0;
-+}
-+
-+static void ipqess_tx_timeout(struct net_device *netdev, unsigned int txq_id)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	struct ipqess_tx_ring *tr = &ess->tx_ring[txq_id];
-+
-+	netdev_warn(netdev, "TX timeout on queue %d\n", tr->idx);
-+}
-+
-+static const struct net_device_ops ipqess_axi_netdev_ops = {
-+	.ndo_init		= ipqess_init,
-+	.ndo_uninit		= ipqess_uninit,
-+	.ndo_open		= ipqess_open,
-+	.ndo_stop		= ipqess_stop,
-+	.ndo_do_ioctl		= ipqess_do_ioctl,
-+	.ndo_start_xmit		= ipqess_xmit,
-+	.ndo_get_stats		= ipqess_get_stats,
-+	.ndo_set_mac_address	= ipqess_set_mac_address,
-+	.ndo_tx_timeout		= ipqess_tx_timeout,
-+};
-+
-+static void ipqess_hw_stop(struct ipqess *ess)
-+{
-+	int i;
-+
-+	/* disable all RX queue IRQs */
-+	for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++)
-+		ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(i), 0);
-+
-+	/* disable all TX queue IRQs */
-+	for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++)
-+		ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(i), 0);
-+
-+	/* disable all other IRQs */
-+	ipqess_w32(ess, IPQESS_REG_MISC_IMR, 0);
-+	ipqess_w32(ess, IPQESS_REG_WOL_IMR, 0);
-+
-+	/* clear the IRQ status registers */
-+	ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+	ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+	ipqess_w32(ess, IPQESS_REG_MISC_ISR, 0x1fff);
-+	ipqess_w32(ess, IPQESS_REG_WOL_ISR, 0x1);
-+	ipqess_w32(ess, IPQESS_REG_WOL_CTRL, 0);
-+
-+	/* disable RX and TX queues */
-+	ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, 0, IPQESS_REG_RXQ_CTRL);
-+	ipqess_m32(ess, IPQESS_TXQ_CTRL_TXQ_EN, 0, IPQESS_REG_TXQ_CTRL);
-+}
-+
-+static int ipqess_hw_init(struct ipqess *ess)
-+{
-+	int i, err;
-+	u32 tmp;
-+
-+	ipqess_hw_stop(ess);
-+
-+	ipqess_m32(ess, BIT(IPQESS_INTR_SW_IDX_W_TYP_SHIFT),
-+		   IPQESS_INTR_SW_IDX_W_TYPE << IPQESS_INTR_SW_IDX_W_TYP_SHIFT,
-+		   IPQESS_REG_INTR_CTRL);
-+
-+	/* enable IRQ delay slot */
-+	ipqess_w32(ess, IPQESS_REG_IRQ_MODRT_TIMER_INIT,
-+		   (IPQESS_TX_IMT << IPQESS_IRQ_MODRT_TX_TIMER_SHIFT) |
-+		   (IPQESS_RX_IMT << IPQESS_IRQ_MODRT_RX_TIMER_SHIFT));
-+
-+	/* Set Customer and Service VLAN TPIDs */
-+	ipqess_w32(ess, IPQESS_REG_VLAN_CFG,
-+		   (ETH_P_8021Q << IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT) |
-+		   (ETH_P_8021AD << IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT));
-+
-+	/* Configure the TX Queue bursting */
-+	ipqess_w32(ess, IPQESS_REG_TXQ_CTRL,
-+		   (IPQESS_TPD_BURST << IPQESS_TXQ_NUM_TPD_BURST_SHIFT) |
-+		   (IPQESS_TXF_BURST << IPQESS_TXQ_TXF_BURST_NUM_SHIFT) |
-+		   IPQESS_TXQ_CTRL_TPD_BURST_EN);
-+
-+	/* Set RSS type */
-+	ipqess_w32(ess, IPQESS_REG_RSS_TYPE,
-+		   IPQESS_RSS_TYPE_IPV4TCP | IPQESS_RSS_TYPE_IPV6_TCP |
-+		   IPQESS_RSS_TYPE_IPV4_UDP | IPQESS_RSS_TYPE_IPV6UDP |
-+		   IPQESS_RSS_TYPE_IPV4 | IPQESS_RSS_TYPE_IPV6);
-+
-+	/* Set RFD ring burst and threshold */
-+	ipqess_w32(ess, IPQESS_REG_RX_DESC1,
-+		   (IPQESS_RFD_BURST << IPQESS_RXQ_RFD_BURST_NUM_SHIFT) |
-+		   (IPQESS_RFD_THR << IPQESS_RXQ_RFD_PF_THRESH_SHIFT) |
-+		   (IPQESS_RFD_LTHR << IPQESS_RXQ_RFD_LOW_THRESH_SHIFT));
-+
-+	/* Set Rx FIFO
-+	 * - threshold to start to DMA data to host
-+	 */
-+	ipqess_w32(ess, IPQESS_REG_RXQ_CTRL,
-+		   IPQESS_FIFO_THRESH_128_BYTE | IPQESS_RXQ_CTRL_RMV_VLAN);
-+
-+	err = ipqess_rx_ring_alloc(ess);
-+	if (err)
-+		return err;
-+
-+	err = ipqess_tx_ring_alloc(ess);
-+	if (err)
-+		goto err_rx_ring_free;
-+
-+	/* Load all of ring base addresses above into the dma engine */
-+	ipqess_m32(ess, 0, BIT(IPQESS_LOAD_PTR_SHIFT), IPQESS_REG_TX_SRAM_PART);
-+
-+	/* Disable TX FIFO low watermark and high watermark */
-+	ipqess_w32(ess, IPQESS_REG_TXF_WATER_MARK, 0);
-+
-+	/* Configure RSS indirection table.
-+	 * 128 hash will be configured in the following
-+	 * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively
-+	 * and so on
-+	 */
-+	for (i = 0; i < IPQESS_NUM_IDT; i++)
-+		ipqess_w32(ess, IPQESS_REG_RSS_IDT(i), IPQESS_RSS_IDT_VALUE);
-+
-+	/* Configure load balance mapping table.
-+	 * 4 table entry will be configured according to the
-+	 * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}
-+	 * respectively.
-+	 */
-+	ipqess_w32(ess, IPQESS_REG_LB_RING, IPQESS_LB_REG_VALUE);
-+
-+	/* Configure Virtual queue for Tx rings */
-+	ipqess_w32(ess, IPQESS_REG_VQ_CTRL0, IPQESS_VQ_REG_VALUE);
-+	ipqess_w32(ess, IPQESS_REG_VQ_CTRL1, IPQESS_VQ_REG_VALUE);
-+
-+	/* Configure Max AXI Burst write size to 128 bytes*/
-+	ipqess_w32(ess, IPQESS_REG_AXIW_CTRL_MAXWRSIZE,
-+		   IPQESS_AXIW_MAXWRSIZE_VALUE);
-+
-+	/* Enable TX queues */
-+	ipqess_m32(ess, 0, IPQESS_TXQ_CTRL_TXQ_EN, IPQESS_REG_TXQ_CTRL);
-+
-+	/* Enable RX queues */
-+	tmp = 0;
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++)
-+		tmp |= IPQESS_RXQ_CTRL_EN(ess->rx_ring[i].idx);
-+
-+	ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, tmp, IPQESS_REG_RXQ_CTRL);
-+
-+	return 0;
-+
-+err_rx_ring_free:
-+
-+	ipqess_rx_ring_free(ess);
-+	return err;
-+}
-+
-+static void ipqess_mac_config(struct phylink_config *config, unsigned int mode,
-+			      const struct phylink_link_state *state)
-+{
-+	/* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_down(struct phylink_config *config,
-+				 unsigned int mode,
-+				 phy_interface_t interface)
-+{
-+	/* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_up(struct phylink_config *config,
-+			       struct phy_device *phy, unsigned int mode,
-+			       phy_interface_t interface,
-+			       int speed, int duplex,
-+			       bool tx_pause, bool rx_pause)
-+{
-+	/* Nothing to do, use fixed Internal mode */
-+}
-+
-+static struct phylink_mac_ops ipqess_phylink_mac_ops = {
-+	.validate		= phylink_generic_validate,
-+	.mac_config		= ipqess_mac_config,
-+	.mac_link_up		= ipqess_mac_link_up,
-+	.mac_link_down		= ipqess_mac_link_down,
-+};
-+
-+static void ipqess_reset(struct ipqess *ess)
-+{
-+	reset_control_assert(ess->ess_rst);
-+
-+	mdelay(10);
-+
-+	reset_control_deassert(ess->ess_rst);
-+
-+	/* Waiting for all inner tables to be flushed and reinitialized.
-+	 * This takes between 5 and 10 ms
-+	 */
-+
-+	mdelay(10);
-+}
-+
-+static int ipqess_axi_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct net_device *netdev;
-+	phy_interface_t phy_mode;
-+	struct ipqess *ess;
-+	int i, err = 0;
-+
-+	netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(*ess),
-+					 IPQESS_NETDEV_QUEUES,
-+					 IPQESS_NETDEV_QUEUES);
-+	if (!netdev)
-+		return -ENOMEM;
-+
-+	ess = netdev_priv(netdev);
-+	ess->netdev = netdev;
-+	ess->pdev = pdev;
-+	spin_lock_init(&ess->stats_lock);
-+	SET_NETDEV_DEV(netdev, &pdev->dev);
-+	platform_set_drvdata(pdev, netdev);
-+
-+	ess->hw_addr = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+	if (IS_ERR(ess->hw_addr))
-+		return PTR_ERR(ess->hw_addr);
-+
-+	err = of_get_phy_mode(np, &phy_mode);
-+	if (err) {
-+		dev_err(&pdev->dev, "incorrect phy-mode\n");
-+		return err;
-+	}
-+
-+	ess->ess_clk = devm_clk_get(&pdev->dev, NULL);
-+	if (!IS_ERR(ess->ess_clk))
-+		clk_prepare_enable(ess->ess_clk);
-+
-+	ess->ess_rst = devm_reset_control_get(&pdev->dev, NULL);
-+	if (IS_ERR(ess->ess_rst))
-+		goto err_clk;
-+
-+	ipqess_reset(ess);
-+
-+	ess->phylink_config.dev = &netdev->dev;
-+	ess->phylink_config.type = PHYLINK_NETDEV;
-+	ess->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
-+					       MAC_100 | MAC_1000FD;
-+
-+	__set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+		  ess->phylink_config.supported_interfaces);
-+
-+	ess->phylink = phylink_create(&ess->phylink_config,
-+				      of_fwnode_handle(np), phy_mode,
-+				      &ipqess_phylink_mac_ops);
-+	if (IS_ERR(ess->phylink)) {
-+		err = PTR_ERR(ess->phylink);
-+		goto err_clk;
-+	}
-+
-+	for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+		ess->tx_irq[i] = platform_get_irq(pdev, i);
-+		scnprintf(ess->tx_irq_names[i], sizeof(ess->tx_irq_names[i]),
-+			  "%s:txq%d", pdev->name, i);
-+	}
-+
-+	for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+		ess->rx_irq[i] = platform_get_irq(pdev, i + IPQESS_MAX_TX_QUEUE);
-+		scnprintf(ess->rx_irq_names[i], sizeof(ess->rx_irq_names[i]),
-+			  "%s:rxq%d", pdev->name, i);
-+	}
-+
-+	netdev->netdev_ops = &ipqess_axi_netdev_ops;
-+	netdev->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
-+			   NETIF_F_HW_VLAN_CTAG_RX |
-+			   NETIF_F_HW_VLAN_CTAG_TX |
-+			   NETIF_F_TSO | NETIF_F_GRO | NETIF_F_SG;
-+	/* feature change is not supported yet */
-+	netdev->hw_features = 0;
-+	netdev->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_RXCSUM |
-+				NETIF_F_TSO |
-+				NETIF_F_GRO;
-+	netdev->watchdog_timeo = 5 * HZ;
-+	netdev->base_addr = (u32)ess->hw_addr;
-+	netdev->max_mtu = 9000;
-+	netdev->gso_max_segs = IPQESS_TX_RING_SIZE / 2;
-+
-+	ipqess_set_ethtool_ops(netdev);
-+
-+	err = ipqess_hw_init(ess);
-+	if (err)
-+		goto err_phylink;
-+
-+	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		netif_napi_add_tx(netdev, &ess->tx_ring[i].napi_tx, ipqess_tx_napi);
-+		netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
-+	}
-+
-+	err = register_netdev(netdev);
-+	if (err)
-+		goto err_hw_stop;
-+
-+	return 0;
-+
-+err_hw_stop:
-+	ipqess_hw_stop(ess);
-+
-+	ipqess_tx_ring_free(ess);
-+	ipqess_rx_ring_free(ess);
-+err_phylink:
-+	phylink_destroy(ess->phylink);
-+
-+err_clk:
-+	clk_disable_unprepare(ess->ess_clk);
-+
-+	return err;
-+}
-+
-+static int ipqess_axi_remove(struct platform_device *pdev)
-+{
-+	const struct net_device *netdev = platform_get_drvdata(pdev);
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	unregister_netdev(ess->netdev);
-+	ipqess_hw_stop(ess);
-+
-+	ipqess_tx_ring_free(ess);
-+	ipqess_rx_ring_free(ess);
-+
-+	phylink_destroy(ess->phylink);
-+	clk_disable_unprepare(ess->ess_clk);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id ipqess_of_mtable[] = {
-+	{.compatible = "qcom,ipq4019-ess-edma" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, ipqess_of_mtable);
-+
-+static struct platform_driver ipqess_axi_driver = {
-+	.driver = {
-+		.name    = "ipqess-edma",
-+		.of_match_table = ipqess_of_mtable,
-+	},
-+	.probe    = ipqess_axi_probe,
-+	.remove   = ipqess_axi_remove,
-+};
-+
-+module_platform_driver(ipqess_axi_driver);
-+
-+MODULE_AUTHOR("Qualcomm Atheros Inc");
-+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -0,0 +1,518 @@
-+/* SPDX-License-Identifier: (GPL-2.0 OR ISC) */
-+/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#ifndef _IPQESS_H_
-+#define _IPQESS_H_
-+
-+#define IPQESS_NETDEV_QUEUES	4
-+
-+#define IPQESS_TPD_EOP_SHIFT 31
-+
-+#define IPQESS_PORT_ID_SHIFT 12
-+#define IPQESS_PORT_ID_MASK 0x7
-+
-+/* tpd word 3 bit 18-28 */
-+#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
-+
-+#define IPQESS_TPD_FROM_CPU_SHIFT 25
-+
-+#define IPQESS_RX_RING_SIZE 128
-+#define IPQESS_RX_HEAD_BUFF_SIZE 1540
-+#define IPQESS_TX_RING_SIZE 128
-+#define IPQESS_MAX_RX_QUEUE 8
-+#define IPQESS_MAX_TX_QUEUE 16
-+
-+/* Configurations */
-+#define IPQESS_INTR_CLEAR_TYPE 0
-+#define IPQESS_INTR_SW_IDX_W_TYPE 0
-+#define IPQESS_FIFO_THRESH_TYPE 0
-+#define IPQESS_RSS_TYPE 0
-+#define IPQESS_RX_IMT 0x0020
-+#define IPQESS_TX_IMT 0x0050
-+#define IPQESS_TPD_BURST 5
-+#define IPQESS_TXF_BURST 0x100
-+#define IPQESS_RFD_BURST 8
-+#define IPQESS_RFD_THR 16
-+#define IPQESS_RFD_LTHR 0
-+
-+/* Flags used in transmit direction */
-+#define IPQESS_DESC_LAST 0x1
-+#define IPQESS_DESC_SINGLE 0x2
-+#define IPQESS_DESC_PAGE 0x4
-+
-+struct ipqess_statistics {
-+	u32 tx_q0_pkt;
-+	u32 tx_q1_pkt;
-+	u32 tx_q2_pkt;
-+	u32 tx_q3_pkt;
-+	u32 tx_q4_pkt;
-+	u32 tx_q5_pkt;
-+	u32 tx_q6_pkt;
-+	u32 tx_q7_pkt;
-+	u32 tx_q8_pkt;
-+	u32 tx_q9_pkt;
-+	u32 tx_q10_pkt;
-+	u32 tx_q11_pkt;
-+	u32 tx_q12_pkt;
-+	u32 tx_q13_pkt;
-+	u32 tx_q14_pkt;
-+	u32 tx_q15_pkt;
-+	u32 tx_q0_byte;
-+	u32 tx_q1_byte;
-+	u32 tx_q2_byte;
-+	u32 tx_q3_byte;
-+	u32 tx_q4_byte;
-+	u32 tx_q5_byte;
-+	u32 tx_q6_byte;
-+	u32 tx_q7_byte;
-+	u32 tx_q8_byte;
-+	u32 tx_q9_byte;
-+	u32 tx_q10_byte;
-+	u32 tx_q11_byte;
-+	u32 tx_q12_byte;
-+	u32 tx_q13_byte;
-+	u32 tx_q14_byte;
-+	u32 tx_q15_byte;
-+	u32 rx_q0_pkt;
-+	u32 rx_q1_pkt;
-+	u32 rx_q2_pkt;
-+	u32 rx_q3_pkt;
-+	u32 rx_q4_pkt;
-+	u32 rx_q5_pkt;
-+	u32 rx_q6_pkt;
-+	u32 rx_q7_pkt;
-+	u32 rx_q0_byte;
-+	u32 rx_q1_byte;
-+	u32 rx_q2_byte;
-+	u32 rx_q3_byte;
-+	u32 rx_q4_byte;
-+	u32 rx_q5_byte;
-+	u32 rx_q6_byte;
-+	u32 rx_q7_byte;
-+	u32 tx_desc_error;
-+};
-+
-+struct ipqess_tx_desc {
-+	__le16  len;
-+	__le16  svlan_tag;
-+	__le32  word1;
-+	__le32  addr;
-+	__le32  word3;
-+} __aligned(16) __packed;
-+
-+struct ipqess_rx_desc {
-+	__le16 rrd0;
-+	__le16 rrd1;
-+	__le16 rrd2;
-+	__le16 rrd3;
-+	__le16 rrd4;
-+	__le16 rrd5;
-+	__le16 rrd6;
-+	__le16 rrd7;
-+} __aligned(16) __packed;
-+
-+struct ipqess_buf {
-+	struct sk_buff *skb;
-+	dma_addr_t dma;
-+	u32 flags;
-+	u16 length;
-+};
-+
-+struct ipqess_tx_ring {
-+	struct napi_struct napi_tx;
-+	u32 idx;
-+	int ring_id;
-+	struct ipqess *ess;
-+	struct netdev_queue *nq;
-+	struct ipqess_tx_desc *hw_desc;
-+	struct ipqess_buf *buf;
-+	dma_addr_t dma;
-+	u16 count;
-+	u16 head;
-+	u16 tail;
-+};
-+
-+struct ipqess_rx_ring {
-+	struct napi_struct napi_rx;
-+	u32 idx;
-+	int ring_id;
-+	struct ipqess *ess;
-+	struct device *ppdev;
-+	struct ipqess_rx_desc **hw_desc;
-+	struct ipqess_buf *buf;
-+	dma_addr_t dma;
-+	u16 head;
-+	u16 tail;
-+	atomic_t refill_count;
-+};
-+
-+struct ipqess_rx_ring_refill {
-+	struct ipqess_rx_ring *rx_ring;
-+	struct work_struct refill_work;
-+};
-+
-+#define IPQESS_IRQ_NAME_LEN	32
-+
-+struct ipqess {
-+	struct net_device *netdev;
-+	void __iomem *hw_addr;
-+
-+	struct clk *ess_clk;
-+	struct reset_control *ess_rst;
-+
-+	struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
-+
-+	struct platform_device *pdev;
-+	struct phylink *phylink;
-+	struct phylink_config phylink_config;
-+	struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
-+
-+	struct ipqess_statistics ipqess_stats;
-+
-+	/* Protects stats */
-+	spinlock_t stats_lock;
-+	struct net_device_stats stats;
-+
-+	struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
-+	u32 tx_irq[IPQESS_MAX_TX_QUEUE];
-+	char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+	u32 rx_irq[IPQESS_MAX_RX_QUEUE];
-+	char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev);
-+void ipqess_update_hw_stats(struct ipqess *ess);
-+
-+/* register definition */
-+#define IPQESS_REG_MAS_CTRL 0x0
-+#define IPQESS_REG_TIMEOUT_CTRL 0x004
-+#define IPQESS_REG_DBG0 0x008
-+#define IPQESS_REG_DBG1 0x00C
-+#define IPQESS_REG_SW_CTRL0 0x100
-+#define IPQESS_REG_SW_CTRL1 0x104
-+
-+/* Interrupt Status Register */
-+#define IPQESS_REG_RX_ISR 0x200
-+#define IPQESS_REG_TX_ISR 0x208
-+#define IPQESS_REG_MISC_ISR 0x210
-+#define IPQESS_REG_WOL_ISR 0x218
-+
-+#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << (x))
-+
-+#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
-+#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
-+#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
-+#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
-+#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
-+
-+#define IPQESS_WOL_ISR 0x00000001
-+
-+/* Interrupt Mask Register */
-+#define IPQESS_REG_MISC_IMR 0x214
-+#define IPQESS_REG_WOL_IMR 0x218
-+
-+#define IPQESS_RX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_TX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
-+#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
-+
-+/* Edma receive consumer index */
-+#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
-+
-+/* Edma transmit consumer index */
-+#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
-+
-+/* IRQ Moderator Initial Timer Register */
-+#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
-+#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
-+#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
-+#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
-+
-+/* Interrupt Control Register */
-+#define IPQESS_REG_INTR_CTRL 0x284
-+#define IPQESS_INTR_CLR_TYP_SHIFT 0
-+#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
-+#define IPQESS_INTR_CLEAR_TYPE_W1 0
-+#define IPQESS_INTR_CLEAR_TYPE_R 1
-+
-+/* RX Interrupt Mask Register */
-+#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
-+
-+/* TX Interrupt mask register */
-+#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
-+
-+/* Load Ptr Register
-+ * Software sets this bit after the initialization of the head and tail
-+ */
-+#define IPQESS_REG_TX_SRAM_PART 0x400
-+#define IPQESS_LOAD_PTR_SHIFT 16
-+
-+/* TXQ Control Register */
-+#define IPQESS_REG_TXQ_CTRL 0x404
-+#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
-+#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
-+#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
-+#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
-+#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
-+#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
-+#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
-+#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
-+#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
-+#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
-+
-+#define	IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
-+#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
-+#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
-+#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
-+#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
-+
-+/* WRR Control Register */
-+#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
-+#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
-+#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
-+#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
-+
-+/* Weight round robin(WRR), it takes queue as input, and computes
-+ * starting bits where we need to write the weight for a particular
-+ * queue
-+ */
-+#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
-+
-+/* Tx Descriptor Control Register */
-+#define IPQESS_REG_TPD_RING_SIZE 0x41C
-+#define IPQESS_TPD_RING_SIZE_SHIFT 0
-+#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
-+
-+/* Transmit descriptor base address */
-+#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
-+
-+/* TPD Index Register */
-+#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
-+#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
-+#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_PROD_IDX_SHIFT 0
-+#define IPQESS_TPD_CONS_IDX_SHIFT 16
-+
-+/* TX Virtual Queue Mapping Control Register */
-+#define IPQESS_REG_VQ_CTRL0 0x4A0
-+#define IPQESS_REG_VQ_CTRL1 0x4A4
-+
-+/* Virtual QID shift, it takes queue as input, and computes
-+ * Virtual QID position in virtual qid control register
-+ */
-+#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
-+
-+/* Virtual Queue Default Value */
-+#define IPQESS_VQ_REG_VALUE 0x240240
-+
-+/* Tx side Port Interface Control Register */
-+#define IPQESS_REG_PORT_CTRL 0x4A8
-+#define IPQESS_PAD_EN_SHIFT 15
-+
-+/* Tx side VLAN Configuration Register */
-+#define IPQESS_REG_VLAN_CFG 0x4AC
-+
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
-+
-+#define IPQESS_TX_CVLAN 16
-+#define IPQESS_TX_INS_CVLAN 17
-+#define IPQESS_TX_CVLAN_TAG_SHIFT 0
-+
-+#define IPQESS_TX_SVLAN 14
-+#define IPQESS_TX_INS_SVLAN 15
-+#define IPQESS_TX_SVLAN_TAG_SHIFT 16
-+
-+/* Tx Queue Packet Statistic Register */
-+#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
-+
-+#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
-+
-+/* Tx Queue Byte Statistic Register */
-+#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
-+
-+/* Load Balance Based Ring Offset Register */
-+#define IPQESS_REG_LB_RING 0x800
-+#define IPQESS_LB_RING_ENTRY_MASK 0xff
-+#define IPQESS_LB_RING_ID_MASK 0x7
-+#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
-+#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
-+#define IPQESS_LB_RING_ID_OFFSET 0
-+#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
-+#define IPQESS_LB_REG_VALUE 0x6040200
-+
-+/* Load Balance Priority Mapping Register */
-+#define IPQESS_REG_LB_PRI_START 0x804
-+#define IPQESS_REG_LB_PRI_END 0x810
-+#define IPQESS_LB_PRI_REG_INC 4
-+#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
-+#define IPQESS_LB_PRI_ENTRY_MASK 0xf
-+
-+/* RSS Priority Mapping Register */
-+#define IPQESS_REG_RSS_PRI 0x820
-+#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
-+#define IPQESS_RSS_RING_ID_MASK 0x7
-+#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
-+
-+/* RSS Indirection Register */
-+#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
-+#define IPQESS_NUM_IDT 16
-+#define IPQESS_RSS_IDT_VALUE 0x64206420
-+
-+/* Default RSS Ring Register */
-+#define IPQESS_REG_DEF_RSS 0x890
-+#define IPQESS_DEF_RSS_MASK 0x7
-+
-+/* RSS Hash Function Type Register */
-+#define IPQESS_REG_RSS_TYPE 0x894
-+#define IPQESS_RSS_TYPE_NONE 0x01
-+#define IPQESS_RSS_TYPE_IPV4TCP 0x02
-+#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
-+#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
-+#define IPQESS_RSS_TYPE_IPV6UDP 0x10
-+#define IPQESS_RSS_TYPE_IPV4 0x20
-+#define IPQESS_RSS_TYPE_IPV6 0x40
-+#define IPQESS_RSS_HASH_MODE_MASK 0x7f
-+
-+#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
-+
-+#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
-+
-+#define IPQESS_HASH_TYPE_START 0
-+#define IPQESS_HASH_TYPE_END 5
-+#define IPQESS_HASH_TYPE_SHIFT 12
-+
-+#define IPQESS_RFS_FLOW_ENTRIES 1024
-+#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
-+#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
-+
-+/* RFD Base Address Register */
-+#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
-+
-+/* RFD Index Register */
-+#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
-+#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
-+#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
-+#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
-+#define IPQESS_RFD_PROD_IDX_SHIFT 0
-+#define IPQESS_RFD_CONS_IDX_SHIFT 16
-+
-+/* Rx Descriptor Control Register */
-+#define IPQESS_REG_RX_DESC0 0xA10
-+#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
-+#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
-+#define IPQESS_RFD_RING_SIZE_SHIFT 0
-+#define IPQESS_RX_BUF_SIZE_SHIFT 16
-+
-+#define IPQESS_REG_RX_DESC1 0xA14
-+#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
-+#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
-+#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
-+#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
-+#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
-+#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
-+
-+/* RXQ Control Register */
-+#define IPQESS_REG_RXQ_CTRL 0xA18
-+#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
-+#define IPQESS_FIFO_THRESH_128_BYTE 0x0
-+#define IPQESS_FIFO_THRESH_64_BYTE 0x1
-+#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
-+#define IPQESS_RXQ_CTRL_EN_MASK			GENMASK(15, 8)
-+#define IPQESS_RXQ_CTRL_EN(__qid)		BIT(8 + (__qid))
-+
-+/* AXI Burst Size Config */
-+#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
-+#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
-+
-+/* Rx Statistics Register */
-+#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
-+#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
-+
-+/* WoL Pattern Length Register */
-+#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
-+#define IPQESS_WOL_PT_LEN_MASK 0xFF
-+#define IPQESS_WOL_PT0_LEN_SHIFT 0
-+#define IPQESS_WOL_PT1_LEN_SHIFT 8
-+#define IPQESS_WOL_PT2_LEN_SHIFT 16
-+#define IPQESS_WOL_PT3_LEN_SHIFT 24
-+
-+#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
-+#define IPQESS_WOL_PT4_LEN_SHIFT 0
-+#define IPQESS_WOL_PT5_LEN_SHIFT 8
-+#define IPQESS_WOL_PT6_LEN_SHIFT 16
-+
-+/* WoL Control Register */
-+#define IPQESS_REG_WOL_CTRL 0xC08
-+#define IPQESS_WOL_WK_EN 0x00000001
-+#define IPQESS_WOL_MG_EN 0x00000002
-+#define IPQESS_WOL_PT0_EN 0x00000004
-+#define IPQESS_WOL_PT1_EN 0x00000008
-+#define IPQESS_WOL_PT2_EN 0x00000010
-+#define IPQESS_WOL_PT3_EN 0x00000020
-+#define IPQESS_WOL_PT4_EN 0x00000040
-+#define IPQESS_WOL_PT5_EN 0x00000080
-+#define IPQESS_WOL_PT6_EN 0x00000100
-+
-+/* MAC Control Register */
-+#define IPQESS_REG_MAC_CTRL0 0xC20
-+#define IPQESS_REG_MAC_CTRL1 0xC24
-+
-+/* WoL Pattern Register */
-+#define IPQESS_REG_WOL_PATTERN_START 0x5000
-+#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
-+
-+/* TX descriptor fields */
-+#define IPQESS_TPD_HDR_SHIFT 0
-+#define IPQESS_TPD_PPPOE_EN 0x00000100
-+#define IPQESS_TPD_IP_CSUM_EN 0x00000200
-+#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
-+#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
-+#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
-+#define IPQESS_TPD_LSO_EN 0x00001000
-+#define IPQESS_TPD_LSO_V2_EN 0x00002000
-+/* The VLAN_TAGGED bit is not used in the publicly available
-+ * drivers. The definition has been stolen from the Atheros
-+ * 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
-+ * seems that it has the same meaning in regard to the EDMA
-+ * hardware.
-+ */
-+#define IPQESS_TPD_VLAN_TAGGED 0x00004000
-+#define IPQESS_TPD_IPV4_EN 0x00010000
-+#define IPQESS_TPD_MSS_MASK 0x1FFF
-+#define IPQESS_TPD_MSS_SHIFT 18
-+#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
-+
-+/* RRD descriptor fields */
-+#define IPQESS_RRD_NUM_RFD_MASK 0x000F
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
-+#define IPQESS_RRD_SVLAN 0x8000
-+#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF
-+
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
-+#define IPQESS_RRD_CVLAN 0x0001
-+#define IPQESS_RRD_DESC_VALID 0x8000
-+
-+#define IPQESS_RRD_PRIORITY_SHIFT 4
-+#define IPQESS_RRD_PRIORITY_MASK 0x7
-+#define IPQESS_RRD_PORT_TYPE_SHIFT 7
-+#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
-+
-+#define IPQESS_RRD_PORT_ID_MASK 0x7000
-+
-+#endif
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-@@ -0,0 +1,164 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/ethtool.h>
-+#include <linux/netdevice.h>
-+#include <linux/string.h>
-+#include <linux/phylink.h>
-+
-+#include "ipqess.h"
-+
-+struct ipqess_ethtool_stats {
-+	u8 string[ETH_GSTRING_LEN];
-+	u32 offset;
-+};
-+
-+#define IPQESS_STAT(m)    offsetof(struct ipqess_statistics, m)
-+#define DRVINFO_LEN	32
-+
-+static const struct ipqess_ethtool_stats ipqess_stats[] = {
-+	{"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
-+	{"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
-+	{"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
-+	{"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
-+	{"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
-+	{"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
-+	{"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
-+	{"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
-+	{"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
-+	{"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
-+	{"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
-+	{"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
-+	{"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
-+	{"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
-+	{"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
-+	{"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
-+	{"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
-+	{"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
-+	{"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
-+	{"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
-+	{"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
-+	{"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
-+	{"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
-+	{"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
-+	{"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
-+	{"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
-+	{"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
-+	{"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
-+	{"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
-+	{"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
-+	{"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
-+	{"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
-+	{"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
-+	{"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
-+	{"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
-+	{"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
-+	{"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
-+	{"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
-+	{"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
-+	{"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
-+	{"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
-+	{"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
-+	{"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
-+	{"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
-+	{"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
-+	{"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
-+	{"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
-+	{"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
-+	{"tx_desc_error", IPQESS_STAT(tx_desc_error)},
-+};
-+
-+static int ipqess_get_strset_count(struct net_device *netdev, int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return ARRAY_SIZE(ipqess_stats);
-+	default:
-+		netdev_dbg(netdev, "%s: Unsupported string set", __func__);
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+static void ipqess_get_strings(struct net_device *netdev, u32 stringset,
-+			       u8 *data)
-+{
-+	u8 *p = data;
-+	u32 i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+			ethtool_puts(&p, ipqess_stats[i].string);
-+		break;
-+	}
-+}
-+
-+static void ipqess_get_ethtool_stats(struct net_device *netdev,
-+				     struct ethtool_stats *stats,
-+				     uint64_t *data)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+	u32 *essstats = (u32 *)&ess->ipqess_stats;
-+	int i;
-+
-+	spin_lock(&ess->stats_lock);
-+
-+	ipqess_update_hw_stats(ess);
-+
-+	for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+		data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
-+
-+	spin_unlock(&ess->stats_lock);
-+}
-+
-+static void ipqess_get_drvinfo(struct net_device *dev,
-+			       struct ethtool_drvinfo *info)
-+{
-+	strscpy(info->driver, "qca_ipqess", DRVINFO_LEN);
-+	strscpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
-+}
-+
-+static int ipqess_get_link_ksettings(struct net_device *netdev,
-+				     struct ethtool_link_ksettings *cmd)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	return phylink_ethtool_ksettings_get(ess->phylink, cmd);
-+}
-+
-+static int ipqess_set_link_ksettings(struct net_device *netdev,
-+				     const struct ethtool_link_ksettings *cmd)
-+{
-+	struct ipqess *ess = netdev_priv(netdev);
-+
-+	return phylink_ethtool_ksettings_set(ess->phylink, cmd);
-+}
-+
-+static void ipqess_get_ringparam(struct net_device *netdev,
-+				 struct ethtool_ringparam *ring,
-+				 struct kernel_ethtool_ringparam *kernel_ering,
-+				 struct netlink_ext_ack *extack)
-+{
-+	ring->tx_max_pending = IPQESS_TX_RING_SIZE;
-+	ring->rx_max_pending = IPQESS_RX_RING_SIZE;
-+}
-+
-+static const struct ethtool_ops ipqesstool_ops = {
-+	.get_drvinfo = &ipqess_get_drvinfo,
-+	.get_link = &ethtool_op_get_link,
-+	.get_link_ksettings = &ipqess_get_link_ksettings,
-+	.set_link_ksettings = &ipqess_set_link_ksettings,
-+	.get_strings = &ipqess_get_strings,
-+	.get_sset_count = &ipqess_get_strset_count,
-+	.get_ethtool_stats = &ipqess_get_ethtool_stats,
-+	.get_ringparam = ipqess_get_ringparam,
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev)
-+{
-+	netdev->ethtool_ops = &ipqesstool_ops;
-+}
diff --git a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
deleted file mode 100644
index 1723f2c749..0000000000
--- a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
+++ /dev/null
@@ -1,238 +0,0 @@
-From a32e16b3c2fc1954ad6e09737439f60e5890278e Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:49 +0100
-Subject: [PATCH] net: dsa: add out-of-band tagging protocol
-
-This tagging protocol is designed for the situation where the link
-between the MAC and the Switch is designed such that the Destination
-Port, which is usually embedded in some part of the Ethernet Header, is
-sent out-of-band, and isn't present at all in the Ethernet frame.
-
-This can happen when the MAC and Switch are tightly integrated on an
-SoC, as is the case with the Qualcomm IPQ4019 for example, where the DSA
-tag is inserted directly into the DMA descriptors. In that case,
-the MAC driver is responsible for sending the tag to the switch using
-the out-of-band medium. To do so, the MAC driver needs to have the
-information of the destination port for that skb.
-
-Add a new tagging protocol based on SKB extensions to convey the
-information about the destination port to the MAC driver
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- Documentation/networking/dsa/dsa.rst | 13 +++++++-
- MAINTAINERS                          |  1 +
- include/linux/dsa/oob.h              | 16 +++++++++
- include/linux/skbuff.h               |  3 ++
- include/net/dsa.h                    |  2 ++
- net/core/skbuff.c                    | 10 ++++++
- net/dsa/Kconfig                      |  9 +++++
- net/dsa/Makefile                     |  1 +
- net/dsa/tag_oob.c                    | 49 ++++++++++++++++++++++++++++
- 9 files changed, 103 insertions(+), 1 deletion(-)
- create mode 100644 include/linux/dsa/oob.h
- create mode 100644 net/dsa/tag_oob.c
-
---- a/Documentation/networking/dsa/dsa.rst
-+++ b/Documentation/networking/dsa/dsa.rst
-@@ -66,7 +66,8 @@ Switch tagging protocols
- ------------------------
- 
- DSA supports many vendor-specific tagging protocols, one software-defined
--tagging protocol, and a tag-less mode as well (``DSA_TAG_PROTO_NONE``).
-+tagging protocol, a tag-less mode as well (``DSA_TAG_PROTO_NONE``) and an
-+out-of-band tagging protocol (``DSA_TAG_PROTO_OOB``).
- 
- The exact format of the tag protocol is vendor specific, but in general, they
- all contain something which:
-@@ -217,6 +218,16 @@ receive all frames regardless of the val
- setting the ``promisc_on_master`` property of the ``struct dsa_device_ops``.
- Note that this assumes a DSA-unaware master driver, which is the norm.
- 
-+Some SoCs have a tight integration between the conduit network interface and the
-+embedded switch, such that the DSA tag isn't transmitted in the packet data,
-+but through another media, using so-called out-of-band tagging. In that case,
-+the host MAC driver is in charge of transmitting the tag to the switch.
-+An example is the IPQ4019 SoC, that transmits the tag between the ipqess
-+ethernet controller and the qca8k switch using the DMA descriptor. In that
-+configuration, tag-chaining is permitted, but the OOB tag will always be the
-+top-most switch in the tree. The tagger (``DSA_TAG_PROTO_OOB``) uses skb
-+extensions to transmit the tag to and from the MAC driver.
-+
- Master network devices
- ----------------------
- 
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17081,6 +17081,7 @@ L:	netdev@vger.kernel.org
- S:	Maintained
- F:	Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
- F:	drivers/net/ethernet/qualcomm/ipqess/
-+F:	net/dsa/tag_oob.c
- 
- QUALCOMM ETHQOS ETHERNET DRIVER
- M:	Vinod Koul <vkoul@kernel.org>
---- /dev/null
-+++ b/include/linux/dsa/oob.h
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only
-+ * Copyright (C) 2022 Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ */
-+
-+#ifndef _NET_DSA_OOB_H
-+#define _NET_DSA_OOB_H
-+
-+#include <linux/skbuff.h>
-+
-+struct dsa_oob_tag_info {
-+	u16 port;
-+};
-+
-+int dsa_oob_tag_push(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+int dsa_oob_tag_pop(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+#endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -4594,6 +4594,9 @@ enum skb_ext_id {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- 	SKB_EXT_MCTP,
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+	SKB_EXT_DSA_OOB,
-+#endif
- 	SKB_EXT_NUM, /* must be last */
- };
- 
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -55,6 +55,7 @@ struct phylink_link_state;
- #define DSA_TAG_PROTO_RTL8_4T_VALUE		25
- #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE		26
- #define DSA_TAG_PROTO_LAN937X_VALUE		27
-+#define DSA_TAG_PROTO_OOB_VALUE			28
- 
- enum dsa_tag_protocol {
- 	DSA_TAG_PROTO_NONE		= DSA_TAG_PROTO_NONE_VALUE,
-@@ -85,6 +86,7 @@ enum dsa_tag_protocol {
- 	DSA_TAG_PROTO_RTL8_4T		= DSA_TAG_PROTO_RTL8_4T_VALUE,
- 	DSA_TAG_PROTO_RZN1_A5PSW	= DSA_TAG_PROTO_RZN1_A5PSW_VALUE,
- 	DSA_TAG_PROTO_LAN937X		= DSA_TAG_PROTO_LAN937X_VALUE,
-+	DSA_TAG_PROTO_OOB		= DSA_TAG_PROTO_OOB_VALUE,
- };
- 
- struct dsa_switch;
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -62,8 +62,12 @@
- #include <linux/mpls.h>
- #include <linux/kcov.h>
- #include <linux/if.h>
-+#ifdef CONFIG_NET_DSA_TAG_OOB
-+#include <linux/dsa/oob.h>
-+#endif
- 
- #include <net/protocol.h>
-+#include <net/dsa.h>
- #include <net/dst.h>
- #include <net/sock.h>
- #include <net/checksum.h>
-@@ -4517,6 +4521,9 @@ static const u8 skb_ext_type_len[] = {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- 	[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+	[SKB_EXT_DSA_OOB] = SKB_EXT_CHUNKSIZEOF(struct dsa_oob_tag_info),
-+#endif
- };
- 
- static __always_inline unsigned int skb_ext_total_length(void)
-@@ -4537,6 +4544,9 @@ static __always_inline unsigned int skb_
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- 		skb_ext_type_len[SKB_EXT_MCTP] +
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+		skb_ext_type_len[SKB_EXT_DSA_OOB] +
-+#endif
- 		0;
- }
- 
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -113,6 +113,15 @@ config NET_DSA_TAG_OCELOT_8021Q
- 	  this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
- 	  use with tc-flower.
- 
-+config NET_DSA_TAG_OOB
-+	select SKB_EXTENSIONS
-+	tristate "Tag driver for Out-of-band tagging drivers"
-+	help
-+	  Say Y or M if you want to enable support for pairs of embedded
-+	  switches and host MAC drivers which perform demultiplexing and
-+	  packet steering to ports using out of band metadata processed
-+	  by the DSA master, rather than tags present in the packets.
-+
- config NET_DSA_TAG_QCA
- 	tristate "Tag driver for Qualcomm Atheros QCA8K switches"
- 	help
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -22,6 +22,7 @@ obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag
- obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
-+obj-$(CONFIG_NET_DSA_TAG_OOB) += tag_oob.o
- obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
- obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
- obj-$(CONFIG_NET_DSA_TAG_RTL8_4) += tag_rtl8_4.o
---- /dev/null
-+++ b/net/dsa/tag_oob.c
-@@ -0,0 +1,49 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+/* Copyright (c) 2022, Maxime Chevallier <maxime.chevallier@bootlin.com> */
-+
-+#include <linux/bitfield.h>
-+#include <linux/dsa/oob.h>
-+#include <linux/skbuff.h>
-+
-+#include "dsa_priv.h"
-+
-+static struct sk_buff *oob_tag_xmit(struct sk_buff *skb,
-+				    struct net_device *dev)
-+{
-+	struct dsa_oob_tag_info *tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+	struct dsa_port *dp = dsa_slave_to_port(dev);
-+
-+	tag_info->port = dp->index;
-+
-+	return skb;
-+}
-+
-+static struct sk_buff *oob_tag_rcv(struct sk_buff *skb,
-+				   struct net_device *dev)
-+{
-+	struct dsa_oob_tag_info *tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+
-+	if (!tag_info)
-+		return NULL;
-+
-+	skb->dev = dsa_master_find_slave(dev, 0, tag_info->port);
-+	if (!skb->dev)
-+		return NULL;
-+
-+	return skb;
-+}
-+
-+static const struct dsa_device_ops oob_tag_dsa_ops = {
-+	.name	= "oob",
-+	.proto	= DSA_TAG_PROTO_OOB,
-+	.xmit	= oob_tag_xmit,
-+	.rcv	= oob_tag_rcv,
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("DSA tag driver for out-of-band tagging");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OOB);
-+
-+module_dsa_tag_driver(oob_tag_dsa_ops);
diff --git a/target/linux/ipq40xx/patches-6.1/702-net-ipqess-Add-out-of-band-DSA-tagging-support.patch b/target/linux/ipq40xx/patches-6.1/702-net-ipqess-Add-out-of-band-DSA-tagging-support.patch
deleted file mode 100644
index ac0718ba2c..0000000000
--- a/target/linux/ipq40xx/patches-6.1/702-net-ipqess-Add-out-of-band-DSA-tagging-support.patch
+++ /dev/null
@@ -1,173 +0,0 @@
-From 4975e2b3f1d37bba04f262784cef0d5b7e0a30a4 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:50 +0100
-Subject: [PATCH] net: ipqess: Add out-of-band DSA tagging support
-
-On the IPQ4019, there's an 5 ports switch connected to the CPU through
-the IPQESS Ethernet controller. The way the DSA tag is sent-out to that
-switch is through the DMA descriptor, due to how tightly it is
-integrated with the switch.
-
-We use the out-of-band tagging protocol by getting the source
-port from the descriptor, push it into the skb extensions, and have the
-tagger pull it to infer the destination netdev. The reverse process is
-done on the TX side, where the driver pulls the tag from the skb and
-builds the descriptor accordingly.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- drivers/net/ethernet/qualcomm/Kconfig         |  1 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 64 ++++++++++++++++++-
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h |  4 ++
- 3 files changed, 68 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -64,6 +64,7 @@ config QCOM_IPQ4019_ESS_EDMA
- 	tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
- 	depends on (OF && ARCH_QCOM) || COMPILE_TEST
- 	select PHYLINK
-+	select NET_DSA_TAG_OOB
- 	help
- 	  This driver supports the Qualcomm Atheros IPQ40xx built-in
- 	  ESS EDMA ethernet controller.
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -9,6 +9,7 @@
- 
- #include <linux/bitfield.h>
- #include <linux/clk.h>
-+#include <linux/dsa/oob.h>
- #include <linux/if_vlan.h>
- #include <linux/interrupt.h>
- #include <linux/module.h>
-@@ -22,6 +23,7 @@
- #include <linux/skbuff.h>
- #include <linux/vmalloc.h>
- #include <net/checksum.h>
-+#include <net/dsa.h>
- #include <net/ip6_checksum.h>
- 
- #include "ipqess.h"
-@@ -327,6 +329,7 @@ static int ipqess_rx_poll(struct ipqess_
- 	tail &= IPQESS_RFD_CONS_IDX_MASK;
- 
- 	while (done < budget) {
-+		struct dsa_oob_tag_info *tag_info;
- 		struct ipqess_rx_desc *rd;
- 		struct sk_buff *skb;
- 
-@@ -406,6 +409,12 @@ static int ipqess_rx_poll(struct ipqess_
- 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
- 					       le16_to_cpu(rd->rrd4));
- 
-+		if (likely(rx_ring->ess->dsa_ports)) {
-+			tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+			tag_info->port = FIELD_GET(IPQESS_RRD_PORT_ID_MASK,
-+						   le16_to_cpu(rd->rrd1));
-+		}
-+
- 		napi_gro_receive(&rx_ring->napi_rx, skb);
- 
- 		rx_ring->ess->stats.rx_packets++;
-@@ -706,6 +715,23 @@ static void ipqess_rollback_tx(struct ip
- 	tx_ring->head = start_index;
- }
- 
-+static void ipqess_process_dsa_tag_sh(struct ipqess *ess, struct sk_buff *skb,
-+				      u32 *word3)
-+{
-+	struct dsa_oob_tag_info *tag_info;
-+
-+	if (unlikely(!ess->dsa_ports))
-+		return;
-+
-+	tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+	if (!tag_info)
-+		return;
-+
-+	*word3 |= tag_info->port << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+	*word3 |= BIT(IPQESS_TPD_FROM_CPU_SHIFT);
-+	*word3 |= 0x3e << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+}
-+
- static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
- 				  struct sk_buff *skb)
- {
-@@ -716,6 +742,8 @@ static int ipqess_tx_map_and_fill(struct
- 	u16 len;
- 	int i;
- 
-+	ipqess_process_dsa_tag_sh(tx_ring->ess, skb, &word3);
-+
- 	if (skb_is_gso(skb)) {
- 		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
- 			lso_word1 |= IPQESS_TPD_IPV4_EN;
-@@ -917,6 +945,33 @@ static const struct net_device_ops ipqes
- 	.ndo_tx_timeout		= ipqess_tx_timeout,
- };
- 
-+static int ipqess_netdevice_event(struct notifier_block *nb,
-+				  unsigned long event, void *ptr)
-+{
-+	struct ipqess *ess = container_of(nb, struct ipqess, netdev_notifier);
-+	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-+	struct netdev_notifier_changeupper_info *info;
-+
-+	if (dev != ess->netdev)
-+		return NOTIFY_DONE;
-+
-+	switch (event) {
-+	case NETDEV_CHANGEUPPER:
-+		info = ptr;
-+
-+		if (!dsa_slave_dev_check(info->upper_dev))
-+			return NOTIFY_DONE;
-+
-+		if (info->linking)
-+			ess->dsa_ports++;
-+		else
-+			ess->dsa_ports--;
-+
-+		return NOTIFY_DONE;
-+	}
-+	return NOTIFY_OK;
-+}
-+
- static void ipqess_hw_stop(struct ipqess *ess)
- {
- 	int i;
-@@ -1184,12 +1239,19 @@ static int ipqess_axi_probe(struct platf
- 		netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
- 	}
- 
--	err = register_netdev(netdev);
-+	ess->netdev_notifier.notifier_call = ipqess_netdevice_event;
-+	err = register_netdevice_notifier(&ess->netdev_notifier);
- 	if (err)
- 		goto err_hw_stop;
- 
-+	err = register_netdev(netdev);
-+	if (err)
-+		goto err_notifier_unregister;
-+
- 	return 0;
- 
-+err_notifier_unregister:
-+	unregister_netdevice_notifier(&ess->netdev_notifier);
- err_hw_stop:
- 	ipqess_hw_stop(ess);
- 
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -171,6 +171,10 @@ struct ipqess {
- 	struct platform_device *pdev;
- 	struct phylink *phylink;
- 	struct phylink_config phylink_config;
-+
-+	struct notifier_block netdev_notifier;
-+	int dsa_ports;
-+
- 	struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
- 
- 	struct ipqess_statistics ipqess_stats;
diff --git a/target/linux/ipq40xx/patches-6.1/703-net-qualcomm-ipqess-release-IRQ-s-on-network-device-.patch b/target/linux/ipq40xx/patches-6.1/703-net-qualcomm-ipqess-release-IRQ-s-on-network-device-.patch
deleted file mode 100644
index bd890e5c71..0000000000
--- a/target/linux/ipq40xx/patches-6.1/703-net-qualcomm-ipqess-release-IRQ-s-on-network-device-.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 5f15f7f170c76220dfd36cb9037d7848d1fc4aaf Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:30:50 +0200
-Subject: [PATCH] net: qualcomm: ipqess: release IRQ-s on network device stop
-
-Currently, IPQESS driver is obtaining the IRQ-s during ndo_open, but they
-are never freed as they are device managed.
-
-However, it is not enough for them to be released when device is removed
-as the same network device can be stopped and started multiple times which
-on the second start would lead to IRQ request to fail with -EBUSY as they
-have already been requested before and are not of the shared type with:
-[   34.480769] ipqess-edma c080000.ethernet eth0: Link is Down
-[   34.488070] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.488131] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.494527] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.502892] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.508137] qca8k-ipq4019 c000000.switch lan1: failed to open master eth0
-[   34.518966] br-lan: port 1(lan1) entered blocking state
-[   34.525165] br-lan: port 1(lan1) entered disabled state
-[   34.530633] device lan1 entered promiscuous mode
-[   34.548598] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.548660] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.553111] qca8k-ipq4019 c000000.switch lan2: failed to open master eth0
-[   34.563841] br-lan: port 2(lan2) entered blocking state
-[   34.570083] br-lan: port 2(lan2) entered disabled state
-[   34.575530] device lan2 entered promiscuous mode
-[   34.587067] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.587132] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.591579] qca8k-ipq4019 c000000.switch lan3: failed to open master eth0
-[   34.602451] br-lan: port 3(lan3) entered blocking state
-[   34.608496] br-lan: port 3(lan3) entered disabled state
-[   34.614084] device lan3 entered promiscuous mode
-[   34.626405] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.626468] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.630871] qca8k-ipq4019 c000000.switch lan4: failed to open master eth0
-[   34.641689] br-lan: port 4(lan4) entered blocking state
-[   34.647834] br-lan: port 4(lan4) entered disabled state
-[   34.653455] device lan4 entered promiscuous mode
-[   34.667282] ipqess-edma c080000.ethernet eth0: ipqess_open
-[   34.667364] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[   34.671830] qca8k-ipq4019 c000000.switch wan: failed to open master eth0
-
-So, lets free the IRQ-s on ndo_stop after stopping NAPI and HW IRQ-s.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -636,9 +636,22 @@ static int ipqess_stop(struct net_device
- 	netif_tx_stop_all_queues(netdev);
- 	phylink_stop(ess->phylink);
- 	ipqess_irq_disable(ess);
-+
- 	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+		int qid;
-+
- 		napi_disable(&ess->tx_ring[i].napi_tx);
- 		napi_disable(&ess->rx_ring[i].napi_rx);
-+
-+		qid = ess->tx_ring[i].idx;
-+		devm_free_irq(&netdev->dev,
-+			      ess->tx_irq[qid],
-+			      &ess->tx_ring[i]);
-+
-+		qid = ess->rx_ring[i].idx;
-+		devm_free_irq(&netdev->dev,
-+			      ess->rx_irq[qid],
-+			      &ess->rx_ring[i]);
- 	}
- 
- 	return 0;
diff --git a/target/linux/ipq40xx/patches-6.1/704-net-qualcomm-ipqess-enable-threaded-NAPI-by-default.patch b/target/linux/ipq40xx/patches-6.1/704-net-qualcomm-ipqess-enable-threaded-NAPI-by-default.patch
deleted file mode 100644
index cd58677284..0000000000
--- a/target/linux/ipq40xx/patches-6.1/704-net-qualcomm-ipqess-enable-threaded-NAPI-by-default.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 9fa4a57a65e270e4d579cace4de5c438f46c7d12 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:38:44 +0200
-Subject: [PATCH] net: qualcomm: ipqess: enable threaded NAPI by default
-
-Threaded NAPI provides a nice performance boost, so lets enable it by
-default.
-
-We do however need to move the __napi_schedule() after HW IRQ has been
-cleared in order to avoid concurency issues.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -530,9 +530,9 @@ static irqreturn_t ipqess_interrupt_tx(i
- 	struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
- 
- 	if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
--		__napi_schedule(&tx_ring->napi_tx);
- 		ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
- 			   0x0);
-+		__napi_schedule(&tx_ring->napi_tx);
- 	}
- 
- 	return IRQ_HANDLED;
-@@ -543,9 +543,9 @@ static irqreturn_t ipqess_interrupt_rx(i
- 	struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
- 
- 	if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
--		__napi_schedule(&rx_ring->napi_rx);
- 		ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
- 			   0x0);
-+		__napi_schedule(&rx_ring->napi_rx);
- 	}
- 
- 	return IRQ_HANDLED;
-@@ -1261,6 +1261,8 @@ static int ipqess_axi_probe(struct platf
- 	if (err)
- 		goto err_notifier_unregister;
- 
-+	dev_set_threaded(netdev, true);
-+
- 	return 0;
- 
- err_notifier_unregister:
diff --git a/target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch b/target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch
deleted file mode 100644
index 27bdebdb93..0000000000
--- a/target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:51 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
- Ethernet controller
-
-The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
-connected to the CPU through the internal IPQESS Ethernet controller.
-
-Add support for this internal interface, which is internally connected to a
-modified version of the QCA8K Ethernet switch.
-
-This Ethernet controller only support a specific internal interface mode
-for connection to the switch.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,54 @@
- 			status = "disabled";
- 		};
- 
-+		gmac: ethernet@c080000 {
-+			compatible = "qcom,ipq4019-ess-edma";
-+			reg = <0xc080000 0x8000>;
-+			resets = <&gcc ESS_RESET>;
-+			reset-names = "ess";
-+			clocks = <&gcc GCC_ESS_CLK>;
-+			clock-names = "ess";
-+			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
-+			phy-mode = "internal";
-+			status = "disabled";
-+			fixed-link {
-+				speed = <1000>;
-+				full-duplex;
-+				pause;
-+			};
-+		};
-+
- 		mdio: mdio@90000 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
diff --git a/target/linux/ipq40xx/patches-6.1/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch b/target/linux/ipq40xx/patches-6.1/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
deleted file mode 100644
index 992884cf31..0000000000
--- a/target/linux/ipq40xx/patches-6.1/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
+++ /dev/null
@@ -1,1132 +0,0 @@
-From a38126870488398932e017dd9d76174b4aadbbbb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Sat, 10 Sep 2022 15:46:09 +0200
-Subject: [PATCH] net: dsa: qca8k: add IPQ4019 built-in switch support
-
-Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
-
-It shares most of the stuff with its external counterpart, however it is
-modified for the SoC.
-Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
-instead of 7.
-It also has no built-in PHY-s but rather requires external PSGMII based
-companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
-out calibration before using them.
-PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
-unfortunately requires some magic values as the datasheet doesnt document
-the bits that are being set or the register at all.
-
-Since its built-in it is MMIO like other peripherals and doesn't have its
-own MDIO bus but depends on the SoC provided one.
-
-CPU connection is at Port 0 and it uses some kind of a internal connection
-and no traditional RGMII/SGMII.
-
-It also doesn't use in-band tagging like other qca8k switches so a out of
-band based tagger is used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/dsa/qca/Kconfig         |   8 +
- drivers/net/dsa/qca/Makefile        |   1 +
- drivers/net/dsa/qca/qca8k-common.c  |   6 +-
- drivers/net/dsa/qca/qca8k-ipq4019.c | 948 ++++++++++++++++++++++++++++
- drivers/net/dsa/qca/qca8k.h         |  56 ++
- 5 files changed, 1016 insertions(+), 3 deletions(-)
- create mode 100644 drivers/net/dsa/qca/qca8k-ipq4019.c
-
---- a/drivers/net/dsa/qca/Kconfig
-+++ b/drivers/net/dsa/qca/Kconfig
-@@ -23,3 +23,11 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
- 	help
- 	  This enabled support for LEDs present on the Qualcomm Atheros
- 	  QCA8K Ethernet switch chips.
-+
-+config NET_DSA_QCA8K_IPQ4019
-+	tristate "Qualcomm Atheros IPQ4019 Ethernet switch support"
-+	select NET_DSA_TAG_OOB
-+	select REGMAP_MMIO
-+	help
-+	  This enables support for the switch built-into Qualcomm Atheros
-+	  IPQ4019 SoCs.
---- a/drivers/net/dsa/qca/Makefile
-+++ b/drivers/net/dsa/qca/Makefile
-@@ -5,3 +5,4 @@ qca8k-y 			+= qca8k-common.o qca8k-8xxx.
- ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT
- qca8k-y				+= qca8k-leds.o
- endif
-+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019)	+= qca8k-ipq4019.o qca8k-common.o
---- a/drivers/net/dsa/qca/qca8k-common.c
-+++ b/drivers/net/dsa/qca/qca8k-common.c
-@@ -412,7 +412,7 @@ static int qca8k_vlan_del(struct qca8k_p
- 
- 	/* Check if we're the last member to be removed */
- 	del = true;
--	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+	for (i = 0; i < priv->ds->num_ports; i++) {
- 		mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
- 
- 		if ((reg & mask) != mask) {
-@@ -653,7 +653,7 @@ int qca8k_port_bridge_join(struct dsa_sw
- 	cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
- 	port_mask = BIT(cpu_port);
- 
--	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+	for (i = 0; i < ds->num_ports; i++) {
- 		if (dsa_is_cpu_port(ds, i))
- 			continue;
- 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
-@@ -685,7 +685,7 @@ void qca8k_port_bridge_leave(struct dsa_
- 
- 	cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
- 
--	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+	for (i = 0; i < ds->num_ports; i++) {
- 		if (dsa_is_cpu_port(ds, i))
- 			continue;
- 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
---- /dev/null
-+++ b/drivers/net/dsa/qca/qca8k-ipq4019.c
-@@ -0,0 +1,948 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
-+ * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2016 John Crispin <john@phrozen.org>
-+ * Copyright (c) 2022 Robert Marko <robert.marko@sartura.hr>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+#include <linux/netdevice.h>
-+#include <linux/bitfield.h>
-+#include <linux/regmap.h>
-+#include <net/dsa.h>
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_platform.h>
-+#include <linux/mdio.h>
-+#include <linux/phylink.h>
-+
-+#include "qca8k.h"
-+
-+static struct regmap_config qca8k_ipq4019_regmap_config = {
-+	.reg_bits = 32,
-+	.val_bits = 32,
-+	.reg_stride = 4,
-+	.max_register = 0x16ac, /* end MIB - Port6 range */
-+	.rd_table = &qca8k_readable_table,
-+};
-+
-+static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
-+	.name = "psgmii-phy",
-+	.reg_bits = 32,
-+	.val_bits = 32,
-+	.reg_stride = 4,
-+	.max_register = 0x7fc,
-+};
-+
-+static enum dsa_tag_protocol
-+qca8k_ipq4019_get_tag_protocol(struct dsa_switch *ds, int port,
-+			       enum dsa_tag_protocol mp)
-+{
-+	return DSA_TAG_PROTO_OOB;
-+}
-+
-+static struct phylink_pcs *
-+qca8k_ipq4019_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
-+				     phy_interface_t interface)
-+{
-+	struct qca8k_priv *priv = ds->priv;
-+	struct phylink_pcs *pcs = NULL;
-+
-+	switch (interface) {
-+	case PHY_INTERFACE_MODE_PSGMII:
-+		switch (port) {
-+		case 0:
-+			pcs = &priv->pcs_port_0.pcs;
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return pcs;
-+}
-+
-+static int qca8k_ipq4019_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+				    phy_interface_t interface,
-+				    const unsigned long *advertising,
-+				    bool permit_pause_to_mac)
-+{
-+	return 0;
-+}
-+
-+static void qca8k_ipq4019_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+}
-+
-+static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
-+{
-+	return container_of(pcs, struct qca8k_pcs, pcs);
-+}
-+
-+static void qca8k_ipq4019_pcs_get_state(struct phylink_pcs *pcs,
-+					struct phylink_link_state *state)
-+{
-+	struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
-+	int port = pcs_to_qca8k_pcs(pcs)->port;
-+	u32 reg;
-+	int ret;
-+
-+	ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
-+	if (ret < 0) {
-+		state->link = false;
-+		return;
-+	}
-+
-+	state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
-+	state->an_complete = state->link;
-+	state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
-+							   DUPLEX_HALF;
-+
-+	switch (reg & QCA8K_PORT_STATUS_SPEED) {
-+	case QCA8K_PORT_STATUS_SPEED_10:
-+		state->speed = SPEED_10;
-+		break;
-+	case QCA8K_PORT_STATUS_SPEED_100:
-+		state->speed = SPEED_100;
-+		break;
-+	case QCA8K_PORT_STATUS_SPEED_1000:
-+		state->speed = SPEED_1000;
-+		break;
-+	default:
-+		state->speed = SPEED_UNKNOWN;
-+		break;
-+	}
-+
-+	if (reg & QCA8K_PORT_STATUS_RXFLOW)
-+		state->pause |= MLO_PAUSE_RX;
-+	if (reg & QCA8K_PORT_STATUS_TXFLOW)
-+		state->pause |= MLO_PAUSE_TX;
-+}
-+
-+static const struct phylink_pcs_ops qca8k_pcs_ops = {
-+	.pcs_get_state = qca8k_ipq4019_pcs_get_state,
-+	.pcs_config = qca8k_ipq4019_pcs_config,
-+	.pcs_an_restart = qca8k_ipq4019_pcs_an_restart,
-+};
-+
-+static void qca8k_ipq4019_setup_pcs(struct qca8k_priv *priv,
-+				    struct qca8k_pcs *qpcs,
-+				    int port)
-+{
-+	qpcs->pcs.ops = &qca8k_pcs_ops;
-+
-+	/* We don't have interrupts for link changes, so we need to poll */
-+	qpcs->pcs.poll = true;
-+	qpcs->priv = priv;
-+	qpcs->port = port;
-+}
-+
-+static void qca8k_ipq4019_phylink_get_caps(struct dsa_switch *ds, int port,
-+					   struct phylink_config *config)
-+{
-+	switch (port) {
-+	case 0: /* CPU port */
-+		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+			  config->supported_interfaces);
-+		break;
-+
-+	case 1:
-+	case 2:
-+	case 3:
-+		__set_bit(PHY_INTERFACE_MODE_PSGMII,
-+			  config->supported_interfaces);
-+		break;
-+	case 4:
-+	case 5:
-+		phy_interface_set_rgmii(config->supported_interfaces);
-+		__set_bit(PHY_INTERFACE_MODE_PSGMII,
-+			  config->supported_interfaces);
-+		break;
-+	}
-+
-+	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
-+		MAC_10 | MAC_100 | MAC_1000FD;
-+
-+	config->legacy_pre_march2020 = false;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_down(struct dsa_switch *ds, int port,
-+				    unsigned int mode,
-+				    phy_interface_t interface)
-+{
-+	struct qca8k_priv *priv = ds->priv;
-+
-+	qca8k_port_set_status(priv, port, 0);
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_up(struct dsa_switch *ds, int port,
-+				  unsigned int mode, phy_interface_t interface,
-+				  struct phy_device *phydev, int speed,
-+				  int duplex, bool tx_pause, bool rx_pause)
-+{
-+	struct qca8k_priv *priv = ds->priv;
-+	u32 reg;
-+
-+	if (phylink_autoneg_inband(mode)) {
-+		reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+	} else {
-+		switch (speed) {
-+		case SPEED_10:
-+			reg = QCA8K_PORT_STATUS_SPEED_10;
-+			break;
-+		case SPEED_100:
-+			reg = QCA8K_PORT_STATUS_SPEED_100;
-+			break;
-+		case SPEED_1000:
-+			reg = QCA8K_PORT_STATUS_SPEED_1000;
-+			break;
-+		default:
-+			reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+			break;
-+		}
-+
-+		if (duplex == DUPLEX_FULL)
-+			reg |= QCA8K_PORT_STATUS_DUPLEX;
-+
-+		if (rx_pause || dsa_is_cpu_port(ds, port))
-+			reg |= QCA8K_PORT_STATUS_RXFLOW;
-+
-+		if (tx_pause || dsa_is_cpu_port(ds, port))
-+			reg |= QCA8K_PORT_STATUS_TXFLOW;
-+	}
-+
-+	reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
-+
-+	qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
-+}
-+
-+static int psgmii_vco_calibrate(struct qca8k_priv *priv)
-+{
-+	int val, ret;
-+
-+	if (!priv->psgmii_ethphy) {
-+		dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
-+		return -ENODEV;
-+	}
-+
-+	/* Fix PSGMII RX 20bit */
-+	ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+	/* Reset PHY PSGMII */
-+	ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
-+	/* Release PHY PSGMII reset */
-+	ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+
-+	/* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
-+	ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
-+					MDIO_MMD_PMAPMD,
-+					0x28, val,
-+					(val & BIT(0)),
-+					10000, 1000000,
-+					false);
-+	if (ret) {
-+		dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
-+		return ret;
-+	}
-+	mdelay(50);
-+
-+	/* Freeze PSGMII RX CDR */
-+	ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
-+
-+	/* Start PSGMIIPHY VCO PLL calibration */
-+	ret = regmap_set_bits(priv->psgmii,
-+			PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
-+			PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
-+
-+	/* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
-+	ret = regmap_read_poll_timeout(priv->psgmii,
-+				       PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
-+				       val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
-+				       10000, 1000000);
-+	if (ret) {
-+		dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
-+		return ret;
-+	}
-+	mdelay(50);
-+
-+	/* Release PSGMII RX CDR */
-+	ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
-+	/* Release PSGMII RX 20bit */
-+	ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
-+	mdelay(200);
-+
-+	return ret;
-+}
-+
-+static void
-+qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
-+{
-+	u32 val = QCA8K_PORT_LOOKUP_LOOPBACK_EN;
-+
-+	if (on == 0)
-+		val = 0;
-+
-+	qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+		  QCA8K_PORT_LOOKUP_LOOPBACK_EN, val);
-+}
-+
-+static int
-+qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
-+{
-+	int a;
-+	u16 status;
-+
-+	for (a = 0; a < 100; a++) {
-+		status = phy_read(phy, MII_QCA8075_SSTATUS);
-+		status &= QCA8075_PHY_SPEC_STATUS_LINK;
-+		status = !!status;
-+		if (status == need_status)
-+			return 0;
-+		mdelay(8);
-+	}
-+
-+	return -1;
-+}
-+
-+static void
-+qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
-+			  int sw_port, int on)
-+{
-+	if (on) {
-+		phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
-+		phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+		qca8k_wait_for_phy_link_state(phy, 0);
-+		qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+		phy_write(phy, MII_BMCR,
-+			BMCR_SPEED1000 |
-+			BMCR_FULLDPLX |
-+			BMCR_LOOPBACK);
-+		qca8k_wait_for_phy_link_state(phy, 1);
-+		qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
-+			QCA8K_PORT_STATUS_SPEED_1000 |
-+			QCA8K_PORT_STATUS_TXMAC |
-+			QCA8K_PORT_STATUS_RXMAC |
-+			QCA8K_PORT_STATUS_DUPLEX);
-+		qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+			QCA8K_PORT_LOOKUP_STATE_FORWARD,
-+			QCA8K_PORT_LOOKUP_STATE_FORWARD);
-+	} else { /* off */
-+		qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+		qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+			QCA8K_PORT_LOOKUP_STATE_DISABLED,
-+			QCA8K_PORT_LOOKUP_STATE_DISABLED);
-+		phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
-+		/* turn off the power of the phys - so that unused
-+			 ports do not raise links */
-+		phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+	}
-+}
-+
-+static void
-+qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
-+		       int pkts_num, int on)
-+{
-+	if (on) {
-+		/* enable CRC checker and packets counters */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
-+			QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
-+		qca8k_wait_for_phy_link_state(phy, 1);
-+		/* packet number */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
-+		/* pkt size - 1504 bytes + 20 bytes */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
-+	} else { /* off */
-+		/* packet number */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
-+		/* disable CRC checker and packet counter */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+		/* disable traffic gen */
-+		phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
-+	}
-+}
-+
-+static void
-+qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
-+{
-+	int val;
-+	/* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
-+	phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+				  val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
-+				  50000, 1000000, true);
-+}
-+
-+static void
-+qca8k_start_phy_pkt_gen(struct phy_device *phy)
-+{
-+	/* start traffic gen */
-+	phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+		      QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
-+}
-+
-+static int
-+qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
-+{
-+	struct phy_device *phy;
-+	phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
-+		0, 0, NULL);
-+	if (!phy) {
-+		dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
-+			QCA8075_MDIO_BRDCST_PHY_ADDR);
-+		return -ENODEV;
-+	}
-+
-+	qca8k_start_phy_pkt_gen(phy);
-+
-+	phy_device_free(phy);
-+	return 0;
-+}
-+
-+static int
-+qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
-+{
-+	u32 tx_ok, tx_error;
-+	u32 rx_ok, rx_error;
-+	u32 tx_ok_high16;
-+	u32 rx_ok_high16;
-+	u32 tx_all_ok, rx_all_ok;
-+
-+	/* check counters */
-+	tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
-+	tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
-+	tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
-+	rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
-+	rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
-+	rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
-+	tx_all_ok = tx_ok + (tx_ok_high16 << 16);
-+	rx_all_ok = rx_ok + (rx_ok_high16 << 16);
-+
-+	if (tx_all_ok < pkts_num)
-+		return -1;
-+	if(rx_all_ok < pkts_num)
-+		return -2;
-+	if(tx_error)
-+		return -3;
-+	if(rx_error)
-+		return -4;
-+	return 0; /* test is ok */
-+}
-+
-+static
-+void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
-+				      struct phy_device *phy, int on)
-+{
-+	u32 val;
-+
-+	val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
-+
-+	if (on == 0)
-+		val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+	else
-+		val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+
-+	phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
-+}
-+
-+static int
-+qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
-+			       int port, int test_phase)
-+{
-+	int res = 0;
-+	const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
-+
-+	if (test_phase == 1) { /* start test preps */
-+		qca8k_phy_loopback_on_off(priv, phy, port, 1);
-+		qca8k_switch_port_loopback_on_off(priv, port, 1);
-+		qca8k_phy_broadcast_write_on_off(priv, phy, 1);
-+		qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
-+	} else if (test_phase == 2) {
-+		/* wait for test results, collect it and cleanup */
-+		qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
-+		res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
-+		qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
-+		qca8k_phy_broadcast_write_on_off(priv, phy, 0);
-+		qca8k_switch_port_loopback_on_off(priv, port, 0);
-+		qca8k_phy_loopback_on_off(priv, phy, port, 0);
-+	}
-+
-+	return res;
-+}
-+
-+static int
-+qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
-+{
-+	struct device_node *dn = priv->dev->of_node;
-+	struct device_node *ports, *port;
-+	struct device_node *phy_dn;
-+	struct phy_device *phy;
-+	int reg, err = 0, test_phase;
-+	u32 tests_result = 0;
-+
-+	ports = of_get_child_by_name(dn, "ports");
-+	if (!ports) {
-+		dev_err(priv->dev, "no ports child node found\n");
-+			return -EINVAL;
-+	}
-+
-+	for (test_phase = 1; test_phase <= 2; test_phase++) {
-+		if (parallel_test && test_phase == 2) {
-+			err = qca8k_start_all_phys_pkt_gens(priv);
-+			if (err)
-+				goto error;
-+		}
-+		for_each_available_child_of_node(ports, port) {
-+			err = of_property_read_u32(port, "reg", &reg);
-+			if (err)
-+				goto error;
-+			if (reg >= QCA8K_NUM_PORTS) {
-+				err = -EINVAL;
-+				goto error;
-+			}
-+			phy_dn = of_parse_phandle(port, "phy-handle", 0);
-+			if (phy_dn) {
-+				phy = of_phy_find_device(phy_dn);
-+				of_node_put(phy_dn);
-+				if (phy) {
-+					int result;
-+					result = qca8k_test_dsa_port_for_errors(priv,
-+						phy, reg, test_phase);
-+					if (!parallel_test && test_phase == 1)
-+						qca8k_start_phy_pkt_gen(phy);
-+					put_device(&phy->mdio.dev);
-+					if (test_phase == 2) {
-+						tests_result <<= 1;
-+						if (result)
-+							tests_result |= 1;
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+end:
-+	of_node_put(ports);
-+	qca8k_fdb_flush(priv);
-+	return tests_result;
-+error:
-+	tests_result |= 0xf000;
-+	goto end;
-+}
-+
-+static int
-+psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
-+{
-+	int ret, a, test_result;
-+	struct qca8k_priv *priv = ds->priv;
-+
-+	for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
-+		ret = psgmii_vco_calibrate(priv);
-+		if (ret)
-+			return ret;
-+		/* first we run serial test */
-+		test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
-+		/* and if it is ok then we run the test in parallel */
-+		if (!test_result)
-+			test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
-+		if (!test_result) {
-+			if (a > 0) {
-+				dev_warn(priv->dev, "PSGMII work was stabilized after %d "
-+					"calibration retries !\n", a);
-+			}
-+			return 0;
-+		} else {
-+			schedule();
-+			if (a > 0 && a % 10 == 0) {
-+				dev_err(priv->dev, "PSGMII work is unstable !!! "
-+					"Let's try to wait a bit ... %d\n", a);
-+				set_current_state(TASK_INTERRUPTIBLE);
-+				schedule_timeout(msecs_to_jiffies(a * 100));
-+			}
-+		}
-+	}
-+
-+	panic("PSGMII work is unstable !!! "
-+		"Repeated recalibration attempts did not help(0x%x) !\n",
-+		test_result);
-+
-+	return -EFAULT;
-+}
-+
-+static int
-+ipq4019_psgmii_configure(struct dsa_switch *ds)
-+{
-+	struct qca8k_priv *priv = ds->priv;
-+	int ret;
-+
-+	if (!priv->psgmii_calibrated) {
-+		dev_info(ds->dev, "PSGMII calibration!\n");
-+		ret = psgmii_vco_calibrate_and_test(ds);
-+
-+		ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
-+					PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
-+		ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
-+				   PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
-+
-+		priv->psgmii_calibrated = true;
-+
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_config(struct dsa_switch *ds, int port,
-+				 unsigned int mode,
-+				 const struct phylink_link_state *state)
-+{
-+	struct qca8k_priv *priv = ds->priv;
-+
-+	switch (port) {
-+	case 0:
-+		/* CPU port, no configuration needed */
-+		return;
-+	case 1:
-+	case 2:
-+	case 3:
-+		if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+			if (ipq4019_psgmii_configure(ds))
-+				dev_err(ds->dev, "PSGMII configuration failed!\n");
-+		return;
-+	case 4:
-+	case 5:
-+		if (state->interface == PHY_INTERFACE_MODE_RGMII ||
-+		    state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-+		    state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-+		    state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
-+			regmap_set_bits(priv->regmap,
-+					QCA8K_IPQ4019_REG_RGMII_CTRL,
-+					QCA8K_IPQ4019_RGMII_CTRL_CLK);
-+		}
-+
-+		if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+			if (ipq4019_psgmii_configure(ds))
-+				dev_err(ds->dev, "PSGMII configuration failed!\n");
-+		return;
-+	default:
-+		dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
-+		return;
-+	}
-+}
-+
-+static int
-+qca8k_ipq4019_setup_port(struct dsa_switch *ds, int port)
-+{
-+	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+	int ret;
-+
-+	/* CPU port gets connected to all user ports of the switch */
-+	if (dsa_is_cpu_port(ds, port)) {
-+		ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+				QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
-+		if (ret)
-+			return ret;
-+
-+		/* Disable CPU ARP Auto-learning by default */
-+		ret = regmap_clear_bits(priv->regmap,
-+					QCA8K_PORT_LOOKUP_CTRL(port),
-+					QCA8K_PORT_LOOKUP_LEARN);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	/* Individual user ports get connected to CPU port only */
-+	if (dsa_is_user_port(ds, port)) {
-+		ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+				QCA8K_PORT_LOOKUP_MEMBER,
-+				BIT(QCA8K_IPQ4019_CPU_PORT));
-+		if (ret)
-+			return ret;
-+
-+		/* Enable ARP Auto-learning by default */
-+		ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
-+				      QCA8K_PORT_LOOKUP_LEARN);
-+		if (ret)
-+			return ret;
-+
-+		/* For port based vlans to work we need to set the
-+		 * default egress vid
-+		 */
-+		ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
-+				QCA8K_EGREES_VLAN_PORT_MASK(port),
-+				QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
-+		if (ret)
-+			return ret;
-+
-+		ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
-+				  QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
-+				  QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int
-+qca8k_ipq4019_setup(struct dsa_switch *ds)
-+{
-+	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+	int ret, i;
-+
-+	/* Make sure that port 0 is the cpu port */
-+	if (!dsa_is_cpu_port(ds, QCA8K_IPQ4019_CPU_PORT)) {
-+		dev_err(priv->dev, "port %d is not the CPU port",
-+			QCA8K_IPQ4019_CPU_PORT);
-+		return -EINVAL;
-+	}
-+
-+	qca8k_ipq4019_setup_pcs(priv, &priv->pcs_port_0, 0);
-+
-+	/* Enable CPU Port */
-+	ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
-+			      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
-+	if (ret) {
-+		dev_err(priv->dev, "failed enabling CPU port");
-+		return ret;
-+	}
-+
-+	/* Enable MIB counters */
-+	ret = qca8k_mib_init(priv);
-+	if (ret)
-+		dev_warn(priv->dev, "MIB init failed");
-+
-+	/* Disable forwarding by default on all ports */
-+	for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+		ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
-+				QCA8K_PORT_LOOKUP_MEMBER, 0);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	/* Enable QCA header mode on the CPU port */
-+	ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_IPQ4019_CPU_PORT),
-+			  FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
-+			  FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
-+	if (ret) {
-+		dev_err(priv->dev, "failed enabling QCA header mode");
-+		return ret;
-+	}
-+
-+	/* Disable MAC by default on all ports */
-+	for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+		if (dsa_is_user_port(ds, i))
-+			qca8k_port_set_status(priv, i, 0);
-+	}
-+
-+	/* Forward all unknown frames to CPU port for Linux processing */
-+	ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
-+			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+			  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)));
-+	if (ret)
-+		return ret;
-+
-+	/* Setup connection between CPU port & user ports */
-+	for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+		ret = qca8k_ipq4019_setup_port(ds, i);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	/* Setup our port MTUs to match power on defaults */
-+	ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
-+	if (ret)
-+		dev_warn(priv->dev, "failed setting MTU settings");
-+
-+	/* Flush the FDB table */
-+	qca8k_fdb_flush(priv);
-+
-+	/* Set min a max ageing value supported */
-+	ds->ageing_time_min = 7000;
-+	ds->ageing_time_max = 458745000;
-+
-+	/* Set max number of LAGs supported */
-+	ds->num_lag_ids = QCA8K_NUM_LAGS;
-+
-+	/* CPU port HW learning doesnt work correctly, so let DSA handle it */
-+	ds->assisted_learning_on_cpu_port = true;
-+
-+	return 0;
-+}
-+
-+static const struct dsa_switch_ops qca8k_ipq4019_switch_ops = {
-+	.get_tag_protocol	= qca8k_ipq4019_get_tag_protocol,
-+	.setup			= qca8k_ipq4019_setup,
-+	.get_strings		= qca8k_get_strings,
-+	.get_ethtool_stats	= qca8k_get_ethtool_stats,
-+	.get_sset_count		= qca8k_get_sset_count,
-+	.set_ageing_time	= qca8k_set_ageing_time,
-+	.get_mac_eee		= qca8k_get_mac_eee,
-+	.set_mac_eee		= qca8k_set_mac_eee,
-+	.port_enable		= qca8k_port_enable,
-+	.port_disable		= qca8k_port_disable,
-+	.port_change_mtu	= qca8k_port_change_mtu,
-+	.port_max_mtu		= qca8k_port_max_mtu,
-+	.port_stp_state_set	= qca8k_port_stp_state_set,
-+	.port_bridge_join	= qca8k_port_bridge_join,
-+	.port_bridge_leave	= qca8k_port_bridge_leave,
-+	.port_fast_age		= qca8k_port_fast_age,
-+	.port_fdb_add		= qca8k_port_fdb_add,
-+	.port_fdb_del		= qca8k_port_fdb_del,
-+	.port_fdb_dump		= qca8k_port_fdb_dump,
-+	.port_mdb_add		= qca8k_port_mdb_add,
-+	.port_mdb_del		= qca8k_port_mdb_del,
-+	.port_mirror_add	= qca8k_port_mirror_add,
-+	.port_mirror_del	= qca8k_port_mirror_del,
-+	.port_vlan_filtering	= qca8k_port_vlan_filtering,
-+	.port_vlan_add		= qca8k_port_vlan_add,
-+	.port_vlan_del		= qca8k_port_vlan_del,
-+	.phylink_mac_select_pcs	= qca8k_ipq4019_phylink_mac_select_pcs,
-+	.phylink_get_caps	= qca8k_ipq4019_phylink_get_caps,
-+	.phylink_mac_config	= qca8k_phylink_ipq4019_mac_config,
-+	.phylink_mac_link_down	= qca8k_phylink_ipq4019_mac_link_down,
-+	.phylink_mac_link_up	= qca8k_phylink_ipq4019_mac_link_up,
-+	.port_lag_join		= qca8k_port_lag_join,
-+	.port_lag_leave		= qca8k_port_lag_leave,
-+};
-+
-+static const struct qca8k_match_data ipq4019 = {
-+	.id = QCA8K_ID_IPQ4019,
-+	.mib_count = QCA8K_QCA833X_MIB_COUNT,
-+};
-+
-+static int
-+qca8k_ipq4019_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct qca8k_priv *priv;
-+	void __iomem *base, *psgmii;
-+	struct device_node *np = dev->of_node, *mdio_np, *psgmii_ethphy_np;
-+	int ret;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->dev = dev;
-+	priv->info = &ipq4019;
-+
-+	/* Start by setting up the register mapping */
-+	base = devm_platform_ioremap_resource_byname(pdev, "base");
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	priv->regmap = devm_regmap_init_mmio(dev, base,
-+					     &qca8k_ipq4019_regmap_config);
-+	if (IS_ERR(priv->regmap)) {
-+		ret = PTR_ERR(priv->regmap);
-+		dev_err(dev, "base regmap initialization failed, %d\n", ret);
-+		return ret;
-+	}
-+
-+	psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
-+	if (IS_ERR(psgmii))
-+		return PTR_ERR(psgmii);
-+
-+	priv->psgmii = devm_regmap_init_mmio(dev, psgmii,
-+					     &qca8k_ipq4019_psgmii_phy_regmap_config);
-+	if (IS_ERR(priv->psgmii)) {
-+		ret = PTR_ERR(priv->psgmii);
-+		dev_err(dev, "PSGMII regmap initialization failed, %d\n", ret);
-+		return ret;
-+	}
-+
-+	mdio_np = of_parse_phandle(np, "mdio", 0);
-+	if (!mdio_np) {
-+		dev_err(dev, "unable to get MDIO bus phandle\n");
-+		of_node_put(mdio_np);
-+		return -EINVAL;
-+	}
-+
-+	priv->bus = of_mdio_find_bus(mdio_np);
-+	of_node_put(mdio_np);
-+	if (!priv->bus) {
-+		dev_err(dev, "unable to find MDIO bus\n");
-+		return -EPROBE_DEFER;
-+	}
-+
-+	psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
-+	if (!psgmii_ethphy_np) {
-+		dev_dbg(dev, "unable to get PSGMII eth PHY phandle\n");
-+		of_node_put(psgmii_ethphy_np);
-+	}
-+
-+	if (psgmii_ethphy_np) {
-+		priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
-+		of_node_put(psgmii_ethphy_np);
-+		if (!priv->psgmii_ethphy) {
-+			dev_err(dev, "unable to get PSGMII eth PHY\n");
-+			return -ENODEV;
-+		}
-+	}
-+
-+	/* Check the detected switch id */
-+	ret = qca8k_read_switch_id(priv);
-+	if (ret)
-+		return ret;
-+
-+	priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
-+	if (!priv->ds)
-+		return -ENOMEM;
-+
-+	priv->ds->dev = dev;
-+	priv->ds->num_ports = QCA8K_IPQ4019_NUM_PORTS;
-+	priv->ds->priv = priv;
-+	priv->ds->ops = &qca8k_ipq4019_switch_ops;
-+	mutex_init(&priv->reg_mutex);
-+	platform_set_drvdata(pdev, priv);
-+
-+	return dsa_register_switch(priv->ds);
-+}
-+
-+static int
-+qca8k_ipq4019_remove(struct platform_device *pdev)
-+{
-+	struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
-+	int i;
-+
-+	if (!priv)
-+		return 0;
-+
-+	for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++)
-+		qca8k_port_set_status(priv, i, 0);
-+
-+	dsa_unregister_switch(priv->ds);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id qca8k_ipq4019_of_match[] = {
-+	{ .compatible = "qca,ipq4019-qca8337n", },
-+	{ /* sentinel */ },
-+};
-+
-+static struct platform_driver qca8k_ipq4019_driver = {
-+	.probe = qca8k_ipq4019_probe,
-+	.remove = qca8k_ipq4019_remove,
-+	.driver = {
-+		.name = "qca8k-ipq4019",
-+		.of_match_table = qca8k_ipq4019_of_match,
-+	},
-+};
-+
-+module_platform_driver(qca8k_ipq4019_driver);
-+
-+MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
-+MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
-+MODULE_LICENSE("GPL");
---- a/drivers/net/dsa/qca/qca8k.h
-+++ b/drivers/net/dsa/qca/qca8k.h
-@@ -19,7 +19,10 @@
- #define QCA8K_ETHERNET_TIMEOUT				5
- 
- #define QCA8K_NUM_PORTS					7
-+#define QCA8K_IPQ4019_NUM_PORTS				6
- #define QCA8K_NUM_CPU_PORTS				2
-+#define QCA8K_IPQ4019_NUM_CPU_PORTS			1
-+#define QCA8K_IPQ4019_CPU_PORT				0
- #define QCA8K_MAX_MTU					9000
- #define QCA8K_NUM_LAGS					4
- #define QCA8K_NUM_PORTS_FOR_LAG				4
-@@ -28,6 +31,7 @@
- #define QCA8K_ID_QCA8327				0x12
- #define PHY_ID_QCA8337					0x004dd036
- #define QCA8K_ID_QCA8337				0x13
-+#define QCA8K_ID_IPQ4019				0x14
- 
- #define QCA8K_QCA832X_MIB_COUNT				39
- #define QCA8K_QCA833X_MIB_COUNT				41
-@@ -265,6 +269,7 @@
- #define   QCA8K_PORT_LOOKUP_STATE_LEARNING		QCA8K_PORT_LOOKUP_STATE(0x3)
- #define   QCA8K_PORT_LOOKUP_STATE_FORWARD		QCA8K_PORT_LOOKUP_STATE(0x4)
- #define   QCA8K_PORT_LOOKUP_LEARN			BIT(20)
-+#define   QCA8K_PORT_LOOKUP_LOOPBACK_EN			BIT(21)
- #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN		BIT(25)
- 
- #define QCA8K_REG_GOL_TRUNK_CTRL0			0x700
-@@ -341,6 +346,53 @@
- #define MII_ATH_MMD_ADDR				0x0d
- #define MII_ATH_MMD_DATA				0x0e
- 
-+/* IPQ4019 PSGMII PHY registers */
-+#define QCA8K_IPQ4019_REG_RGMII_CTRL			0x004
-+#define   QCA8K_IPQ4019_RGMII_CTRL_RGMII_RXC		GENMASK(1, 0)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_RGMII_TXC		GENMASK(9, 8)
-+/* Some kind of CLK selection
-+ * 0: gcc_ess_dly2ns
-+ * 1: gcc_ess_clk
-+ */
-+#define   QCA8K_IPQ4019_RGMII_CTRL_CLK				BIT(10)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII0			GENMASK(17, 16)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_REF_CLK		BIT(18)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII1			GENMASK(20, 19)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_REF_CLK		BIT(21)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_MASTER_EN	BIT(24)
-+#define   QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_MASTER_EN	BIT(25)
-+
-+#define PSGMIIPHY_MODE_CONTROL				0x1b4
-+#define   PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M		BIT(0)
-+#define PSGMIIPHY_TX_CONTROL				0x288
-+#define   PSGMIIPHY_TX_CONTROL_MAGIC_VALUE		0x8380
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1	0x9c
-+#define   PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART		BIT(14)
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2	0xa0
-+#define   PSGMIIPHY_REG_PLL_VCO_CALIB_READY		BIT(0)
-+
-+#define   QCA8K_PSGMII_CALB_NUM				100
-+#define   MII_QCA8075_SSTATUS				0x11
-+#define   QCA8075_PHY_SPEC_STATUS_LINK			BIT(10)
-+#define   QCA8075_MMD7_CRC_AND_PKTS_COUNT		0x8029
-+#define   QCA8075_MMD7_PKT_GEN_PKT_NUMB			0x8021
-+#define   QCA8075_MMD7_PKT_GEN_PKT_SIZE			0x8062
-+#define   QCA8075_MMD7_PKT_GEN_CTRL			0x8020
-+#define   QCA8075_MMD7_CNT_SELFCLR			BIT(1)
-+#define   QCA8075_MMD7_CNT_FRAME_CHK_EN			BIT(0)
-+#define   QCA8075_MMD7_PKT_GEN_START			BIT(13)
-+#define   QCA8075_MMD7_PKT_GEN_INPROGR			BIT(15)
-+#define   QCA8075_MMD7_IG_FRAME_RECV_CNT_HI		0x802a
-+#define   QCA8075_MMD7_IG_FRAME_RECV_CNT_LO		0x802b
-+#define   QCA8075_MMD7_IG_FRAME_ERR_CNT			0x802c
-+#define   QCA8075_MMD7_EG_FRAME_RECV_CNT_HI		0x802d
-+#define   QCA8075_MMD7_EG_FRAME_RECV_CNT_LO		0x802e
-+#define   QCA8075_MMD7_EG_FRAME_ERR_CNT			0x802f
-+#define   QCA8075_MMD7_MDIO_BRDCST_WRITE		0x8028
-+#define   QCA8075_MMD7_MDIO_BRDCST_WRITE_EN 		BIT(15)
-+#define   QCA8075_MDIO_BRDCST_PHY_ADDR			0x1f
-+#define   QCA8075_PKT_GEN_PKTS_COUNT			4096
-+
- enum {
- 	QCA8K_PORT_SPEED_10M = 0,
- 	QCA8K_PORT_SPEED_100M = 1,
-@@ -466,6 +518,10 @@ struct qca8k_priv {
- 	struct qca8k_pcs pcs_port_6;
- 	const struct qca8k_match_data *info;
- 	struct qca8k_led ports_led[QCA8K_LED_COUNT];
-+	/* IPQ4019 specific */
-+	struct regmap *psgmii;
-+	struct phy_device *psgmii_ethphy;
-+	bool psgmii_calibrated;
- };
- 
- struct qca8k_mib_desc {
diff --git a/target/linux/ipq40xx/patches-6.1/707-arm-dts-ipq4019-add-switch-node.patch b/target/linux/ipq40xx/patches-6.1/707-arm-dts-ipq4019-add-switch-node.patch
deleted file mode 100644
index e7203a3ac9..0000000000
--- a/target/linux/ipq40xx/patches-6.1/707-arm-dts-ipq4019-add-switch-node.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 19c507c3fe4a6fc60317dcae2c55de452aecb7d5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:15:04 +0100
-Subject: [PATCH] arm: dts: ipq4019: add switch node
-
-Since the built-in IPQ40xx switch now has a driver, add the required node
-for it to work.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 76 +++++++++++++++++++++++++++++
- 1 file changed, 76 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,82 @@
- 			status = "disabled";
- 		};
- 
-+		switch: switch@c000000 {
-+			compatible = "qca,ipq4019-qca8337n";
-+			reg = <0xc000000 0x80000>, <0x98000 0x800>;
-+			reg-names = "base", "psgmii_phy";
-+			resets = <&gcc ESS_PSGMII_ARES>;
-+			reset-names = "psgmii_rst";
-+			mdio = <&mdio>;
-+			psgmii-ethphy = <&psgmiiphy>;
-+
-+			status = "disabled";
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				port@0 { /* MAC0 */
-+					reg = <0>;
-+					label = "cpu";
-+					ethernet = <&gmac>;
-+					phy-mode = "internal";
-+
-+					fixed-link {
-+						speed = <1000>;
-+						full-duplex;
-+						pause;
-+						asym-pause;
-+					};
-+				};
-+
-+				swport1: port@1 { /* MAC1 */
-+					reg = <1>;
-+					label = "lan1";
-+					phy-handle = <&ethphy0>;
-+					phy-mode = "psgmii";
-+
-+					status = "disabled";
-+				};
-+
-+				swport2: port@2 { /* MAC2 */
-+					reg = <2>;
-+					label = "lan2";
-+					phy-handle = <&ethphy1>;
-+					phy-mode = "psgmii";
-+
-+					status = "disabled";
-+				};
-+
-+				swport3: port@3 { /* MAC3 */
-+					reg = <3>;
-+					label = "lan3";
-+					phy-handle = <&ethphy2>;
-+					phy-mode = "psgmii";
-+
-+					status = "disabled";
-+				};
-+
-+				swport4: port@4 { /* MAC4 */
-+					reg = <4>;
-+					label = "lan4";
-+					phy-handle = <&ethphy3>;
-+					phy-mode = "psgmii";
-+
-+					status = "disabled";
-+				};
-+
-+				swport5: port@5 { /* MAC5 */
-+					reg = <5>;
-+					label = "wan";
-+					phy-handle = <&ethphy4>;
-+					phy-mode = "psgmii";
-+
-+					status = "disabled";
-+				};
-+			};
-+		};
-+
- 		gmac: ethernet@c080000 {
- 			compatible = "qcom,ipq4019-ess-edma";
- 			reg = <0xc080000 0x8000>;
diff --git a/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch b/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
deleted file mode 100644
index e8b89647ce..0000000000
--- a/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 5ac078c8fe18f3e8318547b8ed0ed782730c5039 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 10 Feb 2024 22:28:27 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
-
-Add QCA8075 PHY Package nodes. The PHY nodes that were previously
-defined never worked and actually never had a driver to correctly setup
-these PHY. Now that we have a correct driver, correctly add the PHY
-Package node and set the default value of 300mw for tx driver strength
-following specification of ipq4019 SoC.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts//qcom-ipq4019.dtsi | 35 +++++++++++++++---------
- 1 file changed, 22 insertions(+), 13 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -725,24 +725,33 @@
- 			reg = <0x90000 0x64>;
- 			status = "disabled";
- 
--			ethphy0: ethernet-phy@0 {
-+			ethernet-phy-package@0 {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				compatible = "qcom,qca8075-package";
- 				reg = <0>;
--			};
--
--			ethphy1: ethernet-phy@1 {
--				reg = <1>;
--			};
- 
--			ethphy2: ethernet-phy@2 {
--				reg = <2>;
--			};
--
--			ethphy3: ethernet-phy@3 {
--				reg = <3>;
--			};
-+				qcom,tx-drive-strength-milliwatt = <300>;
- 
--			ethphy4: ethernet-phy@4 {
--				reg = <4>;
-+				ethphy0: ethernet-phy@0 {
-+					reg = <0>;
-+				};
-+
-+				ethphy1: ethernet-phy@1 {
-+					reg = <1>;
-+				};
-+
-+				ethphy2: ethernet-phy@2 {
-+					reg = <2>;
-+				};
-+
-+				ethphy3: ethernet-phy@3 {
-+					reg = <3>;
-+				};
-+
-+				ethphy4: ethernet-phy@4 {
-+					reg = <4>;
-+				};
- 			};
- 		};
- 
diff --git a/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
deleted file mode 100644
index a9ba70ff2f..0000000000
--- a/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 79b38b9f85da868ca59b66715c20aa55104b640b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 2 Oct 2020 10:43:26 +0200
-Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
-
-This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -752,6 +752,10 @@
- 				ethphy4: ethernet-phy@4 {
- 					reg = <4>;
- 				};
-+
-+				psgmiiphy: psgmii-phy@5 {
-+					reg = <5>;
-+				};
- 			};
- 		};
- 
diff --git a/target/linux/ipq40xx/patches-6.1/711-net-qualcomm-ipqess-fix-TX-timeout-errors.patch b/target/linux/ipq40xx/patches-6.1/711-net-qualcomm-ipqess-fix-TX-timeout-errors.patch
deleted file mode 100644
index 149208aa69..0000000000
--- a/target/linux/ipq40xx/patches-6.1/711-net-qualcomm-ipqess-fix-TX-timeout-errors.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From d0055b03d9c8d48ad2b971821989b09ba95c39f8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 17 Sep 2023 20:18:31 +0200
-Subject: [PATCH] net: qualcomm: ipqess: fix TX timeout errors
-
-Currently logic to handle napi tx completion is flawed and on the long
-run on loaded condition cause TX timeout error with the queue not being
-able to handle any new packet.
-
-There are 2 main cause of this:
-- incrementing the packet done value wrongly
-- handling 2 times the tx_ring tail
-
-ipqess_tx_unmap_and_free may return 2 kind values:
-- 0: we are handling first and middle descriptor for the packet
-- packet len: we are at the last descriptor for the packet
-
-Done value was wrongly incremented also for first and intermediate
-descriptor for the packet resulting causing panic and TX timeouts by
-comunicating to the kernel an inconsistent value of packet handling not
-matching the expected ones.
-
-Tx_ring tail was handled twice for ipqess_tx_complete run resulting in
-again done value incremented wrongly and also problem with idx handling
-by actually skipping descriptor for some packets.
-
-Rework the loop logic to fix these 2 problem and also add some comments
-to make sure ipqess_tx_unmap_and_free ret value is better
-understandable.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -453,13 +453,22 @@ static int ipqess_tx_complete(struct ipq
- 	tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
- 	tail &= IPQESS_TPD_CONS_IDX_MASK;
- 
--	do {
-+	while ((tx_ring->tail != tail) && (done < budget)) {
- 		ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
- 					       &tx_ring->buf[tx_ring->tail]);
--		tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+		/* ipqess_tx_unmap_and_free may return 2 kind values:
-+		 * - 0: we are handling first and middle descriptor for the packet
-+		 * - packet len: we are at the last descriptor for the packet
-+		 * Increment total bytes handled and packet done only if we are
-+		 * handling the last descriptor for the packet.
-+		 */
-+		if (ret) {
-+			total += ret;
-+			done++;
-+		}
- 
--		total += ret;
--	} while ((++done < budget) && (tx_ring->tail != tail));
-+		tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+	};
- 
- 	ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
- 		   tx_ring->tail);
diff --git a/target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch
deleted file mode 100644
index 6afb27b178..0000000000
--- a/target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch
+++ /dev/null
@@ -1,175 +0,0 @@
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
- 	  the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
- 	  memory throughput even with lower CPU frequencies.
- 
-+config QCOM_TCSR
-+	tristate "QCOM Top Control and Status Registers"
-+	depends on ARCH_QCOM
-+	help
-+	  Say y here to enable TCSR support.  The TCSR provides control
-+	  functions for various peripherals.
-+
- endmenu
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
- obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
- obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
- obj-$(CONFIG_QCOM_ICC_BWMON)	+= icc-bwmon.o
-+obj-$(CONFIG_QCOM_TCSR)		+= qcom_tcsr.o
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL	0xb0
-+#define TCSR_USB_HSPHY_CONFIG	0xC
-+
-+#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0
-+#define TCSR_ESS_INTERFACE_SEL_MASK     0xf
-+
-+#define TCSR_WIFI0_GLB_CFG_OFFSET	0x0
-+#define TCSR_WIFI1_GLB_CFG_OFFSET	0x4
-+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2	0x4
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	const struct device_node *node = pdev->dev.of_node;
-+	void __iomem *base;
-+	u32 val;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+		dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+		writel(val, base + TCSR_USB_PORT_SEL);
-+	}
-+
-+	if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
-+		dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
-+		writel(val, base + TCSR_USB_HSPHY_CONFIG);
-+	}
-+
-+	if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
-+		u32 tmp = 0;
-+		dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
-+		tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+		tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
-+		tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
-+		writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+        }
-+
-+	if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
-+		dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
-+		writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
-+		writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
-+	}
-+
-+	if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
-+		dev_info(&pdev->dev,
-+			"setting wifi_noc_memtype_m0_m2 = %x\n", val);
-+		writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+	{ .compatible = "qcom,tcsr", },
-+	{ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+	.driver = {
-+		.name		= "tcsr",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= tcsr_dt_match,
-+	},
-+	.probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,48 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0		0x1
-+#define TCSR_USB_SELECT_USB3_P1		0x2
-+#define TCSR_USB_SELECT_USB3_DUAL	0x3
-+
-+/* IPQ40xx HS PHY Mode Select */
-+#define TCSR_USB_HSPHY_HOST_MODE	0x00E700E7
-+#define TCSR_USB_HSPHY_DEVICE_MODE	0x00C700E7
-+
-+/* IPQ40xx ess interface mode select */
-+#define TCSR_ESS_PSGMII              0
-+#define TCSR_ESS_PSGMII_RGMII5       1
-+#define TCSR_ESS_PSGMII_RMII0        2
-+#define TCSR_ESS_PSGMII_RMII1        4
-+#define TCSR_ESS_PSGMII_RMII0_RMII1  6
-+#define TCSR_ESS_PSGMII_RGMII4       9
-+
-+/*
-+ * IPQ40xx WiFi Global Config
-+ * Bit 30:AXID_EN
-+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
-+ * Bit 24: Use locally generated socslv_wxi_bvalid
-+ * 1:  use locally generate socslv_wxi_bvalid for performance.
-+ * 0:  use SNOC socslv_wxi_bvalid.
-+ */
-+#define TCSR_WIFI_GLB_CFG		0x41000000
-+
-+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
-+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2	0x02222222
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
-+
-+#endif
diff --git a/target/linux/ipq40xx/patches-6.1/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch b/target/linux/ipq40xx/patches-6.1/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch
deleted file mode 100644
index c73e40429c..0000000000
--- a/target/linux/ipq40xx/patches-6.1/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 13 Aug 2023 18:13:08 +0200
-Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot"
-
-This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709.
-
-It is breaking reboot on IPQ4019 boards, so revert until a proper fix
-is found.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/firmware/qcom_scm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -1466,7 +1466,8 @@ static int qcom_scm_probe(struct platfor
- static void qcom_scm_shutdown(struct platform_device *pdev)
- {
- 	/* Clean shutdown, disable download mode to allow normal restart */
--	qcom_scm_set_download_mode(false);
-+	if (download_mode)
-+		qcom_scm_set_download_mode(false);
- }
- 
- static const struct of_device_id qcom_scm_dt_match[] = {
diff --git a/target/linux/ipq40xx/patches-6.1/998-lantiq-atm-hacks.patch b/target/linux/ipq40xx/patches-6.1/998-lantiq-atm-hacks.patch
deleted file mode 100644
index c15a4b3ae3..0000000000
--- a/target/linux/ipq40xx/patches-6.1/998-lantiq-atm-hacks.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:25 +0200
-Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
---- a/include/uapi/linux/atm.h
-+++ b/include/uapi/linux/atm.h
-@@ -131,8 +131,14 @@
- #define ATM_ABR		4
- #define ATM_ANYCLASS	5		/* compatible with everything */
- 
-+#define ATM_VBR_NRT     ATM_VBR
-+#define ATM_VBR_RT      6
-+#define ATM_UBR_PLUS    7
-+#define ATM_GFR         8
-+
- #define ATM_MAX_PCR	-1		/* maximum available PCR */
- 
-+
- struct atm_trafprm {
- 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
- 	int		max_pcr;	/* maximum PCR in cells per second */
-@@ -155,6 +161,9 @@ struct atm_trafprm {
- 	unsigned int adtf      :10;     /* ACR Decrease Time Factor (10-bit) */
- 	unsigned int cdf       :3;      /* Cutoff Decrease Factor (3-bit) */
-         unsigned int spare     :9;      /* spare bits */ 
-+	int		scr;		/* sustained rate in cells per second */
-+	int		mbs;		/* maximum burst size (MBS) in cells */
-+	int		cdv;		/* Cell delay variation */
- };
- 
- struct atm_qos {
---- a/net/atm/proc.c
-+++ b/net/atm/proc.c
-@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- 	static const char *const class_name[] = {
--		"off", "UBR", "CBR", "VBR", "ABR"};
-+		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
- 	static const char *const aal_name[] = {
- 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
- 		"???",	"5",	"???",	"???",	/*  4- 7 */
diff --git a/target/linux/ipq40xx/patches-6.1/999-atm-mpoa-intel-dsl-phy-support.patch b/target/linux/ipq40xx/patches-6.1/999-atm-mpoa-intel-dsl-phy-support.patch
deleted file mode 100644
index 3d5b7afe8c..0000000000
--- a/target/linux/ipq40xx/patches-6.1/999-atm-mpoa-intel-dsl-phy-support.patch
+++ /dev/null
@@ -1,137 +0,0 @@
-From: Subhra Banerjee <subhrax.banerjee@intel.com>
-Date: Fri, 31 Aug 2018 12:01:19 +0530
-Subject: [PATCH] UGW_SW-29163: ATM oam support
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -2953,6 +2953,22 @@ char *ppp_dev_name(struct ppp_channel *c
- 	return name;
- }
- 
-+/*
-+ * Return the PPP device interface pointer
-+ */
-+struct net_device *ppp_device(struct ppp_channel *chan)
-+{
-+	struct channel *pch = chan->ppp;
-+	struct net_device *dev = NULL;
-+
-+	if (pch) {
-+		read_lock_bh(&pch->upl);
-+		if (pch->ppp && pch->ppp->dev)
-+			dev = pch->ppp->dev;
-+		read_unlock_bh(&pch->upl);
-+	}
-+	return dev;
-+}
- 
- /*
-  * Disconnect a channel from the generic layer.
-@@ -3599,6 +3615,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
- EXPORT_SYMBOL(ppp_channel_index);
- EXPORT_SYMBOL(ppp_unit_number);
- EXPORT_SYMBOL(ppp_dev_name);
-+EXPORT_SYMBOL(ppp_device);
- EXPORT_SYMBOL(ppp_input);
- EXPORT_SYMBOL(ppp_input_error);
- EXPORT_SYMBOL(ppp_output_wakeup);
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -76,6 +76,9 @@ extern int ppp_unit_number(struct ppp_ch
- /* Get the device name associated with a channel, or NULL if none */
- extern char *ppp_dev_name(struct ppp_channel *);
- 
-+/* Get the device pointer associated with a channel, or NULL if none */
-+extern struct net_device *ppp_device(struct ppp_channel *);
-+
- /*
-  * SMP locking notes:
-  * The channel code must ensure that when it calls ppp_unregister_channel,
---- a/net/atm/Kconfig
-+++ b/net/atm/Kconfig
-@@ -56,6 +56,12 @@ config ATM_MPOA
- 	  subnetwork boundaries. These shortcut connections bypass routers
- 	  enhancing overall network performance.
- 
-+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT
-+	bool "Intel DSL Phy MPOA support"
-+	depends on ATM && INET && ATM_MPOA!=n
-+	help
-+	  Add support for Intel DSL Phy ATM MPOA
-+
- config ATM_BR2684
- 	tristate "RFC1483/2684 Bridged protocols"
- 	depends on ATM && INET
---- a/net/atm/br2684.c
-+++ b/net/atm/br2684.c
-@@ -598,6 +598,11 @@ static int br2684_regvcc(struct atm_vcc
- 	atmvcc->push = br2684_push;
- 	atmvcc->pop = br2684_pop;
- 	atmvcc->release_cb = br2684_release_cb;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+	if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */
-+		atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0,
-+			brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev);
-+#endif
- 	atmvcc->owner = THIS_MODULE;
- 
- 	/* initialize netdev carrier state */
---- a/net/atm/common.c
-+++ b/net/atm/common.c
-@@ -137,6 +137,11 @@ static struct proto vcc_proto = {
- 	.release_cb = vcc_release_cb,
- };
- 
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL;
-+EXPORT_SYMBOL(atm_hook_mpoa_setup);
-+#endif
-+
- int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern)
- {
- 	struct sock *sk;
---- a/net/atm/common.h
-+++ b/net/atm/common.h
-@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s
- 
- void atm_dev_release_vccs(struct atm_dev *dev);
- 
-+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *);
-+
- #endif
---- a/net/atm/mpc.c
-+++ b/net/atm/mpc.c
-@@ -31,6 +31,7 @@
- /* Modular too */
- #include <linux/module.h>
- 
-+#include "common.h"
- #include "lec.h"
- #include "mpc.h"
- #include "resources.h"
-@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at
- 	vcc->proto_data = mpc->dev;
- 	vcc->push = mpc_push;
- 
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+	if (atm_hook_mpoa_setup) /* IPoA, LLC */
-+		atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev);
-+#endif
- 	return 0;
- }
- 
---- a/net/atm/pppoatm.c
-+++ b/net/atm/pppoatm.c
-@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm
- 	atmvcc->user_back = pvcc;
- 	atmvcc->push = pppoatm_push;
- 	atmvcc->pop = pppoatm_pop;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+	if (atm_hook_mpoa_setup) /* PPPoA */
-+		atm_hook_mpoa_setup(atmvcc, 2,
-+			pvcc->encaps == e_llc ? 1 : 0,
-+			ppp_device(&pvcc->chan));
-+#endif
- 	atmvcc->release_cb = pppoatm_release_cb;
- 	__module_get(THIS_MODULE);
- 	atmvcc->owner = THIS_MODULE;
diff --git a/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch b/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch
index 4131b6914d..f535ef2d89 100644
--- a/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch
+++ b/target/linux/ipq40xx/patches-6.6/701-net-dsa-add-out-of-band-tagging-protocol.patch
@@ -93,7 +93,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
 +#endif
 --- a/include/linux/skbuff.h
 +++ b/include/linux/skbuff.h
-@@ -4643,6 +4643,9 @@ enum skb_ext_id {
+@@ -4657,6 +4657,9 @@ enum skb_ext_id {
  #if IS_ENABLED(CONFIG_MCTP_FLOWS)
  	SKB_EXT_MCTP,
  #endif
@@ -136,7 +136,7 @@ Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
  #include <net/dst.h>
  #include <net/sock.h>
  #include <net/checksum.h>
-@@ -4812,6 +4816,9 @@ static const u8 skb_ext_type_len[] = {
+@@ -4823,6 +4827,9 @@ static const u8 skb_ext_type_len[] = {
  #if IS_ENABLED(CONFIG_MCTP_FLOWS)
  	[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
  #endif
diff --git a/target/linux/ipq40xx/patches-6.6/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch b/target/linux/ipq40xx/patches-6.6/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
index e0331d28ab..20dd345c69 100644
--- a/target/linux/ipq40xx/patches-6.6/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
+++ b/target/linux/ipq40xx/patches-6.6/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
@@ -654,7 +654,7 @@ Signed-off-by: Robert Marko <robert.marko@sartura.hr>
 +		}
 +	}
 +
-+	panic("PSGMII work is unstable !!! "
++	dev_err(priv->dev, "PSGMII work is unstable !!! "
 +		"Repeated recalibration attempts did not help(0x%x) !\n",
 +		test_result);
 +
diff --git a/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch b/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
index 6a37cc1f5e..50c8e64534 100644
--- a/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
+++ b/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
@@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  			status = "disabled";
  
 -			ethphy0: ethernet-phy@0 {
-+			ethernet-phy-package@0 {
++			qca807x: ethernet-phy-package@0 {
 +				#address-cells = <1>;
 +				#size-cells = <0>;
 +				compatible = "qcom,qca8075-package";
diff --git a/target/linux/ipq806x/Makefile b/target/linux/ipq806x/Makefile
index cd6f3dc2d3..6bb93d9725 100644
--- a/target/linux/ipq806x/Makefile
+++ b/target/linux/ipq806x/Makefile
@@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15
 CPU_SUBTYPE:=neon-vfpv4
 SUBTARGETS:=generic chromium
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 KERNELNAME:=zImage Image dtbs
 
diff --git a/target/linux/ipq806x/config-6.1 b/target/linux/ipq806x/config-6.1
deleted file mode 100644
index 18325c0346..0000000000
--- a/target/linux/ipq806x/config-6.1
+++ /dev/null
@@ -1,538 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_IPQ40XX is not set
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
-CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_ARM_QCOM_SPM_CPUIDLE=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEVFREQ_GOV_PASSIVE=y
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-# CONFIG_DWMAC_GENERIC is not set
-CONFIG_DWMAC_IPQ806X=y
-# CONFIG_DWMAC_QCOM_ETHQOS is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-CONFIG_IPQ_GCC_806X=y
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KPSS_XCC=y
-CONFIG_KRAITCC=y
-CONFIG_KRAIT_CLOCKS=y
-CONFIG_KRAIT_L2_ACCESSORS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ8064=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_QCOM_RPM=y
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=16
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSM_GCC_8660=y
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K=y
-CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
-CONFIG_NET_DSA_TAG_QCA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=y
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-CONFIG_PINCTRL_IPQ8064=y
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA83XX_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-CONFIG_QCOM_ADM=y
-CONFIG_QCOM_BAM_DMA=y
-CONFIG_QCOM_CLK_RPM=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-CONFIG_QCOM_GSBI=y
-CONFIG_QCOM_HFPLL=y
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMCC=y
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-CONFIG_QCOM_SPM=y
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-CONFIG_QCOM_TSENS=y
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-CONFIG_REGULATOR_QCOM_RPM=y
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
deleted file mode 100644
index 76751910e0..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
+++ /dev/null
@@ -1,743 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8062-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "NEC Platforms Aterm WG2600HP3";
-	compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
-
-	memory {
-		device_type = "memory";
-		reg =  <0x42000000 0x1e000000>;
-	};
-
-	aliases {
-		label-mac-device = &gmac2;
-
-		led-boot = &led_power_green;
-		led-failsafe = &led_power_red;
-		led-running = &led_power_green;
-		led-upgrade = &led_power_red;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		pinctrl-0 = <&buttons_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		mode0 {
-			label = "mode0";
-			gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		mode1 {
-			label = "mode1";
-			gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_1>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-0 = <&leds_pins>;
-		pinctrl-names = "default";
-
-		led_power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_power_red: power_red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
-		};
-
-		active_green {
-			label = "green:active";
-			gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
-		};
-
-		active_red {
-			label = "red:active";
-			gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_green {
-			label = "green:wlan2g";
-			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		wlan2g_red {
-			label = "red:wlan2g";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g_green {
-			label = "green:wlan5g";
-			gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		wlan5g_red {
-			label = "red:wlan5g";
-			gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		tv_green {
-			label = "green:tv";
-			gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
-		};
-
-		tv_red {
-			label = "red:tv";
-			gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
-		};
-
-		converter_green {
-			label = "green:converter";
-			gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
-		};
-
-		converter_red {
-			label = "red:converter";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-/* nand_pins are used for leds_pins, empty the node
- * from ipq8064.dtsi
- */
-&nand_pins {
-	/delete-property/ disable;
-	/delete-property/ pullups;
-	/delete-property/ hold;
-};
-
-&qcom_pinmux {
-	pinctrl-0 = <&akro_pins>;
-	pinctrl-names = "default";
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	buttons_pins: buttons_pins {
-		mux {
-			pins = "gpio22", "gpio24", "gpio40",
-				"gpio41";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	leds_pins: leds_pins {
-		mux {
-			pins = "gpio14", "gpio15", "gpio35",
-				"gpio36", "gpio38", "gpio42",
-				"gpio43", "gpio46", "gpio55",
-				"gpio56", "gpio57", "gpio58";
-			function = "gpio";
-			bias-pull-down;
-		};
-
-		akro2 {
-			pins = "gpio15", "gpio35", "gpio38",
-				"gpio42", "gpio43", "gpio46",
-				"gpio55", "gpio56", "gpio57",
-				"gpio58";
-			drive-strength = <2>;
-		};
-
-		akro4 {
-			pins = "gpio14", "gpio36";
-			drive-strength = <4>;
-		};
-	};
-
-	/*
-	 * Stock firmware has the following settings, so let's do the same.
-	 * I don't sure why these are required.
-	 */
-	akro_pins: akro_pinmux {
-		akro {
-			pins = "gpio17", "gpio26", "gpio47";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-
-		reset {
-			pins = "gpio45";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-disable;
-			output-low;
-		};
-
-		gmac0_rgmii {
-			pins = "gpio25";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-};
-
-&gsbi5 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			reg = <0>;
-			spi-max-frequency = <50000000>;
-			m25p,fast-read;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "SBL1";
-					reg = <0x0000000 0x0020000>;
-					read-only;
-				};
-
-				partition@20000 {
-					label = "MIBIB";
-					reg = <0x0020000 0x0020000>;
-					read-only;
-				};
-
-				partition@40000 {
-					label = "SBL2";
-					reg = <0x0040000 0x0040000>;
-					read-only;
-				};
-
-				partition@80000 {
-					label = "SBL3";
-					reg = <0x0080000 0x0080000>;
-					read-only;
-				};
-
-				partition@100000 {
-					label = "DDRCONFIG";
-					reg = <0x0100000 0x0010000>;
-					read-only;
-				};
-
-				partition@110000 {
-					label = "SSD";
-					reg = <0x0110000 0x0010000>;
-					read-only;
-				};
-
-				partition@120000 {
-					label = "TZ";
-					reg = <0x0120000 0x0080000>;
-					read-only;
-				};
-
-				partition@1a0000 {
-					label = "RPM";
-					reg = <0x01a0000 0x0080000>;
-					read-only;
-				};
-
-				partition@220000 {
-					label = "APPSBL";
-					reg = <0x0220000 0x0080000>;
-					read-only;
-				};
-
-				partition@2a0000 {
-					label = "APPSBLENV";
-					reg = <0x02a0000 0x0010000>;
-					read-only;
-				};
-
-				factory: partition@2b0000 {
-					label = "PRODUCTDATA";
-					reg = <0x02b0000 0x0030000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_factory_0: macaddr@0 {
-							reg = <0x0 0x6>;
-						};
-
-						macaddr_factory_6: macaddr@6 {
-							reg = <0x6 0x6>;
-						};
-
-						macaddr_PRODUCTDATA_c: macaddr@c {
-							reg = <0xc 0x6>;
-						};
-
-						macaddr_PRODUCTDATA_12: macaddr@12 {
-							reg = <0x12 0x6>;
-						};
-					};
-				};
-
-				partition@2e0000 {
-					label = "ART";
-					reg = <0x02e0000 0x0040000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						precal_ART_1000: precal@1000 {
-							reg = <0x1000 0x2f20>;
-						};
-
-						precal_ART_5000: precal@5000 {
-							reg = <0x5000 0x2f20>;
-						};
-					};
-				};
-
-				partition@320000 {
-					label = "TP";
-					reg = <0x0320000 0x0040000>;
-					read-only;
-				};
-
-				partition@360000 {
-					label = "TINY";
-					reg = <0x0360000 0x0500000>;
-					read-only;
-				};
-
-				partition@860000 {
-					compatible = "denx,uimage";
-					label = "firmware";
-					reg = <0x0860000 0x17a0000>;
-				};
-			};
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-
-			qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
-			nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	force_gen1 = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			reg = <0x00010000 0 0 0 0>;
-
-			ieee80211-freq-limit = <2400000 2483000>;
-			qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
-			nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_WAN;
-						function-enumerator = <1>;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_WAN;
-						function-enumerator = <2>;
-						default-state = "keep";
-					};
-
-					led@2 {
-						reg = <2>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_WAN;
-						function-enumerator = <3>;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <1>;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <2>;
-						default-state = "keep";
-					};
-
-					led@2 {
-						reg = <2>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <3>;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <1>;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <2>;
-						default-state = "keep";
-					};
-
-					led@2 {
-						reg = <2>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <3>;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <1>;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <2>;
-						default-state = "keep";
-					};
-
-					led@2 {
-						reg = <2>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <3>;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <1>;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <2>;
-						default-state = "keep";
-					};
-
-					led@2 {
-						reg = <2>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						function-enumerator = <3>;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-				qca,sgmii-rxclk-falling-edge;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	mdiobus = <&mdio0>;
-	nvmem-cells = <&macaddr_factory_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	mdiobus = <&mdio0>;
-	nvmem-cells = <&macaddr_factory_6>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
deleted file mode 100644
index f306201754..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
+++ /dev/null
@@ -1,487 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		ramoops@42100000 {
-			compatible = "ramoops";
-			reg = <0x42100000 0x40000>;
-			record-size = <0x4000>;
-			console-size = <0x4000>;
-			ftrace-size = <0x4000>;
-			pmsg-size = <0x4000>;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-		label-mac-device = &gmac2;
-	};
-};
-
-&qcom_pinmux {
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	usb0_pwr_en_pin: usb0_pwr_en_pin {
-		mux {
-			pins = "gpio25";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pin: usb1_pwr_en_pin {
-		mux {
-			pins = "gpio23";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-			output-high;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "SBL1";
-					reg = <0x0 0x20000>;
-					read-only;
-				};
-
-				partition@20000 {
-					label = "MIBIB";
-					reg = <0x20000 0x20000>;
-					read-only;
-				};
-
-				partition@40000 {
-					label = "SBL2";
-					reg = <0x40000 0x20000>;
-					read-only;
-				};
-
-				partition@60000 {
-					label = "SBL3";
-					reg = <0x60000 0x30000>;
-					read-only;
-				};
-
-				partition@90000 {
-					label = "DDRCONFIG";
-					reg = <0x90000 0x10000>;
-					read-only;
-				};
-
-				partition@a0000 {
-					label = "SSD";
-					reg = <0xa0000 0x10000>;
-					read-only;
-				};
-
-				partition@b0000 {
-					label = "TZ";
-					reg = <0xb0000 0x30000>;
-					read-only;
-				};
-
-				partition@e0000 {
-					label = "RPM";
-					reg = <0xe0000 0x20000>;
-					read-only;
-				};
-
-				partition@100000 {
-					label = "fs-uboot";
-					reg = <0x100000 0x70000>;
-					read-only;
-				};
-
-				partition@170000 {
-					label = "uboot-env";
-					reg = <0x170000 0x40000>;
-					read-only;
-				};
-
-				partition@1b0000 {
-					label = "radio";
-					reg = <0x1b0000 0x40000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						precal_radio_1000: precal@1000 {
-							reg = <0x1000 0x2f20>;
-						};
-
-						precal_radio_5000: precal@5000 {
-							reg = <0x5000 0x2f20>;
-						};
-					};
-				};
-
-				partition@1f0000 {
-					label = "os-image";
-					reg = <0x1f0000 0x400000>;
-				};
-
-				partition@5f0000 {
-					label = "rootfs";
-					reg = <0x5f0000 0x1900000>;
-				};
-
-				defaultmac: partition@1ef0000 {
-					label = "default-mac";
-					reg = <0x1ef0000 0x00200>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_defaultmac_8: macaddr@8 {
-							compatible = "mac-base";
-							reg = <0x8 0x6>;
-							#nvmem-cell-cells = <1>;
-						};
-					};
-				};
-
-				partition@1ef0200 {
-					label = "pin";
-					reg = <0x1ef0200 0x00200>;
-					read-only;
-				};
-
-				partition@1ef0400 {
-					label = "product-info";
-					reg = <0x1ef0400 0x0fc00>;
-					read-only;
-				};
-
-				partition@1f00000 {
-					label = "partition-table";
-					reg = <0x1f00000 0x10000>;
-					read-only;
-				};
-
-				partition@1f10000 {
-					label = "soft-version";
-					reg = <0x1f10000 0x10000>;
-					read-only;
-				};
-
-				partition@1f20000 {
-					label = "support-list";
-					reg = <0x1f20000 0x10000>;
-					read-only;
-				};
-
-				partition@1f30000 {
-					label = "profile";
-					reg = <0x1f30000 0x10000>;
-					read-only;
-				};
-
-				partition@1f40000 {
-					label = "default-config";
-					reg = <0x1f40000 0x10000>;
-					read-only;
-				};
-
-				partition@1f50000 {
-					label = "user-config";
-					reg = <0x1f50000 0x40000>;
-					read-only;
-				};
-
-				partition@1f90000 {
-					label = "qos-db";
-					reg = <0x1f90000 0x40000>;
-					read-only;
-				};
-
-				partition@1fd0000 {
-					label = "usb-config";
-					reg = <0x1fd0000 0x10000>;
-					read-only;
-				};
-
-				partition@1fe0000 {
-					label = "log";
-					reg = <0x1fe0000 0x20000>;
-					read-only;
-				};
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pin>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pin>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_defaultmac_8 (-1)>, <&precal_radio_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_defaultmac_8 0>, <&precal_radio_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_defaultmac_8 1>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_defaultmac_8 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts
deleted file mode 100644
index 6e4c9bc773..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
-	model = "TP-Link Talon AD7200";
-	compatible = "tplink,ad7200", "qcom,ipq8064";
-
-	aliases {
-		led-boot = &led_status;
-		led-failsafe = &led_status;
-		led-running = &led_status;
-		led-upgrade = &led_status;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		led_enable {
-			label = "led-enable";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_LIGHTS_TOGGLE>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		lan {
-			function = LED_FUNCTION_LAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb1 {
-			label = "blue:usb1";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "blue:wlan5g";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb3 {
-			label = "blue:usb3";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g {
-			label = "blue:wlan2g";
-			gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_orange {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		wan_blue {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan60g {
-			label = "blue:wlan60g";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status: status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio53", "gpio54", "gpio67";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26",
-					"gpio33", "gpio55", "gpio56", "gpio66";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
-
-&mdio0 {
-	switch@10 {
-		ports {
-			port@1 {
-				label = "wan";
-			};
-
-			port@2 {
-				label = "lan1";
-			};
-
-			port@3 {
-				label = "lan2";
-			};
-
-			port@4 {
-				label = "lan3";
-			};
-
-			port@5 {
-				label = "lan4";
-			};
-		};
-	};
-};
-
-&pcie2 {
-	status = "okay";
-	max-link-speed = <1>;
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
deleted file mode 100644
index bd8f0d6019..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ /dev/null
@@ -1,219 +0,0 @@
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
-	model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
-	compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&flash {
-	partitions {
-		compatible = "qcom,smem-part";
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "qcom,smem-part";
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			/*
-			port@6 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "rgmii";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-					pause;
-					asym-pause;
-				};
-			};
-			*/
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
deleted file mode 100644
index 9d0b451f43..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
+++ /dev/null
@@ -1,254 +0,0 @@
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
-	model = "Qualcomm IPQ8064/AP161";
-	compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-	};
-};
-
-&qcom_pinmux {
-	rgmii2_pins: rgmii2-pins {
-		mux {
-			pins = "gpio27", "gpio28", "gpio29",
-			       "gpio30", "gpio31", "gpio32",
-			       "gpio51", "gpio52", "gpio59",
-			       "gpio60", "gpio61", "gpio62",
-			       "gpio2", "gpio66";
-		};
-	};
-};
-
-&flash {
-	partitions {
-		compatible = "qcom,smem-part";
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-};
-
-&pcie2 {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "qcom,smem-part";
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac0>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			/*
-			port@6 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "rgmii";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-					pause;
-					asym-pause;
-				};
-			};
-			*/
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-
-	phy3: ethernet-phy@3 {
-		device_type = "ethernet-phy";
-		reg = <3>;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts
deleted file mode 100644
index 442bcf19a6..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-asus-onhub.dts
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
-	model = "ASUS OnHub";
-	compatible = "asus,onhub", "google,arkham", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
-	ap3223_pins: ap3223_pinmux {
-		pins = "gpio22";
-		function = "gpio";
-		bias-none;
-	};
-
-	i2c7_pins: i2c7_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "gsbi7";
-		};
-		data {
-			pins = "gpio8";
-			bias-disable;
-		};
-		clk {
-			pins = "gpio9";
-			bias-disable;
-		};
-	};
-};
-
-&gsbi7 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
-	status = "okay";
-	clock-frequency = <100000>;
-	pinctrl-0 = <&i2c7_pins>;
-	pinctrl-names = "default";
-
-	ap3223@1c {
-		compatible = "dynaimage,ap3223";
-		reg = <0x1c>;
-
-		pinctrl-0 = <&ap3223_pins>;
-		pinctrl-names = "default";
-
-		int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
-	};
-
-	led-controller@32 {
-		compatible = "national,lp5523";
-		reg = <0x32>;
-		clock-mode = /bits/ 8 <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led@4 {
-			reg = <4>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-		};
-
-		led@5 {
-			reg = <5>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-		};
-
-		led@8 {
-			reg = <8>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status";
-			led-cur = /bits/ 8 <0xfa>;
-			max-cur = /bits/ 8 <0xff>;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
deleted file mode 100644
index b8cb25ede0..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
+++ /dev/null
@@ -1,126 +0,0 @@
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
-	model = "TP-Link Archer C2600";
-	compatible = "tplink,c2600", "qcom,ipq8064";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &general;
-		led-running = &power;
-		led-upgrade = &general;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		ledswitch {
-			label = "ledswitch";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_LIGHTS_TOGGLE>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		lan {
-			function = LED_FUNCTION_LAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb4 {
-			label = "white:usb_4";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb2 {
-			label = "white:usb_2";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		wan_white {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		general: general {
-			label = "white:general";
-			gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio16", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
-					"gpio53", "gpio66";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
deleted file mode 100644
index 8077c3a090..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
+++ /dev/null
@@ -1,485 +0,0 @@
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Netgear Nighthawk X4 D7800";
-	compatible = "netgear,d7800", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		rsvd@5fe00000 {
-			reg = <0x5fe00000 0x200000>;
-			reusable;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power_white;
-		led-failsafe = &power_amber;
-		led-running = &power_white;
-		led-upgrade = &power_amber;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		usb1 {
-			label = "white:usb1";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb2 {
-			label = "white:usb2";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_amber: power_amber {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_white {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		esata {
-			label = "white:esata";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_white: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
-				"gpio24","gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio68";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie2 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie2_pins>;
-	pinctrl-names = "default";
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			qcadata@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			APPSBL@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			APPSBLENV@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			artbak: art@1340000 {
-				label = "artbak";
-				reg = <0x1340000 0x0140000>;
-				read-only;
-			};
-
-			kernel@1480000 {
-				label = "kernel";
-				reg = <0x1480000 0x0400000>;
-			};
-
-			ubi@1880000 {
-				label = "ubi";
-				reg = <0x1880000 0x6080000>;
-			};
-
-			reserve@7900000 {
-				label = "reserve";
-				reg = <0x7900000 0x0700000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_art_6 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts
deleted file mode 100644
index 063f27c6d2..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ /dev/null
@@ -1,263 +0,0 @@
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
-	model = "Qualcomm IPQ8064/DB149";
-	compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
-
-	aliases {
-		serial0 = &gsbi2_serial;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-};
-
-&qcom_pinmux {
-	rgmii0_pins: rgmii0_pins {
-		mux {
-			pins = "gpio2", "gpio66";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-};
-
-&gsbi2 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-	status = "okay";
-
-	gsbi2_serial: serial@12490000 {
-		status = "okay";
-	};
-};
-
-&gsbi4 {
-	status = "disabled";
-};
-
-&gsbi4_serial {
-	status = "disabled";
-};
-
-&flash {
-	m25p,fast-read;
-
-	partition@0 {
-		label = "lowlevel_init";
-		reg = <0x0 0x1b0000>;
-	};
-
-	partition@1 {
-		label = "u-boot";
-		reg = <0x1b0000 0x80000>;
-	};
-
-	partition@2 {
-		label = "u-boot-env";
-		reg = <0x230000 0x40000>;
-	};
-
-	partition@3 {
-		label = "caldata";
-		reg = <0x270000 0x40000>;
-	};
-
-	partition@4 {
-		label = "firmware";
-		reg = <0x2b0000 0x1d50000>;
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac0>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			/*
-			port@6 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "rgmii";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-					pause;
-					asym-pause;
-				};
-			};
-			*/
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-
-	phy6: ethernet-phy@6 {
-		reg = <6>;
-	};
-
-	phy7: ethernet-phy@7 {
-		reg = <7>;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-
-	pinctrl-0 = <&rgmii0_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <1>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	phy-handle = <&phy6>;
-};
-
-&gmac3 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <3>;
-	phy-handle = <&phy7>;
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts
deleted file mode 100644
index 2a565cc2db..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts
+++ /dev/null
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
-	model = "Linksys EA7500 V1 WiFi Router";
-	compatible = "linksys,ea7500-v1", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0xe000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	chosen {
-		/* look for root deviceblock nbr in this bootarg */
-		find-rootblock = "ubi.mtd=";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio65", "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio6";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
-
-&partitions {
-	partition@5f80000 {
-		label = "sysdiag";
-		reg = <0x5f80000 0x100000>;
-	};
-
-	partition@6080000 {
-		label = "syscfg";
-		reg = <0x6080000 0x1f80000>;
-	};
-};
-
-&mdio0 {
-	switch@10 {
-		ports {
-			port@1 {
-				label = "wan";
-			};
-
-			port@2 {
-				label = "lan1";
-			};
-
-			port@3 {
-				label = "lan2";
-			};
-
-			port@4 {
-				label = "lan3";
-			};
-
-			port@5 {
-				label = "lan4";
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
deleted file mode 100644
index d9155081a5..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ /dev/null
@@ -1,126 +0,0 @@
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
-	model = "Linksys EA8500 WiFi Router";
-	compatible = "linksys,ea8500", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		wifi {
-			label = "green:wifi";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio65", "gpio67", "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio6", "gpio53", "gpio54";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&partitions {
-	partition@5f80000 {
-		label = "syscfg";
-		reg = <0x5f80000 0x2080000>;
-	};
-};
-
-&gmac1 {
-	qcom,phy_mdio_addr = <4>;
-	qcom,poll_required = <1>;
-	qcom,rgmii_delay = <0>;
-	qcom,emulation = <0>;
-};
-
-/* LAN */
-&gmac2 {
-	qcom,phy_mdio_addr = <0>;	/* none */
-	qcom,poll_required = <0>;	/* no polling */
-	qcom,rgmii_delay = <0>;
-	qcom,emulation = <0>;
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
deleted file mode 100644
index e5cc242419..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
+++ /dev/null
@@ -1,317 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-	chosen {
-		bootargs = "console=ttyMSM0,115200n8";
-		/* append to bootargs adding the root deviceblock nbr from bootloader */
-		append-rootblock = "ubi.mtd=";
-	};
-};
-
-&qcom_pinmux {
-	/* eax500 routers reuse the pcie2 reset pin for switch reset pin */
-	switch_reset: switch_reset_pins {
-		mux {
-			pins = "gpio63";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-up;
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	max-link-speed = <1>;
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x0c80000>;
-
-		partitions: partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "MIBIB";
-				reg = <0x0040000 0x0140000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "SBL2";
-				reg = <0x0180000 0x0140000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "SBL3";
-				reg = <0x02c0000 0x0280000>;
-				read-only;
-			};
-
-			partition@540000 {
-				label = "DDRCONFIG";
-				reg = <0x0540000 0x0120000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "SSD";
-				reg = <0x0660000 0x0120000>;
-				read-only;
-			};
-
-			partition@780000 {
-				label = "TZ";
-				reg = <0x0780000 0x0280000>;
-				read-only;
-			};
-
-			partition@a00000 {
-				label = "RPM";
-				reg = <0x0a00000 0x0280000>;
-				read-only;
-			};
-
-			art: partition@c80000 {
-				label = "art";
-				reg = <0x0c80000 0x0140000>;
-				read-only;
-			};
-
-			partition@dc0000 {
-				label = "APPSBL";
-				reg = <0x0dc0000 0x0100000>;
-				read-only;
-			};
-
-			partition@ec0000 {
-				label = "u_env";
-				reg = <0x0ec0000 0x0040000>;
-			};
-
-			partition@f00000 {
-				label = "s_env";
-				reg = <0x0f00000 0x0040000>;
-			};
-
-			partition@f40000 {
-				label = "devinfo";
-				reg = <0x0f40000 0x0040000>;
-			};
-
-			partition@f80000 {
-				label = "kernel1";
-				reg = <0x0f80000 0x2800000>;  /* 4 MB, spill to rootfs */
-			};
-
-			partition@1380000 {
-				label = "rootfs1";
-				reg = <0x1380000 0x2400000>;
-			};
-
-			partition@3780000 {
-				label = "kernel2";
-				reg = <0x3780000 0x2800000>;
-			};
-
-			partition@3b80000 {
-				label = "rootfs2";
-				reg = <0x3b80000 0x2400000>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	/* Switch from documentation require at least 10ms for reset */
-	reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
-	reset-post-delay-us = <12000>;
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts
deleted file mode 100644
index bb66c6c808..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts
+++ /dev/null
@@ -1,413 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Fortinet FAP-421E";
-	compatible = "fortinet,fap-421e", "qcom,ipq8064";
-
-	memory@42000000 {
-		device_type = "memory";
-		reg = <0x42000000 0xe000000>;
-	};
-
-	reserved-memory {
-		rsvd@41200000 {
-			no-map;
-			reg = <0x41200000 0x300000>;
-		};
-		wifi_dump@44000000 {
-			no-map;
-			reg = <0x44000000 0x600000>;
-		};
-	};
-
-	aliases {
-		led-boot = &led_power_yellow;
-		led-failsafe = &led_power_yellow;
-		led-running = &led_power_yellow;
-		led-upgrade = &led_power_yellow;
-		label-mac-device = &gmac0;
-	};
-
-	chosen {
-		bootargs-override = "console=ttyMSM0,9600n8";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-		
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		eth1-amber {
-			label = "amber:eth1";
-			gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
-		};
-
-		eth1-yellow {
-			label = "yellow:eth1";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		eth2-amber {
-			label = "amber:eth2";
-			gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
-		};
-
-		eth2-yellow {
-			label = "yellow:eth2";
-			gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
-		};
-
-		power-amber {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
-		};
-
-		led_power_yellow: power-yellow {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_YELLOW>;
-			gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
-		};
-
-		2g-yellow {
-			label = "yellow:2g";
-			gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
-		};
-
-		5g-yellow {
-			label = "yellow:5g";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			bias-pull-up;
-			drive-strength = <2>;
-			pins = "gpio56";
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			bias-pull-down;
-			drive-strength = <2>;
-			function = "gpio";
-			output-low;
-			pins = "gpio23";
-		};
-	};
-
-	rgmii2_pins: rgmii2-pins {
-		mux {
-			bias-disable;
-			drive-strength = <16>;
-			function = "rgmii2";
-			pins = "gpio66";
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	uart0_pins: uart0_pins {
-		mux {
-			bias-disable;
-			drive-strength = <12>;
-			function = "gsbi7";
-			pins = "gpio6", "gpio7";
-		};
-	};
-	
-	usb_pwr_en_pins: usb_pwr_en_pins {
-		mux {
-			pins = "gpio22";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-low;
-		};
-	};
-};
-
-&gsbi7 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-
-	status = "okay";
-};
-
-&gsbi7_serial{
-	pinctrl-0 = <&uart0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	status = "okay";
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-			m25p,fast-read;
-
-			partition@0 {
-				label = "SBL1";
-				reg = <0x0 0x20000>;
-				read-only;
-			};
-
-			partition@20000 {
-				label = "MIBIB";
-				reg = <0x20000 0x20000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "SBL2";
-				reg = <0x40000 0x40000>;
-				read-only;
-			};
-
-			partition@80000 {
-				label = "SBL3";
-				reg = <0x80000 0x80000>;
-				read-only;
-			};
-
-			partition@100000 {
-				label = "DDRCONFIG";
-				reg = <0x100000 0x10000>;
-				read-only;
-			};
-
-			partition@110000 {
-				label = "SSD";
-				reg = <0x110000 0x10000>;
-				read-only;
-			};
-
-			partition@120000 {
-				label = "TZ";
-				reg = <0x120000 0x80000>;
-				read-only;
-			};
-
-			partition@1a0000 {
-				label = "RPM";
-				reg = <0x1a0000 0x80000>;
-				read-only;
-			};
-
-			partition@220000 {
-				label = "APPSBL";
-				reg = <0x220000 0x80000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_appsbl_7ff80: mac-address@7ff80 {
-						compatible = "mac-base";
-						reg = <0x7ff80 0xc>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@2a0000 {
-				label = "APPSBLENV";
-				reg = <0x2a0000 0x40000>;
-			};
-
-			partition@2e0000 {
-				label = "ART";
-				reg = <0x2e0000 0x40000>;
-				read-only;
-			};
-
-			partition@320000 {
-				label = "kernel";
-				reg = <0x320000 0x600000>;
-			};
-
-			partition@920000 {
-				label = "ubi";
-				reg = <0x920000 0x1400000>;
-			};
-
-			partition@1d20000 {
-				label = "reserved";
-				reg = <0x1d20000 0x260000>;
-				read-only;
-			};
-
-			partition@1f80000 {
-				label = "config";
-				reg = <0x1f80000 0x80000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_appsbl_7ff80 8>;
-			nvmem-cell-names = "mac-address";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_appsbl_7ff80 16>;
-			nvmem-cell-names = "mac-address";
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	#address-cells = <0x1>;
-	#size-cells = <0x0>;
-	gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-			<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-
-	phy2: ethernet-phy@2 {
-		reg = <2>;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-	nvmem-cells = <&macaddr_appsbl_7ff80 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	nvmem-cells = <&macaddr_appsbl_7ff80 1>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts
deleted file mode 100644
index 24273291cb..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-g10.dts
+++ /dev/null
@@ -1,383 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	compatible = "asrock,g10", "qcom,ipq8064";
-	model = "ASRock G10";
-
-	aliases {
-		ethernet0 = &gmac1;
-		ethernet1 = &gmac0;
-
-		led-boot = &led_status_blue;
-		led-failsafe = &led_status_amber;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_amber;
-	};
-
-	chosen {
-		bootargs-override = "console=ttyMSM0,115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		/*
-		 * this is a bit misleading. Because there are about seven
-		 * multicolor LEDs connected all wired together in parallel.
-		 */
-
-		status_yellow {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_YELLOW>;
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_amber: status_amber {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_blue: status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		/*
-		 * LED is declared in vendors boardfile but it's not
-		 * working and the manual doesn't mention anything
-		 * about the LED being white.
-
-		status_white {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-		*/
-	};
-
-	i2c-gpio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		compatible = "i2c-gpio";
-		gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
-			<&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
-		i2c-gpio,delay-us = <5>;
-		i2c-gpio,scl-output-only;
-
-		mcu@50 {
-			reg = <0x50>;
-			compatible = "sonix,sn8f25e21";
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		ir-remote {
-			label = "ir-remote";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps5g {
-			label = "wps5g";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps2g {
-			label = "wps2g";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&gmac1 {
-	status = "okay";
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gsbi4_serial {
-	pinctrl-0 = <&uart0_pins>;
-	pinctrl-names = "default";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1200000>;
-
-		partitions {
-			compatible = "qcom,smem-part";
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi5g: wifi@1,0 {
-			reg = <0x00010000 0 0 0 0>;
-			compatible = "qcom,ath10k";
-			qcom,ath10k-calibration-variant = "ASRock-G10";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2g: wifi@1,0 {
-			reg = <0x00010000 0 0 0 0>;
-			compatible = "qcom,ath10k";
-			qcom,ath10k-calibration-variant = "ASRock-G10";
-		};
-	};
-};
-
-&qcom_pinmux {
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio26";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio15", "gpio16", "gpio64", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	uart0_pins: uart0_pins {
-		mux {
-			pins = "gpio10", "gpio11";
-			function = "gsbi4";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-};
-
-&rpm {
-	pinctrl-0 = <&i2c4_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&tcsr {
-	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-/delete-node/ &pcie2_pins;
-/delete-node/ &pcie2;
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi
deleted file mode 100644
index 5b8de27ad6..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-onhub.dtsi
+++ /dev/null
@@ -1,545 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	aliases {
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac2;
-		mdio-gpio0 = &mdio;
-		serial0 = &gsbi4_serial;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		dev {
-			label = "dev";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_CONFIG>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	mdio: mdio {
-		compatible = "virtual,mdio-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-			<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-		pinctrl-0 = <&mdio_pins>;
-		pinctrl-names = "default";
-
-		switch@10 {
-			compatible = "qca,qca8337";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x10>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "cpu";
-					ethernet = <&gmac0>;
-					phy-mode = "rgmii";
-					tx-internal-delay-ps = <1000>;
-					rx-internal-delay-ps = <1000>;
-
-					fixed-link {
-						speed = <1000>;
-						full-duplex;
-					};
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "lan1";
-					phy-mode = "internal";
-					phy-handle = <&phy_port1>;
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "wan";
-					phy-mode = "internal";
-					phy-handle = <&phy_port2>;
-				};
-
-				port@6 {
-					reg = <6>;
-					label = "cpu";
-					ethernet = <&gmac2>;
-					phy-mode = "sgmii";
-					qca,sgmii-enable-pll;
-
-					fixed-link {
-						speed = <1000>;
-						full-duplex;
-					};
-				};
-			};
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				phy_port1: phy@0 {
-					reg = <0>;
-				};
-
-				phy_port2: phy@1 {
-					reg = <1>;
-				};
-			};
-		};
-	};
-
-	soc {
-		rng@1a500000 {
-			status = "disabled";
-		};
-
-		sound {
-			compatible = "google,storm-audio";
-			qcom,model = "ipq806x-storm";
-			cpu = <&lpass>;
-			codec = <&max98357a>;
-		};
-
-		lpass: lpass@28100000 {
-			status = "okay";
-			pinctrl-names = "default", "idle";
-			pinctrl-0 = <&mi2s_default>;
-			pinctrl-1 = <&mi2s_idle>;
-		};
-
-		max98357a: max98357a {
-			compatible = "maxim,max98357a";
-			#sound-dai-cells = <1>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&sdmode_pins>;
-			sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	rgmii0_pins: rgmii0_pins {
-		mux {
-			pins = "gpio2", "gpio66";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-	mi2s_pins {
-		mi2s_default: mi2s_default {
-			dout {
-				pins = "gpio32";
-				function = "mi2s";
-				drive-strength = <16>;
-				bias-disable;
-			};
-			sync {
-				pins = "gpio27";
-				function = "mi2s";
-				drive-strength = <16>;
-				bias-disable;
-			};
-			clk {
-				pins = "gpio28";
-				function = "mi2s";
-				drive-strength = <16>;
-				bias-disable;
-			};
-		};
-		mi2s_idle: mi2s_idle {
-			dout {
-				pins = "gpio32";
-				function = "mi2s";
-				drive-strength = <2>;
-				bias-pull-down;
-			};
-			sync {
-				pins = "gpio27";
-				function = "mi2s";
-				drive-strength = <2>;
-				bias-pull-down;
-			};
-			clk {
-				pins = "gpio28";
-				function = "mi2s";
-				drive-strength = <2>;
-				bias-pull-down;
-			};
-		};
-	};
-
-	mdio_pins: mdio_pins {
-		mux {
-			pins = "gpio0", "gpio1";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-disable;
-		};
-		rst {
-			pins = "gpio26";
-			output-low;
-		};
-	};
-
-	sdmode_pins: sdmode_pinmux {
-		pins = "gpio25";
-		function = "gpio";
-		drive-strength = <16>;
-		bias-disable;
-	};
-
-	sdcc1_pins: sdcc1_pinmux {
-		mux {
-			pins = "gpio38", "gpio39", "gpio40",
-			       "gpio41", "gpio42", "gpio43",
-			       "gpio44", "gpio45", "gpio46",
-			       "gpio47";
-			function = "sdc1";
-		};
-		cmd {
-			pins = "gpio45";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-		data {
-			pins = "gpio38", "gpio39", "gpio40",
-			       "gpio41", "gpio43", "gpio44",
-			       "gpio46", "gpio47";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-		clk {
-			pins = "gpio42";
-			drive-strength = <16>;
-			bias-pull-down;
-		};
-	};
-
-	i2c1_pins: i2c1_pinmux {
-		pins = "gpio53", "gpio54";
-		function = "gsbi1";
-		bias-disable;
-	};
-
-	rpm_i2c_pinmux: rpm_i2c_pinmux {
-		mux {
-			pins = "gpio12", "gpio13";
-			function = "gsbi4";
-			drive-strength = <12>;
-			bias-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-			/delete-property/ bias-none;
-			/delete-property/ drive-strength;
-		};
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	fw_pinmux {
-		wp {
-			pins = "gpio17";
-			output-low;
-		};
-	};
-
-	button_pins: button_pins {
-		recovery {
-			pins = "gpio16";
-			function = "gpio";
-			bias-none;
-		};
-		developer {
-			pins = "gpio15";
-			function = "gpio";
-			bias-none;
-		};
-	};
-
-	spi6_pins: spi6_pins {
-		mux {
-			pins = "gpio55", "gpio56", "gpio58";
-			function = "gsbi6";
-			bias-pull-down;
-		};
-		data {
-			pins = "gpio55", "gpio56";
-			drive-strength = <10>;
-		};
-		cs {
-			pins = "gpio57";
-			drive-strength = <10>;
-			bias-pull-up;
-			output-high;
-		};
-		clk {
-			pins = "gpio58";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-
-	pinctrl-0 = <&rgmii0_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gsbi1 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi1_i2c {
-	status = "okay";
-
-	clock-frequency = <100000>;
-
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-names = "default";
-
-	tpm@20 {
-		compatible = "infineon,slb9645tt";
-		reg = <0x20>;
-		powered-while-suspended;
-	};
-};
-
-&gsbi4 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi4_serial {
-	status = "okay";
-};
-
-&gsbi5 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	spi4: spi@1a280000 {
-		status = "okay";
-		spi-max-frequency = <50000000>;
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 0>;
-
-		flash: flash@0 {
-			compatible = "jedec,spi-nor";
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-		};
-	};
-};
-
-&gsbi6 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_SPI>;
-};
-
-&gsbi6_spi {
-	status = "okay";
-	spi-max-frequency = <25000000>;
-
-	pinctrl-0 = <&spi6_pins>;
-	pinctrl-names = "default";
-
-	cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
-
-	dmas = <&adm_dma 8 0xb>,
-	       <&adm_dma 7 0x14>;
-	dma-names = "rx", "tx";
-
-	/*
-	 * This "spidev" was included in the manufacturer device tree. I suspect
-	 * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
-	 * no driver or binding for this at the moment.
-	 */
-	spidev@0 {
-		compatible = "spidev";
-		reg = <0>;
-		spi-max-frequency = <25000000>;
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	pcie@0 {
-		reg = <0 0 0 0 0>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		#address-cells = <3>;
-		device_type = "pci";
-		interrupt-controller;
-
-		ath10k@0,0 {
-			reg = <0 0 0 0 0>;
-			device_type = "pci";
-			qcom,ath10k-sa-gpio = <2 3 4 0>;
-			qcom,ath10k-sa-gpio-func = <5 5 5 0>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	pcie@0 {
-		reg = <0 0 0 0 0>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		#address-cells = <3>;
-		device_type = "pci";
-		interrupt-controller;
-
-		ath10k@0,0 {
-			reg = <0 0 0 0 0>;
-			device_type = "pci";
-			qcom,ath10k-sa-gpio = <2 3 4 0>;
-			qcom,ath10k-sa-gpio-func = <5 5 5 0>;
-		};
-	};
-};
-
-&pcie2 {
-	status = "okay";
-
-	pcie@0 {
-		reg = <0 0 0 0 0>;
-		#interrupt-cells = <1>;
-		#size-cells = <2>;
-		#address-cells = <3>;
-		device_type = "pci";
-		interrupt-controller;
-
-		ath10k@0,0 {
-			reg = <0 0 0 0 0>;
-			device_type = "pci";
-		};
-	};
-};
-
-&rpm {
-	pinctrl-0 = <&rpm_i2c_pinmux>;
-	pinctrl-names = "default";
-};
-
-&sdcc1 {
-	status = "okay";
-	pinctrl-0 = <&sdcc1_pins>;
-	pinctrl-names = "default";
-	/delete-property/ mmc-ddr-1_8v;
-};
-
-&tcsr {
-	compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
-	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
deleted file mode 100644
index c2703b05d7..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
+++ /dev/null
@@ -1,415 +0,0 @@
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Netgear Nighthawk X4 R7500";
-	compatible = "netgear,r7500", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0xe000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		rsvd@41200000 {
-			reg = <0x41200000 0x300000>;
-			no-map;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power_white;
-		led-failsafe = &power_amber;
-		led-running = &power_white;
-		led-upgrade = &power_amber;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		usb1 {
-			label = "white:usb1";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb2 {
-			label = "white:usb2";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_amber: power_amber {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_white {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		esata {
-			label = "white:esata";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_white: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
-				"gpio24","gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-};
-
-&gsbi5 {
-	status = "disabled";
-
-	spi@1a280000 {
-		status = "disabled";
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			qcadata@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			APPSBL@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			APPSBLENV@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art: art@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-				};
-			};
-
-			kernel@1340000 {
-				label = "kernel";
-				reg = <0x1340000 0x0400000>;
-			};
-
-			ubi@1740000 {
-				label = "ubi";
-				reg = <0x1740000 0x1600000>;
-			};
-
-			netgear@2d40000 {
-				label = "netgear";
-				reg = <0x2d40000 0x0c00000>;
-				read-only;
-			};
-
-			reserve@3940000 {
-				label = "reserve";
-				reg = <0x3940000 0x46c0000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_art_6>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&tcsr {
-	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-	compatible = "qcom,tcsr";
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
deleted file mode 100644
index 6c52d51ebc..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
+++ /dev/null
@@ -1,477 +0,0 @@
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Netgear Nighthawk X4 R7500v2";
-	compatible = "netgear,r7500v2", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		rsvd@5fe00000 {
-			reg = <0x5fe00000 0x200000>;
-			reusable;
-		};
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		usb1 {
-			label = "amber:usb1";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb3 {
-			label = "amber:usb3";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		status {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		internet {
-			label = "white:internet";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		esata {
-			label = "white:esata";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
-				"gpio24","gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio68";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1180000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			qcadata@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			APPSBL@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			APPSBLENV@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			artbak: art@1340000 {
-				label = "artbak";
-				reg = <0x1340000 0x0140000>;
-				read-only;
-			};
-
-			kernel@1480000 {
-				label = "kernel";
-				reg = <0x1480000 0x0400000>;
-			};
-
-			ubi@1880000 {
-				label = "ubi";
-				reg = <0x1880000 0x6080000>;
-			};
-
-			reserve@7900000 {
-				label = "reserve";
-				reg = <0x7900000 0x0700000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_art_6 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts
deleted file mode 100644
index 6adc6be4ae..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-tplink-onhub.dts
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
-	model = "TP-Link OnHub";
-	compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
-	i2c7_pins: i2c7_pinmux {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "gsbi7";
-		};
-		data {
-			pins = "gpio8";
-			bias-disable;
-		};
-		clk {
-			pins = "gpio9";
-			bias-disable;
-		};
-	};
-};
-
-&gsbi7 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
-	status = "okay";
-	clock-frequency = <100000>;
-	pinctrl-0 = <&i2c7_pins>;
-	pinctrl-names = "default";
-
-	led-controller@32 {
-		compatible = "national,lp5523";
-		reg = <0x32>;
-		clock-mode = /bits/ 8 <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led@0 {
-			reg = <0>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-0";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@1 {
-			reg = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-0";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@2 {
-			reg = <2>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-0";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@3 {
-			reg = <3>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-1";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@4 {
-			reg = <4>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-1";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@5 {
-			reg = <5>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-1";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@6 {
-			reg = <6>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-2";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@7 {
-			reg = <7>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-2";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@8 {
-			reg = <8>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-2";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-	};
-
-	led-controller@33 {
-		compatible = "national,lp5523";
-		reg = <0x33>;
-		clock-mode = /bits/ 8 <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		led@0 {
-			reg = <0>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-3";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@1 {
-			reg = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-3";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@2 {
-			reg = <2>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-3";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@3 {
-			reg = <3>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-4";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@4 {
-			reg = <4>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-4";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@5 {
-			reg = <5>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-4";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@6 {
-			reg = <6>;
-			color = <LED_COLOR_ID_RED>;
-			chan-name = "red:status-5";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@7 {
-			reg = <7>;
-			color = <LED_COLOR_ID_GREEN>;
-			chan-name = "green:status-5";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-
-		led@8 {
-			reg = <8>;
-			color = <LED_COLOR_ID_BLUE>;
-			chan-name = "blue:status-5";
-			linux,default-trigger = "default-on";
-			led-cur = /bits/ 8 <0x64>;
-			max-cur = /bits/ 8 <0x78>;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
deleted file mode 100644
index fac41897d4..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Ubiquiti UniFi AC HD";
-	compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064";
-
-	aliases {
-		label-mac-device = &gmac2;
-		led-boot = &led_dome_white;
-		led-failsafe = &led_dome_white;
-		led-running = &led_dome_blue;
-		led-upgrade = &led_dome_blue;
-		mdio-gpio0 = &mdio0;
-		ethernet0 = &gmac2;
-		ethernet1 = &gmac1;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_dome_blue: dome_blue {
-			label = "blue:dome";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_dome_white: dome_white {
-			label = "white:dome";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio9", "gpio53";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-			output-low;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			drive-strength = <10>;
-			bias-none;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&CPU_SPC {
-	status = "disabled";
-};
-
-&gsbi5 {
-	status = "okay";
-
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-		cs-gpios = <&qcom_pinmux 20 0>;
-
-		flash@0 {
-			compatible = "mx25u25635f", "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-			m25p,fast-read;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "SBL1";
-					reg = <0x0 0x20000>;
-					read-only;
-				};
-
-				partition@20000 {
-					label = "MIBIB";
-					reg = <0x20000 0x10000>;
-					read-only;
-				};
-
-				partition@30000 {
-					label = "SBL2";
-					reg = <0x30000 0x20000>;
-					read-only;
-				};
-
-				partition@50000 {
-					label = "SBL3";
-					reg = <0x50000 0x30000>;
-					read-only;
-				};
-
-				partition@80000 {
-					label = "DDRCONFIG";
-					reg = <0x80000 0x10000>;
-					read-only;
-				};
-
-				partition@90000 {
-					label = "SSD";
-					reg = <0x90000 0x10000>;
-					read-only;
-				};
-
-				partition@a0000 {
-					label = "TZ";
-					reg = <0xa0000 0x30000>;
-					read-only;
-				};
-
-				partition@d0000 {
-					label = "RPM";
-					reg = <0xd0000 0x20000>;
-					read-only;
-				};
-
-				partition@f0000 {
-					label = "APPSBL";
-					reg = <0xf0000 0xc0000>;
-					read-only;
-				};
-
-				partition@1b0000 {
-					label = "APPSBLENV";
-					reg = <0x1b0000 0x10000>;
-					read-only;
-				};
-
-				eeprom: partition@1c0000 {
-					label = "EEPROM";
-					reg = <0x1c0000 0x10000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_eeprom_0: macaddr@0 {
-							reg = <0x0 0x6>;
-						};
-
-						macaddr_eeprom_6: macaddr@6 {
-							reg = <0x6 0x6>;
-						};
-					};
-				};
-
-				partition@1d0000 {
-					label = "bootselect";
-					reg = <0x1d0000 0x10000>;
-				};
-
-				partition@1e0000 {
-					compatible = "denx,fit";
-					label = "firmware";
-					reg = <0x1e0000 0xe70000>;
-				};
-
-				partition@1050000 {
-					label = "kernel1";
-					reg = <0x1050000 0xe70000>;
-					read-only;
-				};
-
-				partition@1ec0000 {
-					label = "debug";
-					reg = <0x1ec0000 0x100000>;
-					read-only;
-				};
-
-				partition@1fc0000 {
-					label = "cfg";
-					reg = <0x1fc0000 0x40000>;
-					read-only;
-				};
-			};
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	nand-ecc-strength = <4>;
-	nand-bus-width = <8>;
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-
-	phy5: ethernet-phy@5 {
-		reg = <5>;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	mdiobus = <&mdio0>;
-	phy-handle = <&phy5>;
-	phy-mode = "sgmii";
-	qcom,id = <1>;
-
-	nvmem-cells = <&macaddr_eeprom_6>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac2 {
-	status = "okay";
-
-	mdiobus = <&mdio0>;
-	phy-handle = <&phy4>;
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_eeprom_0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&tcsr {
-	status = "okay";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
deleted file mode 100644
index 62530efeb1..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
+++ /dev/null
@@ -1,515 +0,0 @@
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "TP-Link Archer VR2600v";
-	compatible = "tplink,vr2600v", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power;
-		led-failsafe = &general;
-		led-running = &power;
-		led-upgrade = &general;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		dect {
-			label = "dect";
-			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_PHONE>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		ledswitch {
-			label = "ledswitch";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_LIGHTS_TOGGLE>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		dsl {
-			label = "white:dsl";
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan {
-			function = LED_FUNCTION_LAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g {
-			label = "white:wlan2g";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g {
-			label = "white:wlan5g";
-			gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		phone {
-			label = "white:phone";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
-		};
-
-		general: general {
-			label = "white:general";
-			gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
-				"gpio26", "gpio53", "gpio56", "gpio66";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "SBL1";
-					reg = <0x0 0x20000>;
-					read-only;
-				};
-
-				partition@20000 {
-					label = "MIBIB";
-					reg = <0x20000 0x20000>;
-					read-only;
-				};
-
-				partition@40000 {
-					label = "SBL2";
-					reg = <0x40000 0x40000>;
-					read-only;
-				};
-
-				partition@80000 {
-					label = "SBL3";
-					reg = <0x80000 0x80000>;
-					read-only;
-				};
-
-				partition@100000 {
-					label = "DDRCONFIG";
-					reg = <0x100000 0x10000>;
-					read-only;
-				};
-
-				partition@110000 {
-					label = "SSD";
-					reg = <0x110000 0x10000>;
-					read-only;
-				};
-
-				partition@120000 {
-					label = "TZ";
-					reg = <0x120000 0x80000>;
-					read-only;
-				};
-
-				partition@1a0000 {
-					label = "RPM";
-					reg = <0x1a0000 0x80000>;
-					read-only;
-				};
-
-				partition@220000 {
-					label = "APPSBL";
-					reg = <0x220000 0x80000>;
-					read-only;
-				};
-
-				partition@2a0000 {
-					label = "APPSBLENV";
-					reg = <0x2a0000 0x40000>;
-					read-only;
-				};
-
-				partition@2e0000 {
-					label = "OLDART";
-					reg = <0x2e0000 0x40000>;
-					read-only;
-				};
-
-				partition@320000 {
-					label = "firmware";
-					reg = <0x320000 0xc60000>;
-					compatible = "openwrt,uimage";
-					openwrt,offset = <512>; /* account for pad-extra 512 */
-				};
-
-				/* hole 0xf80000 - 0xfaf100 */
-
-				partition@faf100 {
-					label = "default-mac";
-					reg = <0xfaf100 0x00200>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_defaultmac_0: macaddr@0 {
-							compatible = "mac-base";
-							reg = <0x0 0x6>;
-							#nvmem-cell-cells = <1>;
-						};
-					};
-				};
-
-				partition@fc0000 {
-					label = "ART";
-					reg = <0xfc0000 0x40000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						precal_ART_1000: precal@1000 {
-							reg = <0x1000 0x2f20>;
-						};
-
-						precal_ART_5000: precal@5000 {
-							reg = <0x5000 0x2f20>;
-						};
-					};
-				};
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_defaultmac_0 1>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_defaultmac_0 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
deleted file mode 100644
index 0afc9219c9..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
+++ /dev/null
@@ -1,552 +0,0 @@
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "NEC Aterm WG2600HP";
-	compatible = "nec,wg2600hp", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-
-		led-boot = &power_green;
-		led-failsafe = &power_red;
-		led-running = &power_green;
-		led-upgrade = &power_green;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		bridge {
-			label = "bridge";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		converter {
-			label = "converter";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		converter_green {
-			label = "green:converter";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_red: power_red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		active_green {
-			label = "green:active";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		active_red {
-			label = "red:active";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
-		};
-
-		converter_red {
-			label = "red:converter";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_green {
-			label = "green:wlan2g";
-			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_red {
-			label = "red:wlan2g";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g_green {
-			label = "green:wlan5g";
-			gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan5g_red {
-			label = "red:wlan5g";
-			gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
-		};
-
-		tv_green {
-			label = "green:tv";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		tv_red {
-			label = "red:tv";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&CPU_SPC {
-	status = "disabled";
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-				qca,sgmii-rxclk-falling-edge;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_PRODUCTDATA_6>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_PRODUCTDATA_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gsbi5 {
-	status = "okay";
-
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				SBL1@0 {
-					label = "SBL1";
-					reg = <0x0 0x20000>;
-					read-only;
-				};
-
-				MIBIB@20000 {
-					label = "MIBIB";
-					reg = <0x20000 0x20000>;
-					read-only;
-				};
-
-				SBL2@40000 {
-					label = "SBL2";
-					reg = <0x40000 0x40000>;
-					read-only;
-				};
-
-				SBL3@80000 {
-					label = "SBL3";
-					reg = <0x80000 0x80000>;
-					read-only;
-				};
-
-				DDRCONFIG@100000 {
-					label = "DDRCONFIG";
-					reg = <0x100000 0x10000>;
-					read-only;
-				};
-
-				SSD@110000 {
-					label = "SSD";
-					reg = <0x110000 0x10000>;
-					read-only;
-				};
-
-				TZ@120000 {
-					label = "TZ";
-					reg = <0x120000 0x80000>;
-					read-only;
-				};
-
-				RPM@1a0000 {
-					label = "RPM";
-					reg = <0x1a0000 0x80000>;
-					read-only;
-				};
-
-				APPSBL@220000 {
-					label = "APPSBL";
-					reg = <0x220000 0x80000>;
-					read-only;
-				};
-
-				APPSBLENV@2a0000 {
-					label = "APPSBLENV";
-					reg = <0x2a0000 0x10000>;
-				};
-
-				PRODUCTDATA: PRODUCTDATA@2b0000 {
-					label = "PRODUCTDATA";
-					reg = <0x2b0000 0x30000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_PRODUCTDATA_0: macaddr@0 {
-							reg = <0x0 0x6>;
-						};
-
-						macaddr_PRODUCTDATA_6: macaddr@6 {
-							reg = <0x6 0x6>;
-						};
-
-						macaddr_PRODUCTDATA_c: macaddr@c {
-							reg = <0xc 0x6>;
-						};
-
-						macaddr_PRODUCTDATA_12: macaddr@12 {
-							reg = <0x12 0x6>;
-						};
-					};
-				};
-
-				ART@2e0000 {
-					label = "ART";
-					reg = <0x2e0000 0x40000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						precal_ART_1000: precal@1000 {
-							reg = <0x1000 0x2f20>;
-						};
-
-						precal_ART_5000: precal@5000 {
-							reg = <0x5000 0x2f20>;
-						};
-					};
-				};
-
-				TP@320000 {
-					label = "TP";
-					reg = <0x320000 0x40000>;
-					read-only;
-				};
-
-				TINY@360000 {
-					label = "TINY";
-					reg = <0x360000 0x500000>;
-					read-only;
-				};
-
-				firmware@860000 {
-					compatible = "denx,uimage";
-					label = "firmware";
-					reg = <0x860000 0x17a0000>;
-				};
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio16", "gpio54", "gpio24", "gpio25";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
-				"gpio15", "gpio55", "gpio56", "gpio57", "gpio58",
-				"gpio64", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	usb_pwr_en_pins: usb_pwr_en_pins {
-		mux {
-			pins = "gpio22";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
deleted file mode 100644
index 0fb7e0531d..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
+++ /dev/null
@@ -1,557 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- *  Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
- *  Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
- *  All rights reserved.
- */
-
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	compatible = "compex,wpq864", "qcom,ipq8064";
-	model = "Compex WPQ864";
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-		ethernet0 = &gmac1;
-		ethernet1 = &gmac0;
-
-		led-boot = &led_pass;
-		led-failsafe = &led_fail;
-		led-running = &led_pass;
-		led-upgrade = &led_pass;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		rss4 {
-			label = "green:rss4";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		rss3 {
-			label = "green:rss3";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		rss2 {
-			label = "orange:rss2";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		rss1 {
-			label = "red:rss1";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_pass: pass {
-			label = "green:pass";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_fail: fail {
-			label = "green:fail";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		usb-pcie {
-			label = "green:usb-pcie";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	beeper {
-		compatible = "gpio-beeper";
-
-		pinctrl-0 = <&beeper_pins>;
-		pinctrl-names = "default";
-
-		gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&rpm {
-	pinctrl-0 = <&rpm_pins>;
-	pinctrl-names = "default";
-};
-
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	mt29f2g08abbeah4@0 {
-		compatible = "qcom,nandcs";
-
-		reg = <0>;
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x0040000 0x0140000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "0:SBL2";
-				reg = <0x0180000 0x0140000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "0:SBL3";
-				reg = <0x02c0000 0x0280000>;
-				read-only;
-			};
-
-			partition@540000 {
-				label = "0:DDRCONFIG";
-				reg = <0x0540000 0x0120000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "0:SSD";
-				reg = <0x0660000 0x0120000>;
-				read-only;
-			};
-
-			partition@780000 {
-				label = "0:TZ";
-				reg = <0x0780000 0x0280000>;
-				read-only;
-			};
-
-			partition@a00000 {
-				label = "0:RPM";
-				reg = <0x0a00000 0x0280000>;
-				read-only;
-			};
-
-			partition@c80000 {
-				label = "0:APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			partition@1180000 {
-				label = "0:APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-			};
-
-			partition@1200000 {
-				label = "0:ART";
-				reg = <0x1200000 0x0140000>;
-			};
-
-			partition@1340000 {
-				label = "ubi";
-				reg = <0x1340000 0x4000000>;
-			};
-
-			partition@5340000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x5340000 0x0060000>;
-			};
-
-			partition@53a0000 {
-				label = "0:SBL2_1";
-				reg = <0x53a0000 0x0140000>;
-				read-only;
-			};
-
-			partition@54e0000 {
-				label = "0:SBL3_1";
-				reg = <0x54e0000 0x0280000>;
-				read-only;
-			};
-
-			partition@5760000 {
-				label = "0:DDRCONFIG_1";
-				reg = <0x5760000 0x0120000>;
-				read-only;
-			};
-
-			partition@5880000 {
-				label = "0:SSD_1";
-				reg = <0x5880000 0x0120000>;
-				read-only;
-			};
-
-			partition@59a0000 {
-				label = "0:TZ_1";
-				reg = <0x59a0000 0x0280000>;
-				read-only;
-			};
-
-			partition@5c20000 {
-				label = "0:RPM_1";
-				reg = <0x5c20000 0x0280000>;
-				read-only;
-			};
-
-			partition@5ea0000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x5ea0000 0x0060000>;
-			};
-
-			partition@5f00000 {
-				label = "0:APPSBL_1";
-				reg = <0x5f00000 0x0500000>;
-				read-only;
-			};
-
-			partition@6400000 {
-				label = "ubi_1";
-				reg = <0x6400000 0x4000000>;
-			};
-
-			partition@a400000 {
-				label = "unused";
-				reg = <0xa400000 0x5c00000>;
-			};
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gsbi4_serial {
-	pinctrl-0 = <&uart0_pins>;
-	pinctrl-names = "default";
-};
-
-&flash {
-	compatible = "jedec,spi-nor";
-};
-
-&sata_phy {
-	status = "disabled";
-};
-
-&sata {
-	status = "disabled";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-
-	rx_eq = <2>;
-	tx_deamp_3_5db = <32>;
-	mpll = <160>;
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-
-	rx_eq = <2>;
-	tx_deamp_3_5db = <32>;
-	mpll = <160>;
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-};
-
-&qcom_pinmux {
-	pinctrl-names = "default";
-	pinctrl-0 = <&state_default>;
-
-	state_default: pinctrl0 {
-		pcie0_pcie2_perst {
-			pins = "gpio3";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio22",
-			       "gpio23", "gpio24", "gpio25", "gpio53";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio54";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	beeper_pins: beeper_pins {
-		mux {
-			pins = "gpio55";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	rpm_pins: rpm_pins {
-		mux {
-			pins = "gpio12", "gpio13";
-			function = "gsbi4";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-
-	uart0_pins: uart0_pins {
-		mux {
-			pins = "gpio10", "gpio11";
-			function = "gsbi4";
-			drive-strength = <10>;
-			bias-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19";
-			function = "gsbi5";
-			drive-strength = <10>;
-			bias-pull-down;
-		};
-
-		clk {
-			pins = "gpio21";
-			function = "gsbi5";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-
-		cs {
-			pins = "gpio20";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-	};
-};
-
-&tcsr {
-	qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
deleted file mode 100644
index 5807425830..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
+++ /dev/null
@@ -1,622 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Buffalo WXR-2533DHP";
-	compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
-
-	memory@42000000 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &diag;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	chosen {
-		/* use "ubi_rootfs" volume in "ubi" partition as rootfs */
-		bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&hub_port0 &hub_port1>;
-		};
-
-		guestport {
-			label = "green:guestport";
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		diag: diag {
-			label = "orange:diag";
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		internet_orange {
-			label = "orange:internet";
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
-		};
-
-		internet_white {
-			label = "white:internet";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wireless_orange {
-			label = "orange:wireless";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		wireless_white {
-			label = "white:wireless";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		router_orange {
-			label = "orange:router";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		router_white {
-			label = "white:router";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		power {
-			label = "power";
-			gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_POWER>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		eject {
-			label = "eject";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_EJECTCD>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		guest {
-			label = "guest";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_0>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		ap {
-			label = "ap";
-			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_1>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		router {
-			label = "router";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_1>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		auto {
-			label = "auto";
-			gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
-			linux,code = <BTN_1>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	cs@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ubi@0 {
-				label = "ubi";
-				reg = <0x0000000 0x4000000>;
-			};
-
-			rootfs_1@4000000 {
-				label = "rootfs_1";
-				reg = <0x4000000 0x4000000>;
-			};
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_ART_6>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-
-	nvmem-cells = <&macaddr_ART_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gsbi4_serial {
-	pinctrl-0 = <&uart0_pins>;
-	pinctrl-names = "default";
-};
-
-&gsbi5 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_SPI>;
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				SBL1@0 {
-					label = "SBL1";
-					reg = <0x0 0x10000>;
-					read-only;
-				};
-
-				MIBIB@10000 {
-					label = "MIBIB";
-					reg = <0x10000 0x20000>;
-					read-only;
-				};
-
-				SBL2@30000 {
-					label = "SBL2";
-					reg = <0x30000 0x30000>;
-					read-only;
-				};
-
-				SBL3@60000 {
-					label = "SBL3";
-					reg = <0x60000 0x30000>;
-					read-only;
-				};
-
-				DDRCONFIG@90000 {
-					label = "DDRCONFIG";
-					reg = <0x90000 0x10000>;
-					read-only;
-				};
-
-				SSD@a0000 {
-					label = "SSD";
-					reg = <0xa0000 0x10000>;
-					read-only;
-				};
-
-				TZ@b0000 {
-					label = "TZ";
-					reg = <0xb0000 0x30000>;
-					read-only;
-				};
-
-				RPM@e0000 {
-					label = "RPM";
-					reg = <0xe0000 0x20000>;
-					read-only;
-				};
-
-				APPSBL@100000 {
-					label = "APPSBL";
-					reg = <0x100000 0x70000>;
-					read-only;
-				};
-
-				APPSBLENV@170000 {
-					label = "APPSBLENV";
-					reg = <0x170000 0x10000>;
-					read-only;
-				};
-
-				ART@180000 {
-					label = "ART";
-					reg = <0x180000 0x40000>;
-					read-only;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_ART_0: macaddr@0 {
-							reg = <0x0 0x6>;
-						};
-
-						macaddr_ART_6: macaddr@6 {
-							reg = <0x6 0x6>;
-						};
-
-						macaddr_ART_18: macaddr@18 {
-							reg = <0x18 0x6>;
-						};
-
-						macaddr_ART_1e: macaddr@1e {
-							reg = <0x1e 0x6>;
-						};
-
-						precal_ART_1000: precal@1000 {
-							reg = <0x1000 0x2f20>;
-						};
-
-						precal_ART_5000: precal@5000 {
-							reg = <0x5000 0x2f20>;
-						};
-					};
-				};
-
-				BOOTCONFIG@1c0000 {
-					label = "BOOTCONFIG";
-					reg = <0x1c0000 0x10000>;
-					read-only;
-				};
-
-				APPSBL_1@1d0000 {
-					label = "APPSBL_1";
-					reg = <0x1d0000 0x70000>;
-					read-only;
-				};
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&dwc3_0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hub_port0: port@1 {
-		reg = <1>;
-		#trigger-source-cells = <0>;
-	};
-};
-
-&dwc3_1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hub_port1: port@1 {
-		reg = <1>;
-		#trigger-source-cells = <0>;
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
-			nvmem-cell-names = "mac-address", "pre-calibration";
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57",
-				"gpio58", "gpio64", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22",
-				"gpio23", "gpio24", "gpio25", "gpio26", "gpio53";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	uart0_pins: uart0_pins {
-		mux {
-			pins = "gpio10", "gpio11";
-			function = "gsbi4";
-			drive-strength = <12>;
-			bias-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs{
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	usb_pwr_en_pins: usb_pwr_en_pins {
-		mux{
-			pins = "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-			output-high;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts
deleted file mode 100644
index 7151f8de52..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-ac400i.dts
+++ /dev/null
@@ -1,318 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Nokia AC400i";
-	compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064";
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-
-		led-boot = &pwr_red;
-		led-failsafe = &pwr_red;
-		led-running = &pwr_green;
-		led-upgrade = &pwr_green;
-	};
-
-	chosen {
-		bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		5g_red {
-			label = "red:5g";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
-		};
-
-		5g_green {
-			label = "green:5g";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		2g_red {
-			label = "red:2g";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-		};
-
-		2g_green {
-			label = "green:2g";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
-		};
-
-		eth1_red {
-			label = "red:eth1";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
-		};
-
-		eth1_green {
-			label = "green:eth1";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
-		};
-
-		eth2_red {
-			label = "red:eth2";
-			gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>;
-		};
-
-		eth2_green {
-			label = "green:eth2";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
-		};
-
-		ctrl_red {
-			label = "red:ctrl";
-			gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
-		};
-
-		ctrl_green {
-			label = "green:ctrl";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
-		};
-
-		pwr_red: pwr_red {
-			label = "red:pwr";
-			gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>;
-		};
-
-		pwr_green: pwr_green {
-			label = "green:pwr";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19";
-			function = "gsbi5";
-			drive-strength = <10>;
-			bias-pull-down;
-		};
-
-		clk {
-			pins = "gpio21";
-			function = "gsbi5";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-
-		cs {
-			pins = "gpio20";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio65", "gpio64",
-				   "gpio53", "gpio54",
-				   "gpio68", "gpio22",
-				   "gpio67", "gpio23",
-				   "gpio55", "gpio56",
-				   "gpio2", "gpio26";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-		spi-max-frequency = <50000000>;
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		m25p80@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "qcom,smem-part";
-			};
-		};
-	};
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-			reg = <0x00000000 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			wifi@1,0 {
-					compatible = "qcom,ath10k";
-					status = "okay";
-					reg = <0x00010000 0 0 0 0>;
-					qcom,ath10k-calibration-variant = "Nokia-AC400i";
-			};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-			reg = <0x00000000 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges;
-
-			wifi@1,0 {
-					compatible = "qcom,ath10k";
-					status = "okay";
-					reg = <0x00010000 0 0 0 0>;
-					qcom,ath10k-calibration-variant = "Nokia-AC400i";
-			};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-
-};
-
-//POE
-&gmac0 {
-	status = "okay";
-	qcom,id = <0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	mdiobus = <&mdio0>;
-	phy-handle = <&phy0>;
-	phy-mode = "rgmii";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-//LAN1
-&gmac1 {
-	status = "okay";
-	qcom,id = <1>;
-
-	mdiobus = <&mdio0>;
-	phy-handle = <&phy1>;
-	phy-mode = "rgmii";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&nand {
-	status = "okay";
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			rootfs@0 {
-				label = "rootfs";
-				reg = <0x0000000 0x4000000>;
-			};
-
-			rootfs_1@4000000 {
-				label = "rootfs_1";
-				reg = <0x4000000 0x4000000>;
-			};
-
-			cfg@8000000 {
-				label = "cfg";
-				reg = <0x8000000 0x8000000>;
-			};
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
deleted file mode 100644
index 7d22b4f541..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
+++ /dev/null
@@ -1,395 +0,0 @@
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "ZyXEL NBG6817";
-	compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		mdio-gpio0 = &mdio0;
-		sdcc1 = &sdcc1;
-
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1";
-		append-rootblock = "root=/dev/mmcblk0p";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			linux,input-type = <EV_SW>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		internet {
-			label = "white:internet";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		wifi2g {
-			label = "amber:wifi2g";
-			gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
-		};
-
-		/* wifi2g amber from the manual is missing */
-
-		wifi5g {
-			label = "amber:wifi5g";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-		};
-
-		/* wifi5g amber from the manual is missing */
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio53", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio9", "gpio26", "gpio33", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	mdio0_pins: mdio0-pins {
-		clk {
-			pins = "gpio1";
-			input-disable;
-		};
-	};
-
-	rgmii2_pins: rgmii2-pins {
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		cs {
-			pins = "gpio20";
-			drive-strength = <12>;
-		};
-	};
-
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio17";
-			function = "gpio";
-			drive-strength = <12>;
-		};
-
-		pwr {
-			pins = "gpio17";
-			bias-pull-down;
-			output-high;
-		};
-
-		ovc {
-			pins = "gpio16";
-			bias-pull-up;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio14", "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-		};
-
-		pwr {
-			pins = "gpio14";
-			bias-pull-down;
-			output-high;
-		};
-
-		ovc {
-			pins = "gpio15";
-			bias-pull-up;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		m25p80@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <51200000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "qcom,smem-part";
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,phy_mdio_addr = <4>;
-	qcom,poll_required = <0>;
-	qcom,rgmii_delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,phy_mdio_addr = <0>;	/* none */
-	qcom,poll_required = <0>;	/* no polling */
-	qcom,rgmii_delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&sdcc1 {
-	status = "okay";
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
deleted file mode 100644
index a7f0b1dbf0..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi
+++ /dev/null
@@ -1,541 +0,0 @@
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	reserved-memory {
-		rsvd@5fe00000 {
-			reg = <0x5fe00000 0x200000>;
-			reusable;
-		};
-
-		ramoops@42100000 {
-			compatible = "ramoops";
-			reg = <0x42100000 0x40000>;
-			record-size = <0x4000>;
-			console-size = <0x4000>;
-			ftrace-size = <0x4000>;
-			pmsg-size = <0x4000>;
-		};
-	};
-
-	aliases {
-		label-mac-device = &gmac2;
-
-		led-boot = &power_white;
-		led-failsafe = &power_amber;
-		led-running = &power_white;
-		led-upgrade = &power_amber;
-
-		mdio-gpio0 = &mdio0;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		wifi {
-			label = "wifi";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds: leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		power_white: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
-			default-state = "keep";
-		};
-
-		power_amber: power_amber {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_white {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		wan_amber {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		wifi {
-			label = "white:wifi";
-			gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54", "gpio65";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8", "gpio9",
-				"gpio22", "gpio23", "gpio24",
-				"gpio26", "gpio53", "gpio64";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	mdio0_pins: mdio0-pins {
-		clk {
-			pins = "gpio1";
-			input-disable;
-		};
-	};
-
-	rgmii2_pins: rgmii2-pins {
-		tx {
-			pins = "gpio27", "gpio28", "gpio29",
-				"gpio30", "gpio31", "gpio32";
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19", "gpio21";
-			function = "gsbi5";
-			bias-pull-down;
-		};
-
-		data {
-			pins = "gpio18", "gpio19";
-			drive-strength = <10>;
-		};
-
-		cs {
-			pins = "gpio20";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio21";
-			drive-strength = <12>;
-		};
-	};
-
-	spi6_pins: spi6_pins {
-		mux {
-			pins = "gpio55", "gpio56", "gpio58";
-			function = "gsbi6";
-			bias-pull-down;
-		};
-
-		mosi {
-			pins = "gpio55";
-			drive-strength = <12>;
-		};
-
-		miso {
-			pins = "gpio56";
-			drive-strength = <14>;
-		};
-
-		cs {
-			pins = "gpio57";
-			drive-strength = <12>;
-			bias-pull-up;
-		};
-
-		clk {
-			pins = "gpio58";
-			drive-strength = <12>;
-		};
-
-		reset {
-			pins = "gpio33";
-			drive-strength = <10>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb0_pwr_en_pins: usb0_pwr_en_pins {
-		mux {
-			pins = "gpio15";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	usb1_pwr_en_pins: usb1_pwr_en_pins {
-		mux {
-			pins = "gpio16", "gpio68";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x1180000>;
-
-		partitions: partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "qcadata";
-				reg = <0x0000000 0x0c80000>;
-				read-only;
-			};
-
-			partition@c80000 {
-				label = "APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			partition@1180000 {
-				label = "APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-				read-only;
-			};
-
-			art: partition@1200000 {
-				label = "art";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_art_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_art_6: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-
-					macaddr_art_c: macaddr@c {
-						reg = <0xc 0x6>;
-					};
-
-					precal_art_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_art_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@1340000 {
-				label = "artbak";
-				reg = <0x1340000 0x0140000>;
-				read-only;
-			};
-
-			partition@1480000 {
-				label = "kernel";
-				reg = <0x1480000 0x0400000>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac2>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac1 {
-	status = "okay";
-
-	phy-mode = "rgmii";
-	qcom,id = <1>;
-	qcom,phy_mdio_addr = <4>;
-	qcom,poll_required = <0>;
-	qcom,rgmii_delay = <1>;
-	qcom,phy_mii_type = <0>;
-	qcom,emulation = <0>;
-	qcom,irq = <255>;
-	mdiobus = <&mdio0>;
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	nvmem-cells = <&macaddr_art_6 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	phy-mode = "sgmii";
-	qcom,id = <2>;
-	qcom,phy_mdio_addr = <0>;	/* none */
-	qcom,poll_required = <0>;	/* no polling */
-	qcom,rgmii_delay = <0>;
-	qcom,phy_mii_type = <1>;
-	qcom,emulation = <0>;
-	qcom,irq = <258>;
-	mdiobus = <&mdio0>;
-
-	nvmem-cells = <&macaddr_art_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&sata_phy {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-
-	pinctrl-0 = <&usb0_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-
-	pinctrl-0 = <&usb1_pwr_en_pins>;
-	pinctrl-names = "default";
-};
-
-&pcie0 {
-	status = "okay";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi0: wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi1: wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
deleted file mode 100644
index 3440c52699..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
+++ /dev/null
@@ -1,46 +0,0 @@
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
-	model = "Netgear Nighthawk X4S R7800";
-	compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
-};
-
-&leds {
-	usb1 {
-		label = "white:usb1";
-		gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-	};
-
-	usb2 {
-		label = "white:usb2";
-		gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	esata {
-		label = "white:esata";
-		gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&partitions {
-	partition@1880000 {
-		label = "ubi";
-		reg = <0x1880000 0x6080000>;
-	};
-
-	partition@7900000 {
-		label = "reserve";
-		reg = <0x7900000 0x0700000>;
-		read-only;
-	};
-};
-
-&wifi0 {
-	nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
-	nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
deleted file mode 100644
index 12f15bd147..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
+++ /dev/null
@@ -1,601 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Askey RT4230W REV6";
-	compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x3e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		led-boot = &ledctrl3;
-		led-failsafe = &ledctrl1;
-		led-running = &ledctrl2;
-		led-upgrade = &ledctrl3;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		ledctrl1: ledctrl1 {
-			label = "ledctrl1";
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
-		};
-
-		ledctrl2: ledctrl2 {
-			label = "ledctrl2";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		ledctrl3: ledctrl3 {
-			label = "ledctrl3";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio54", "gpio68";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio22", "gpio23", "gpio24";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	rgmii2_pins: rgmii2-pins {
-		mux {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
-				"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
-			function = "rgmii2";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		cs {
-			pins = "gpio20";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "everspin,mr25h256";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <40000000>;
-			reg = <0>;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x0040000 0x0140000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "0:SBL2";
-				reg = <0x0180000 0x0140000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "0:SBL3";
-				reg = <0x02c0000 0x0280000>;
-				read-only;
-			};
-
-			partition@540000 {
-				label = "0:DDRCONFIG";
-				reg = <0x0540000 0x0120000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "0:SSD";
-				reg = <0x0660000 0x0120000>;
-				read-only;
-			};
-
-			partition@780000 {
-				label = "0:TZ";
-				reg = <0x0780000 0x0280000>;
-				read-only;
-			};
-
-			partition@a00000 {
-				label = "0:RPM";
-				reg = <0x0a00000 0x0280000>;
-				read-only;
-			};
-
-			partition@c80000 {
-				label = "0:APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-
-			partition@1180000 {
-				label = "0:APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-			};
-
-			partition@1200000 {
-				label = "0:ART";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_ART_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_ART_6: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-
-					precal_ART_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-
-					precal_ART_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-
-			partition@1340000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x1340000 0x0060000>;
-				read-only;
-			};
-
-			partition@13a0000 {
-				label = "0:SBL2_1";
-				reg = <0x13a0000 0x0140000>;
-				read-only;
-			};
-
-			partition@14e0000 {
-				label = "0:SBL3_1";
-				reg = <0x14e0000 0x0280000>;
-				read-only;
-			};
-
-			partition@1760000 {
-				label = "0:DDRCONFIG_1";
-				reg = <0x1760000 0x0120000>;
-				read-only;
-			};
-
-			partition@1880000 {
-				label = "0:SSD_1";
-				reg = <0x1880000 0x0120000>;
-				read-only;
-			};
-
-			partition@19a0000 {
-				label = "0:TZ_1";
-				reg = <0x19a0000 0x0280000>;
-				read-only;
-			};
-
-			partition@1c20000 {
-				label = "0:RPM_1";
-				reg = <0x1c20000 0x0280000>;
-				read-only;
-			};
-
-			partition@1ea0000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x1ea0000 0x0060000>;
-				read-only;
-			};
-
-			partition@1f00000 {
-				label = "0:APPSBL_1";
-				reg = <0x1f00000 0x0500000>;
-				read-only;
-			};
-
-			partition@2400000 {
-				label = "ubi";
-				reg = <0x2400000 0x1a000000>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac0>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_WAN;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_AMBER>;
-						function = LED_FUNCTION_WAN;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_AMBER>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_AMBER>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_AMBER>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@5 {
-				reg = <5>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port5>;
-
-				leds {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					led@0 {
-						reg = <0>;
-						color = <LED_COLOR_ID_GREEN>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-
-					led@1 {
-						reg = <1>;
-						color = <LED_COLOR_ID_AMBER>;
-						function = LED_FUNCTION_LAN;
-						default-state = "keep";
-					};
-				};
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-
-			phy_port5: phy@4 {
-				reg = <4>;
-			};
-		};
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-
-	nvmem-cells = <&macaddr_ART_0>;
-	nvmem-cell-names = "mac-address";
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <1>;
-
-	nvmem-cells = <&macaddr_ART_6>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi0: wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&precal_ART_1000>;
-			nvmem-cell-names = "pre-calibration";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi1: wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&precal_ART_5000>;
-			nvmem-cell-names = "pre-calibration";
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
deleted file mode 100644
index 8818e95e8d..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
+++ /dev/null
@@ -1,524 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Arris TR4400 v2";
-	compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x42000000 0x1e000000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		led-boot = &led_status_blue;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_blue;
-		led-upgrade = &led_status_red;
-	};
-
-	chosen {
-		bootargs = "rootfstype=squashfs noinitrd";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_status_red: status_red {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_status_blue: status_blue {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&qcom_pinmux {
-	button_pins: button_pins {
-		mux {
-			pins = "gpio6", "gpio54";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio7", "gpio8";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-		};
-	};
-
-	rgmii2_pins: rgmii2-pins {
-		tx {
-			pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
-			input-disable;
-		};
-	};
-
-	spi_pins: spi_pins {
-		cs {
-			pins = "gpio20";
-			drive-strength = <12>;
-		};
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi@1a280000 {
-		status = "okay";
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "everspin,mr25h256";
-			spi-max-frequency = <40000000>;
-			reg = <0>;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		compatible = "qcom,nandcs";
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "0:SBL1";
-				reg = <0x0000000 0x0040000>;
-				read-only;
-			};
-			partition@40000 {
-				label = "0:MIBIB";
-				reg = <0x0040000 0x0140000>;
-				read-only;
-			};
-			partition@180000 {
-				label = "0:SBL2";
-				reg = <0x0180000 0x0140000>;
-				read-only;
-			};
-			partition@2c0000 {
-				label = "0:SBL3";
-				reg = <0x02c0000 0x0280000>;
-				read-only;
-			};
-			partition@540000 {
-				label = "0:DDRCONFIG";
-				reg = <0x0540000 0x0120000>;
-				read-only;
-			};
-			partition@660000 {
-				label = "0:SSD";
-				reg = <0x0660000 0x0120000>;
-				read-only;
-			};
-			partition@780000 {
-				label = "0:TZ";
-				reg = <0x0780000 0x0280000>;
-				read-only;
-			};
-			partition@a00000 {
-				label = "0:RPM";
-				reg = <0x0a00000 0x0280000>;
-				read-only;
-			};
-			partition@c80000 {
-				label = "0:APPSBL";
-				reg = <0x0c80000 0x0500000>;
-				read-only;
-			};
-			partition@1180000 {
-				label = "0:APPSBLENV";
-				reg = <0x1180000 0x0080000>;
-			};
-			partition@1200000 {
-				label = "0:ART";
-				reg = <0x1200000 0x0140000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					precal_ART_1000: precal@1000 {
-						reg = <0x1000 0x2f20>;
-					};
-					precal_ART_5000: precal@5000 {
-						reg = <0x5000 0x2f20>;
-					};
-				};
-			};
-			stock_partition@1340000 {
-				label = "stock_rootfs";
-				reg = <0x1340000 0x4000000>;
-
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "extra";
-					reg = <0x0 0x4000000>;
-				};
-			};
-			partition@5340000 {
-				label = "0:BOOTCONFIG";
-				reg = <0x5340000 0x0060000>;
-				read-only;
-			};
-			partition@53a0000 {
-				label = "0:SBL2_1";
-				reg = <0x53a0000 0x0140000>;
-				read-only;
-			};
-			partition@54e0000 {
-				label = "0:SBL3_1";
-				reg = <0x54e0000 0x0280000>;
-				read-only;
-			};
-			partition@5760000 {
-				label = "0:DDRCONFIG_1";
-				reg = <0x5760000 0x0120000>;
-				read-only;
-			};
-			partition@5880000 {
-				label = "0:SSD_1";
-				reg = <0x5880000 0x0120000>;
-				read-only;
-			};
-			partition@59a0000 {
-				label = "0:TZ_1";
-				reg = <0x59a0000 0x0280000>;
-				read-only;
-			};
-			partition@5c20000 {
-				label = "0:RPM_1";
-				reg = <0x5c20000 0x0280000>;
-				read-only;
-			};
-			partition@5ea0000 {
-				label = "0:BOOTCONFIG1";
-				reg = <0x5ea0000 0x0060000>;
-				read-only;
-			};
-			partition@5f00000 {
-				label = "0:APPSBL_1";
-				reg = <0x5f00000 0x0500000>;
-				read-only;
-			};
-			stock_partition@6400000 {
-				label = "stock_rootfs_1";
-				reg = <0x6400000 0x4000000>;
-
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					label = "fw_env";
-					reg = <0x0 0x100000>;
-
-					nvmem-layout {
-						compatible = "fixed-layout";
-						#address-cells = <1>;
-						#size-cells = <1>;
-
-						macaddr_fw_env_0: macaddr@0 {
-							reg = <0x00 0x6>;
-						};
-						macaddr_fw_env_6: macaddr@6 {
-							reg = <0x06 0x6>;
-						};
-						macaddr_fw_env_c: macaddr@c {
-							reg = <0x0c 0x6>;
-						};
-						macaddr_fw_env_12: macaddr@12 {
-							reg = <0x12 0x6>;
-						};
-						macaddr_fw_env_18: macaddr@18 {
-							reg = <0x18 0x6>;
-						};
-					};
-				};
-
-				partition@100000 {
-					label = "ubi";
-					reg = <0x100000 0x9b00000>;
-				};
-			};
-			stock_partition@a400000 {
-				label = "stock_fw_env";
-				reg = <0xa400000 0x0100000>;
-			};
-			stock_partition@a500000 {
-				label = "stock_config";
-				reg = <0xa500000 0x0800000>;
-			};
-			stock_partition@ad00000 {
-				label = "stock_PKI";
-				reg = <0xad00000 0x0200000>;
-			};
-			stock_partition@af00000 {
-				label = "stock_scfgmgr";
-				reg = <0xaf00000 0x0100000>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	switch@10 {
-		compatible = "qca,qca8337";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x10>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&gmac0>;
-				phy-mode = "rgmii";
-				tx-internal-delay-ps = <1000>;
-				rx-internal-delay-ps = <1000>;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan1";
-				phy-mode = "internal";
-				phy-handle = <&phy_port1>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan2";
-				phy-mode = "internal";
-				phy-handle = <&phy_port2>;
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan3";
-				phy-mode = "internal";
-				phy-handle = <&phy_port3>;
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan4";
-				phy-mode = "internal";
-				phy-handle = <&phy_port4>;
-			};
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&gmac1>;
-				phy-mode = "sgmii";
-				qca,sgmii-enable-pll;
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			phy_port1: phy@0 {
-				reg = <0>;
-			};
-
-			phy_port2: phy@1 {
-				reg = <1>;
-			};
-
-			phy_port3: phy@2 {
-				reg = <2>;
-			};
-
-			phy_port4: phy@3 {
-				reg = <3>;
-			};
-		};
-	};
-
-	phy7: ethernet-phy@7 {
-		reg = <7>;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-	qcom,id = <0>;
-
-	nvmem-cells = <&macaddr_fw_env_18>;
-	nvmem-cell-names = "mac-address";
-
-	pinctrl-0 = <&rgmii2_pins>;
-	pinctrl-names = "default";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac1 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <1>;
-
-	nvmem-cells = <&macaddr_fw_env_0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac3 {
-	status = "okay";
-	phy-mode = "sgmii";
-	qcom,id = <3>;
-	phy-handle = <&phy7>;
-
-	nvmem-cells = <&macaddr_fw_env_6>;
-	nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie0 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-names = "default";
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi0: wifi@1,0 {
-			compatible = "pci168c,0046";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
-			nvmem-cell-names = "pre-calibration", "mac-address";
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-	reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
-	pinctrl-0 = <&pcie1_pins>;
-	pinctrl-names = "default";
-	max-link-speed = <1>;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi1: wifi@1,0 {
-			compatible = "pci168c,0040";
-			reg = <0x00010000 0 0 0 0>;
-
-			nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
-			nvmem-cell-names = "pre-calibration", "mac-address";
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts
deleted file mode 100644
index 1d4e9d36fe..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr450.dts
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
-	model = "Netgear Nighthawk XR450";
-	compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
-	usb1 {
-		label = "white:usb1";
-		gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	usb2 {
-		label = "white:usb2";
-		gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&partitions {
-	partition@1880000 {
-		label = "ubi";
-		reg = <0x1880000 0xce00000>;
-	};
-
-	partition@e680000 {
-		label = "reserve";
-		reg = <0xe680000 0x0780000>;
-		read-only;
-	};
-};
-
-&wifi0 {
-	nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
-	nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
deleted file mode 100644
index 9eef59eaf3..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
-	model = "Netgear Nighthawk XR500";
-	compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
-	usb1 {
-		label = "white:usb1";
-		gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
-	};
-
-	usb2 {
-		label = "white:usb2";
-		gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&partitions {
-	partition@1880000 {
-		label = "ubi";
-		reg = <0x1880000 0xce00000>;
-	};
-
-	partition@e680000 {
-		label = "reserve";
-		reg = <0xe680000 0x0780000>;
-		read-only;
-	};
-};
-
-&wifi0 {
-	nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
-	nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
-	nvmem-cell-names = "mac-address", "pre-calibration";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts
deleted file mode 100644
index 0c865ef7c7..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ap3935.dts
+++ /dev/null
@@ -1,358 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Extreme Networks AP3935";
-	compatible = "extreme,ap3935", "qcom,ipq8064";
-
-	memory@0 {
-		reg = <0x41400000 0x3ec00000>;
-		device_type = "memory";
-	};
-
-	aliases {
-		serial0 = &gsbi7_serial;
-		serial1 = &gsbi2_serial;
-		mdio-gpio0 = &mdio0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac2;
-
-		led-boot = &led_power_green;
-		led-failsafe = &led_power_orange;
-		led-running = &led_power_green;
-		led-upgrade = &led_power_green;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs-override = "ubi.block=0,0 root=/dev/ubiblock0_0";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
-		};
-
-		led_power_orange: power_orange { 
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
-		};
-
-		led_wlan2g_green {
-			label = "green:wlan2g";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led_wlan5g_green {
-			label = "green:wlan5g";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led_lan1_green {
-			label = "green:lan1";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		led_lan1_orange {
-			label = "orange:lan1";
-			gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
-		};
-
-		led_lan2_green {
-			label = "green:lan2";
-			gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
-		};
-
-		led_lan2_orange {
-			label = "orange:lan2";
-			gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-
-&qcom_pinmux {
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19";
-			function = "gsbi5";
-			drive-strength = <10>;
-			bias-pull-down;
-		};
-
-		clk {
-			pins = "gpio21";
-			function = "gsbi5";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-
-		cs {
-			pins = "gpio20";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio22", "gpio23", "gpio24", "gpio25",
-				    "gpio26", "gpio27", "gpio28", "gpio29";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio56";
-			function = "gpio";
-			bias-pull-up;
-		};
-	};
-};
-
-&gsbi2 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-	status = "okay";
-
-	gsbi2_serial: serial@12490000 {
-		status = "okay";
-	};
-};
-
-&gsbi4 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-	status = "okay";
-
-	serial@16340000 {
-		status = "disabled";
-	};
-};
-
-&gsbi7 {
-	qcom,mode = <GSBI_PROT_I2C_UART>;
-	status = "okay";
-
-	gsbi7_serial: serial@16640000 {
-		status = "okay";
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-		spi-max-frequency = <50000000>;
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		flash@0 {
-			compatible = "jedec,spi-nor";
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				cfg1@2a0000 {
-					compatible = "u-boot,env-redundant-bool";
-					label = "CFG1";
-					reg = <0x2a0000 0x0010000>;
-
-					ethaddr: ethaddr {
-						#nvmem-cell-cells = <1>;
-					};
-				};
-
-				bootpri@2b0000 {
-					label = "BootPRI";
-					reg = <0x2b0000 0x0080000>;
-				};
-
-				cfg2@330000 {
-					label = "CFG2";
-					reg = <0x330000 0x0010000>;
-				};
-
-				fs@340000 {
-					label = "FS";
-					reg = <0x340000 0x0080000>;
-				};
-
-				priimg@3c0000 {
-					label = "PriImg";
-					reg = <0x3c0000 0x0e10000>;
-				};
-
-				secimg@11d0000 {
-					label = "SecImg";
-					reg = <0x11d0000 0x0e10000>;
-				};
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	pinctrl-0 = <&nand_pins>;
-	pinctrl-names = "default";
-
-	nand@0 {
-		compatible = "qcom,nandcs";
-
-		reg = <0>;
-
-		nand-ecc-strength = <8>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			
-			ubi@0 {
-				label = "ubi";
-				reg = <0x0000000 0x20000000>;
-			};
-		};
-	};
-};
-
-&soc {
-	mdio1: mdio {
-		compatible = "virtual,mdio-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		status = "okay";
-
-		pinctrl-0 = <&mdio0_pins>;
-		pinctrl-names = "default";
-
-		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
-		phy1: ethernet-phy@1 {
-			reg = <1>;
-		};
-
-		phy2: ethernet-phy@2 {
-			reg = <2>;
-		};
-	};
-};
-
-&gmac0 {
-	status = "okay";
-
-	qcom,id = <0>;
-	mdiobus = <&mdio1>;
-
-	phy-mode = "rgmii";
-	phy-handle = <&phy1>;
-
-	nvmem-cells = <&ethaddr 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	qcom,id = <2>;
-	mdiobus = <&mdio1>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy2>;
-
-	nvmem-cells = <&ethaddr 1>;
-	nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
deleted file mode 100644
index a8f43591f9..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-/ {
-	memory {
-		device_type = "memory";
-		linux,usable-memory = <0x41500000 0x1ea00000>;
-		reg = <0x40000000 0x20000000>;
-	};
-
-	cpus {
-		idle-states {
-			CPU_SPC: spc {
-				status = "disabled";
-			};
-		};
-	};
-
-	chosen {
-		bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
-	};
-};
-
-&qcom_pinmux {
-	mdio0_pins_active: mdio0_pins_active {
-		mux {
-			pins = "gpio0", "gpio1";
-			function = "mdio";
-			drive-strength = <2>;
-			bias-pull-down;
-			output-low;
-		};
-
-		clk {
-			pins = "gpio1";
-			input-disable;
-		};
-	};
-
-	phy_active: phy_active {
-		phy {
-			pins = "gpio6", "gpio7";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-down;
-			output-high;
-		};
-	};
-
-	uart1_pins: uart1_pins {
-		mux {
-			pins = "gpio51", "gpio52";
-			function = "gsbi1";
-			drive-strength = <4>;
-			bias-disable;
-		};
-	};
-};
-
-&gsbi1 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_UART_W_FC>;
-
-	serial@12450000 {
-		status = "okay";
-
-		pinctrl-0 = <&uart1_pins>;
-		pinctrl-names = "default";
-	};
-};
-
-&pcie0 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-		reg = <0x0 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi0: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x10000 0 0 0 0>;
-		};
-	};
-};
-
-&pcie1 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-		reg = <0x0 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi1: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x10000 0 0 0 0>;
-		};
-	};
-};
-
-&pcie2 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-		reg = <0x0 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi2: wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x10000 0 0 0 0>;
-		};
-	};
-};
-
-&adm_dma {
-	status = "okay";
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		compatible = "qcom,nandcs";
-
-		reg = <0>;
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		nand-is-boot-medium;
-		qcom,boot-partitions = <0x0 0x2140000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "sbl1";
-				reg = <0x0 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "mibib";
-				reg = <0x40000 0x140000>;
-				read-only;
-			};
-
-			partition@180000 {
-				label = "sbl2";
-				reg = <0x180000 0x140000>;
-				read-only;
-			};
-
-			partition@2c0000 {
-				label = "sbl3";
-				reg = <0x2c0000 0x280000>;
-				read-only;
-			};
-
-			partition@540000 {
-				label = "ddrconfig";
-				reg = <0x540000 0x120000>;
-				read-only;
-			};
-
-			partition@660000 {
-				label = "ssd";
-				reg = <0x660000 0x120000>;
-				read-only;
-			};
-
-			partition@780000 {
-				label = "tz";
-				reg = <0x780000 0x280000>;
-				read-only;
-			};
-
-			partition@a00000 {
-				label = "rpm";
-				reg = <0xa00000 0x280000>;
-				read-only;
-			};
-
-			partition@1fc0000 {
-				label = "u-boot";
-				reg = <0x1fc0000 0x180000>;
-				read-only;
-			};
-
-			partition@21c0000 {
-				label = "bootkernel1";
-				reg = <0x21c0000 0xa80000>;
-			};
-
-			partition@2c40000 {
-				label = "bootkernel2";
-				reg = <0x2c40000 0xa80000>;
-			};
-
-			partition@36c0000 {
-				label = "ubi";
-				reg = <0x36c0000 0x46c0000>;
-			};
-
-			partition@7d80000 {
-				label = "art";
-				reg = <0x7d80000 0x200000>;
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
deleted file mode 100644
index 9f6c5fb696..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
+++ /dev/null
@@ -1,332 +0,0 @@
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "Edgecore ECW5410";
-	compatible = "edgecore,ecw5410", "qcom,ipq8064";
-
-	reserved-memory {
-		nss@40000000 {
-			reg = <0x40000000 0x1000000>;
-			no-map;
-		};
-
-		smem: smem@41000000 {
-			reg = <0x41000000 0x200000>;
-			no-map;
-		};
-
-		wifi_dump@44000000 {
-			reg = <0x44000000 0x600000>;
-			no-map;
-		};
-	};
-
-	cpus {
-		idle-states {
-			CPU_SPC: spc {
-				status = "disabled";
-			};
-		};
-	};
-
-	aliases {
-		serial1 = &gsbi1_serial;
-		ethernet0 = &gmac2;
-		ethernet1 = &gmac3;
-
-		led-boot = &led_power_green;
-		led-failsafe = &led_power_red;
-		led-running = &led_power_green;
-		led-upgrade = &led_power_green;
-	};
-
-	chosen {
-		bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1";
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power_green: power_green {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
-		};
-
-		wlan2g_green {
-			label = "green:wlan2g";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan2g_yellow {
-			label = "yellow:wlan2g";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan5g_green {
-			label = "green:wlan5g";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		led_power_red: power_red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
-		};
-
-		wlan5g_yellow {
-			label = "yellow:wlan5g";
-			gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-
-&qcom_pinmux {
-	spi_pins: spi_pins {
-		mux {
-			pins = "gpio18", "gpio19";
-			function = "gsbi5";
-			drive-strength = <10>;
-			bias-pull-down;
-		};
-
-		clk {
-			pins = "gpio21";
-			function = "gsbi5";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-
-		cs {
-			pins = "gpio20";
-			function = "gpio";
-			drive-strength = <10>;
-			bias-pull-up;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio16", "gpio23", "gpio24", "gpio26",
-				   "gpio28", "gpio59";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio25";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	uart1_pins: uart1_pins {
-		mux {
-			pins = "gpio51", "gpio52", "gpio53", "gpio54";
-			function = "gsbi1";
-			drive-strength = <12>;
-			bias-none;
-		};
-	};
-};
-
-&gsbi1 {
-	qcom,mode = <GSBI_PROT_UART_W_FC>;
-	status = "okay";
-
-	serial@12450000 {
-		status = "okay";
-
-		pinctrl-0 = <&uart1_pins>;
-		pinctrl-names = "default";
-	};
-};
-
-&gsbi5 {
-	qcom,mode = <GSBI_PROT_SPI>;
-	status = "okay";
-
-	spi4: spi@1a280000 {
-		status = "okay";
-		spi-max-frequency = <50000000>;
-
-		pinctrl-0 = <&spi_pins>;
-		pinctrl-names = "default";
-
-		cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
-		m25p80@0 {
-			compatible = "jedec,spi-nor";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			spi-max-frequency = <50000000>;
-			reg = <0>;
-
-			partitions {
-				compatible = "qcom,smem-part";
-			};
-		};
-	};
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
-		};
-	};
-};
-
-&pcie2 {
-	status = "okay";
-
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
-	bridge@0,0 {
-		reg = <0x00000000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		wifi@1,0 {
-			compatible = "qcom,ath10k";
-			status = "okay";
-			reg = <0x00010000 0 0 0 0>;
-			qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	nand@0 {
-		compatible = "qcom,nandcs";
-
-		reg = <0>;
-
-		nand-ecc-strength = <4>;
-		nand-bus-width = <8>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			rootfs1@0 {
-				label = "rootfs1";
-				reg = <0x0000000 0x4000000>;
-			};
-
-			rootfs2@4000000 {
-				label = "rootfs2";
-				reg = <0x4000000 0x4000000>;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	qcom,id = <2>;
-	mdiobus = <&mdio0>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
-};
-
-&gmac3 {
-	status = "okay";
-
-	qcom,id = <3>;
-	mdiobus = <&mdio0>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
-};
-
-&adm_dma {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
deleted file mode 100644
index 7ec11de56b..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr42.dts
+++ /dev/null
@@ -1,233 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Meraki MR42";
-	compatible = "meraki,mr42", "qcom,ipq8064";
-
-	aliases {
-		serial1 = &gsbi1_serial;
-		ethernet0 = &gmac3;
-
-		led-boot = &led_active;
-		led-failsafe = &led_power;
-		led-running = &led_active;
-		led-upgrade = &led_active;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_active: active {
-			label = "white:active";
-			gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&gmac3 {
-	status = "okay";
-
-	qcom,id = <3>;
-	mdiobus = <&mdio0>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy2>;
-
-	nvmem-cells = <&mac_address 0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gsbi2 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi2_i2c {
-	status = "okay";
-
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-
-	ina2xx@40 {
-		compatible = "ina219";
-		shunt-resistor = <40000>;
-		reg = <0x40>;
-	};
-
-	eeprom@56 {
-		compatible = "atmel,24c64";
-		pagesize = <32>;
-		reg = <0x56>;
-		read-only;
-
-		nvmem-layout {
-			compatible = "fixed-layout";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			mac_address: mac-address@66 {
-				compatible = "mac-base";
-				reg = <0x66 0x6>;
-				#nvmem-cell-cells = <1>;
-			};
-		};
-	};
-};
-
-&gsbi6 {
-	qcom,mode = <GSBI_PROT_I2C>;
-	status = "okay";
-};
-
-&gsbi6_i2c {
-	status = "okay";
-
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-names = "default";
-
-	tlc591xx@40 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "ti,tlc59108";
-		reg = <0x40>;
-
-		red@0 {
-			label = "red:user";
-			reg = <0x0>;
-		};
-
-		green@1 {
-			label = "green:user";
-			reg = <0x1>;
-		};
-
-		blue@2 {
-			label = "blue:user";
-			reg = <0x2>;
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
-	pinctrl-names = "default";
-
-	phy2: ethernet-phy2 {
-		reg = <2>;
-
-		reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <24000>;
-
-		eee-broken-100tx;
-		eee-broken-1000t;
-	};
-};
-
-&qcom_pinmux {
-	i2c0_pins: i2c0_pins {
-		mux {
-			pins = "gpio24", "gpio25";
-			function = "gsbi2";
-			drive-strength = <2>;
-			bias-pull-up;
-			input;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio26";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-		};
-	};
-
-	i2c1_pins: i2c1_pins {
-		mux {
-			pins = "gpio29", "gpio30";
-			function = "gsbi6";
-			drive-strength = <2>;
-			bias-pull-up;
-			input;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio31", "gpio32";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-low;
-		};
-	};
-};
-
-&wifi0 {
-	nvmem-cells = <&mac_address 1>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
-	nvmem-cells = <&mac_address 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
-	nvmem-cells = <&mac_address 3>;
-	nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
deleted file mode 100644
index 7512bfb74f..0000000000
--- a/target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8068-mr52.dts
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Meraki MR52";
-	compatible = "meraki,mr52", "qcom,ipq8064";
-
-	aliases {
-		serial1 = &gsbi1_serial;
-		mdio-gpio0 = &mdio_gpio0;
-		ethernet0 = &gmac2;
-		ethernet1 = &gmac3;
-
-		led-boot = &led_active;
-		led-failsafe = &led_power;
-		led-running = &led_active;
-		led-upgrade = &led_active;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-			debounce-interval = <60>;
-			wakeup-source;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&led_pins>;
-		pinctrl-names = "default";
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan2_green {
-			label = "green:lan2";
-			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan1_green {
-			label = "green:lan1";
-			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_active: active {
-			label = "white:active";
-			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
-		};
-
-		lan2_orange {
-			label = "orange:lan2";
-			gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan1_orange {
-			label = "orange:lan1";
-			gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&gmac2 {
-	status = "okay";
-
-	qcom,id = <2>;
-	mdiobus = <&mdio0>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
-
-	nvmem-cells = <&mac_address 0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac3 {
-	status = "okay";
-
-	qcom,id = <3>;
-	mdiobus = <&mdio_gpio0>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy4>;
-
-	nvmem-cells = <&mac_address 1>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gsbi7 {
-	status = "okay";
-	qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi7_i2c {
-	status = "okay";
-
-	pinctrl-0 = <&i2c_pins>;
-	pinctrl-names = "default";
-
-	ina2xx@45 {
-		compatible = "ina219";
-		shunt-resistor = <80000>;
-		reg = <0x45>;
-	};
-
-	tlc591xx@49 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "ti,tlc59108";
-		reg = <0x49>;
-
-		red@0 {
-			label = "red:user";
-			reg = <0x0>;
-		};
-
-		green@1 {
-			label = "green:user";
-			reg = <0x1>;
-		};
-
-		blue@2 {
-			label = "blue:user";
-			reg = <0x2>;
-		};
-	};
-
-	eeprom@52 {
-		compatible = "atmel,24c64";
-		pagesize = <32>;
-		reg = <0x52>;
-		read-only;
-
-		nvmem-layout {
-			compatible = "fixed-layout";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			mac_address: mac-address@66 {
-				compatible = "mac-base";
-				reg = <0x66 0x6>;
-				#nvmem-cell-cells = <1>;
-			};
-		};
-	};
-};
-
-&qcom_pinmux {
-	i2c_pins: i2c_pins {
-		mux {
-			pins = "gpio8", "gpio9";
-			function = "gsbi7";
-			drive-strength = <2>;
-			bias-pull-up;
-			input;
-		};
-	};
-
-	led_pins: led_pins {
-		mux {
-			pins = "gpio19", "gpio26";
-			function = "gpio";
-			drive-strength = <12>;
-			bias-pull-down;
-			output-low;
-		};
-	};
-
-	button_pins: button_pins {
-		mux {
-			pins = "gpio25";
-			function = "gpio";
-			drive-strength = <2>;
-			bias-pull-up;
-			input;
-		};
-	};
-};
-
-&soc {
-	mdio_gpio0: mdio {
-		compatible = "virtual,mdio-gpio";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		status = "okay";
-
-		pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
-		pinctrl-names = "default";
-
-		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH
-			 &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
-		phy0: ethernet-phy0 {
-			reg = <0>;
-			reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <24000>;
-		};
-
-		phy4: ethernet-phy4 {
-			reg = <4>;
-			reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <24000>;
-		};
-	};
-};
-
-&wifi0 {
-	nvmem-cells = <&mac_address 4>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
-	nvmem-cells = <&mac_address 3>;
-	nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
-	nvmem-cells = <&mac_address 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
-	status = "okay";
-};
-
-&ss_phy_0 {
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-};
-
-&hs_phy_1 {
-	status = "okay";
-};
-
-&ss_phy_1 {
-	status = "okay";
-};
-
-&usb3_1 {
-	status = "okay";
-};
diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts
index 12f15bd147..f10fa367f1 100644
--- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts
+++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-rt4230w-rev6.dts
@@ -14,10 +14,10 @@
 	};
 
 	aliases {
-		led-boot = &ledctrl3;
+		led-boot = &ledctrl1;
 		led-failsafe = &ledctrl1;
-		led-running = &ledctrl2;
-		led-upgrade = &ledctrl3;
+		led-running = &ledctrl3;
+		led-upgrade = &ledctrl1;
 	};
 
 	chosen {
@@ -55,6 +55,7 @@
 		ledctrl2: ledctrl2 {
 			label = "ledctrl2";
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
 		};
 
 		ledctrl3: ledctrl3 {
diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi
index a8f43591f9..2e71575331 100644
--- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi
+++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-cryptid-common.dtsi
@@ -73,10 +73,6 @@
 &pcie0 {
 	status = "okay";
 
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
 	bridge@0,0 {
 		reg = <0x0 0 0 0 0>;
 		#address-cells = <3>;
@@ -94,10 +90,6 @@
 &pcie1 {
 	status = "okay";
 
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
 	bridge@0,0 {
 		reg = <0x0 0 0 0 0>;
 		#address-cells = <3>;
@@ -115,10 +107,6 @@
 &pcie2 {
 	status = "okay";
 
-	/delete-property/ pinctrl-0;
-	/delete-property/ pinctrl-names;
-	/delete-property/ perst-gpios;
-
 	bridge@0,0 {
 		reg = <0x0 0 0 0 0>;
 		#address-cells = <3>;
diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts
index 7512bfb74f..0d3230e6de 100644
--- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts
+++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts
@@ -46,13 +46,13 @@
 			gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
 		};
 
-		lan2_green {
-			label = "green:lan2";
+		lan1_green {
+			label = "green:lan1";
 			gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
 		};
 
-		lan1_green {
-			label = "green:lan1";
+		lan2_green {
+			label = "green:lan2";
 			gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
 		};
 
@@ -61,13 +61,13 @@
 			gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
 		};
 
-		lan2_orange {
-			label = "orange:lan2";
+		lan1_orange {
+			label = "orange:lan1";
 			gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
 		};
 
-		lan1_orange {
-			label = "orange:lan1";
+		lan2_orange {
+			label = "orange:lan2";
 			gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
 		};
 	};
diff --git a/target/linux/ipq806x/image/Makefile b/target/linux/ipq806x/image/Makefile
index c6be9371e3..b616fecfbb 100644
--- a/target/linux/ipq806x/image/Makefile
+++ b/target/linux/ipq806x/image/Makefile
@@ -6,7 +6,7 @@ include $(INCLUDE_DIR)/image.mk
 define Device/Default
 	PROFILES := Default
 	KERNEL_LOADADDR = 0x42208000
-	DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+	DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
 	DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
 	DEVICE_DTS_CONFIG := config@1
 	IMAGES := sysupgrade.bin
diff --git a/target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch
deleted file mode 100644
index 9395f1b241..0000000000
--- a/target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:17:34 +0100
-Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider
-
-krait-cc use this driver for the secondary mux. Register it as a clk
-provider to correctly use this clk in other drivers.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/kpss-xcc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/kpss-xcc.c
-+++ b/drivers/clk/qcom/kpss-xcc.c
-@@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
- 
- static int kpss_xcc_driver_probe(struct platform_device *pdev)
- {
-+	struct device *dev = &pdev->dev;
- 	const struct of_device_id *id;
- 	void __iomem *base;
- 	struct clk_hw *hw;
- 	const char *name;
- 
--	id = of_match_device(kpss_xcc_match_table, &pdev->dev);
-+	id = of_match_device(kpss_xcc_match_table, dev);
- 	if (!id)
- 		return -ENODEV;
- 
-@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct
- 		return PTR_ERR(base);
- 
- 	if (id->data) {
--		if (of_property_read_string_index(pdev->dev.of_node,
-+		if (of_property_read_string_index(dev->of_node,
- 						  "clock-output-names",
- 						  0, &name))
- 			return -ENODEV;
-@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct
- 		base += 0x28;
- 	}
- 
--	hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
-+	hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
- 							ARRAY_SIZE(aux_parents), 0,
- 							base, 0, 0x3,
- 							0, aux_parent_map, NULL);
-+	if (IS_ERR(hw))
-+		return PTR_ERR(hw);
- 
--	return PTR_ERR_OR_ZERO(hw);
-+	of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
-+
-+	return 0;
- }
- 
- static struct platform_driver kpss_xcc_driver = {
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch
deleted file mode 100644
index 65c1fc17f2..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:58:27 +0100
-Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier
- register
-
-Use devm variant for clk notifier register and correctly handle free
-resource on driver remove.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -62,7 +62,7 @@ static int krait_notifier_register(struc
- 	int ret = 0;
- 
- 	mux->clk_nb.notifier_call = krait_notifier_cb;
--	ret = clk_notifier_register(clk, &mux->clk_nb);
-+	ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
- 	if (ret)
- 		dev_err(dev, "failed to register clock notifier: %d\n", ret);
- 
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch
deleted file mode 100644
index 2dcb69399c..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:27 +0100
-Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary
- mux
-
-The secondary mux parent order is swapped.
-This currently doesn't cause problems as the secondary mux is used for idle
-clk and as a safe clk source while reprogramming the hfpll.
-
-Each mux have 2 or more output but he always have a safe source to
-switch while reprogramming the connected pll. We use a clk notifier to
-switch to the correct parent before clk core can apply the correct rate.
-The parent to switch is hardcoded in the mux struct.
-
-For the secondary mux the safe source to use is the qsb parent as it's
-the only fixed clk as the acpus_aux is a pll that can source from pxo or
-from pll8.
-
-The hardcoded safe parent for the secondary mux is set to index 0 that
-in the secondary mux map is set to 2.
-
-But the index 0 is actually acpu_aux in the parent list.
-
-Fix the swapped parents to correctly handle idle frequency and output a
-sane clk_summary report.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in
- 	int ret;
- 	struct krait_mux_clk *mux;
- 	static const char *sec_mux_list[] = {
--		"acpu_aux",
- 		"qsb",
-+		"acpu_aux",
- 	};
- 	struct clk_init_data init = {
- 		.parent_names = sec_mux_list,
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch
deleted file mode 100644
index 6261a940d7..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:28 +0100
-Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div
- clk
-
-clk-krait ignore any rate change if clk is not flagged as enabled.
-Correctly enable the secondary mux and div clk to correctly change rate
-instead of silently ignoring the request.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id
- 	};
- 	const char *p_names[1];
- 	struct clk *clk;
-+	int cpu;
- 
- 	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- 	if (!div)
-@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id
- 	}
- 
- 	clk = devm_clk_register(dev, &div->hw);
-+	if (IS_ERR(clk))
-+		goto err;
-+
-+	/* clk-krait ignore any rate change if mux is not flagged as enabled */
-+	if (id < 0)
-+		for_each_online_cpu(cpu)
-+			clk_prepare_enable(div->hw.clk);
-+	else
-+		clk_prepare_enable(div->hw.clk);
-+
-+err:
- 	kfree(p_names[0]);
- 	kfree(init.name);
- 
-@@ -113,7 +125,7 @@ static int
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- 		  unsigned int offset, bool unique_aux)
- {
--	int ret;
-+	int cpu, ret;
- 	struct krait_mux_clk *mux;
- 	static const char *sec_mux_list[] = {
- 		"qsb",
-@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in
- 	if (ret)
- 		goto unique_aux;
- 
-+	/* clk-krait ignore any rate change if mux is not flagged as enabled */
-+	if (id < 0)
-+		for_each_online_cpu(cpu)
-+			clk_prepare_enable(mux->hw.clk);
-+	else
-+		clk_prepare_enable(mux->hw.clk);
-+
- unique_aux:
- 	if (unique_aux)
- 		kfree(sec_mux_list[0]);
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch
deleted file mode 100644
index fabb299f42..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:29 +0100
-Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of
- acpu_aux
-
-Some bootloader may leave the system in an even more undefined state
-with the secondary mux of L2 or other cores sourcing out of the acpu_aux
-parent. This results in the clk set to the PXO rate or a PLL8 rate.
-
-The current logic to reset the mux and set them to a defined state only
-handle if the mux are configured to source out of QSB. Change this and
-force a new and defined state if the current clk is lower than the aux
-rate. This way we can handle any wrong configuration where the mux is
-sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1),
-PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz).
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor
- 	 */
- 	cur_rate = clk_get_rate(l2_pri_mux_clk);
- 	aux_rate = 384000000;
--	if (cur_rate == 1) {
--		pr_info("L2 @ QSB rate. Forcing new rate.\n");
-+	if (cur_rate < aux_rate) {
-+		pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- 		cur_rate = aux_rate;
- 	}
- 	clk_set_rate(l2_pri_mux_clk, aux_rate);
-@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor
- 	for_each_possible_cpu(cpu) {
- 		clk = clks[cpu];
- 		cur_rate = clk_get_rate(clk);
--		if (cur_rate == 1) {
--			pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
-+		if (cur_rate < aux_rate) {
-+			pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- 			cur_rate = aux_rate;
- 		}
- 
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch
deleted file mode 100644
index 049b1fa49f..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:30 +0100
-Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register
-
-clk_register is now deprecated. Convert the driver to devm_clk_hw_register.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------
- 1 file changed, 19 insertions(+), 12 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
- 	const char *p_names[1];
--	struct clk *clk;
--	int cpu;
-+	int cpu, ret;
- 
- 	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- 	if (!div)
-@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id
- 		return -ENOMEM;
- 	}
- 
--	clk = devm_clk_register(dev, &div->hw);
--	if (IS_ERR(clk))
-+	ret = devm_clk_hw_register(dev, &div->hw);
-+	if (ret)
- 		goto err;
- 
- 	/* clk-krait ignore any rate change if mux is not flagged as enabled */
-@@ -118,7 +117,7 @@ err:
- 	kfree(p_names[0]);
- 	kfree(init.name);
- 
--	return PTR_ERR_OR_ZERO(clk);
-+	return ret;
- }
- 
- static int
-@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in
- 		.ops = &krait_mux_clk_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
--	struct clk *clk;
- 
- 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- 	if (!mux)
-@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in
- 	if (unique_aux) {
- 		sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
- 		if (!sec_mux_list[0]) {
--			clk = ERR_PTR(-ENOMEM);
-+			ret = -ENOMEM;
- 			goto err_aux;
- 		}
- 	}
- 
--	clk = devm_clk_register(dev, &mux->hw);
-+	ret = devm_clk_hw_register(dev, &mux->hw);
-+	if (ret)
-+		goto unique_aux;
- 
--	ret = krait_notifier_register(dev, clk, mux);
-+	ret = krait_notifier_register(dev, mux->hw.clk, mux);
- 	if (ret)
- 		goto unique_aux;
- 
-@@ -189,7 +189,7 @@ unique_aux:
- 		kfree(sec_mux_list[0]);
- err_aux:
- 	kfree(init.name);
--	return PTR_ERR_OR_ZERO(clk);
-+	return ret;
- }
- 
- static struct clk *
-@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in
- 		goto err_p2;
- 	}
- 
--	clk = devm_clk_register(dev, &mux->hw);
-+	ret = devm_clk_hw_register(dev, &mux->hw);
-+	if (ret) {
-+		clk = ERR_PTR(ret);
-+		goto err_p3;
-+	}
-+
-+	clk = mux->hw.clk;
- 
- 	ret = krait_notifier_register(dev, clk, mux);
- 	if (ret)
--		goto err_p3;
-+		clk = ERR_PTR(ret);
-+
- err_p3:
- 	kfree(p_names[2]);
- err_p2:
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch
deleted file mode 100644
index 453a37dfc0..0000000000
--- a/target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch
+++ /dev/null
@@ -1,414 +0,0 @@
-From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:31 +0100
-Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API
-
-Modernize the krait-cc driver to parent-data API and refactor to drop
-any use of parent_names. From Documentation all the required clocks should
-be declared in DTS so fw_name can be correctly used to get the parents
-for all the muxes. .name is also declared to save compatibility with old
-DT.
-
-While at it also drop some hardcoded index and introduce an enum to make
-index values more clear.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++----------------
- 1 file changed, 112 insertions(+), 90 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -15,6 +15,16 @@
- 
- #include "clk-krait.h"
- 
-+enum {
-+	cpu0_mux = 0,
-+	cpu1_mux,
-+	cpu2_mux,
-+	cpu3_mux,
-+	l2_mux,
-+
-+	clks_max,
-+};
-+
- static unsigned int sec_mux_map[] = {
- 	2,
- 	0,
-@@ -69,21 +79,23 @@ static int krait_notifier_register(struc
- 	return ret;
- }
- 
--static int
-+static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
- 	struct krait_div2_clk *div;
-+	static struct clk_parent_data p_data[1];
- 	struct clk_init_data init = {
--		.num_parents = 1,
-+		.num_parents = ARRAY_SIZE(p_data),
- 		.ops = &krait_div2_clk_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
--	const char *p_names[1];
-+	struct clk_hw *clk;
-+	char *parent_name;
- 	int cpu, ret;
- 
- 	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- 	if (!div)
--		return -ENOMEM;
-+		return ERR_PTR(-ENOMEM);
- 
- 	div->width = 2;
- 	div->shift = 6;
-@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id
- 
- 	init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
- 	if (!init.name)
--		return -ENOMEM;
-+		return ERR_PTR(-ENOMEM);
- 
--	init.parent_names = p_names;
--	p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
--	if (!p_names[0]) {
--		kfree(init.name);
--		return -ENOMEM;
-+	init.parent_data = p_data;
-+	parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+	if (!parent_name) {
-+		clk = ERR_PTR(-ENOMEM);
-+		goto err_parent_name;
- 	}
- 
-+	p_data[0].fw_name = parent_name;
-+	p_data[0].name = parent_name;
-+
- 	ret = devm_clk_hw_register(dev, &div->hw);
--	if (ret)
--		goto err;
-+	if (ret) {
-+		clk = ERR_PTR(ret);
-+		goto err_clk;
-+	}
-+
-+	clk = &div->hw;
- 
- 	/* clk-krait ignore any rate change if mux is not flagged as enabled */
- 	if (id < 0)
-@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id
- 	else
- 		clk_prepare_enable(div->hw.clk);
- 
--err:
--	kfree(p_names[0]);
-+err_clk:
-+	kfree(parent_name);
-+err_parent_name:
- 	kfree(init.name);
- 
--	return ret;
-+	return clk;
- }
- 
--static int
-+static struct clk_hw *
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- 		  unsigned int offset, bool unique_aux)
- {
- 	int cpu, ret;
- 	struct krait_mux_clk *mux;
--	static const char *sec_mux_list[] = {
--		"qsb",
--		"acpu_aux",
-+	static struct clk_parent_data sec_mux_list[2] = {
-+		{ .name = "qsb", .fw_name = "qsb" },
-+		{},
- 	};
- 	struct clk_init_data init = {
--		.parent_names = sec_mux_list,
-+		.parent_data = sec_mux_list,
- 		.num_parents = ARRAY_SIZE(sec_mux_list),
- 		.ops = &krait_mux_clk_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
-+	struct clk_hw *clk;
-+	char *parent_name;
- 
- 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- 	if (!mux)
--		return -ENOMEM;
-+		return ERR_PTR(-ENOMEM);
- 
- 	mux->offset = offset;
- 	mux->lpl = id >= 0;
-@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in
- 
- 	init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
- 	if (!init.name)
--		return -ENOMEM;
-+		return ERR_PTR(-ENOMEM);
- 
- 	if (unique_aux) {
--		sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
--		if (!sec_mux_list[0]) {
--			ret = -ENOMEM;
-+		parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-+		if (!parent_name) {
-+			clk = ERR_PTR(-ENOMEM);
- 			goto err_aux;
- 		}
-+		sec_mux_list[1].fw_name = parent_name;
-+		sec_mux_list[1].name = parent_name;
-+	} else {
-+		sec_mux_list[1].name = "apu_aux";
- 	}
- 
- 	ret = devm_clk_hw_register(dev, &mux->hw);
--	if (ret)
--		goto unique_aux;
-+	if (ret) {
-+		clk = ERR_PTR(ret);
-+		goto err_clk;
-+	}
-+
-+	clk = &mux->hw;
- 
- 	ret = krait_notifier_register(dev, mux->hw.clk, mux);
--	if (ret)
--		goto unique_aux;
-+	if (ret) {
-+		clk = ERR_PTR(ret);
-+		goto err_clk;
-+	}
- 
- 	/* clk-krait ignore any rate change if mux is not flagged as enabled */
- 	if (id < 0)
-@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in
- 	else
- 		clk_prepare_enable(mux->hw.clk);
- 
--unique_aux:
-+err_clk:
- 	if (unique_aux)
--		kfree(sec_mux_list[0]);
-+		kfree(parent_name);
- err_aux:
- 	kfree(init.name);
--	return ret;
-+	return clk;
- }
- 
--static struct clk *
--krait_add_pri_mux(struct device *dev, int id, const char *s,
--		  unsigned int offset)
-+static struct clk_hw *
-+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
-+		  int id, const char *s, unsigned int offset)
- {
- 	int ret;
- 	struct krait_mux_clk *mux;
--	const char *p_names[3];
-+	static struct clk_parent_data p_data[3];
- 	struct clk_init_data init = {
--		.parent_names = p_names,
--		.num_parents = ARRAY_SIZE(p_names),
-+		.parent_data = p_data,
-+		.num_parents = ARRAY_SIZE(p_data),
- 		.ops = &krait_mux_clk_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
--	struct clk *clk;
-+	struct clk_hw *clk;
-+	char *hfpll_name;
- 
- 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- 	if (!mux)
-@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in
- 	if (!init.name)
- 		return ERR_PTR(-ENOMEM);
- 
--	p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
--	if (!p_names[0]) {
-+	hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+	if (!hfpll_name) {
- 		clk = ERR_PTR(-ENOMEM);
--		goto err_p0;
-+		goto err_hfpll;
- 	}
- 
--	p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
--	if (!p_names[1]) {
--		clk = ERR_PTR(-ENOMEM);
--		goto err_p1;
--	}
-+	p_data[0].fw_name = hfpll_name;
-+	p_data[0].name = hfpll_name;
- 
--	p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
--	if (!p_names[2]) {
--		clk = ERR_PTR(-ENOMEM);
--		goto err_p2;
--	}
-+	p_data[1].hw = hfpll_div;
-+	p_data[2].hw = sec_mux;
- 
- 	ret = devm_clk_hw_register(dev, &mux->hw);
- 	if (ret) {
- 		clk = ERR_PTR(ret);
--		goto err_p3;
-+		goto err_clk;
- 	}
- 
--	clk = mux->hw.clk;
-+	clk = &mux->hw;
- 
--	ret = krait_notifier_register(dev, clk, mux);
-+	ret = krait_notifier_register(dev, mux->hw.clk, mux);
- 	if (ret)
- 		clk = ERR_PTR(ret);
- 
--err_p3:
--	kfree(p_names[2]);
--err_p2:
--	kfree(p_names[1]);
--err_p1:
--	kfree(p_names[0]);
--err_p0:
-+err_clk:
-+	kfree(hfpll_name);
-+err_hfpll:
- 	kfree(init.name);
- 	return clk;
- }
- 
- /* id < 0 for L2, otherwise id == physical CPU number */
--static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
-+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
- {
--	int ret;
-+	struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
- 	unsigned int offset;
- 	void *p = NULL;
- 	const char *s;
--	struct clk *clk;
- 
- 	if (id >= 0) {
- 		offset = 0x4501 + (0x1000 * id);
-@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct
- 		s = "_l2";
- 	}
- 
--	ret = krait_add_div(dev, id, s, offset);
--	if (ret) {
--		clk = ERR_PTR(ret);
-+	hfpll_div = krait_add_div(dev, id, s, offset);
-+	if (IS_ERR(hfpll_div)) {
-+		pri_mux = hfpll_div;
- 		goto err;
- 	}
- 
--	ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
--	if (ret) {
--		clk = ERR_PTR(ret);
-+	sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-+	if (IS_ERR(sec_mux)) {
-+		pri_mux = sec_mux;
- 		goto err;
- 	}
- 
--	clk = krait_add_pri_mux(dev, id, s, offset);
-+	pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
-+
- err:
- 	kfree(p);
--	return clk;
-+	return pri_mux;
- }
- 
- static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o
- 	unsigned int idx = clkspec->args[0];
- 	struct clk **clks = data;
- 
--	if (idx >= 5) {
-+	if (idx >= clks_max) {
- 		pr_err("%s: invalid clock index %d\n", __func__, idx);
- 		return ERR_PTR(-EINVAL);
- 	}
-@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor
- 	const struct of_device_id *id;
- 	unsigned long cur_rate, aux_rate;
- 	int cpu;
--	struct clk *clk;
--	struct clk **clks;
--	struct clk *l2_pri_mux_clk;
-+	struct clk_hw *mux, *l2_pri_mux;
-+	struct clk *clk, **clks;
- 
- 	id = of_match_device(krait_cc_match_table, dev);
- 	if (!id)
-@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor
- 	}
- 
- 	/* Krait configurations have at most 4 CPUs and one L2 */
--	clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
-+	clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
- 	if (!clks)
- 		return -ENOMEM;
- 
- 	for_each_possible_cpu(cpu) {
--		clk = krait_add_clks(dev, cpu, id->data);
-+		mux = krait_add_clks(dev, cpu, id->data);
- 		if (IS_ERR(clk))
- 			return PTR_ERR(clk);
--		clks[cpu] = clk;
-+		clks[cpu] = mux->clk;
- 	}
- 
--	l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
--	if (IS_ERR(l2_pri_mux_clk))
--		return PTR_ERR(l2_pri_mux_clk);
--	clks[4] = l2_pri_mux_clk;
-+	l2_pri_mux = krait_add_clks(dev, -1, id->data);
-+	if (IS_ERR(l2_pri_mux))
-+		return PTR_ERR(l2_pri_mux);
-+	clks[l2_mux] = l2_pri_mux->clk;
- 
- 	/*
- 	 * We don't want the CPU or L2 clocks to be turned off at late init
-@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor
- 	 * they take over.
- 	 */
- 	for_each_online_cpu(cpu) {
--		clk_prepare_enable(l2_pri_mux_clk);
-+		clk_prepare_enable(clks[l2_mux]);
- 		WARN(clk_prepare_enable(clks[cpu]),
- 		     "Unable to turn on CPU%d clock", cpu);
- 	}
-@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor
- 	 * two different rates to force a HFPLL reinit under all
- 	 * circumstances.
- 	 */
--	cur_rate = clk_get_rate(l2_pri_mux_clk);
-+	cur_rate = clk_get_rate(clks[l2_mux]);
- 	aux_rate = 384000000;
- 	if (cur_rate < aux_rate) {
- 		pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- 		cur_rate = aux_rate;
- 	}
--	clk_set_rate(l2_pri_mux_clk, aux_rate);
--	clk_set_rate(l2_pri_mux_clk, 2);
--	clk_set_rate(l2_pri_mux_clk, cur_rate);
--	pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
-+	clk_set_rate(clks[l2_mux], aux_rate);
-+	clk_set_rate(clks[l2_mux], 2);
-+	clk_set_rate(clks[l2_mux], cur_rate);
-+	pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- 	for_each_possible_cpu(cpu) {
- 		clk = clks[cpu];
- 		cur_rate = clk_get_rate(clk);
diff --git a/target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch
deleted file mode 100644
index 7e65f4cdff..0000000000
--- a/target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 25 Oct 2022 01:38:17 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1
-
-It was reported non working mmc with this option enabled.
-Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't
-be run at 1.8v.
-Disable it to restore correct functionality of this SoC feature.
-
-Tested-by: Hendrik Koerner <koerhen@web.de>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -756,7 +756,6 @@
- 				non-removable;
- 				cap-sd-highspeed;
- 				cap-mmc-highspeed;
--				mmc-ddr-1_8v;
- 				vmmc-supply = <&vsdcc_fixed>;
- 				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- 				dma-names = "tx", "rx";
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch
deleted file mode 100644
index 76df0f5681..0000000000
--- a/target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From de48d8766afcd97d147699aaff78a338081c9973 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:55 +0200
-Subject: [PATCH 1/3] thermal/drivers/qcom/tsens: Init debugfs only with
- successful probe
-
-Calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
-double or a wrong init of the debugfs information. Init debugfs only
-with successful probe fixing warning about directory already present.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
-Link: https://lore.kernel.org/r/20221022125657.22530-2-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
- 	if (tsens_version(priv) >= VER_0_1)
- 		tsens_enable_irq(priv);
- 
--	tsens_debug_init(op);
--
- err_put_device:
- 	put_device(&op->dev);
- 	return ret;
-@@ -1156,7 +1154,11 @@ static int tsens_probe(struct platform_d
- 		}
- 	}
- 
--	return tsens_register(priv);
-+	ret = tsens_register(priv);
-+	if (!ret)
-+		tsens_debug_init(pdev);
-+
-+	return ret;
- }
- 
- static int tsens_remove(struct platform_device *pdev)
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch
deleted file mode 100644
index 10f1e36b58..0000000000
--- a/target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From c7e077e921fa94e0c06c8d14af6c0504c8a5f4bd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:56 +0200
-Subject: [PATCH 2/3] thermal/drivers/qcom/tsens: Fix wrong version id
- dbg_version_show
-
-For VER_0 the version was incorrectly reported as 0.1.0.
-
-Fix that and correctly report the major version for this old tsens
-revision.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-3-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
- 			return ret;
- 		seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
- 	} else {
--		seq_puts(s, "0.1.0\n");
-+		seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
- 	}
- 
- 	return 0;
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch
deleted file mode 100644
index 63cce7974b..0000000000
--- a/target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 89992d95ed1046338c7866ef7bbe6de543a2af91 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:57 +0200
-Subject: [PATCH 3/3] thermal/drivers/qcom/tsens: Rework debugfs file structure
-
-The current tsens debugfs structure is composed by:
-- a tsens dir in debugfs with a version file
-- a directory for each tsens istance with sensors file to dump all the
-  sensors value.
-
-This works on the assumption that we have the same version for each
-istance but this assumption seems fragile and with more than one tsens
-istance results in the version file not tracking each of them.
-
-A better approach is to just create a subdirectory for each tsens
-istance and put there version and sensors debugfs file.
-
-Using this new implementation results in less code since debugfs entry
-are created only on successful tsens probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-4-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 13 +++----------
- 1 file changed, 3 insertions(+), 10 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -704,21 +704,14 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
- static void tsens_debug_init(struct platform_device *pdev)
- {
- 	struct tsens_priv *priv = platform_get_drvdata(pdev);
--	struct dentry *root, *file;
- 
--	root = debugfs_lookup("tsens", NULL);
--	if (!root)
-+	priv->debug_root = debugfs_lookup("tsens", NULL);
-+	if (!priv->debug_root)
- 		priv->debug_root = debugfs_create_dir("tsens", NULL);
--	else
--		priv->debug_root = root;
--
--	file = debugfs_lookup("version", priv->debug_root);
--	if (!file)
--		debugfs_create_file("version", 0444, priv->debug_root,
--				    pdev, &dbg_version_fops);
- 
- 	/* A directory for each instance of the TSENS IP */
- 	priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
-+	debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
- 	debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
- }
- #else
diff --git a/target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
deleted file mode 100644
index e0c195f1ab..0000000000
--- a/target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 09:31:44 +0100
-Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/mtd/mtdpart.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti
- 
- 	/* allocate the partition structure */
- 	child = kzalloc(sizeof(*child), GFP_KERNEL);
--	name = kstrdup(part->name, GFP_KERNEL);
-+	/* "rootfs" conflicts with OpenWrt auto mounting */
-+	if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs"))
-+		name = "ubi";
-+	else
-+		name = kstrdup(part->name, GFP_KERNEL);
- 	if (!name || !child) {
- 		printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
- 		       parent->name);
diff --git a/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
deleted file mode 100644
index 0a594b2688..0000000000
--- a/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 17 Jan 2022 23:39:34 +0100
-Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
- ipq8064
-
-Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
-Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
-for the secondary mux.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -301,6 +301,12 @@
- 	};
- 
- 	clocks {
-+		qsb: qsb {
-+			compatible = "fixed-clock";
-+			clock-frequency = <225000000>;
-+			#clock-cells = <0>;
-+		};
-+
- 		cxo_board: cxo_board {
- 			compatible = "fixed-clock";
- 			#clock-cells = <0>;
-@@ -575,15 +581,30 @@
- 			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- 			clock-names = "pll8_vote", "pxo";
- 			clock-output-names = "acpu_l2_aux";
-+			#clock-cells = <0>;
-+		};
-+
-+		kraitcc: clock-controller {
-+			compatible = "qcom,krait-cc-v1";
-+			clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
-+				 <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
-+			clock-names = "hfpll0", "hfpll1", "hfpll_l2",
-+				      "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
-+				      "qsb", "pxo";
-+			#clock-cells = <1>;
- 		};
- 
- 		acc0: clock-controller@2088000 {
- 			compatible = "qcom,kpss-acc-v1";
- 			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-+			clock-output-names = "acpu0_aux";
-+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+			clock-names = "pll8_vote", "pxo";
-+			#clock-cells = <0>;
- 		};
- 
- 		saw0: regulator@2089000 {
--			compatible = "qcom,saw2";
-+			compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- 			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- 			regulator;
- 		};
-@@ -591,14 +612,24 @@
- 		acc1: clock-controller@2098000 {
- 			compatible = "qcom,kpss-acc-v1";
- 			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-+			clock-output-names = "acpu1_aux";
-+			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+			clock-names = "pll8_vote", "pxo";
-+			#clock-cells = <0>;
- 		};
- 
- 		saw1: regulator@2099000 {
--			compatible = "qcom,saw2";
-+			compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- 			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- 			regulator;
- 		};
- 
-+		saw_l2: regulator@02012000 {
-+			compatible = "qcom,saw2", "syscon";
-+			reg = <0x02012000 0x1000>;
-+			regulator;
-+		};
-+
- 		nss_common: syscon@03000000 {
- 			compatible = "syscon";
- 			reg = <0x03000000 0x0000FFFF>;
diff --git a/target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch
deleted file mode 100644
index 16e924b303..0000000000
--- a/target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch
+++ /dev/null
@@ -1,268 +0,0 @@
-From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:03:47 +0100
-Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
- ipq8064
-
-Add opp table for cpu and l2 cache. While the current cpufreq is
-the generic one that doesn't scale the L2 cache, we add the l2
-cache opp anyway for the sake of completeness. This will be handy in the
-future when a dedicated cpufreq driver is introduced for krait cores
-that will correctly scale l2 cache with the core freq.
-
-Opp-level is set based on the logic of
-0: idle level
-1: normal level
-2: turbo level
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
- 1 file changed, 99 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -48,6 +48,105 @@
- 		};
- 	};
- 
-+	opp_table_l2: opp_table_l2 {
-+		compatible = "operating-points-v2";
-+
-+		opp-384000000 {
-+			opp-hz = /bits/ 64 <384000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <0>;
-+		};
-+
-+		opp-1000000000 {
-+			opp-hz = /bits/ 64 <1000000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <1150000>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
-+		};
-+	};
-+
-+	opp_table0: opp_table0 {
-+		compatible = "operating-points-v2-kryo-cpu";
-+		nvmem-cells = <&speedbin_efuse>;
-+
-+		/*
-+		 * Voltage thresholds are <target min max>
-+		 */
-+		opp-384000000 {
-+			opp-hz = /bits/ 64 <384000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+			opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
-+			opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
-+			opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <0>;
-+		};
-+
-+		opp-600000000 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+			opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+			opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+			opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-800000000 {
-+			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+			opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
-+			opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1000000000 {
-+			opp-hz = /bits/ 64 <1000000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+			opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+			opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+			opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <1>;
-+		};
-+
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
-+			opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
-+			opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
-+			opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
-+		};
-+
-+		opp-1400000000 {
-+			opp-hz = /bits/ 64 <1400000000>;
-+			opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
-+			opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
-+			opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+			opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <100000>;
-+			opp-level = <2>;
-+		};
-+	};
-+
- 	thermal-zones {
- 		sensor0-thermal {
- 			polling-delay-passive = <0>;
---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
-@@ -6,3 +6,92 @@
- 	model = "Qualcomm Technologies, Inc. IPQ8065";
- 	compatible = "qcom,ipq8065", "qcom,ipq8064";
- };
-+
-+&opp_table_l2 {
-+	/delete-node/opp-1200000000;
-+
-+	opp-1400000000 {
-+		opp-hz = /bits/ 64 <1400000000>;
-+		opp-microvolt = <1150000>;
-+		clock-latency-ns = <100000>;
-+		opp-level = <2>;
-+	};
-+};
-+
-+&opp_table0 {
-+	/*
-+	 * On ipq8065 1.2 ghz freq is not present
-+	 * Remove it to make cpufreq work and not
-+	 * complain for missing definition
-+	 */
-+
-+	/delete-node/opp-1200000000;
-+
-+	/*
-+	 * Voltage thresholds are <target min max>
-+	 */
-+	opp-384000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
-+		opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
-+		opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+		opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+		opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
-+		opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
-+		opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
-+	};
-+
-+	opp-600000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+		opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+		opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
-+		opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
-+		opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
-+		opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
-+		opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
-+	};
-+
-+	opp-800000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+		opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+		opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
-+		opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
-+		opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
-+		opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
-+		opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
-+	};
-+
-+	opp-1000000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+		opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+		opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
-+		opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
-+		opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
-+		opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
-+		opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
-+	};
-+
-+	opp-1400000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
-+		opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
-+		opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+		opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
-+		opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
-+		opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
-+		opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
-+		opp-level = <1>;
-+	};
-+
-+	opp-1725000000 {
-+		opp-hz = /bits/ 64 <1725000000>;
-+		opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
-+		opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
-+		opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
-+		opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
-+		opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
-+		opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
-+		opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
-+		opp-supported-hw = <0x1>;
-+		clock-latency-ns = <100000>;
-+		opp-level = <2>;
-+	};
-+};
---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
-@@ -6,3 +6,39 @@
- 	model = "Qualcomm Technologies, Inc. IPQ8062";
- 	compatible = "qcom,ipq8062", "qcom,ipq8064";
- };
-+
-+&opp_table0 {
-+	/delete-node/opp-1200000000;
-+	/delete-node/opp-1400000000;
-+
-+	/*
-+	 * Voltage thresholds are <target min max>
-+	 */
-+	opp-384000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+		opp-microvolt-speed0-pvs1-v0 = < 925000 878750  971250>;
-+		opp-microvolt-speed0-pvs2-v0 = < 875000 831250  918750>;
-+		opp-microvolt-speed0-pvs3-v0 = < 800000 760000  840000>;
-+	};
-+
-+	opp-600000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+		opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
-+		opp-microvolt-speed0-pvs2-v0 = < 925000 878750  971250>;
-+		opp-microvolt-speed0-pvs3-v0 = < 850000 807500  892500>;
-+	};
-+
-+	opp-800000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+		opp-microvolt-speed0-pvs1-v0 = <1025000  973750 1076250>;
-+		opp-microvolt-speed0-pvs2-v0 = < 995000  945250 1044750>;
-+		opp-microvolt-speed0-pvs3-v0 = < 900000  855000  945000>;
-+	};
-+
-+	opp-1000000000 {
-+		opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+		opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+		opp-microvolt-speed0-pvs2-v0 = <1025000  973750 1076250>;
-+		opp-microvolt-speed0-pvs3-v0 = < 950000  902500  997500>;
-+	};
-+};
diff --git a/target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch
deleted file mode 100644
index cf27aaa08b..0000000000
--- a/target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch
+++ /dev/null
@@ -1,153 +0,0 @@
-From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:07:57 +0100
-Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
- and l2 for ipq8064
-
-Add multiple binding for cpu node, l2 node and add idle-states
-definition for ipq8064 dtsi.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -30,6 +30,15 @@
- 			next-level-cache = <&L2>;
- 			qcom,acc = <&acc0>;
- 			qcom,saw = <&saw0>;
-+			clocks = <&kraitcc 0>, <&kraitcc 4>;
-+			clock-names = "cpu", "l2";
-+			clock-latency = <100000>;
-+			operating-points-v2 = <&opp_table0>;
-+			voltage-tolerance = <5>;
-+			cooling-min-state = <0>;
-+			cooling-max-state = <10>;
-+			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_SPC>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -40,11 +49,35 @@
- 			next-level-cache = <&L2>;
- 			qcom,acc = <&acc1>;
- 			qcom,saw = <&saw1>;
-+			clocks = <&kraitcc 1>, <&kraitcc 4>;
-+			clock-names = "cpu", "l2";
-+			clock-latency = <100000>;
-+			operating-points-v2 = <&opp_table0>;
-+			voltage-tolerance = <5>;
-+			cooling-min-state = <0>;
-+			cooling-max-state = <10>;
-+			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_SPC>;
-+		};
-+
-+		idle-states {
-+			CPU_SPC: spc {
-+				compatible = "qcom,idle-state-spc";
-+				status = "disabled";
-+				entry-latency-us = <400>;
-+				exit-latency-us = <900>;
-+				min-residency-us = <3000>;
-+			};
- 		};
- 
- 		L2: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
-+			qcom,saw = <&saw_l2>;
-+
-+			clocks = <&kraitcc 4>;
-+			clock-names = "l2";
-+			operating-points-v2 = <&opp_table_l2>;
- 		};
- 	};
- 
---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-@@ -2,6 +2,18 @@
- 
- #include "qcom-ipq8064.dtsi"
- 
-+&cpu0 {
-+	cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+	l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- 	smb208_regulators: regulators {
- 		compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-@@ -2,6 +2,18 @@
- 
- #include "qcom-ipq8064-v2.0.dtsi"
- 
-+&cpu0 {
-+	cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+	l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- 	smb208_regulators: regulators {
- 		compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-@@ -2,6 +2,18 @@
- 
- #include "qcom-ipq8062.dtsi"
- 
-+&cpu0 {
-+	cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+	l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- 	smb208_regulators: regulators {
- 		compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-@@ -2,6 +2,18 @@
- 
- #include "qcom-ipq8065.dtsi"
- 
-+&cpu0 {
-+	cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+	l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- 	smb208_regulators: regulators {
- 		compatible = "qcom,rpm-smb208-regulators";
diff --git a/target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch
deleted file mode 100644
index 6be9334e7d..0000000000
--- a/target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:47:09 +0200
-Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
-
-Fix wrong nand_pings definition for bias-disable pins.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -599,12 +599,9 @@
- 			};
- 
- 			nand_pins: nand_pins {
--				mux {
-+				disable {
- 					pins = "gpio34", "gpio35", "gpio36",
--					       "gpio37", "gpio38", "gpio39",
--					       "gpio40", "gpio41", "gpio42",
--					       "gpio43", "gpio44", "gpio45",
--					       "gpio46", "gpio47";
-+					       "gpio37", "gpio38";
- 					function = "nand";
- 					drive-strength = <10>;
- 					bias-disable;
diff --git a/target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch
deleted file mode 100644
index a35bb3874f..0000000000
--- a/target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:59:30 +0200
-Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
- ipq806x
-
-Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
-correctly use the new tag.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
- arch/arm/boot/dts/qcom-ipq8064.dtsi       |  14 +++
- 2 files changed, 81 insertions(+), 67 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-@@ -25,73 +25,6 @@
- 		device_type = "memory";
- 	};
- 
--	mdio0: mdio-0 {
--		status = "okay";
--		compatible = "virtual,mdio-gpio";
--		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
--			<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
--		#address-cells = <1>;
--		#size-cells = <0>;
--
--		pinctrl-0 = <&mdio0_pins>;
--		pinctrl-names = "default";
--
--		switch0: switch@10 {
--			compatible = "qca,qca8337";
--			#address-cells = <1>;
--			#size-cells = <0>;
--
--			dsa,member = <0 0>;
--
--			pinctrl-0 = <&sw0_reset_pin>;
--			pinctrl-names = "default";
--
--			reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
--			reg = <0x10>;
--
--			ports {
--				#address-cells = <1>;
--				#size-cells = <0>;
--
--				switch0cpu: port@0 {
--					reg = <0>;
--					label = "cpu";
--					ethernet = <&gmac0>;
--					phy-mode = "rgmii-id";
--					fixed-link {
--						speed = <1000>;
--						full-duplex;
--					};
--				};
--
--				port@1 {
--					reg = <1>;
--					label = "sw1";
--				};
--
--				port@2 {
--					reg = <2>;
--					label = "sw2";
--				};
--
--				port@3 {
--					reg = <3>;
--					label = "sw3";
--				};
--
--				port@4 {
--					reg = <4>;
--					label = "sw4";
--				};
--
--				port@5 {
--					reg = <5>;
--					label = "sw5";
--				};
--			};
--		};
--	};
--
- 	mdio1: mdio-1 {
- 		status = "okay";
- 		compatible = "virtual,mdio-gpio";
-@@ -222,6 +155,73 @@
- 	status = "okay";
- };
- 
-+&mdio0 {
-+	status = "okay";
-+	compatible = "virtual,mdio-gpio";
-+	gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-+		<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pinctrl-0 = <&mdio0_pins>;
-+	pinctrl-names = "default";
-+
-+	switch0: switch@10 {
-+		compatible = "qca,qca8337";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		dsa,member = <0 0>;
-+
-+		pinctrl-0 = <&sw0_reset_pin>;
-+		pinctrl-names = "default";
-+
-+		reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-+		reg = <0x10>;
-+
-+		ports {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			switch0cpu: port@0 {
-+				reg = <0>;
-+				label = "cpu";
-+				ethernet = <&gmac0>;
-+				phy-mode = "rgmii-id";
-+				fixed-link {
-+					speed = <1000>;
-+					full-duplex;
-+				};
-+			};
-+
-+			port@1 {
-+				reg = <1>;
-+				label = "sw1";
-+			};
-+
-+			port@2 {
-+				reg = <2>;
-+				label = "sw2";
-+			};
-+
-+			port@3 {
-+				reg = <3>;
-+				label = "sw3";
-+			};
-+
-+			port@4 {
-+				reg = <4>;
-+				label = "sw4";
-+			};
-+
-+			port@5 {
-+				reg = <5>;
-+				label = "sw5";
-+			};
-+		};
-+	};
-+};
-+
- &gmac0 {
- 	status = "okay";
- 
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -476,6 +476,20 @@
- 			snps,blen = <16 0 0 0 0 0 0>;
- 		};
- 
-+		mdio0: mdio@37000000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			compatible = "qcom,ipq8064-mdio", "syscon";
-+			reg = <0x37000000 0x200000>;
-+			resets = <&gcc GMAC_CORE1_RESET>;
-+			reset-names = "stmmaceth";
-+			clocks = <&gcc GMAC_CORE1_CLK>;
-+			clock-names = "stmmaceth";
-+
-+			status = "disabled";
-+		};
-+
- 		vsdcc_fixed: vsdcc-regulator {
- 			compatible = "regulator-fixed";
- 			regulator-name = "SDCC Power";
diff --git a/target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch
deleted file mode 100644
index 9de7328879..0000000000
--- a/target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch
+++ /dev/null
@@ -1,235 +0,0 @@
-From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 5 Aug 2020 14:19:23 +0200
-Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
-
-Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
-scale the Cache frequency when the CPU frequency is changed. This
-devfreq driver register with the cpu notifier and scale the Cache
-based on the max Freq across all core as the CPU cache is shared across
-all of them. If provided this also scale the voltage of the regulator
-attached to the CPU cache. The scaling logic is based on the CPU freq
-and the 3 scaling interval are set by the device dts.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig               |  11 ++
- drivers/devfreq/Makefile              |   1 +
- drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
- 3 files changed, 200 insertions(+)
- create mode 100644 drivers/devfreq/krait-cache-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
- 	  This adds the DEVFREQ driver for the MBUS controller in some
- 	  Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
- 
-+config ARM_KRAIT_CACHE_DEVFREQ
-+	tristate "Scaling support for Krait CPU Cache Devfreq"
-+	depends on ARCH_QCOM || COMPILE_TEST
-+	select DEVFREQ_GOV_PASSIVE
-+	help
-+	  This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
-+
-+	  The driver register with the cpufreq notifier and find the right frequency
-+	  based on the max frequency across all core and the range set in the device
-+	  dts. If provided this scale also the regulator attached to the l2 cache.
-+
- source "drivers/devfreq/event/Kconfig"
- 
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)	+
- obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
-+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ)	+= krait-cache-devfreq.o
- 
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT)		+= event/
---- /dev/null
-+++ b/drivers/devfreq/krait-cache-devfreq.c
-@@ -0,0 +1,181 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct krait_cache_data {
-+	struct clk *clk;
-+	unsigned long idle_freq;
-+	int token;
-+};
-+
-+static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
-+			struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
-+			void *data, bool scaling_down)
-+{
-+	struct krait_cache_data *kdata;
-+	unsigned long old_freq, freq;
-+	unsigned long idle_freq;
-+	struct clk *clk;
-+	int ret;
-+
-+	kdata = dev_get_drvdata(dev);
-+	idle_freq = kdata->idle_freq;
-+	clk = kdata->clk;
-+
-+	old_freq = dev_pm_opp_get_freq(old_opp);
-+	freq = dev_pm_opp_get_freq(opp);
-+
-+	/*
-+	 * Set to idle bin if switching from normal to high bin
-+	 * or vice versa. It has been notice that a bug is triggered
-+	 * in cache scaling when more than one bin is scaled, to fix
-+	 * this we first need to transition to the base rate and then
-+	 * to target rate
-+	 */
-+	if (likely(freq != idle_freq && old_freq != idle_freq)) {
-+		ret = clk_set_rate(clk, idle_freq);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return clk_set_rate(clk, freq);
-+};
-+
-+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+	struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+	*freq = clk_get_rate(data->clk);
-+
-+	return 0;
-+};
-+
-+static int krait_cache_target(struct device *dev, unsigned long *freq,
-+			      u32 flags)
-+{
-+	struct dev_pm_opp *opp;
-+
-+	opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+	if (unlikely(IS_ERR(opp)))
-+		return PTR_ERR(opp);
-+
-+	dev_pm_opp_put(opp);
-+
-+	return dev_pm_opp_set_rate(dev, *freq);
-+};
-+
-+static int krait_cache_get_dev_status(struct device *dev,
-+				      struct devfreq_dev_status *stat)
-+{
-+	struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+	stat->busy_time = 0;
-+	stat->total_time = 0;
-+	stat->current_frequency = clk_get_rate(data->clk);
-+
-+	return 0;
-+};
-+
-+static struct devfreq_dev_profile krait_cache_devfreq_profile = {
-+	.target = krait_cache_target,
-+	.get_dev_status = krait_cache_get_dev_status,
-+	.get_cur_freq = krait_cache_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+	.parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int krait_cache_probe(struct platform_device *pdev)
-+{
-+	struct dev_pm_opp_config config = { };
-+	struct device *dev = &pdev->dev;
-+	struct krait_cache_data *data;
-+	struct devfreq *devfreq;
-+	struct dev_pm_opp *opp;
-+	struct clk *clk;
-+	int ret, token;
-+
-+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+
-+	clk = devm_clk_get(dev, "l2");
-+	if (IS_ERR(clk))
-+		return PTR_ERR(clk);
-+
-+	config.regulator_names = (const char *[]){ "l2", NULL };
-+	config.clk_names = (const char *[]){ "l2", NULL };
-+	config.config_clks = krait_cache_config_clk;
-+
-+	token = dev_pm_opp_set_config(dev, &config);
-+	if (token < 0)
-+		return token;
-+
-+	ret = devm_pm_opp_of_add_table(dev);
-+	if (ret)
-+		goto free_opp;
-+
-+	opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
-+	if (IS_ERR(opp)) {
-+		ret = PTR_ERR(opp);
-+		goto free_opp;
-+	}
-+	dev_pm_opp_put(opp);
-+
-+	data->token = token;
-+	data->clk = clk;
-+	dev_set_drvdata(dev, data);
-+	devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
-+					  DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+	if (IS_ERR(devfreq)) {
-+		ret = PTR_ERR(devfreq);
-+		goto free_opp;
-+	}
-+
-+	return 0;
-+
-+free_opp:
-+	dev_pm_opp_clear_config(token);
-+	return ret;
-+};
-+
-+static int krait_cache_remove(struct platform_device *pdev)
-+{
-+	struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
-+
-+	dev_pm_opp_clear_config(data->token);
-+
-+	return 0;
-+};
-+
-+static const struct of_device_id krait_cache_match_table[] = {
-+	{ .compatible = "qcom,krait-cache" },
-+	{}
-+};
-+
-+static struct platform_driver krait_cache_driver = {
-+	.probe		= krait_cache_probe,
-+	.remove		= krait_cache_remove,
-+	.driver		= {
-+		.name   = "krait-cache-scaling",
-+		.of_match_table = krait_cache_match_table,
-+	},
-+};
-+module_platform_driver(krait_cache_driver);
-+
-+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch
deleted file mode 100644
index 45f05dd423..0000000000
--- a/target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 18:39:21 +0200
-Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi
-
-Add qcom,krait-cache compatible to enable cache devfreq driver for
-ipq806x SoC and move the L2 node to the soc node to make the devfreq
-driver correctly probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++-----------
- 1 file changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -69,16 +69,6 @@
- 				min-residency-us = <3000>;
- 			};
- 		};
--
--		L2: l2-cache {
--			compatible = "cache";
--			cache-level = <2>;
--			qcom,saw = <&saw_l2>;
--
--			clocks = <&kraitcc 4>;
--			clock-names = "l2";
--			operating-points-v2 = <&opp_table_l2>;
--		};
- 	};
- 
- 	opp_table_l2: opp_table_l2 {
-@@ -1409,6 +1399,16 @@
- 			#reset-cells = <1>;
- 		};
- 
-+		L2: l2-cache {
-+			compatible = "cache", "qcom,krait-cache";
-+			cache-level = <2>;
-+			qcom,saw = <&saw_l2>;
-+
-+			clocks = <&kraitcc 4>;
-+			clock-names = "l2";
-+			operating-points-v2 = <&opp_table_l2>;
-+		};
-+
- 		lpass@28100000 {
- 			compatible = "qcom,lpass-cpu";
- 			status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch
deleted file mode 100644
index c9cd3ebdf7..0000000000
--- a/target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch
+++ /dev/null
@@ -1,203 +0,0 @@
-From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 19:56:08 +0200
-Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver
-
-Add ipq806x fabric scaling driver using the devfreq passive governor.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig               |  11 ++
- drivers/devfreq/Makefile              |   1 +
- drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -162,6 +162,17 @@ config ARM_KRAIT_CACHE_DEVFREQ
- 	  based on the max frequency across all core and the range set in the device
- 	  dts. If provided this scale also the regulator attached to the l2 cache.
- 
-+config ARM_IPQ806X_FAB_DEVFREQ
-+	tristate "Scaling support for ipq806x Soc Fabric"
-+	depends on ARCH_QCOM || COMPILE_TEST
-+	select DEVFREQ_GOV_PASSIVE
-+	help
-+	  This adds the DEVFREQ driver for the ipq806x Soc Fabric.
-+
-+	  The driver register with the cpufreq notifier and find the right frequency
-+	  based on the max frequency across all core and the range set in the device
-+	  dts.
-+
- source "drivers/devfreq/event/Kconfig"
- 
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+=
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)	+= sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra30-devfreq.o
- obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ)	+= krait-cache-devfreq.o
-+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ)	+= ipq806x-fab-devfreq.o
- 
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT)		+= event/
---- /dev/null
-+++ b/drivers/devfreq/ipq806x-fab-devfreq.c
-@@ -0,0 +1,155 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct ipq806x_fab_data {
-+	struct clk *fab_clk;
-+	struct clk *ddr_clk;
-+};
-+
-+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+	struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+	*freq = clk_get_rate(data->fab_clk);
-+
-+	return 0;
-+};
-+
-+static int ipq806x_fab_target(struct device *dev, unsigned long *freq,
-+			      u32 flags)
-+{
-+	struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+	struct dev_pm_opp *opp;
-+	int ret;
-+
-+	opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+	if (unlikely(IS_ERR(opp)))
-+		return PTR_ERR(opp);
-+
-+	dev_pm_opp_put(opp);
-+
-+	ret = clk_set_rate(data->fab_clk, *freq);
-+	if (ret)
-+		return ret;
-+
-+	return clk_set_rate(data->ddr_clk, *freq);
-+};
-+
-+static int ipq806x_fab_get_dev_status(struct device *dev,
-+				      struct devfreq_dev_status *stat)
-+{
-+	struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+	stat->busy_time = 0;
-+	stat->total_time = 0;
-+	stat->current_frequency = clk_get_rate(data->fab_clk);
-+
-+	return 0;
-+};
-+
-+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = {
-+	.target = ipq806x_fab_target,
-+	.get_dev_status = ipq806x_fab_get_dev_status,
-+	.get_cur_freq = ipq806x_fab_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+	.parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int ipq806x_fab_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct ipq806x_fab_data *data;
-+	struct devfreq *devfreq;
-+	struct clk *clk;
-+	int ret;
-+
-+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+
-+	clk = devm_clk_get(dev, "apps-fab-clk");
-+	if (IS_ERR(clk)) {
-+		dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n");
-+		return PTR_ERR(clk);
-+	}
-+
-+	clk_prepare_enable(clk);
-+	data->fab_clk = clk;
-+
-+	clk = devm_clk_get(dev, "ddr-fab-clk");
-+	if (IS_ERR(clk)) {
-+		dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n");
-+		goto err_ddr;
-+	}
-+
-+	clk_prepare_enable(clk);
-+	data->ddr_clk = clk;
-+
-+	ret = dev_pm_opp_of_add_table(dev);
-+	if (ret) {
-+		dev_err(dev, "failed to parse fab freq thresholds\n");
-+		return ret;
-+	}
-+
-+	dev_set_drvdata(dev, data);
-+
-+	devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile,
-+					  DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+	if (IS_ERR(devfreq))
-+		dev_pm_opp_remove_table(dev);
-+
-+	return PTR_ERR_OR_ZERO(devfreq);
-+
-+err_ddr:
-+	clk_unprepare(data->fab_clk);
-+	clk_put(data->fab_clk);
-+	return PTR_ERR(clk);
-+};
-+
-+static int ipq806x_fab_remove(struct platform_device *pdev)
-+{
-+	struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev);
-+
-+	clk_unprepare(data->fab_clk);
-+	clk_put(data->fab_clk);
-+
-+	clk_unprepare(data->ddr_clk);
-+	clk_put(data->ddr_clk);
-+
-+	dev_pm_opp_remove_table(&pdev->dev);
-+
-+	return 0;
-+};
-+
-+static const struct of_device_id ipq806x_fab_match_table[] = {
-+	{ .compatible = "qcom,fab-scaling" },
-+	{}
-+};
-+
-+static struct platform_driver ipq806x_fab_driver = {
-+	.probe		= ipq806x_fab_probe,
-+	.remove		= ipq806x_fab_remove,
-+	.driver		= {
-+		.name   = "ipq806x-fab-scaling",
-+		.of_match_table = ipq806x_fab_match_table,
-+	},
-+};
-+module_platform_driver(ipq806x_fab_driver);
-+
-+MODULE_DESCRIPTION("ipq806x Fab Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch
deleted file mode 100644
index 24e0ecf619..0000000000
--- a/target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 20:03:05 +0200
-Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x
-
-Add fabric scaling node for ipq806x to correctly scale apps and ddr
-fabric clk.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -170,6 +170,18 @@
- 		};
- 	};
- 
-+	opp_table_fab: opp_table_fab {
-+		compatible = "operating-points-v2";
-+
-+		opp-533000000 {
-+			opp-hz = /bits/ 64 <533000000>;
-+		};
-+
-+		opp-400000000 {
-+			opp-hz = /bits/ 64 <400000000>;
-+		};
-+	};
-+
- 	thermal-zones {
- 		sensor0-thermal {
- 			polling-delay-passive = <0>;
-@@ -1409,6 +1421,13 @@
- 			operating-points-v2 = <&opp_table_l2>;
- 		};
- 
-+		fab-scaling {
-+			compatible = "qcom,fab-scaling";
-+			clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
-+			clock-names = "apps-fab-clk", "ddr-fab-clk";
-+			operating-points-v2 = <&opp_table_fab>;
-+		};
-+
- 		lpass@28100000 {
- 			compatible = "qcom,lpass-cpu";
- 			status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch
deleted file mode 100644
index c30c245d0a..0000000000
--- a/target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:19:28 +0200
-Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
-
-qsb fixed clk may be defined in DTS and correctly passed in the clocks
-list. Add related code to handle this and modify the logic to
-dynamically read qsb clock frequency.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor
- {
- 	struct device *dev = &pdev->dev;
- 	const struct of_device_id *id;
--	unsigned long cur_rate, aux_rate;
-+	unsigned long cur_rate, aux_rate, qsb_rate;
- 	int cpu;
- 	struct clk_hw *mux, *l2_pri_mux;
- 	struct clk *clk, **clks;
-@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor
- 	if (!id)
- 		return -ENODEV;
- 
--	/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
--	clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+	/*
-+	 * Per Documentation qsb should be provided from DTS.
-+	 * To address old implementation, register the fixed clock anyway.
-+	 * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
-+	 */
-+	clk = clk_get(dev, "qsb");
-+	if (IS_ERR(clk))
-+		clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
- 	if (IS_ERR(clk))
- 		return PTR_ERR(clk);
- 
-+	qsb_rate = clk_get_rate(clk);
-+
- 	if (!id->data) {
- 		clk = clk_register_fixed_factor(dev, "acpu_aux",
- 						"gpll0_vote", 0, 1, 2);
diff --git a/target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch
deleted file mode 100644
index e2f78f79fb..0000000000
--- a/target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:24:33 +0200
-Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock
-
-With some tools it was discovered the real frequency of the qsb fixed
-clock. While not 100% correct it's still better than using 1 as a dummy
-frequency.
-Correctly register the qsb fixed clock with the frequency of 225 MHz
-instead of 1.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,6 +25,8 @@ enum {
- 	clks_max,
- };
- 
-+#define QSB_RATE	2250000000
-+
- static unsigned int sec_mux_map[] = {
- 	2,
- 	0,
-@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor
- 	 */
- 	clk = clk_get(dev, "qsb");
- 	if (IS_ERR(clk))
--		clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+		clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE);
- 	if (IS_ERR(clk))
- 		return PTR_ERR(clk);
- 
diff --git a/target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch
deleted file mode 100644
index d95a63fc44..0000000000
--- a/target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 18 Mar 2022 16:12:14 +0100
-Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info
-
-Replace pr_info() with dev_info() to provide better diagnostics.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor
- 	cur_rate = clk_get_rate(clks[l2_mux]);
- 	aux_rate = 384000000;
- 	if (cur_rate < aux_rate) {
--		pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-+		dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
- 		cur_rate = aux_rate;
- 	}
- 	clk_set_rate(clks[l2_mux], aux_rate);
- 	clk_set_rate(clks[l2_mux], 2);
- 	clk_set_rate(clks[l2_mux], cur_rate);
--	pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-+	dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- 	for_each_possible_cpu(cpu) {
- 		clk = clks[cpu];
- 		cur_rate = clk_get_rate(clk);
- 		if (cur_rate < aux_rate) {
--			pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-+			dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- 			cur_rate = aux_rate;
- 		}
- 
- 		clk_set_rate(clk, aux_rate);
- 		clk_set_rate(clk, 2);
- 		clk_set_rate(clk, cur_rate);
--		pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+		dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
- 	}
- 
- 	of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch
deleted file mode 100644
index 8f88e06991..0000000000
--- a/target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 03:33:13 +0200
-Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
- hfpll
-
-Rework and clean mux reset logic.
-Compact it to a for loop to handle both CPU and L2 in one place.
-Move hardcoded aux_rate to define and add a new hfpll_rate value to
-reset hfpll settings.
-Change logic to now reset the hfpll to the lowest value of 600 Mhz and
-then restoring the previous frequency. This permits to reset the hfpll if
-the primary mux was set to source out of the secondary mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,7 +25,9 @@ enum {
- 	clks_max,
- };
- 
--#define QSB_RATE	2250000000
-+#define QSB_RATE	225000000
-+#define AUX_RATE	384000000
-+#define HFPLL_RATE	600000000
- 
- static unsigned int sec_mux_map[] = {
- 	2,
-@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
- {
- 	struct device *dev = &pdev->dev;
- 	const struct of_device_id *id;
--	unsigned long cur_rate, aux_rate, qsb_rate;
-+	unsigned long cur_rate, qsb_rate;
- 	int cpu;
- 	struct clk_hw *mux, *l2_pri_mux;
- 	struct clk *clk, **clks;
-@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
- 	 * two different rates to force a HFPLL reinit under all
- 	 * circumstances.
- 	 */
--	cur_rate = clk_get_rate(clks[l2_mux]);
--	aux_rate = 384000000;
--	if (cur_rate < aux_rate) {
--		dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
--		cur_rate = aux_rate;
--	}
--	clk_set_rate(clks[l2_mux], aux_rate);
--	clk_set_rate(clks[l2_mux], 2);
--	clk_set_rate(clks[l2_mux], cur_rate);
--	dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
--	for_each_possible_cpu(cpu) {
-+	for (cpu = 0; cpu < 5; cpu++) {
-+		const char *l2_s = "L2";
-+		char cpu_s[5];
-+
- 		clk = clks[cpu];
-+		if (!clk)
-+			continue;
-+
-+		if (cpu < 4)
-+			snprintf(cpu_s, 5, "CPU%d", cpu);
-+
- 		cur_rate = clk_get_rate(clk);
--		if (cur_rate < aux_rate) {
--			dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
--			cur_rate = aux_rate;
-+		if (cur_rate < AUX_RATE) {
-+			dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
-+				 cpu < 4 ? cpu_s : l2_s);
-+			cur_rate = AUX_RATE;
- 		}
- 
--		clk_set_rate(clk, aux_rate);
--		clk_set_rate(clk, 2);
-+		clk_set_rate(clk, AUX_RATE);
-+		clk_set_rate(clk, HFPLL_RATE);
- 		clk_set_rate(clk, cur_rate);
--		dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+		dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
-+			 clk_get_rate(clk) / 1000);
- 	}
- 
- 	of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch
deleted file mode 100644
index a7c0f046c8..0000000000
--- a/target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch
+++ /dev/null
@@ -1,156 +0,0 @@
-From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 23 Sep 2022 19:05:39 +0200
-Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
-
-Generilize div functions and remove hardcode to a divisor of 2.
-This is just a cleanup and permit to make it more clear the settings of
-the devisor when used by the krait-cc driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
- drivers/clk/qcom/clk-krait.h | 11 ++++---
- drivers/clk/qcom/krait-cc.c  |  7 +++--
- 3 files changed, 42 insertions(+), 33 deletions(-)
-
---- a/drivers/clk/qcom/clk-krait.c
-+++ b/drivers/clk/qcom/clk-krait.c
-@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
- EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
- 
- /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
--static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
-+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
- 				  unsigned long *parent_rate)
- {
--	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
--	return DIV_ROUND_UP(*parent_rate, 2);
-+	struct krait_div_clk *d = to_krait_div_clk(hw);
-+
-+	*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-+					 rate * d->divisor);
-+
-+	return DIV_ROUND_UP(*parent_rate, d->divisor);
- }
- 
--static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
-+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
- 			       unsigned long parent_rate)
- {
--	struct krait_div2_clk *d = to_krait_div2_clk(hw);
-+	struct krait_div_clk *d = to_krait_div_clk(hw);
-+	u8 div_val = krait_div_to_val(d->divisor);
- 	unsigned long flags;
--	u32 val;
--	u32 mask = BIT(d->width) - 1;
--
--	if (d->lpl)
--		mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
--	else
--		mask <<= d->shift;
-+	u32 regval;
- 
- 	spin_lock_irqsave(&krait_clock_reg_lock, flags);
--	val = krait_get_l2_indirect_reg(d->offset);
--	val &= ~mask;
--	krait_set_l2_indirect_reg(d->offset, val);
-+	regval = krait_get_l2_indirect_reg(d->offset);
-+
-+	regval &= ~(d->mask << d->shift);
-+	regval |= (div_val & d->mask) << d->shift;
-+
-+	if (d->lpl) {
-+		regval &= ~(d->mask << (d->shift + LPL_SHIFT));
-+		regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
-+	}
-+
-+	krait_set_l2_indirect_reg(d->offset, regval);
- 	spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
- 
- 	return 0;
- }
- 
- static unsigned long
--krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
- {
--	struct krait_div2_clk *d = to_krait_div2_clk(hw);
--	u32 mask = BIT(d->width) - 1;
-+	struct krait_div_clk *d = to_krait_div_clk(hw);
- 	u32 div;
- 
- 	div = krait_get_l2_indirect_reg(d->offset);
- 	div >>= d->shift;
--	div &= mask;
--	div = (div + 1) * 2;
-+	div &= d->mask;
- 
--	return DIV_ROUND_UP(parent_rate, div);
-+	return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
- }
- 
--const struct clk_ops krait_div2_clk_ops = {
--	.round_rate = krait_div2_round_rate,
--	.set_rate = krait_div2_set_rate,
--	.recalc_rate = krait_div2_recalc_rate,
-+const struct clk_ops krait_div_clk_ops = {
-+	.round_rate = krait_div_round_rate,
-+	.set_rate = krait_div_set_rate,
-+	.recalc_rate = krait_div_recalc_rate,
- };
--EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
-+EXPORT_SYMBOL_GPL(krait_div_clk_ops);
---- a/drivers/clk/qcom/clk-krait.h
-+++ b/drivers/clk/qcom/clk-krait.h
-@@ -25,17 +25,20 @@ struct krait_mux_clk {
- 
- extern const struct clk_ops krait_mux_clk_ops;
- 
--struct krait_div2_clk {
-+struct krait_div_clk {
- 	u32		offset;
--	u8		width;
-+	u32		mask;
-+	u8		divisor;
- 	u32		shift;
- 	bool		lpl;
- 
- 	struct clk_hw	hw;
- };
- 
--#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
-+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
-+#define krait_div_to_val(_div)		((_div) / 2) - 1
-+#define krait_val_to_div(_val)		((_val) + 1) * 2
- 
--extern const struct clk_ops krait_div2_clk_ops;
-+extern const struct clk_ops krait_div_clk_ops;
- 
- #endif
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -86,11 +86,11 @@ static int krait_notifier_register(struc
- static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
--	struct krait_div2_clk *div;
-+	struct krait_div_clk *div;
- 	static struct clk_parent_data p_data[1];
- 	struct clk_init_data init = {
- 		.num_parents = ARRAY_SIZE(p_data),
--		.ops = &krait_div2_clk_ops,
-+		.ops = &krait_div_clk_ops,
- 		.flags = CLK_SET_RATE_PARENT,
- 	};
- 	struct clk_hw *clk;
-@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
- 	if (!div)
- 		return ERR_PTR(-ENOMEM);
- 
--	div->width = 2;
-+	div->mask = 0x3;
-+	div->divisor = 2;
- 	div->shift = 6;
- 	div->lpl = id >= 0;
- 	div->offset = offset;
diff --git a/target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch
deleted file mode 100644
index 0df29a0787..0000000000
--- a/target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 5 Jul 2022 18:30:18 +0200
-Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
- pxo and cxo
-
-Now that these clock are defined as fixed clk in dts, we can drop the
-register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/gcc-ipq806x.c | 8 --------
- 1 file changed, 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat
- 	struct regmap *regmap;
- 	int ret;
- 
--	ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
--	if (ret)
--		return ret;
--
--	ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
--	if (ret)
--		return ret;
--
- 	if (of_machine_is_compatible("qcom,ipq8065")) {
- 		ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
- 		ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
diff --git a/target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch
deleted file mode 100644
index 397c4481ab..0000000000
--- a/target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SOCINFO)	+= socinfo.o
- obj-$(CONFIG_QCOM_SPM)		+= spm.o
- obj-$(CONFIG_QCOM_STATS)	+= qcom_stats.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR)	 += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -213,6 +213,13 @@ config QCOM_STATS
- 	  various SoC level low power modes statistics and export to debugfs
- 	  interface.
- 
-+config QCOM_TCSR
-+	tristate "QCOM Top Control and Status Registers"
-+	depends on ARCH_QCOM
-+	help
-+	  Say y here to enable TCSR support.  The TCSR provides control
-+	  functions for various peripherals.
-+
- config QCOM_WCNSS_CTRL
- 	tristate "Qualcomm WCNSS control driver"
- 	depends on ARCH_QCOM || COMPILE_TEST
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL	0xb0
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	const struct device_node *node = pdev->dev.of_node;
-+	void __iomem *base;
-+	u32 val;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+		dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+		writel(val, base + TCSR_USB_PORT_SEL);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+	{ .compatible = "qcom,tcsr", },
-+	{ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+	.driver = {
-+		.name		= "tcsr",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= tcsr_dt_match,
-+	},
-+	.probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,23 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0		0x1
-+#define TCSR_USB_SELECT_USB3_P1		0x2
-+#define TCSR_USB_SELECT_USB3_DUAL	0x3
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
-+
-+#endif
diff --git a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
deleted file mode 100644
index c9583549d0..0000000000
--- a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
+++ /dev/null
@@ -1,37 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config CMDLINE
- 	string "Default kernel command string"
- 	default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
- 	if (p != NULL && l > 0)
- 		strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
- 
-+    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+     * device tree option of chosen/bootargs-override. This is
-+     * helpful on boards where u-boot sets bootargs, and is unable
-+     * to be modified.
-+     */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+	if (p != NULL && l > 0)
-+		strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
- 	/*
- 	 * CONFIG_CMDLINE is meant to be a default in case nothing else
diff --git a/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch b/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch
deleted file mode 100644
index 04e2a0c57e..0000000000
--- a/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 19:48:30 +0100
-Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
- appended DTB
-
-There is currently a problem with a very specific sets of kernel config
-and AUTO_ZRELADDR.
-
-For the most common case AUTO_ZRELADDR check the PC register and
-calculate the start of the physical memory. Then fdt_check_mem_start is
-called to make sure the detected value makes sense by comparing it with
-what is present in DTB in the memory nodes and if additional fixup are
-required with the use of linux,usable-memory-range in the chosen node to
-hardcode usable memory range in case some reserved space needs to be
-addressed. With the help of this function the right address is
-calculated and the kernel correctly decompress and loads.
-
-Things starts to become problematic when in the mix,
-CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
-used when legacy systems doesn't support passing a DTB directly and a
-DTB is appended at the end of the image.
-
-In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
-as the appended DTB can be augumented later with ATAGS passed from the
-bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
-
-The main problem and what this patch address is the fact that
-fdt_check_mem_start is never called later when the appended DTB is
-augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
-detection inconsistent and most of the time wrong.
-
-Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
-and calling fdt_check_mem_start with the appended DTB and the augumented
-values permitting legacy device to provide info in DTB instead of
-disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -443,6 +443,28 @@ restart:	adr	r0, LC1
- 		add	r6, r6, r5
- 		add	r10, r10, r5
- 		add	sp, sp, r5
-+
-+#ifdef CONFIG_AUTO_ZRELADDR
-+		/*
-+		 * Validate calculated start of physical memory with appended DTB.
-+		 * In the first iteration for physical memory start calculation,
-+		 * we skipped validating it as it could have been augumented by
-+		 * ATAGS stored at an offset from the same start of physical memory.
-+		 *
-+		 * We now have parsed them and augumented the appended DTB if asked
-+		 * so we can finally validate the start of physical memory.
-+		 *
-+		 * This is needed to apply additional fixup with
-+		 * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
-+		 * the correct value.
-+		 */
-+		sub	r0, r4, #TEXT_OFFSET	@ revert to base address
-+		mov	r1, r8			@ use appended DTB
-+		bl	fdt_check_mem_start
-+
-+		/* Determine final kernel image address. */
-+		add	r4, r0, #TEXT_OFFSET
-+#endif
- dtb_check_done:
- #endif
- 
diff --git a/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch b/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
deleted file mode 100644
index 2e4c4de545..0000000000
--- a/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 20:33:10 +0100
-Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
-
-Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-information about mounted RAM size and physical location.
-Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-size is 512Mb causing kernel panic.
-
-Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
-and not augument appended DTB memory node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/Kconfig                        | 12 ++++++++++++
- arch/arm/boot/compressed/atags_to_fdt.c |  4 ++++
- 2 files changed, 16 insertions(+)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
- 	  bootloaders, this option allows zImage to extract the information
- 	  from the ATAG list and store it at run time into the appended DTB.
- 
-+config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
-+	bool "Ignore MEM ATAG information from bootloader"
-+	depends on ARM_ATAG_DTB_COMPAT
-+	help
-+	  Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-+	  information about mounted RAM size and physical location.
-+	  Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-+	  size is 512Mb causing kernel panic.
-+
-+	  Enable this option if MEM ATAGs should be ignored and the memory
-+	  node in the appended DTB should NOT be augumented.
-+
- choice
- 	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
- 	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
- 				setprop_string(fdt, "/chosen", "bootargs",
- 					       atag->u.cmdline.cmdline);
- 		} else if (atag->hdr.tag == ATAG_MEM) {
-+			/* Bootloader MEM ATAG are broken and should be ignored */
-+			if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
-+				continue;
-+
- 			if (memcount >= sizeof(mem_reg_property)/4)
- 				continue;
- 			if (!atag->u.mem.size)
diff --git a/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
deleted file mode 100644
index 604ac731a8..0000000000
--- a/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
+++ /dev/null
@@ -1,197 +0,0 @@
-From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 21 Jan 2024 23:36:57 +0100
-Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-[ reworked to a cleaner patch ]
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/Kconfig                        |  10 +++
- arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
- init/main.c                             |  12 +++
- 3 files changed, 117 insertions(+), 7 deletions(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 	  The command-line arguments provided by the boot loader will be
- 	  appended to the the device tree bootargs property.
- 
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+	bool "Append rootblock parsing bootloader's kernel arguments"
-+	help
-+	  The command-line arguments provided by the boot loader will be
-+	  appended to a new device tree property: bootloader-args.
-+
-+	  If there is a property "append-rootblock" in DT under /chosen
-+	  and a root= option in bootloaders command line it will be parsed
-+	  and added to DT bootargs with the form: <append-rootblock>XX.
-+
- endchoice
- 
- config CMDLINE_OVERRIDE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -3,7 +3,8 @@
- #include <asm/setup.h>
- #include <libfdt.h>
- 
--#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
-+	defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
- #define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
-@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
- 	return cell_size;
- }
- 
-+/**
-+ * taken from arch/x86/boot/string.c
-+ * local_strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+static char *local_strstr(const char *s1, const char *s2)
-+{
-+	size_t l1, l2;
-+
-+	l2 = strlen(s2);
-+	if (!l2)
-+		return (char *)s1;
-+	l1 = strlen(s1);
-+	while (l1 >= l2) {
-+		l1--;
-+		if (!memcmp(s1, s2, l2))
-+			return (char *)s1;
-+		s1++;
-+	}
-+	return NULL;
-+}
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+	char *ptr, *end, *tmp;
-+	const char *root="root=";
-+	const char *find_rootblock;
-+	int i, l;
-+	const char *rootblock;
-+
-+	find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
-+	if (!find_rootblock)
-+		find_rootblock = root;
-+
-+	/* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
-+	ptr = local_strstr(str, find_rootblock);
-+	if (!ptr)
-+		return dest;
-+
-+	end = strchr(ptr, ' ');
-+	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+	/* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
-+	tmp = strchr(ptr, ',');
-+	if (tmp)
-+		end = end < tmp ? end : tmp - 1;
-+
-+	/*
-+	 * find partition number
-+	 * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
-+	 */
-+	for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+
-+	ptr = end + 1;
-+
-+	/* if append-rootblock property is set use it to append to command line */
-+	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+	if (rootblock != NULL) {
-+		if (*dest != ' ') {
-+			*dest = ' ';
-+			dest++;
-+			len++;
-+		}
-+
-+		if (len + l + i <= COMMAND_LINE_SIZE) {
-+			memcpy(dest, rootblock, l);
-+			dest += l - 1;
-+
-+			memcpy(dest, ptr, i);
-+			dest += i;
-+		}
-+	}
-+
-+	return dest;
-+}
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- 	char cmdline[COMMAND_LINE_SIZE];
-@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
- 			ptr += len - 1;
- 		}
- 
--	/* and append the ATAG_CMDLINE */
- 	if (fdt_cmdline) {
--		len = strlen(fdt_cmdline);
--		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
--			*ptr++ = ' ';
--			memcpy(ptr, fdt_cmdline, len);
--			ptr += len;
-+		if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
-+			/*
-+			* save original bootloader args
-+			* and append ubi.mtd with root partition number
-+			* to current cmdline
-+			*/
-+			setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+			ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+		} else {
-+			/* and append the ATAG_CMDLINE */
-+			len = strlen(fdt_cmdline);
-+			if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-+				*ptr++ = ' ';
-+				memcpy(ptr, fdt_cmdline, len);
-+				ptr += len;
-+			}
- 		}
- 	}
- 	*ptr = '\0';
---- a/init/main.c
-+++ b/init/main.c
-@@ -28,6 +28,7 @@
- #include <linux/initrd.h>
- #include <linux/memblock.h>
- #include <linux/acpi.h>
-+#include <linux/of.h>
- #include <linux/bootconfig.h>
- #include <linux/console.h>
- #include <linux/nmi.h>
-@@ -996,6 +997,17 @@ asmlinkage __visible void __init __no_sa
- 	pr_notice("Kernel command line: %s\n", saved_command_line);
- 	/* parameters may set static keys */
- 	jump_label_init();
-+
-+	/* Show bootloader's original command line for reference */
-+	if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
-+		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+
-+		if(prop)
-+			pr_notice("Bootloader command line (ignored): %s\n", prop);
-+		else
-+			pr_notice("Bootloader command line not present\n");
-+	}
-+
- 	parse_early_param();
- 	after_dashes = parse_args("Booting kernel",
- 				  static_command_line, __start___param,
diff --git a/target/linux/ipq806x/patches-6.6/130-mtd-rawnand-qcom-Fix-broken-misc_cmd_type-in-exec_op.patch b/target/linux/ipq806x/patches-6.6/130-mtd-rawnand-qcom-Fix-broken-misc_cmd_type-in-exec_op.patch
deleted file mode 100644
index caa5b070e4..0000000000
--- a/target/linux/ipq806x/patches-6.6/130-mtd-rawnand-qcom-Fix-broken-misc_cmd_type-in-exec_op.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 9732c4f2d93a4a39ffc903c88ab7d531a8bb2e74 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 20 Mar 2024 00:47:58 +0100
-Subject: [PATCH] mtd: rawnand: qcom: Fix broken misc_cmd_type in exec_op
-
-misc_cmd_type in exec_op have multiple problems. With commit a82990c8a409
-("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") it was
-reworked and generalized but actually dropped the handling of the
-RESET_DEVICE command.
-
-Also additional logic was added without clear explaination causing the
-erase command to be broken on testing it on a ipq806x nandc.
-
-Add some additional logic to restore RESET_DEVICE command handling and
-fix erase command.
-
-Fixes: a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path")
-Cc: stable@vger.kernel.org
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/mtd/nand/raw/qcom_nandc.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
---- a/drivers/mtd/nand/raw/qcom_nandc.c
-+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struc
- 			      host->cfg0_raw & ~(7 << CW_PER_PAGE));
- 		nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
- 		instrs = 3;
--	} else {
-+	} else if (q_op.cmd_reg != OP_RESET_DEVICE) {
- 		return 0;
- 	}
- 
-@@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struc
- 	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
- 
- 	write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
--	(q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
--	2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
--	NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
-+	if (q_op.cmd_reg == OP_BLOCK_ERASE)
-+		write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
- 
- 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- 	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
diff --git a/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
index 969f8b9ef3..db4ad0ce68 100644
--- a/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
+++ b/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
@@ -177,7 +177,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  #include <linux/bootconfig.h>
  #include <linux/console.h>
  #include <linux/nmi.h>
-@@ -930,6 +931,17 @@ void start_kernel(void)
+@@ -932,6 +933,17 @@ void start_kernel(void)
  	pr_notice("Kernel command line: %s\n", saved_command_line);
  	/* parameters may set static keys */
  	jump_label_init();
diff --git a/target/linux/ixp4xx/Makefile b/target/linux/ixp4xx/Makefile
index f089687da9..f84f07798d 100644
--- a/target/linux/ixp4xx/Makefile
+++ b/target/linux/ixp4xx/Makefile
@@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk
 ARCH:=armeb
 BOARD:=ixp4xx
 BOARDNAME:=Intel XScale IXP4xx
-FEATURES:=dt squashfs gpio
+FEATURES:=dt squashfs gpio ext4 rootfs-part
 CPU_TYPE:=xscale
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for the IXP4xx XScale CPU
diff --git a/target/linux/ixp4xx/base-files/etc/board.d/02_network b/target/linux/ixp4xx/base-files/etc/board.d/02_network
index 864328d6bc..6a361d4f53 100644
--- a/target/linux/ixp4xx/base-files/etc/board.d/02_network
+++ b/target/linux/ixp4xx/base-files/etc/board.d/02_network
@@ -4,10 +4,13 @@
 board_config_update
 
 case "$(board_name)" in
+freecom,fsg-3|\
 gateworks,gw2348|\
 gateworks,gw2358)
 	ucidef_set_interfaces_lan_wan "eth0" "eth1"
 	;;
+dlink,dsm-g600-a|\
+iom,nas-100d|\
 linksys,nslu2)
 	ucidef_set_interface_lan "eth0" "dhcp"
 	;;
diff --git a/target/linux/ixp4xx/config-6.1 b/target/linux/ixp4xx/config-6.1
deleted file mode 100644
index 4c4aa11969..0000000000
--- a/target/linux/ixp4xx/config-6.1
+++ /dev/null
@@ -1,253 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AMD_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IXP4XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_ENDIAN_BE32=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DEV_IXP4XX=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xc8000003
-CONFIG_DEBUG_UART_VIRT=0xfec00003
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-# CONFIG_FARSYNC is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_PCI=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GW_PLD=y
-CONFIG_GPIO_IXP4XX=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDLC=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IXP4XX=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_IOP3XX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INTEL_IXP4XX_EB=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_IXP4XX_ETH=y
-CONFIG_IXP4XX_HSS=y
-CONFIG_IXP4XX_IRQ=y
-CONFIG_IXP4XX_NPE=y
-CONFIG_IXP4XX_QMGR=y
-CONFIG_IXP4XX_TIMER=y
-CONFIG_IXP4XX_WATCHDOG=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_IXP4XX=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_XSCALE=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-# CONFIG_OLD_SIGACTION is not set
-# CONFIG_OLD_SIGSUSPEND3 is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PATA_IXP4XX_CF=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_IXP4XX=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RUST_IS_AVAILABLE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250_EXAR is not set
-# CONFIG_SERIAL_8250_FSL is not set
-# CONFIG_SERIAL_8250_PCI is not set
-# CONFIG_SERIAL_8250_PERICOM is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/target/linux/ixp4xx/config-6.6 b/target/linux/ixp4xx/config-6.6
new file mode 100644
index 0000000000..960012ada4
--- /dev/null
+++ b/target/linux/ixp4xx/config-6.6
@@ -0,0 +1,263 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMD_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IXP4XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_ENDIAN_BE32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_DEV_IXP4XX=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_PHYS=0xc8000003
+CONFIG_DEBUG_UART_VIRT=0xfec00003
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+# CONFIG_FARSYNC is not set
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FORCE_PCI=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GW_PLD=y
+CONFIG_GPIO_IXP4XX=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDLC=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_IXP4XX=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IOP3XX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_IXP4XX_EB=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_IWMMXT is not set
+CONFIG_IXP4XX_ETH=y
+CONFIG_IXP4XX_HSS=y
+CONFIG_IXP4XX_IRQ=y
+CONFIG_IXP4XX_NPE=y
+CONFIG_IXP4XX_QMGR=y
+CONFIG_IXP4XX_TIMER=y
+CONFIG_IXP4XX_WATCHDOG=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_OTP=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_XSCALE=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PATA_IXP4XX_CF=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_IXP4XX=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile
index c6d4817c96..ace533e50f 100644
--- a/target/linux/ixp4xx/image/Makefile
+++ b/target/linux/ixp4xx/image/Makefile
@@ -12,6 +12,16 @@ define Build/linksys-ixp425-image
 	mv $@.new $@
 endef
 
+define Build/freecom-image
+	mkdir -p $@.tmptar
+	# Add kernel
+	cp $@ $@.tmptar/zImage
+	cd $@.tmptar && tar -c -j -f $@.new --numeric-owner --owner=0 --group=0 *
+	rm -rf $@.tmptar
+	encode_crc $@.new $@
+	rm -f $@.new
+endef
+
 # Build sysupgrade image
 define BuildFirmware/Generic
 	dd if=$(KDIR)/zImage of=$(KDIR)/zImage.pad bs=64k conv=sync; \
@@ -29,12 +39,39 @@ endef
 
 define Device/Default
 	PROFILES := Default
+	DEVICE_DTS_DIR = $$(DTS_DIR)/intel/ixp
 	KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
 	KERNEL_NAME := zImage
 	KERNEL := kernel-bin | append-dtb
 	BLOCKSIZE := 128k
 endef
 
+define Device/dlink_dsm_g600_a
+	DEVICE_VENDOR := D-Link
+	DEVICE_MODEL := DSM G600 A
+	DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563 kmod-via-velocity kmod-ata-artop kmod-ath5k wpad-basic-mbedtls
+	DEVICE_DTS := intel-ixp42x-dlink-dsm-g600
+	KERNEL := kernel-bin | append-dtb
+	IMAGES := kernel.bin rootfs.bin
+	IMAGE/kernel.bin := append-kernel
+	IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k
+endef
+TARGET_DEVICES += dlink_dsm_g600_a
+
+define Device/freecom_fsg_3
+	DEVICE_VENDOR := Freecom
+	DEVICE_MODEL := FSG-3
+	DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-isl1208 kmod-ath5k wpad-basic-mbedtls
+	# Only 4 MB of Flash so not building by default
+	DEFAULT := n
+	DEVICE_DTS := intel-ixp42x-freecom-fsg-3
+	KERNEL := kernel-bin | append-dtb
+	IMAGES := factory.bin
+	# This has to boot from harddisk so just append the kernel
+	IMAGE/factory.bin := append-kernel | freecom-image
+endef
+TARGET_DEVICES += freecom_fsg_3
+
 define Device/gateworks_avila
 	DEVICE_VENDOR := Gateworks
 	DEVICE_MODEL := Avila GW2348-4
@@ -59,6 +96,19 @@ define Device/gateworks_cambria
 endef
 TARGET_DEVICES += gateworks_cambria
 
+define Device/iomega_nas100d
+	DEVICE_VENDOR := Iomega
+	DEVICE_MODEL := NAS100d
+	# USB2 is compiled in and needs no package
+	DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563
+	DEVICE_DTS := intel-ixp42x-iomega-nas100d
+	KERNEL := kernel-bin | append-dtb
+	IMAGES := factory.bin
+	# This has to boot from harddisk so just append the kernel
+	IMAGE/factory.bin := append-kernel | linksys-ixp425-image "nas100d"
+endef
+TARGET_DEVICES += iomega_nas100d
+
 define Device/linksys_nslu2
 	DEVICE_VENDOR := Linksys
 	DEVICE_MODEL := NSLU2
diff --git a/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch b/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
deleted file mode 100644
index 38adecd64f..0000000000
--- a/target/linux/ixp4xx/patches-6.1/0002-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Thu, 21 Sep 2023 00:12:42 +0200
-Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
-
-This makes it possible to provide basic clock output on pins
-14 and 15. The clocks are typically used by random electronics,
-not modeled in the device tree, so they just need to be provided
-on request.
-
-In order to not disturb old systems that require that the
-hardware defaults are kept in the clock setting bits, we only
-manipulate these if either device tree property is present.
-Once we know a device needs one of the clocks we can set it
-in the device tree.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
- 1 file changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpio-ixp4xx.c
-+++ b/drivers/gpio/gpio-ixp4xx.c
-@@ -38,6 +38,18 @@
- #define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)
- #define IXP4XX_GPIO_STYLE_SIZE		3
- 
-+/*
-+ * Clock output control register defines.
-+ */
-+#define IXP4XX_GPCLK_CLK0DC_SHIFT	0
-+#define IXP4XX_GPCLK_CLK0TC_SHIFT	4
-+#define IXP4XX_GPCLK_CLK0_MASK		GENMASK(7, 0)
-+#define IXP4XX_GPCLK_MUX14		BIT(8)
-+#define IXP4XX_GPCLK_CLK1DC_SHIFT	16
-+#define IXP4XX_GPCLK_CLK1TC_SHIFT	20
-+#define IXP4XX_GPCLK_CLK1_MASK		GENMASK(23, 16)
-+#define IXP4XX_GPCLK_MUX15		BIT(24)
-+
- /**
-  * struct ixp4xx_gpio - IXP4 GPIO state container
-  * @dev: containing device for this instance
-@@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
- 	struct ixp4xx_gpio *g;
- 	struct gpio_irq_chip *girq;
- 	struct device_node *irq_parent;
-+	bool clk_14, clk_15;
-+	u32 val;
- 	int ret;
- 
- 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
-@@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
- 	 */
- 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||
- 	    of_machine_is_compatible("iom,nas-100d"))
--		__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
-+		val = 0;
-+	else
-+		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
-+
-+	/*
-+	 * If either clock output is enabled explicitly in the device tree
-+	 * we take full control of the clock by masking off all bits for
-+	 * the clock control and selectively enabling them. Otherwise
-+	 * we leave the hardware default settings.
-+	 *
-+	 * Enable clock outputs with default timings of requested clock.
-+	 * If you need control over TC and DC, add these to the device
-+	 * tree bindings and use them here.
-+	 */
-+	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
-+	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
-+	if (clk_14 || clk_15) {
-+		val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
-+		val &= ~IXP4XX_GPCLK_CLK0_MASK;
-+		val &= ~IXP4XX_GPCLK_CLK1_MASK;
-+		if (clk_14) {
-+			val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
-+			val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
-+			val |= IXP4XX_GPCLK_MUX14;
-+		}
-+
-+		if (clk_15) {
-+			val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
-+			val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
-+			val |= IXP4XX_GPCLK_MUX15;
-+		}
-+	}
-+
-+	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);
- 
- 	/*
- 	 * This is a very special big-endian ARM issue: when the IXP4xx is
diff --git a/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch b/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
deleted file mode 100644
index 0ae80d170e..0000000000
--- a/target/linux/ixp4xx/patches-6.1/0004-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
+++ /dev/null
@@ -1,260 +0,0 @@
-From 02693ffdb93bffcbe772bd91a399dabd123b8c19 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 19 Sep 2023 16:02:15 +0200
-Subject: [PATCH 4/4] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
-
-This is a USRobotics NAS/Firewall/router that has been supported
-by OpenWrt in the past. It had dedicated users so let's get it
-properly supported.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/Makefile                    |   3 +-
- .../dts/intel-ixp42x-usrobotics-usr8200.dts   | 229 ++++++++++++++++++
- 2 files changed, 231 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
- 	intel-ixp43x-gateworks-gw2358.dtb \
- 	intel-ixp42x-netgear-wg302v1.dtb \
- 	intel-ixp42x-arcom-vulcan.dtb \
--	intel-ixp42x-gateway-7001.dtb
-+	intel-ixp42x-gateway-7001.dtb \
-+	intel-ixp42x-usrobotics-usr8200.dtb
- dtb-$(CONFIG_ARCH_KEYSTONE) += \
- 	keystone-k2hk-evm.dtb \
- 	keystone-k2l-evm.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the USRobotics USR8200 firewall
-+ * VPN and NAS. Based on know-how from Peter Denison.
-+ *
-+ * This machine is based on IXP422, the USR internal codename
-+ * is "Jeeves".
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+	model = "USRobotics USR8200";
-+	compatible = "usr,usr8200", "intel,ixp42x";
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x00000000 0x4000000>;
-+	};
-+
-+	chosen {
-+		bootargs = "console=ttyS0,115200n8";
-+		stdout-path = "uart1:115200n8";
-+	};
-+
-+	aliases {
-+		/* These are switched around */
-+		serial0 = &uart1;
-+		serial1 = &uart0;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+		ieee1394_led: led-1394 {
-+			label = "usr8200:green:1394";
-+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
-+			default-state = "off";
-+		};
-+		usb1_led: led-usb1 {
-+			label = "usr8200:green:usb1";
-+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
-+			default-state = "off";
-+		};
-+		usb2_led: led-usb2 {
-+			label = "usr8200:green:usb2";
-+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-+			default-state = "off";
-+		};
-+		wireless_led: led-wireless {
-+			/*
-+			 * This LED is mounted inside the case but cannot be
-+			 * seen from the outside: probably USR planned at one
-+			 * point for the device to have a wireless card, then
-+			 * changed their mind and didn't mount it, leaving the
-+			 * LED in place.
-+			 */
-+			label = "usr8200:green:wireless";
-+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-+			default-state = "off";
-+		};
-+		pwr_led: led-pwr {
-+			label = "usr8200:green:pwr";
-+			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-+			default-state = "on";
-+			linux,default-trigger = "heartbeat";
-+		};
-+	};
-+
-+	gpio_keys {
-+		compatible = "gpio-keys";
-+
-+		button-reset {
-+			wakeup-source;
-+			linux,code = <KEY_RESTART>;
-+			label = "reset";
-+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	soc {
-+		bus@c4000000 {
-+			flash@0,0 {
-+				compatible = "intel,ixp4xx-flash", "cfi-flash";
-+				bank-width = <2>;
-+				/* Enable writes on the expansion bus */
-+				intel,ixp4xx-eb-write-enable = <1>;
-+				/* 16 MB of Flash mapped in at CS0 */
-+				reg = <0 0x00000000 0x1000000>;
-+
-+				partitions {
-+					compatible = "redboot-fis";
-+					/* Eraseblock at 0x0fe0000 */
-+					fis-index-block = <0x7f>;
-+				};
-+			};
-+			rtc@2,0 {
-+				/* EPSON RTC7301 DG DIL-capsule */
-+				compatible = "epson,rtc7301dg";
-+				/*
-+				 * These timing settings were found in the boardfile patch:
-+				 * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
-+				 *                  IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
-+				 */
-+				intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
-+				intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
-+				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
-+				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
-+				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
-+				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
-+				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
-+				intel,ixp4xx-eb-mux-address-and-data = <0>;
-+				intel,ixp4xx-eb-ahb-split-transfers = <0>;
-+				intel,ixp4xx-eb-write-enable = <1>;
-+				intel,ixp4xx-eb-byte-access = <1>;
-+				/* 512 bytes at CS2 */
-+				reg = <2 0x00000000 0x0000200>;
-+				reg-io-width = <1>;
-+				native-endian;
-+				/* FIXME: try to check if there is an IRQ for the RTC? */
-+			};
-+		};
-+
-+		pci@c0000000 {
-+			status = "okay";
-+
-+			/*
-+			 * Taken from USR8200 boardfile from OpenWrt
-+			 *
-+			 * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
-+			 * We assume the same IRQ for all pins on the remaining slots, that
-+			 * is what the boardfile was doing.
-+			 */
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0xf800 0 0 7>;
-+			interrupt-map =
-+			/* IDSEL 14 used for "Wireless" in the board file */
-+			<0x7000 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
-+			/* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
-+			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
-+			/* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
-+			<0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
-+			<0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
-+			<0x8000 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
-+		};
-+
-+		gpio@c8004000 {
-+			/* Enable clock out on GPIO 15 */
-+			intel,ixp4xx-gpio15-clkout;
-+		};
-+
-+		/* EthB WAN */
-+		ethernet@c8009000 {
-+			status = "okay";
-+			queue-rx = <&qmgr 3>;
-+			queue-txready = <&qmgr 20>;
-+			phy-mode = "rgmii";
-+			phy-handle = <&phy9>;
-+
-+			mdio {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				phy9: ethernet-phy@9 {
-+					reg = <9>;
-+				};
-+
-+				/* The switch uses MDIO addresses 16 thru 31 */
-+				switch@16 {
-+					compatible = "marvell,mv88e6060";
-+					reg = <16>;
-+
-+					ports {
-+						#address-cells = <1>;
-+						#size-cells = <0>;
-+
-+						port@0 {
-+							reg = <0>;
-+							label = "lan1";
-+						};
-+
-+						port@1 {
-+							reg = <1>;
-+							label = "lan2";
-+						};
-+
-+						port@2 {
-+							reg = <2>;
-+							label = "lan3";
-+						};
-+
-+						port@3 {
-+							reg = <3>;
-+							label = "lan4";
-+						};
-+
-+						port@5 {
-+							/* Port 5 is the CPU port according to the MV88E6060 datasheet */
-+							reg = <5>;
-+							phy-mode = "rgmii-id";
-+							ethernet = <&ethc>;
-+							label = "cpu";
-+							fixed-link {
-+								speed = <100>;
-+								full-duplex;
-+							};
-+						};
-+					};
-+				};
-+			};
-+		};
-+
-+		/* EthC LAN connected to the Marvell DSA Switch */
-+		ethc: ethernet@c800a000 {
-+			status = "okay";
-+			queue-rx = <&qmgr 4>;
-+			queue-txready = <&qmgr 21>;
-+			phy-mode = "rgmii";
-+			fixed-link {
-+				speed = <100>;
-+				full-duplex;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch b/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch
deleted file mode 100644
index bf056b89a9..0000000000
--- a/target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From a1ab45966e5a21841af58742adf27725e523d303 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 14 Oct 2023 19:53:24 +0200
-Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
-
-The MV88E6060 switch has internal PHY registers at MDIO
-addresses 0x00..0x04. Tie each port to the corresponding
-PHY.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../dts/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -165,6 +165,24 @@
- 				#address-cells = <1>;
- 				#size-cells = <0>;
- 
-+				/*
-+				 * PHY 0..4 are internal to the MV88E6060 switch but appear
-+				 * as independent devices.
-+				 */
-+				phy0: ethernet-phy@0 {
-+					reg = <0>;
-+				};
-+				phy1: ethernet-phy@1 {
-+					reg = <1>;
-+				};
-+				phy2: ethernet-phy@2 {
-+					reg = <2>;
-+				};
-+				phy3: ethernet-phy@3 {
-+					reg = <3>;
-+				};
-+
-+				/* Altima AMI101L used by the WAN port */
- 				phy9: ethernet-phy@9 {
- 					reg = <9>;
- 				};
-@@ -181,21 +199,25 @@
- 						port@0 {
- 							reg = <0>;
- 							label = "lan1";
-+							phy-handle = <&phy0>;
- 						};
- 
- 						port@1 {
- 							reg = <1>;
- 							label = "lan2";
-+							phy-handle = <&phy1>;
- 						};
- 
- 						port@2 {
- 							reg = <2>;
- 							label = "lan3";
-+							phy-handle = <&phy2>;
- 						};
- 
- 						port@3 {
- 							reg = <3>;
- 							label = "lan4";
-+							phy-handle = <&phy3>;
- 						};
- 
- 						port@5 {
diff --git a/target/linux/ixp4xx/patches-6.1/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch b/target/linux/ixp4xx/patches-6.1/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch
deleted file mode 100644
index ffd69a774c..0000000000
--- a/target/linux/ixp4xx/patches-6.1/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 2792791a19f90b0141ed2e781599ba0a42a8cfd5 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 29 May 2023 23:32:44 +0200
-Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
-
-This enforces harddrive boot on the NSLU2. The flash is too small
-to hold any rootfs these days.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-@@ -21,7 +21,7 @@
- 	};
- 
- 	chosen {
--		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
-+		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
- 		stdout-path = "uart0:115200n8";
- 	};
- 
diff --git a/target/linux/ixp4xx/patches-6.6/0001-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch b/target/linux/ixp4xx/patches-6.6/0001-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
new file mode 100644
index 0000000000..0498edcd1b
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0001-gpio-ixp4xx-Handle-clock-output-on-pin-14-and-15.patch
@@ -0,0 +1,93 @@
+From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 21 Sep 2023 00:12:42 +0200
+Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
+
+This makes it possible to provide basic clock output on pins
+14 and 15. The clocks are typically used by random electronics,
+not modeled in the device tree, so they just need to be provided
+on request.
+
+In order to not disturb old systems that require that the
+hardware defaults are kept in the clock setting bits, we only
+manipulate these if either device tree property is present.
+Once we know a device needs one of the clocks we can set it
+in the device tree.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ixp4xx.c
++++ b/drivers/gpio/gpio-ixp4xx.c
+@@ -38,6 +38,18 @@
+ #define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)
+ #define IXP4XX_GPIO_STYLE_SIZE		3
+ 
++/*
++ * Clock output control register defines.
++ */
++#define IXP4XX_GPCLK_CLK0DC_SHIFT	0
++#define IXP4XX_GPCLK_CLK0TC_SHIFT	4
++#define IXP4XX_GPCLK_CLK0_MASK		GENMASK(7, 0)
++#define IXP4XX_GPCLK_MUX14		BIT(8)
++#define IXP4XX_GPCLK_CLK1DC_SHIFT	16
++#define IXP4XX_GPCLK_CLK1TC_SHIFT	20
++#define IXP4XX_GPCLK_CLK1_MASK		GENMASK(23, 16)
++#define IXP4XX_GPCLK_MUX15		BIT(24)
++
+ /**
+  * struct ixp4xx_gpio - IXP4 GPIO state container
+  * @dev: containing device for this instance
+@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct plat
+ 	struct ixp4xx_gpio *g;
+ 	struct gpio_irq_chip *girq;
+ 	struct device_node *irq_parent;
++	bool clk_14, clk_15;
++	u32 val;
+ 	int ret;
+ 
+ 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+@@ -231,7 +245,40 @@ static int ixp4xx_gpio_probe(struct plat
+ 	 */
+ 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||
+ 	    of_machine_is_compatible("iom,nas-100d"))
+-		__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
++		val = 0;
++	else
++		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
++
++	/*
++	 * If either clock output is enabled explicitly in the device tree
++	 * we take full control of the clock by masking off all bits for
++	 * the clock control and selectively enabling them. Otherwise
++	 * we leave the hardware default settings.
++	 *
++	 * Enable clock outputs with default timings of requested clock.
++	 * If you need control over TC and DC, add these to the device
++	 * tree bindings and use them here.
++	 */
++	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
++	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
++	if (clk_14 || clk_15) {
++		val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
++		val &= ~IXP4XX_GPCLK_CLK0_MASK;
++		val &= ~IXP4XX_GPCLK_CLK1_MASK;
++		if (clk_14) {
++			val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
++			val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
++			val |= IXP4XX_GPCLK_MUX14;
++		}
++
++		if (clk_15) {
++			val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
++			val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
++			val |= IXP4XX_GPCLK_MUX15;
++		}
++	}
++
++	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);
+ 
+ 	/*
+ 	 * This is a very special big-endian ARM issue: when the IXP4xx is
diff --git a/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch b/target/linux/ixp4xx/patches-6.6/0002-net-ixp4xx_eth-Support-changing-the-MTU.patch
index 4abc6cdbe4..4abc6cdbe4 100644
--- a/target/linux/ixp4xx/patches-6.1/0005-net-ixp4xx_eth-Support-changing-the-MTU.patch
+++ b/target/linux/ixp4xx/patches-6.6/0002-net-ixp4xx_eth-Support-changing-the-MTU.patch
diff --git a/target/linux/ixp4xx/patches-6.6/0003-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch b/target/linux/ixp4xx/patches-6.6/0003-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
new file mode 100644
index 0000000000..93b12a5381
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0003-ARM-dts-ixp4xx-Add-USRobotics-USR8200-device-tree.patch
@@ -0,0 +1,260 @@
+From a1490c1e8a12a8286c6a34c3d277a519066fc51e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 7 Oct 2023 14:32:40 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
+
+This is a USRobotics NAS/Firewall/router that has been supported
+by OpenWrt in the past. It had dedicated users so let's get it
+properly supported.
+
+Some debugging and fixing was provided by Howard Harte.
+
+Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/Makefile          |   3 +-
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts   | 229 ++++++++++++++++++
+ 2 files changed, 231 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+
+--- a/arch/arm/boot/dts/intel/ixp/Makefile
++++ b/arch/arm/boot/dts/intel/ixp/Makefile
+@@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ 	intel-ixp43x-gateworks-gw2358.dtb \
+ 	intel-ixp42x-netgear-wg302v1.dtb \
+ 	intel-ixp42x-arcom-vulcan.dtb \
+-	intel-ixp42x-gateway-7001.dtb
++	intel-ixp42x-gateway-7001.dtb \
++	intel-ixp42x-usrobotics-usr8200.dtb
+--- /dev/null
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for the USRobotics USR8200 firewall
++ * VPN and NAS. Based on know-how from Peter Denison.
++ *
++ * This machine is based on IXP422, the USR internal codename
++ * is "Jeeves".
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "USRobotics USR8200";
++	compatible = "usr,usr8200", "intel,ixp42x";
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	memory@0 {
++		device_type = "memory";
++		reg = <0x00000000 0x4000000>;
++	};
++
++	chosen {
++		bootargs = "console=ttyS0,115200n8";
++		stdout-path = "uart1:115200n8";
++	};
++
++	aliases {
++		/* These are switched around */
++		serial0 = &uart1;
++		serial1 = &uart0;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		ieee1394_led: led-1394 {
++			label = "usr8200:green:1394";
++			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		usb1_led: led-usb1 {
++			label = "usr8200:green:usb1";
++			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		usb2_led: led-usb2 {
++			label = "usr8200:green:usb2";
++			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		wireless_led: led-wireless {
++			/*
++			 * This LED is mounted inside the case but cannot be
++			 * seen from the outside: probably USR planned at one
++			 * point for the device to have a wireless card, then
++			 * changed their mind and didn't mount it, leaving the
++			 * LED in place.
++			 */
++			label = "usr8200:green:wireless";
++			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++			default-state = "off";
++		};
++		pwr_led: led-pwr {
++			label = "usr8200:green:pwr";
++			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	gpio_keys {
++		compatible = "gpio-keys";
++
++		button-reset {
++			wakeup-source;
++			linux,code = <KEY_RESTART>;
++			label = "reset";
++			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	soc {
++		bus@c4000000 {
++			flash@0,0 {
++				compatible = "intel,ixp4xx-flash", "cfi-flash";
++				bank-width = <2>;
++				/* Enable writes on the expansion bus */
++				intel,ixp4xx-eb-write-enable = <1>;
++				/* 16 MB of Flash mapped in at CS0 */
++				reg = <0 0x00000000 0x1000000>;
++
++				partitions {
++					compatible = "redboot-fis";
++					/* Eraseblock at 0x0fe0000 */
++					fis-index-block = <0x7f>;
++				};
++			};
++			rtc@2,0 {
++				/* EPSON RTC7301 DG DIL-capsule */
++				compatible = "epson,rtc7301dg";
++				/*
++				 * These timing settings were found in the boardfile patch:
++				 * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
++				 *                  IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
++				 */
++				intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
++				intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
++				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
++				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
++				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
++				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
++				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
++				intel,ixp4xx-eb-mux-address-and-data = <0>;
++				intel,ixp4xx-eb-ahb-split-transfers = <0>;
++				intel,ixp4xx-eb-write-enable = <1>;
++				intel,ixp4xx-eb-byte-access = <1>;
++				/* 512 bytes at CS2 */
++				reg = <2 0x00000000 0x0000200>;
++				reg-io-width = <1>;
++				native-endian;
++				/* FIXME: try to check if there is an IRQ for the RTC? */
++			};
++		};
++
++		pci@c0000000 {
++			status = "okay";
++
++			/*
++			 * Taken from USR8200 boardfile from OpenWrt
++			 *
++			 * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
++			 * We assume the same IRQ for all pins on the remaining slots, that
++			 * is what the boardfile was doing.
++			 */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0xf800 0 0 7>;
++			interrupt-map =
++			/* IDSEL 14 used for "Wireless" in the board file */
++			<0x7000 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
++			/* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
++			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
++			/* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
++			<0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
++			<0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
++			<0x8000 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
++		};
++
++		gpio@c8004000 {
++			/* Enable clock out on GPIO 15 */
++			intel,ixp4xx-gpio15-clkout;
++		};
++
++		/* EthB WAN */
++		ethernet@c8009000 {
++			status = "okay";
++			queue-rx = <&qmgr 3>;
++			queue-txready = <&qmgr 20>;
++			phy-mode = "rgmii";
++			phy-handle = <&phy9>;
++
++			mdio {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				phy9: ethernet-phy@9 {
++					reg = <9>;
++				};
++
++				/* The switch uses MDIO addresses 16 thru 31 */
++				switch@16 {
++					compatible = "marvell,mv88e6060";
++					reg = <16>;
++
++					ports {
++						#address-cells = <1>;
++						#size-cells = <0>;
++
++						port@0 {
++							reg = <0>;
++							label = "lan1";
++						};
++
++						port@1 {
++							reg = <1>;
++							label = "lan2";
++						};
++
++						port@2 {
++							reg = <2>;
++							label = "lan3";
++						};
++
++						port@3 {
++							reg = <3>;
++							label = "lan4";
++						};
++
++						port@5 {
++							/* Port 5 is the CPU port according to the MV88E6060 datasheet */
++							reg = <5>;
++							phy-mode = "rgmii-id";
++							ethernet = <&ethc>;
++							label = "cpu";
++							fixed-link {
++								speed = <100>;
++								full-duplex;
++							};
++						};
++					};
++				};
++			};
++		};
++
++		/* EthC LAN connected to the Marvell DSA Switch */
++		ethc: ethernet@c800a000 {
++			status = "okay";
++			queue-rx = <&qmgr 4>;
++			queue-txready = <&qmgr 21>;
++			phy-mode = "rgmii";
++			fixed-link {
++				speed = <100>;
++				full-duplex;
++			};
++		};
++	};
++};
diff --git a/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch b/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch
new file mode 100644
index 0000000000..93458bc2e8
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0004-ARM-dts-usr8200-Fix-phy-registers.patch
@@ -0,0 +1,69 @@
+From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 20 Oct 2023 15:11:41 +0200
+Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
+
+The MV88E6060 switch has internal PHY registers at MDIO
+addresses 0x00..0x04. Tie each port to the corresponding
+PHY.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -165,6 +165,24 @@
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 
++				/*
++				 * PHY 0..4 are internal to the MV88E6060 switch but appear
++				 * as independent devices.
++				 */
++				phy0: ethernet-phy@0 {
++					reg = <0>;
++				};
++				phy1: ethernet-phy@1 {
++					reg = <1>;
++				};
++				phy2: ethernet-phy@2 {
++					reg = <2>;
++				};
++				phy3: ethernet-phy@3 {
++					reg = <3>;
++				};
++
++				/* Altima AMI101L used by the WAN port */
+ 				phy9: ethernet-phy@9 {
+ 					reg = <9>;
+ 				};
+@@ -181,21 +199,25 @@
+ 						port@0 {
+ 							reg = <0>;
+ 							label = "lan1";
++							phy-handle = <&phy0>;
+ 						};
+ 
+ 						port@1 {
+ 							reg = <1>;
+ 							label = "lan2";
++							phy-handle = <&phy1>;
+ 						};
+ 
+ 						port@2 {
+ 							reg = <2>;
+ 							label = "lan3";
++							phy-handle = <&phy2>;
+ 						};
+ 
+ 						port@3 {
+ 							reg = <3>;
+ 							label = "lan4";
++							phy-handle = <&phy3>;
+ 						};
+ 
+ 						port@5 {
diff --git a/target/linux/ixp4xx/patches-6.6/0005-ARM-dts-ixp4xx-nslu2-Enable-write-on-flash.patch b/target/linux/ixp4xx/patches-6.6/0005-ARM-dts-ixp4xx-nslu2-Enable-write-on-flash.patch
new file mode 100644
index 0000000000..ccbd7ea77d
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0005-ARM-dts-ixp4xx-nslu2-Enable-write-on-flash.patch
@@ -0,0 +1,25 @@
+From 89eccb6726d93c9c78997e91bd641b0e46bc3c5f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:48 +0200
+Subject: [PATCH] ARM: dts: ixp4xx-nslu2: Enable write on flash
+
+To upgrade the firmware and similar, the flash needs write
+access.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -101,6 +101,8 @@
+ 			flash@0,0 {
+ 				compatible = "intel,ixp4xx-flash", "cfi-flash";
+ 				bank-width = <2>;
++				/* Enable writes on the expansion bus */
++				intel,ixp4xx-eb-write-enable = <1>;
+ 				/*
+ 				 * 8 MB of Flash in 0x20000 byte blocks
+ 				 * mapped in at CS0.
diff --git a/target/linux/ixp4xx/patches-6.6/0006-ARM-dts-ixp4xx-Use-right-restart-keycode.patch b/target/linux/ixp4xx/patches-6.6/0006-ARM-dts-ixp4xx-Use-right-restart-keycode.patch
new file mode 100644
index 0000000000..648c6efe2b
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/0006-ARM-dts-ixp4xx-Use-right-restart-keycode.patch
@@ -0,0 +1,62 @@
+From deb93908958e74dffbef1ce6a1cc2f82ac4f96ed Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:49 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Use right restart keycode
+
+The "reset" key on a few IXP4xx routers were sending KEY_ESC
+but what we want to send is KEY_RESTART which will make
+OpenWrt and similar userspace do a controlled reboot.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts  | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts  | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
+@@ -57,7 +57,7 @@
+ 
+ 		button-reset {
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ 		};
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
+@@ -44,7 +44,7 @@
+ 		};
+ 		button-reset {
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ 		};
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
+@@ -63,7 +63,7 @@
+ 		};
+ 		button-reset {
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ 		};
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -65,7 +65,7 @@
+ 		};
+ 		button-reset {
+ 			wakeup-source;
+-			linux,code = <KEY_ESC>;
++			linux,code = <KEY_RESTART>;
+ 			label = "reset";
+ 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ 		};
diff --git a/target/linux/ixp4xx/patches-6.6/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch b/target/linux/ixp4xx/patches-6.6/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch
new file mode 100644
index 0000000000..2a82ec0a2d
--- /dev/null
+++ b/target/linux/ixp4xx/patches-6.6/301-ARM-dts-ixp4xx-Boot-NSLU2-from-harddrive.patch
@@ -0,0 +1,24 @@
+From 6484f966af53447deefcd4b805c201d8624981cb Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 29 May 2023 23:32:44 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
+
+This enforces harddrive boot on the NSLU2. The flash is too small
+to hold any rootfs these days.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -21,7 +21,7 @@
+ 	};
+ 
+ 	chosen {
+-		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ 		stdout-path = "uart0:115200n8";
+ 	};
+ 
diff --git a/target/linux/kirkwood/base-files/etc/board.d/02_network b/target/linux/kirkwood/base-files/etc/board.d/02_network
index 3ed2fa94b0..ff7897fe13 100644
--- a/target/linux/kirkwood/base-files/etc/board.d/02_network
+++ b/target/linux/kirkwood/base-files/etc/board.d/02_network
@@ -19,6 +19,7 @@ kirkwood_setup_interfaces()
 	cloudengines,pogoe02|\
 	cloudengines,pogoplugv4|\
 	ctera,c200-v1|\
+	dlink,dns320l|\
 	globalscale,sheevaplug|\
 	iom,iconnect-1.1|\
 	iom,ix2-200|\
@@ -60,6 +61,9 @@ kirkwood_setup_macs()
 	local label_mac=""
 
 	case "$board" in
+	dlink,dns320l)
+		lan_mac=$(mtd_get_mac_text "mini firmware")
+		;;
 	iptime,nas1)
 		lan_mac=$(mtd_get_mac_binary u-boot 0x3ffa8)
 		label_mac=$lan_mac
diff --git a/target/linux/kirkwood/files-6.1/arch/arm/boot/dts/kirkwood-dns320l.dts b/target/linux/kirkwood/files-6.1/arch/arm/boot/dts/kirkwood-dns320l.dts
new file mode 100644
index 0000000000..bd86c04ea7
--- /dev/null
+++ b/target/linux/kirkwood/files-6.1/arch/arm/boot/dts/kirkwood-dns320l.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree file for DLINK DNS-320L
+ *
+ * Copyright (C) 2024, Zoltan HERPAI <wigyori@uid0.hu>
+ * Copyright (C) 2015, Sunke Schlüters <sunke-dev@schlueters.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This file is based on the works of:
+ * - Sunke Schlüters <sunke-dev@schlueters.de>
+ *   - https://github.com/scus1/dns320l/blob/master/kernel/dts/kirkwood-dns320l.dts
+ * - Andreas Böhler <dev@aboehler.at>:
+ *   - http://www.aboehler.at/doku/doku.php/projects:dns320l
+ *   - http://www.aboehler.at/hg/linux-dns320l/file/ba7a60ad7687/linux-3.12/kirkwood-dns320l.dts
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "D-Link DNS-320L";
+	compatible = "dlink,dns320l", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_buttons>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "Reset push button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 28 1>;
+		};
+
+		button@2 {
+			label = "USB unmount button";
+			linux,code = <KEY_EJECTCD>;
+			gpios = <&gpio0 27 1>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_leds>;
+		pinctrl-names = "default";
+
+		blue-usb {
+			label = "dns320l:usb:blue";
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usbport";
+		};
+
+		orange-usb {
+			label = "dns320l:usb:orange";
+			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+		};
+
+		orange-l-hdd {
+			label = "dns320l:orange:l_hdd";
+			gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+		};
+
+		orange-r-hdd {
+			label = "dns320l:orange:r_hdd";
+			gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	ocp@f1000000 {
+		sata@80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+		serial@12000 {
+			status = "okay";
+		};
+
+		serial@12100 {
+			pinctrl-0 = <&pmx_uart1>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_sata>;
+		pinctrl-names = "default";
+
+		sata_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 24 0>;
+		};
+	};
+};
+
+&nand {
+	pinctrl-0 = <&pmx_nand>;
+	pinctrl-names = "default";
+	chip-delay = <40>;
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+	};
+
+	partition@100000 {
+		label = "ubootenv";
+		reg = <0x100000 0x20000>;
+	};
+
+	partition@120000 {
+		label = "ubi";
+		reg = <0x120000 0x6de0000>;
+	};
+
+	partition@6f00000 {
+		label = "mini firmware";
+		reg = <0x6f00000 0xa00000>;
+	};
+
+	partition@7900000 {
+		label = "config";
+		reg = <0x7900000 0x500000>;
+	};
+
+	partition@7e00000 {
+		label = "my-dlink";
+		reg = <0x7e00000 0x200000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	pmx_sata1: pmx-sata1 {
+		marvell,pins = "mpp20";
+		marvell,function = "sata1";
+	};
+
+	pmx_sata0: pmx-sata0 {
+		marvell,pins = "mpp21";
+		marvell,function = "sata0";
+	};
+
+	pmx_power_sata: pmx-power-sata {
+		marvell,pins = "mpp24";
+		marvell,function = "gpio";
+	};
+
+	pmx_leds: pmx-leds {
+		marvell,pins = "mpp22", "mpp23", "mpp25", "mpp26";
+		marvell,function = "gpio";
+	};
+
+	pmx_buttons: pmx-buttons {
+		marvell,pins = "mpp27", "mpp28", "mpp29";
+		marvell,function = "gpio";
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/target/linux/kirkwood/files-6.6/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts b/target/linux/kirkwood/files-6.6/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
new file mode 100644
index 0000000000..bd86c04ea7
--- /dev/null
+++ b/target/linux/kirkwood/files-6.6/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree file for DLINK DNS-320L
+ *
+ * Copyright (C) 2024, Zoltan HERPAI <wigyori@uid0.hu>
+ * Copyright (C) 2015, Sunke Schlüters <sunke-dev@schlueters.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This file is based on the works of:
+ * - Sunke Schlüters <sunke-dev@schlueters.de>
+ *   - https://github.com/scus1/dns320l/blob/master/kernel/dts/kirkwood-dns320l.dts
+ * - Andreas Böhler <dev@aboehler.at>:
+ *   - http://www.aboehler.at/doku/doku.php/projects:dns320l
+ *   - http://www.aboehler.at/hg/linux-dns320l/file/ba7a60ad7687/linux-3.12/kirkwood-dns320l.dts
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "D-Link DNS-320L";
+	compatible = "dlink,dns320l", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_buttons>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "Reset push button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 28 1>;
+		};
+
+		button@2 {
+			label = "USB unmount button";
+			linux,code = <KEY_EJECTCD>;
+			gpios = <&gpio0 27 1>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_leds>;
+		pinctrl-names = "default";
+
+		blue-usb {
+			label = "dns320l:usb:blue";
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usbport";
+		};
+
+		orange-usb {
+			label = "dns320l:usb:orange";
+			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+		};
+
+		orange-l-hdd {
+			label = "dns320l:orange:l_hdd";
+			gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+		};
+
+		orange-r-hdd {
+			label = "dns320l:orange:r_hdd";
+			gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	ocp@f1000000 {
+		sata@80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+		serial@12000 {
+			status = "okay";
+		};
+
+		serial@12100 {
+			pinctrl-0 = <&pmx_uart1>;
+			pinctrl-names = "default";
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_sata>;
+		pinctrl-names = "default";
+
+		sata_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 24 0>;
+		};
+	};
+};
+
+&nand {
+	pinctrl-0 = <&pmx_nand>;
+	pinctrl-names = "default";
+	chip-delay = <40>;
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+	};
+
+	partition@100000 {
+		label = "ubootenv";
+		reg = <0x100000 0x20000>;
+	};
+
+	partition@120000 {
+		label = "ubi";
+		reg = <0x120000 0x6de0000>;
+	};
+
+	partition@6f00000 {
+		label = "mini firmware";
+		reg = <0x6f00000 0xa00000>;
+	};
+
+	partition@7900000 {
+		label = "config";
+		reg = <0x7900000 0x500000>;
+	};
+
+	partition@7e00000 {
+		label = "my-dlink";
+		reg = <0x7e00000 0x200000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&pinctrl {
+	pmx_sata1: pmx-sata1 {
+		marvell,pins = "mpp20";
+		marvell,function = "sata1";
+	};
+
+	pmx_sata0: pmx-sata0 {
+		marvell,pins = "mpp21";
+		marvell,function = "sata0";
+	};
+
+	pmx_power_sata: pmx-power-sata {
+		marvell,pins = "mpp24";
+		marvell,function = "gpio";
+	};
+
+	pmx_leds: pmx-leds {
+		marvell,pins = "mpp22", "mpp23", "mpp25", "mpp26";
+		marvell,function = "gpio";
+	};
+
+	pmx_buttons: pmx-buttons {
+		marvell,pins = "mpp27", "mpp28", "mpp29";
+		marvell,function = "gpio";
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/target/linux/kirkwood/image/Makefile b/target/linux/kirkwood/image/Makefile
index cc13648890..2bd2f64159 100644
--- a/target/linux/kirkwood/image/Makefile
+++ b/target/linux/kirkwood/image/Makefile
@@ -182,6 +182,14 @@ define Device/ctera_c200-v1
 endef
 TARGET_DEVICES += ctera_c200-v1
 
+define Device/dlink_dns320l
+  DEVICE_VENDOR := D-Link
+  DEVICE_MODEL := DNS-320L
+  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-gpio-button-hotplug \
+	kmod-usb-storage kmod-usb-ledtrig-usbport dns320l-mcu kmod-rtc-mv
+endef
+TARGET_DEVICES += dlink_dns320l
+
 define Device/endian_4i-edge-200
   DEVICE_VENDOR := Endian
   DEVICE_MODEL := 4i Edge 200
@@ -378,7 +386,8 @@ TARGET_DEVICES += zyxel_nsa310b
 define Device/zyxel_nsa310s
   DEVICE_VENDOR := ZyXEL
   DEVICE_MODEL := NSA310S
-  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-gpio-button-hotplug
+  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \
+	kmod-gpio-button-hotplug kmod-rtc-mv
 endef
 TARGET_DEVICES += zyxel_nsa310s
 
diff --git a/target/linux/kirkwood/patches-6.1/005-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch b/target/linux/kirkwood/patches-6.1/005-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch
deleted file mode 100644
index cd838394d9..0000000000
--- a/target/linux/kirkwood/patches-6.1/005-6.7-net-dsa-mv88e6xxx-fix-marvell-6350-switch-probing.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
-From: Greg Ungerer <gerg@kernel.org>
-Date: Fri, 24 Nov 2023 14:15:28 +1000
-Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
-
-As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
-be filled") Marvell 88e6350 switches fail to be probed:
-
-    ...
-    mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
-    mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
-    error creating PHYLINK: -22
-    mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
-    ...
-
-The problem stems from the use of mv88e6185_phylink_get_caps() to get
-the device capabilities. Create a new dedicated phylink_get_caps for the
-6351 family (which the 6350 is one of) to properly support their set of
-capabilities.
-
-According to chip.h the 6351 switch family includes the 6171, 6175, 6350
-and 6351 switches, so update each of these to use the correct
-phylink_get_caps.
-
-Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
-Signed-off-by: Greg Ungerer <gerg@kernel.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mv88e6xxx/chip.c
-+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
- 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
- }
- 
-+static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
-+				       struct phylink_config *config)
-+{
-+	unsigned long *supported = config->supported_interfaces;
-+
-+	/* Translate the default cmode */
-+	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-+
-+	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
-+				   MAC_1000FD;
-+}
-+
- static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
- {
- 	u16 reg, val;
-@@ -4498,7 +4510,7 @@ static const struct mv88e6xxx_ops mv88e6
- 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- 	.stu_getnext = mv88e6352_g1_stu_getnext,
- 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
--	.phylink_get_caps = mv88e6185_phylink_get_caps,
-+	.phylink_get_caps = mv88e6351_phylink_get_caps,
- };
- 
- static const struct mv88e6xxx_ops mv88e6172_ops = {
-@@ -4599,7 +4611,7 @@ static const struct mv88e6xxx_ops mv88e6
- 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- 	.stu_getnext = mv88e6352_g1_stu_getnext,
- 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
--	.phylink_get_caps = mv88e6185_phylink_get_caps,
-+	.phylink_get_caps = mv88e6351_phylink_get_caps,
- };
- 
- static const struct mv88e6xxx_ops mv88e6176_ops = {
-@@ -5256,7 +5268,7 @@ static const struct mv88e6xxx_ops mv88e6
- 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- 	.stu_getnext = mv88e6352_g1_stu_getnext,
- 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
--	.phylink_get_caps = mv88e6185_phylink_get_caps,
-+	.phylink_get_caps = mv88e6351_phylink_get_caps,
- };
- 
- static const struct mv88e6xxx_ops mv88e6351_ops = {
-@@ -5302,7 +5314,7 @@ static const struct mv88e6xxx_ops mv88e6
- 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
- 	.avb_ops = &mv88e6352_avb_ops,
- 	.ptp_ops = &mv88e6352_ptp_ops,
--	.phylink_get_caps = mv88e6185_phylink_get_caps,
-+	.phylink_get_caps = mv88e6351_phylink_get_caps,
- };
- 
- static const struct mv88e6xxx_ops mv88e6352_ops = {
diff --git a/target/linux/kirkwood/patches-6.1/118-dns-320l.patch b/target/linux/kirkwood/patches-6.1/118-dns-320l.patch
new file mode 100644
index 0000000000..d6c84e2c59
--- /dev/null
+++ b/target/linux/kirkwood/patches-6.1/118-dns-320l.patch
@@ -0,0 +1,35 @@
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -310,6 +310,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
+ 	kirkwood-db-88f6282.dtb \
+ 	kirkwood-dir665.dtb \
+ 	kirkwood-dns320.dtb \
++	kirkwood-dns320l.dtb \
+ 	kirkwood-dns325.dtb \
+ 	kirkwood-dockstar.dtb \
+ 	kirkwood-dreamplug.dtb \
+--- a/arch/arm/boot/dts/kirkwood-dns320l.dts
++++ b/arch/arm/boot/dts/kirkwood-dns320l.dts
+@@ -32,6 +32,13 @@
+ 		reg = <0x00000000 0x10000000>;
+ 	};
+ 
++	aliases {
++		led-boot = &led_orange_usb;
++		led-failsafe = &led_orange_usb;
++		led-running = &led_orange_usb;
++		led-upgrade = &led_orange_usb;
++	};
++
+ 	chosen {
+ 		bootargs = "console=ttyS0,115200n8 earlyprintk";
+ 		stdout-path = &uart0;
+@@ -68,7 +75,7 @@
+ 			linux,default-trigger = "usbport";
+ 		};
+ 
+-		orange-usb {
++		led_orange_usb: orange-usb {
+ 			label = "dns320l:usb:orange";
+ 			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ 		};
diff --git a/target/linux/kirkwood/patches-6.6/118-dns-320l.patch b/target/linux/kirkwood/patches-6.6/118-dns-320l.patch
new file mode 100644
index 0000000000..8f19441bbe
--- /dev/null
+++ b/target/linux/kirkwood/patches-6.6/118-dns-320l.patch
@@ -0,0 +1,35 @@
+--- a/arch/arm/boot/dts/marvell/Makefile
++++ b/arch/arm/boot/dts/marvell/Makefile
+@@ -92,6 +92,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
+ 	kirkwood-db-88f6282.dtb \
+ 	kirkwood-dir665.dtb \
+ 	kirkwood-dns320.dtb \
++	kirkwood-dns320l.dtb \
+ 	kirkwood-dns325.dtb \
+ 	kirkwood-dockstar.dtb \
+ 	kirkwood-dreamplug.dtb \
+--- a/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
++++ b/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
+@@ -32,6 +32,13 @@
+ 		reg = <0x00000000 0x10000000>;
+ 	};
+ 
++	aliases {
++		led-boot = &led_orange_usb;
++		led-failsafe = &led_orange_usb;
++		led-running = &led_orange_usb;
++		led-upgrade = &led_orange_usb;
++	};
++
+ 	chosen {
+ 		bootargs = "console=ttyS0,115200n8 earlyprintk";
+ 		stdout-path = &uart0;
+@@ -68,7 +75,7 @@
+ 			linux,default-trigger = "usbport";
+ 		};
+ 
+-		orange-usb {
++		led_orange_usb: orange-usb {
+ 			label = "dns320l:usb:orange";
+ 			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ 		};
diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile
index 2e166a5f37..3474ebe462 100644
--- a/target/linux/lantiq/Makefile
+++ b/target/linux/lantiq/Makefile
@@ -9,7 +9,8 @@ BOARDNAME:=Lantiq
 FEATURES:=squashfs
 SUBTARGETS:=xrx200 xway xway_legacy falcon ase
 
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for Lantiq SoC
diff --git a/target/linux/lantiq/ase/config-5.15 b/target/linux/lantiq/ase/config-5.15
index 195e49df69..c4d8e575eb 100644
--- a/target/linux/lantiq/ase/config-5.15
+++ b/target/linux/lantiq/ase/config-5.15
@@ -3,7 +3,6 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 CONFIG_CPU_MIPSR1=y
 CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_FIRMWARE_MEMMAP=y
 CONFIG_GENERIC_ALLOCATOR=y
@@ -15,7 +14,7 @@ CONFIG_LANTIQ_ETOP=y
 CONFIG_NLS=y
 CONFIG_SGL_ALLOC=y
 CONFIG_SOC_AMAZON_SE=y
-CONFIG_SOC_TYPE_XWAY=y
+# CONFIG_SOC_XWAY is not set
 CONFIG_SWCONFIG=y
 CONFIG_TARGET_ISA_REV=1
 CONFIG_USB=y
diff --git a/target/linux/lantiq/ase/config-6.1 b/target/linux/lantiq/ase/config-6.1
new file mode 100644
index 0000000000..c4d8e575eb
--- /dev/null
+++ b/target/linux/lantiq/ase/config-6.1
@@ -0,0 +1,24 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_HW_RANDOM=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_NLS=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AMAZON_SE=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SWCONFIG=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/lantiq/ase/config-6.6 b/target/linux/lantiq/ase/config-6.6
new file mode 100644
index 0000000000..c4d8e575eb
--- /dev/null
+++ b/target/linux/lantiq/ase/config-6.6
@@ -0,0 +1,24 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_HW_RANDOM=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_NLS=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AMAZON_SE=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SWCONFIG=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/lantiq/config-5.15 b/target/linux/lantiq/config-5.15
index 90d48fff04..39862948e2 100644
--- a/target/linux/lantiq/config-5.15
+++ b/target/linux/lantiq/config-5.15
@@ -1,30 +1,15 @@
 CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
-CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
-CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_ARCH_MMAP_RND_BITS_MAX=15
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CPU_BIG_ENDIAN=y
 CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_LOAD_STORE_LR=y
+CONFIG_CPU_HAS_DIEI=y
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_RIXI=y
 CONFIG_CPU_HAS_SYNC=y
@@ -32,6 +17,7 @@ CONFIG_CPU_MIPS32=y
 # CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
@@ -42,20 +28,18 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CSRC_R4K=y
 CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
 CONFIG_DTC=y
 # CONFIG_DT_EASY50712 is not set
 CONFIG_EARLY_PRINTK=y
-CONFIG_EFI_EARLYCON=y
 CONFIG_FIXED_PHY=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
 CONFIG_GENERIC_IOMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
@@ -71,6 +55,7 @@ CONFIG_GENERIC_PHY=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_MM_LANTIQ=y
 CONFIG_GPIO_STP_XWAY=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
@@ -78,46 +63,10 @@ CONFIG_HARDWARE_WATCHPOINTS=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PCI=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
 CONFIG_HZ_PERIODIC=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_MIPS_CPU=y
 CONFIG_IRQ_WORK=y
@@ -139,19 +88,16 @@ CONFIG_MIGRATION=y
 CONFIG_MIPS=y
 CONFIG_MIPS_ASID_BITS=8
 CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CBPF_JIT=y
 CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
 # CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
 CONFIG_MIPS_CMDLINE_FROM_DTB=y
-# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+CONFIG_MIPS_EBPF_JIT=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 CONFIG_MIPS_LD_CAN_LINK_VDSO=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_NO_APPENDED_DTB is not set
 CONFIG_MIPS_RAW_APPENDED_DTB=y
 CONFIG_MIPS_SPRAM=y
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
@@ -166,8 +112,10 @@ CONFIG_MTD_SPLIT_TPLINK_FW=y
 CONFIG_MTD_SPLIT_UIMAGE_FW=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_SELFTESTS=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@@ -176,8 +124,6 @@ CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-# CONFIG_PCIE_LANTIQ is not set
 CONFIG_PCI_DRIVERS_LEGACY=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
@@ -190,6 +136,7 @@ CONFIG_PINCTRL_LANTIQ=y
 CONFIG_PINCTRL_XWAY=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_RESET_CONTROLLER=y
@@ -199,7 +146,8 @@ CONFIG_SERIAL_LANTIQ=y
 CONFIG_SERIAL_LANTIQ_CONSOLE=y
 # CONFIG_SOC_AMAZON_SE is not set
 # CONFIG_SOC_FALCON is not set
-# CONFIG_SOC_XWAY is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
 CONFIG_SPI=y
 CONFIG_SPI_LANTIQ_SSC=y
 CONFIG_SPI_MASTER=y
diff --git a/target/linux/lantiq/config-6.1 b/target/linux/lantiq/config-6.1
new file mode 100644
index 0000000000..e037a63068
--- /dev/null
+++ b/target/linux/lantiq/config-6.1
@@ -0,0 +1,182 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_EASY50712 is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_MM_LANTIQ=y
+CONFIG_GPIO_STP_XWAY=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LANTIQ=y
+CONFIG_LANTIQ_DT_NONE=y
+# CONFIG_LANTIQ_ETOP is not set
+CONFIG_LANTIQ_WDT=y
+# CONFIG_LANTIQ_XRX200 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHY_LANTIQ_RCU_USB2=y
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LANTIQ=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_XWAY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_LANTIQ=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_SERIAL_LANTIQ_CONSOLE=y
+# CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_FALCON is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
+CONFIG_SPI=y
+CONFIG_SPI_LANTIQ_SSC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
diff --git a/target/linux/lantiq/config-6.6 b/target/linux/lantiq/config-6.6
new file mode 100644
index 0000000000..1890d82ff8
--- /dev/null
+++ b/target/linux/lantiq/config-6.6
@@ -0,0 +1,190 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_EASY50712 is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_MM_LANTIQ=y
+CONFIG_GPIO_STP_XWAY=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LANTIQ=y
+CONFIG_LANTIQ_DT_NONE=y
+# CONFIG_LANTIQ_ETOP is not set
+CONFIG_LANTIQ_WDT=y
+# CONFIG_LANTIQ_XRX200 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_GPIO_MM_GPIOCHIP=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHY_LANTIQ_RCU_USB2=y
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LANTIQ=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_XWAY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_LANTIQ=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_SERIAL_LANTIQ_CONSOLE=y
+# CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_FALCON is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
+CONFIG_SPI=y
+CONFIG_SPI_LANTIQ_SSC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
diff --git a/target/linux/lantiq/falcon/config-5.15 b/target/linux/lantiq/falcon/config-5.15
index 3041c65dbd..d5c5c61505 100644
--- a/target/linux/lantiq/falcon/config-5.15
+++ b/target/linux/lantiq/falcon/config-5.15
@@ -1,4 +1,3 @@
-CONFIG_CPU_HAS_DIEI=y
 CONFIG_MTD_NAND_CORE=y
 CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND_ECC_SW_HAMMING=y
@@ -6,4 +5,5 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
 CONFIG_PINCTRL_FALCON=y
 CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
 CONFIG_SPI_FALCON=y
diff --git a/target/linux/lantiq/falcon/config-6.1 b/target/linux/lantiq/falcon/config-6.1
new file mode 100644
index 0000000000..d5c5c61505
--- /dev/null
+++ b/target/linux/lantiq/falcon/config-6.1
@@ -0,0 +1,9 @@
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_PINCTRL_FALCON=y
+CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SPI_FALCON=y
diff --git a/target/linux/lantiq/falcon/config-6.6 b/target/linux/lantiq/falcon/config-6.6
new file mode 100644
index 0000000000..d5c5c61505
--- /dev/null
+++ b/target/linux/lantiq/falcon/config-6.6
@@ -0,0 +1,9 @@
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_PINCTRL_FALCON=y
+CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SPI_FALCON=y
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi
index 5c608dab63..6ae7ab6188 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi
@@ -197,7 +197,7 @@
 			compatible = "lantiq,mei-xway";
 			reg = <0xe116000 0x400>;
 			interrupt-parent = <&icu0>;
-			interrupts = <81>;
+			interrupts = <81 83 92>;
 		};
 
 		usb: usb@e101000 {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi
index b12005ff6b..789ca67002 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi
@@ -376,7 +376,7 @@
 			compatible = "lantiq,mei-xway";
 			reg = <0xe116000 0x9c>;
 			interrupt-parent = <&icu0>;
-			interrupts = <63>;
+			interrupts = <63 61 68>;
 		};
 
 		gsw: etop@e180000 {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi
index c19ce2af7e..5fe6699ac2 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi
@@ -291,7 +291,7 @@
 			compatible = "lantiq,mei-xway";
 			reg = <0xe116000 0x400>;
 			interrupt-parent = <&icu0>;
-			interrupts = <63>;
+			interrupts = <63 61 159>;
 		};
 
 		gsw: etop@e180000 {
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
index e4c9be8f87..e0e49f377a 100644
--- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
+++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
@@ -528,7 +528,7 @@
 			reg = <0xd900000 0x1000>;
 
 			interrupt-parent = <&icu0>;
-			interrupts = <161 144>;
+			interrupts = <161 144 145 146 147>;
 
 			phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
 			phy-names = "pcie";
diff --git a/target/linux/lantiq/image/vr9.mk b/target/linux/lantiq/image/vr9.mk
index a9df6598d7..dc307e1ee4 100644
--- a/target/linux/lantiq/image/vr9.mk
+++ b/target/linux/lantiq/image/vr9.mk
@@ -377,6 +377,7 @@ define Device/zyxel_p-2812hnu-f1
   DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-mbedtls kmod-usb-dwc2 kmod-usb-ledtrig-usbport
   KERNEL_SIZE := 3072k
   SUPPORTED_DEVICES += P2812HNUF1
+  DEFAULT := n
 endef
 TARGET_DEVICES += zyxel_p-2812hnu-f1
 
diff --git a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch
index 16b87ed0a5..3e6c267685 100644
--- a/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch
+++ b/target/linux/lantiq/patches-5.15/0008-MIPS-lantiq-backport-old-timer-code.patch
@@ -186,7 +186,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-y += vmmc.o
 --- /dev/null
 +++ b/arch/mips/lantiq/xway/timer.c
-@@ -0,0 +1,852 @@
+@@ -0,0 +1,887 @@
 +#ifndef CONFIG_SOC_AMAZON_SE
 +
 +#include <linux/kernel.h>
@@ -203,6 +203,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/sched.h>
 +#include <linux/sched/signal.h>
 +
++#include <linux/of_platform.h>
++
 +#include <asm/irq.h>
 +#include <asm/div64.h>
 +#include "../clk.h"
@@ -978,10 +980,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
-+int __init lq_gptu_init(void)
++static int gptu_probe(struct platform_device *pdev)
 +{
 +	int ret;
-+	unsigned int i;
++	int i;
 +
 +	ltq_w32(0, LQ_GPTU_IRNEN);
 +	ltq_w32(0xfff, LQ_GPTU_IRNCR);
@@ -1005,15 +1007,24 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	}
 +
 +	for (i = 0; i < timer_dev.number_of_timers; i++) {
-+		ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
-+		if (ret) {
-+			for (; i >= 0; i--)
-+				free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
++		int irq = platform_get_irq(pdev, i);
++		if (irq < 0) {
++			printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 +			misc_deregister(&gptu_miscdev);
++			return irq;
++		}
++
++		ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
++		if (ret) {
 +			printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++			misc_deregister(&gptu_miscdev);
 +			return ret;
 +		} else {
-+			timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
++			timer_dev.timer[i].irq = irq;
 +			disable_irq(timer_dev.timer[i].irq);
 +			printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 +		}
@@ -1022,6 +1033,30 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
++static const struct of_device_id gptu_match[] = {
++	{ .compatible = "lantiq,gptu-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gptu_match);
++
++static struct platform_driver gptu_driver = {
++	.probe = gptu_probe,
++	.driver = {
++		.name = "gptu-xway",
++		.owner = THIS_MODULE,
++		.of_match_table = gptu_match,
++	},
++};
++
++int __init lq_gptu_init(void)
++{
++	int ret = platform_driver_register(&gptu_driver);
++
++	if (ret)
++		pr_info("gptu: Error registering platform driver\n");
++	return ret;
++}
++
 +void __exit lq_gptu_exit(void)
 +{
 +	unsigned int i;
diff --git a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
index a11ec3ec98..93108cac3a 100644
--- a/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
+++ b/target/linux/lantiq/patches-5.15/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -39,7 +39,19 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  #include "ifxmips_pcie.h"
  #include "ifxmips_pcie_reg.h"
  
-@@ -40,6 +47,11 @@
+@@ -25,11 +32,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+ 
+-#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +42,30 @@
  static DEFINE_SPINLOCK(ifx_pcie_lock);
  
  u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
@@ -51,7 +63,31 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
      {
-@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ...
+         .ir_irq = {
+-            .irq  = IFX_PCIE_IR,
+             .name = "ifx_pcie_rc0",
+         },
+ 
+         .legacy_irq = {
+             {
+                 .irq_bit = PCIE_IRN_INTA,
+-                .irq     = IFX_PCIE_INTA,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTB,
+-                .irq     = IFX_PCIE_INTB,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTC,
+-                .irq     = IFX_PCIE_INTC,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTD,
+-                .irq     = IFX_PCIE_INTD,
+             },
+         },
+     },
+@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
  	printk("%s", buf);
  }
  
@@ -74,7 +110,17 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  static inline int pcie_ltssm_enable(int pcie_port)
  {
-@@ -988,10 +1016,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
+@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+ 	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ 		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ 	if (ret)
+-		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++		printk(KERN_ERR "%s request irq %d failed\n", __func__,
++		       pcie_irqs[pcie_port].ir_irq.irq);
+ 
+ 	return ret;
+ }
+@@ -988,10 +1007,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
  static int
  pcie_rc_initialize(int pcie_port)
  {
@@ -103,7 +149,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  	pcie_ep_gpio_rst_init(pcie_port);
  
-@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
  	* reset PCIe PHY will solve this issue 
  	*/
  	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
@@ -140,7 +186,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  
  		/* Enable PCIe PHY and Clock */
  		pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
  		/* Once link is up, break out */
  		if (pcie_app_loigc_setup(pcie_port) == 0)
  			break;
@@ -151,7 +197,7 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  	}
  	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
  		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
  	return 0;
  }
  
@@ -193,10 +239,9 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
 -    
 +
 +    ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
-+    if (IS_ERR(ltq_pcie_phy)) {
-+        dev_err(&pdev->dev, "failed to get the PCIe PHY\n");
-+        return PTR_ERR(ltq_pcie_phy);
-+    }
++    if (IS_ERR(ltq_pcie_phy))
++        return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++                             "failed to get the PCIe PHY\n");
 +
 +    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
 +    if (IS_ERR(ltq_pcie_reset)) {
@@ -228,15 +273,27 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
      for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
  	if (pcie_rc_initialize(pcie_port) == 0) {
  	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
-@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+                 IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
                  return -ENOMEM;
              }
++            pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++            if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++                return pcie_irqs[pcie_port].ir_irq.irq;
++
++            for (int i = 0; i <= 3; i++){
++                pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++                if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++                    return pcie_irqs[pcie_port].legacy_irq[i].irq;
++            }
++
              ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
 +            pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
  
              register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
              /* XXX, clear error status */
-@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi
  
      return 0;
  }
@@ -409,3 +466,21 @@ Signed-off-by: Eddi De Pieri <eddi@depieri.net>
  static inline void pcie_core_pmu_setup(int pcie_port)
  {
  	struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+ 
+ typedef struct ifx_pcie_ir_irq {
+-    const unsigned int irq;
++    unsigned int irq;
+     const char name[16];
+ }ifx_pcie_ir_irq_t;
+ 
+ typedef struct ifx_pcie_legacy_irq{
+     const u32 irq_bit;
+-    const int irq;
++    int irq;
+ }ifx_pcie_legacy_irq_t;
+ 
+ typedef struct ifx_pcie_irq {
diff --git a/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
new file mode 100644
index 0000000000..472a24e66b
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
@@ -0,0 +1,97 @@
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -13,6 +13,10 @@
+ 
+ static unsigned int *cp1_base;
+ 
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ 	if (!cp1_base)
+@@ -22,16 +26,65 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+ 
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++	if (!ad0_irq)
++		panic("no ad0 irq was set\n");
++
++	return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++	if (!ad1_irq)
++		panic("no ad1 irq was set\n");
++
++	return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++	if (!vc_irq[idx])
++		panic("no vc%d irq was set\n", idx);
++
++	return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE       (1 << 20)
+ 	int gpio_count;
+ 	dma_addr_t dma;
++	int i;
+ 
+ 	cp1_base =
+ 		(void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ 						    &dma, GFP_KERNEL));
+ 
++	ad0_irq = platform_get_irq(pdev, 4);
++	if (ad0_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++		return ad0_irq;
++	}
++
++	ad1_irq = platform_get_irq(pdev, 5);
++	if (ad1_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++		return ad1_irq;
++	}
++
++	for (i = 0; i < 4; i++) {
++	vc_irq[i] = platform_get_irq(pdev, i);
++		if (vc_irq[i] < 0) {
++			dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++				i, vc_irq[i]);
++			return vc_irq[i];
++		}
++	}
++
+ 	gpio_count = of_gpio_count(pdev->dev.of_node);
+ 	while (gpio_count > 0) {
+ 		enum of_gpio_flags flags;
diff --git a/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch b/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
new file mode 100644
index 0000000000..c6befe05e5
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
@@ -0,0 +1,32 @@
+From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:52:25 +0200
+Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing
+ phy-mode and fixed-link
+
+The CPU port has to specify a phy-mode and either a phy or a fixed-link.
+Since GSWIP is connected using a SoC internal protocol there's no PHY
+involved. Add phy-mode = "internal" and a fixed-link to describe the
+communication between the PMAC (Ethernet controller) and GSWIP switch.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+@@ -97,7 +97,13 @@ switch@e108000 {
+ 		port@6 {
+ 			reg = <0x6>;
+ 			label = "cpu";
++			phy-mode = "internal";
+ 			ethernet = <&eth0>;
++
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch b/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
new file mode 100644
index 0000000000..cc94a41cf3
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
@@ -0,0 +1,33 @@
+From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:59:35 +0200
+Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode =
+ "internal" on the CPU port
+
+Add the CPU port to gswip_xrx200_phylink_get_caps() and
+gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus,
+so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1513,6 +1513,7 @@ static void gswip_xrx200_phylink_validat
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ 			goto unsupported;
+ 		break;
+@@ -1552,6 +1553,7 @@ static void gswip_xrx300_phylink_validat
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ 			goto unsupported;
+ 		break;
diff --git a/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch b/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
new file mode 100644
index 0000000000..b1658e15d8
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
@@ -0,0 +1,145 @@
+From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 31 Jul 2022 22:54:52 +0200
+Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where
+ appropriate
+
+dev_err_probe() can be used to simplify the existing code. Also it means
+we get rid of the following warning which is seen whenever the PMAC
+(Ethernet controller which connects to GSWIP's CPU port) has not been
+probed yet:
+  gswip 1e108000.switch: dsa switch register failed: -517
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------
+ 1 file changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1939,11 +1939,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 	msleep(200);
+ 
+ 	ret = request_firmware(&fw, gphy_fw->fw_name, dev);
+-	if (ret) {
+-		dev_err(dev, "failed to load firmware: %s, error: %i\n",
+-			gphy_fw->fw_name, ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
++				     gphy_fw->fw_name);
+ 
+ 	/* GPHY cores need the firmware code in a persistent and contiguous
+ 	 * memory area with a 16 kB boundary aligned start address.
+@@ -1956,9 +1954,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 		dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ 		memcpy(fw_addr, fw->data, fw->size);
+ 	} else {
+-		dev_err(dev, "failed to alloc firmware memory\n");
+ 		release_firmware(fw);
+-		return -ENOMEM;
++		return dev_err_probe(dev, -ENOMEM,
++				     "failed to alloc firmware memory\n");
+ 	}
+ 
+ 	release_firmware(fw);
+@@ -1985,8 +1983,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 
+ 	gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
+ 	if (IS_ERR(gphy_fw->clk_gate)) {
+-		dev_err(dev, "Failed to lookup gate clock\n");
+-		return PTR_ERR(gphy_fw->clk_gate);
++		return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
++				     "Failed to lookup gate clock\n");
+ 	}
+ 
+ 	ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
+@@ -2006,8 +2004,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 		gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
+ 		break;
+ 	default:
+-		dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+-		return -EINVAL;
++		return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
++				     gphy_mode);
+ 	}
+ 
+ 	gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
+@@ -2060,8 +2058,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 			priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ 			break;
+ 		default:
+-			dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-			return -ENOENT;
++			return dev_err_probe(dev, -ENOENT,
++					     "unknown GSWIP version: 0x%x",
++					     version);
+ 		}
+ 	}
+ 
+@@ -2069,10 +2068,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 	if (match && match->data)
+ 		priv->gphy_fw_name_cfg = match->data;
+ 
+-	if (!priv->gphy_fw_name_cfg) {
+-		dev_err(dev, "GPHY compatible type not supported");
+-		return -ENOENT;
+-	}
++	if (!priv->gphy_fw_name_cfg)
++		return dev_err_probe(dev, -ENOENT,
++				     "GPHY compatible type not supported");
+ 
+ 	priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
+ 	if (!priv->num_gphy_fw)
+@@ -2171,8 +2169,8 @@ static int gswip_probe(struct platform_d
+ 			return -EINVAL;
+ 		break;
+ 	default:
+-		dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-		return -ENOENT;
++		return dev_err_probe(dev, -ENOENT,
++				     "unknown GSWIP version: 0x%x", version);
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2180,10 +2178,9 @@ static int gswip_probe(struct platform_d
+ 	if (gphy_fw_np) {
+ 		err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
+ 		of_node_put(gphy_fw_np);
+-		if (err) {
+-			dev_err(dev, "gphy fw probe failed\n");
+-			return err;
+-		}
++		if (err)
++			return dev_err_probe(dev, err,
++					     "gphy fw probe failed\n");
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2191,20 +2188,20 @@ static int gswip_probe(struct platform_d
+ 	if (mdio_np) {
+ 		err = gswip_mdio(priv, mdio_np);
+ 		if (err) {
+-			dev_err(dev, "mdio probe failed\n");
++			dev_err_probe(dev, err, "mdio probe failed\n");
+ 			goto put_mdio_node;
+ 		}
+ 	}
+ 
+ 	err = dsa_register_switch(priv->ds);
+ 	if (err) {
+-		dev_err(dev, "dsa switch register failed: %i\n", err);
++		dev_err_probe(dev, err, "dsa switch registration failed\n");
+ 		goto mdio_bus;
+ 	}
+ 	if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
+-		dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
+-			priv->hw_info->cpu_port);
+-		err = -EINVAL;
++		err = dev_err_probe(dev, -EINVAL,
++				    "wrong CPU port defined, HW only supports port: %i",
++				    priv->hw_info->cpu_port);
+ 		goto disable_switch;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch b/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
new file mode 100644
index 0000000000..1493826c53
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
@@ -0,0 +1,25 @@
+From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 28 Jul 2022 22:37:11 +0200
+Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call
+ gswip_port_enable()
+
+We don't need to manually call gswip_port_enable() from within
+gswip_setup() for the CPU port. DSA does this automatically for us.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -874,8 +874,6 @@ static int gswip_setup(struct dsa_switch
+ 
+ 	ds->mtu_enforcement_ingress = true;
+ 
+-	gswip_port_enable(ds, cpu_port, NULL);
+-
+ 	ds->configure_vlan_while_not_filtering = false;
+ 
+ 	return 0;
diff --git a/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch b/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
new file mode 100644
index 0000000000..2d95b37358
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
@@ -0,0 +1,70 @@
+From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Fri, 10 May 2024 13:52:10 +0200
+Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port
+
+Before commit 74be4babe72f ("net: dsa: do not enable or disable non user
+ports"), gswip_port_enable/disable() were also executed for the cpu port
+in gswip_setup() which disabled the cpu port during initialization.
+
+Let's restore this by removing the dsa_is_user_port checks. Also, let's
+clean up the gswip_port_enable() function so that we only have to check
+for the cpu port once.
+
+Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports")
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ drivers/net/dsa/lantiq_gswip.c | 24 ++++++++----------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -671,13 +671,18 @@ static int gswip_port_enable(struct dsa_
+ 	struct gswip_priv *priv = ds->priv;
+ 	int err;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return 0;
+-
+ 	if (!dsa_is_cpu_port(ds, port)) {
++		u32 mdio_phy = 0;
++
+ 		err = gswip_add_single_port_br(priv, port, true);
+ 		if (err)
+ 			return err;
++
++		if (phydev)
++			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
++
++		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
++				GSWIP_MDIO_PHYp(port));
+ 	}
+ 
+ 	/* RMON Counter Enable for port */
+@@ -690,16 +695,6 @@ static int gswip_port_enable(struct dsa_
+ 	gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
+ 			  GSWIP_SDMA_PCTRLp(port));
+ 
+-	if (!dsa_is_cpu_port(ds, port)) {
+-		u32 mdio_phy = 0;
+-
+-		if (phydev)
+-			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
+-
+-		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
+-				GSWIP_MDIO_PHYp(port));
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -707,9 +702,6 @@ static void gswip_port_disable(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return;
+-
+ 	gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
+ 			  GSWIP_FDMA_PCTRLp(port));
+ 	gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
diff --git a/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch b/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
new file mode 100644
index 0000000000..26f7c0f414
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
@@ -0,0 +1,30 @@
+From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 18 May 2022 23:53:09 +0200
+Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in
+ gswip_port_change_mtu()
+
+Make the check for the CPU port in gswip_port_change_mtu() consistent
+with other areas of the driver by using dsa_is_cpu_port().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1463,12 +1463,11 @@ static int gswip_port_max_mtu(struct dsa
+ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ 	struct gswip_priv *priv = ds->priv;
+-	int cpu_port = priv->hw_info->cpu_port;
+ 
+ 	/* CPU port always has maximum mtu of user ports, so use it to set
+ 	 * switch frame size, including 8 byte special header.
+ 	 */
+-	if (port == cpu_port) {
++	if (dsa_is_cpu_port(ds, port)) {
+ 		new_mtu += 8;
+ 		gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
+ 			       GSWIP_MAC_FLEN);
diff --git a/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch b/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
new file mode 100644
index 0000000000..0a17d14759
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
@@ -0,0 +1,24 @@
+From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 17 May 2022 22:39:58 +0200
+Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN
+
+The addr variable in gswip_port_fdb_dump() stores a mac address. Use
+ETH_ALEN to make this consistent across other drivers.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1383,7 +1383,7 @@ static int gswip_port_fdb_dump(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 	struct gswip_pce_table_entry mac_bridge = {0,};
+-	unsigned char addr[6];
++	unsigned char addr[ETH_ALEN];
+ 	int i;
+ 	int err;
+ 
diff --git a/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch b/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
new file mode 100644
index 0000000000..87382876c2
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
@@ -0,0 +1,47 @@
+From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 21:23:49 +0200
+Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for
+ the mac bridge table
+
+Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout
+the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT()
+macro. This makes the driver code easier to understand.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -236,7 +236,8 @@
+ #define GSWIP_TABLE_ACTIVE_VLAN		0x01
+ #define GSWIP_TABLE_VLAN_MAPPING	0x02
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+-#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	0x01	/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1279,7 +1280,8 @@ static void gswip_port_fast_age(struct d
+ 		if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
+ 			continue;
+ 
+-		if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
++		if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++				      mac_bridge.val[0]))
+ 			continue;
+ 
+ 		mac_bridge.valid = false;
+@@ -1414,7 +1416,8 @@ static int gswip_port_fdb_dump(struct ds
+ 					return err;
+ 			}
+ 		} else {
+-			if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
++			if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++					      mac_bridge.val[0])) {
+ 				err = cb(addr, 0, false, data);
+ 				if (err)
+ 					return err;
diff --git a/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch b/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
new file mode 100644
index 0000000000..aafea1ec2e
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
@@ -0,0 +1,26 @@
+From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:24:24 +0200
+Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid
+ gswip_add_single_port_br on the CPU port
+
+Calling gswip_add_single_port_br() with the CPU port would be a bug
+because then only the CPU port could talk to itself. Add the CPU port to
+the validation at the beginning of gswip_add_single_port_br().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -633,7 +633,7 @@ static int gswip_add_single_port_br(stru
+ 	unsigned int max_ports = priv->hw_info->max_ports;
+ 	int err;
+ 
+-	if (port >= max_ports) {
++	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+ 		dev_err(priv->dev, "single port for %i supported\n", port);
+ 		return -EIO;
+ 	}
diff --git a/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch b/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
new file mode 100644
index 0000000000..ef8302fe80
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
@@ -0,0 +1,26 @@
+From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:26:20 +0200
+Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in
+ gswip_add_single_port_br()
+
+The error message is printed when the port cannot be used. Update the
+error message to reflect that.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -634,7 +634,8 @@ static int gswip_add_single_port_br(stru
+ 	int err;
+ 
+ 	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+-		dev_err(priv->dev, "single port for %i supported\n", port);
++		dev_err(priv->dev, "single port for %i is not supported\n",
++			port);
+ 		return -EIO;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch b/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
new file mode 100644
index 0000000000..6eeed5b27a
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
@@ -0,0 +1,36 @@
+From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:06:40 +0200
+Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in
+ gswip_port_vlan_filtering()
+
+Update the comments in gswip_port_vlan_filtering() so it's clear that
+there are two separate cases, one for "tag based VLAN" and another one
+for "port based VLAN".
+
+Suggested-by: Martin Schiller <ms@dev.tdt.de>
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -762,7 +762,7 @@ static int gswip_port_vlan_filtering(str
+ 	}
+ 
+ 	if (vlan_filtering) {
+-		/* Use port based VLAN tag */
++		/* Use tag based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_VSR,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+@@ -771,7 +771,7 @@ static int gswip_port_vlan_filtering(str
+ 		gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
+ 				  GSWIP_PCE_PCTRL_0p(port));
+ 	} else {
+-		/* Use port based VLAN tag */
++		/* Use port based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+ 				  GSWIP_PCE_VCTRL_VEMR,
diff --git a/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch b/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
new file mode 100644
index 0000000000..b9912e8735
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
@@ -0,0 +1,33 @@
+From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:19:05 +0200
+Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a
+ GSWIP_TABLE_MAC_BRIDGE_FID macro
+
+Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a
+macro so this becomes obvious when reading the driver code.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -238,6 +238,7 @@
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+ #define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
+ #define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
++#define  GSWIP_TABLE_MAC_BRIDGE_FID	GENMASK(5, 0)	/* Filtering identifier */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1357,7 +1358,7 @@ static int gswip_port_fdb(struct dsa_swi
+ 	mac_bridge.key[0] = addr[5] | (addr[4] << 8);
+ 	mac_bridge.key[1] = addr[3] | (addr[2] << 8);
+ 	mac_bridge.key[2] = addr[1] | (addr[0] << 8);
+-	mac_bridge.key[3] = fid;
++	mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid);
+ 	mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
+ 	mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
+ 	mac_bridge.valid = add;
diff --git a/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch b/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
new file mode 100644
index 0000000000..2538a4c856
--- /dev/null
+++ b/target/linux/lantiq/patches-5.15/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
@@ -0,0 +1,26 @@
+From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 16:31:57 +0200
+Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in
+ gswip_port_fdb()
+
+Print the port which is not found to be part of a bridge so it's easier
+to investigate the underlying issue.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1349,7 +1349,8 @@ static int gswip_port_fdb(struct dsa_swi
+ 	}
+ 
+ 	if (fid == -1) {
+-		dev_err(priv->dev, "Port not part of a bridge\n");
++		dev_err(priv->dev,
++			"Port %d is not known to be part of bridge\n", port);
+ 		return -EINVAL;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch
new file mode 100644
index 0000000000..b8f3116bb4
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0001-MIPS-lantiq-add-pcie-driver.patch
@@ -0,0 +1,5550 @@
+From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:12:28 +0200
+Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/Kconfig           |   10 +
+ arch/mips/lantiq/xway/sysctrl.c    |    2 +
+ arch/mips/pci/Makefile             |    2 +
+ arch/mips/pci/fixup-lantiq-pcie.c  |   82 +++
+ arch/mips/pci/fixup-lantiq.c       |    5 +-
+ arch/mips/pci/ifxmips_pci_common.h |   57 ++
+ arch/mips/pci/ifxmips_pcie.c       | 1099 ++++++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie.h       |  135 ++++
+ arch/mips/pci/ifxmips_pcie_ar10.h  |  290 ++++++++
+ arch/mips/pci/ifxmips_pcie_msi.c   |  392 +++++++++++
+ arch/mips/pci/ifxmips_pcie_phy.c   |  478 +++++++++++++
+ arch/mips/pci/ifxmips_pcie_pm.c    |  176 +++++
+ arch/mips/pci/ifxmips_pcie_pm.h    |   36 +
+ arch/mips/pci/ifxmips_pcie_reg.h   | 1001 +++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie_vr9.h   |  271 ++++++++
+ arch/mips/pci/pci.c                |   25 +
+ arch/mips/pci/pcie-lantiq.h        | 1305 ++++++++++++++++++++++++++++++++++++
+ drivers/pci/pcie/aer/Kconfig       |    2 +-
+ include/linux/pci.h                |    2 +
+ include/linux/pci_ids.h            |    6 +
+ 20 files changed, 5374 insertions(+), 2 deletions(-)
+ create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pci_common.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h
+ create mode 100644 arch/mips/pci/pcie-lantiq.h
+
+--- a/arch/mips/lantiq/Kconfig
++++ b/arch/mips/lantiq/Kconfig
+@@ -20,6 +20,7 @@ config SOC_XWAY
+ 	bool "XWAY"
+ 	select SOC_TYPE_XWAY
+ 	select HAVE_PCI
++	select ARCH_SUPPORTS_MSI
+ 	select MFD_SYSCON
+ 	select MFD_CORE
+ 
+@@ -52,4 +53,13 @@ config PCI_LANTIQ
+ 	bool "PCI Support"
+ 	depends on SOC_XWAY && PCI
+ 
++config PCIE_LANTIQ
++	bool "PCIE Support"
++	depends on SOC_XWAY && PCI
++
++config PCIE_LANTIQ_MSI
++	bool
++	depends on PCIE_LANTIQ && PCI_MSI
++	default y
++
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,8 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+ obj-$(CONFIG_TOSHIBA_RBTX4927)	+= fixup-rbtx4927.o
+--- /dev/null
++++ b/arch/mips/pci/fixup-lantiq-pcie.c
+@@ -0,0 +1,74 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_fixup_pcie.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe 
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_fixup_pcie.c
++ \ingroup IFX_PCIE  
++ \brief PCIe Fixup functions source file
++*/
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/pci_ids.h>
++
++#include <lantiq_soc.h>
++
++#include "pcie-lantiq.h"
++
++static void
++ifx_pcie_fixup_resource(struct pci_dev *dev)
++{
++    u32 reg;
++
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++    printk("%s: fixup host controller %s (%04x:%04x)\n", 
++        __func__, pci_name(dev), dev->vendor, dev->device); 
++
++   /* Setup COMMAND register */
++    reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | 
++          PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR;
++    pci_write_config_word(dev, PCI_COMMAND, reg);
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource);
++
++static void
++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev)
++{
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++    if (dev->devfn == PCI_DEVFN(0, 0) &&
++        (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
++
++        dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff);
++
++        printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__);
++    }
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++    mdelay(10);
++}
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE,
++     ifx_pcie_rc_class_early_fixup);
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE,
++     ifx_pcie_rc_class_early_fixup);
+--- a/arch/mips/pci/fixup-lantiq.c
++++ b/arch/mips/pci/fixup-lantiq.c
+@@ -6,12 +6,19 @@
+ 
+ #include <linux/of_irq.h>
+ #include <linux/of_pci.h>
++#include <linux/pci.h>
++#include "ifxmips_pci_common.h"
+ 
+ int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;
+ int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
+ 
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++	if (pci_find_capability(dev, PCI_CAP_ID_EXP))
++		ifx_pcie_bios_plat_dev_init(dev);
++#endif
++
+ 	if (ltq_pci_plat_arch_init)
+ 		return ltq_pci_plat_arch_init(dev);
+ 
+@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev
+ 
+ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++	if (pci_find_capability((struct pci_dev *)dev, PCI_CAP_ID_EXP))
++		return ifx_pcie_bios_map_irq(dev, slot, pin);
++#endif
++
+ 	return of_irq_parse_and_map_pci(dev, slot, pin);
+ }
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pci_common.h
+@@ -0,0 +1,53 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pci_common.h
++** PROJECT      : IFX UEIP
++** MODULES      : PCI subsystem
++**
++** DATE         : 30 June 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    30 June,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++
++#ifndef IFXMIPS_PCI_COMMON_H
++#define IFXMIPS_PCI_COMMON_H
++#include <linux/version.h>
++/*!
++ \defgroup IFX_PCI_COM  IFX PCI/PCIe common parts for OS integration  
++ \brief  PCI/PCIe common parts
++*/
++
++/*!
++ \defgroup IFX_PCI_COM_OS OS APIs
++ \ingroup IFX_PCI_COM
++ \brief PCI/PCIe bus driver OS interface functions
++*/
++/*!
++  \file ifxmips_pci_common.h
++  \ingroup IFX_PCI_COM
++  \brief PCI/PCIe bus driver common OS header file
++*/
++#define IFX_PCI_CONST const
++#ifdef CONFIG_IFX_PCI
++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev);
++#endif /* COFNIG_IFX_PCI */
++
++#ifdef CONFIG_PCIE_LANTIQ
++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev);
++#endif
++
++#endif /* IFXMIPS_PCI_COMMON_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -0,0 +1,1091 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2009 Lei Chuanhua <chuanhua.lei@infineon.com>
++ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <asm/paccess.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/module.h>
++
++#include "ifxmips_pcie.h"
++#include "ifxmips_pcie_reg.h"
++
++/* Enable 32bit io due to its mem mapped io nature */
++#define IFX_PCIE_ERROR_INT
++#define IFX_PCIE_IO_32BIT
++
++#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
++#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
++#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
++#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
++#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
++#define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
++#define SM(_v, _f)  (((_v) << _f##_S) & (_f))
++#define IFX_REG_SET_BIT(_f, _r) \
++	IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r))
++
++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10
++
++static DEFINE_SPINLOCK(ifx_pcie_lock);
++
++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++
++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
++    {
++        .ir_irq = {
++            .irq  = IFX_PCIE_IR,
++            .name = "ifx_pcie_rc0",
++        },
++
++        .legacy_irq = {
++            {
++                .irq_bit = PCIE_IRN_INTA,
++                .irq     = IFX_PCIE_INTA,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTB,
++                .irq     = IFX_PCIE_INTB,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTC,
++                .irq     = IFX_PCIE_INTC,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTD,
++                .irq     = IFX_PCIE_INTD,
++            },
++        },
++    },
++
++};
++
++void ifx_pcie_debug(const char *fmt, ...)
++{
++	static char buf[256] = {0};      /* XXX */
++	va_list ap;
++
++	va_start(ap, fmt);
++	vsnprintf(buf, sizeof(buf), fmt, ap);
++	va_end(ap);
++
++	printk("%s", buf);
++}
++
++
++static inline int pcie_ltssm_enable(int pcie_port)
++{
++	int i;
++
++	/* Enable LTSSM */
++	IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port));
++
++	/* Wait for the link to come up */
++	for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) {
++		if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING))
++			return 0;
++		udelay(10);
++	}
++
++	printk("%s link timeout!!!!!\n", __func__);
++	return -1;
++}
++
++static inline void pcie_status_register_clear(int pcie_port)
++{
++	IFX_REG_W32(0, PCIE_RC_DR(pcie_port));
++	IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_RSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_UES_R(pcie_port));
++	IFX_REG_W32(0, PCIE_UEMR(pcie_port));
++	IFX_REG_W32(0, PCIE_UESR(pcie_port));
++	IFX_REG_W32(0, PCIE_CESR(pcie_port));
++	IFX_REG_W32(0, PCIE_CEMR(pcie_port));
++	IFX_REG_W32(0, PCIE_RESR(pcie_port));
++	IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port));
++	IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port));
++	IFX_REG_W32(0, PCIE_TPFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_TNPFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_TCFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_QSR(pcie_port));
++	IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port));
++}
++
++static inline int ifx_pcie_link_up(int pcie_port)
++{
++    return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0;
++}
++
++
++static inline void pcie_mem_io_setup(int pcie_port)
++{
++    u32 reg;
++    /*
++     * BAR[0:1] readonly register 
++     * RC contains only minimal BARs for packets mapped to this device 
++     * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that
++     * reside on the downstream side fo the bridge.
++     */
++    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR)
++        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR);
++
++    IFX_REG_W32(reg, PCIE_MBML(pcie_port));
++
++
++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT
++    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR)
++        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT)
++        | PCIE_PMBL_64BIT_ADDR;
++    IFX_REG_W32(reg, PCIE_PMBL(pcie_port));
++
++    /* Must configure upper 32bit */
++    IFX_REG_W32(0, PCIE_PMBU32(pcie_port));
++    IFX_REG_W32(0, PCIE_PMLU32(pcie_port));
++#else
++    /* PCIe_PBML, same as MBML */
++    IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port));
++#endif 
++
++    /* IO Address Range */
++    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR)
++        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR);
++#ifdef IFX_PCIE_IO_32BIT    
++    reg |= PCIE_IOBLSECS_32BIT_IO_ADDR;
++#endif /* IFX_PCIE_IO_32BIT */
++    IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port));
++
++#ifdef IFX_PCIE_IO_32BIT
++    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT)
++        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE);
++    IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port));
++
++#endif /* IFX_PCIE_IO_32BIT */
++}
++
++static inline void
++pcie_device_setup(int pcie_port)
++{
++    u32 reg;
++
++    /* Device capability register, set up Maximum payload size */
++    reg = IFX_REG_R32(PCIE_DCAP(pcie_port));
++    reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT;
++    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE);
++
++    /* Only available for EP */
++    reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY);
++    IFX_REG_W32(reg, PCIE_DCAP(pcie_port));
++
++    /* Device control and status register */
++    /* Set Maximum Read Request size for the device as a Requestor */
++    reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port));
++
++    /* 
++     * Request size can be larger than the MPS used, but the completions returned 
++     * for the read will be bounded by the MPS size.
++     * In our system, Max request size depends on AHB burst size. It is 64 bytes.
++     * but we set it as 128 as minimum one.
++     */
++    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE)
++            | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE);
++
++    /* Enable relaxed ordering, no snoop, and all kinds of errors */
++    reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN;
++
++    IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port));
++}
++
++static inline void
++pcie_link_setup(int pcie_port)
++{
++    u32 reg;
++
++    /*
++     * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM 
++     * L0s is reported during link training via TS1 order set by N_FTS
++     */
++    reg = IFX_REG_R32(PCIE_LCAP(pcie_port));
++    reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY;
++    reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY);
++    IFX_REG_W32(reg, PCIE_LCAP(pcie_port));
++
++    /* Link control and status register */
++    reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++    /* Link Enable, ASPM enabled  */
++    reg &= ~PCIE_LCTLSTS_LINK_DISABLE;
++
++#ifdef CONFIG_PCIEASPM
++    /*  
++     * We use the same physical reference clock that the platform provides on the connector 
++     * It paved the way for ASPM to calculate the new exit Latency
++     */
++    reg |= PCIE_LCTLSTS_SLOT_CLK_CFG;
++    reg |= PCIE_LCTLSTS_COM_CLK_CFG;
++    /*
++     * We should disable ASPM by default except that we have dedicated power management support
++     * Enable ASPM will cause the system hangup/instability, performance degration
++     */
++    reg |= PCIE_LCTLSTS_ASPM_ENABLE;
++#else
++    reg &= ~PCIE_LCTLSTS_ASPM_ENABLE;
++#endif /* CONFIG_PCIEASPM */
++
++    /* 
++     * The maximum size of any completion with data packet is bounded by the MPS setting 
++     * in  device control register 
++     */
++
++    /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */
++    reg &= ~ PCIE_LCTLSTS_RCB128;
++
++    IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port));
++}
++
++static inline void pcie_error_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* 
++	* Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone 
++	* Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE 
++	*/
++	reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port));
++	reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE;
++
++	IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port));
++
++	/* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */
++	reg = IFX_REG_R32(PCIE_UEMR(pcie_port));
++	reg &= ~PCIE_ALL_UNCORRECTABLE_ERR;
++	IFX_REG_W32(reg, PCIE_UEMR(pcie_port));
++
++	/* Uncorrectable Error Severity Register, ALL errors are FATAL */
++	IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port));
++
++	/* Correctable Error Mask Register, unmask <enable> all bits */
++	reg = IFX_REG_R32(PCIE_CEMR(pcie_port));
++	reg &= ~PCIE_CORRECTABLE_ERR;
++	IFX_REG_W32(reg, PCIE_CEMR(pcie_port));
++
++	/* Advanced Error Capabilities and Control Registr */
++	reg = IFX_REG_R32(PCIE_AECCR(pcie_port));
++	reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN;
++	IFX_REG_W32(reg, PCIE_AECCR(pcie_port));
++
++	/* Root Error Command Register, Report all types of errors */
++	reg = IFX_REG_R32(PCIE_RECR(pcie_port));
++	reg |= PCIE_RECR_ERR_REPORT_EN;
++	IFX_REG_W32(reg, PCIE_RECR(pcie_port));
++
++	/* Clear the Root status register */
++	reg = IFX_REG_R32(PCIE_RESR(pcie_port));
++	IFX_REG_W32(reg, PCIE_RESR(pcie_port));
++}
++
++static inline void pcie_port_logic_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* FTS number, default 12, increase to 63, may increase time from/to L0s to L0  */
++	reg = IFX_REG_R32(PCIE_AFR(pcie_port));
++	reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM);
++	reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM)
++		| SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM);
++	/* L0s and L1 entry latency */
++	reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY);
++	reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY)
++		| SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY);
++	IFX_REG_W32(reg, PCIE_AFR(pcie_port));
++
++
++	/* Port Link Control Register */
++	reg = IFX_REG_R32(PCIE_PLCR(pcie_port));
++	reg |= PCIE_PLCR_DLL_LINK_EN;  /* Enable the DLL link */
++	IFX_REG_W32(reg, PCIE_PLCR(pcie_port));
++
++	/* Lane Skew Register */
++	reg = IFX_REG_R32(PCIE_LSR(pcie_port));
++	/* Enable ACK/NACK and FC */
++	reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE);
++	IFX_REG_W32(reg, PCIE_LSR(pcie_port));
++
++	/* Symbol Timer Register and Filter Mask Register 1 */
++	reg = IFX_REG_R32(PCIE_STRFMR(pcie_port));
++
++	/* Default SKP interval is very accurate already, 5us */
++	/* Enable IO/CFG transaction */
++	reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE;
++	/* Disable FC WDT */
++	reg &= ~PCIE_STRFMR_FC_WDT_DISABLE;
++	IFX_REG_W32(reg, PCIE_STRFMR(pcie_port));
++
++	/* Filter Masker Register 2 */
++	reg = IFX_REG_R32(PCIE_FMR2(pcie_port));
++	reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1;
++	IFX_REG_W32(reg, PCIE_FMR2(pcie_port));
++
++	/* VC0 Completion Receive Queue Control Register */
++	reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port));
++	reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE;
++	reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE);
++	IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port));
++}
++
++static inline void pcie_rc_cfg_reg_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* Disable LTSSM */
++	IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */
++
++	pcie_mem_io_setup(pcie_port);
++
++	/* XXX, MSI stuff should only apply to EP */
++	/* MSI Capability: Only enable 32-bit addresses */
++	reg = IFX_REG_R32(PCIE_MCAPR(pcie_port));
++	reg &= ~PCIE_MCAPR_ADDR64_CAP;
++
++	reg |= PCIE_MCAPR_MSI_ENABLE;
++
++	/* Disable multiple message */
++	reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE);
++	IFX_REG_W32(reg, PCIE_MCAPR(pcie_port));
++
++
++	/* Enable PME, Soft reset enabled */
++	reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port));
++	reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST;
++	IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port));
++
++	/* setup the bus */
++	reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM);
++	IFX_REG_W32(reg, PCIE_BNR(pcie_port));
++
++
++	pcie_device_setup(pcie_port);
++	pcie_link_setup(pcie_port);
++	pcie_error_setup(pcie_port);
++
++	/* Root control and capabilities register */
++	reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port));
++	reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN;
++	IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port));
++
++	/* Port VC Capability Register 2 */
++	reg = IFX_REG_R32(PCIE_PVC2(pcie_port));
++	reg &= ~PCIE_PVC2_VC_ARB_WRR;
++	reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR;
++	IFX_REG_W32(reg, PCIE_PVC2(pcie_port));
++
++	/* VC0 Resource Capability Register */
++	reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port));
++	reg &= ~PCIE_VC0_RC_REJECT_SNOOP;
++	IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port));
++
++	pcie_port_logic_setup(pcie_port);
++}
++
++static int ifx_pcie_wait_phy_link_up(int pcie_port)
++{
++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT  1000 /* XXX, tunable */
++    int i;
++
++    /* Wait for PHY link is up */
++    for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) {
++        if (ifx_pcie_link_up(pcie_port)) {
++            break;
++        }
++        udelay(100);
++    }
++    if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) {
++        printk(KERN_ERR "%s timeout\n", __func__);
++        return -1;
++    }
++
++    /* Check data link up or not */
++    if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) {
++        printk(KERN_ERR "%s DLL link is still down\n", __func__);
++        return -1;
++    }
++
++    /* Check Data link active or not */
++    if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) {
++        printk(KERN_ERR "%s DLL is not active\n", __func__);
++        return -1;
++    }
++    return 0;
++}
++
++static inline int pcie_app_loigc_setup(int pcie_port)
++{
++	/* supress ahb bus errrors */
++	IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port));
++
++	/* Pull PCIe EP out of reset */
++	pcie_device_rst_deassert(pcie_port);
++
++	/* Start LTSSM training between RC and EP */
++	pcie_ltssm_enable(pcie_port);
++
++	/* Check PHY status after enabling LTSSM */
++	if (ifx_pcie_wait_phy_link_up(pcie_port) != 0)
++		return -1;
++
++	return 0;
++}
++
++/*
++ * The numbers below are directly from the PCIe spec table 3-4/5. 
++ */
++static inline void pcie_replay_time_update(int pcie_port)
++{
++	u32 reg;
++	int nlw;
++	int rtl;
++
++	reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++	nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH);
++	switch (nlw) {
++	case PCIE_MAX_LENGTH_WIDTH_X1:
++		rtl = 1677;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X2:
++		rtl = 867;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X4:
++		rtl = 462;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X8:
++		rtl = 258;
++		break;
++	default:
++		rtl = 1677;
++		break;
++	}
++	reg = IFX_REG_R32(PCIE_ALTRT(pcie_port));
++	reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT;
++	reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT);
++	IFX_REG_W32(reg, PCIE_ALTRT(pcie_port));
++}
++
++/*
++ * Table 359 Enhanced Configuration Address Mapping1)
++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1
++ * Memory Address PCI Express Configuration Space
++ * A[(20+n-1):20] Bus Number 1 < n < 8
++ * A[19:15] Device Number
++ * A[14:12] Function Number
++ * A[11:8] Extended Register Number
++ * A[7:2] Register Number
++ * A[1:0] Along with size of the access, used to generate Byte Enables
++ * For VR9, only the address bits [22:0] are mapped to the configuration space:
++ * . Address bits [22:20] select the target bus (1-of-8)1)
++ * . Address bits [19:15] select the target device (1-of-32) on the bus
++ * . Address bits [14:12] select the target function (1-of-8) within the device.
++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space
++ * . Address bits [1:0] define the start byte location within the selected dword.
++ */
++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where)
++{
++	u32 addr;
++	u8  bus;
++
++	if (!bus_num) {
++		/* type 0 */
++		addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3);
++	} else {
++		bus = bus_num;
++		/* type 1, only support 8 buses  */
++		addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) |
++			((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3);
++	}
++	return addr;
++}
++
++static int pcie_valid_config(int pcie_port, int bus, int dev)
++{
++	/* RC itself */
++	if ((bus == 0) && (dev == 0)) {
++		return 1;
++	}
++
++	/* No physical link */
++	if (!ifx_pcie_link_up(pcie_port)) {
++		return 0;
++	}
++
++	/* Bus zero only has RC itself
++	* XXX, check if EP will be integrated 
++	*/
++	if ((bus == 0) && (dev != 0)) {
++		return 0;
++	}
++
++	/* Maximum 8 buses supported for VRX */
++	if (bus > 9) {
++		return 0;
++	}
++
++	/* 
++	 * PCIe is PtP link, one bus only supports only one device 
++	 * except bus zero and PCIe switch which is virtual bus device
++	 * The following two conditions really depends on the system design
++	 * and attached the device.
++	 * XXX, how about more new switch
++	*/
++	if ((bus == 1) && (dev != 0)) {
++		return 0;
++	}
++
++	if ((bus >= 3) && (dev != 0)) {
++		return 0;
++	}
++	return 1;
++}
++
++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg)
++{
++    return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++    IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg)
++{
++    return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++	IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value)
++{
++	u32 tvalue = value;
++
++	if (where == PCI_PRIMARY_BUS) {
++		u8 primary, secondary, subordinate;
++
++		primary = tvalue & 0xFF;
++		secondary = (tvalue >> 8) & 0xFF;
++		subordinate = (tvalue >> 16) & 0xFF;
++		primary += pcibios_1st_host_bus_nr();
++		secondary += pcibios_1st_host_bus_nr();
++		subordinate += pcibios_1st_host_bus_nr();
++		tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++	}
++	return tvalue;
++}
++
++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value)
++{
++    u32 tvalue = value;
++
++    if (where == PCI_PRIMARY_BUS) {
++        u8 primary, secondary, subordinate;
++
++        primary = tvalue & 0xFF;
++        secondary = (tvalue >> 8) & 0xFF;
++        subordinate = (tvalue >> 16) & 0xFF;
++        if (primary > 0 && primary != 0xFF) {
++            primary -= pcibios_1st_host_bus_nr();
++        }
++
++        if (secondary > 0 && secondary != 0xFF) {
++            secondary -= pcibios_1st_host_bus_nr();
++        }
++        if (subordinate > 0 && subordinate != 0xFF) {
++            subordinate -= pcibios_1st_host_bus_nr();
++        }
++        tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++    }
++    else if (where == PCI_SUBORDINATE_BUS) {
++        u8 subordinate = tvalue & 0xFF;
++
++        subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0;
++        tvalue = subordinate;
++    }
++    return tvalue;
++}
++
++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn,
++				int where, int size, u32 *value)
++{
++    u32 data = 0;
++    int bus_number = bus->number;
++    static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
++    int ret = PCIBIOS_SUCCESSFUL;
++    struct ifx_pci_controller *ctrl = bus->sysdata;
++    int pcie_port = ctrl->port;
++
++    if (unlikely(size != 1 && size != 2 && size != 4)){
++        ret = PCIBIOS_BAD_REGISTER_NUMBER;
++        goto out;
++    }
++
++    /* Make sure the address is aligned to natural boundary */
++    if (unlikely(((size - 1) & where))) {
++        ret = PCIBIOS_BAD_REGISTER_NUMBER;
++        goto out;
++    }
++
++    /* 
++     * If we are second controller, we have to cheat OS so that it assume 
++     * its bus number starts from 0 in host controller
++     */
++    bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++    /* 
++     * We need to force the bus number to be zero on the root 
++     * bus. Linux numbers the 2nd root bus to start after all 
++     * busses on root 0. 
++     */ 
++    if (bus->parent == NULL) {
++        bus_number = 0; 
++    }
++
++    /* 
++     * PCIe only has a single device connected to it. It is 
++     * always device ID 0. Don't bother doing reads for other 
++     * device IDs on the first segment. 
++     */ 
++    if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) {
++        ret = PCIBIOS_FUNC_NOT_SUPPORTED;
++        goto out; 
++    }
++
++    if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++        *value = 0xffffffff;
++        ret = PCIBIOS_DEVICE_NOT_FOUND;
++        goto out;
++    }
++
++    PCIE_IRQ_LOCK(ifx_pcie_lock);
++    if (bus_number == 0) { /* RC itself */
++        u32 t;
++
++        t = (where & ~3);
++        data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++    } else {
++        u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++        data = ifx_pcie_cfg_rd(pcie_port, addr);
++    #ifdef CONFIG_IFX_PCIE_HW_SWAP
++            data = le32_to_cpu(data);
++    #endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    }
++    /* To get a correct PCI topology, we have to restore the bus number to OS */
++    data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1);
++
++    PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++
++    *value = (data >> (8 * (where & 3))) & mask[size & 7];
++out:
++    return ret;
++}
++
++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value)
++{
++	u32 shift;
++	u32 tdata = data;
++
++	switch (size) {
++	case 1:
++		shift = (where & 0x3) << 3;
++		tdata &= ~(0xffU << shift);
++		tdata |= ((value & 0xffU) << shift);
++		break;
++	case 2:
++		shift = (where & 3) << 3;
++		tdata &= ~(0xffffU << shift);
++		tdata |= ((value & 0xffffU) << shift);
++		break;
++	case 4:
++		tdata = value;
++		break;
++	}
++	return tdata;
++}
++
++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn,
++				int where, int size, u32 value)
++{
++	int bus_number = bus->number;
++	int ret = PCIBIOS_SUCCESSFUL;
++	struct ifx_pci_controller *ctrl = bus->sysdata;
++	int pcie_port = ctrl->port;
++	u32 tvalue = value;
++	u32 data;
++
++	/* Make sure the address is aligned to natural boundary */
++	if (unlikely(((size - 1) & where))) {
++		ret = PCIBIOS_BAD_REGISTER_NUMBER;
++		goto out;
++	}
++	/* 
++	* If we are second controller, we have to cheat OS so that it assume 
++	* its bus number starts from 0 in host controller
++	*/
++	bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++	/* 
++	* We need to force the bus number to be zero on the root 
++	* bus. Linux numbers the 2nd root bus to start after all 
++	* busses on root 0. 
++	*/ 
++	if (bus->parent == NULL) {
++		bus_number = 0; 
++	}
++
++	if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++		ret = PCIBIOS_DEVICE_NOT_FOUND;
++		goto out;
++	}
++
++	/* XXX, some PCIe device may need some delay */
++	PCIE_IRQ_LOCK(ifx_pcie_lock);
++
++	/* 
++	* To configure the correct bus topology using native way, we have to cheat Os so that
++	* it can configure the PCIe hardware correctly.
++	*/
++	tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0);
++
++	if (bus_number == 0) { /* RC itself */
++		u32 t;
++
++		t = (where & ~3);
++		data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++
++		data = ifx_pcie_size_to_value(where, size, data, tvalue);
++
++		ifx_pcie_rc_cfg_wr(pcie_port, t, data);
++	} else {
++		u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++		data = ifx_pcie_cfg_rd(pcie_port, addr);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++		data = le32_to_cpu(data);
++#endif
++
++		data = ifx_pcie_size_to_value(where, size, data, tvalue);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++		data = cpu_to_le32(data);
++#endif
++		ifx_pcie_cfg_wr(pcie_port, addr, data);
++	}
++	PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++out:
++	return ret;
++}
++
++static struct resource ifx_pcie_io_resource = {
++	.name	= "PCIe0 I/O space",
++	.start	= PCIE_IO_PHY_BASE,
++	.end	= PCIE_IO_PHY_END,
++	.flags	= IORESOURCE_IO,
++};
++
++static struct resource ifx_pcie_mem_resource = {
++	.name	= "PCIe0 Memory space",
++	.start	= PCIE_MEM_PHY_BASE,
++	.end	= PCIE_MEM_PHY_END,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct pci_ops ifx_pcie_ops = {
++	.read	= ifx_pcie_read_config,
++	.write	= ifx_pcie_write_config,
++};
++
++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = {
++    {
++        .pcic = {
++            .pci_ops      = &ifx_pcie_ops,
++            .mem_resource = &ifx_pcie_mem_resource,
++            .io_resource  = &ifx_pcie_io_resource,
++         },
++         .port = IFX_PCIE_PORT0,
++    },
++};
++
++#ifdef IFX_PCIE_ERROR_INT
++
++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id)
++{
++	struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id;
++	int pcie_port = ctrl->port;
++	u32 reg;
++
++	pr_debug("PCIe RC error intr %d\n", irq);
++	reg = IFX_REG_R32(PCIE_IRNCR(pcie_port));
++	reg &= PCIE_RC_CORE_COMBINED_INT;
++	IFX_REG_W32(reg, PCIE_IRNCR(pcie_port));
++
++	return IRQ_HANDLED;
++}
++
++static int
++pcie_rc_core_int_init(int pcie_port)
++{
++	int ret;
++
++	/* Enable core interrupt */
++	IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port));
++
++	/* Clear it first */
++	IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port));
++	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
++		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
++	if (ret)
++		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++
++	return ret;
++}
++#endif
++
++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin)
++{
++	u32 irq_bit = 0;
++	int irq = 0;
++	struct ifx_pci_controller *ctrl = dev->bus->sysdata;
++	int pcie_port = ctrl->port;
++
++	printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin);
++
++	if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) {
++		printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin);
++		return -1;
++	}
++
++	/* Pin index so minus one */
++	irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit;
++	irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq;
++	IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port));
++	IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port));
++	printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq);
++	return irq;
++}
++
++int  ifx_pcie_bios_plat_dev_init(struct pci_dev *dev)
++{
++    u16 config;
++#ifdef IFX_PCIE_ERROR_INT
++    u32 dconfig; 
++    int pos;
++#endif
++
++    /* Enable reporting System errors and parity errors on all devices */ 
++    /* Enable parity checking and error reporting */ 
++    pci_read_config_word(dev, PCI_COMMAND, &config);
++    config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE |
++          PCI_COMMAND_FAST_BACK*/;
++    pci_write_config_word(dev, PCI_COMMAND, config);
++
++    if (dev->subordinate) {
++        /* Set latency timers on sub bridges */
++        pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */
++        /* More bridge error detection */
++        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
++        config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
++        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
++    }
++#ifdef IFX_PCIE_ERROR_INT
++    /* Enable the PCIe normal error reporting */
++    pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
++    if (pos) {
++
++        /* Disable system error generation in response to error messages */
++        pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config);
++        config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE);
++        pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config);
++
++        /* Clear PCIE Capability's Device Status */
++        pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config);
++        pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config);
++
++        /* Update Device Control */ 
++        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
++        /* Correctable Error Reporting */
++        config |= PCI_EXP_DEVCTL_CERE;
++        /* Non-Fatal Error Reporting */
++        config |= PCI_EXP_DEVCTL_NFERE;
++        /* Fatal Error Reporting */
++        config |= PCI_EXP_DEVCTL_FERE;
++        /* Unsupported Request */
++        config |= PCI_EXP_DEVCTL_URRE;
++        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
++    }
++
++    /* Find the Advanced Error Reporting capability */
++    pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
++    if (pos) {
++        /* Clear Uncorrectable Error Status */ 
++        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig);
++        /* Enable reporting of all uncorrectable errors */
++        /* Uncorrectable Error Mask - turned on bits disable errors */
++        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
++        /* 
++        * Leave severity at HW default. This only controls if 
++        * errors are reported as uncorrectable or 
++        * correctable, not if the error is reported. 
++        */ 
++        /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
++        /* Clear Correctable Error Status */
++        pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
++        /* Enable reporting of all correctable errors */
++        /* Correctable Error Mask - turned on bits disable errors */
++        pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
++        /* Advanced Error Capabilities */ 
++        pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
++        /* ECRC Generation Enable */
++        if (dconfig & PCI_ERR_CAP_ECRC_GENC) {
++            dconfig |= PCI_ERR_CAP_ECRC_GENE;
++        }
++        /* ECRC Check Enable */
++        if (dconfig & PCI_ERR_CAP_ECRC_CHKC) {
++            dconfig |= PCI_ERR_CAP_ECRC_CHKE;
++        }
++        pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
++
++        /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
++        /* Enable Root Port's interrupt in response to error messages */
++        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
++              PCI_ERR_ROOT_CMD_COR_EN |
++              PCI_ERR_ROOT_CMD_NONFATAL_EN |
++              PCI_ERR_ROOT_CMD_FATAL_EN); 
++        /* Clear the Root status register */
++        pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
++    }
++#endif /* IFX_PCIE_ERROR_INT */
++    /* WAR, only 128 MRRS is supported, force all EPs to support this value */
++    pcie_set_readrq(dev, 128);
++    return 0;
++}
++
++static int
++pcie_rc_initialize(int pcie_port)
++{
++	int i;
++#define IFX_PCIE_PHY_LOOP_CNT  5
++
++	pcie_rcu_endian_setup(pcie_port);
++
++	pcie_ep_gpio_rst_init(pcie_port);
++
++	/* 
++	* XXX, PCIe elastic buffer bug will cause not to be detected. One more 
++	* reset PCIe PHY will solve this issue 
++	*/
++	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
++		/* Disable PCIe PHY Analog part for sanity check */
++		pcie_phy_pmu_disable(pcie_port);
++
++		pcie_phy_rst_assert(pcie_port);
++		pcie_phy_rst_deassert(pcie_port);
++
++		/* Make sure PHY PLL is stable */
++		udelay(20);
++
++		/* PCIe Core reset enabled, low active, sw programmed */
++		pcie_core_rst_assert(pcie_port);
++
++		/* Put PCIe EP in reset status */
++		pcie_device_rst_assert(pcie_port);
++
++		/* PCI PHY & Core reset disabled, high active, sw programmed */
++		pcie_core_rst_deassert(pcie_port);
++
++		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
++		pcie_phy_clock_mode_setup(pcie_port);
++
++		/* Enable PCIe PHY and Clock */
++		pcie_core_pmu_setup(pcie_port);
++
++		/* Clear status registers */
++		pcie_status_register_clear(pcie_port);
++
++#ifdef CONFIG_PCI_MSI
++		pcie_msi_init(pcie_port);
++#endif /* CONFIG_PCI_MSI */
++		pcie_rc_cfg_reg_setup(pcie_port);
++
++		/* Once link is up, break out */
++		if (pcie_app_loigc_setup(pcie_port) == 0)
++			break;
++	}
++	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
++		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
++		return -EIO;
++	}
++	/* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */
++	pcie_replay_time_update(pcie_port);
++	return 0;
++}
++
++static int __init ifx_pcie_bios_init(void)
++{
++    void __iomem *io_map_base;
++    int pcie_port;
++    int startup_port;
++
++    /* Enable AHB Master/ Slave */
++    pcie_ahb_pmu_setup();
++
++    startup_port = IFX_PCIE_PORT0;
++    
++    for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
++	if (pcie_rc_initialize(pcie_port) == 0) {
++	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
++                 __func__, PCIE_CFG_PORT_TO_BASE(pcie_port));
++            /* Otherwise, warning will pop up */
++            io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE);
++            if (io_map_base == NULL) {
++                IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
++                return -ENOMEM;
++            }
++            ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++
++            register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
++            /* XXX, clear error status */
++
++            IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", 
++                              __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, 
++                              &ifx_pcie_controller[pcie_port].pcic.io_resource);
++
++        #ifdef IFX_PCIE_ERROR_INT
++            pcie_rc_core_int_init(pcie_port);
++        #endif /* IFX_PCIE_ERROR_INT */
++        }
++    }
++
++    return 0;
++}
++arch_initcall(ifx_pcie_bios_init);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -0,0 +1,131 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_H
++#define IFXMIPS_PCIE_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include "ifxmips_pci_common.h"
++#include "ifxmips_pcie_reg.h"
++
++/*!
++ \defgroup IFX_PCIE  PCI Express bus driver module   
++ \brief  PCI Express IP module support VRX200 
++*/
++
++/*!
++ \defgroup IFX_PCIE_OS OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module common header file
++*/
++#define PCIE_IRQ_LOCK(lock) do {             \
++    unsigned long flags;                     \
++    spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock)                \
++    spin_unlock_irqrestore(&(lock), flags);  \
++} while (0)
++
++#define PCIE_MSG_MSI        0x00000001
++#define PCIE_MSG_ISR        0x00000002
++#define PCIE_MSG_FIXUP      0x00000004
++#define PCIE_MSG_READ_CFG   0x00000008
++#define PCIE_MSG_WRITE_CFG  0x00000010
++#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG        0x00000020
++#define PCIE_MSG_INIT       0x00000040
++#define PCIE_MSG_ERR        0x00000080
++#define PCIE_MSG_PHY        0x00000100
++#define PCIE_MSG_ANY        0x000001ff
++
++#define IFX_PCIE_PORT0      0
++#define IFX_PCIE_PORT1      1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR    2
++#else
++#define IFX_PCIE_CORE_NR    1
++#endif
++
++#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \
++        ifx_pcie_debug((_fmt), ##args);          \
++} while (0)
++
++#define INLINE 
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...)   \
++    do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++	struct pci_controller   pcic;
++    
++	/* RC specific, per host bus information */
++	u32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++    const unsigned int irq;
++    const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++    const u32 irq_bit;
++    const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++    ifx_pcie_ir_irq_t ir_irq;
++    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++#define CONFIG_VR9
++
++#ifdef CONFIG_VR9
++#include "ifxmips_pcie_vr9.h"
++#elif defined (CONFIG_AR10)
++#include "ifxmips_pcie_ar10.h"
++#else
++#error "PCIE: platform not defined"
++#endif /* CONFIG_VR9 */
++
++#endif  /* IFXMIPS_PCIE_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_ar10.h
+@@ -0,0 +1,305 @@
++/****************************************************************************
++                              Copyright (c) 2010
++                            Lantiq Deutschland GmbH
++                     Am Campeon 3; 85579 Neubiberg, Germany
++
++  For licensing information, see the file 'LICENSE' in the root folder of
++  this software module.
++
++ *****************************************************************************/
++/*!
++  \file ifxmips_pcie_ar10.h
++  \ingroup IFX_PCIE
++  \brief PCIe RC driver ar10 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_AR10_H
++#define IFXMIPS_PCIE_AR10_H
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/types.h>
++#include <linux/delay.h>
++
++/* Project header file */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_pmu.h>
++#include <asm/ifx/ifx_gpio.h>
++#include <asm/ifx/ifx_ebu_led.h>
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++    ifx_ebu_led_enable();
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 1);        
++    }
++    else {
++        ifx_ebu_led_set_data(12, 1);  
++    }
++}
++
++static inline void pcie_ahb_pmu_setup(void) 
++{
++    /* XXX, moved to CGU to control AHBM */
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Inbound, big endian */
++    reg |= IFX_RCU_BE_AHB4S;
++    if (pcie_port == 0) {
++        reg |= IFX_RCU_BE_PCIE0M;
++
++    #ifdef CONFIG_IFX_PCIE_HW_SWAP
++        /* Outbound, software swap needed */
++        reg |= IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE0S;
++    #else
++        /* Outbound little endian  */
++        reg &= ~IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE0S;
++    #endif
++    }
++    else {
++        reg |= IFX_RCU_BE_PCIE1M;
++    #ifdef CONFIG_IFX_PCIE1_HW_SWAP
++        /* Outbound, software swap needed */
++        reg |= IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE1S;
++    #else
++        /* Outbound little endian  */
++        reg &= ~IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE1S;
++    #endif
++    }
++
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++    if (pcie_port == 0) { /* XXX, should use macro*/
++        PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++    if (pcie_port == 0) { /* XXX, should use macro*/
++        PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++    }
++    else {
++        PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++    }
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    if (pcie_port == 0) {
++        /* Config AHB->PCIe and PDI endianness */
++        reg |= IFX_RCU_BE_PCIE0_PDI;
++    }
++    else {
++        /* Config AHB->PCIe and PDI endianness */
++        reg |= IFX_RCU_BE_PCIE1_PDI;
++    }
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++    if (pcie_port == 0) {
++        /* Enable PDI to access PCIe PHY register */
++        PDI0_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PDI1_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset Core, bit 22 */
++    if (pcie_port == 0) {
++        reg |= 0x00400000;
++    }
++    else {
++        reg |= 0x08000000; /* Bit 27 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg &= ~0x00400000; /* bit 22 */
++    }
++    else {
++        reg &= ~0x08000000; /* Bit 27 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg |= 0x00001000; /* Bit 12 */
++    }
++    else {
++        reg |= 0x00002000; /* Bit 13 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg &= ~0x00001000; /* Bit 12 */
++    }
++    else {
++        reg &= ~0x00002000; /* Bit 13 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 0);
++    }
++    else {
++        ifx_ebu_led_set_data(12, 0);
++    }
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 1);
++    }
++    else {
++        ifx_ebu_led_set_data(12, 1);
++    }
++    ifx_ebu_led_disable();
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++    if (pcie_port == 0) {
++        PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); 
++    }
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++    pcie_msi_pic_init(pcie_port);
++    if (pcie_port == 0) {
++        MSI0_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        MSI1_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++        if (pcibios_host_nr() > 1) {
++            tbus_number -= pcibios_1st_host_bus_nr();
++        }        
++    }
++#endif /* CONFIG_IFX_PCI */
++    return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_IFX_PCIE_2ND_CORE
++        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++            if (pcibios_host_nr() > 1) {
++                tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++            }
++        }
++    #endif /* CONFIG_IFX_PCIE_2ND_CORE */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_IFX_PCIE_2ND_CORE
++        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++            if (pcibios_host_nr() > 1) {
++                tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++            }
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_AR10_H */
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_msi.c
+@@ -0,0 +1,391 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_msi.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCI MSI sub module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe MSI Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Date        $Author         $Comment
++** 02 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \defgroup IFX_PCIE_MSI MSI OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie_msi.c
++ \ingroup IFX_PCIE 
++ \brief PCIe MSI OS interface file
++*/
++
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/pci.h>
++#include <linux/msi.h>
++#include <linux/module.h>
++#include <asm/bootinfo.h>
++#include <asm/irq.h>
++#include <asm/traps.h>
++
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/irq.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++#define IFX_MSI_IRQ_NUM    16
++
++enum {
++    IFX_PCIE_MSI_IDX0 = 0,
++    IFX_PCIE_MSI_IDX1,
++    IFX_PCIE_MSI_IDX2,
++    IFX_PCIE_MSI_IDX3,
++};
++
++typedef struct ifx_msi_irq_idx {
++    const int irq;
++    const int idx;
++}ifx_msi_irq_idx_t;
++
++struct ifx_msi_pic {
++    volatile u32  pic_table[IFX_MSI_IRQ_NUM];
++    volatile u32  pic_endian;    /* 0x40  */
++};
++typedef struct ifx_msi_pic *ifx_msi_pic_t;
++
++typedef struct ifx_msi_irq {
++    const volatile ifx_msi_pic_t msi_pic_p;
++    const u32 msi_phy_base;
++    const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];
++    /*
++     * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 
++     * in use.
++     */
++    u16 msi_free_irq_bitmask;
++
++    /*
++     * Each bit in msi_multiple_irq_bitmask tells that the device using 
++     * this bit in msi_free_irq_bitmask is also using the next bit. This 
++     * is used so we can disable all of the MSI interrupts when a device 
++     * uses multiple.
++     */
++    u16 msi_multiple_irq_bitmask;
++}ifx_msi_irq_t;
++
++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {
++    {
++        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,
++        .msi_phy_base = PCIE_MSI_PHY_BASE,
++        .msi_irq_idx = {
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++        },
++        .msi_free_irq_bitmask = 0,
++        .msi_multiple_irq_bitmask= 0,
++    },
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    {
++        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,
++        .msi_phy_base = PCIE1_MSI_PHY_BASE,
++        .msi_irq_idx = {
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++        },
++        .msi_free_irq_bitmask = 0,
++        .msi_multiple_irq_bitmask= 0,
++
++    },
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++};
++
++/* 
++ * This lock controls updates to msi_free_irq_bitmask, 
++ * msi_multiple_irq_bitmask and pic register settting
++ */ 
++static DEFINE_SPINLOCK(ifx_pcie_msi_lock);
++
++void pcie_msi_pic_init(int pcie_port)
++{
++    spin_lock(&ifx_pcie_msi_lock);
++    msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;
++    spin_unlock(&ifx_pcie_msi_lock);
++}
++
++/** 
++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++ * \brief Called when a driver request MSI interrupts instead of the 
++ * legacy INT A-D. This routine will allocate multiple interrupts 
++ * for MSI devices that support them. A device can override this by 
++ * programming the MSI control bits [6:4] before calling 
++ * pci_enable_msi(). 
++ * 
++ * \param[in] pdev   Device requesting MSI interrupts 
++ * \param[in] desc   MSI descriptor 
++ * 
++ * \return   -EINVAL Invalid pcie root port or invalid msi bit
++ * \return    0        OK
++ * \ingroup IFX_PCIE_MSI
++ */
++int 
++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++{
++    int  irq, pos;
++    u16  control;
++    int  irq_idx;
++    int  irq_step;
++    int configured_private_bits;
++    int request_private_bits;
++    struct msi_msg msg;
++    u16 search_mask;
++    struct ifx_pci_controller *ctrl = pdev->bus->sysdata;
++    int pcie_port = ctrl->port;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev));
++
++    /* XXX, skip RC MSI itself */
++    if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
++        IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__);
++        return -EINVAL;
++    }
++
++    /*
++     * Read the MSI config to figure out how many IRQs this device 
++     * wants.  Most devices only want 1, which will give 
++     * configured_private_bits and request_private_bits equal 0. 
++     */
++    pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);
++
++    /*
++     * If the number of private bits has been configured then use 
++     * that value instead of the requested number. This gives the 
++     * driver the chance to override the number of interrupts 
++     * before calling pci_enable_msi(). 
++     */
++    configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 
++    if (configured_private_bits == 0) {
++        /* Nothing is configured, so use the hardware requested size */
++        request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
++    }
++    else {
++        /*
++         * Use the number of configured bits, assuming the 
++         * driver wanted to override the hardware request 
++         * value.
++         */
++        request_private_bits = configured_private_bits;
++    }
++
++    /*
++     * The PCI 2.3 spec mandates that there are at most 32
++     * interrupts. If this device asks for more, only give it one.
++     */
++    if (request_private_bits > 5) {
++        request_private_bits = 0;
++    }
++again:
++    /*
++     * The IRQs have to be aligned on a power of two based on the
++     * number being requested.
++     */
++    irq_step = (1 << request_private_bits);
++
++    /* Mask with one bit for each IRQ */
++    search_mask = (1 << irq_step) - 1;
++
++    /*
++     * We're going to search msi_free_irq_bitmask_lock for zero 
++     * bits. This represents an MSI interrupt number that isn't in 
++     * use.
++     */
++    spin_lock(&ifx_pcie_msi_lock);
++    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {
++        if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {
++            msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; 
++            msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;
++            break; 
++        }
++    }
++    spin_unlock(&ifx_pcie_msi_lock); 
++
++    /* Make sure the search for available interrupts didn't fail */ 
++    if (pos >= IFX_MSI_IRQ_NUM) {
++        if (request_private_bits) {
++            IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free "
++                  "interrupts, trying just one", __func__, 1 << request_private_bits);
++            request_private_bits = 0;
++            goto again;
++        }
++        else {
++            printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__);
++            return -EINVAL;
++        }
++    } 
++    irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;
++    irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx);
++
++    /*
++     * Initialize MSI. This has to match the memory-write endianess from the device 
++     * Address bits [23:12]
++     */
++    spin_lock(&ifx_pcie_msi_lock); 
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |
++                    SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |
++                    SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++
++    /* Enable this entry */
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;
++    spin_unlock(&ifx_pcie_msi_lock);
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n",
++        pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);
++
++    /* Update the number of IRQs the device has available to it */
++    control &= ~PCI_MSI_FLAGS_QSIZE;
++    control |= (request_private_bits << 4);
++    pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);
++
++    set_irq_msi(irq, desc);
++    msg.address_hi = 0x0;
++    msg.address_lo = msi_irqs[pcie_port].msi_phy_base;
++    msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data);
++
++    write_msi_msg(irq, &msg);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++    return 0;
++}
++
++static int
++pcie_msi_irq_to_port(unsigned int irq, int *port)
++{
++    int ret = 0;
++
++    if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||
++        irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {
++        *port = IFX_PCIE_PORT0;
++    }
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||
++        irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {
++        *port = IFX_PCIE_PORT1;
++    }
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++    else {
++        printk(KERN_ERR "%s: Attempted to teardown illegal " 
++            "MSI interrupt (%d)\n", __func__, irq);
++        ret = -EINVAL;
++    }
++    return ret;
++}
++
++/** 
++ * \fn void arch_teardown_msi_irq(unsigned int irq)
++ * \brief Called when a device no longer needs its MSI interrupts. All 
++ * MSI interrupts for the device are freed. 
++ * 
++ * \param irq   The devices first irq number. There may be multple in sequence.
++ * \return none
++ * \ingroup IFX_PCIE_MSI
++ */
++void 
++arch_teardown_msi_irq(unsigned int irq)
++{
++    int pos;
++    int number_irqs; 
++    u16 bitmask;
++    int pcie_port;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__);
++
++    BUG_ON(irq > INT_NUM_IM4_IRL31);
++
++    if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {
++        return;
++    }
++
++    /* Shift the mask to the correct bit location, not always correct 
++     * Probally, the first match will be chosen.
++     */
++    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {
++        if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) 
++            && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {
++            break;
++        }
++    }
++    if (pos >= IFX_MSI_IRQ_NUM) {
++        printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__);
++        return;
++    }
++    spin_lock(&ifx_pcie_msi_lock);
++    /* Disable this entry */
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);
++    spin_unlock(&ifx_pcie_msi_lock); 
++    /*
++     * Count the number of IRQs we need to free by looking at the
++     * msi_multiple_irq_bitmask. Each bit set means that the next
++     * IRQ is also owned by this device.
++     */ 
++    number_irqs = 0; 
++    while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && 
++        (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {
++        number_irqs++;
++    }
++    number_irqs++;
++
++    /* Mask with one bit for each IRQ */
++    bitmask = (1 << number_irqs) - 1;
++
++    bitmask <<= pos;
++    if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {
++        printk(KERN_ERR "%s: Attempted to teardown MSI "
++             "interrupt (%d) not in use\n", __func__, irq);
++        return;
++    }
++    /* Checks are done, update the in use bitmask */
++    spin_lock(&ifx_pcie_msi_lock);
++    msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;
++    msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);
++    spin_unlock(&ifx_pcie_msi_lock);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_phy.c
+@@ -0,0 +1,478 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_phy.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe PHY sub module
++**
++** DATE         : 14 May 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    14 May,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_phy.c
++ \ingroup IFX_PCIE  
++ \brief PCIe PHY PLL register programming source file
++*/
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/paccess.h>
++#include <linux/delay.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++/* PCIe PDI only supports 16 bit operation */
++
++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \
++    ((*(volatile u16 *) (__addr)) = (__data))
++    
++#define IFX_PCIE_PHY_REG_READ16(__addr)  \
++    (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG16(__addr)   \
++    (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \
++    u16 read_data;                                    \
++    u16 write_data;                                   \
++    read_data = IFX_PCIE_PHY_REG_READ16((__reg));      \
++    write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\
++    IFX_PCIE_PHY_REG_WRITE16((__reg), write_data);               \
++} while (0)
++
++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */
++
++//#define IFX_PCI_PHY_REG_DUMP
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++static void
++pcie_phy_reg_dump(int pcie_port) 
++{
++    printk("PLL REGFILE\n");
++    printk("PCIE_PHY_PLL_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL3    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL4    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL5    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL6    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL7    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL3  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port)));
++    printk("PCIE_PHY_PLL_STATUS   0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)));
++
++    printk("TX1 REGFILE\n");
++    printk("PCIE_PHY_TX1_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX1_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX1_CTRL3    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port)));
++    printk("PCIE_PHY_TX1_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX1_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD1     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD2     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD3     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port)));
++
++    printk("TX2 REGFILE\n");
++    printk("PCIE_PHY_TX2_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX2_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX2_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX2_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD1     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD2     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD3     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port)));
++
++    printk("RX1 REGFILE\n");
++    printk("PCIE_PHY_RX1_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port)));
++    printk("PCIE_PHY_RX1_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port)));
++    printk("PCIE_PHY_RX1_CDR      0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port)));
++    printk("PCIE_PHY_RX1_EI       0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port)));
++    printk("PCIE_PHY_RX1_A_CTRL   0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port)));
++}
++#endif /* IFX_PCI_PHY_REG_DUMP */
++
++static void
++pcie_phy_comm_setup(int pcie_port)
++{
++   /* PLL Setting */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++    /* increase the bias reference voltage */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++    /* Endcnt */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++    /* force */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++    /* ctrl_lim */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++    /* ctrl */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++    /* RTERM*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++    /* Improved 100MHz clock output  */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++    /* Reduced CDR BW to avoid glitches */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++}
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++static void 
++pcie_phy_36mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE
++static void 
++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++
++    /* PLL Setting */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++    /* Increase the bias reference voltage */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++    /* Endcnt */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++    /* Force */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++    /* Predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++    /* ctrl_lim */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++    /* ctrl */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++    /* RTERM*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100);
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF);
++
++    /* improved 100MHz clock output  */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++    /* reduced CDR BW to avoid glitches */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++    
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE
++static void 
++pcie_phy_25mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* pll_ensdm */    
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200);
++
++    /* en_ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE
++static void 
++pcie_phy_100mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif 
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */
++
++static int
++pcie_phy_wait_startup_ready(int pcie_port)
++{
++    int i;
++
++    for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) {
++        if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) {
++            break;
++        }
++        udelay(10);
++    }
++    if (i >= IFX_PCIE_PLL_TIMEOUT) {
++        printk(KERN_ERR "%s PLL Link timeout\n", __func__);
++        return -1;
++    }
++    return 0;
++}
++
++static void 
++pcie_phy_load_enable(int pcie_port, int slice) 
++{
++    /* Set the load_en of tx/rx slice to '1' */
++    switch (slice) {
++        case 1:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010);
++            break;
++        case 2:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010);
++            break;
++        case 3:
++            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002);
++            break;
++    }
++}
++
++static void 
++pcie_phy_load_disable(int pcie_port, int slice) 
++{ 
++    /* set the load_en of tx/rx slice to '0' */ 
++    switch (slice) {
++        case 1:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010);
++            break;
++        case 2:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010);
++            break;
++        case 3: 
++            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002);
++            break;
++    }
++}
++
++static void 
++pcie_phy_load_war(int pcie_port)
++{
++    int slice;
++
++    for (slice = 1; slice < 4; slice++) {
++        pcie_phy_load_enable(pcie_port, slice);
++        udelay(1);
++        pcie_phy_load_disable(pcie_port, slice);
++    }
++}
++
++static void 
++pcie_phy_tx2_modulation(int pcie_port)
++{
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF);
++    mdelay(1);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void 
++pcie_phy_tx1_modulation(int pcie_port)
++{
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF);
++    mdelay(1);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void
++pcie_phy_tx_modulation_war(int pcie_port)
++{
++    int i;
++
++#define PCIE_PHY_MODULATION_NUM 5 
++    for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) {
++        pcie_phy_tx2_modulation(pcie_port);
++        pcie_phy_tx1_modulation(pcie_port);
++    }
++#undef PCIE_PHY_MODULATION_NUM
++}
++
++void
++pcie_phy_clock_mode_setup(int pcie_port)
++{
++    pcie_pdi_big_endian(pcie_port);
++
++    /* Enable PDI to access PCIe PHY register */
++    pcie_pdi_pmu_enable(pcie_port);
++
++    /* Configure PLL and PHY clock */
++    pcie_phy_comm_setup(pcie_port);
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++    pcie_phy_36mhz_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE)
++    pcie_phy_36mhz_ssc_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE)
++    pcie_phy_25mhz_mode_setup(pcie_port);
++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE)
++    pcie_phy_100mhz_mode_setup(pcie_port);
++#else
++    #error "PCIE PHY Clock Mode must be chosen first!!!!"
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++    /* Enable PCIe PHY and make PLL setting take effect */
++    pcie_phy_pmu_enable(pcie_port);
++
++    /* Check if we are in startup_ready status */
++    pcie_phy_wait_startup_ready(pcie_port);
++
++    pcie_phy_load_war(pcie_port);
++
++    /* Apply TX modulation workarounds */
++    pcie_phy_tx_modulation_war(pcie_port);
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.c
+@@ -0,0 +1,176 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_pm.c
++** PROJECT      : IFX UEIP
++** MODULES      : PCIE Root Complex Driver
++**
++** DATE         : 21 Dec 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIE Root Complex Driver Power Managment
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Lantiq Deutschland GmbH
++**                      Am Campeon 3, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 21 Dec,2009   Lei Chuanhua    First UEIP release
++*******************************************************************************/
++/*!
++  \defgroup IFX_PCIE_PM Power Management functions
++  \ingroup IFX_PCIE
++  \brief IFX PCIE Root Complex Driver power management functions
++*/
++
++/*!
++ \file ifxmips_pcie_pm.c
++ \ingroup IFX_PCIE    
++ \brief source file for PCIE Root Complex Driver Power Management
++*/
++
++#ifndef EXPORT_SYMTAB
++#define EXPORT_SYMTAB
++#endif
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/system.h>
++
++/* Project header */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/ifx_pmcu.h>
++#include "ifxmips_pcie_pm.h"
++
++/** 
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++ * \brief the callback function to request pmcu state in the power management hardware-dependent module
++ *
++ * \param pmcuState This parameter is a PMCU state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++{
++    switch(pmcuState) 
++    {
++        case IFX_PMCU_STATE_D0:
++            return IFX_PMCU_RETURN_SUCCESS;
++        case IFX_PMCU_STATE_D1: // Not Applicable
++            return IFX_PMCU_RETURN_DENIED;
++        case IFX_PMCU_STATE_D2: // Not Applicable
++            return IFX_PMCU_RETURN_DENIED;
++        case IFX_PMCU_STATE_D3: // Module clock gating and Power gating
++            return IFX_PMCU_RETURN_SUCCESS;
++        default:
++            return IFX_PMCU_RETURN_DENIED;
++    }
++}
++
++/** 
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++ * \brief the callback function to get pmcu state in the power management hardware-dependent module
++
++ * \param pmcuState Pointer to return power state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ * 
++ * \param   pmcuModule      Module
++ * \param   newState        New state
++ * \param   oldState        Old state
++ * \return  IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return  IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ * 
++ * \param   pmcuModule      Module
++ * \param   newState        New state
++ * \param   oldState        Old state
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/** 
++ * \fn static void ifx_pcie_pmcu_init(void)
++ * \brief Register with central PMCU module
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_init(void)
++{
++    IFX_PMCU_REGISTER_t pmcuRegister;
++
++    /* XXX, hook driver context */
++
++    /* State function register */
++    memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t));
++    pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++    pmcuRegister.pmcuModuleNr = 0;
++    pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change;
++    pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get;
++    pmcuRegister.pre = ifx_pcie_pmcu_prechange;
++    pmcuRegister.post= ifx_pcie_pmcu_postchange;
++    ifx_pmcu_register(&pmcuRegister); 
++}
++
++/** 
++ * \fn static void ifx_pcie_pmcu_exit(void)
++ * \brief Unregister with central PMCU module
++ *
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_exit(void)
++{
++    IFX_PMCU_REGISTER_t pmcuUnRegister;
++
++   /* XXX, hook driver context */
++   
++    pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++    pmcuUnRegister.pmcuModuleNr = 0;
++    ifx_pmcu_unregister(&pmcuUnRegister);
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_pm.h
++** PROJECT      : IFX UEIP
++** MODULES      : PCIe Root Complex Driver
++**
++** DATE         : 21 Dec 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver Power Managment
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Lantiq Deutschland GmbH
++**                      Am Campeon 3, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 21 Dec,2009   Lei Chuanhua    First UEIP release
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_pm.h
++ \ingroup IFX_PCIE 
++ \brief header file for PCIe Root Complex Driver Power Management
++*/
++
++#ifndef IFXMIPS_PCIE_PM_H
++#define IFXMIPS_PCIE_PM_H
++
++void ifx_pcie_pmcu_init(void);
++void ifx_pcie_pmcu_exit(void);
++
++#endif /* IFXMIPS_PCIE_PM_H  */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_reg.h
+@@ -0,0 +1,1001 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_reg.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE        0x1D000000UL
++#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE        0x1C000000UL
++#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE         0x1D800000UL
++#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE        0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE        0x1F106800UL
++#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE            0x400
++
++#define PCIE1_CFG_PHY_BASE        0x19000000UL
++#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE        0x18000000UL
++#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE         0x19800000UL
++#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE        0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE        0x1F700400UL
++#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE            0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4
++
++#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S            9
++
++#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++    PCIE_RC_DR_D0 = 0,
++    PCIE_RC_DR_D1,   /* Not supported */
++    PCIE_RC_DR_D2,   /* Not supported */
++    PCIE_RC_DR_D3,
++    PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S              4
++#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S             9
++#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S                0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S               0
++#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S             5
++#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S                 12
++#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S               18
++#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S                22
++
++/* Format Definition */
++enum {
++    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/
++    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */
++    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */
++    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++    PCIE_VM_MSG_TC0 = 0,
++    PCIE_VM_MSG_TC1,
++    PCIE_VM_MSG_TC2,
++    PCIE_VM_MSG_TC3,
++    PCIE_VM_MSG_TC4,
++    PCIE_VM_MSG_TC5,
++    PCIE_VM_MSG_TC6,
++    PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */
++    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */
++    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/
++    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN  0
++#define PCIE_VM_MSG_LEN_MAX  1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8
++#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S              16
++#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S               24
++
++#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S             3
++#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S               5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S             0
++#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA                       0x00002000  /* INTA */
++#define PCIE_IRN_INTB                       0x00004000  /* INTB */
++#define PCIE_IRN_INTC                       0x00008000  /* INTC */
++#define PCIE_IRN_INTD                       0x00010000  /* INTD */
++#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S           0
++#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S         8
++#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S               16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4
++#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S               4
++#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S              20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */
++#define PCIE_PMBL_64BIT_ADDR                    0x00000001
++#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S                 4
++#define PCIE_PMBL_E64MA                         0x00010000
++#define PCIE_PMBL_END_ADDR                      0xFFF00000
++#define PCIE_PMBL_END_ADDR_S                    20
++#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */
++#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16
++
++#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S               0
++#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S                8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++    PCIE_INTRBCTRL_INT_NON = 0,
++    PCIE_INTRBCTRL_INTA,
++    PCIE_INTRBCTRL_INTB,
++    PCIE_INTRBCTRL_INTC,
++    PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S         0
++#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S           0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8
++#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S        17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20
++#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */
++#define PCIE_MD_DATA_S                    0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S                    0
++#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S              8
++#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S                   16
++#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S         20
++#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S           25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0
++#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S          3
++#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S        6
++#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S         9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++    PCIE_MAX_PAYLOAD_128 = 0,
++    PCIE_MAX_PAYLOAD_256,
++    PCIE_MAX_PAYLOAD_512,
++    PCIE_MAX_PAYLOAD_1024,
++    PCIE_MAX_PAYLOAD_2048,
++    PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5
++#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++                                  PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S             0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4
++#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S                 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12
++#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S            15
++#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */
++#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */
++#define PCIE_LCAP_PORT_NUM_S                   24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES  0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2   0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4   0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8   0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16  0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32  0x20
++
++/* Active State Link PM definition */
++enum {
++    PCIE_ASPM_RES0                = 0,
++    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */
++    PCIE_ASPM_RES1,
++    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */
++    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */
++    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */
++    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */
++    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */
++    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */
++    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */
++    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */
++};
++
++/* L1 Exit Latency definition */
++enum {
++    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */
++    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */
++    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */
++    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */
++    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */
++    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */
++    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */
++    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S          0
++#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S           16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S                 0
++#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */
++#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S               0
++#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S              16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */
++#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \
++                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */
++#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */
++#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S          0
++#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S              27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S                  0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4
++#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S                     8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN   0
++#define PCIE_EXT_VC_CNT_MAX   7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR                0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24
++
++/* Port VC Control and Status Register */     
++#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S            1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17
++#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S                 24
++#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16
++
++/* Other Message Register */
++#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S                 0
++#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */
++#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */
++#define PCIE_PFLR_LINK_STATE_S               16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */
++#define PCIE_AFR_AF_S                        0
++#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S                   8
++#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S               16
++#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24
++#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S          27
++#define PCIE_AFR_FTS_NUM_DEFAULT             32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  
++#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S                16
++#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S             0
++#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */
++#define PCIE_SNR_TS_S                        0
++#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S                       8
++#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S              14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19
++#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S                  28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S          0
++#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12
++
++/* Queue Status Register */
++#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21
++
++/* Applicable to the above three registers */
++enum {
++    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,
++    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/* 
++ * PCIe PDI PHY register definition, suppose all the following 
++ * stuff is confidential. 
++ * XXX, detailed bit definition
++ */
++#define	PCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define	PCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define	PCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define	PCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define	PCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define	PCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define	PCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define	PCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define	PCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define	PCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define	PCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++ 
++#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA  1
++#define PCIE_LEGACY_INTB  2
++#define PCIE_LEGACY_INTC  3
++#define PCIE_LEGACY_INTD  4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#endif /* IFXMIPS_PCIE_REG_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -0,0 +1,284 @@
++/****************************************************************************
++                              Copyright (c) 2010
++                            Lantiq Deutschland GmbH
++                     Am Campeon 3; 85579 Neubiberg, Germany
++
++  For licensing information, see the file 'LICENSE' in the root folder of
++  this software module.
++
++ *****************************************************************************/
++/*!
++  \file ifxmips_pcie_vr9.h
++  \ingroup IFX_PCIE
++  \brief PCIe RC driver vr9 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_VR9_H
++#define IFXMIPS_PCIE_VR9_H
++
++#include <linux/types.h>
++#include <linux/delay.h>
++
++#include <linux/gpio.h>
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET  494
++
++#define IFX_REG_R32    ltq_r32
++#define IFX_REG_W32    ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU                                 (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S                    0x00000008  /* Configure AHB slave port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY   (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL  (1)
++#define IFX_PMU1_MODULE_PDI        (4)
++#define IFX_PMU1_MODULE_MSI        (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++#define IFX_GPIO				(KSEG1 | 0x1E100B00)
++#define ALT0			((volatile u32*)(IFX_GPIO + 0x007c))
++#define ALT1			((volatile u32*)(IFX_GPIO + 0x0080))
++#define OD			((volatile u32*)(IFX_GPIO + 0x0084))
++#define DIR			((volatile u32*)(IFX_GPIO + 0x0078))
++#define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++
++	gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
++	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++
++/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
++}
++
++static inline void pcie_ahb_pmu_setup(void) 
++{
++	/* Enable AHB bus master/slave */
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "ahb");
++	clk_enable(clk);
++
++    //AHBM_PMU_SETUP(IFX_PMU_ENABLE);
++    //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg |= IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else 
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "phy");
++	clk_enable(clk);
++
++	//PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "phy");
++	clk_disable(clk);
++
++//    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    /* SRAM2PDI endianness control. */
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Config AHB->PCIe and PDI endianness */
++    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++    /* Enable PDI to access PCIe PHY register */
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "pdi");
++	clk_enable(clk);
++    //PDI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
++    reg |= 0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    /* Reset PCIe PHY & Core, bit 22 */
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg |= 0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "ctl");
++	clk_enable(clk);
++	clk = clk_get_sys("1d900000.pcie", "bus");
++	clk_enable(clk);
++
++    /* PCIe Core controller enabled */
++//    PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++
++    /* Enable PCIe L0 Clock */
++//  PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++	struct clk *clk;
++	pcie_msi_pic_init(pcie_port);
++	clk = clk_get_sys("ltq_pcie", "msi");
++	clk_enable(clk);
++//    MSI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++    if (pcibios_host_nr() > 1) {
++        tbus_number -= pcibios_1st_host_bus_nr();
++    }
++#endif /* CONFIG_PCI_LANTIQ */
++    return tbus_number;
++}
++
++static inline struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++        }
++    #endif /* CONFIG_PCI_LANTIQ */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
+--- a/arch/mips/pci/pci-legacy.c
++++ b/arch/mips/pci/pci-legacy.c
+@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str)
+ 		return pcibios_plat_setup(str);
+ 	return str;
+ }
++
++int pcibios_host_nr(void)
++{
++    int count = 0;
++    struct pci_controller *hose;
++    list_for_each_entry(hose, &controllers, list) {
++        count++;
++    }
++    return count;
++}
++EXPORT_SYMBOL(pcibios_host_nr);
++
++int pcibios_1st_host_bus_nr(void)
++{
++    int bus_nr = 0;
++    struct pci_controller *hose;
++
++    hose = list_first_entry_or_null(&controllers, struct pci_controller, list);
++
++    if (hose != NULL) {
++        if (hose->bus != NULL) {
++            bus_nr = hose->bus->number + 1;
++        }
++    }
++    return bus_nr;
++}
++EXPORT_SYMBOL(pcibios_1st_host_bus_nr);
+--- /dev/null
++++ b/arch/mips/pci/pcie-lantiq.h
+@@ -0,0 +1,1316 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_reg.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE        0x1D000000UL
++#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE        0x1C000000UL
++#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE         0x1D800000UL
++#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE        0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE        0x1F106800UL
++#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE            0x400
++
++#define PCIE1_CFG_PHY_BASE        0x19000000UL
++#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE        0x18000000UL
++#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE         0x19800000UL
++#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE        0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE        0x1F700400UL
++#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE            0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4
++
++#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S            9
++
++#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++    PCIE_RC_DR_D0 = 0,
++    PCIE_RC_DR_D1,   /* Not supported */
++    PCIE_RC_DR_D2,   /* Not supported */
++    PCIE_RC_DR_D3,
++    PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S              4
++#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S             9
++#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S                0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S               0
++#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S             5
++#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S                 12
++#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S               18
++#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S                22
++
++/* Format Definition */
++enum {
++    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/
++    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */
++    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */
++    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++    PCIE_VM_MSG_TC0 = 0,
++    PCIE_VM_MSG_TC1,
++    PCIE_VM_MSG_TC2,
++    PCIE_VM_MSG_TC3,
++    PCIE_VM_MSG_TC4,
++    PCIE_VM_MSG_TC5,
++    PCIE_VM_MSG_TC6,
++    PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */
++    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */
++    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/
++    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN  0
++#define PCIE_VM_MSG_LEN_MAX  1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8
++#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S              16
++#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S               24
++
++#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S             3
++#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S               5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S             0
++#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA                       0x00002000  /* INTA */
++#define PCIE_IRN_INTB                       0x00004000  /* INTB */
++#define PCIE_IRN_INTC                       0x00008000  /* INTC */
++#define PCIE_IRN_INTD                       0x00010000  /* INTD */
++#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S           0
++#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S         8
++#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S               16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4
++#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S               4
++#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S              20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */
++#define PCIE_PMBL_64BIT_ADDR                    0x00000001
++#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S                 4
++#define PCIE_PMBL_E64MA                         0x00010000
++#define PCIE_PMBL_END_ADDR                      0xFFF00000
++#define PCIE_PMBL_END_ADDR_S                    20
++#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */
++#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16
++
++#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S               0
++#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S                8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++    PCIE_INTRBCTRL_INT_NON = 0,
++    PCIE_INTRBCTRL_INTA,
++    PCIE_INTRBCTRL_INTB,
++    PCIE_INTRBCTRL_INTC,
++    PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S         0
++#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S           0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8
++#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S        17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20
++#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */
++#define PCIE_MD_DATA_S                    0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S                    0
++#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S              8
++#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S                   16
++#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S         20
++#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S           25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0
++#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S          3
++#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S        6
++#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S         9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++    PCIE_MAX_PAYLOAD_128 = 0,
++    PCIE_MAX_PAYLOAD_256,
++    PCIE_MAX_PAYLOAD_512,
++    PCIE_MAX_PAYLOAD_1024,
++    PCIE_MAX_PAYLOAD_2048,
++    PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5
++#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++                                  PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S             0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4
++#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S                 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12
++#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S            15
++#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */
++#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */
++#define PCIE_LCAP_PORT_NUM_S                   24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES  0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2   0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4   0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8   0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16  0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32  0x20
++
++/* Active State Link PM definition */
++enum {
++    PCIE_ASPM_RES0                = 0,
++    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */
++    PCIE_ASPM_RES1,
++    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */
++    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */
++    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */
++    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */
++    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */
++    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */
++    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */
++    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */
++};
++
++/* L1 Exit Latency definition */
++enum {
++    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */
++    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */
++    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */
++    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */
++    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */
++    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */
++    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */
++    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S          0
++#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S           16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S                 0
++#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */
++#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S               0
++#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S              16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */
++#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \
++                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */
++#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */
++#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S          0
++#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S              27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S                  0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4
++#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S                     8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN   0
++#define PCIE_EXT_VC_CNT_MAX   7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR                0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24
++
++/* Port VC Control and Status Register */     
++#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S            1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17
++#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S                 24
++#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16
++
++/* Other Message Register */
++#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S                 0
++#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */
++#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */
++#define PCIE_PFLR_LINK_STATE_S               16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */
++#define PCIE_AFR_AF_S                        0
++#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S                   8
++#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S               16
++#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24
++#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S          27
++#define PCIE_AFR_FTS_NUM_DEFAULT             32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  
++#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S                16
++#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S             0
++#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */
++#define PCIE_SNR_TS_S                        0
++#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S                       8
++#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S              14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19
++#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S                  28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S          0
++#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12
++
++/* Queue Status Register */
++#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21
++
++/* Applicable to the above three registers */
++enum {
++    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,
++    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/* 
++ * PCIe PDI PHY register definition, suppose all the following 
++ * stuff is confidential. 
++ * XXX, detailed bit definition
++ */
++#define	PCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define	PCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define	PCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define	PCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define	PCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define	PCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define	PCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define	PCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define	PCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define	PCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define	PCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++ 
++#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA  1
++#define PCIE_LEGACY_INTB  2
++#define PCIE_LEGACY_INTC  3
++#define PCIE_LEGACY_INTD  4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#define PCIE_IRQ_LOCK(lock) do {             \
++    unsigned long flags;                     \
++    spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock)                \
++    spin_unlock_irqrestore(&(lock), flags);  \
++} while (0)
++
++#define PCIE_MSG_MSI        0x00000001
++#define PCIE_MSG_ISR        0x00000002
++#define PCIE_MSG_FIXUP      0x00000004
++#define PCIE_MSG_READ_CFG   0x00000008
++#define PCIE_MSG_WRITE_CFG  0x00000010
++#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG        0x00000020
++#define PCIE_MSG_INIT       0x00000040
++#define PCIE_MSG_ERR        0x00000080
++#define PCIE_MSG_PHY        0x00000100
++#define PCIE_MSG_ANY        0x000001ff
++
++#define IFX_PCIE_PORT0      0
++#define IFX_PCIE_PORT1      1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR    2
++#else
++#define IFX_PCIE_CORE_NR    1
++#endif
++
++//#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \
++    if (g_pcie_debug_flag & (_m)) {              \
++        ifx_pcie_debug((_fmt), ##args);          \
++    }                                            \
++} while (0)
++
++#define INLINE 
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...)   \
++    do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++	struct pci_controller   pcic;
++    
++	/* RC specific, per host bus information */
++	u32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++    const unsigned int irq;
++    const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++    const u32 irq_bit;
++    const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++    ifx_pcie_ir_irq_t ir_irq;
++    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/clk.h>
++
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET  38
++#define IFX_REG_R32	ltq_r32
++#define IFX_REG_W32	ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU                                 (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY   (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL  (1)
++#define IFX_PMU1_MODULE_PDI        (4)
++#define IFX_PMU1_MODULE_MSI        (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++}
++
++static inline void pcie_ahb_pmu_setup(void)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "ahb");
++	clk_enable(clk);
++	//ltq_pmu_enable(PMU_AHBM | PMU_AHBS);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg |= IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else 
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "phy");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "phy");
++	clk_disable(clk);
++	//ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    /* SRAM2PDI endianness control. */
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Config AHB->PCIe and PDI endianness */
++    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "pdi");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
++    reg |= 0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    /* Reset PCIe PHY & Core, bit 22 */
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg |= 0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++  //  ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++//    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "ctl");
++	clk_enable(clk);
++	clk = clk_get_sys("ltq_pcie", "bus");
++	clk_enable(clk);
++
++	//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL);
++	//ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++	struct clk *clk;
++    pcie_msi_pic_init(pcie_port);
++	clk = clk_get_sys("ltq_pcie", "msi");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++    if (pcibios_host_nr() > 1) {
++        tbus_number -= pcibios_1st_host_bus_nr();
++    }
++#endif /* CONFIG_PCI_LANTIQ */
++    return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++        }
++    #endif /* CONFIG_PCI_LANTIQ */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
++
+--- a/drivers/pci/pcie/Kconfig
++++ b/drivers/pci/pcie/Kconfig
+@@ -51,6 +51,7 @@ config PCIEAER_INJECT
+ config PCIE_ECRC
+ 	bool "PCI Express ECRC settings control"
+ 	depends on PCIEAER
++	default n
+ 	help
+ 	  Used to override firmware/bios settings for PCI Express ECRC
+ 	  (transaction layer end-to-end CRC checking).
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1558,6 +1558,8 @@ void pci_walk_bus_locked(struct pci_bus
+ 			 void *userdata);
+ int pci_cfg_space_size(struct pci_dev *dev);
+ unsigned char pci_bus_max_busnr(struct pci_bus *bus);
++int pcibios_host_nr(void);
++int pcibios_1st_host_bus_nr(void);
+ void pci_setup_bridge(struct pci_bus *bus);
+ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
+ 					 unsigned long type);
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1097,6 +1097,12 @@
+ #define PCI_DEVICE_ID_SGI_IOC3		0x0003
+ #define PCI_DEVICE_ID_SGI_LITHIUM	0x1002
+ 
++#define PCI_VENDOR_ID_INFINEON		0x15D1
++#define PCI_DEVICE_ID_INFINEON_DANUBE	0x000F
++#define PCI_DEVICE_ID_INFINEON_PCIE	0x0011
++#define PCI_VENDOR_ID_LANTIQ		0x1BEF
++#define PCI_DEVICE_ID_LANTIQ_PCIE	0x0011
++
+ #define PCI_VENDOR_ID_WINBOND		0x10ad
+ #define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+ #define PCI_DEVICE_ID_WINBOND_83C553	0x0565
diff --git a/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch b/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
new file mode 100644
index 0000000000..6b70f8b9a7
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
@@ -0,0 +1,62 @@
+From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 6 May 2024 09:41:42 +0200
+Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
+
+Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
+only switched to the gpiod API, but also inverted / changed the polarity
+of the GPIO.
+
+According to the PCI specification, the RST# pin is an active-low
+signal. However, most of the device trees that have been widely used for
+a long time (mainly in the openWrt project) define this GPIO as
+active-high and the old driver code inverted the signal internally.
+
+Apparently there are actually boards where the reset gpio must be
+operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
+flag for initialization. Instead, we must explicitly set the gpio to
+value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
+may have been set.
+
+In order to remain compatible with all these existing device trees, we
+should therefore keep the logic as it was before the commit.
+
+Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/pci/pci-lantiq.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
+ 		clk_disable(clk_external);
+ 
+ 	/* setup reset gpio used by pci */
+-	reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+-					     GPIOD_OUT_LOW);
++	reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
+ 	error = PTR_ERR_OR_ZERO(reset_gpio);
+ 	if (error) {
+ 		dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
+ 		return error;
+ 	}
+ 	gpiod_set_consumer_name(reset_gpio, "pci_reset");
++	gpiod_direction_output(reset_gpio, 1);
+ 
+ 	/* enable auto-switching between PCI and EBU */
+ 	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
+@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
+ 
+ 	/* toggle reset pin */
+ 	if (reset_gpio) {
+-		gpiod_set_value_cansleep(reset_gpio, 1);
++		gpiod_set_value_cansleep(reset_gpio, 0);
+ 		wmb();
+ 		mdelay(1);
+-		gpiod_set_value_cansleep(reset_gpio, 0);
++		gpiod_set_value_cansleep(reset_gpio, 1);
+ 	}
+ 	return 0;
+ }
diff --git a/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch
new file mode 100644
index 0000000000..e32e4e2daa
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0004-MIPS-lantiq-add-atm-hack.patch
@@ -0,0 +1,482 @@
+From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++
+ arch/mips/lantiq/irq.c                         |    2 +
+ arch/mips/mm/cache.c                           |    4 +
+ include/uapi/linux/atm.h                       |    6 +
+ net/atm/common.c                               |    6 +
+ net/atm/proc.c                                 |    2 +-
+ 7 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+@@ -0,0 +1,196 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_atm.h
++** PROJECT      : UEIP
++** MODULES      : ATM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global ATM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_ATM_H
++#define IFX_ATM_H
++
++
++
++/*!
++  \defgroup IFX_ATM UEIP Project - ATM driver module
++  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_ATM_IOCTL IOCTL Commands
++  \ingroup IFX_ATM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_ATM_STRUCT Structures
++  \ingroup IFX_ATM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_atm.h
++  \ingroup IFX_ATM
++  \brief ATM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ATM MIB
++ */
++
++/*!
++  \struct atm_cell_ifEntry_t
++  \brief Structure used for Cell Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
++	__u32	ifInErrors;         /*!< counter of error ingress cells     */
++	__u32	ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
++	__u32	ifOutErrors;        /*!< counter of error egress cells      */
++} atm_cell_ifEntry_t;
++
++/*!
++  \struct atm_aal5_ifEntry_t
++  \brief Structure used for AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
++	__u32	ifInUcastPkts;      /*!< counter of ingress packets         */
++	__u32	ifOutUcastPkts;     /*!< counter of egress packets          */
++	__u32	ifInErrors;         /*!< counter of error ingress packets   */
++	__u32	ifInDiscards;       /*!< counter of dropped ingress packets */
++	__u32	ifOutErros;         /*!< counter of error egress packets    */
++	__u32	ifOutDiscards;      /*!< counter of dropped egress packets  */
++} atm_aal5_ifEntry_t;
++
++/*!
++  \struct atm_aal5_vcc_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  This structure is a part of structure "atm_aal5_vcc_x_t".
++ */
++typedef struct {
++	__u32	aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
++	__u32	aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
++	__u32	aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
++} atm_aal5_vcc_t;
++
++/*!
++  \struct atm_aal5_vcc_x_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
++ */
++typedef struct {
++	int             vpi;        /*!< VPI of the VCC to get MIB counters */
++	int             vci;        /*!< VCI of the VCC to get MIB counters */
++	atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
++} atm_aal5_vcc_x_t;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief ATM IOCTL Magic Number
++ */
++#define PPE_ATM_IOC_MAGIC       'o'
++/*!
++  \brief ATM IOCTL Command - Get Cell Level MIB Counters
++
++   This command is obsolete. User can get cell level MIB from DSL API.
++   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
++
++   Get AAL5 packet counters.
++   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get Per PVC MIB Counters
++
++   Get AAL5 packet counters for each PVC.
++   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
++ */
++#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
++/*!
++  \brief Total Number of ATM IOCTL Commands
++ */
++#define PPE_ATM_IOC_MAXNR       3
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_ATM_H
++
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+@@ -0,0 +1,203 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_ptm.h
++** PROJECT      : UEIP
++** MODULES      : PTM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global PTM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_PTM_H
++#define IFX_PTM_H
++
++
++
++/*!
++  \defgroup IFX_PTM UEIP Project - PTM driver module
++  \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_PTM_IOCTL IOCTL Commands
++  \ingroup IFX_PTM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_PTM_STRUCT Structures
++  \ingroup IFX_PTM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_ptm.h
++  \ingroup IFX_PTM
++  \brief PTM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_PTM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief PTM IOCTL Command - Get codeword MIB counters.
++
++  This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
++ */
++#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1
++/*!
++  \brief PTM IOCTL Command - Get packet MIB counters.
++
++  This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
++ */
++#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2
++/*!
++  \brief PTM IOCTL Command - Get firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3
++/*!
++  \brief PTM IOCTL Command - Set firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4
++/*!
++  \brief PTM IOCTL Command - Program priority value to TX queue mapping.
++
++  This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
++ */
++#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14
++
++/*@}*/
++
++
++/*!
++  \addtogroup IFX_PTM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ioctl Data Type
++ */
++
++/*!
++  \typedef PTM_CW_IF_ENTRY_T
++  \brief Wrapping of structure "ptm_cw_ifEntry_t".
++ */
++/*!
++  \struct ptm_cw_ifEntry_t
++  \brief Structure used for CodeWord level MIB counters.
++ */
++typedef struct ptm_cw_ifEntry_t {
++    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */
++    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */
++    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */
++    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */
++    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */
++} PTM_CW_IF_ENTRY_T;
++
++/*!
++  \typedef PTM_FRAME_MIB_T
++  \brief Wrapping of structure "ptm_frame_mib_t".
++ */
++/*!
++  \struct ptm_frame_mib_t
++  \brief Structure used for packet level MIB counters.
++ */
++typedef struct ptm_frame_mib_t {
++    uint32_t    RxCorrect;      /*!< output, number of ingress packet */
++    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */
++    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */
++    uint32_t    TxSend;         /*!< output, number of egress packet */
++} PTM_FRAME_MIB_T;
++
++/*!
++  \typedef IFX_PTM_CFG_T
++  \brief Wrapping of structure "ptm_cfg_t".
++ */
++/*!
++  \struct ptm_cfg_t
++  \brief Structure used for ETH/TC CRC configuration.
++ */
++typedef struct ptm_cfg_t {
++    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */
++    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */
++    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */
++    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */
++    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */
++    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */
++    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */
++} IFX_PTM_CFG_T;
++
++/*!
++  \typedef IFX_PTM_PRIO_Q_MAP_T
++  \brief Wrapping of structure "ppe_prio_q_map".
++ */
++/*!
++  \struct ppe_prio_q_map
++  \brief Structure used for Priority Value to TX Queue mapping.
++ */
++typedef struct ppe_prio_q_map {
++    int             pkt_prio;
++    int             qid;
++    int             vpi;    //  ignored in eth interface
++    int             vci;    //  ignored in eth interface
++} IFX_PTM_PRIO_Q_MAP_T;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_PTM_H
++
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -13,6 +13,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/module.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d)
+ 	}
+ 	raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
+ }
++EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+ 
+ void ltq_mask_and_ack_irq(struct irq_data *d)
+ {
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_wback);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+ /*
+--- a/include/uapi/linux/atm.h
++++ b/include/uapi/linux/atm.h
+@@ -131,8 +131,14 @@
+ #define ATM_ABR		4
+ #define ATM_ANYCLASS	5		/* compatible with everything */
+ 
++#define ATM_VBR_NRT     ATM_VBR
++#define ATM_VBR_RT      6
++#define ATM_UBR_PLUS    7
++#define ATM_GFR         8
++
+ #define ATM_MAX_PCR	-1		/* maximum available PCR */
+ 
++
+ struct atm_trafprm {
+ 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
+ 	int		max_pcr;	/* maximum PCR in cells per second */
+--- a/net/atm/proc.c
++++ b/net/atm/proc.c
+@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ 	static const char *const class_name[] = {
+-		"off", "UBR", "CBR", "VBR", "ABR"};
++		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ 	static const char *const aal_name[] = {
+ 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
+ 		"???",	"5",	"???",	"???",	/*  4- 7 */
diff --git a/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch
new file mode 100644
index 0000000000..3e6c267685
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch
@@ -0,0 +1,1076 @@
+From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:30:56 +0200
+Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
+ arch/mips/lantiq/xway/Makefile                   |    2 +-
+ arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
+ 3 files changed, 1001 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+ create mode 100644 arch/mips/lantiq/xway/timer.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+@@ -0,0 +1,155 @@
++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++
++
++/******************************************************************************
++       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
++
++                               No Warranty
++   Because the program is licensed free of charge, there is no warranty for
++   the program, to the extent permitted by applicable law.  Except when
++   otherwise stated in writing the copyright holders and/or other parties
++   provide the program "as is" without warranty of any kind, either
++   expressed or implied, including, but not limited to, the implied
++   warranties of merchantability and fitness for a particular purpose. The
++   entire risk as to the quality and performance of the program is with
++   you.  should the program prove defective, you assume the cost of all
++   necessary servicing, repair or correction.
++
++   In no event unless required by applicable law or agreed to in writing
++   will any copyright holder, or any other party who may modify and/or
++   redistribute the program as permitted above, be liable to you for
++   damages, including any general, special, incidental or consequential
++   damages arising out of the use or inability to use the program
++   (including but not limited to loss of data or data being rendered
++   inaccurate or losses sustained by you or third parties or a failure of
++   the program to operate with any other programs), even if such holder or
++   other party has been advised of the possibility of such damages.
++******************************************************************************/
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*
++ *  Available Timer/Counter Index
++ */
++#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
++#define TIMER_ANY                       0x00
++#define TIMER1A                         TIMER(1, 0)
++#define TIMER1B                         TIMER(1, 1)
++#define TIMER2A                         TIMER(2, 0)
++#define TIMER2B                         TIMER(2, 1)
++#define TIMER3A                         TIMER(3, 0)
++#define TIMER3B                         TIMER(3, 1)
++
++/*
++ *  Flag of Timer/Counter
++ *  These flags specify the way in which timer is configured.
++ */
++/*  Bit size of timer/counter.                      */
++#define TIMER_FLAG_16BIT                0x0000
++#define TIMER_FLAG_32BIT                0x0001
++/*  Switch between timer and counter.               */
++#define TIMER_FLAG_TIMER                0x0000
++#define TIMER_FLAG_COUNTER              0x0002
++/*  Stop or continue when overflowing/underflowing. */
++#define TIMER_FLAG_ONCE                 0x0000
++#define TIMER_FLAG_CYCLIC               0x0004
++/*  Count up or counter down.                       */
++#define TIMER_FLAG_UP                   0x0000
++#define TIMER_FLAG_DOWN                 0x0008
++/*  Count on specific level or edge.                */
++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
++#define TIMER_FLAG_RISE_EDGE            0x0010
++#define TIMER_FLAG_FALL_EDGE            0x0020
++#define TIMER_FLAG_ANY_EDGE             0x0030
++/*  Signal is syncronous to module clock or not.    */
++#define TIMER_FLAG_UNSYNC               0x0000
++#define TIMER_FLAG_SYNC                 0x0080
++/*  Different interrupt handle type.                */
++#define TIMER_FLAG_NO_HANDLE            0x0000
++#if defined(__KERNEL__)
++    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
++#endif  //  defined(__KERNEL__)
++#define TIMER_FLAG_SIGNAL               0x0300
++/*  Internal clock source or external clock source  */
++#define TIMER_FLAG_INT_SRC              0x0000
++#define TIMER_FLAG_EXT_SRC              0x1000
++
++
++/*
++ *  ioctl Command
++ */
++#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
++#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
++#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
++#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
++#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
++#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
++#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
++#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
++
++/*
++ *  Data Type Used to Call ioctl
++ */
++struct gptu_ioctl_param {
++    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
++                                                 *  timer/counter. If it's zero, a timer/counter would  *
++                                                 *  be dynamically allocated and ID would be stored in  *
++                                                 *  this field.                                         *
++                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
++                                                 *  ignored.                                            *
++                                                 *  In other command, this field is ID of timer/counter *
++                                                 *  allocated.                                          */
++    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
++                                                 *  specify how to configure timer/counter.             *
++                                                 *  In command GPTU_START_TIMER, zero indicate start    *
++                                                 *  and non-zero indicate resume timer/counter.         *
++                                                 *  In other command, this field is ignored.            */
++    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
++                                                 *  init/reload value.                                  *
++                                                 *  In command GPTU_SET_TIMER, this field contains      *
++                                                 *  frequency (0.001Hz) of timer.                       *
++                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
++                                                 *  value would be stored in this field.                *
++                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
++                                                 *  contains frequency wanted, and after calculation,   *
++                                                 *  divider would be stored in this field to overwrite  *
++                                                 *  the frequency.                                      *
++                                                 *  In other command, this field is ignored.            */
++    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains process  *
++                                                 *  ID to which signal would be sent.                   *
++                                                 *  In other command, this field is ignored.            */
++    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains signal   *
++                                                 *  number which would be sent.                         *
++                                                 *  In other command, this field is ignored.            */
++};
++
++/*
++ * ####################################
++ *              Data Type
++ * ####################################
++ */
++typedef void (*timer_callback)(unsigned long arg);
++
++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
++extern int lq_free_timer(unsigned int);
++extern int lq_start_timer(unsigned int, int);
++extern int lq_stop_timer(unsigned int);
++extern int lq_reset_counter_flags(u32 timer, u32 flags);
++extern int lq_get_count_value(unsigned int, unsigned long *);
++extern u32 lq_cal_divider(unsigned long);
++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
++extern int lq_set_counter(unsigned int timer, unsigned int flag,
++	u32 reload, unsigned long arg1, unsigned long arg2);
++
++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,4 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o
++
++ifdef CONFIG_SOC_AMAZON_SE
++obj-y += gptu.o
++else
++obj-y += timer.o
++endif
+ 
+ obj-y += vmmc.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/timer.c
+@@ -0,0 +1,887 @@
++#ifndef CONFIG_SOC_AMAZON_SE
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/init.h>
++#include <linux/uaccess.h>
++#include <linux/unistd.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/sched/signal.h>
++
++#include <linux/of_platform.h>
++
++#include <asm/irq.h>
++#include <asm/div64.h>
++#include "../clk.h"
++
++#include <lantiq_soc.h>
++#include <lantiq_irq.h>
++#include <lantiq_timer.h>
++
++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS	6
++
++#ifdef TIMER1A
++#define FIRST_TIMER			TIMER1A
++#else
++#define FIRST_TIMER			2
++#endif
++
++/*
++ *  GPTC divider is set or not.
++ */
++#define GPTU_CLC_RMC_IS_SET		0
++
++/*
++ *  Timer Interrupt (IRQ)
++ */
++/*  Must be adjusted when ICU driver is available */
++#define TIMER_INTERRUPT			(INT_NUM_IM3_IRL0 + 22)
++
++/*
++ *  Bits Operation
++ */
++#define GET_BITS(x, msb, lsb)		\
++	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
++#define SET_BITS(x, msb, lsb, value)	\
++	(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
++	(((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
++
++/*
++ *  GPTU Register Mapping
++ */
++#define LQ_GPTU			(KSEG1 + 0x1E100A00)
++#define LQ_GPTU_CLC		((volatile u32 *)(LQ_GPTU + 0x0000))
++#define LQ_GPTU_ID			((volatile u32 *)(LQ_GPTU + 0x0008))
++#define LQ_GPTU_CON(n, X)		((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_RUN(n, X)		((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_RELOAD(n, X)	((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_COUNT(n, X)	((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_IRNEN		((volatile u32 *)(LQ_GPTU + 0x00F4))
++#define LQ_GPTU_IRNICR		((volatile u32 *)(LQ_GPTU + 0x00F8))
++#define LQ_GPTU_IRNCR		((volatile u32 *)(LQ_GPTU + 0x00FC))
++
++/*
++ *  Clock Control Register
++ */
++#define GPTU_CLC_SMC			GET_BITS(*LQ_GPTU_CLC, 23, 16)
++#define GPTU_CLC_RMC			GET_BITS(*LQ_GPTU_CLC, 15, 8)
++#define GPTU_CLC_FSOE			(*LQ_GPTU_CLC & (1 << 5))
++#define GPTU_CLC_EDIS			(*LQ_GPTU_CLC & (1 << 3))
++#define GPTU_CLC_SPEN			(*LQ_GPTU_CLC & (1 << 2))
++#define GPTU_CLC_DISS			(*LQ_GPTU_CLC & (1 << 1))
++#define GPTU_CLC_DISR			(*LQ_GPTU_CLC & (1 << 0))
++
++#define GPTU_CLC_SMC_SET(value)		SET_BITS(0, 23, 16, (value))
++#define GPTU_CLC_RMC_SET(value)		SET_BITS(0, 15, 8, (value))
++#define GPTU_CLC_FSOE_SET(value)	((value) ? (1 << 5) : 0)
++#define GPTU_CLC_SBWE_SET(value)	((value) ? (1 << 4) : 0)
++#define GPTU_CLC_EDIS_SET(value)	((value) ? (1 << 3) : 0)
++#define GPTU_CLC_SPEN_SET(value)	((value) ? (1 << 2) : 0)
++#define GPTU_CLC_DISR_SET(value)	((value) ? (1 << 0) : 0)
++
++/*
++ *  ID Register
++ */
++#define GPTU_ID_ID			GET_BITS(*LQ_GPTU_ID, 15, 8)
++#define GPTU_ID_CFG			GET_BITS(*LQ_GPTU_ID, 7, 5)
++#define GPTU_ID_REV			GET_BITS(*LQ_GPTU_ID, 4, 0)
++
++/*
++ *  Control Register of Timer/Counter nX
++ *    n is the index of block (1 based index)
++ *    X is either A or B
++ */
++#define GPTU_CON_SRC_EG(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 10))
++#define GPTU_CON_SRC_EXT(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 9))
++#define GPTU_CON_SYNC(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 8))
++#define GPTU_CON_EDGE(n, X)		GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
++#define GPTU_CON_INV(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 5))
++#define GPTU_CON_EXT(n, X)		(*LQ_GPTU_CON(n, A) & (1 << 4))	/* Timer/Counter B does not have this bit */
++#define GPTU_CON_STP(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 3))
++#define GPTU_CON_CNT(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 2))
++#define GPTU_CON_DIR(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 1))
++#define GPTU_CON_EN(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 0))
++
++#define GPTU_CON_SRC_EG_SET(value)	((value) ? 0 : (1 << 10))
++#define GPTU_CON_SRC_EXT_SET(value)	((value) ? (1 << 9) : 0)
++#define GPTU_CON_SYNC_SET(value)	((value) ? (1 << 8) : 0)
++#define GPTU_CON_EDGE_SET(value)	SET_BITS(0, 7, 6, (value))
++#define GPTU_CON_INV_SET(value)		((value) ? (1 << 5) : 0)
++#define GPTU_CON_EXT_SET(value)		((value) ? (1 << 4) : 0)
++#define GPTU_CON_STP_SET(value)		((value) ? (1 << 3) : 0)
++#define GPTU_CON_CNT_SET(value)		((value) ? (1 << 2) : 0)
++#define GPTU_CON_DIR_SET(value)		((value) ? (1 << 1) : 0)
++
++#define GPTU_RUN_RL_SET(value)		((value) ? (1 << 2) : 0)
++#define GPTU_RUN_CEN_SET(value)		((value) ? (1 << 1) : 0)
++#define GPTU_RUN_SEN_SET(value)		((value) ? (1 << 0) : 0)
++
++#define GPTU_IRNEN_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++#define GPTU_IRNCR_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++
++#define TIMER_FLAG_MASK_SIZE(x)		(x & 0x0001)
++#define TIMER_FLAG_MASK_TYPE(x)		(x & 0x0002)
++#define TIMER_FLAG_MASK_STOP(x)		(x & 0x0004)
++#define TIMER_FLAG_MASK_DIR(x)		(x & 0x0008)
++#define TIMER_FLAG_NONE_EDGE		0x0000
++#define TIMER_FLAG_MASK_EDGE(x)		(x & 0x0030)
++#define TIMER_FLAG_REAL			0x0000
++#define TIMER_FLAG_INVERT		0x0040
++#define TIMER_FLAG_MASK_INVERT(x)	(x & 0x0040)
++#define TIMER_FLAG_MASK_TRIGGER(x)	(x & 0x0070)
++#define TIMER_FLAG_MASK_SYNC(x)		(x & 0x0080)
++#define TIMER_FLAG_CALLBACK_IN_HB	0x0200
++#define TIMER_FLAG_MASK_HANDLE(x)	(x & 0x0300)
++#define TIMER_FLAG_MASK_SRC(x)		(x & 0x1000)
++
++struct timer_dev_timer {
++	unsigned int f_irq_on;
++	unsigned int irq;
++	unsigned int flag;
++	unsigned long arg1;
++	unsigned long arg2;
++};
++
++struct timer_dev {
++	struct mutex gptu_mutex;
++	unsigned int number_of_timers;
++	unsigned int occupation;
++	unsigned int f_gptu_on;
++	struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
++};
++
++
++unsigned int ltq_get_fpi_bus_clock(int fpi) {
++	struct clk *clk = clk_get_fpi();
++	return clk_get_rate(clk);
++}
++
++
++static long gptu_ioctl(struct file *, unsigned int, unsigned long);
++static int gptu_open(struct inode *, struct file *);
++static int gptu_release(struct inode *, struct file *);
++
++static struct file_operations gptu_fops = {
++	.owner = THIS_MODULE,
++	.unlocked_ioctl = gptu_ioctl,
++	.open = gptu_open,
++	.release = gptu_release
++};
++
++static struct miscdevice gptu_miscdev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "gptu",
++	.fops = &gptu_fops,
++};
++
++static struct timer_dev timer_dev;
++
++static irqreturn_t timer_irq_handler(int irq, void *p)
++{
++	unsigned int timer;
++	unsigned int flag;
++	struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
++
++	timer = irq - TIMER_INTERRUPT;
++	if (timer < timer_dev.number_of_timers
++		&& dev_timer == &timer_dev.timer[timer]) {
++		/*  Clear interrupt.    */
++		ltq_w32(1 << timer, LQ_GPTU_IRNCR);
++
++		/*  Call user hanler or signal. */
++		flag = dev_timer->flag;
++		if (!(timer & 0x01)
++			|| TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++			/* 16-bit timer or timer A of 32-bit timer  */
++			switch (TIMER_FLAG_MASK_HANDLE(flag)) {
++			case TIMER_FLAG_CALLBACK_IN_IRQ:
++			case TIMER_FLAG_CALLBACK_IN_HB:
++				if (dev_timer->arg1)
++					(*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
++				break;
++			case TIMER_FLAG_SIGNAL:
++				send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
++				break;
++			}
++		}
++	}
++	return IRQ_HANDLED;
++}
++
++static inline void lq_enable_gptu(void)
++{
++	struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++	clk_enable(clk);
++
++	//ltq_pmu_enable(PMU_GPT);
++
++	/*  Set divider as 1, disable write protection for SPEN, enable module. */
++	*LQ_GPTU_CLC =
++		GPTU_CLC_SMC_SET(0x00) |
++		GPTU_CLC_RMC_SET(0x01) |
++		GPTU_CLC_FSOE_SET(0) |
++		GPTU_CLC_SBWE_SET(1) |
++		GPTU_CLC_EDIS_SET(0) |
++		GPTU_CLC_SPEN_SET(0) |
++		GPTU_CLC_DISR_SET(0);
++}
++
++static inline void lq_disable_gptu(void)
++{
++	struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++	ltq_w32(0x00, LQ_GPTU_IRNEN);
++	ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++	/*  Set divider as 0, enable write protection for SPEN, disable module. */
++	*LQ_GPTU_CLC =
++		GPTU_CLC_SMC_SET(0x00) |
++		GPTU_CLC_RMC_SET(0x00) |
++		GPTU_CLC_FSOE_SET(0) |
++		GPTU_CLC_SBWE_SET(0) |
++		GPTU_CLC_EDIS_SET(0) |
++		GPTU_CLC_SPEN_SET(0) |
++		GPTU_CLC_DISR_SET(1);
++
++	clk_enable(clk);
++}
++
++int lq_request_timer(unsigned int timer, unsigned int flag,
++	unsigned long value, unsigned long arg1, unsigned long arg2)
++{
++	int ret = 0;
++	unsigned int con_reg, irnen_reg;
++	int n, X;
++
++	if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
++		timer, flag, value);
++
++	if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
++		value &= 0xFFFF;
++	else
++		timer &= ~0x01;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	/*
++	 *  Allocate timer.
++	 */
++	if (timer < FIRST_TIMER) {
++		unsigned int mask;
++		unsigned int shift;
++		/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
++		unsigned int offset = TIMER2A;
++
++		/*
++		 *  Pick up a free timer.
++		 */
++		if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++			mask = 1 << offset;
++			shift = 1;
++		} else {
++			mask = 3 << offset;
++			shift = 2;
++		}
++		for (timer = offset;
++		     timer < offset + timer_dev.number_of_timers;
++		     timer += shift, mask <<= shift)
++			if (!(timer_dev.occupation & mask)) {
++				timer_dev.occupation |= mask;
++				break;
++			}
++		if (timer >= offset + timer_dev.number_of_timers) {
++			printk("failed![%d]\n", __LINE__);
++			mutex_unlock(&timer_dev.gptu_mutex);
++			return -EINVAL;
++		} else
++			ret = timer;
++	} else {
++		register unsigned int mask;
++
++		/*
++		 *  Check if the requested timer is free.
++		 */
++		mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++		if ((timer_dev.occupation & mask)) {
++			printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
++				__LINE__, mask, timer_dev.occupation);
++			mutex_unlock(&timer_dev.gptu_mutex);
++			return -EBUSY;
++		} else {
++			timer_dev.occupation |= mask;
++			ret = 0;
++		}
++	}
++
++	/*
++	 *  Prepare control register value.
++	 */
++	switch (TIMER_FLAG_MASK_EDGE(flag)) {
++	default:
++	case TIMER_FLAG_NONE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x00);
++		break;
++	case TIMER_FLAG_RISE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x01);
++		break;
++	case TIMER_FLAG_FALL_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x02);
++		break;
++	case TIMER_FLAG_ANY_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x03);
++		break;
++	}
++	if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
++		con_reg |=
++			TIMER_FLAG_MASK_SRC(flag) ==
++			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
++			GPTU_CON_SRC_EXT_SET(0);
++	else
++		con_reg |=
++			TIMER_FLAG_MASK_SRC(flag) ==
++			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
++			GPTU_CON_SRC_EG_SET(0);
++	con_reg |=
++		TIMER_FLAG_MASK_SYNC(flag) ==
++		TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
++		GPTU_CON_SYNC_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_INVERT(flag) ==
++		TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_SIZE(flag) ==
++		TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
++		GPTU_CON_EXT_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_STOP(flag) ==
++		TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++	con_reg |=
++		TIMER_FLAG_MASK_TYPE(flag) ==
++		TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
++		GPTU_CON_CNT_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_DIR(flag) ==
++		TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++	/*
++	 *  Fill up running data.
++	 */
++	timer_dev.timer[timer - FIRST_TIMER].flag = flag;
++	timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
++	timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
++
++	/*
++	 *  Enable GPTU module.
++	 */
++	if (!timer_dev.f_gptu_on) {
++		lq_enable_gptu();
++		timer_dev.f_gptu_on = 1;
++	}
++
++	/*
++	 *  Enable IRQ.
++	 */
++	if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
++		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
++			timer_dev.timer[timer - FIRST_TIMER].arg1 =
++				(unsigned long) find_task_by_vpid((int) arg1);
++
++		irnen_reg = 1 << (timer - FIRST_TIMER);
++
++		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
++		    || (TIMER_FLAG_MASK_HANDLE(flag) ==
++			TIMER_FLAG_CALLBACK_IN_IRQ
++			&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {
++			enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++			timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
++		}
++	} else
++		irnen_reg = 0;
++
++	/*
++	 *  Write config register, reload value and enable interrupt.
++	 */
++	n = timer >> 1;
++	X = timer & 0x01;
++	*LQ_GPTU_CON(n, X) = con_reg;
++	*LQ_GPTU_RELOAD(n, X) = value;
++	/* printk("reload value = %d\n", (u32)value); */
++	*LQ_GPTU_IRNEN |= irnen_reg;
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++	printk("successful!\n");
++	return ret;
++}
++EXPORT_SYMBOL(lq_request_timer);
++
++int lq_free_timer(unsigned int timer)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	if (GPTU_CON_EN(n, X))
++		*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++	*LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
++	*LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
++
++	if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
++		disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++		timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
++	}
++
++	timer_dev.occupation &= ~mask;
++	if (!timer_dev.occupation && timer_dev.f_gptu_on) {
++		lq_disable_gptu();
++		timer_dev.f_gptu_on = 0;
++	}
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_free_timer);
++
++int lq_start_timer(unsigned int timer, int is_resume)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) ==
++	TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
++
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_start_timer);
++
++int lq_stop_timer(unsigned int timer)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER
++	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_stop_timer);
++
++int lq_reset_counter_flags(u32 timer, u32 flags)
++{
++	unsigned int oflag;
++	unsigned int mask, con_reg;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	switch (TIMER_FLAG_MASK_EDGE(flags)) {
++	default:
++	case TIMER_FLAG_NONE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x00);
++		break;
++	case TIMER_FLAG_RISE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x01);
++		break;
++	case TIMER_FLAG_FALL_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x02);
++		break;
++	case TIMER_FLAG_ANY_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x03);
++		break;
++	}
++	if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
++		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
++	else
++		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
++	con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
++	con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++	con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
++	con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++	con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
++	con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++	timer_dev.timer[timer - FIRST_TIMER].flag = flags;
++	if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
++		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_CON(n, X) = con_reg;
++	smp_wmb();
++	mutex_unlock(&timer_dev.gptu_mutex);
++	return 0;
++}
++EXPORT_SYMBOL(lq_reset_counter_flags);
++
++int lq_get_count_value(unsigned int timer, unsigned long *value)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER
++	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*value = *LQ_GPTU_COUNT(n, X);
++
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_get_count_value);
++
++u32 lq_cal_divider(unsigned long freq)
++{
++	u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
++	u32 clock_divider = 1;
++	module_freq = fpi * 1000;
++	do_div(module_freq, clock_divider * freq);
++	return module_freq;
++}
++EXPORT_SYMBOL(lq_cal_divider);
++
++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
++	int is_ext_src, unsigned int handle_flag, unsigned long arg1,
++	unsigned long arg2)
++{
++	unsigned long divider;
++	unsigned int flag;
++
++	divider = lq_cal_divider(freq);
++	if (divider == 0)
++		return -EINVAL;
++	flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
++		| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
++		| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
++		| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
++		| TIMER_FLAG_MASK_HANDLE(handle_flag);
++
++	printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
++		timer, freq, divider);
++	return lq_request_timer(timer, flag, divider, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_timer);
++
++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
++	unsigned long arg1, unsigned long arg2)
++{
++	printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
++	return lq_request_timer(timer, flag, reload, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_counter);
++
++static long gptu_ioctl(struct file *file, unsigned int cmd,
++	unsigned long arg)
++{
++	int ret;
++	struct gptu_ioctl_param param;
++
++	if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param)))
++		return -EFAULT;
++	if (copy_from_user(&param, (void __user *)arg, sizeof(param)))
++		return -EFAULT;
++
++	if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
++	       || GPTU_SET_COUNTER) && param.timer < 2)
++	     || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
++	    && !access_ok((void __user *)arg,
++			   sizeof(struct gptu_ioctl_param)))
++		return -EFAULT;
++
++	switch (cmd) {
++	case GPTU_REQUEST_TIMER:
++		ret = lq_request_timer(param.timer, param.flag, param.value,
++				     (unsigned long) param.pid,
++				     (unsigned long) param.sig);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	case GPTU_FREE_TIMER:
++		ret = lq_free_timer(param.timer);
++		break;
++	case GPTU_START_TIMER:
++		ret = lq_start_timer(param.timer, param.flag);
++		break;
++	case GPTU_STOP_TIMER:
++		ret = lq_stop_timer(param.timer);
++		break;
++	case GPTU_GET_COUNT_VALUE:
++		ret = lq_get_count_value(param.timer, &param.value);
++		if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)->
++		    value, &param.value,sizeof(param.value)))
++			ret = -EFAULT;
++		break;
++	case GPTU_CALCULATE_DIVIDER:
++		param.value = lq_cal_divider(param.value);
++		if (param.value == 0)
++			ret = -EINVAL;
++		else if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++				      value, &param.value,
++				      sizeof(param.value)))
++			ret = -EFAULT;
++		else
++			ret = 0;
++		break;
++	case GPTU_SET_TIMER:
++		ret = lq_set_timer(param.timer, param.value,
++				 TIMER_FLAG_MASK_STOP(param.flag) !=
++				 TIMER_FLAG_ONCE ? 1 : 0,
++				 TIMER_FLAG_MASK_SRC(param.flag) ==
++				 TIMER_FLAG_EXT_SRC ? 1 : 0,
++				 TIMER_FLAG_MASK_HANDLE(param.flag) ==
++				 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
++				 TIMER_FLAG_NO_HANDLE,
++				 (unsigned long) param.pid,
++				 (unsigned long) param.sig);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	case GPTU_SET_COUNTER:
++		lq_set_counter(param.timer, param.flag, param.value, 0, 0);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	default:
++		ret = -ENOTTY;
++	}
++
++	return ret;
++}
++
++static int gptu_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int gptu_release(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int gptu_probe(struct platform_device *pdev)
++{
++	int ret;
++	int i;
++
++	ltq_w32(0, LQ_GPTU_IRNEN);
++	ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++	memset(&timer_dev, 0, sizeof(timer_dev));
++	mutex_init(&timer_dev.gptu_mutex);
++
++	lq_enable_gptu();
++	timer_dev.number_of_timers = GPTU_ID_CFG * 2;
++	lq_disable_gptu();
++	if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
++		timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
++	printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
++
++	ret = misc_register(&gptu_miscdev);
++	if (ret) {
++		printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
++		return ret;
++	} else {
++		printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
++	}
++
++	for (i = 0; i < timer_dev.number_of_timers; i++) {
++		int irq = platform_get_irq(pdev, i);
++		if (irq < 0) {
++			printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++			misc_deregister(&gptu_miscdev);
++			return irq;
++		}
++
++		ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
++		if (ret) {
++			printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++			misc_deregister(&gptu_miscdev);
++			return ret;
++		} else {
++			timer_dev.timer[i].irq = irq;
++			disable_irq(timer_dev.timer[i].irq);
++			printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
++		}
++	}
++
++	return 0;
++}
++
++static const struct of_device_id gptu_match[] = {
++	{ .compatible = "lantiq,gptu-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gptu_match);
++
++static struct platform_driver gptu_driver = {
++	.probe = gptu_probe,
++	.driver = {
++		.name = "gptu-xway",
++		.owner = THIS_MODULE,
++		.of_match_table = gptu_match,
++	},
++};
++
++int __init lq_gptu_init(void)
++{
++	int ret = platform_driver_register(&gptu_driver);
++
++	if (ret)
++		pr_info("gptu: Error registering platform driver\n");
++	return ret;
++}
++
++void __exit lq_gptu_exit(void)
++{
++	unsigned int i;
++
++	for (i = 0; i < timer_dev.number_of_timers; i++) {
++		if (timer_dev.timer[i].f_irq_on)
++			disable_irq(timer_dev.timer[i].irq);
++		free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++	}
++	lq_disable_gptu();
++	misc_deregister(&gptu_miscdev);
++}
++
++module_init(lq_gptu_init);
++module_exit(lq_gptu_exit);
++
++#endif
diff --git a/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch
new file mode 100644
index 0000000000..f420d8cde5
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0018-MTD-nand-lots-of-xrx200-fixes.patch
@@ -0,0 +1,121 @@
+From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 23:12:15 +0200
+Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/raw/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -61,6 +61,24 @@
+ #define NAND_CON_CSMUX		(1 << 1)
+ #define NAND_CON_NANDM		1
+ 
++#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
++#define PCI_CR_PR_OFFSET	    (KSEG1+0x1E105400)
++#define PCI_CR_PC_ARB		    (PCI_CR_PR_OFFSET + 0x0080)
++
++/*
++ * req_mask provides a mechanism to prevent interference between
++ * nand and pci (probably only relevant for the BT Home Hub 2B).
++ * Setting it causes the corresponding pci req pins to be masked
++ * during nand access, and also moves ebu locking from the read/write
++ * functions to the chip select function to ensure that the whole
++ * operation runs with interrupts disabled.
++ * In addition it switches on some extra waiting in xway_cmd_ctrl().
++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
++ * which in turn seems to be necessary for the nor chip to be recognised
++ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
++ */
++static __be32 req_mask = 0;
++
+ struct xway_nand_data {
+ 	struct nand_controller	controller;
+ 	struct nand_chip	chip;
+@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand
+ 	case -1:
+ 		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
++
++		if (req_mask) {
++			/* Unmask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
++		}
++
+ 		spin_unlock_irqrestore(&ebu_lock, data->csflags);
+ 		break;
+ 	case 0:
+ 		spin_lock_irqsave(&ebu_lock, data->csflags);
++
++		if (req_mask) {
++			/* Mask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
++		}
++
+ 		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
+ 		break;
+@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch
+ {
+ 	struct mtd_info *mtd = nand_to_mtd(chip);
+ 
++	if (req_mask) {
++		if (cmd != NAND_CMD_STATUS)
++			ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
++	}
++
+ 	if (cmd == NAND_CMD_NONE)
+ 		return;
+ 
+@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ 	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ 		;
++
++	if (req_mask) {
++	       /*
++		* program and erase have their own busy handlers
++		* status and sequential in needs no delay
++		*/
++		switch (cmd) {
++			case NAND_CMD_ERASE1:
++			case NAND_CMD_SEQIN:
++			case NAND_CMD_STATUS:
++			case NAND_CMD_READID:
++			return;
++		}
++
++		/* wait until command is processed */
++		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++			;
++	}
+ }
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+@@ -169,6 +222,7 @@ static int xway_nand_probe(struct platfo
+ 	int err;
+ 	u32 cs;
+ 	u32 cs_flag = 0;
++	const __be32 *req_mask_ptr;
+ 
+ 	/* Allocate memory for the device structure (and zero it) */
+ 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
+@@ -204,6 +258,15 @@ static int xway_nand_probe(struct platfo
+ 	if (!err && cs == 1)
+ 		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
+ 
++	req_mask_ptr = of_get_property(pdev->dev.of_node,
++					"req-mask", NULL);
++
++	/*
++	 * Load the PCI req lines to mask from the device tree. If the
++	 * property is not present, setting req_mask to 0 disables masking.
++	 */
++	req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
++
+ 	/* setup the EBU to run in NAND mode on our base addr */
+ 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)
+ 		    | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
diff --git a/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
new file mode 100644
index 0000000000..c1fc59487a
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
@@ -0,0 +1,25 @@
+From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:18:00 +0200
+Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/maps/lantiq-flash.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd
+ 	if (!ltq_mtd->map)
+ 		return -ENOMEM;
+ 
+-	ltq_mtd->map->phys = ltq_mtd->res->start;
++	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++		ltq_mtd->map->phys = NO_XIP;
++	else
++		ltq_mtd->map->phys = ltq_mtd->res->start;
++	ltq_mtd->res->start;
+ 	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+ 	ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
+ 	if (IS_ERR(ltq_mtd->map->virt))
diff --git a/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch
new file mode 100644
index 0000000000..fcc760b911
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0023-NET-PHY-add-led-support-for-intel-xway.patch
@@ -0,0 +1,294 @@
+From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:15:36 +0200
+Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/Kconfig  |    5 +
+ drivers/net/phy/Makefile |    1 +
+ drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 237 insertions(+)
+ create mode 100644 drivers/net/phy/lantiq.c
+
+--- a/drivers/net/phy/intel-xway.c
++++ b/drivers/net/phy/intel-xway.c
+@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p
+ 			  XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
+ }
+ 
++#if IS_ENABLED(CONFIG_OF_MDIO)
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++	u32 tmp;
++
++	/* store the led values if one was passed by the devicetree */
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H,  tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
++
++	return 0;
++}
++#else
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++	return 0;
++}
++#endif /* CONFIG_OF_MDIO */
++
+ static int xway_gphy_config_init(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct
+ 	if (err)
+ 		return err;
+ 
++	vr9_gphy_of_reg_init(phydev);
+ 	return 0;
+ }
+ 
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
+@@ -0,0 +1,216 @@
++Lanitq PHY binding
++============================================
++
++This devicetree binding controls the lantiq ethernet phys led functionality.
++
++Example:
++	mdio@0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "lantiq,xrx200-mdio";
++			phy5: ethernet-phy@5 {
++			reg = <0x1>;
++			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
++		};
++		phy11: ethernet-phy@11 {
++			reg = <0x11>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led2h = <0x00>;
++			lantiq,led2l = <0x03>;
++		};
++		phy12: ethernet-phy@12 {
++			reg = <0x12>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led1h = <0x00>;
++			lantiq,led1l = <0x03>;
++		};
++		phy13: ethernet-phy@13 {
++			reg = <0x13>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led2h = <0x00>;
++			lantiq,led2l = <0x03>;
++		};
++		phy14: ethernet-phy@14 {
++			reg = <0x14>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led1h = <0x00>;
++			lantiq,led1l = <0x03>;
++		};
++	};
++
++Register Description
++============================================
++
++LEDCH:
++
++Name	Hardware Reset Value
++LEDCH	0x00C5
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|   FBF   |   SBF   |RES |     NACS     |
++=========================================
++
++Field	Bits	Type	Description
++FBF	7:6	RW	Fast Blink Frequency
++			---
++			0x0 (00b) F02HZ 2 Hz blinking frequency
++			0x1 (01b) F04HZ 4 Hz blinking frequency
++			0x2 (10b) F08HZ 8 Hz blinking frequency
++			0x3 (11b) F16HZ 16 Hz blinking frequency
++
++SBF	5:4	RW	Slow Blink Frequency
++			---
++			0x0 (00b) F02HZ 2 Hz blinking frequency
++			0x1 (01b) F04HZ 4 Hz blinking frequency
++			0x2 (10b) F08HZ 8 Hz blinking frequency
++			0x3 (11b) F16HZ 16 Hz blinking frequency
++
++NACS	2:0	RW	Inverse of Scan Function
++			---
++			0x0 (000b) NONE No Function
++			0x1 (001b) LINK Complex function enabled when link is up
++			0x2 (010b) PDOWN Complex function enabled when device is powered-down
++			0x3 (011b) EEE Complex function enabled when device is in EEE mode
++			0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
++			0x5 (101b) ABIST Complex function enabled when analog self-test is running
++			0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
++			0x7 (111b) TEST Complex function enabled when test mode is running
++
++LEDCL:
++
++Name	Hardware Reset Value
++LEDCL	0x0067
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|RES |     SCAN     |RES |    CBLINK    |
++=========================================
++
++Field	Bits	Type	Description
++SCAN	6:4	RW	Complex Scan Configuration
++			---
++			000 B NONE No Function
++			001 B LINK Complex function enabled when link is up
++			010 B PDOWN Complex function enabled when device is powered-down
++			011 B EEE Complex function enabled when device is in EEE mode
++			100 B ANEG Complex function enabled when auto-negotiation is running
++			101 B ABIST Complex function enabled when analog self-test is running
++			110 B CDIAG Complex function enabled when cable diagnostics are running
++			111 B TEST Complex function enabled when test mode is running
++
++CBLINK	2:0	RW	Complex Blinking Configuration
++			---
++			000 B NONE No Function
++			001 B LINK Complex function enabled when link is up
++			010 B PDOWN Complex function enabled when device is powered-down
++			011 B EEE Complex function enabled when device is in EEE mode
++			100 B ANEG Complex function enabled when auto-negotiation is running
++			101 B ABIST Complex function enabled when analog self-test is running
++			110 B CDIAG Complex function enabled when cable diagnostics are running
++			111 B TEST Complex function enabled when test mode is running
++
++LEDxH:
++
++Name	Hardware Reset Value
++LED0H	0x0070
++LED1H	0x0020
++LED2H	0x0040
++LED3H	0x0040
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|        CON        |       BLINKF      |
++=========================================
++
++Field	Bits	Type	Description
++CON	7:4	RW	Constant On Configuration
++			---
++			0x0 (0000b) NONE LED does not light up constantly
++			0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
++			0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
++			0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN LED is on when device is powered-down
++			0x9 (1001b) EEE LED is on when device is in EEE mode
++			0xA (1010b) ANEG LED is on when auto-negotiation is running
++			0xB (1011b) ABIST LED is on when analog self-test is running
++			0xC (1100b) CDIAG LED is on when cable diagnostics are running
++
++BLINKF	3:0	RW	Fast Blinking Configuration
++			---
++			0x0 (0000b) NONE No Blinking
++			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN Blink when device is powered-down
++			0x9 (1001b) EEE Blink when device is in EEE mode
++			0xA (1010b) ANEG Blink when auto-negotiation is running
++			0xB (1011b) ABIST Blink when analog self-test is running
++			0xC (1100b) CDIAG Blink when cable diagnostics are running
++
++LEDxL:
++
++Name	Hardware Reset Value
++LED0L	0x0003
++LED1L	0x0000
++LED2L	0x0000
++LED3L	0x0020
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|      BLINKS       |       PULSE       |
++=========================================
++
++Field	Bits	Type	Description
++BLINKS	7:4	RW	Slow Blinkin Configuration
++			---
++			0x0 (0000b) NONE No Blinking
++			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN Blink when device is powered-down
++			0x9 (1001b) EEE Blink when device is in EEE mode
++			0xA (1010b) ANEG Blink when auto-negotiation is running
++			0xB (1011b) ABIST Blink when analog self-test is running
++			0xC (1100b) CDIAG Blink when cable diagnostics are runningning
++
++PULSE	3:0	RW	Pulsing Configuration
++			The pulse field is a mask field by which certain events can be combined
++			---
++			0x0 (0000b) NONE No pulsing
++			0x1 (0001b) TXACT Transmit activity
++			0x2 (0010b) RXACT Receive activity
++			0x4 (0100b) COL Collision
++			0x8 (1000b) RES Reserved
diff --git a/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch
new file mode 100644
index 0000000000..8ac1097267
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0028-NET-lantiq-various-etop-fixes.patch
@@ -0,0 +1,886 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 22:45:34 +0200
+Subject: [PATCH 28/36] NET: lantiq: various etop fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+  *
+- *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
+  */
+ 
+ #include <linux/kernel.h>
+@@ -20,12 +20,17 @@
+ #include <linux/mm.h>
+ #include <linux/platform_device.h>
+ #include <linux/ethtool.h>
++#include <linux/if_vlan.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -33,7 +38,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+ 
+-#define LTQ_ETOP_MDIO		0x11804
++#define LTQ_ETOP_MDIO_ACC	0x11804
+ #define MDIO_REQUEST		0x80000000
+ #define MDIO_READ		0x40000000
+ #define MDIO_ADDR_MASK		0x1f
+@@ -42,44 +47,91 @@
+ #define MDIO_REG_OFFSET		0x10
+ #define MDIO_VAL_MASK		0xffff
+ 
+-#define PPE32_CGEN		0x800
+-#define LQ_PPE32_ENET_MAC_CFG	0x1840
++#define LTQ_ETOP_MDIO_CFG       0x11800
++#define MDIO_CFG_MASK           0x6
++
++#define LTQ_ETOP_CFG            0x11808
++#define LTQ_ETOP_IGPLEN         0x11820
++#define LTQ_ETOP_MAC_CFG	0x11840
+ 
+ #define LTQ_ETOP_ENETS0		0x11850
+ #define LTQ_ETOP_MAC_DA0	0x1186C
+ #define LTQ_ETOP_MAC_DA1	0x11870
+-#define LTQ_ETOP_CFG		0x16020
+-#define LTQ_ETOP_IGPLEN		0x16080
++
++#define MAC_CFG_MASK		0xfff
++#define MAC_CFG_CGEN		(1 << 11)
++#define MAC_CFG_DUPLEX		(1 << 2)
++#define MAC_CFG_SPEED		(1 << 1)
++#define MAC_CFG_LINK		(1 << 0)
+ 
+ #define MAX_DMA_CHAN		0x8
+ #define MAX_DMA_CRC_LEN		0x4
+ #define MAX_DMA_DATA_LEN	0x600
+ 
+ #define ETOP_FTCU		BIT(28)
+-#define ETOP_MII_MASK		0xf
+-#define ETOP_MII_NORMAL		0xd
+-#define ETOP_MII_REVERSE	0xe
+ #define ETOP_PLEN_UNDER		0x40
+-#define ETOP_CGEN		0x800
++#define ETOP_CFG_MII0		0x01
+ 
+-/* use 2 static channels for TX/RX */
+-#define LTQ_ETOP_TX_CHANNEL	1
+-#define LTQ_ETOP_RX_CHANNEL	6
+-#define IS_TX(x)		((x) == LTQ_ETOP_TX_CHANNEL)
+-#define IS_RX(x)		((x) == LTQ_ETOP_RX_CHANNEL)
++#define ETOP_CFG_MASK           0xfff
++#define ETOP_CFG_FEN0		(1 << 8)
++#define ETOP_CFG_SEN0		(1 << 6)
++#define ETOP_CFG_OFF1		(1 << 3)
++#define ETOP_CFG_REMII0		(1 << 1)
++#define ETOP_CFG_OFF0		(1 << 0)
++
++#define LTQ_GBIT_MDIO_CTL	0xCC
++#define LTQ_GBIT_MDIO_DATA	0xd0
++#define LTQ_GBIT_GCTL0		0x68
++#define LTQ_GBIT_PMAC_HD_CTL	0x8c
++#define LTQ_GBIT_P0_CTL		0x4
++#define LTQ_GBIT_PMAC_RX_IPG	0xa8
++#define LTQ_GBIT_RGMII_CTL	0x78
++
++#define PMAC_HD_CTL_AS		(1 << 19)
++#define PMAC_HD_CTL_RXSH	(1 << 22)
++
++/* Switch Enable (0=disable, 1=enable) */
++#define GCTL0_SE		0x80000000
++/* Disable MDIO auto polling (0=disable, 1=enable) */
++#define PX_CTL_DMDIO		0x00400000
++
++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
++#define MDC_CLOCK_MASK		0xff000000
++#define MDC_CLOCK_OFFSET	24
++
++/* register information for the gbit's MDIO bus */
++#define MDIO_XR9_REQUEST	0x00008000
++#define MDIO_XR9_READ		0x00000800
++#define MDIO_XR9_WRITE		0x00000400
++#define MDIO_XR9_REG_MASK	0x1f
++#define MDIO_XR9_ADDR_MASK	0x1f
++#define MDIO_XR9_RD_MASK	0xffff
++#define MDIO_XR9_REG_OFFSET	0
++#define MDIO_XR9_ADDR_OFFSET	5
++#define MDIO_XR9_WR_OFFSET	16
+ 
++#define LTQ_DMA_ETOP	((of_machine_is_compatible("lantiq,ase")) ? \
++			(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
++
++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+ #define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
+ #define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
+ #define ltq_etop_w32_mask(x, y, z)	\
+ 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
+ 
+-#define DRV_VERSION	"1.0"
++#define ltq_gbit_r32(x)		ltq_r32(ltq_gbit_membase + (x))
++#define ltq_gbit_w32(x, y)	ltq_w32(x, ltq_gbit_membase + (y))
++#define ltq_gbit_w32_mask(x, y, z)	\
++		ltq_w32_mask(x, y, ltq_gbit_membase + (z))
++
++#define DRV_VERSION	"1.2"
+ 
+ static void __iomem *ltq_etop_membase;
++static void __iomem *ltq_gbit_membase;
+ 
+ struct ltq_etop_chan {
+-	int idx;
+ 	int tx_free;
++	int irq;
+ 	struct net_device *netdev;
+ 	struct napi_struct napi;
+ 	struct ltq_dma_channel dma;
+@@ -89,26 +141,39 @@ struct ltq_etop_chan {
+ struct ltq_etop_priv {
+ 	struct net_device *netdev;
+ 	struct platform_device *pdev;
+-	struct ltq_eth_data *pldata;
+ 	struct resource *res;
+ 
+ 	struct mii_bus *mii_bus;
+ 
+-	struct ltq_etop_chan ch[MAX_DMA_CHAN];
+-	int tx_free[MAX_DMA_CHAN >> 1];
++	struct ltq_etop_chan txch;
++	struct ltq_etop_chan rxch;
+ 
+ 	int tx_burst_len;
+ 	int rx_burst_len;
+ 
+-	spinlock_t lock;
++	int tx_irq;
++	int rx_irq;
++
++	unsigned char mac[6];
++	phy_interface_t mii_mode;
++ 
++ 	spinlock_t lock;
++
++	struct clk *clk_ppe;
++	struct clk *clk_switch;
++	struct clk *clk_ephy;
++	struct clk *clk_ephycgu;
+ };
+ 
++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
++				int phy_reg, u16 phy_data);
++
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 
+-	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
++	ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
+ 	if (!ch->skb[ch->dma.desc])
+ 		return -ENOMEM;
+ 	ch->dma.desc_base[ch->dma.desc].addr =
+@@ -143,8 +208,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	skb_put(skb, len);
++	skb->dev = ch->netdev;
+ 	skb->protocol = eth_type_trans(skb, ch->netdev);
+ 	netif_receive_skb(skb);
++	ch->netdev->stats.rx_packets++;
++	ch->netdev->stats.rx_bytes += len;
+ }
+ 
+ static int
+@@ -152,7 +220,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ {
+ 	struct ltq_etop_chan *ch = container_of(napi,
+ 				struct ltq_etop_chan, napi);
++	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	int work_done = 0;
++	unsigned long flags;
+ 
+ 	while (work_done < budget) {
+ 		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+@@ -164,7 +234,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ 	}
+ 	if (work_done < budget) {
+ 		napi_complete_done(&ch->napi, work_done);
++		spin_lock_irqsave(&priv->lock, flags);
+ 		ltq_dma_ack_irq(&ch->dma);
++		spin_unlock_irqrestore(&priv->lock, flags);
+ 	}
+ 	return work_done;
+ }
+@@ -176,12 +248,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 		container_of(napi, struct ltq_etop_chan, napi);
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	struct netdev_queue *txq =
+-		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
++		netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&priv->lock, flags);
+ 	while ((ch->dma.desc_base[ch->tx_free].ctl &
+ 			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
++		ch->netdev->stats.tx_packets++;
++		ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
+ 		dev_kfree_skb_any(ch->skb[ch->tx_free]);
+ 		ch->skb[ch->tx_free] = NULL;
+ 		memset(&ch->dma.desc_base[ch->tx_free], 0,
+@@ -194,7 +268,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 	if (netif_tx_queue_stopped(txq))
+ 		netif_tx_start_queue(txq);
+ 	napi_complete(&ch->napi);
++	spin_lock_irqsave(&priv->lock, flags);
+ 	ltq_dma_ack_irq(&ch->dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
+ 	return 1;
+ }
+ 
+@@ -202,9 +278,10 @@ static irqreturn_t
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ 	struct ltq_etop_priv *priv = _priv;
+-	int ch = irq - LTQ_DMA_CH0_INT;
+-
+-	napi_schedule(&priv->ch[ch].napi);
++	if (irq == priv->txch.dma.irq)
++		napi_schedule(&priv->txch.napi);
++	else
++		napi_schedule(&priv->rxch.napi);
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -216,7 +293,7 @@ ltq_etop_free_channel(struct net_device
+ 	ltq_dma_free(&ch->dma);
+ 	if (ch->dma.irq)
+ 		free_irq(ch->dma.irq, priv);
+-	if (IS_RX(ch->idx)) {
++	if (ch == &priv->txch) {
+ 		int desc;
+ 
+ 		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
+@@ -228,80 +305,135 @@ static void
+ ltq_etop_hw_exit(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+ 
+-	ltq_pmu_disable(PMU_PPE);
+-	for (i = 0; i < MAX_DMA_CHAN; i++)
+-		if (IS_TX(i) || IS_RX(i))
+-			ltq_etop_free_channel(dev, &priv->ch[i]);
++	clk_disable(priv->clk_ppe);
++
++	if (of_machine_is_compatible("lantiq,ar9"))
++		clk_disable(priv->clk_switch);
++
++	if (of_machine_is_compatible("lantiq,ase")) {
++		clk_disable(priv->clk_ephy);
++		clk_disable(priv->clk_ephycgu);
++	}
++
++	ltq_etop_free_channel(dev, &priv->txch);
++	ltq_etop_free_channel(dev, &priv->rxch);
++}
++
++static void
++ltq_etop_gbit_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++
++	clk_enable(priv->clk_switch);
++
++	/* enable gbit port0 on the SoC */
++	ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
++
++	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
++	/* disable MDIO auto polling mode */
++	ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
++	/* set 1522 packet size */
++	ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
++	/* disable pmac & dmac headers */
++	ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
++		LTQ_GBIT_PMAC_HD_CTL);
++	/* Due to traffic halt when burst length 8,
++		replace default IPG value with 0x3B */
++	ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
++	/* set mdc clock to 2.5 MHz */
++	ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
++		LTQ_GBIT_RGMII_CTL);
+ }
+ 
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+-	int err;
++	phy_interface_t mii_mode = priv->mii_mode;
+ 
+-	ltq_pmu_enable(PMU_PPE);
++	clk_enable(priv->clk_ppe);
+ 
+-	switch (priv->pldata->mii_mode) {
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		ltq_etop_gbit_init(dev);
++		/* force the etops link to the gbit to MII */
++		mii_mode = PHY_INTERFACE_MODE_MII;
++	}
++	ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
++	ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
++			MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
++
++	switch (mii_mode) {
+ 	case PHY_INTERFACE_MODE_RMII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	case PHY_INTERFACE_MODE_MII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	default:
++		if (of_machine_is_compatible("lantiq,ase")) {
++			clk_enable(priv->clk_ephy);
++			/* disable external MII */
++			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
++			/* enable clock for internal PHY */
++			clk_enable(priv->clk_ephycgu);
++			/* we need to write this magic to the internal phy to
++			   make it work */
++			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
++			pr_info("Selected EPHY mode\n");
++			break;
++		}
+ 		netdev_err(dev, "unknown mii mode %d\n",
+-			   priv->pldata->mii_mode);
++			   mii_mode);
+ 		return -ENOTSUPP;
+ 	}
+ 
+-	/* enable crc generation */
+-	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
++	return 0;
++}
++
++static int
++ltq_etop_dma_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++	int tx = priv->tx_irq - LTQ_DMA_ETOP;
++	int rx = priv->rx_irq - LTQ_DMA_ETOP;
++	int err;
+ 
+ 	ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		int irq = LTQ_DMA_CH0_INT + i;
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		ch->dma.nr = i;
+-		ch->idx = ch->dma.nr;
+-		ch->dma.dev = &priv->pdev->dev;
+-
+-		if (IS_TX(i)) {
+-			ltq_dma_alloc_tx(&ch->dma);
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Tx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
+-		} else if (IS_RX(i)) {
+-			ltq_dma_alloc_rx(&ch->dma);
+-			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+-					ch->dma.desc++)
+-				if (ltq_etop_alloc_skb(ch))
+-					return -ENOMEM;
+-			ch->dma.desc = 0;
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Rx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
++	priv->txch.dma.nr = tx;
++	priv->txch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_tx(&priv->txch.dma);
++	err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
++	if (err) {
++		netdev_err(dev, "failed to allocate tx irq\n");
++		goto err_out;
++	}
++	priv->txch.dma.irq = priv->tx_irq;
++
++	priv->rxch.dma.nr = rx;
++	priv->rxch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_rx(&priv->rxch.dma);
++	for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
++			priv->rxch.dma.desc++) {
++		if (ltq_etop_alloc_skb(&priv->rxch)) {
++			netdev_err(dev, "failed to allocate skbs\n");
++			err = -ENOMEM;
++			goto err_out;
+ 		}
+-		ch->dma.irq = irq;
+ 	}
+-	return 0;
++	priv->rxch.dma.desc = 0;
++	err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
++	if (err)
++		netdev_err(dev, "failed to allocate rx irq\n");
++	else
++		priv->rxch.dma.irq = priv->rx_irq;
++err_out:
++	return err;
+ }
+ 
+ static void
+@@ -320,6 +452,39 @@ static const struct ethtool_ops ltq_etop
+ };
+ 
+ static int
++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
++		int phy_reg, u16 phy_data)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
++		(phy_data << MDIO_XR9_WR_OFFSET) |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	return 0;
++}
++
++static int
++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
++	return val;
++}
++
++static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ 	u32 val = MDIO_REQUEST |
+@@ -327,9 +492,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
+ 		phy_data;
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+ 	return 0;
+ }
+ 
+@@ -340,12 +505,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
+ 		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
++	val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
+ 	return val;
+ }
+ 
+@@ -361,7 +526,10 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct phy_device *phydev;
+ 
+-	phydev = phy_find_first(priv->mii_bus);
++	if (of_machine_is_compatible("lantiq,ase"))
++		phydev = mdiobus_get_phy(priv->mii_bus, 8);
++	else
++		phydev = mdiobus_get_phy(priv->mii_bus, 0);
+ 
+ 	if (!phydev) {
+ 		netdev_err(dev, "no PHY found\n");
+@@ -369,14 +537,17 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	}
+ 
+ 	phydev = phy_connect(dev, phydev_name(phydev),
+-			     &ltq_etop_mdio_link, priv->pldata->mii_mode);
++			     &ltq_etop_mdio_link, priv->mii_mode);
+ 
+ 	if (IS_ERR(phydev)) {
+ 		netdev_err(dev, "Could not attach to PHY\n");
+ 		return PTR_ERR(phydev);
+ 	}
+ 
+-	phy_set_max_speed(phydev, SPEED_100);
++	if (of_machine_is_compatible("lantiq,ar9"))
++		phy_set_max_speed(phydev, SPEED_1000);
++	else
++		phy_set_max_speed(phydev, SPEED_100);
+ 
+ 	phy_attached_info(phydev);
+ 
+@@ -397,8 +568,13 @@ ltq_etop_mdio_init(struct net_device *de
+ 	}
+ 
+ 	priv->mii_bus->priv = dev;
+-	priv->mii_bus->read = ltq_etop_mdio_rd;
+-	priv->mii_bus->write = ltq_etop_mdio_wr;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
++		priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
++	} else {
++		priv->mii_bus->read = ltq_etop_mdio_rd;
++		priv->mii_bus->write = ltq_etop_mdio_wr;
++	}
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+@@ -435,18 +611,21 @@ static int
+ ltq_etop_open(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
++	napi_enable(&priv->txch.napi);
++	napi_enable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_open(&priv->txch.dma);
++	ltq_dma_enable_irq(&priv->txch.dma);
++	ltq_dma_open(&priv->rxch.dma);
++	ltq_dma_enable_irq(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	if (dev->phydev)
++		phy_start(dev->phydev);
+ 
+-		if (!IS_TX(i) && (!IS_RX(i)))
+-			continue;
+-		ltq_dma_open(&ch->dma);
+-		ltq_dma_enable_irq(&ch->dma);
+-		napi_enable(&ch->napi);
+-	}
+-	phy_start(dev->phydev);
+ 	netif_tx_start_all_queues(dev);
+ 	return 0;
+ }
+@@ -455,18 +634,19 @@ static int
+ ltq_etop_stop(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+ 	netif_tx_stop_all_queues(dev);
+-	phy_stop(dev->phydev);
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		if (!IS_RX(i) && !IS_TX(i))
+-			continue;
+-		napi_disable(&ch->napi);
+-		ltq_dma_close(&ch->dma);
+-	}
++	if (dev->phydev)
++		phy_stop(dev->phydev);
++	napi_disable(&priv->txch.napi);
++	napi_disable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_close(&priv->txch.dma);
++	ltq_dma_close(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
+ 	return 0;
+ }
+ 
+@@ -476,15 +656,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	int queue = skb_get_queue_mapping(skb);
+ 	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+-	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+-	int len;
++	struct ltq_dma_desc *desc =
++		&priv->txch.dma.desc_base[priv->txch.dma.desc];
+ 	unsigned long flags;
+ 	u32 byte_offset;
++	int len;
+ 
+ 	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+ 
+-	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
++	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
++			priv->txch.skb[priv->txch.dma.desc]) {
+ 		netdev_err(dev, "tx ring full\n");
+ 		netif_tx_stop_queue(txq);
+ 		return NETDEV_TX_BUSY;
+@@ -492,7 +673,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 
+ 	/* dma needs to start on a burst length value aligned address */
+ 	byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
+-	ch->skb[ch->dma.desc] = skb;
++	priv->txch.skb[priv->txch.dma.desc] = skb;
+ 
+ 	netif_trans_update(dev);
+ 
+@@ -503,11 +684,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	wmb();
+ 	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
+ 		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
+-	ch->dma.desc++;
+-	ch->dma.desc %= LTQ_DESC_NUM;
++	priv->txch.dma.desc++;
++	priv->txch.dma.desc %= LTQ_DESC_NUM;
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+-	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
++	if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
+ 		netif_tx_stop_queue(txq);
+ 
+ 	return NETDEV_TX_OK;
+@@ -518,11 +699,14 @@ ltq_etop_change_mtu(struct net_device *d
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	unsigned long flags;
++	int max;
+ 
+ 	dev->mtu = new_mtu;
+ 
++	max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
++
+ 	spin_lock_irqsave(&priv->lock, flags);
+-	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
++	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	return 0;
+@@ -575,6 +759,9 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 	ltq_etop_change_mtu(dev, 1500);
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 
+ 	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+@@ -592,9 +779,10 @@ ltq_etop_init(struct net_device *dev)
+ 		dev->addr_assign_type = NET_ADDR_RANDOM;
+ 
+ 	ltq_etop_set_multicast_list(dev);
+-	err = ltq_etop_mdio_init(dev);
+-	if (err)
+-		goto err_netdev;
++	if (!ltq_etop_mdio_init(dev))
++		dev->ethtool_ops = &ltq_etop_ethtool_ops;
++	else
++		pr_warn("etop: mdio probe failed\n");;
+ 	return 0;
+ 
+ err_netdev:
+@@ -614,6 +802,9 @@ ltq_etop_tx_timeout(struct net_device *d
+ 	err = ltq_etop_hw_init(dev);
+ 	if (err)
+ 		goto err_hw;
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 	netif_trans_update(dev);
+ 	netif_wake_queue(dev);
+ 	return;
+@@ -637,14 +828,18 @@ static const struct net_device_ops ltq_e
+ 	.ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+ 
+-static int __init
+-ltq_etop_probe(struct platform_device *pdev)
++static int ltq_etop_probe(struct platform_device *pdev)
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+-	struct resource *res;
++	struct resource *res, *gbit_res, irqres[2];
+ 	int err;
+-	int i;
++
++	err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
++	if (err != 2) {
++		dev_err(&pdev->dev, "failed to get etop irqs\n");
++		return -EINVAL;
++	}
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (!res) {
+@@ -670,19 +865,55 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_out;
+ 	}
+ 
+-	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+-	if (!dev) {
+-		err = -ENOMEM;
+-		goto err_out;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++		if (!gbit_res) {
++			dev_err(&pdev->dev, "failed to get gbit resource\n");
++			err = -ENOENT;
++			goto err_out;
++		}
++		ltq_gbit_membase = devm_ioremap(&pdev->dev,
++			gbit_res->start, resource_size(gbit_res));
++		if (!ltq_gbit_membase) {
++			dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
++				pdev->id);
++			err = -ENOMEM;
++			goto err_out;
++		}
+ 	}
++
++	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ 	strcpy(dev->name, "eth%d");
+ 	dev->netdev_ops = &ltq_eth_netdev_ops;
+-	dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ 	priv = netdev_priv(dev);
+ 	priv->res = res;
+ 	priv->pdev = pdev;
+-	priv->pldata = dev_get_platdata(&pdev->dev);
+ 	priv->netdev = dev;
++	priv->tx_irq = irqres[0].start;
++	priv->rx_irq = irqres[1].start;
++	err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode);
++	if (err)
++		pr_err("Can't find phy-mode for port\n");
++
++	of_get_mac_address(pdev->dev.of_node, priv->mac);
++
++	priv->clk_ppe = clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->clk_ppe))
++		return PTR_ERR(priv->clk_ppe);
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->clk_switch = clk_get(&pdev->dev, "switch");
++		if (IS_ERR(priv->clk_switch))
++			return PTR_ERR(priv->clk_switch);
++	}
++	if (of_machine_is_compatible("lantiq,ase")) {
++		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
++		if (IS_ERR(priv->clk_ephy))
++			return PTR_ERR(priv->clk_ephy);
++		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
++		if (IS_ERR(priv->clk_ephycgu))
++			return PTR_ERR(priv->clk_ephycgu);
++	}
++
+ 	spin_lock_init(&priv->lock);
+ 	SET_NETDEV_DEV(dev, &pdev->dev);
+ 
+@@ -698,15 +929,10 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_free;
+ 	}
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		if (IS_TX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_tx, 8);
+-		else if (IS_RX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_rx, 32);
+-		priv->ch[i].netdev = dev;
+-	}
++	netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
++	netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
++	priv->txch.netdev = dev;
++	priv->rxch.netdev = dev;
+ 
+ 	err = register_netdev(dev);
+ 	if (err)
+@@ -735,31 +961,22 @@ ltq_etop_remove(struct platform_device *
+ 	return 0;
+ }
+ 
++static const struct of_device_id ltq_etop_match[] = {
++	{ .compatible = "lantiq,etop-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ltq_etop_match);
++
+ static struct platform_driver ltq_mii_driver = {
++	.probe = ltq_etop_probe,
+ 	.remove = ltq_etop_remove,
+ 	.driver = {
+ 		.name = "ltq_etop",
++		.of_match_table = ltq_etop_match,
+ 	},
+ };
+ 
+-static int __init
+-init_ltq_etop(void)
+-{
+-	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
+-
+-	if (ret)
+-		pr_err("ltq_etop: Error registering platform driver!");
+-	return ret;
+-}
+-
+-static void __exit
+-exit_ltq_etop(void)
+-{
+-	platform_driver_unregister(&ltq_mii_driver);
+-}
+-
+-module_init(init_ltq_etop);
+-module_exit(exit_ltq_etop);
++module_platform_driver(ltq_mii_driver);
+ 
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+ MODULE_DESCRIPTION("Lantiq SoC ETOP");
diff --git a/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
new file mode 100644
index 0000000000..b5f79e95a8
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
@@ -0,0 +1,1034 @@
+From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:26:42 +0200
+Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master
+
+This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/i2c/busses/Kconfig      |   10 +
+ drivers/i2c/busses/Makefile     |    1 +
+ drivers/i2c/busses/i2c-lantiq.c |  747 +++++++++++++++++++++++++++++++++++++++
+ drivers/i2c/busses/i2c-lantiq.h |  234 ++++++++++++
+ 4 files changed, 992 insertions(+)
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.c
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.h
+
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -795,6 +795,16 @@ config I2C_MICROCHIP_CORE
+ 	  This driver can also be built as a module. If so, the module will be
+ 	  called i2c-microchip-core.
+ 
++config I2C_LANTIQ
++	tristate "Lantiq I2C interface"
++	depends on LANTIQ && SOC_FALCON
++	help
++	  If you say yes to this option, support will be included for the
++	  Lantiq I2C core.
++
++	  This driver can also be built as a module. If so, the module
++	  will be called i2c-lantiq.
++
+ config I2C_MPC
+ 	tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
+ 	depends on PPC
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C)	+= i2c-imx-l
+ obj-$(CONFIG_I2C_IOP3XX)	+= i2c-iop3xx.o
+ obj-$(CONFIG_I2C_JZ4780)	+= i2c-jz4780.o
+ obj-$(CONFIG_I2C_KEMPLD)	+= i2c-kempld.o
++obj-$(CONFIG_I2C_LANTIQ)	+= i2c-lantiq.o
+ obj-$(CONFIG_I2C_LPC2K)		+= i2c-lpc2k.o
+ obj-$(CONFIG_I2C_MESON)		+= i2c-meson.o
+ obj-$(CONFIG_I2C_MICROCHIP_CORE)	+= i2c-microchip-corei2c.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.c
+@@ -0,0 +1,747 @@
++
++/*
++ * Lantiq I2C bus adapter
++ *
++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/slab.h> /* for kzalloc, kfree */
++#include <linux/i2c.h>
++#include <linux/errno.h>
++#include <linux/completion.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/of_irq.h>
++
++#include <lantiq_soc.h>
++#include "i2c-lantiq.h"
++
++/*
++ * CURRENT ISSUES:
++ * - no high speed support
++ * - ten bit mode is not tested (no slave devices)
++ */
++
++/* access macros */
++#define i2c_r32(reg)	\
++	__raw_readl(&(priv->membase)->reg)
++#define i2c_w32(val, reg)	\
++	__raw_writel(val, &(priv->membase)->reg)
++#define i2c_w32_mask(clear, set, reg)	\
++	i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)
++
++#define DRV_NAME "i2c-lantiq"
++#define DRV_VERSION "1.00"
++
++#define LTQ_I2C_BUSY_TIMEOUT		20 /* ms */
++
++#ifdef DEBUG
++#define LTQ_I2C_XFER_TIMEOUT		(25*HZ)
++#else
++#define LTQ_I2C_XFER_TIMEOUT		HZ
++#endif
++
++#define LTQ_I2C_IMSC_DEFAULT_MASK	(I2C_IMSC_I2C_P_INT_EN | \
++					 I2C_IMSC_I2C_ERR_INT_EN)
++
++#define LTQ_I2C_ARB_LOST		(1 << 0)
++#define LTQ_I2C_NACK			(1 << 1)
++#define LTQ_I2C_RX_UFL			(1 << 2)
++#define LTQ_I2C_RX_OFL			(1 << 3)
++#define LTQ_I2C_TX_UFL			(1 << 4)
++#define LTQ_I2C_TX_OFL			(1 << 5)
++
++struct ltq_i2c {
++	struct mutex mutex;
++
++
++	/* active clock settings */
++	unsigned int input_clock;	/* clock input for i2c hardware block */
++	unsigned int i2c_clock;		/* approximated bus clock in kHz */
++
++	struct clk *clk_gate;
++	struct clk *clk_input;
++
++
++	/* resources (memory and interrupts) */
++	int irq_lb;				/* last burst irq */
++
++	struct lantiq_reg_i2c __iomem *membase;	/* base of mapped registers */
++
++	struct i2c_adapter adap;
++	struct device *dev;
++
++	struct completion cmd_complete;
++
++
++	/* message transfer data */
++	struct i2c_msg *current_msg;	/* current message */
++	int msgs_num;		/* number of messages to handle */
++	u8 *msg_buf;		/* current buffer */
++	u32 msg_buf_len;	/* remaining length of current buffer */
++	int msg_err;		/* error status of the current transfer */
++
++
++	/* master status codes */
++	enum {
++		STATUS_IDLE,
++		STATUS_ADDR,	/* address phase */
++		STATUS_WRITE,
++		STATUS_READ,
++		STATUS_READ_END,
++		STATUS_STOP
++	} status;
++};
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);
++
++static inline void enable_burst_irq(struct ltq_i2c *priv)
++{
++	i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
++}
++static inline void disable_burst_irq(struct ltq_i2c *priv)
++{
++	i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
++}
++
++static void prepare_msg_send_addr(struct ltq_i2c *priv)
++{
++	struct i2c_msg *msg = priv->current_msg;
++	int rd = !!(msg->flags & I2C_M_RD);	/* extends to 0 or 1 */
++	u16 addr = msg->addr;
++
++	/* new i2c_msg */
++	priv->msg_buf = msg->buf;
++	priv->msg_buf_len = msg->len;
++	if (rd)
++		priv->status = STATUS_READ;
++	else
++		priv->status = STATUS_WRITE;
++
++	/* send slave address */
++	if (msg->flags & I2C_M_TEN) {
++		i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
++		i2c_w32(addr & 0xff, txd);
++	} else {
++		i2c_w32((addr & 0x7f) << 1 | rd, txd);
++	}
++}
++
++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)
++{
++	struct i2c_msg *msg = priv->current_msg;
++	int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
++
++	pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T');
++
++	priv->status = STATUS_ADDR;
++
++	if (!(msg->flags & I2C_M_RD))
++		len += msg->len;
++	else
++		/* set maximum received packet size (before rx int!) */
++		i2c_w32(msg->len, mrps_ctrl);
++	i2c_w32(len, tps_ctrl);
++	enable_burst_irq(priv);
++}
++
++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)
++{
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++	unsigned int input_clock = clk_get_rate(priv->clk_input);
++	u32 dec, inc = 1;
++
++	/* clock changed? */
++	if (priv->input_clock == input_clock)
++		return 0;
++
++	/*
++	 * this formula is only an approximation, found by the recommended
++	 * values in the "I2C Architecture Specification 1.7.1"
++	 */
++	dec = input_clock / (priv->i2c_clock * 2);
++	if (dec <= 6)
++		return -ENXIO;
++
++	i2c_w32(0, fdiv_high_cfg);
++	i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |
++		(dec << I2C_FDIV_CFG_DEC_OFFSET),
++		fdiv_cfg);
++
++	dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n",
++		input_clock, priv->i2c_clock, dec);
++
++	priv->input_clock = input_clock;
++	return 0;
++}
++
++static int ltq_i2c_hw_init(struct i2c_adapter *adap)
++{
++	int ret = 0;
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++
++	/* disable bus */
++	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++#ifndef DEBUG
++	/* set normal operation clock divider */
++	i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
++#else
++	/* for debugging a higher divider value! */
++	i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
++#endif
++
++	/* setup clock */
++	ret = ltq_i2c_hw_set_clock(adap);
++	if (ret != 0) {
++		dev_warn(priv->dev, "invalid clock settings\n");
++		return ret;
++	}
++
++	/* configure fifo */
++	i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
++		I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
++		I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
++		I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
++		I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
++		I2C_FIFO_CFG_RXBS_RXBS0,  /* rx fifo burst size is 1 word */
++		fifo_cfg);
++
++	/* configure address */
++	i2c_w32(I2C_ADDR_CFG_SOPE_EN |	/* generate stop when no more data in
++					   the fifo */
++		I2C_ADDR_CFG_SONA_EN |	/* generate stop when NA received */
++		I2C_ADDR_CFG_MnS_EN |	/* we are master device */
++		0,			/* our slave address (not used!) */
++		addr_cfg);
++
++	/* enable bus */
++	i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
++
++	return 0;
++}
++
++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)
++{
++	unsigned long timeout;
++
++	timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);
++
++	do {
++		u32 stat = i2c_r32(bus_stat);
++
++		if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)
++			return 0;
++
++		cond_resched();
++	} while (!time_after_eq(jiffies, timeout));
++
++	dev_err(priv->dev, "timeout waiting for bus ready\n");
++	return -ETIMEDOUT;
++}
++
++static void ltq_i2c_tx(struct ltq_i2c *priv, int last)
++{
++	if (priv->msg_buf_len && priv->msg_buf) {
++		i2c_w32(*priv->msg_buf, txd);
++
++		if (--priv->msg_buf_len)
++			priv->msg_buf++;
++		else
++			priv->msg_buf = NULL;
++	} else {
++		last = 1;
++	}
++
++	if (last)
++		disable_burst_irq(priv);
++}
++
++static void ltq_i2c_rx(struct ltq_i2c *priv, int last)
++{
++	u32 fifo_stat, timeout;
++	if (priv->msg_buf_len && priv->msg_buf) {
++		timeout = 5000000;
++		do {
++			fifo_stat = i2c_r32(ffs_stat);
++		} while (!fifo_stat && --timeout);
++		if (!timeout) {
++			last = 1;
++			pr_debug("\nrx timeout\n");
++			goto err;
++		}
++		while (fifo_stat) {
++			*priv->msg_buf = i2c_r32(rxd);
++			if (--priv->msg_buf_len) {
++				priv->msg_buf++;
++			} else {
++				priv->msg_buf = NULL;
++				last = 1;
++				break;
++			}
++			/*
++			 * do not read more than burst size, otherwise no "last
++			 * burst" is generated and the transaction is blocked!
++			 */
++			fifo_stat = 0;
++		}
++	} else {
++		last = 1;
++	}
++err:
++	if (last) {
++		disable_burst_irq(priv);
++
++		if (priv->status == STATUS_READ_END) {
++			/* 
++			 * do the STATUS_STOP and complete() here, as sometimes
++			 * the tx_end is already seen before this is finished
++			 */
++			priv->status = STATUS_STOP;
++			complete(&priv->cmd_complete);
++		} else {
++			i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++			priv->status = STATUS_READ_END;
++		}
++	}
++}
++
++static void ltq_i2c_xfer_init(struct ltq_i2c *priv)
++{
++	/* enable interrupts */
++	i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);
++
++	/* trigger transfer of first msg */
++	ltq_i2c_set_tx_len(priv);
++}
++
++static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
++{
++#if defined(DEBUG)
++	int i, j;
++	pr_debug("Messages %d %s\n", num, rx ? "out" : "in");
++	for (i = 0; i < num; i++) {
++		pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i,
++			(msgs[i].flags & I2C_M_RD) ? 'R' : 'T',
++			msgs[i].len, msgs[i].addr);
++		if (!(msgs[i].flags & I2C_M_RD) || rx) {
++			for (j = 0; j < msgs[i].len; j++)
++				pr_debug("%02X ", msgs[i].buf[j]);
++		}
++		pr_debug("\n");
++	}
++#endif
++}
++
++static void ltq_i2c_release_bus(struct ltq_i2c *priv)
++{
++	if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
++		i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++}
++
++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
++			   int num)
++{
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++	int ret;
++
++	dev_dbg(priv->dev, "xfer %u messages\n", num);
++	dump_msgs(msgs, num, 0);
++
++	mutex_lock(&priv->mutex);
++
++	init_completion(&priv->cmd_complete);
++	priv->current_msg = msgs;
++	priv->msgs_num = num;
++	priv->msg_err = 0;
++	priv->status = STATUS_IDLE;
++
++	/* wait for the bus to become ready */
++	ret = ltq_i2c_wait_bus_not_busy(priv);
++	if (ret)
++		goto done;
++
++	while (priv->msgs_num) {
++		/* start the transfers */
++		ltq_i2c_xfer_init(priv);
++
++		/* wait for transfers to complete */
++		ret = wait_for_completion_interruptible_timeout(
++			&priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);
++		if (ret == 0) {
++			dev_err(priv->dev, "controller timed out\n");
++			ltq_i2c_hw_init(adap);
++			ret = -ETIMEDOUT;
++			goto done;
++		} else if (ret < 0)
++			goto done;
++
++		if (priv->msg_err) {
++			if (priv->msg_err & LTQ_I2C_NACK)
++				ret = -ENXIO;
++			else
++				ret = -EREMOTEIO;
++			goto done;
++		}
++		if (--priv->msgs_num)
++			priv->current_msg++;
++	}
++	/* no error? */
++	ret = num;
++
++done:
++	ltq_i2c_release_bus(priv);
++
++	mutex_unlock(&priv->mutex);
++
++	if (ret >= 0)
++		dump_msgs(msgs, num, 1);
++
++	pr_debug("XFER ret %d\n", ret);
++	return ret;
++}
++
++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)
++{
++	struct ltq_i2c *priv = dev_id;
++	struct i2c_msg *msg = priv->current_msg;
++	int last = (irq == priv->irq_lb);
++
++	if (last)
++		pr_debug("LB ");
++	else
++		pr_debug("B ");
++
++	if (msg->flags & I2C_M_RD) {
++		switch (priv->status) {
++		case STATUS_ADDR:
++			pr_debug("X");
++			prepare_msg_send_addr(priv);
++			disable_burst_irq(priv);
++			break;
++		case STATUS_READ:
++		case STATUS_READ_END:
++			pr_debug("R");
++			ltq_i2c_rx(priv, last);
++			break;
++		default:
++			disable_burst_irq(priv);
++			pr_warn("Status R %d\n", priv->status);
++			break;
++		}
++	} else {
++		switch (priv->status) {
++		case STATUS_ADDR:
++			pr_debug("x");
++			prepare_msg_send_addr(priv);
++			break;
++		case STATUS_WRITE:
++			pr_debug("w");
++			ltq_i2c_tx(priv, last);
++			break;
++		default:
++			disable_burst_irq(priv);
++			pr_warn("Status W %d\n", priv->status);
++			break;
++		}
++	}
++
++	i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
++	return IRQ_HANDLED;
++}
++
++static void ltq_i2c_isr_prot(struct ltq_i2c *priv)
++{
++	u32 i_pro = i2c_r32(p_irqss);
++
++	pr_debug("i2c-p");
++
++	/* not acknowledge */
++	if (i_pro & I2C_P_IRQSS_NACK) {
++		priv->msg_err |= LTQ_I2C_NACK;
++		pr_debug(" nack");
++	}
++
++	/* arbitration lost */
++	if (i_pro & I2C_P_IRQSS_AL) {
++		priv->msg_err |= LTQ_I2C_ARB_LOST;
++		pr_debug(" arb-lost");
++	}
++	/* tx -> rx switch */
++	if (i_pro & I2C_P_IRQSS_RX)
++		pr_debug(" rx");
++
++	/* tx end */
++	if (i_pro & I2C_P_IRQSS_TX_END)
++		pr_debug(" txend");
++	pr_debug("\n");
++
++	if (!priv->msg_err) {
++		/* tx -> rx switch */
++		if (i_pro & I2C_P_IRQSS_RX) {
++			priv->status = STATUS_READ;
++			enable_burst_irq(priv);
++		}
++		if (i_pro & I2C_P_IRQSS_TX_END) {
++			if (priv->status == STATUS_READ)
++				priv->status = STATUS_READ_END;
++			else {
++				disable_burst_irq(priv);
++				priv->status = STATUS_STOP;
++			}
++		}
++	}
++
++	i2c_w32(i_pro, p_irqsc);
++}
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)
++{
++	u32 i_raw, i_err = 0;
++	struct ltq_i2c *priv = dev_id;
++
++	i_raw = i2c_r32(mis);
++	pr_debug("i_raw 0x%08X\n", i_raw);
++
++	/* error interrupt */
++	if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
++		i_err = i2c_r32(err_irqss);
++		pr_debug("i_err 0x%08X bus_stat 0x%04X\n",
++			i_err, i2c_r32(bus_stat));
++
++		/* tx fifo overflow (8) */
++		if (i_err & I2C_ERR_IRQSS_TXF_OFL)
++			priv->msg_err |= LTQ_I2C_TX_OFL;
++
++		/* tx fifo underflow (4) */
++		if (i_err & I2C_ERR_IRQSS_TXF_UFL)
++			priv->msg_err |= LTQ_I2C_TX_UFL;
++
++		/* rx fifo overflow (2) */
++		if (i_err & I2C_ERR_IRQSS_RXF_OFL)
++			priv->msg_err |= LTQ_I2C_RX_OFL;
++
++		/* rx fifo underflow (1) */
++		if (i_err & I2C_ERR_IRQSS_RXF_UFL)
++			priv->msg_err |= LTQ_I2C_RX_UFL;
++
++		i2c_w32(i_err, err_irqsc);
++	}
++
++	/* protocol interrupt */
++	if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
++		ltq_i2c_isr_prot(priv);
++
++	if ((priv->msg_err) || (priv->status == STATUS_STOP))
++		complete(&priv->cmd_complete);
++
++	return IRQ_HANDLED;
++}
++
++static u32 ltq_i2c_functionality(struct i2c_adapter *adap)
++{
++	return	I2C_FUNC_I2C |
++		I2C_FUNC_10BIT_ADDR |
++		I2C_FUNC_SMBUS_EMUL;
++}
++
++static struct i2c_algorithm ltq_i2c_algorithm = {
++	.master_xfer	= ltq_i2c_xfer,
++	.functionality	= ltq_i2c_functionality,
++};
++
++static int ltq_i2c_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	struct ltq_i2c *priv;
++	struct i2c_adapter *adap;
++	struct resource *mmres, irqres[4];
++	int ret = 0;
++
++	dev_dbg(&pdev->dev, "probing\n");
++
++	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	ret = of_irq_to_resource_table(node, irqres, 4);
++	if (!mmres || (ret != 4)) {
++		dev_err(&pdev->dev, "no resources\n");
++		return -ENODEV;
++	}
++
++	/* allocate private data */
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&pdev->dev, "can't allocate private data\n");
++		return -ENOMEM;
++	}
++
++	adap = &priv->adap;
++	i2c_set_adapdata(adap, priv);
++	adap->owner = THIS_MODULE;
++	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++	strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
++	adap->algo = &ltq_i2c_algorithm;
++	adap->dev.parent = &pdev->dev;
++	adap->dev.of_node = pdev->dev.of_node;
++
++	if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) {
++		dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n");
++		priv->i2c_clock = 100000;
++	}
++
++	init_completion(&priv->cmd_complete);
++	mutex_init(&priv->mutex);
++
++	priv->membase = devm_ioremap_resource(&pdev->dev, mmres);
++	if (IS_ERR(priv->membase))
++		return PTR_ERR(priv->membase);
++
++	priv->dev = &pdev->dev;
++	priv->irq_lb = irqres[0].start;
++
++	ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,
++		0x0, "i2c lb", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
++			irqres[0].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,
++		0x0, "i2c b", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get burst IRQ %d\n",
++			irqres[1].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,
++		0x0, "i2c err", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get error IRQ %d\n",
++			irqres[2].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,
++		0x0, "i2c p", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
++			irqres[3].start);
++		return -ENODEV;
++	}
++
++	dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
++	dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start,
++		irqres[1].start, irqres[2].start, irqres[3].start);
++
++	priv->clk_gate = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->clk_gate)) {
++		dev_err(&pdev->dev, "failed to get i2c clk\n");
++		return -ENOENT;
++	}
++
++	/* this is a static clock, which has no refcounting */
++	priv->clk_input = clk_get_fpi();
++	if (IS_ERR(priv->clk_input)) {
++		dev_err(&pdev->dev, "failed to get fpi clk\n");
++		return -ENOENT;
++	}
++
++	clk_activate(priv->clk_gate);
++
++	/* add our adapter to the i2c stack */
++	ret = i2c_add_numbered_adapter(adap);
++	if (ret) {
++		dev_err(&pdev->dev, "can't register I2C adapter\n");
++		goto out;
++	}
++
++	platform_set_drvdata(pdev, priv);
++	i2c_set_adapdata(adap, priv);
++
++	/* print module version information */
++	dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
++		(i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
++		(i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
++
++	/* initialize HW */
++	ret = ltq_i2c_hw_init(adap);
++	if (ret) {
++		dev_err(&pdev->dev, "can't configure adapter\n");
++		i2c_del_adapter(adap);
++		platform_set_drvdata(pdev, NULL);
++		goto out;
++	} else {
++		dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
++	}
++
++out:
++	/* if init failed, we need to deactivate the clock gate */
++	if (ret)
++		clk_deactivate(priv->clk_gate);
++
++	return ret;
++}
++
++static int ltq_i2c_remove(struct platform_device *pdev)
++{
++	struct ltq_i2c *priv = platform_get_drvdata(pdev);
++
++	/* disable bus */
++	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++	/* power down the core */
++	clk_deactivate(priv->clk_gate);
++
++	/* remove driver */
++	i2c_del_adapter(&priv->adap);
++	kfree(priv);
++
++	dev_dbg(&pdev->dev, "removed\n");
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++static const struct of_device_id ltq_i2c_match[] = {
++	{ .compatible = "lantiq,lantiq-i2c" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ltq_i2c_match);
++
++static struct platform_driver ltq_i2c_driver = {
++	.probe	= ltq_i2c_probe,
++	.remove	= ltq_i2c_remove,
++	.driver	= {
++		.name	= DRV_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = ltq_i2c_match,
++	},
++};
++
++module_platform_driver(ltq_i2c_driver);
++
++MODULE_DESCRIPTION("Lantiq I2C bus adapter");
++MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>");
++MODULE_ALIAS("platform:" DRV_NAME);
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRV_VERSION);
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.h
+@@ -0,0 +1,234 @@
++#ifndef I2C_LANTIQ_H
++#define I2C_LANTIQ_H
++
++/* I2C register structure */
++struct lantiq_reg_i2c {
++	/* I2C Kernel Clock Control Register */
++	unsigned int clc; /* 0x00000000 */
++	/* Reserved */
++	unsigned int res_0; /* 0x00000004 */
++	/* I2C Identification Register */
++	unsigned int id; /* 0x00000008 */
++	/* Reserved */
++	unsigned int res_1; /* 0x0000000C */
++	/*
++	 * I2C RUN Control Register
++	 * This register enables and disables the I2C peripheral. Before
++	 * enabling, the I2C has to be configured properly. After enabling
++	 * no configuration is possible
++	 */
++	unsigned int run_ctrl; /* 0x00000010 */
++	/*
++	 * I2C End Data Control Register
++	 * This register is used to either turn around the data transmission
++	 * direction or to address another slave without sending a stop
++	 * condition. Also the software can stop the slave-transmitter by
++	 * sending a not-accolade when working as master-receiver or even
++	 * stop data transmission immediately when operating as
++	 * master-transmitter. The writing to the bits of this control
++	 * register is only effective when in MASTER RECEIVES BYTES, MASTER
++	 * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
++	 */
++	unsigned int endd_ctrl; /* 0x00000014 */
++	/*
++	 * I2C Fractional Divider Configuration Register
++	 * These register is used to program the fractional divider of the I2C
++	 * bus. Before the peripheral is switched on by setting the RUN-bit the
++	 * two (fixed) values for the two operating frequencies are programmed
++	 * into these (configuration) registers. The Register FDIV_HIGH_CFG has
++	 * the same layout as I2C_FDIV_CFG.
++	 */
++	unsigned int fdiv_cfg; /* 0x00000018 */
++	/*
++	 * I2C Fractional Divider (highspeed mode) Configuration Register
++	 * These register is used to program the fractional divider of the I2C
++	 * bus. Before the peripheral is switched on by setting the RUN-bit the
++	 * two (fixed) values for the two operating frequencies are programmed
++	 * into these (configuration) registers. The Register FDIV_CFG has the
++	 * same layout as I2C_FDIV_CFG.
++	 */
++	unsigned int fdiv_high_cfg; /* 0x0000001C */
++	/* I2C Address Configuration Register */
++	unsigned int addr_cfg; /* 0x00000020 */
++	/* I2C Bus Status Register
++	 * This register gives a status information of the I2C. This additional
++	 * information can be used by the software to start proper actions.
++	 */
++	unsigned int bus_stat; /* 0x00000024 */
++	/* I2C FIFO Configuration Register */
++	unsigned int fifo_cfg; /* 0x00000028 */
++	/* I2C Maximum Received Packet Size Register */
++	unsigned int mrps_ctrl; /* 0x0000002C */
++	/* I2C Received Packet Size Status Register */
++	unsigned int rps_stat; /* 0x00000030 */
++	/* I2C Transmit Packet Size Register */
++	unsigned int tps_ctrl; /* 0x00000034 */
++	/* I2C Filled FIFO Stages Status Register */
++	unsigned int ffs_stat; /* 0x00000038 */
++	/* Reserved */
++	unsigned int res_2; /* 0x0000003C */
++	/* I2C Timing Configuration Register */
++	unsigned int tim_cfg; /* 0x00000040 */
++	/* Reserved */
++	unsigned int res_3[7]; /* 0x00000044 */
++	/* I2C Error Interrupt Request Source Mask Register */
++	unsigned int err_irqsm; /* 0x00000060 */
++	/* I2C Error Interrupt Request Source Status Register */
++	unsigned int err_irqss; /* 0x00000064 */
++	/* I2C Error Interrupt Request Source Clear Register */
++	unsigned int err_irqsc; /* 0x00000068 */
++	/* Reserved */
++	unsigned int res_4; /* 0x0000006C */
++	/* I2C Protocol Interrupt Request Source Mask Register */
++	unsigned int p_irqsm; /* 0x00000070 */
++	/* I2C Protocol Interrupt Request Source Status Register */
++	unsigned int p_irqss; /* 0x00000074 */
++	/* I2C Protocol Interrupt Request Source Clear Register */
++	unsigned int p_irqsc; /* 0x00000078 */
++	/* Reserved */
++	unsigned int res_5; /* 0x0000007C */
++	/* I2C Raw Interrupt Status Register */
++	unsigned int ris; /* 0x00000080 */
++	/* I2C Interrupt Mask Control Register */
++	unsigned int imsc; /* 0x00000084 */
++	/* I2C Masked Interrupt Status Register */
++	unsigned int mis; /* 0x00000088 */
++	/* I2C Interrupt Clear Register */
++	unsigned int icr; /* 0x0000008C */
++	/* I2C Interrupt Set Register */
++	unsigned int isr; /* 0x00000090 */
++	/* I2C DMA Enable Register */
++	unsigned int dmae; /* 0x00000094 */
++	/* Reserved */
++	unsigned int res_6[8154]; /* 0x00000098 */
++	/* I2C Transmit Data Register */
++	unsigned int txd; /* 0x00008000 */
++	/* Reserved */
++	unsigned int res_7[4095]; /* 0x00008004 */
++	/* I2C Receive Data Register */
++	unsigned int rxd; /* 0x0000C000 */
++	/* Reserved */
++	unsigned int res_8[4095]; /* 0x0000C004 */
++};
++
++/*
++ * Clock Divider for Normal Run Mode
++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long
++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx
++ * on reading.
++ */
++#define I2C_CLC_RMC_MASK 0x0000FF00
++/* field offset */
++#define I2C_CLC_RMC_OFFSET 8
++
++/* Fields of "I2C Identification Register" */
++/* Module ID */
++#define I2C_ID_ID_MASK 0x0000FF00
++/* field offset */
++#define I2C_ID_ID_OFFSET 8
++/* Revision */
++#define I2C_ID_REV_MASK 0x000000FF
++/* field offset */
++#define I2C_ID_REV_OFFSET 0
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_BREQ_INT_EN 0x00000008
++/* Enable */
++#define I2C_IMSC_LBREQ_INT_EN 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_INC_OFFSET 16
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_I2C_P_INT_EN 0x00000020
++/* Enable */
++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
++
++/* Fields of "I2C Error Interrupt Request Source Status Register" */
++/* TXF_OFL */
++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
++/* TXF_UFL */
++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
++/* RXF_OFL */
++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
++/* RXF_UFL */
++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
++
++/* Fields of "I2C Raw Interrupt Status Register" */
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* TX FIFO Flow Control */
++#define I2C_FIFO_CFG_TXFC 0x00020000
++/* RX FIFO Flow Control */
++#define I2C_FIFO_CFG_RXFC 0x00010000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
++/* 1 word */
++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* 1 word */
++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
++/* Stop on Packet End Enable */
++#define I2C_ADDR_CFG_SOPE_EN 0x00200000
++/* Stop on Not Acknowledge Enable */
++#define I2C_ADDR_CFG_SONA_EN 0x00100000
++/* Enable */
++#define I2C_ADDR_CFG_MnS_EN 0x00080000
++
++/* Fields of "I2C Interrupt Clear Register" */
++/* Clear */
++#define I2C_ICR_BREQ_INT_CLR 0x00000008
++/* Clear */
++#define I2C_ICR_LBREQ_INT_CLR 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_DEC_OFFSET 0
++
++/* Fields of "I2C Bus Status Register" */
++/* Bus Status */
++#define I2C_BUS_STAT_BS_MASK 0x00000003
++/* Read from I2C Bus. */
++#define I2C_BUS_STAT_RNW_READ 0x00000004
++/* I2C Bus is free. */
++#define I2C_BUS_STAT_BS_FREE 0x00000000
++/*
++ * The device is working as master and has claimed the control on the
++ * I2C-bus (busy master).
++ */
++#define I2C_BUS_STAT_BS_BM 0x00000002
++
++/* Fields of "I2C RUN Control Register" */
++/* Enable */
++#define I2C_RUN_CTRL_RUN_EN 0x00000001
++
++/* Fields of "I2C End Data Control Register" */
++/*
++ * Set End of Transmission
++ * Note:Do not write '1' to this bit when bus is free. This will cause an
++ * abort after the first byte when a new transfer is started.
++ */
++#define I2C_ENDD_CTRL_SETEND 0x00000002
++
++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
++/* NACK */
++#define I2C_P_IRQSS_NACK 0x00000010
++/* AL */
++#define I2C_P_IRQSS_AL 0x00000008
++/* RX */
++#define I2C_P_IRQSS_RX 0x00000040
++/* TX_END */
++#define I2C_P_IRQSS_TX_END 0x00000020
++
++
++#endif /* I2C_LANTIQ_H */
diff --git a/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
new file mode 100644
index 0000000000..aea5716596
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
@@ -0,0 +1,218 @@
+From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Sep 2014 22:42:14 +0200
+Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +
+ arch/mips/lantiq/xway/Makefile                     |   3 +
+ arch/mips/lantiq/xway/ath5k_eep.c                  | 136 +++++++++++++++++++++
+ arch/mips/lantiq/xway/eth_mac.c                    |  25 ++++
+ drivers/net/ethernet/lantiq_etop.c                 |   6 +-
+ 5 files changed, 172 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
+ create mode 100644 arch/mips/lantiq/xway/eth_mac.c
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev,
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
+ 
++/* allow the ethernet driver to load a flash mapped mac addr */
++const u8* ltq_get_eth_mac(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -8,3 +8,6 @@ obj-y += timer.o
+ endif
+ 
+ obj-y += vmmc.o
++
++obj-y += eth_mac.o
++obj-$(CONFIG_PCI) += ath5k_eep.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/ath5k_eep.c
+@@ -0,0 +1,136 @@
++/*
++ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
++ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
++ *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
++ *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/etherdevice.h>
++#include <linux/ath5k_platform.h>
++#include <linux/pci.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <lantiq_soc.h>
++
++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
++struct ath5k_platform_data ath5k_pdata;
++static u8 athxk_eeprom_mac[6];
++
++static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
++{
++	dev->dev.platform_data = &ath5k_pdata;
++	return 0;
++}
++
++static int ath5k_eep_load;
++int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
++	int mac_offset;
++	u32 mac_inc = 0;
++	int i;
++	struct mtd_info *the_mtd;
++	size_t flash_readlen;
++	const __be32 *list;
++	const char *part;
++	phandle phandle;
++
++	list = of_get_property(np, "ath,eep-flash", &i);
++	if (!list || (i != (2 * sizeof(*list))))
++		return -ENODEV;
++
++	phandle = be32_to_cpup(list++);
++	if (phandle)
++		mtd_np = of_find_node_by_phandle(phandle);
++
++	if (!mtd_np)
++		return -ENODEV;
++
++	part = of_get_property(mtd_np, "label", NULL);
++	if (!part)
++		part = mtd_np->name;
++
++	the_mtd = get_mtd_device_nm(part);
++	if (IS_ERR(the_mtd))
++		return -ENODEV;
++
++	ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
++
++	i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
++		&flash_readlen, (void *) ath5k_pdata.eeprom_data);
++
++	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
++		size_t mac_readlen;
++		mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
++			(void *) athxk_eeprom_mac);
++	}
++	put_mtd_device(the_mtd);
++
++	if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
++		dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
++		return -ENODEV;
++	}
++
++	if (of_find_property(np, "ath,eep-swap", NULL))
++		for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
++			ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
++		ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac)) {
++		dev_warn(&pdev->dev, "using random mac\n");
++		eth_random_addr(athxk_eeprom_mac);
++	}
++
++	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
++		athxk_eeprom_mac[5] += mac_inc;
++
++	ath5k_pdata.macaddr = athxk_eeprom_mac;
++	ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
++
++	dev_info(&pdev->dev, "loaded ath5k eeprom\n");
++
++	return 0;
++}
++
++static struct of_device_id ath5k_eeprom_ids[] = {
++	{ .compatible = "ath5k,eeprom" },
++	{ }
++};
++
++static struct platform_driver ath5k_eeprom_driver = {
++	.driver		= {
++		.name		= "ath5k,eeprom",
++		.owner	= THIS_MODULE,
++		.of_match_table	= of_match_ptr(ath5k_eeprom_ids),
++	},
++};
++
++static int __init of_ath5k_eeprom_init(void)
++{
++	int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++
++	if (ret)
++		ath5k_eep_load = 1;
++
++	return ret;
++}
++
++static int __init of_ath5k_eeprom_init_late(void)
++{
++	if (!ath5k_eep_load)
++		return 0;
++
++	return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++}
++late_initcall(of_ath5k_eeprom_init_late);
++subsys_initcall(of_ath5k_eeprom_init);
+--- /dev/null
++++ b/arch/mips/lantiq/xway/eth_mac.c
+@@ -0,0 +1,25 @@
++/*
++ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/if_ether.h>
++
++static u8 eth_mac[6];
++static int eth_mac_set;
++
++const u8* ltq_get_eth_mac(void)
++{
++	return eth_mac;
++}
++
++static int __init setup_ethaddr(char *str)
++{
++	eth_mac_set = mac_pton(str, eth_mac);
++	return !eth_mac_set;
++}
++early_param("ethaddr", setup_ethaddr);
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -763,7 +763,11 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 
+-	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
++	memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
++
++	if (!is_valid_ether_addr(mac.sa_data))
++		memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
++
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+ 		pr_warn("etop: invalid MAC, using random\n");
+ 		eth_random_addr(mac.sa_data);
diff --git a/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch
new file mode 100644
index 0000000000..c81222af57
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0042-arch-mips-increase-io_space_limit.patch
@@ -0,0 +1,24 @@
+From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 3 Jun 2016 13:12:20 +0200
+Subject: [PATCH] arch: mips: increase io_space_limit
+
+this value comes from x86 and breaks some pci devices
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/spaces.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __ASM_MACH_LANTIQ_SPACES_H_
++#define __ASM_MACH_LANTIQ_SPACES_H_
++
++#define IO_SPACE_LIMIT  0xffffffff
++
++#include <asm/mach-generic/spaces.h>
++#endif
diff --git a/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch
new file mode 100644
index 0000000000..a3bbda7c33
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch
@@ -0,0 +1,80 @@
+From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:55:24 +0100
+Subject: [PATCH 2/2] usb: dwc2:  add support for other Lantiq SoCs
+
+The size of the internal RAM of the DesignWare USB controller changed
+between the different Lantiq SoCs. We have the following sizes:
+
+Amazon + Danube: 8 KByte
+Amazon SE + arx100: 2 KByte
+xrx200 + xrx300: 2.5 KByte
+
+For Danube SoC we do not provide the params and let the driver decide
+to use sane defaults, for the Amazon SE and arx100 we use small fifos
+and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
+The auto detection of max_transfer_size and max_packet_count should
+work, so remove it.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 39 insertions(+), 7 deletions(-)
+
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -115,7 +115,15 @@ static void dwc2_set_rk_params(struct dw
+ 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ }
+ 
+-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
++{
++	struct dwc2_core_params *p = &hsotg->params;
++
++	p->otg_caps.hnp_support = false;
++	p->otg_caps.srp_support = false;
++}
++
++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+ 
+@@ -124,12 +132,21 @@ static void dwc2_set_ltq_params(struct d
+ 	p->host_rx_fifo_size = 288;
+ 	p->host_nperio_tx_fifo_size = 128;
+ 	p->host_perio_tx_fifo_size = 96;
+-	p->max_transfer_size = 65535;
+-	p->max_packet_count = 511;
+ 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ 		GAHBCFG_HBSTLEN_SHIFT;
+ }
+ 
++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
++{
++	struct dwc2_core_params *p = &hsotg->params;
++
++	p->otg_caps.hnp_support = false;
++	p->otg_caps.srp_support = false;
++	p->host_rx_fifo_size = 288;
++	p->host_nperio_tx_fifo_size = 128;
++	p->host_perio_tx_fifo_size = 136;
++}
++
+ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+@@ -241,8 +258,11 @@ const struct of_device_id dwc2_of_match_
+ 	{ .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
+ 	{ .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
+ 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
+-	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
+-	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
++	{ .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
++	{ .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
++	{ .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
++	{ .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
++	{ .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
+ 	{ .compatible = "snps,dwc2" },
+ 	{ .compatible = "samsung,s3c6400-hsotg",
+ 	  .data = dwc2_set_s3c6400_params },
diff --git a/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch
new file mode 100644
index 0000000000..dca9880e8f
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0051-MIPS-lantiq-improve-USB-initialization.patch
@@ -0,0 +1,49 @@
+From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:40:12 +0100
+Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
+
+This adds code to initialize the USB controller and PHY also on Danube,
+Amazon SE and AR10. This code is based on the Vendor driver from
+different UGW versions and compared to the hardware documentation.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/lantiq/xway/sysctrl.c |  20 +++++++
+ 2 files changed, 110 insertions(+), 30 deletions(-)
+
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk)
+ 		pr_warn("deactivating PMU module failed!");
+ }
+ 
++static void usb_set_clock(void)
++{
++	unsigned int val = ltq_cgu_r32(ifccr);
++
++	if (of_machine_is_compatible("lantiq,ar10") ||
++	    of_machine_is_compatible("lantiq,grx390")) {
++		val &= ~0x03; /* XTAL divided by 3 */
++	} else if (of_machine_is_compatible("lantiq,ar9") ||
++		   of_machine_is_compatible("lantiq,vr9")) {
++		/* TODO: this depends on the XTAL frequency */
++		val |= 0x03; /* XTAL divided by 3 */
++	} else if (of_machine_is_compatible("lantiq,ase")) {
++		val |= 0x20; /* from XTAL */
++	} else if (of_machine_is_compatible("lantiq,danube")) {
++		val |= 0x30; /* 12 MHz, generated from 36 MHz */
++	}
++	ltq_cgu_w32(val, ifccr);
++}
++
+ /* the pci enable helper */
+ static int pci_enable(struct clk *clk)
+ {
+@@ -589,4 +608,5 @@ void __init ltq_soc_init(void)
+ 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
+ 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ 	}
++	usb_set_clock();
+ }
diff --git a/target/linux/lantiq/patches-6.1/0101-find_active_root.patch b/target/linux/lantiq/patches-6.1/0101-find_active_root.patch
new file mode 100644
index 0000000000..99e187a012
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0101-find_active_root.patch
@@ -0,0 +1,103 @@
+From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] find active root
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/parsers/ofpart_core.c
++++ b/drivers/mtd/parsers/ofpart_core.c
+@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d
+ 	return of_get_property(pp, "compatible", NULL);
+ }
+ 
++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
++						loff_t offset)
++{
++	static uint8_t root_id;
++	int err, len;
++
++	err = mtd_read(master, offset, 0x01, &len, &root_id);
++
++	if (mtd_is_bitflip(err) || !err)
++		return &root_id;
++
++	return NULL;
++}
++
++static void brnboot_set_active_root_part(struct mtd_partition *pparts,
++					 struct device_node **part_nodes,
++					 int nr_parts,
++					 uint8_t *root_id)
++{
++	int i;
++
++	for (i = 0; i < nr_parts; i++) {
++		int part_root_id;
++
++		if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
++		    && part_root_id == *root_id) {
++			pparts[i].name = "firmware";
++			break;
++		}
++	}
++}
++
+ static int parse_fixed_partitions(struct mtd_info *master,
+ 				  const struct mtd_partition **pparts,
+ 				  struct mtd_part_parser_data *data)
+@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct
+ 	struct device_node *pp;
+ 	int nr_parts, i, ret = 0;
+ 	bool dedicated = true;
++	uint8_t *proot_id = NULL;
++	struct device_node **part_nodes;
+ 
+ 	/* Pull of_node from the master device node */
+ 	mtd_node = mtd_get_of_node(master);
+@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct
+ 		return 0;
+ 
+ 	parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
+-	if (!parts)
++	part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);
++
++	if (!parts || !part_nodes)
+ 		return -ENOMEM;
+ 
+ 	i = 0;
+@@ -166,6 +202,11 @@ static int parse_fixed_partitions(struct
+ 		if (of_property_read_bool(pp, "slc-mode"))
+ 			parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;
+ 
++		if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
++			proot_id = brnboot_get_selected_root_part(master, parts[i].offset);
++
++		part_nodes[i] = pp;
++
+ 		i++;
+ 	}
+ 
+@@ -175,6 +216,11 @@ static int parse_fixed_partitions(struct
+ 	if (quirks && quirks->post_parse)
+ 		quirks->post_parse(master, parts, nr_parts);
+ 
++	if (proot_id)
++		brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);
++
++	kfree(part_nodes);
++
+ 	*pparts = parts;
+ 	return nr_parts;
+ 
+@@ -185,6 +231,7 @@ ofpart_fail:
+ ofpart_none:
+ 	of_node_put(pp);
+ 	kfree(parts);
++	kfree(part_nodes);
+ 	return ret;
+ }
+ 
diff --git a/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch
new file mode 100644
index 0000000000..b83bf992a6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -0,0 +1,486 @@
+From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 14 Oct 2014 11:04:00 +0000
+Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/Makefile           |   2 +-
+ arch/mips/pci/ifxmips_pcie.c     | 151 +++++++++++++++++++++++++++----
+ arch/mips/pci/ifxmips_pcie_vr9.h | 105 ---------------------
+ 3 files changed, 133 insertions(+), 125 deletions(-)
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,7 +41,7 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+-obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie.o fixup-lantiq-pcie.o
+ obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+--- a/arch/mips/pci/ifxmips_pcie.c
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -16,8 +16,15 @@
+ #include <asm/paccess.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ 
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++
+ #include "ifxmips_pcie.h"
+ #include "ifxmips_pcie_reg.h"
+ 
+@@ -25,11 +32,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+ 
+-#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +42,30 @@
+ static DEFINE_SPINLOCK(ifx_pcie_lock);
+ 
+ u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++static int pcie_reset_gpio;
++static struct phy *ltq_pcie_phy;
++static struct reset_control *ltq_pcie_reset;
++static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
+ 
+ static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
+     {
+         .ir_irq = {
+-            .irq  = IFX_PCIE_IR,
+             .name = "ifx_pcie_rc0",
+         },
+ 
+         .legacy_irq = {
+             {
+                 .irq_bit = PCIE_IRN_INTA,
+-                .irq     = IFX_PCIE_INTA,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTB,
+-                .irq     = IFX_PCIE_INTB,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTC,
+-                .irq     = IFX_PCIE_INTC,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTD,
+-                .irq     = IFX_PCIE_INTD,
+             },
+         },
+     },
+@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
+ 	printk("%s", buf);
+ }
+ 
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++	gpio_direction_output(pcie_reset_gpio, 1);
++	gpio_set_value(pcie_reset_gpio, 1);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(pcie_reset_gpio, 0);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++	mdelay(100);
++	gpio_direction_output(pcie_reset_gpio, 1);
++}
+ 
+ static inline int pcie_ltssm_enable(int pcie_port)
+ {
+@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+ 	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ 		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ 	if (ret)
+-		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++		printk(KERN_ERR "%s request irq %d failed\n", __func__,
++		       pcie_irqs[pcie_port].ir_irq.irq);
+ 
+ 	return ret;
+ }
+@@ -988,10 +1007,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
+ static int
+ pcie_rc_initialize(int pcie_port)
+ {
+-	int i;
++	int i, ret;
+ #define IFX_PCIE_PHY_LOOP_CNT  5
+ 
+-	pcie_rcu_endian_setup(pcie_port);
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
++			   IFX_RCU_AHB_BE_PCIE_M);
++
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   IFX_RCU_AHB_BE_PCIE_S);
++       if (switch_pcie_endianess) {
++	        regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++			           IFX_RCU_AHB_BE_XBAR_S);
++       }
++#else
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   0x0);
++#endif
++
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
++			   0x0);
+ 
+ 	pcie_ep_gpio_rst_init(pcie_port);
+ 
+@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
+ 	* reset PCIe PHY will solve this issue 
+ 	*/
+ 	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
+-		/* Disable PCIe PHY Analog part for sanity check */
+-		pcie_phy_pmu_disable(pcie_port);
+-
+-		pcie_phy_rst_assert(pcie_port);
+-		pcie_phy_rst_deassert(pcie_port);
+-
+-		/* Make sure PHY PLL is stable */
+-		udelay(20);
+-
+-		/* PCIe Core reset enabled, low active, sw programmed */
+-		pcie_core_rst_assert(pcie_port);
++		ret = phy_init(ltq_pcie_phy);
++		if (ret)
++			continue;
+ 
+ 		/* Put PCIe EP in reset status */
+ 		pcie_device_rst_assert(pcie_port);
+ 
+-		/* PCI PHY & Core reset disabled, high active, sw programmed */
+-		pcie_core_rst_deassert(pcie_port);
++		udelay(1);
++		reset_control_deassert(ltq_pcie_reset);
+ 
+-		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
+-		pcie_phy_clock_mode_setup(pcie_port);
++		ret = phy_power_on(ltq_pcie_phy);
++		if (ret) {
++			phy_exit(ltq_pcie_phy);
++			continue;
++		}
+ 
+ 		/* Enable PCIe PHY and Clock */
+ 		pcie_core_pmu_setup(pcie_port);
+@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
+ 		/* Once link is up, break out */
+ 		if (pcie_app_loigc_setup(pcie_port) == 0)
+ 			break;
++
++		phy_power_off(ltq_pcie_phy);
++		reset_control_assert(ltq_pcie_reset);
++		phy_exit(ltq_pcie_phy);
+ 	}
+ 	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
+ 		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
+@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
+ 	return 0;
+ }
+ 
+-static int __init ifx_pcie_bios_init(void)
++static int ifx_pcie_bios_probe(struct platform_device *pdev)
+ {
++    struct device_node *node = pdev->dev.of_node;
+     void __iomem *io_map_base;
+     int pcie_port;
+     int startup_port;
++    struct device_node *np;
++    struct pci_bus *bus;
++
++    /*
++     * In case a PCI device is physical present, the Lantiq PCI driver need
++     * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
++     * will work.
++     *
++     * In case the lantiq PCI driver is enabled in the device tree, check if
++     * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
++     * registered.
++     *
++     * It will fail if there is another PCI controller, this controller is
++     * registered before the Lantiq PCIe driver is probe and the lantiq PCI
++     */
++    np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
++
++    if (of_device_is_available(np)) {
++        bus = pci_find_next_bus(bus);
++
++        if (!bus)
++	     return -EPROBE_DEFER;
++    }
+ 
+     /* Enable AHB Master/ Slave */
+     pcie_ahb_pmu_setup();
+ 
+     startup_port = IFX_PCIE_PORT0;
+-    
++
++    ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
++    if (IS_ERR(ltq_pcie_phy))
++        return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++                             "failed to get the PCIe PHY\n");
++
++    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
++    if (IS_ERR(ltq_pcie_reset)) {
++        dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
++        return PTR_ERR(ltq_pcie_reset);
++    }
++
++    if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++        switch_pcie_endianess = true;
++        dev_info(&pdev->dev, "switch pcie endianess requested\n");
++    } else {
++        switch_pcie_endianess = false;
++    }
++
++    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
++    if (IS_ERR(ltq_rcu_regmap))
++        return PTR_ERR(ltq_rcu_regmap);
++
++    pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
++    if (gpio_is_valid(pcie_reset_gpio)) {
++        int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
++        if (ret) {
++            dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
++            return ret;
++        }
++        gpio_direction_output(pcie_reset_gpio, 1);
++    }
++
+     for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
+ 	if (pcie_rc_initialize(pcie_port) == 0) {
+ 	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
+@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+                 IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
+                 return -ENOMEM;
+             }
++            pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++            if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++                return pcie_irqs[pcie_port].ir_irq.irq;
++
++            for (int i = 0; i <= 3; i++){
++                pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++                if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++                    return pcie_irqs[pcie_port].legacy_irq[i].irq;
++            }
++
+             ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++            pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
+ 
+             register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
+             /* XXX, clear error status */
+@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi
+ 
+     return 0;
+ }
++
++static const struct of_device_id ifxmips_pcie_match[] = {
++        { .compatible = "lantiq,pcie-xrx200" },
++        {},
++};
++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
++
++static struct platform_driver ltq_pci_driver = {
++        .probe = ifx_pcie_bios_probe,
++        .driver = {
++                .name = "pcie-xrx200",
++                .owner = THIS_MODULE,
++                .of_match_table = ifxmips_pcie_match,
++        },
++};
++
++int __init ifx_pcie_bios_init(void)
++{
++        int ret = platform_driver_register(&ltq_pci_driver);
++        if (ret)
++                pr_info("pcie-xrx200: Error registering platform driver!");
++        return ret;
++}
++
+ arch_initcall(ifx_pcie_bios_init);
+ 
+ MODULE_LICENSE("GPL");
+--- a/arch/mips/pci/ifxmips_pcie_vr9.h
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -22,8 +22,6 @@
+ #include <linux/gpio.h>
+ #include <lantiq_soc.h>
+ 
+-#define IFX_PCIE_GPIO_RESET  494
+-
+ #define IFX_REG_R32    ltq_r32
+ #define IFX_REG_W32    ltq_w32
+ #define CONFIG_IFX_PCIE_HW_SWAP
+@@ -54,21 +52,6 @@
+ #define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
+ 
+ 
+-static inline void pcie_ep_gpio_rst_init(int pcie_port)
+-{
+-
+-	gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-
+-/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
+-}
+-
+ static inline void pcie_ahb_pmu_setup(void) 
+ {
+ 	/* Enable AHB bus master/slave */
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
+     //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_rcu_endian_setup(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-#ifdef CONFIG_IFX_PCIE_HW_SWAP
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg |= IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#else 
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
+-}
+-
+ static inline void pcie_phy_pmu_enable(int pcie_port)
+ {
+ 	struct clk *clk;
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
+ //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
+ }
+ 
+-static inline void pcie_pdi_big_endian(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* SRAM2PDI endianness control. */
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-    /* Config AHB->PCIe and PDI endianness */
+-    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-}
+-
+ static inline void pcie_pdi_pmu_enable(int pcie_port)
+ {
+     /* Enable PDI to access PCIe PHY register */
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
+     //PDI_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_core_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-
+-    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
+-    reg |= 0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_core_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    /* Reset PCIe PHY & Core, bit 22 */
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg |= 0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_device_rst_assert(int pcie_port)
+-{
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
+-//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+-static inline void pcie_device_rst_deassert(int pcie_port)
+-{
+-    mdelay(100);
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+ static inline void pcie_core_pmu_setup(int pcie_port)
+ {
+ 	struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+ 
+ typedef struct ifx_pcie_ir_irq {
+-    const unsigned int irq;
++    unsigned int irq;
+     const char name[16];
+ }ifx_pcie_ir_irq_t;
+ 
+ typedef struct ifx_pcie_legacy_irq{
+     const u32 irq_bit;
+-    const int irq;
++    int irq;
+ }ifx_pcie_legacy_irq_t;
+ 
+ typedef struct ifx_pcie_irq {
diff --git a/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch
new file mode 100644
index 0000000000..51810fe924
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0152-lantiq-VPE.patch
@@ -0,0 +1,187 @@
+From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Thu, 20 Oct 2016 21:32:00 +0200
+Subject: [PATCH] lantiq: vpe
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/Kconfig                  |  6 ++++
+ arch/mips/include/asm/mipsmtregs.h |  5 ++++
+ arch/mips/include/asm/vpe.h        |  9 ++++++
+ arch/mips/kernel/vpe-mt.c          | 47 ++++++++++++++++++++++++++++++
+ arch/mips/kernel/vpe.c             | 35 ++++++++++++++++++++++
+ arch/mips/lantiq/prom.c            |  4 +++
+ 6 files changed, 106 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2306,6 +2306,12 @@ config MIPS_VPE_LOADER
+ 	  Includes a loader for loading an elf relocatable object
+ 	  onto another VPE and running it.
+ 
++config IFX_VPE_EXT
++	bool "IFX APRP Extensions"
++	depends on MIPS_VPE_LOADER
++	help
++	  IFX included extensions in APRP
++
+ config MIPS_VPE_LOADER_CMP
+ 	bool
+ 	default "y"
+--- a/arch/mips/include/asm/mipsmtregs.h
++++ b/arch/mips/include/asm/mipsmtregs.h
+@@ -31,6 +31,9 @@
+ #define read_c0_vpeconf1()		__read_32bit_c0_register($1, 3)
+ #define write_c0_vpeconf1(val)		__write_32bit_c0_register($1, 3, val)
+ 
++#define read_c0_vpeopt()		__read_32bit_c0_register($1, 7)
++#define write_c0_vpeopt(val)		__write_32bit_c0_register($1, 7, val)
++
+ #define read_c0_tcstatus()		__read_32bit_c0_register($2, 1)
+ #define write_c0_tcstatus(val)		__write_32bit_c0_register($2, 1, val)
+ 
+@@ -377,6 +380,8 @@ do {									\
+ #define write_vpe_c0_vpeconf0(val)	mttc0(1, 2, val)
+ #define read_vpe_c0_vpeconf1()		mftc0(1, 3)
+ #define write_vpe_c0_vpeconf1(val)	mttc0(1, 3, val)
++#define read_vpe_c0_vpeopt()		mftc0(1, 7)
++#define write_vpe_c0_vpeopt(val)	mttc0(1, 7, val)
+ #define read_vpe_c0_count()		mftc0(9, 0)
+ #define write_vpe_c0_count(val)		mttc0(9, 0, val)
+ #define read_vpe_c0_status()		mftc0(12, 0)
+--- a/arch/mips/include/asm/vpe.h
++++ b/arch/mips/include/asm/vpe.h
+@@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc);
+ 
+ int __init vpe_module_init(void);
+ void __exit vpe_module_exit(void);
++
++/* For the explanation of the APIs please refer the section "MT APRP Kernel
++ * Programming" in AR9 SW Architecture Specification
++ */
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
++int32_t vpe1_sw_stop(uint32_t flags);
++uint32_t vpe1_get_load_addr(uint32_t flags);
++uint32_t vpe1_get_max_mem(uint32_t flags);
++
+ #endif /* _ASM_VPE_H */
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -416,6 +416,8 @@ int __init vpe_module_init(void)
+ 			}
+ 
+ 			v->ntcs = hw_tcs - aprp_cpu_index();
++			write_tc_c0_tcbind((read_tc_c0_tcbind() &
++						~TCBIND_CURVPE) | 1);
+ 
+ 			/* add the tc to the list of this vpe's tc's. */
+ 			list_add(&t->tc, &v->tc);
+@@ -519,3 +521,47 @@ void __exit vpe_module_exit(void)
+ 			release_vpe(v);
+ 	}
+ }
++
++#ifdef CONFIG_IFX_VPE_EXT
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
++{
++	enum vpe_state state;
++	struct vpe *v = get_vpe(tclimit);
++	struct vpe_notifications *not;
++
++	if (tcmask || flags) {
++		pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
++		return -1;
++	}
++
++	state = xchg(&v->state, VPE_STATE_INUSE);
++	if (state != VPE_STATE_UNUSED) {
++		vpe_stop(v);
++
++		list_for_each_entry(not, &v->notify, list) {
++			not->stop(tclimit);
++		}
++	}
++
++	v->__start = (unsigned long)sw_start_addr;
++
++	if (!vpe_run(v)) {
++		pr_debug("VPE loader: VPE1 running successfully\n");
++		return 0;
++	}
++	return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_start);
++
++int32_t vpe1_sw_stop(uint32_t flags)
++{
++	struct vpe *v = get_vpe(tclimit);
++
++	if (!vpe_free(v)) {
++		pr_debug("RP Stopped\n");
++		return 0;
++	} else
++		return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_stop);
++#endif
+--- a/arch/mips/kernel/vpe.c
++++ b/arch/mips/kernel/vpe.c
+@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
+ 	.tc_list	= LIST_HEAD_INIT(vpecontrol.tc_list)
+ };
+ 
++#ifdef CONFIG_IFX_VPE_EXT
++unsigned int vpe1_load_addr;
++
++static int __init load_address(char *str)
++{
++	get_option(&str, &vpe1_load_addr);
++	return 1;
++}
++__setup("vpe1_load_addr=", load_address);
++
++static unsigned int vpe1_mem;
++static int __init vpe1mem(char *str)
++{
++	vpe1_mem = memparse(str, &str);
++	return 1;
++}
++__setup("vpe1_mem=", vpe1mem);
++
++uint32_t vpe1_get_load_addr(uint32_t flags)
++{
++	return vpe1_load_addr;
++}
++EXPORT_SYMBOL(vpe1_get_load_addr);
++
++uint32_t vpe1_get_max_mem(uint32_t flags)
++{
++	if (!vpe1_mem)
++		return P_SIZE;
++	else
++		return vpe1_mem;
++}
++EXPORT_SYMBOL(vpe1_get_max_mem);
++
++#endif
++
+ /* get the vpe associated with this minor */
+ struct vpe *get_vpe(int minor)
+ {
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -42,10 +42,14 @@ extern const struct plat_smp_ops vsmp_sm
+ static struct plat_smp_ops lantiq_smp_ops;
+ #endif
+ 
++/* for Multithreading (APRP), vpe.c will use it */
++unsigned long cp0_memsize;
++
+ const char *get_system_type(void)
+ {
+ 	return soc_info.sys_type;
+ }
++EXPORT_SYMBOL(ltq_soc_type);
+ 
+ int ltq_soc_type(void)
+ {
diff --git a/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch
new file mode 100644
index 0000000000..9214f786d7
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0154-lantiq-pci-bar11mask-fix.patch
@@ -0,0 +1,32 @@
+From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 8 Nov 2016 17:38:00 +0100
+Subject: [PATCH] lantiq: pci: bar11mask fix
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/pci-lantiq.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -59,6 +59,8 @@
+ #define ltq_pci_cfg_w32(x, y)	ltq_w32((x), ltq_pci_mapped_cfg + (y))
+ #define ltq_pci_cfg_r32(x)	ltq_r32(ltq_pci_mapped_cfg + (x))
+ 
++extern u32 max_low_pfn;
++
+ __iomem void *ltq_pci_mapped_cfg;
+ static __iomem void *ltq_pci_membase;
+ 
+@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi
+ 	u32 mem, bar11mask;
+ 
+ 	/* BAR11MASK value depends on available memory on system. */
+-	mem = get_num_physpages() * PAGE_SIZE;
+-	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
++	mem = max_low_pfn << PAGE_SHIFT;
++	bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;
+ 
+ 	return bar11mask;
+ }
diff --git a/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch
new file mode 100644
index 0000000000..015acabcfe
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0155-lantiq-VPE-nosmp.patch
@@ -0,0 +1,24 @@
+From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Mon, 13 Mar 2017 23:42:00 +0100
+Subject: [PATCH] lantiq: vpe nosmp
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/kernel/vpe-mt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -131,7 +131,10 @@ int vpe_run(struct vpe *v)
+ 	 * kernels need to turn it on, even if that wasn't the pre-dvpe() state.
+ 	 */
+ #ifdef CONFIG_SMP
+-	evpe(vpeflags);
++	if (!setup_max_cpus) /* nosmp is set */
++		evpe(EVPE_ENABLE);
++	else
++		evpe(vpeflags);
+ #else
+ 	evpe(EVPE_ENABLE);
+ #endif
diff --git a/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch
new file mode 100644
index 0000000000..a83325c094
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0160-owrt-lantiq-multiple-flash.patch
@@ -0,0 +1,230 @@
+From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001
+From: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+Date: Fri, 14 Nov 2014 17:06:00 +0000
+Subject: [PATCH] owrt: lantiq: multiple flash
+
+Signed-off-by: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+---
+ drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++-----------
+ 1 file changed, 109 insertions(+), 59 deletions(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/cfi.h>
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/mtd/concat.h>
+ #include <linux/of.h>
+ 
+ #include <lantiq_soc.h>
+@@ -36,13 +37,16 @@ enum {
+ 	LTQ_NOR_NORMAL
+ };
+ 
++#define MAX_RESOURCES		4
++
+ struct ltq_mtd {
+-	struct resource *res;
+-	struct mtd_info *mtd;
+-	struct map_info *map;
++	struct mtd_info *mtd[MAX_RESOURCES];
++	struct mtd_info	*cmtd;
++	struct map_info map[MAX_RESOURCES];
+ };
+ 
+ static const char ltq_map_name[] = "ltq_nor";
++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL };
+ 
+ static map_word
+ ltq_read16(struct map_info *map, unsigned long adr)
+@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign
+ }
+ 
+ static int
++ltq_mtd_remove(struct platform_device *pdev)
++{
++	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
++	int i;
++
++	if (ltq_mtd == NULL)
++		return 0;
++
++	if (ltq_mtd->cmtd) {
++		mtd_device_unregister(ltq_mtd->cmtd);
++		if (ltq_mtd->cmtd != ltq_mtd->mtd[0])
++			mtd_concat_destroy(ltq_mtd->cmtd);
++	}
++
++	for (i = 0; i < MAX_RESOURCES; i++) {
++		if (ltq_mtd->mtd[i] != NULL)
++			map_destroy(ltq_mtd->mtd[i]);
++	}
++
++	kfree(ltq_mtd);
++
++	return 0;
++}
++
++static int
+ ltq_mtd_probe(struct platform_device *pdev)
+ {
+ 	struct ltq_mtd *ltq_mtd;
+ 	struct cfi_private *cfi;
+-	int err;
++	int err = 0;
++	int i;
++	int devices_found = 0;
++
++	static const char *rom_probe_types[] = {
++		"cfi_probe", "jedec_probe", NULL
++	};
++	const char **type;
+ 
+ 	ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
+ 	if (!ltq_mtd)
+@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd
+ 
+ 	platform_set_drvdata(pdev, ltq_mtd);
+ 
+-	ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	if (!ltq_mtd->res) {
+-		dev_err(&pdev->dev, "failed to get memory resource\n");
+-		return -ENOENT;
++	for (i = 0; i < pdev->num_resources; i++) {
++		printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n",
++		       (unsigned long long)resource_size(&pdev->resource[i]),
++		       (unsigned long long)pdev->resource[i].start);
++	
++		if (!devm_request_mem_region(&pdev->dev,
++			pdev->resource[i].start,
++			resource_size(&pdev->resource[i]),
++			dev_name(&pdev->dev))) {
++			dev_err(&pdev->dev, "Could not reserve memory region\n");
++			return -ENOMEM;
++		}
++
++		ltq_mtd->map[i].name = ltq_map_name;
++		ltq_mtd->map[i].bankwidth = 2;
++		ltq_mtd->map[i].read = ltq_read16;
++		ltq_mtd->map[i].write = ltq_write16;
++		ltq_mtd->map[i].copy_from = ltq_copy_from;
++		ltq_mtd->map[i].copy_to = ltq_copy_to;
++
++		if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++			ltq_mtd->map[i].phys = NO_XIP;
++		else
++			ltq_mtd->map[i].phys = pdev->resource[i].start;
++		ltq_mtd->map[i].size = resource_size(&pdev->resource[i]);
++		ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,
++						 ltq_mtd->map[i].size);
++		if (IS_ERR(ltq_mtd->map[i].virt))
++			return PTR_ERR(ltq_mtd->map[i].virt);
++
++		if (ltq_mtd->map[i].virt == NULL) {
++			dev_err(&pdev->dev, "Failed to ioremap flash region\n");
++			err = PTR_ERR(ltq_mtd->map[i].virt);
++			goto err_out;
++		}
++
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;
++		for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)
++			ltq_mtd->mtd[i] = do_map_probe(*type, &ltq_mtd->map[i]);
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;
++
++		if (!ltq_mtd->mtd[i]) {
++			dev_err(&pdev->dev, "probing failed\n");
++			return -ENXIO;
++		} else {
++			devices_found++;
++		}
++
++		ltq_mtd->mtd[i]->owner = THIS_MODULE;
++		ltq_mtd->mtd[i]->dev.parent = &pdev->dev;
++
++		cfi = ltq_mtd->map[i].fldrv_priv;
++		cfi->addr_unlock1 ^= 1;
++		cfi->addr_unlock2 ^= 1;
+ 	}
+ 
+-	ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),
+-				    GFP_KERNEL);
+-	if (!ltq_mtd->map)
+-		return -ENOMEM;
+-
+-	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+-		ltq_mtd->map->phys = NO_XIP;
+-	else
+-		ltq_mtd->map->phys = ltq_mtd->res->start;
+-	ltq_mtd->res->start;
+-	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+-	ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
+-	if (IS_ERR(ltq_mtd->map->virt))
+-		return PTR_ERR(ltq_mtd->map->virt);
+-
+-	ltq_mtd->map->name = ltq_map_name;
+-	ltq_mtd->map->bankwidth = 2;
+-	ltq_mtd->map->read = ltq_read16;
+-	ltq_mtd->map->write = ltq_write16;
+-	ltq_mtd->map->copy_from = ltq_copy_from;
+-	ltq_mtd->map->copy_to = ltq_copy_to;
+-
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
+-	ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
+-
+-	if (!ltq_mtd->mtd) {
+-		dev_err(&pdev->dev, "probing failed\n");
+-		return -ENXIO;
++	if (devices_found == 1) {
++		ltq_mtd->cmtd = ltq_mtd->mtd[0];
++	} else if (devices_found > 1) {
++		/*
++		 * We detected multiple devices. Concatenate them together.
++		 */
++		ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
++		if (ltq_mtd->cmtd == NULL)
++			err = -ENXIO;
+ 	}
+ 
+-	ltq_mtd->mtd->dev.parent = &pdev->dev;
+-	mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);
+-
+-	cfi = ltq_mtd->map->fldrv_priv;
+-	cfi->addr_unlock1 ^= 1;
+-	cfi->addr_unlock2 ^= 1;
++	ltq_mtd->cmtd->dev.parent = &pdev->dev;
++	mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node);
+ 
+-	err = mtd_device_register(ltq_mtd->mtd, NULL, 0);
++	err = mtd_device_register(ltq_mtd->cmtd, NULL, 0);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "failed to add partitions\n");
+-		goto err_destroy;
++		goto err_out;
+ 	}
+ 
+ 	return 0;
+ 
+-err_destroy:
+-	map_destroy(ltq_mtd->mtd);
++err_out:
++	ltq_mtd_remove(pdev);
+ 	return err;
+ }
+ 
+-static int
+-ltq_mtd_remove(struct platform_device *pdev)
+-{
+-	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
+-
+-	if (ltq_mtd && ltq_mtd->mtd) {
+-		mtd_device_unregister(ltq_mtd->mtd);
+-		map_destroy(ltq_mtd->mtd);
+-	}
+-	return 0;
+-}
+-
+ static const struct of_device_id ltq_mtd_match[] = {
+ 	{ .compatible = "lantiq,nor" },
+ 	{},
diff --git a/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
new file mode 100644
index 0000000000..f057ba324e
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
@@ -0,0 +1,99 @@
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -14,6 +14,10 @@
+ 
+ static unsigned int *cp1_base;
+ 
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ 	if (!cp1_base)
+@@ -23,6 +27,33 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+ 
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++	if (!ad0_irq)
++		panic("no ad0 irq was set\n");
++
++	return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++	if (!ad1_irq)
++		panic("no ad1 irq was set\n");
++
++	return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++	if (!vc_irq[idx])
++		panic("no vc%d irq was set\n", idx);
++
++	return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE       (1 << 20)
+@@ -30,11 +61,33 @@ static int vmmc_probe(struct platform_de
+ 	int gpio_count;
+ 	dma_addr_t dma;
+ 	int error;
++	int i;
+ 
+ 	cp1_base =
+ 		(void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ 						    &dma, GFP_KERNEL));
+ 
++	ad0_irq = platform_get_irq(pdev, 4);
++	if (ad0_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++		return ad0_irq;
++	}
++
++	ad1_irq = platform_get_irq(pdev, 5);
++	if (ad1_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++		return ad1_irq;
++	}
++
++	for (i = 0; i < 4; i++) {
++	vc_irq[i] = platform_get_irq(pdev, i);
++		if (vc_irq[i] < 0) {
++			dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++				i, vc_irq[i]);
++			return vc_irq[i];
++		}
++	}
++
+ 	gpio_count = gpiod_count(&pdev->dev, NULL);
+ 	while (gpio_count > 0) {
+ 		gpio = devm_gpiod_get_index(&pdev->dev,
diff --git a/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
new file mode 100644
index 0000000000..f62d167078
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
@@ -0,0 +1,21 @@
+From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001
+From: Matti Laakso <malaakso@elisanet.fi>
+Date: Sat, 14 Feb 2015 20:48:00 +0000
+Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes
+
+Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -39,7 +39,7 @@
+ /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
+ 
+ // debugging, turns off buffer write mode if set to 1
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ /* Intel chips */
+ #define I82802AB	0x00ad
diff --git a/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch
new file mode 100644
index 0000000000..e46790b2c3
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch
@@ -0,0 +1,40 @@
+From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] xrx200: add gphy clk src device tree binding
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void)
+ 	}
+ }
+ 
++static void set_phy_clock_source(struct device_node *np_cgu)
++{
++	u32 phy_clk_src, ifcc;
++
++	if (!np_cgu)
++		return;
++
++	if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
++		return;
++
++	ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
++	ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
++}
++
+ /* bring up all register ranges that we need for basic system control */
+ void __init ltq_soc_init(void)
+ {
+@@ -609,4 +623,6 @@ void __init ltq_soc_init(void)
+ 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ 	}
+ 	usb_set_clock();
++
++	set_phy_clock_source(np_cgu);
+ }
diff --git a/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch b/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch
new file mode 100644
index 0000000000..c43d9d4b35
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch
@@ -0,0 +1,62 @@
+From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001
+From: Aleksander Jan Bajkowski <olek2@wp.pl>
+Date: Sat, 6 May 2023 14:32:00 +0200
+Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if
+ FORCE_WORD_WRITE is 1
+
+Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1.
+So the compile warning messages are output if FORCE_WORD_WRITE is 1. To
+resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1.
+
+This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f.
+
+Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -61,8 +61,10 @@
+ 
+ static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+ static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *);
++#endif
+ static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_intelext_sync (struct mtd_info *);
+ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+@@ -304,6 +306,7 @@ static void fixup_use_point(struct mtd_i
+ 	}
+ }
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -314,6 +317,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_writev = cfi_intelext_writev;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Some chips power-up with all sectors locked by default.
+@@ -1719,6 +1723,7 @@ static int cfi_intelext_write_words (str
+ }
+ 
+ 
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const struct kvec **pvec,
+ 				    unsigned long *pvec_seek, int len)
+@@ -1947,6 +1952,7 @@ static int cfi_intelext_write_buffers (s
+ 
+ 	return cfi_intelext_writev(mtd, &vec, 1, to, retlen);
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
+ 				      unsigned long adr, int len, void *thunk)
diff --git a/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch b/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch
new file mode 100644
index 0000000000..edf0626860
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch
@@ -0,0 +1,38 @@
+From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001
+From: Thomas Nixon <tom@tomn.co.uk>
+Date: Sun, 26 Mar 2023 11:08:49 +0100
+Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock
+
+The nand driver normally while waiting for the device to become ready;
+this is normally fine, but xway_nand holds the ebu_lock spinlock, and
+this can cause lockups if other threads which use ebu_lock are
+interleaved. Fix this by waiting instead of polling.
+
+This mainly showed up as crashes in ath9k_pci_owl_loader (see
+https://github.com/openwrt/openwrt/issues/9829 ), but turning on
+spinlock debugging shows this happening in other places too.
+
+This doesn't seem to measurably impact boot time.
+
+Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
+---
+ drivers/mtd/nand/raw/xway_nand.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+ {
+-	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
++	/*
++	 * wait until ready, as otherwise the driver will yield in nand_wait or
++	 * nand_wait_ready, which is a bad idea when we're holding ebu_lock
++	 */
++	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++		cpu_relax();
++	return 1;
+ }
+ 
+ static unsigned char xway_read_byte(struct nand_chip *chip)
diff --git a/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch
new file mode 100644
index 0000000000..19c027b9f8
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0701-NET-lantiq-etop-of-mido.patch
@@ -0,0 +1,47 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: Johann Neuhauser <johann@it-neuhauser.de>
+Date: Thu, 17 May 2018 19:12:35 +0200
+Subject: [PATCH] net: lantiq_etop: of mdio
+
+Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
+---
+ drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -31,6 +31,7 @@
+ #include <linux/of_net.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/of_mdio.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -558,7 +559,8 @@ static int
+ ltq_etop_mdio_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int err;
++	struct device_node *mdio_np = NULL;
++	int err, ret;
+ 
+ 	priv->mii_bus = mdiobus_alloc();
+ 	if (!priv->mii_bus) {
+@@ -578,7 +580,15 @@ ltq_etop_mdio_init(struct net_device *de
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+-	if (mdiobus_register(priv->mii_bus)) {
++
++	mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
++
++	if (mdio_np)
++		ret = of_mdiobus_register(priv->mii_bus, mdio_np);
++	else
++		ret = mdiobus_register(priv->mii_bus);
++
++	if (ret) {
+ 		err = -ENXIO;
+ 		goto err_out_free_mdiobus;
+ 	}
diff --git a/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch b/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
new file mode 100644
index 0000000000..c337c564b6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
@@ -0,0 +1,32 @@
+From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:52:25 +0200
+Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing
+ phy-mode and fixed-link
+
+The CPU port has to specify a phy-mode and either a phy or a fixed-link.
+Since GSWIP is connected using a SoC internal protocol there's no PHY
+involved. Add phy-mode = "internal" and a fixed-link to describe the
+communication between the PMAC (Ethernet controller) and GSWIP switch.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+@@ -96,7 +96,13 @@ switch@e108000 {
+ 
+ 		port@6 {
+ 			reg = <0x6>;
++			phy-mode = "internal";
+ 			ethernet = <&eth0>;
++
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch b/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
new file mode 100644
index 0000000000..4800ee1dd2
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
@@ -0,0 +1,33 @@
+From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:59:35 +0200
+Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode =
+ "internal" on the CPU port
+
+Add the CPU port to gswip_xrx200_phylink_get_caps() and
+gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus,
+so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1509,6 +1509,7 @@ static void gswip_xrx200_phylink_get_cap
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
+ 		break;
+@@ -1540,6 +1541,7 @@ static void gswip_xrx300_phylink_get_cap
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
+ 		break;
diff --git a/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch b/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
new file mode 100644
index 0000000000..f30e7ab00c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
@@ -0,0 +1,145 @@
+From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 31 Jul 2022 22:54:52 +0200
+Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where
+ appropriate
+
+dev_err_probe() can be used to simplify the existing code. Also it means
+we get rid of the following warning which is seen whenever the PMAC
+(Ethernet controller which connects to GSWIP's CPU port) has not been
+probed yet:
+  gswip 1e108000.switch: dsa switch register failed: -517
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------
+ 1 file changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1919,11 +1919,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 	msleep(200);
+ 
+ 	ret = request_firmware(&fw, gphy_fw->fw_name, dev);
+-	if (ret) {
+-		dev_err(dev, "failed to load firmware: %s, error: %i\n",
+-			gphy_fw->fw_name, ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
++				     gphy_fw->fw_name);
+ 
+ 	/* GPHY cores need the firmware code in a persistent and contiguous
+ 	 * memory area with a 16 kB boundary aligned start address.
+@@ -1936,9 +1934,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 		dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ 		memcpy(fw_addr, fw->data, fw->size);
+ 	} else {
+-		dev_err(dev, "failed to alloc firmware memory\n");
+ 		release_firmware(fw);
+-		return -ENOMEM;
++		return dev_err_probe(dev, -ENOMEM,
++				     "failed to alloc firmware memory\n");
+ 	}
+ 
+ 	release_firmware(fw);
+@@ -1965,8 +1963,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 
+ 	gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
+ 	if (IS_ERR(gphy_fw->clk_gate)) {
+-		dev_err(dev, "Failed to lookup gate clock\n");
+-		return PTR_ERR(gphy_fw->clk_gate);
++		return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
++				     "Failed to lookup gate clock\n");
+ 	}
+ 
+ 	ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
+@@ -1986,8 +1984,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 		gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
+ 		break;
+ 	default:
+-		dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+-		return -EINVAL;
++		return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
++				     gphy_mode);
+ 	}
+ 
+ 	gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
+@@ -2038,8 +2036,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 			priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ 			break;
+ 		default:
+-			dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-			return -ENOENT;
++			return dev_err_probe(dev, -ENOENT,
++					     "unknown GSWIP version: 0x%x",
++					     version);
+ 		}
+ 	}
+ 
+@@ -2047,10 +2046,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 	if (match && match->data)
+ 		priv->gphy_fw_name_cfg = match->data;
+ 
+-	if (!priv->gphy_fw_name_cfg) {
+-		dev_err(dev, "GPHY compatible type not supported");
+-		return -ENOENT;
+-	}
++	if (!priv->gphy_fw_name_cfg)
++		return dev_err_probe(dev, -ENOENT,
++				     "GPHY compatible type not supported");
+ 
+ 	priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
+ 	if (!priv->num_gphy_fw)
+@@ -2150,8 +2148,8 @@ static int gswip_probe(struct platform_d
+ 			return -EINVAL;
+ 		break;
+ 	default:
+-		dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-		return -ENOENT;
++		return dev_err_probe(dev, -ENOENT,
++				     "unknown GSWIP version: 0x%x", version);
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2159,10 +2157,9 @@ static int gswip_probe(struct platform_d
+ 	if (gphy_fw_np) {
+ 		err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
+ 		of_node_put(gphy_fw_np);
+-		if (err) {
+-			dev_err(dev, "gphy fw probe failed\n");
+-			return err;
+-		}
++		if (err)
++			return dev_err_probe(dev, err,
++					     "gphy fw probe failed\n");
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2170,20 +2167,20 @@ static int gswip_probe(struct platform_d
+ 	if (mdio_np) {
+ 		err = gswip_mdio(priv, mdio_np);
+ 		if (err) {
+-			dev_err(dev, "mdio probe failed\n");
++			dev_err_probe(dev, err, "mdio probe failed\n");
+ 			goto put_mdio_node;
+ 		}
+ 	}
+ 
+ 	err = dsa_register_switch(priv->ds);
+ 	if (err) {
+-		dev_err(dev, "dsa switch register failed: %i\n", err);
++		dev_err_probe(dev, err, "dsa switch registration failed\n");
+ 		goto mdio_bus;
+ 	}
+ 	if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
+-		dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
+-			priv->hw_info->cpu_port);
+-		err = -EINVAL;
++		err = dev_err_probe(dev, -EINVAL,
++				    "wrong CPU port defined, HW only supports port: %i",
++				    priv->hw_info->cpu_port);
+ 		goto disable_switch;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch b/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
new file mode 100644
index 0000000000..de8416380a
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
@@ -0,0 +1,25 @@
+From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 28 Jul 2022 22:37:11 +0200
+Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call
+ gswip_port_enable()
+
+We don't need to manually call gswip_port_enable() from within
+gswip_setup() for the CPU port. DSA does this automatically for us.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -891,8 +891,6 @@ static int gswip_setup(struct dsa_switch
+ 
+ 	ds->mtu_enforcement_ingress = true;
+ 
+-	gswip_port_enable(ds, cpu_port, NULL);
+-
+ 	ds->configure_vlan_while_not_filtering = false;
+ 
+ 	return 0;
diff --git a/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch b/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
new file mode 100644
index 0000000000..a653c85841
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
@@ -0,0 +1,70 @@
+From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Fri, 10 May 2024 13:52:10 +0200
+Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port
+
+Before commit 74be4babe72f ("net: dsa: do not enable or disable non user
+ports"), gswip_port_enable/disable() were also executed for the cpu port
+in gswip_setup() which disabled the cpu port during initialization.
+
+Let's restore this by removing the dsa_is_user_port checks. Also, let's
+clean up the gswip_port_enable() function so that we only have to check
+for the cpu port once.
+
+Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports")
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ drivers/net/dsa/lantiq_gswip.c | 24 ++++++++----------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -688,13 +688,18 @@ static int gswip_port_enable(struct dsa_
+ 	struct gswip_priv *priv = ds->priv;
+ 	int err;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return 0;
+-
+ 	if (!dsa_is_cpu_port(ds, port)) {
++		u32 mdio_phy = 0;
++
+ 		err = gswip_add_single_port_br(priv, port, true);
+ 		if (err)
+ 			return err;
++
++		if (phydev)
++			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
++
++		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
++				GSWIP_MDIO_PHYp(port));
+ 	}
+ 
+ 	/* RMON Counter Enable for port */
+@@ -707,16 +712,6 @@ static int gswip_port_enable(struct dsa_
+ 	gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
+ 			  GSWIP_SDMA_PCTRLp(port));
+ 
+-	if (!dsa_is_cpu_port(ds, port)) {
+-		u32 mdio_phy = 0;
+-
+-		if (phydev)
+-			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
+-
+-		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
+-				GSWIP_MDIO_PHYp(port));
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -724,9 +719,6 @@ static void gswip_port_disable(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return;
+-
+ 	gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
+ 			  GSWIP_FDMA_PCTRLp(port));
+ 	gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
diff --git a/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch b/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
new file mode 100644
index 0000000000..fd19982264
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
@@ -0,0 +1,30 @@
+From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 18 May 2022 23:53:09 +0200
+Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in
+ gswip_port_change_mtu()
+
+Make the check for the CPU port in gswip_port_change_mtu() consistent
+with other areas of the driver by using dsa_is_cpu_port().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1457,12 +1457,11 @@ static int gswip_port_max_mtu(struct dsa
+ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ 	struct gswip_priv *priv = ds->priv;
+-	int cpu_port = priv->hw_info->cpu_port;
+ 
+ 	/* CPU port always has maximum mtu of user ports, so use it to set
+ 	 * switch frame size, including 8 byte special header.
+ 	 */
+-	if (port == cpu_port) {
++	if (dsa_is_cpu_port(ds, port)) {
+ 		new_mtu += 8;
+ 		gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
+ 			       GSWIP_MAC_FLEN);
diff --git a/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch b/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
new file mode 100644
index 0000000000..74e52d1d18
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
@@ -0,0 +1,24 @@
+From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 17 May 2022 22:39:58 +0200
+Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN
+
+The addr variable in gswip_port_fdb_dump() stores a mac address. Use
+ETH_ALEN to make this consistent across other drivers.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1406,7 +1406,7 @@ static int gswip_port_fdb_dump(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 	struct gswip_pce_table_entry mac_bridge = {0,};
+-	unsigned char addr[6];
++	unsigned char addr[ETH_ALEN];
+ 	int i;
+ 	int err;
+ 
diff --git a/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch b/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
new file mode 100644
index 0000000000..0ea90db483
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
@@ -0,0 +1,47 @@
+From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 21:23:49 +0200
+Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for
+ the mac bridge table
+
+Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout
+the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT()
+macro. This makes the driver code easier to understand.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -236,7 +236,8 @@
+ #define GSWIP_TABLE_ACTIVE_VLAN		0x01
+ #define GSWIP_TABLE_VLAN_MAPPING	0x02
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+-#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	0x01	/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1300,7 +1301,8 @@ static void gswip_port_fast_age(struct d
+ 		if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
+ 			continue;
+ 
+-		if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
++		if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++				      mac_bridge.val[0]))
+ 			continue;
+ 
+ 		mac_bridge.valid = false;
+@@ -1438,7 +1440,8 @@ static int gswip_port_fdb_dump(struct ds
+ 					return err;
+ 			}
+ 		} else {
+-			if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
++			if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++					      mac_bridge.val[0])) {
+ 				err = cb(addr, 0, false, data);
+ 				if (err)
+ 					return err;
diff --git a/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch b/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
new file mode 100644
index 0000000000..1347a98c5c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
@@ -0,0 +1,26 @@
+From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:24:24 +0200
+Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid
+ gswip_add_single_port_br on the CPU port
+
+Calling gswip_add_single_port_br() with the CPU port would be a bug
+because then only the CPU port could talk to itself. Add the CPU port to
+the validation at the beginning of gswip_add_single_port_br().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -650,7 +650,7 @@ static int gswip_add_single_port_br(stru
+ 	unsigned int max_ports = priv->hw_info->max_ports;
+ 	int err;
+ 
+-	if (port >= max_ports) {
++	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+ 		dev_err(priv->dev, "single port for %i supported\n", port);
+ 		return -EIO;
+ 	}
diff --git a/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch b/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
new file mode 100644
index 0000000000..732588308e
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
@@ -0,0 +1,26 @@
+From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:26:20 +0200
+Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in
+ gswip_add_single_port_br()
+
+The error message is printed when the port cannot be used. Update the
+error message to reflect that.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -651,7 +651,8 @@ static int gswip_add_single_port_br(stru
+ 	int err;
+ 
+ 	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+-		dev_err(priv->dev, "single port for %i supported\n", port);
++		dev_err(priv->dev, "single port for %i is not supported\n",
++			port);
+ 		return -EIO;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch b/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
new file mode 100644
index 0000000000..679dd53c47
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
@@ -0,0 +1,36 @@
+From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:06:40 +0200
+Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in
+ gswip_port_vlan_filtering()
+
+Update the comments in gswip_port_vlan_filtering() so it's clear that
+there are two separate cases, one for "tag based VLAN" and another one
+for "port based VLAN".
+
+Suggested-by: Martin Schiller <ms@dev.tdt.de>
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -779,7 +779,7 @@ static int gswip_port_vlan_filtering(str
+ 	}
+ 
+ 	if (vlan_filtering) {
+-		/* Use port based VLAN tag */
++		/* Use tag based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_VSR,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+@@ -788,7 +788,7 @@ static int gswip_port_vlan_filtering(str
+ 		gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
+ 				  GSWIP_PCE_PCTRL_0p(port));
+ 	} else {
+-		/* Use port based VLAN tag */
++		/* Use port based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+ 				  GSWIP_PCE_VCTRL_VEMR,
diff --git a/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch b/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
new file mode 100644
index 0000000000..3d284c2ea6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
@@ -0,0 +1,33 @@
+From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:19:05 +0200
+Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a
+ GSWIP_TABLE_MAC_BRIDGE_FID macro
+
+Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a
+macro so this becomes obvious when reading the driver code.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -238,6 +238,7 @@
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+ #define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
+ #define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
++#define  GSWIP_TABLE_MAC_BRIDGE_FID	GENMASK(5, 0)	/* Filtering identifier */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1378,7 +1379,7 @@ static int gswip_port_fdb(struct dsa_swi
+ 	mac_bridge.key[0] = addr[5] | (addr[4] << 8);
+ 	mac_bridge.key[1] = addr[3] | (addr[2] << 8);
+ 	mac_bridge.key[2] = addr[1] | (addr[0] << 8);
+-	mac_bridge.key[3] = fid;
++	mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid);
+ 	mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
+ 	mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
+ 	mac_bridge.valid = add;
diff --git a/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch b/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
new file mode 100644
index 0000000000..5c756c5a19
--- /dev/null
+++ b/target/linux/lantiq/patches-6.1/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
@@ -0,0 +1,26 @@
+From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 16:31:57 +0200
+Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in
+ gswip_port_fdb()
+
+Print the port which is not found to be part of a bridge so it's easier
+to investigate the underlying issue.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1370,7 +1370,8 @@ static int gswip_port_fdb(struct dsa_swi
+ 	}
+ 
+ 	if (fid == -1) {
+-		dev_err(priv->dev, "Port not part of a bridge\n");
++		dev_err(priv->dev,
++			"Port %d is not known to be part of bridge\n", port);
+ 		return -EINVAL;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.6/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-6.6/0001-MIPS-lantiq-add-pcie-driver.patch
new file mode 100644
index 0000000000..3e23c0f23d
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0001-MIPS-lantiq-add-pcie-driver.patch
@@ -0,0 +1,5550 @@
+From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:12:28 +0200
+Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/Kconfig           |   10 +
+ arch/mips/lantiq/xway/sysctrl.c    |    2 +
+ arch/mips/pci/Makefile             |    2 +
+ arch/mips/pci/fixup-lantiq-pcie.c  |   82 +++
+ arch/mips/pci/fixup-lantiq.c       |    5 +-
+ arch/mips/pci/ifxmips_pci_common.h |   57 ++
+ arch/mips/pci/ifxmips_pcie.c       | 1099 ++++++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie.h       |  135 ++++
+ arch/mips/pci/ifxmips_pcie_ar10.h  |  290 ++++++++
+ arch/mips/pci/ifxmips_pcie_msi.c   |  392 +++++++++++
+ arch/mips/pci/ifxmips_pcie_phy.c   |  478 +++++++++++++
+ arch/mips/pci/ifxmips_pcie_pm.c    |  176 +++++
+ arch/mips/pci/ifxmips_pcie_pm.h    |   36 +
+ arch/mips/pci/ifxmips_pcie_reg.h   | 1001 +++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie_vr9.h   |  271 ++++++++
+ arch/mips/pci/pci.c                |   25 +
+ arch/mips/pci/pcie-lantiq.h        | 1305 ++++++++++++++++++++++++++++++++++++
+ drivers/pci/pcie/aer/Kconfig       |    2 +-
+ include/linux/pci.h                |    2 +
+ include/linux/pci_ids.h            |    6 +
+ 20 files changed, 5374 insertions(+), 2 deletions(-)
+ create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pci_common.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h
+ create mode 100644 arch/mips/pci/pcie-lantiq.h
+
+--- a/arch/mips/lantiq/Kconfig
++++ b/arch/mips/lantiq/Kconfig
+@@ -20,6 +20,7 @@ config SOC_XWAY
+ 	bool "XWAY"
+ 	select SOC_TYPE_XWAY
+ 	select HAVE_PCI
++	select ARCH_SUPPORTS_MSI
+ 	select MFD_SYSCON
+ 	select MFD_CORE
+ 
+@@ -52,4 +53,13 @@ config PCI_LANTIQ
+ 	bool "PCI Support"
+ 	depends on SOC_XWAY && PCI
+ 
++config PCIE_LANTIQ
++	bool "PCIE Support"
++	depends on SOC_XWAY && PCI
++
++config PCIE_LANTIQ_MSI
++	bool
++	depends on PCIE_LANTIQ && PCI_MSI
++	default y
++
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,8 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+ obj-$(CONFIG_TOSHIBA_RBTX4927)	+= fixup-rbtx4927.o
+--- /dev/null
++++ b/arch/mips/pci/fixup-lantiq-pcie.c
+@@ -0,0 +1,74 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_fixup_pcie.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe 
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_fixup_pcie.c
++ \ingroup IFX_PCIE  
++ \brief PCIe Fixup functions source file
++*/
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/pci_ids.h>
++
++#include <lantiq_soc.h>
++
++#include "pcie-lantiq.h"
++
++static void
++ifx_pcie_fixup_resource(struct pci_dev *dev)
++{
++    u32 reg;
++
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++    printk("%s: fixup host controller %s (%04x:%04x)\n", 
++        __func__, pci_name(dev), dev->vendor, dev->device); 
++
++   /* Setup COMMAND register */
++    reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | 
++          PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR;
++    pci_write_config_word(dev, PCI_COMMAND, reg);
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource);
++
++static void
++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev)
++{
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++    if (dev->devfn == PCI_DEVFN(0, 0) &&
++        (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
++
++        dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff);
++
++        printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__);
++    }
++    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++    mdelay(10);
++}
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE,
++     ifx_pcie_rc_class_early_fixup);
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE,
++     ifx_pcie_rc_class_early_fixup);
+--- a/arch/mips/pci/fixup-lantiq.c
++++ b/arch/mips/pci/fixup-lantiq.c
+@@ -6,12 +6,19 @@
+ 
+ #include <linux/of_irq.h>
+ #include <linux/of_pci.h>
++#include <linux/pci.h>
++#include "ifxmips_pci_common.h"
+ 
+ int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;
+ int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
+ 
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++	if (pci_find_capability(dev, PCI_CAP_ID_EXP))
++		ifx_pcie_bios_plat_dev_init(dev);
++#endif
++
+ 	if (ltq_pci_plat_arch_init)
+ 		return ltq_pci_plat_arch_init(dev);
+ 
+@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev
+ 
+ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++	if (pci_find_capability((struct pci_dev *)dev, PCI_CAP_ID_EXP))
++		return ifx_pcie_bios_map_irq(dev, slot, pin);
++#endif
++
+ 	return of_irq_parse_and_map_pci(dev, slot, pin);
+ }
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pci_common.h
+@@ -0,0 +1,53 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pci_common.h
++** PROJECT      : IFX UEIP
++** MODULES      : PCI subsystem
++**
++** DATE         : 30 June 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    30 June,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++
++#ifndef IFXMIPS_PCI_COMMON_H
++#define IFXMIPS_PCI_COMMON_H
++#include <linux/version.h>
++/*!
++ \defgroup IFX_PCI_COM  IFX PCI/PCIe common parts for OS integration  
++ \brief  PCI/PCIe common parts
++*/
++
++/*!
++ \defgroup IFX_PCI_COM_OS OS APIs
++ \ingroup IFX_PCI_COM
++ \brief PCI/PCIe bus driver OS interface functions
++*/
++/*!
++  \file ifxmips_pci_common.h
++  \ingroup IFX_PCI_COM
++  \brief PCI/PCIe bus driver common OS header file
++*/
++#define IFX_PCI_CONST const
++#ifdef CONFIG_IFX_PCI
++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev);
++#endif /* COFNIG_IFX_PCI */
++
++#ifdef CONFIG_PCIE_LANTIQ
++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev);
++#endif
++
++#endif /* IFXMIPS_PCI_COMMON_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -0,0 +1,1091 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2009 Lei Chuanhua <chuanhua.lei@infineon.com>
++ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <asm/paccess.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/module.h>
++
++#include "ifxmips_pcie.h"
++#include "ifxmips_pcie_reg.h"
++
++/* Enable 32bit io due to its mem mapped io nature */
++#define IFX_PCIE_ERROR_INT
++#define IFX_PCIE_IO_32BIT
++
++#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
++#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
++#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
++#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
++#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
++#define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
++#define SM(_v, _f)  (((_v) << _f##_S) & (_f))
++#define IFX_REG_SET_BIT(_f, _r) \
++	IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r))
++
++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10
++
++static DEFINE_SPINLOCK(ifx_pcie_lock);
++
++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++
++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
++    {
++        .ir_irq = {
++            .irq  = IFX_PCIE_IR,
++            .name = "ifx_pcie_rc0",
++        },
++
++        .legacy_irq = {
++            {
++                .irq_bit = PCIE_IRN_INTA,
++                .irq     = IFX_PCIE_INTA,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTB,
++                .irq     = IFX_PCIE_INTB,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTC,
++                .irq     = IFX_PCIE_INTC,
++            },
++            {
++                .irq_bit = PCIE_IRN_INTD,
++                .irq     = IFX_PCIE_INTD,
++            },
++        },
++    },
++
++};
++
++void ifx_pcie_debug(const char *fmt, ...)
++{
++	static char buf[256] = {0};      /* XXX */
++	va_list ap;
++
++	va_start(ap, fmt);
++	vsnprintf(buf, sizeof(buf), fmt, ap);
++	va_end(ap);
++
++	printk("%s", buf);
++}
++
++
++static inline int pcie_ltssm_enable(int pcie_port)
++{
++	int i;
++
++	/* Enable LTSSM */
++	IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port));
++
++	/* Wait for the link to come up */
++	for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) {
++		if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING))
++			return 0;
++		udelay(10);
++	}
++
++	printk("%s link timeout!!!!!\n", __func__);
++	return -1;
++}
++
++static inline void pcie_status_register_clear(int pcie_port)
++{
++	IFX_REG_W32(0, PCIE_RC_DR(pcie_port));
++	IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_RSTS(pcie_port));
++	IFX_REG_W32(0, PCIE_UES_R(pcie_port));
++	IFX_REG_W32(0, PCIE_UEMR(pcie_port));
++	IFX_REG_W32(0, PCIE_UESR(pcie_port));
++	IFX_REG_W32(0, PCIE_CESR(pcie_port));
++	IFX_REG_W32(0, PCIE_CEMR(pcie_port));
++	IFX_REG_W32(0, PCIE_RESR(pcie_port));
++	IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port));
++	IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port));
++	IFX_REG_W32(0, PCIE_TPFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_TNPFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_TCFCS(pcie_port));
++	IFX_REG_W32(0, PCIE_QSR(pcie_port));
++	IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port));
++}
++
++static inline int ifx_pcie_link_up(int pcie_port)
++{
++    return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0;
++}
++
++
++static inline void pcie_mem_io_setup(int pcie_port)
++{
++    u32 reg;
++    /*
++     * BAR[0:1] readonly register 
++     * RC contains only minimal BARs for packets mapped to this device 
++     * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that
++     * reside on the downstream side fo the bridge.
++     */
++    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR)
++        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR);
++
++    IFX_REG_W32(reg, PCIE_MBML(pcie_port));
++
++
++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT
++    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR)
++        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT)
++        | PCIE_PMBL_64BIT_ADDR;
++    IFX_REG_W32(reg, PCIE_PMBL(pcie_port));
++
++    /* Must configure upper 32bit */
++    IFX_REG_W32(0, PCIE_PMBU32(pcie_port));
++    IFX_REG_W32(0, PCIE_PMLU32(pcie_port));
++#else
++    /* PCIe_PBML, same as MBML */
++    IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port));
++#endif 
++
++    /* IO Address Range */
++    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR)
++        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR);
++#ifdef IFX_PCIE_IO_32BIT    
++    reg |= PCIE_IOBLSECS_32BIT_IO_ADDR;
++#endif /* IFX_PCIE_IO_32BIT */
++    IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port));
++
++#ifdef IFX_PCIE_IO_32BIT
++    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT)
++        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE);
++    IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port));
++
++#endif /* IFX_PCIE_IO_32BIT */
++}
++
++static inline void
++pcie_device_setup(int pcie_port)
++{
++    u32 reg;
++
++    /* Device capability register, set up Maximum payload size */
++    reg = IFX_REG_R32(PCIE_DCAP(pcie_port));
++    reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT;
++    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE);
++
++    /* Only available for EP */
++    reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY);
++    IFX_REG_W32(reg, PCIE_DCAP(pcie_port));
++
++    /* Device control and status register */
++    /* Set Maximum Read Request size for the device as a Requestor */
++    reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port));
++
++    /* 
++     * Request size can be larger than the MPS used, but the completions returned 
++     * for the read will be bounded by the MPS size.
++     * In our system, Max request size depends on AHB burst size. It is 64 bytes.
++     * but we set it as 128 as minimum one.
++     */
++    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE)
++            | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE);
++
++    /* Enable relaxed ordering, no snoop, and all kinds of errors */
++    reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN;
++
++    IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port));
++}
++
++static inline void
++pcie_link_setup(int pcie_port)
++{
++    u32 reg;
++
++    /*
++     * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM 
++     * L0s is reported during link training via TS1 order set by N_FTS
++     */
++    reg = IFX_REG_R32(PCIE_LCAP(pcie_port));
++    reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY;
++    reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY);
++    IFX_REG_W32(reg, PCIE_LCAP(pcie_port));
++
++    /* Link control and status register */
++    reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++    /* Link Enable, ASPM enabled  */
++    reg &= ~PCIE_LCTLSTS_LINK_DISABLE;
++
++#ifdef CONFIG_PCIEASPM
++    /*  
++     * We use the same physical reference clock that the platform provides on the connector 
++     * It paved the way for ASPM to calculate the new exit Latency
++     */
++    reg |= PCIE_LCTLSTS_SLOT_CLK_CFG;
++    reg |= PCIE_LCTLSTS_COM_CLK_CFG;
++    /*
++     * We should disable ASPM by default except that we have dedicated power management support
++     * Enable ASPM will cause the system hangup/instability, performance degration
++     */
++    reg |= PCIE_LCTLSTS_ASPM_ENABLE;
++#else
++    reg &= ~PCIE_LCTLSTS_ASPM_ENABLE;
++#endif /* CONFIG_PCIEASPM */
++
++    /* 
++     * The maximum size of any completion with data packet is bounded by the MPS setting 
++     * in  device control register 
++     */
++
++    /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */
++    reg &= ~ PCIE_LCTLSTS_RCB128;
++
++    IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port));
++}
++
++static inline void pcie_error_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* 
++	* Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone 
++	* Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE 
++	*/
++	reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port));
++	reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE;
++
++	IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port));
++
++	/* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */
++	reg = IFX_REG_R32(PCIE_UEMR(pcie_port));
++	reg &= ~PCIE_ALL_UNCORRECTABLE_ERR;
++	IFX_REG_W32(reg, PCIE_UEMR(pcie_port));
++
++	/* Uncorrectable Error Severity Register, ALL errors are FATAL */
++	IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port));
++
++	/* Correctable Error Mask Register, unmask <enable> all bits */
++	reg = IFX_REG_R32(PCIE_CEMR(pcie_port));
++	reg &= ~PCIE_CORRECTABLE_ERR;
++	IFX_REG_W32(reg, PCIE_CEMR(pcie_port));
++
++	/* Advanced Error Capabilities and Control Registr */
++	reg = IFX_REG_R32(PCIE_AECCR(pcie_port));
++	reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN;
++	IFX_REG_W32(reg, PCIE_AECCR(pcie_port));
++
++	/* Root Error Command Register, Report all types of errors */
++	reg = IFX_REG_R32(PCIE_RECR(pcie_port));
++	reg |= PCIE_RECR_ERR_REPORT_EN;
++	IFX_REG_W32(reg, PCIE_RECR(pcie_port));
++
++	/* Clear the Root status register */
++	reg = IFX_REG_R32(PCIE_RESR(pcie_port));
++	IFX_REG_W32(reg, PCIE_RESR(pcie_port));
++}
++
++static inline void pcie_port_logic_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* FTS number, default 12, increase to 63, may increase time from/to L0s to L0  */
++	reg = IFX_REG_R32(PCIE_AFR(pcie_port));
++	reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM);
++	reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM)
++		| SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM);
++	/* L0s and L1 entry latency */
++	reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY);
++	reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY)
++		| SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY);
++	IFX_REG_W32(reg, PCIE_AFR(pcie_port));
++
++
++	/* Port Link Control Register */
++	reg = IFX_REG_R32(PCIE_PLCR(pcie_port));
++	reg |= PCIE_PLCR_DLL_LINK_EN;  /* Enable the DLL link */
++	IFX_REG_W32(reg, PCIE_PLCR(pcie_port));
++
++	/* Lane Skew Register */
++	reg = IFX_REG_R32(PCIE_LSR(pcie_port));
++	/* Enable ACK/NACK and FC */
++	reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE);
++	IFX_REG_W32(reg, PCIE_LSR(pcie_port));
++
++	/* Symbol Timer Register and Filter Mask Register 1 */
++	reg = IFX_REG_R32(PCIE_STRFMR(pcie_port));
++
++	/* Default SKP interval is very accurate already, 5us */
++	/* Enable IO/CFG transaction */
++	reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE;
++	/* Disable FC WDT */
++	reg &= ~PCIE_STRFMR_FC_WDT_DISABLE;
++	IFX_REG_W32(reg, PCIE_STRFMR(pcie_port));
++
++	/* Filter Masker Register 2 */
++	reg = IFX_REG_R32(PCIE_FMR2(pcie_port));
++	reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1;
++	IFX_REG_W32(reg, PCIE_FMR2(pcie_port));
++
++	/* VC0 Completion Receive Queue Control Register */
++	reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port));
++	reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE;
++	reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE);
++	IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port));
++}
++
++static inline void pcie_rc_cfg_reg_setup(int pcie_port)
++{
++	u32 reg;
++
++	/* Disable LTSSM */
++	IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */
++
++	pcie_mem_io_setup(pcie_port);
++
++	/* XXX, MSI stuff should only apply to EP */
++	/* MSI Capability: Only enable 32-bit addresses */
++	reg = IFX_REG_R32(PCIE_MCAPR(pcie_port));
++	reg &= ~PCIE_MCAPR_ADDR64_CAP;
++
++	reg |= PCIE_MCAPR_MSI_ENABLE;
++
++	/* Disable multiple message */
++	reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE);
++	IFX_REG_W32(reg, PCIE_MCAPR(pcie_port));
++
++
++	/* Enable PME, Soft reset enabled */
++	reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port));
++	reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST;
++	IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port));
++
++	/* setup the bus */
++	reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM);
++	IFX_REG_W32(reg, PCIE_BNR(pcie_port));
++
++
++	pcie_device_setup(pcie_port);
++	pcie_link_setup(pcie_port);
++	pcie_error_setup(pcie_port);
++
++	/* Root control and capabilities register */
++	reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port));
++	reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN;
++	IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port));
++
++	/* Port VC Capability Register 2 */
++	reg = IFX_REG_R32(PCIE_PVC2(pcie_port));
++	reg &= ~PCIE_PVC2_VC_ARB_WRR;
++	reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR;
++	IFX_REG_W32(reg, PCIE_PVC2(pcie_port));
++
++	/* VC0 Resource Capability Register */
++	reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port));
++	reg &= ~PCIE_VC0_RC_REJECT_SNOOP;
++	IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port));
++
++	pcie_port_logic_setup(pcie_port);
++}
++
++static int ifx_pcie_wait_phy_link_up(int pcie_port)
++{
++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT  1000 /* XXX, tunable */
++    int i;
++
++    /* Wait for PHY link is up */
++    for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) {
++        if (ifx_pcie_link_up(pcie_port)) {
++            break;
++        }
++        udelay(100);
++    }
++    if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) {
++        printk(KERN_ERR "%s timeout\n", __func__);
++        return -1;
++    }
++
++    /* Check data link up or not */
++    if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) {
++        printk(KERN_ERR "%s DLL link is still down\n", __func__);
++        return -1;
++    }
++
++    /* Check Data link active or not */
++    if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) {
++        printk(KERN_ERR "%s DLL is not active\n", __func__);
++        return -1;
++    }
++    return 0;
++}
++
++static inline int pcie_app_loigc_setup(int pcie_port)
++{
++	/* supress ahb bus errrors */
++	IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port));
++
++	/* Pull PCIe EP out of reset */
++	pcie_device_rst_deassert(pcie_port);
++
++	/* Start LTSSM training between RC and EP */
++	pcie_ltssm_enable(pcie_port);
++
++	/* Check PHY status after enabling LTSSM */
++	if (ifx_pcie_wait_phy_link_up(pcie_port) != 0)
++		return -1;
++
++	return 0;
++}
++
++/*
++ * The numbers below are directly from the PCIe spec table 3-4/5. 
++ */
++static inline void pcie_replay_time_update(int pcie_port)
++{
++	u32 reg;
++	int nlw;
++	int rtl;
++
++	reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++	nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH);
++	switch (nlw) {
++	case PCIE_MAX_LENGTH_WIDTH_X1:
++		rtl = 1677;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X2:
++		rtl = 867;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X4:
++		rtl = 462;
++		break;
++	case PCIE_MAX_LENGTH_WIDTH_X8:
++		rtl = 258;
++		break;
++	default:
++		rtl = 1677;
++		break;
++	}
++	reg = IFX_REG_R32(PCIE_ALTRT(pcie_port));
++	reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT;
++	reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT);
++	IFX_REG_W32(reg, PCIE_ALTRT(pcie_port));
++}
++
++/*
++ * Table 359 Enhanced Configuration Address Mapping1)
++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1
++ * Memory Address PCI Express Configuration Space
++ * A[(20+n-1):20] Bus Number 1 < n < 8
++ * A[19:15] Device Number
++ * A[14:12] Function Number
++ * A[11:8] Extended Register Number
++ * A[7:2] Register Number
++ * A[1:0] Along with size of the access, used to generate Byte Enables
++ * For VR9, only the address bits [22:0] are mapped to the configuration space:
++ * . Address bits [22:20] select the target bus (1-of-8)1)
++ * . Address bits [19:15] select the target device (1-of-32) on the bus
++ * . Address bits [14:12] select the target function (1-of-8) within the device.
++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space
++ * . Address bits [1:0] define the start byte location within the selected dword.
++ */
++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where)
++{
++	u32 addr;
++	u8  bus;
++
++	if (!bus_num) {
++		/* type 0 */
++		addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3);
++	} else {
++		bus = bus_num;
++		/* type 1, only support 8 buses  */
++		addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) |
++			((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3);
++	}
++	return addr;
++}
++
++static int pcie_valid_config(int pcie_port, int bus, int dev)
++{
++	/* RC itself */
++	if ((bus == 0) && (dev == 0)) {
++		return 1;
++	}
++
++	/* No physical link */
++	if (!ifx_pcie_link_up(pcie_port)) {
++		return 0;
++	}
++
++	/* Bus zero only has RC itself
++	* XXX, check if EP will be integrated 
++	*/
++	if ((bus == 0) && (dev != 0)) {
++		return 0;
++	}
++
++	/* Maximum 8 buses supported for VRX */
++	if (bus > 9) {
++		return 0;
++	}
++
++	/* 
++	 * PCIe is PtP link, one bus only supports only one device 
++	 * except bus zero and PCIe switch which is virtual bus device
++	 * The following two conditions really depends on the system design
++	 * and attached the device.
++	 * XXX, how about more new switch
++	*/
++	if ((bus == 1) && (dev != 0)) {
++		return 0;
++	}
++
++	if ((bus >= 3) && (dev != 0)) {
++		return 0;
++	}
++	return 1;
++}
++
++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg)
++{
++    return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++    IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg)
++{
++    return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++	IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value)
++{
++	u32 tvalue = value;
++
++	if (where == PCI_PRIMARY_BUS) {
++		u8 primary, secondary, subordinate;
++
++		primary = tvalue & 0xFF;
++		secondary = (tvalue >> 8) & 0xFF;
++		subordinate = (tvalue >> 16) & 0xFF;
++		primary += pcibios_1st_host_bus_nr();
++		secondary += pcibios_1st_host_bus_nr();
++		subordinate += pcibios_1st_host_bus_nr();
++		tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++	}
++	return tvalue;
++}
++
++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value)
++{
++    u32 tvalue = value;
++
++    if (where == PCI_PRIMARY_BUS) {
++        u8 primary, secondary, subordinate;
++
++        primary = tvalue & 0xFF;
++        secondary = (tvalue >> 8) & 0xFF;
++        subordinate = (tvalue >> 16) & 0xFF;
++        if (primary > 0 && primary != 0xFF) {
++            primary -= pcibios_1st_host_bus_nr();
++        }
++
++        if (secondary > 0 && secondary != 0xFF) {
++            secondary -= pcibios_1st_host_bus_nr();
++        }
++        if (subordinate > 0 && subordinate != 0xFF) {
++            subordinate -= pcibios_1st_host_bus_nr();
++        }
++        tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++    }
++    else if (where == PCI_SUBORDINATE_BUS) {
++        u8 subordinate = tvalue & 0xFF;
++
++        subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0;
++        tvalue = subordinate;
++    }
++    return tvalue;
++}
++
++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn,
++				int where, int size, u32 *value)
++{
++    u32 data = 0;
++    int bus_number = bus->number;
++    static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
++    int ret = PCIBIOS_SUCCESSFUL;
++    struct ifx_pci_controller *ctrl = bus->sysdata;
++    int pcie_port = ctrl->port;
++
++    if (unlikely(size != 1 && size != 2 && size != 4)){
++        ret = PCIBIOS_BAD_REGISTER_NUMBER;
++        goto out;
++    }
++
++    /* Make sure the address is aligned to natural boundary */
++    if (unlikely(((size - 1) & where))) {
++        ret = PCIBIOS_BAD_REGISTER_NUMBER;
++        goto out;
++    }
++
++    /* 
++     * If we are second controller, we have to cheat OS so that it assume 
++     * its bus number starts from 0 in host controller
++     */
++    bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++    /* 
++     * We need to force the bus number to be zero on the root 
++     * bus. Linux numbers the 2nd root bus to start after all 
++     * busses on root 0. 
++     */ 
++    if (bus->parent == NULL) {
++        bus_number = 0; 
++    }
++
++    /* 
++     * PCIe only has a single device connected to it. It is 
++     * always device ID 0. Don't bother doing reads for other 
++     * device IDs on the first segment. 
++     */ 
++    if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) {
++        ret = PCIBIOS_FUNC_NOT_SUPPORTED;
++        goto out; 
++    }
++
++    if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++        *value = 0xffffffff;
++        ret = PCIBIOS_DEVICE_NOT_FOUND;
++        goto out;
++    }
++
++    PCIE_IRQ_LOCK(ifx_pcie_lock);
++    if (bus_number == 0) { /* RC itself */
++        u32 t;
++
++        t = (where & ~3);
++        data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++    } else {
++        u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++        data = ifx_pcie_cfg_rd(pcie_port, addr);
++    #ifdef CONFIG_IFX_PCIE_HW_SWAP
++            data = le32_to_cpu(data);
++    #endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    }
++    /* To get a correct PCI topology, we have to restore the bus number to OS */
++    data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1);
++
++    PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++
++    *value = (data >> (8 * (where & 3))) & mask[size & 7];
++out:
++    return ret;
++}
++
++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value)
++{
++	u32 shift;
++	u32 tdata = data;
++
++	switch (size) {
++	case 1:
++		shift = (where & 0x3) << 3;
++		tdata &= ~(0xffU << shift);
++		tdata |= ((value & 0xffU) << shift);
++		break;
++	case 2:
++		shift = (where & 3) << 3;
++		tdata &= ~(0xffffU << shift);
++		tdata |= ((value & 0xffffU) << shift);
++		break;
++	case 4:
++		tdata = value;
++		break;
++	}
++	return tdata;
++}
++
++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn,
++				int where, int size, u32 value)
++{
++	int bus_number = bus->number;
++	int ret = PCIBIOS_SUCCESSFUL;
++	struct ifx_pci_controller *ctrl = bus->sysdata;
++	int pcie_port = ctrl->port;
++	u32 tvalue = value;
++	u32 data;
++
++	/* Make sure the address is aligned to natural boundary */
++	if (unlikely(((size - 1) & where))) {
++		ret = PCIBIOS_BAD_REGISTER_NUMBER;
++		goto out;
++	}
++	/* 
++	* If we are second controller, we have to cheat OS so that it assume 
++	* its bus number starts from 0 in host controller
++	*/
++	bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++	/* 
++	* We need to force the bus number to be zero on the root 
++	* bus. Linux numbers the 2nd root bus to start after all 
++	* busses on root 0. 
++	*/ 
++	if (bus->parent == NULL) {
++		bus_number = 0; 
++	}
++
++	if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++		ret = PCIBIOS_DEVICE_NOT_FOUND;
++		goto out;
++	}
++
++	/* XXX, some PCIe device may need some delay */
++	PCIE_IRQ_LOCK(ifx_pcie_lock);
++
++	/* 
++	* To configure the correct bus topology using native way, we have to cheat Os so that
++	* it can configure the PCIe hardware correctly.
++	*/
++	tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0);
++
++	if (bus_number == 0) { /* RC itself */
++		u32 t;
++
++		t = (where & ~3);
++		data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++
++		data = ifx_pcie_size_to_value(where, size, data, tvalue);
++
++		ifx_pcie_rc_cfg_wr(pcie_port, t, data);
++	} else {
++		u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++		data = ifx_pcie_cfg_rd(pcie_port, addr);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++		data = le32_to_cpu(data);
++#endif
++
++		data = ifx_pcie_size_to_value(where, size, data, tvalue);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++		data = cpu_to_le32(data);
++#endif
++		ifx_pcie_cfg_wr(pcie_port, addr, data);
++	}
++	PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++out:
++	return ret;
++}
++
++static struct resource ifx_pcie_io_resource = {
++	.name	= "PCIe0 I/O space",
++	.start	= PCIE_IO_PHY_BASE,
++	.end	= PCIE_IO_PHY_END,
++	.flags	= IORESOURCE_IO,
++};
++
++static struct resource ifx_pcie_mem_resource = {
++	.name	= "PCIe0 Memory space",
++	.start	= PCIE_MEM_PHY_BASE,
++	.end	= PCIE_MEM_PHY_END,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct pci_ops ifx_pcie_ops = {
++	.read	= ifx_pcie_read_config,
++	.write	= ifx_pcie_write_config,
++};
++
++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = {
++    {
++        .pcic = {
++            .pci_ops      = &ifx_pcie_ops,
++            .mem_resource = &ifx_pcie_mem_resource,
++            .io_resource  = &ifx_pcie_io_resource,
++         },
++         .port = IFX_PCIE_PORT0,
++    },
++};
++
++#ifdef IFX_PCIE_ERROR_INT
++
++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id)
++{
++	struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id;
++	int pcie_port = ctrl->port;
++	u32 reg;
++
++	pr_debug("PCIe RC error intr %d\n", irq);
++	reg = IFX_REG_R32(PCIE_IRNCR(pcie_port));
++	reg &= PCIE_RC_CORE_COMBINED_INT;
++	IFX_REG_W32(reg, PCIE_IRNCR(pcie_port));
++
++	return IRQ_HANDLED;
++}
++
++static int
++pcie_rc_core_int_init(int pcie_port)
++{
++	int ret;
++
++	/* Enable core interrupt */
++	IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port));
++
++	/* Clear it first */
++	IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port));
++	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
++		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
++	if (ret)
++		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++
++	return ret;
++}
++#endif
++
++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin)
++{
++	u32 irq_bit = 0;
++	int irq = 0;
++	struct ifx_pci_controller *ctrl = dev->bus->sysdata;
++	int pcie_port = ctrl->port;
++
++	printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin);
++
++	if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) {
++		printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin);
++		return -1;
++	}
++
++	/* Pin index so minus one */
++	irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit;
++	irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq;
++	IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port));
++	IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port));
++	printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq);
++	return irq;
++}
++
++int  ifx_pcie_bios_plat_dev_init(struct pci_dev *dev)
++{
++    u16 config;
++#ifdef IFX_PCIE_ERROR_INT
++    u32 dconfig; 
++    int pos;
++#endif
++
++    /* Enable reporting System errors and parity errors on all devices */ 
++    /* Enable parity checking and error reporting */ 
++    pci_read_config_word(dev, PCI_COMMAND, &config);
++    config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE |
++          PCI_COMMAND_FAST_BACK*/;
++    pci_write_config_word(dev, PCI_COMMAND, config);
++
++    if (dev->subordinate) {
++        /* Set latency timers on sub bridges */
++        pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */
++        /* More bridge error detection */
++        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
++        config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
++        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
++    }
++#ifdef IFX_PCIE_ERROR_INT
++    /* Enable the PCIe normal error reporting */
++    pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
++    if (pos) {
++
++        /* Disable system error generation in response to error messages */
++        pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config);
++        config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE);
++        pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config);
++
++        /* Clear PCIE Capability's Device Status */
++        pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config);
++        pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config);
++
++        /* Update Device Control */ 
++        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
++        /* Correctable Error Reporting */
++        config |= PCI_EXP_DEVCTL_CERE;
++        /* Non-Fatal Error Reporting */
++        config |= PCI_EXP_DEVCTL_NFERE;
++        /* Fatal Error Reporting */
++        config |= PCI_EXP_DEVCTL_FERE;
++        /* Unsupported Request */
++        config |= PCI_EXP_DEVCTL_URRE;
++        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
++    }
++
++    /* Find the Advanced Error Reporting capability */
++    pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
++    if (pos) {
++        /* Clear Uncorrectable Error Status */ 
++        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig);
++        /* Enable reporting of all uncorrectable errors */
++        /* Uncorrectable Error Mask - turned on bits disable errors */
++        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
++        /* 
++        * Leave severity at HW default. This only controls if 
++        * errors are reported as uncorrectable or 
++        * correctable, not if the error is reported. 
++        */ 
++        /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
++        /* Clear Correctable Error Status */
++        pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
++        /* Enable reporting of all correctable errors */
++        /* Correctable Error Mask - turned on bits disable errors */
++        pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
++        /* Advanced Error Capabilities */ 
++        pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
++        /* ECRC Generation Enable */
++        if (dconfig & PCI_ERR_CAP_ECRC_GENC) {
++            dconfig |= PCI_ERR_CAP_ECRC_GENE;
++        }
++        /* ECRC Check Enable */
++        if (dconfig & PCI_ERR_CAP_ECRC_CHKC) {
++            dconfig |= PCI_ERR_CAP_ECRC_CHKE;
++        }
++        pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
++
++        /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
++        /* Enable Root Port's interrupt in response to error messages */
++        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
++              PCI_ERR_ROOT_CMD_COR_EN |
++              PCI_ERR_ROOT_CMD_NONFATAL_EN |
++              PCI_ERR_ROOT_CMD_FATAL_EN); 
++        /* Clear the Root status register */
++        pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
++        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
++    }
++#endif /* IFX_PCIE_ERROR_INT */
++    /* WAR, only 128 MRRS is supported, force all EPs to support this value */
++    pcie_set_readrq(dev, 128);
++    return 0;
++}
++
++static int
++pcie_rc_initialize(int pcie_port)
++{
++	int i;
++#define IFX_PCIE_PHY_LOOP_CNT  5
++
++	pcie_rcu_endian_setup(pcie_port);
++
++	pcie_ep_gpio_rst_init(pcie_port);
++
++	/* 
++	* XXX, PCIe elastic buffer bug will cause not to be detected. One more 
++	* reset PCIe PHY will solve this issue 
++	*/
++	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
++		/* Disable PCIe PHY Analog part for sanity check */
++		pcie_phy_pmu_disable(pcie_port);
++
++		pcie_phy_rst_assert(pcie_port);
++		pcie_phy_rst_deassert(pcie_port);
++
++		/* Make sure PHY PLL is stable */
++		udelay(20);
++
++		/* PCIe Core reset enabled, low active, sw programmed */
++		pcie_core_rst_assert(pcie_port);
++
++		/* Put PCIe EP in reset status */
++		pcie_device_rst_assert(pcie_port);
++
++		/* PCI PHY & Core reset disabled, high active, sw programmed */
++		pcie_core_rst_deassert(pcie_port);
++
++		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
++		pcie_phy_clock_mode_setup(pcie_port);
++
++		/* Enable PCIe PHY and Clock */
++		pcie_core_pmu_setup(pcie_port);
++
++		/* Clear status registers */
++		pcie_status_register_clear(pcie_port);
++
++#ifdef CONFIG_PCI_MSI
++		pcie_msi_init(pcie_port);
++#endif /* CONFIG_PCI_MSI */
++		pcie_rc_cfg_reg_setup(pcie_port);
++
++		/* Once link is up, break out */
++		if (pcie_app_loigc_setup(pcie_port) == 0)
++			break;
++	}
++	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
++		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
++		return -EIO;
++	}
++	/* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */
++	pcie_replay_time_update(pcie_port);
++	return 0;
++}
++
++static int __init ifx_pcie_bios_init(void)
++{
++    void __iomem *io_map_base;
++    int pcie_port;
++    int startup_port;
++
++    /* Enable AHB Master/ Slave */
++    pcie_ahb_pmu_setup();
++
++    startup_port = IFX_PCIE_PORT0;
++    
++    for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
++	if (pcie_rc_initialize(pcie_port) == 0) {
++	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
++                 __func__, PCIE_CFG_PORT_TO_BASE(pcie_port));
++            /* Otherwise, warning will pop up */
++            io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE);
++            if (io_map_base == NULL) {
++                IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
++                return -ENOMEM;
++            }
++            ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++
++            register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
++            /* XXX, clear error status */
++
++            IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", 
++                              __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, 
++                              &ifx_pcie_controller[pcie_port].pcic.io_resource);
++
++        #ifdef IFX_PCIE_ERROR_INT
++            pcie_rc_core_int_init(pcie_port);
++        #endif /* IFX_PCIE_ERROR_INT */
++        }
++    }
++
++    return 0;
++}
++arch_initcall(ifx_pcie_bios_init);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -0,0 +1,131 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_H
++#define IFXMIPS_PCIE_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include "ifxmips_pci_common.h"
++#include "ifxmips_pcie_reg.h"
++
++/*!
++ \defgroup IFX_PCIE  PCI Express bus driver module   
++ \brief  PCI Express IP module support VRX200 
++*/
++
++/*!
++ \defgroup IFX_PCIE_OS OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module common header file
++*/
++#define PCIE_IRQ_LOCK(lock) do {             \
++    unsigned long flags;                     \
++    spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock)                \
++    spin_unlock_irqrestore(&(lock), flags);  \
++} while (0)
++
++#define PCIE_MSG_MSI        0x00000001
++#define PCIE_MSG_ISR        0x00000002
++#define PCIE_MSG_FIXUP      0x00000004
++#define PCIE_MSG_READ_CFG   0x00000008
++#define PCIE_MSG_WRITE_CFG  0x00000010
++#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG        0x00000020
++#define PCIE_MSG_INIT       0x00000040
++#define PCIE_MSG_ERR        0x00000080
++#define PCIE_MSG_PHY        0x00000100
++#define PCIE_MSG_ANY        0x000001ff
++
++#define IFX_PCIE_PORT0      0
++#define IFX_PCIE_PORT1      1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR    2
++#else
++#define IFX_PCIE_CORE_NR    1
++#endif
++
++#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \
++        ifx_pcie_debug((_fmt), ##args);          \
++} while (0)
++
++#define INLINE 
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...)   \
++    do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++	struct pci_controller   pcic;
++    
++	/* RC specific, per host bus information */
++	u32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++    const unsigned int irq;
++    const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++    const u32 irq_bit;
++    const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++    ifx_pcie_ir_irq_t ir_irq;
++    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++#define CONFIG_VR9
++
++#ifdef CONFIG_VR9
++#include "ifxmips_pcie_vr9.h"
++#elif defined (CONFIG_AR10)
++#include "ifxmips_pcie_ar10.h"
++#else
++#error "PCIE: platform not defined"
++#endif /* CONFIG_VR9 */
++
++#endif  /* IFXMIPS_PCIE_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_ar10.h
+@@ -0,0 +1,305 @@
++/****************************************************************************
++                              Copyright (c) 2010
++                            Lantiq Deutschland GmbH
++                     Am Campeon 3; 85579 Neubiberg, Germany
++
++  For licensing information, see the file 'LICENSE' in the root folder of
++  this software module.
++
++ *****************************************************************************/
++/*!
++  \file ifxmips_pcie_ar10.h
++  \ingroup IFX_PCIE
++  \brief PCIe RC driver ar10 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_AR10_H
++#define IFXMIPS_PCIE_AR10_H
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/types.h>
++#include <linux/delay.h>
++
++/* Project header file */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_pmu.h>
++#include <asm/ifx/ifx_gpio.h>
++#include <asm/ifx/ifx_ebu_led.h>
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++    ifx_ebu_led_enable();
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 1);        
++    }
++    else {
++        ifx_ebu_led_set_data(12, 1);  
++    }
++}
++
++static inline void pcie_ahb_pmu_setup(void) 
++{
++    /* XXX, moved to CGU to control AHBM */
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Inbound, big endian */
++    reg |= IFX_RCU_BE_AHB4S;
++    if (pcie_port == 0) {
++        reg |= IFX_RCU_BE_PCIE0M;
++
++    #ifdef CONFIG_IFX_PCIE_HW_SWAP
++        /* Outbound, software swap needed */
++        reg |= IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE0S;
++    #else
++        /* Outbound little endian  */
++        reg &= ~IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE0S;
++    #endif
++    }
++    else {
++        reg |= IFX_RCU_BE_PCIE1M;
++    #ifdef CONFIG_IFX_PCIE1_HW_SWAP
++        /* Outbound, software swap needed */
++        reg |= IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE1S;
++    #else
++        /* Outbound little endian  */
++        reg &= ~IFX_RCU_BE_AHB3M;
++        reg &= ~IFX_RCU_BE_PCIE1S;
++    #endif
++    }
++
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++    if (pcie_port == 0) { /* XXX, should use macro*/
++        PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++    if (pcie_port == 0) { /* XXX, should use macro*/
++        PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++    }
++    else {
++        PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++    }
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    if (pcie_port == 0) {
++        /* Config AHB->PCIe and PDI endianness */
++        reg |= IFX_RCU_BE_PCIE0_PDI;
++    }
++    else {
++        /* Config AHB->PCIe and PDI endianness */
++        reg |= IFX_RCU_BE_PCIE1_PDI;
++    }
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++    if (pcie_port == 0) {
++        /* Enable PDI to access PCIe PHY register */
++        PDI0_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PDI1_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset Core, bit 22 */
++    if (pcie_port == 0) {
++        reg |= 0x00400000;
++    }
++    else {
++        reg |= 0x08000000; /* Bit 27 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg &= ~0x00400000; /* bit 22 */
++    }
++    else {
++        reg &= ~0x08000000; /* Bit 27 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg |= 0x00001000; /* Bit 12 */
++    }
++    else {
++        reg |= 0x00002000; /* Bit 13 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    if (pcie_port == 0) {
++        reg &= ~0x00001000; /* Bit 12 */
++    }
++    else {
++        reg &= ~0x00002000; /* Bit 13 */
++    }
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 0);
++    }
++    else {
++        ifx_ebu_led_set_data(12, 0);
++    }
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++    if (pcie_port == 0) {
++        ifx_ebu_led_set_data(11, 1);
++    }
++    else {
++        ifx_ebu_led_set_data(12, 1);
++    }
++    ifx_ebu_led_disable();
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++    if (pcie_port == 0) {
++        PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); 
++    }
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++    pcie_msi_pic_init(pcie_port);
++    if (pcie_port == 0) {
++        MSI0_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++    else {
++        MSI1_PMU_SETUP(IFX_PMU_ENABLE);
++    }
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++        if (pcibios_host_nr() > 1) {
++            tbus_number -= pcibios_1st_host_bus_nr();
++        }        
++    }
++#endif /* CONFIG_IFX_PCI */
++    return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_IFX_PCIE_2ND_CORE
++        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++            if (pcibios_host_nr() > 1) {
++                tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++            }
++        }
++    #endif /* CONFIG_IFX_PCIE_2ND_CORE */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_IFX_PCIE_2ND_CORE
++        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++            if (pcibios_host_nr() > 1) {
++                tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++            }
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_AR10_H */
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_msi.c
+@@ -0,0 +1,391 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_msi.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCI MSI sub module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe MSI Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Date        $Author         $Comment
++** 02 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \defgroup IFX_PCIE_MSI MSI OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie_msi.c
++ \ingroup IFX_PCIE 
++ \brief PCIe MSI OS interface file
++*/
++
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/pci.h>
++#include <linux/msi.h>
++#include <linux/module.h>
++#include <asm/bootinfo.h>
++#include <asm/irq.h>
++#include <asm/traps.h>
++
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/irq.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++#define IFX_MSI_IRQ_NUM    16
++
++enum {
++    IFX_PCIE_MSI_IDX0 = 0,
++    IFX_PCIE_MSI_IDX1,
++    IFX_PCIE_MSI_IDX2,
++    IFX_PCIE_MSI_IDX3,
++};
++
++typedef struct ifx_msi_irq_idx {
++    const int irq;
++    const int idx;
++}ifx_msi_irq_idx_t;
++
++struct ifx_msi_pic {
++    volatile u32  pic_table[IFX_MSI_IRQ_NUM];
++    volatile u32  pic_endian;    /* 0x40  */
++};
++typedef struct ifx_msi_pic *ifx_msi_pic_t;
++
++typedef struct ifx_msi_irq {
++    const volatile ifx_msi_pic_t msi_pic_p;
++    const u32 msi_phy_base;
++    const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];
++    /*
++     * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 
++     * in use.
++     */
++    u16 msi_free_irq_bitmask;
++
++    /*
++     * Each bit in msi_multiple_irq_bitmask tells that the device using 
++     * this bit in msi_free_irq_bitmask is also using the next bit. This 
++     * is used so we can disable all of the MSI interrupts when a device 
++     * uses multiple.
++     */
++    u16 msi_multiple_irq_bitmask;
++}ifx_msi_irq_t;
++
++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {
++    {
++        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,
++        .msi_phy_base = PCIE_MSI_PHY_BASE,
++        .msi_irq_idx = {
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++        },
++        .msi_free_irq_bitmask = 0,
++        .msi_multiple_irq_bitmask= 0,
++    },
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    {
++        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,
++        .msi_phy_base = PCIE1_MSI_PHY_BASE,
++        .msi_irq_idx = {
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++        },
++        .msi_free_irq_bitmask = 0,
++        .msi_multiple_irq_bitmask= 0,
++
++    },
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++};
++
++/* 
++ * This lock controls updates to msi_free_irq_bitmask, 
++ * msi_multiple_irq_bitmask and pic register settting
++ */ 
++static DEFINE_SPINLOCK(ifx_pcie_msi_lock);
++
++void pcie_msi_pic_init(int pcie_port)
++{
++    spin_lock(&ifx_pcie_msi_lock);
++    msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;
++    spin_unlock(&ifx_pcie_msi_lock);
++}
++
++/** 
++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++ * \brief Called when a driver request MSI interrupts instead of the 
++ * legacy INT A-D. This routine will allocate multiple interrupts 
++ * for MSI devices that support them. A device can override this by 
++ * programming the MSI control bits [6:4] before calling 
++ * pci_enable_msi(). 
++ * 
++ * \param[in] pdev   Device requesting MSI interrupts 
++ * \param[in] desc   MSI descriptor 
++ * 
++ * \return   -EINVAL Invalid pcie root port or invalid msi bit
++ * \return    0        OK
++ * \ingroup IFX_PCIE_MSI
++ */
++int 
++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++{
++    int  irq, pos;
++    u16  control;
++    int  irq_idx;
++    int  irq_step;
++    int configured_private_bits;
++    int request_private_bits;
++    struct msi_msg msg;
++    u16 search_mask;
++    struct ifx_pci_controller *ctrl = pdev->bus->sysdata;
++    int pcie_port = ctrl->port;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev));
++
++    /* XXX, skip RC MSI itself */
++    if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
++        IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__);
++        return -EINVAL;
++    }
++
++    /*
++     * Read the MSI config to figure out how many IRQs this device 
++     * wants.  Most devices only want 1, which will give 
++     * configured_private_bits and request_private_bits equal 0. 
++     */
++    pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);
++
++    /*
++     * If the number of private bits has been configured then use 
++     * that value instead of the requested number. This gives the 
++     * driver the chance to override the number of interrupts 
++     * before calling pci_enable_msi(). 
++     */
++    configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; 
++    if (configured_private_bits == 0) {
++        /* Nothing is configured, so use the hardware requested size */
++        request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
++    }
++    else {
++        /*
++         * Use the number of configured bits, assuming the 
++         * driver wanted to override the hardware request 
++         * value.
++         */
++        request_private_bits = configured_private_bits;
++    }
++
++    /*
++     * The PCI 2.3 spec mandates that there are at most 32
++     * interrupts. If this device asks for more, only give it one.
++     */
++    if (request_private_bits > 5) {
++        request_private_bits = 0;
++    }
++again:
++    /*
++     * The IRQs have to be aligned on a power of two based on the
++     * number being requested.
++     */
++    irq_step = (1 << request_private_bits);
++
++    /* Mask with one bit for each IRQ */
++    search_mask = (1 << irq_step) - 1;
++
++    /*
++     * We're going to search msi_free_irq_bitmask_lock for zero 
++     * bits. This represents an MSI interrupt number that isn't in 
++     * use.
++     */
++    spin_lock(&ifx_pcie_msi_lock);
++    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {
++        if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {
++            msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; 
++            msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;
++            break; 
++        }
++    }
++    spin_unlock(&ifx_pcie_msi_lock); 
++
++    /* Make sure the search for available interrupts didn't fail */ 
++    if (pos >= IFX_MSI_IRQ_NUM) {
++        if (request_private_bits) {
++            IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free "
++                  "interrupts, trying just one", __func__, 1 << request_private_bits);
++            request_private_bits = 0;
++            goto again;
++        }
++        else {
++            printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__);
++            return -EINVAL;
++        }
++    } 
++    irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;
++    irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx);
++
++    /*
++     * Initialize MSI. This has to match the memory-write endianess from the device 
++     * Address bits [23:12]
++     */
++    spin_lock(&ifx_pcie_msi_lock); 
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |
++                    SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |
++                    SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++
++    /* Enable this entry */
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;
++    spin_unlock(&ifx_pcie_msi_lock);
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n",
++        pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);
++
++    /* Update the number of IRQs the device has available to it */
++    control &= ~PCI_MSI_FLAGS_QSIZE;
++    control |= (request_private_bits << 4);
++    pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);
++
++    set_irq_msi(irq, desc);
++    msg.address_hi = 0x0;
++    msg.address_lo = msi_irqs[pcie_port].msi_phy_base;
++    msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data);
++
++    write_msi_msg(irq, &msg);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++    return 0;
++}
++
++static int
++pcie_msi_irq_to_port(unsigned int irq, int *port)
++{
++    int ret = 0;
++
++    if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||
++        irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {
++        *port = IFX_PCIE_PORT0;
++    }
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++    else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||
++        irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {
++        *port = IFX_PCIE_PORT1;
++    }
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++    else {
++        printk(KERN_ERR "%s: Attempted to teardown illegal " 
++            "MSI interrupt (%d)\n", __func__, irq);
++        ret = -EINVAL;
++    }
++    return ret;
++}
++
++/** 
++ * \fn void arch_teardown_msi_irq(unsigned int irq)
++ * \brief Called when a device no longer needs its MSI interrupts. All 
++ * MSI interrupts for the device are freed. 
++ * 
++ * \param irq   The devices first irq number. There may be multple in sequence.
++ * \return none
++ * \ingroup IFX_PCIE_MSI
++ */
++void 
++arch_teardown_msi_irq(unsigned int irq)
++{
++    int pos;
++    int number_irqs; 
++    u16 bitmask;
++    int pcie_port;
++
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__);
++
++    BUG_ON(irq > INT_NUM_IM4_IRL31);
++
++    if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {
++        return;
++    }
++
++    /* Shift the mask to the correct bit location, not always correct 
++     * Probally, the first match will be chosen.
++     */
++    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {
++        if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) 
++            && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {
++            break;
++        }
++    }
++    if (pos >= IFX_MSI_IRQ_NUM) {
++        printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__);
++        return;
++    }
++    spin_lock(&ifx_pcie_msi_lock);
++    /* Disable this entry */
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;
++    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);
++    spin_unlock(&ifx_pcie_msi_lock); 
++    /*
++     * Count the number of IRQs we need to free by looking at the
++     * msi_multiple_irq_bitmask. Each bit set means that the next
++     * IRQ is also owned by this device.
++     */ 
++    number_irqs = 0; 
++    while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && 
++        (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {
++        number_irqs++;
++    }
++    number_irqs++;
++
++    /* Mask with one bit for each IRQ */
++    bitmask = (1 << number_irqs) - 1;
++
++    bitmask <<= pos;
++    if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {
++        printk(KERN_ERR "%s: Attempted to teardown MSI "
++             "interrupt (%d) not in use\n", __func__, irq);
++        return;
++    }
++    /* Checks are done, update the in use bitmask */
++    spin_lock(&ifx_pcie_msi_lock);
++    msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;
++    msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);
++    spin_unlock(&ifx_pcie_msi_lock);
++    IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_phy.c
+@@ -0,0 +1,478 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_phy.c
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe PHY sub module
++**
++** DATE         : 14 May 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    14 May,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_phy.c
++ \ingroup IFX_PCIE  
++ \brief PCIe PHY PLL register programming source file
++*/
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/paccess.h>
++#include <linux/delay.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++/* PCIe PDI only supports 16 bit operation */
++
++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \
++    ((*(volatile u16 *) (__addr)) = (__data))
++    
++#define IFX_PCIE_PHY_REG_READ16(__addr)  \
++    (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG16(__addr)   \
++    (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \
++    u16 read_data;                                    \
++    u16 write_data;                                   \
++    read_data = IFX_PCIE_PHY_REG_READ16((__reg));      \
++    write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\
++    IFX_PCIE_PHY_REG_WRITE16((__reg), write_data);               \
++} while (0)
++
++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */
++
++//#define IFX_PCI_PHY_REG_DUMP
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++static void
++pcie_phy_reg_dump(int pcie_port) 
++{
++    printk("PLL REGFILE\n");
++    printk("PCIE_PHY_PLL_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL3    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL4    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL5    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL6    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port)));
++    printk("PCIE_PHY_PLL_CTRL7    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_PLL_A_CTRL3  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port)));
++    printk("PCIE_PHY_PLL_STATUS   0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)));
++
++    printk("TX1 REGFILE\n");
++    printk("PCIE_PHY_TX1_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX1_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX1_CTRL3    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port)));
++    printk("PCIE_PHY_TX1_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX1_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD1     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD2     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port)));
++    printk("PCIE_PHY_TX1_MOD3     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port)));
++
++    printk("TX2 REGFILE\n");
++    printk("PCIE_PHY_TX2_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX2_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX2_A_CTRL1  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port)));
++    printk("PCIE_PHY_TX2_A_CTRL2  0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD1     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD2     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port)));
++    printk("PCIE_PHY_TX2_MOD3     0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port)));
++
++    printk("RX1 REGFILE\n");
++    printk("PCIE_PHY_RX1_CTRL1    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port)));
++    printk("PCIE_PHY_RX1_CTRL2    0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port)));
++    printk("PCIE_PHY_RX1_CDR      0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port)));
++    printk("PCIE_PHY_RX1_EI       0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port)));
++    printk("PCIE_PHY_RX1_A_CTRL   0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port)));
++}
++#endif /* IFX_PCI_PHY_REG_DUMP */
++
++static void
++pcie_phy_comm_setup(int pcie_port)
++{
++   /* PLL Setting */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++    /* increase the bias reference voltage */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++    /* Endcnt */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++    /* force */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++    /* ctrl_lim */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++    /* ctrl */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++    /* RTERM*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++    /* Improved 100MHz clock output  */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++    /* Reduced CDR BW to avoid glitches */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++}
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++static void 
++pcie_phy_36mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE
++static void 
++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++
++    /* PLL Setting */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++    /* Increase the bias reference voltage */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++    /* Endcnt */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++    /* Force */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++    /* Predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++    /* ctrl_lim */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++    /* ctrl */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++    /* predrv_ser_en */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++    /* RTERM*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100);
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF);
++
++    /* improved 100MHz clock output  */
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++    /* reduced CDR BW to avoid glitches */
++    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++    
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE
++static void 
++pcie_phy_25mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* pll_ensdm */    
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200);
++
++    /* en_ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE
++static void 
++pcie_phy_100mhz_mode_setup(int pcie_port) 
++{
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif 
++    /* en_ext_mmd_div_ratio */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++    /* ext_mmd_div_ratio*/
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++    /* pll_ensdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++    /* en_const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++    /* mmd */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++    /* lf_mode */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++    /* const_sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++    /* const sdm */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++    /* pllmod */
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */
++
++static int
++pcie_phy_wait_startup_ready(int pcie_port)
++{
++    int i;
++
++    for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) {
++        if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) {
++            break;
++        }
++        udelay(10);
++    }
++    if (i >= IFX_PCIE_PLL_TIMEOUT) {
++        printk(KERN_ERR "%s PLL Link timeout\n", __func__);
++        return -1;
++    }
++    return 0;
++}
++
++static void 
++pcie_phy_load_enable(int pcie_port, int slice) 
++{
++    /* Set the load_en of tx/rx slice to '1' */
++    switch (slice) {
++        case 1:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010);
++            break;
++        case 2:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010);
++            break;
++        case 3:
++            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002);
++            break;
++    }
++}
++
++static void 
++pcie_phy_load_disable(int pcie_port, int slice) 
++{ 
++    /* set the load_en of tx/rx slice to '0' */ 
++    switch (slice) {
++        case 1:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010);
++            break;
++        case 2:
++            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010);
++            break;
++        case 3: 
++            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002);
++            break;
++    }
++}
++
++static void 
++pcie_phy_load_war(int pcie_port)
++{
++    int slice;
++
++    for (slice = 1; slice < 4; slice++) {
++        pcie_phy_load_enable(pcie_port, slice);
++        udelay(1);
++        pcie_phy_load_disable(pcie_port, slice);
++    }
++}
++
++static void 
++pcie_phy_tx2_modulation(int pcie_port)
++{
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF);
++    mdelay(1);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void 
++pcie_phy_tx1_modulation(int pcie_port)
++{
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF);
++    mdelay(1);
++    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void
++pcie_phy_tx_modulation_war(int pcie_port)
++{
++    int i;
++
++#define PCIE_PHY_MODULATION_NUM 5 
++    for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) {
++        pcie_phy_tx2_modulation(pcie_port);
++        pcie_phy_tx1_modulation(pcie_port);
++    }
++#undef PCIE_PHY_MODULATION_NUM
++}
++
++void
++pcie_phy_clock_mode_setup(int pcie_port)
++{
++    pcie_pdi_big_endian(pcie_port);
++
++    /* Enable PDI to access PCIe PHY register */
++    pcie_pdi_pmu_enable(pcie_port);
++
++    /* Configure PLL and PHY clock */
++    pcie_phy_comm_setup(pcie_port);
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++    pcie_phy_36mhz_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE)
++    pcie_phy_36mhz_ssc_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE)
++    pcie_phy_25mhz_mode_setup(pcie_port);
++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE)
++    pcie_phy_100mhz_mode_setup(pcie_port);
++#else
++    #error "PCIE PHY Clock Mode must be chosen first!!!!"
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++    /* Enable PCIe PHY and make PLL setting take effect */
++    pcie_phy_pmu_enable(pcie_port);
++
++    /* Check if we are in startup_ready status */
++    pcie_phy_wait_startup_ready(pcie_port);
++
++    pcie_phy_load_war(pcie_port);
++
++    /* Apply TX modulation workarounds */
++    pcie_phy_tx_modulation_war(pcie_port);
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++    IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n");
++    pcie_phy_reg_dump(pcie_port);
++#endif
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.c
+@@ -0,0 +1,176 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_pm.c
++** PROJECT      : IFX UEIP
++** MODULES      : PCIE Root Complex Driver
++**
++** DATE         : 21 Dec 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIE Root Complex Driver Power Managment
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Lantiq Deutschland GmbH
++**                      Am Campeon 3, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 21 Dec,2009   Lei Chuanhua    First UEIP release
++*******************************************************************************/
++/*!
++  \defgroup IFX_PCIE_PM Power Management functions
++  \ingroup IFX_PCIE
++  \brief IFX PCIE Root Complex Driver power management functions
++*/
++
++/*!
++ \file ifxmips_pcie_pm.c
++ \ingroup IFX_PCIE    
++ \brief source file for PCIE Root Complex Driver Power Management
++*/
++
++#ifndef EXPORT_SYMTAB
++#define EXPORT_SYMTAB
++#endif
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/system.h>
++
++/* Project header */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/ifx_pmcu.h>
++#include "ifxmips_pcie_pm.h"
++
++/** 
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++ * \brief the callback function to request pmcu state in the power management hardware-dependent module
++ *
++ * \param pmcuState This parameter is a PMCU state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++{
++    switch(pmcuState) 
++    {
++        case IFX_PMCU_STATE_D0:
++            return IFX_PMCU_RETURN_SUCCESS;
++        case IFX_PMCU_STATE_D1: // Not Applicable
++            return IFX_PMCU_RETURN_DENIED;
++        case IFX_PMCU_STATE_D2: // Not Applicable
++            return IFX_PMCU_RETURN_DENIED;
++        case IFX_PMCU_STATE_D3: // Module clock gating and Power gating
++            return IFX_PMCU_RETURN_SUCCESS;
++        default:
++            return IFX_PMCU_RETURN_DENIED;
++    }
++}
++
++/** 
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++ * \brief the callback function to get pmcu state in the power management hardware-dependent module
++
++ * \param pmcuState Pointer to return power state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ * 
++ * \param   pmcuModule      Module
++ * \param   newState        New state
++ * \param   oldState        Old state
++ * \return  IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return  IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ * 
++ * \param   pmcuModule      Module
++ * \param   newState        New state
++ * \param   oldState        Old state
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR   Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t 
++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++    return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/** 
++ * \fn static void ifx_pcie_pmcu_init(void)
++ * \brief Register with central PMCU module
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_init(void)
++{
++    IFX_PMCU_REGISTER_t pmcuRegister;
++
++    /* XXX, hook driver context */
++
++    /* State function register */
++    memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t));
++    pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++    pmcuRegister.pmcuModuleNr = 0;
++    pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change;
++    pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get;
++    pmcuRegister.pre = ifx_pcie_pmcu_prechange;
++    pmcuRegister.post= ifx_pcie_pmcu_postchange;
++    ifx_pmcu_register(&pmcuRegister); 
++}
++
++/** 
++ * \fn static void ifx_pcie_pmcu_exit(void)
++ * \brief Unregister with central PMCU module
++ *
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_exit(void)
++{
++    IFX_PMCU_REGISTER_t pmcuUnRegister;
++
++   /* XXX, hook driver context */
++   
++    pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++    pmcuUnRegister.pmcuModuleNr = 0;
++    ifx_pmcu_unregister(&pmcuUnRegister);
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_pm.h
++** PROJECT      : IFX UEIP
++** MODULES      : PCIe Root Complex Driver
++**
++** DATE         : 21 Dec 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver Power Managment
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Lantiq Deutschland GmbH
++**                      Am Campeon 3, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 21 Dec,2009   Lei Chuanhua    First UEIP release
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_pm.h
++ \ingroup IFX_PCIE 
++ \brief header file for PCIe Root Complex Driver Power Management
++*/
++
++#ifndef IFXMIPS_PCIE_PM_H
++#define IFXMIPS_PCIE_PM_H
++
++void ifx_pcie_pmcu_init(void);
++void ifx_pcie_pmcu_exit(void);
++
++#endif /* IFXMIPS_PCIE_PM_H  */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_reg.h
+@@ -0,0 +1,1001 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_reg.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE        0x1D000000UL
++#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE        0x1C000000UL
++#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE         0x1D800000UL
++#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE        0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE        0x1F106800UL
++#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE            0x400
++
++#define PCIE1_CFG_PHY_BASE        0x19000000UL
++#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE        0x18000000UL
++#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE         0x19800000UL
++#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE        0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE        0x1F700400UL
++#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE            0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4
++
++#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S            9
++
++#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++    PCIE_RC_DR_D0 = 0,
++    PCIE_RC_DR_D1,   /* Not supported */
++    PCIE_RC_DR_D2,   /* Not supported */
++    PCIE_RC_DR_D3,
++    PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S              4
++#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S             9
++#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S                0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S               0
++#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S             5
++#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S                 12
++#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S               18
++#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S                22
++
++/* Format Definition */
++enum {
++    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/
++    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */
++    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */
++    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++    PCIE_VM_MSG_TC0 = 0,
++    PCIE_VM_MSG_TC1,
++    PCIE_VM_MSG_TC2,
++    PCIE_VM_MSG_TC3,
++    PCIE_VM_MSG_TC4,
++    PCIE_VM_MSG_TC5,
++    PCIE_VM_MSG_TC6,
++    PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */
++    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */
++    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/
++    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN  0
++#define PCIE_VM_MSG_LEN_MAX  1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8
++#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S              16
++#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S               24
++
++#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S             3
++#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S               5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S             0
++#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA                       0x00002000  /* INTA */
++#define PCIE_IRN_INTB                       0x00004000  /* INTB */
++#define PCIE_IRN_INTC                       0x00008000  /* INTC */
++#define PCIE_IRN_INTD                       0x00010000  /* INTD */
++#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S           0
++#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S         8
++#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S               16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4
++#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S               4
++#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S              20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */
++#define PCIE_PMBL_64BIT_ADDR                    0x00000001
++#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S                 4
++#define PCIE_PMBL_E64MA                         0x00010000
++#define PCIE_PMBL_END_ADDR                      0xFFF00000
++#define PCIE_PMBL_END_ADDR_S                    20
++#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */
++#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16
++
++#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S               0
++#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S                8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++    PCIE_INTRBCTRL_INT_NON = 0,
++    PCIE_INTRBCTRL_INTA,
++    PCIE_INTRBCTRL_INTB,
++    PCIE_INTRBCTRL_INTC,
++    PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S         0
++#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S           0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8
++#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S        17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20
++#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */
++#define PCIE_MD_DATA_S                    0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S                    0
++#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S              8
++#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S                   16
++#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S         20
++#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S           25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0
++#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S          3
++#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S        6
++#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S         9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++    PCIE_MAX_PAYLOAD_128 = 0,
++    PCIE_MAX_PAYLOAD_256,
++    PCIE_MAX_PAYLOAD_512,
++    PCIE_MAX_PAYLOAD_1024,
++    PCIE_MAX_PAYLOAD_2048,
++    PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5
++#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++                                  PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S             0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4
++#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S                 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12
++#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S            15
++#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */
++#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */
++#define PCIE_LCAP_PORT_NUM_S                   24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES  0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2   0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4   0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8   0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16  0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32  0x20
++
++/* Active State Link PM definition */
++enum {
++    PCIE_ASPM_RES0                = 0,
++    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */
++    PCIE_ASPM_RES1,
++    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */
++    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */
++    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */
++    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */
++    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */
++    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */
++    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */
++    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */
++};
++
++/* L1 Exit Latency definition */
++enum {
++    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */
++    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */
++    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */
++    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */
++    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */
++    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */
++    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */
++    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S          0
++#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S           16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S                 0
++#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */
++#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S               0
++#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S              16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */
++#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \
++                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */
++#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */
++#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S          0
++#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S              27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S                  0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4
++#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S                     8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN   0
++#define PCIE_EXT_VC_CNT_MAX   7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR                0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24
++
++/* Port VC Control and Status Register */     
++#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S            1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17
++#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S                 24
++#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16
++
++/* Other Message Register */
++#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S                 0
++#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */
++#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */
++#define PCIE_PFLR_LINK_STATE_S               16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */
++#define PCIE_AFR_AF_S                        0
++#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S                   8
++#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S               16
++#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24
++#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S          27
++#define PCIE_AFR_FTS_NUM_DEFAULT             32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  
++#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S                16
++#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S             0
++#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */
++#define PCIE_SNR_TS_S                        0
++#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S                       8
++#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S              14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19
++#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S                  28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S          0
++#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12
++
++/* Queue Status Register */
++#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21
++
++/* Applicable to the above three registers */
++enum {
++    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,
++    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/* 
++ * PCIe PDI PHY register definition, suppose all the following 
++ * stuff is confidential. 
++ * XXX, detailed bit definition
++ */
++#define	PCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define	PCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define	PCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define	PCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define	PCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define	PCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define	PCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define	PCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define	PCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define	PCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define	PCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++ 
++#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA  1
++#define PCIE_LEGACY_INTB  2
++#define PCIE_LEGACY_INTC  3
++#define PCIE_LEGACY_INTD  4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#endif /* IFXMIPS_PCIE_REG_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -0,0 +1,284 @@
++/****************************************************************************
++                              Copyright (c) 2010
++                            Lantiq Deutschland GmbH
++                     Am Campeon 3; 85579 Neubiberg, Germany
++
++  For licensing information, see the file 'LICENSE' in the root folder of
++  this software module.
++
++ *****************************************************************************/
++/*!
++  \file ifxmips_pcie_vr9.h
++  \ingroup IFX_PCIE
++  \brief PCIe RC driver vr9 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_VR9_H
++#define IFXMIPS_PCIE_VR9_H
++
++#include <linux/types.h>
++#include <linux/delay.h>
++
++#include <linux/gpio.h>
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET  494
++
++#define IFX_REG_R32    ltq_r32
++#define IFX_REG_W32    ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU                                 (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S                    0x00000008  /* Configure AHB slave port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY   (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL  (1)
++#define IFX_PMU1_MODULE_PDI        (4)
++#define IFX_PMU1_MODULE_MSI        (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++#define IFX_GPIO				(KSEG1 | 0x1E100B00)
++#define ALT0			((volatile u32*)(IFX_GPIO + 0x007c))
++#define ALT1			((volatile u32*)(IFX_GPIO + 0x0080))
++#define OD			((volatile u32*)(IFX_GPIO + 0x0084))
++#define DIR			((volatile u32*)(IFX_GPIO + 0x0078))
++#define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++
++	gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
++	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++
++/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
++}
++
++static inline void pcie_ahb_pmu_setup(void) 
++{
++	/* Enable AHB bus master/slave */
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "ahb");
++	clk_enable(clk);
++
++    //AHBM_PMU_SETUP(IFX_PMU_ENABLE);
++    //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg |= IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else 
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "phy");
++	clk_enable(clk);
++
++	//PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "phy");
++	clk_disable(clk);
++
++//    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    /* SRAM2PDI endianness control. */
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Config AHB->PCIe and PDI endianness */
++    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++    /* Enable PDI to access PCIe PHY register */
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "pdi");
++	clk_enable(clk);
++    //PDI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
++    reg |= 0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    /* Reset PCIe PHY & Core, bit 22 */
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg |= 0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("1d900000.pcie", "ctl");
++	clk_enable(clk);
++	clk = clk_get_sys("1d900000.pcie", "bus");
++	clk_enable(clk);
++
++    /* PCIe Core controller enabled */
++//    PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++
++    /* Enable PCIe L0 Clock */
++//  PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++	struct clk *clk;
++	pcie_msi_pic_init(pcie_port);
++	clk = clk_get_sys("ltq_pcie", "msi");
++	clk_enable(clk);
++//    MSI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++    if (pcibios_host_nr() > 1) {
++        tbus_number -= pcibios_1st_host_bus_nr();
++    }
++#endif /* CONFIG_PCI_LANTIQ */
++    return tbus_number;
++}
++
++static inline struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++        }
++    #endif /* CONFIG_PCI_LANTIQ */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
+--- a/arch/mips/pci/pci-legacy.c
++++ b/arch/mips/pci/pci-legacy.c
+@@ -304,3 +304,30 @@ char *__init pcibios_setup(char *str)
+ 		return pcibios_plat_setup(str);
+ 	return str;
+ }
++
++int pcibios_host_nr(void)
++{
++    int count = 0;
++    struct pci_controller *hose;
++    list_for_each_entry(hose, &controllers, list) {
++        count++;
++    }
++    return count;
++}
++EXPORT_SYMBOL(pcibios_host_nr);
++
++int pcibios_1st_host_bus_nr(void)
++{
++    int bus_nr = 0;
++    struct pci_controller *hose;
++
++    hose = list_first_entry_or_null(&controllers, struct pci_controller, list);
++
++    if (hose != NULL) {
++        if (hose->bus != NULL) {
++            bus_nr = hose->bus->number + 1;
++        }
++    }
++    return bus_nr;
++}
++EXPORT_SYMBOL(pcibios_1st_host_bus_nr);
+--- /dev/null
++++ b/arch/mips/pci/pcie-lantiq.h
+@@ -0,0 +1,1316 @@
++/******************************************************************************
++**
++** FILE NAME    : ifxmips_pcie_reg.h
++** PROJECT      : IFX UEIP for VRX200
++** MODULES      : PCIe module
++**
++** DATE         : 02 Mar 2009
++** AUTHOR       : Lei Chuanhua
++** DESCRIPTION  : PCIe Root Complex Driver
++** COPYRIGHT    :       Copyright (c) 2009
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++** HISTORY
++** $Version $Date        $Author         $Comment
++** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE  
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE        0x1D000000UL
++#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE        0x1C000000UL
++#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE         0x1D800000UL
++#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE        0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE        0x1F106800UL
++#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE            0x400
++
++#define PCIE1_CFG_PHY_BASE        0x19000000UL
++#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE        0x18000000UL
++#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE         0x19800000UL
++#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE            (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE        0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE        0x1F700400UL
++#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE            0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4
++
++#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S            9
++
++#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++    PCIE_RC_DR_D0 = 0,
++    PCIE_RC_DR_D1,   /* Not supported */
++    PCIE_RC_DR_D2,   /* Not supported */
++    PCIE_RC_DR_D3,
++    PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S              4
++#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S             9
++#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S                0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S               0
++#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S             5
++#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S                 12
++#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S               18
++#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S                22
++
++/* Format Definition */
++enum {
++    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/
++    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */
++    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */
++    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++    PCIE_VM_MSG_TC0 = 0,
++    PCIE_VM_MSG_TC1,
++    PCIE_VM_MSG_TC2,
++    PCIE_VM_MSG_TC3,
++    PCIE_VM_MSG_TC4,
++    PCIE_VM_MSG_TC5,
++    PCIE_VM_MSG_TC6,
++    PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */
++    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */
++    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/
++    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN  0
++#define PCIE_VM_MSG_LEN_MAX  1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8
++#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S              16
++#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S               24
++
++#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S             3
++#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S               5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S             0
++#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA                       0x00002000  /* INTA */
++#define PCIE_IRN_INTB                       0x00004000  /* INTB */
++#define PCIE_IRN_INTC                       0x00008000  /* INTC */
++#define PCIE_IRN_INTD                       0x00010000  /* INTD */
++#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S           0
++#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S         8
++#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S               16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4
++#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S               4
++#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S              20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */
++#define PCIE_PMBL_64BIT_ADDR                    0x00000001
++#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S                 4
++#define PCIE_PMBL_E64MA                         0x00010000
++#define PCIE_PMBL_END_ADDR                      0xFFF00000
++#define PCIE_PMBL_END_ADDR_S                    20
++#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */
++#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16
++
++#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S               0
++#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S                8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++    PCIE_INTRBCTRL_INT_NON = 0,
++    PCIE_INTRBCTRL_INTA,
++    PCIE_INTRBCTRL_INTB,
++    PCIE_INTRBCTRL_INTC,
++    PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S         0
++#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S           0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8
++#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S        17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20
++#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */
++#define PCIE_MD_DATA_S                    0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S                    0
++#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S              8
++#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S                   16
++#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S         20
++#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S           25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0
++#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S          3
++#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S        6
++#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S         9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++    PCIE_MAX_PAYLOAD_128 = 0,
++    PCIE_MAX_PAYLOAD_256,
++    PCIE_MAX_PAYLOAD_512,
++    PCIE_MAX_PAYLOAD_1024,
++    PCIE_MAX_PAYLOAD_2048,
++    PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5
++#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++                                  PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S             0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4
++#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S                 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12
++#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S            15
++#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */
++#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */
++#define PCIE_LCAP_PORT_NUM_S                   24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES  0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2   0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4   0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8   0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16  0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32  0x20
++
++/* Active State Link PM definition */
++enum {
++    PCIE_ASPM_RES0                = 0,
++    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */
++    PCIE_ASPM_RES1,
++    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */
++    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */
++    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */
++    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */
++    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */
++    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */
++    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */
++    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */
++};
++
++/* L1 Exit Latency definition */
++enum {
++    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */
++    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */
++    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */
++    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */
++    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */
++    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */
++    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */
++    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S          0
++#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S           16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S                 0
++#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */
++#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S               0
++#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S              16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */
++#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \
++                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */
++#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */
++#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S          0
++#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S              27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S                  0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4
++#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S                     8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN   0
++#define PCIE_EXT_VC_CNT_MAX   7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR                0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24
++
++/* Port VC Control and Status Register */     
++#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S            1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17
++#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S                 24
++#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16
++
++/* Other Message Register */
++#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S                 0
++#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */
++#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */
++#define PCIE_PFLR_LINK_STATE_S               16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */
++#define PCIE_AFR_AF_S                        0
++#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S                   8
++#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S               16
++#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24
++#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S          27
++#define PCIE_AFR_FTS_NUM_DEFAULT             32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  
++#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S                16
++#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S             0
++#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */
++#define PCIE_SNR_TS_S                        0
++#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S                       8
++#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S              14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19
++#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S                  28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S          0
++#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12
++
++/* Queue Status Register */
++#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21
++
++/* Applicable to the above three registers */
++enum {
++    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,
++    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/* 
++ * PCIe PDI PHY register definition, suppose all the following 
++ * stuff is confidential. 
++ * XXX, detailed bit definition
++ */
++#define	PCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define	PCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define	PCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define	PCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define	PCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define	PCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define	PCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define	PCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define	PCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define	PCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define	PCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++ 
++#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA  1
++#define PCIE_LEGACY_INTB  2
++#define PCIE_LEGACY_INTC  3
++#define PCIE_LEGACY_INTD  4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#define PCIE_IRQ_LOCK(lock) do {             \
++    unsigned long flags;                     \
++    spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock)                \
++    spin_unlock_irqrestore(&(lock), flags);  \
++} while (0)
++
++#define PCIE_MSG_MSI        0x00000001
++#define PCIE_MSG_ISR        0x00000002
++#define PCIE_MSG_FIXUP      0x00000004
++#define PCIE_MSG_READ_CFG   0x00000008
++#define PCIE_MSG_WRITE_CFG  0x00000010
++#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG        0x00000020
++#define PCIE_MSG_INIT       0x00000040
++#define PCIE_MSG_ERR        0x00000080
++#define PCIE_MSG_PHY        0x00000100
++#define PCIE_MSG_ANY        0x000001ff
++
++#define IFX_PCIE_PORT0      0
++#define IFX_PCIE_PORT1      1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR    2
++#else
++#define IFX_PCIE_CORE_NR    1
++#endif
++
++//#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \
++    if (g_pcie_debug_flag & (_m)) {              \
++        ifx_pcie_debug((_fmt), ##args);          \
++    }                                            \
++} while (0)
++
++#define INLINE 
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...)   \
++    do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++	struct pci_controller   pcic;
++    
++	/* RC specific, per host bus information */
++	u32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++    const unsigned int irq;
++    const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++    const u32 irq_bit;
++    const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++    ifx_pcie_ir_irq_t ir_irq;
++    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/clk.h>
++
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET  38
++#define IFX_REG_R32	ltq_r32
++#define IFX_REG_W32	ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU                                 (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY   (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL  (1)
++#define IFX_PMU1_MODULE_PDI        (4)
++#define IFX_PMU1_MODULE_MSI        (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++}
++
++static inline void pcie_ahb_pmu_setup(void)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "ahb");
++	clk_enable(clk);
++	//ltq_pmu_enable(PMU_AHBM | PMU_AHBS);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg |= IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else 
++    reg |= IFX_RCU_AHB_BE_PCIE_M;
++    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "phy");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "phy");
++	clk_disable(clk);
++	//ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++    u32 reg;
++
++    /* SRAM2PDI endianness control. */
++    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++    /* Config AHB->PCIe and PDI endianness */
++    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "pdi");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
++    reg |= 0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    /* Reset PCIe PHY & Core, bit 22 */
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00400000;
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++    u32 reg;
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg |= 0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++    u32 reg;
++
++    /* Make sure one micro-second delay */
++    udelay(1);
++
++    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++    reg &= ~0x00001000; /* Bit 12 */
++    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++  //  ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++    mdelay(100);
++	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++//    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++	struct clk *clk;
++	clk = clk_get_sys("ltq_pcie", "ctl");
++	clk_enable(clk);
++	clk = clk_get_sys("ltq_pcie", "bus");
++	clk_enable(clk);
++
++	//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL);
++	//ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++	struct clk *clk;
++    pcie_msi_pic_init(pcie_port);
++	clk = clk_get_sys("ltq_pcie", "msi");
++	clk_enable(clk);
++	//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++    u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++    if (pcibios_host_nr() > 1) {
++        tbus_number -= pcibios_1st_host_bus_nr();
++    }
++#endif /* CONFIG_PCI_LANTIQ */
++    return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++	struct pci_dev *dev;
++
++	list_for_each_entry(dev, &bus->devices, bus_list) {
++		if (dev->devfn == devfn)
++			goto out;
++	}
++
++	dev = NULL;
++ out:
++	pci_dev_get(dev);
++	return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++    struct pci_dev *pdev;
++    u32 tvalue = value;
++
++    /* Sanity check */
++    pdev = ifx_pci_get_slot(bus, devfn);
++    if (pdev == NULL) {
++        return tvalue;
++    }
++
++    /* Only care about PCI bridge */
++    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++        return tvalue;
++    }
++
++    if (read) { /* Read hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++        }
++    #endif /* CONFIG_PCI_LANTIQ */
++    }
++    else { /* Write hack */
++    #ifdef CONFIG_PCI_LANTIQ
++        if (pcibios_host_nr() > 1) {
++            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++        }
++    #endif
++    }
++    return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
++
+--- a/drivers/pci/pcie/Kconfig
++++ b/drivers/pci/pcie/Kconfig
+@@ -55,6 +55,7 @@ config PCIEAER_INJECT
+ config PCIE_ECRC
+ 	bool "PCI Express ECRC settings control"
+ 	depends on PCIEAER
++	default n
+ 	help
+ 	  Used to override firmware/bios settings for PCI Express ECRC
+ 	  (transaction layer end-to-end CRC checking).
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1599,6 +1599,8 @@ void pci_walk_bus_locked(struct pci_bus
+ 			 void *userdata);
+ int pci_cfg_space_size(struct pci_dev *dev);
+ unsigned char pci_bus_max_busnr(struct pci_bus *bus);
++int pcibios_host_nr(void);
++int pcibios_1st_host_bus_nr(void);
+ void pci_setup_bridge(struct pci_bus *bus);
+ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
+ 					 unsigned long type);
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1108,6 +1108,12 @@
+ #define PCI_DEVICE_ID_SGI_IOC3		0x0003
+ #define PCI_DEVICE_ID_SGI_LITHIUM	0x1002
+ 
++#define PCI_VENDOR_ID_INFINEON		0x15D1
++#define PCI_DEVICE_ID_INFINEON_DANUBE	0x000F
++#define PCI_DEVICE_ID_INFINEON_PCIE	0x0011
++#define PCI_VENDOR_ID_LANTIQ		0x1BEF
++#define PCI_DEVICE_ID_LANTIQ_PCIE	0x0011
++
+ #define PCI_VENDOR_ID_WINBOND		0x10ad
+ #define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+ #define PCI_DEVICE_ID_WINBOND_83C553	0x0565
diff --git a/target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch b/target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
new file mode 100644
index 0000000000..6b70f8b9a7
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
@@ -0,0 +1,62 @@
+From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 6 May 2024 09:41:42 +0200
+Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
+
+Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
+only switched to the gpiod API, but also inverted / changed the polarity
+of the GPIO.
+
+According to the PCI specification, the RST# pin is an active-low
+signal. However, most of the device trees that have been widely used for
+a long time (mainly in the openWrt project) define this GPIO as
+active-high and the old driver code inverted the signal internally.
+
+Apparently there are actually boards where the reset gpio must be
+operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
+flag for initialization. Instead, we must explicitly set the gpio to
+value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
+may have been set.
+
+In order to remain compatible with all these existing device trees, we
+should therefore keep the logic as it was before the commit.
+
+Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/pci/pci-lantiq.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
+ 		clk_disable(clk_external);
+ 
+ 	/* setup reset gpio used by pci */
+-	reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+-					     GPIOD_OUT_LOW);
++	reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
+ 	error = PTR_ERR_OR_ZERO(reset_gpio);
+ 	if (error) {
+ 		dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
+ 		return error;
+ 	}
+ 	gpiod_set_consumer_name(reset_gpio, "pci_reset");
++	gpiod_direction_output(reset_gpio, 1);
+ 
+ 	/* enable auto-switching between PCI and EBU */
+ 	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
+@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
+ 
+ 	/* toggle reset pin */
+ 	if (reset_gpio) {
+-		gpiod_set_value_cansleep(reset_gpio, 1);
++		gpiod_set_value_cansleep(reset_gpio, 0);
+ 		wmb();
+ 		mdelay(1);
+-		gpiod_set_value_cansleep(reset_gpio, 0);
++		gpiod_set_value_cansleep(reset_gpio, 1);
+ 	}
+ 	return 0;
+ }
diff --git a/target/linux/lantiq/patches-6.6/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-6.6/0004-MIPS-lantiq-add-atm-hack.patch
new file mode 100644
index 0000000000..2e36b41beb
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0004-MIPS-lantiq-add-atm-hack.patch
@@ -0,0 +1,482 @@
+From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++
+ arch/mips/lantiq/irq.c                         |    2 +
+ arch/mips/mm/cache.c                           |    4 +
+ include/uapi/linux/atm.h                       |    6 +
+ net/atm/common.c                               |    6 +
+ net/atm/proc.c                                 |    2 +-
+ 7 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+@@ -0,0 +1,196 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_atm.h
++** PROJECT      : UEIP
++** MODULES      : ATM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global ATM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_ATM_H
++#define IFX_ATM_H
++
++
++
++/*!
++  \defgroup IFX_ATM UEIP Project - ATM driver module
++  \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_ATM_IOCTL IOCTL Commands
++  \ingroup IFX_ATM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_ATM_STRUCT Structures
++  \ingroup IFX_ATM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_atm.h
++  \ingroup IFX_ATM
++  \brief ATM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ATM MIB
++ */
++
++/*!
++  \struct atm_cell_ifEntry_t
++  \brief Structure used for Cell Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */
++	__u32	ifInErrors;         /*!< counter of error ingress cells     */
++	__u32	ifInUnknownProtos;  /*!< counter of unknown ingress cells   */
++	__u32	ifOutErrors;        /*!< counter of error egress cells      */
++} atm_cell_ifEntry_t;
++
++/*!
++  \struct atm_aal5_ifEntry_t
++  \brief Structure used for AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
++ */
++typedef struct {
++	__u32	ifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
++	__u32	ifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
++	__u32	ifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */
++	__u32	ifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */
++	__u32	ifInUcastPkts;      /*!< counter of ingress packets         */
++	__u32	ifOutUcastPkts;     /*!< counter of egress packets          */
++	__u32	ifInErrors;         /*!< counter of error ingress packets   */
++	__u32	ifInDiscards;       /*!< counter of dropped ingress packets */
++	__u32	ifOutErros;         /*!< counter of error egress packets    */
++	__u32	ifOutDiscards;      /*!< counter of dropped egress packets  */
++} atm_aal5_ifEntry_t;
++
++/*!
++  \struct atm_aal5_vcc_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  This structure is a part of structure "atm_aal5_vcc_x_t".
++ */
++typedef struct {
++	__u32	aal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */
++	__u32	aal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet
++	__u32	aal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */
++} atm_aal5_vcc_t;
++
++/*!
++  \struct atm_aal5_vcc_x_t
++  \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++  User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
++ */
++typedef struct {
++	int             vpi;        /*!< VPI of the VCC to get MIB counters */
++	int             vci;        /*!< VCI of the VCC to get MIB counters */
++	atm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */
++} atm_aal5_vcc_x_t;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_ATM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief ATM IOCTL Magic Number
++ */
++#define PPE_ATM_IOC_MAGIC       'o'
++/*!
++  \brief ATM IOCTL Command - Get Cell Level MIB Counters
++
++   This command is obsolete. User can get cell level MIB from DSL API.
++   This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
++
++   Get AAL5 packet counters.
++   This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
++/*!
++  \brief ATM IOCTL Command - Get Per PVC MIB Counters
++
++   Get AAL5 packet counters for each PVC.
++   This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
++ */
++#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
++/*!
++  \brief Total Number of ATM IOCTL Commands
++ */
++#define PPE_ATM_IOC_MAXNR       3
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_ATM_H
++
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+@@ -0,0 +1,203 @@
++/******************************************************************************
++**
++** FILE NAME    : ifx_ptm.h
++** PROJECT      : UEIP
++** MODULES      : PTM
++**
++** DATE         : 17 Jun 2009
++** AUTHOR       : Xu Liang
++** DESCRIPTION  : Global PTM driver header file
++** COPYRIGHT    :       Copyright (c) 2006
++**                      Infineon Technologies AG
++**                      Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++**    This program is free software; you can redistribute it and/or modify
++**    it under the terms of the GNU General Public License as published by
++**    the Free Software Foundation; either version 2 of the License, or
++**    (at your option) any later version.
++**
++** HISTORY
++** $Date        $Author         $Comment
++** 07 JUL 2009  Xu Liang        Init Version
++*******************************************************************************/
++
++#ifndef IFX_PTM_H
++#define IFX_PTM_H
++
++
++
++/*!
++  \defgroup IFX_PTM UEIP Project - PTM driver module
++  \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++  \defgroup IFX_PTM_IOCTL IOCTL Commands
++  \ingroup IFX_PTM
++  \brief IOCTL Commands used by user application.
++ */
++
++/*!
++  \defgroup IFX_PTM_STRUCT Structures
++  \ingroup IFX_PTM
++  \brief Structures used by user application.
++ */
++
++/*!
++  \file ifx_ptm.h
++  \ingroup IFX_PTM
++  \brief PTM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++
++
++/*
++ * ####################################
++ *                IOCTL
++ * ####################################
++ */
++
++/*!
++  \addtogroup IFX_PTM_IOCTL
++ */
++/*@{*/
++
++/*
++ *  ioctl Command
++ */
++/*!
++  \brief PTM IOCTL Command - Get codeword MIB counters.
++
++  This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
++ */
++#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1
++/*!
++  \brief PTM IOCTL Command - Get packet MIB counters.
++
++  This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
++ */
++#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2
++/*!
++  \brief PTM IOCTL Command - Get firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3
++/*!
++  \brief PTM IOCTL Command - Set firmware configuration (CRC).
++
++  This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4
++/*!
++  \brief PTM IOCTL Command - Program priority value to TX queue mapping.
++
++  This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
++ */
++#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14
++
++/*@}*/
++
++
++/*!
++  \addtogroup IFX_PTM_STRUCT
++ */
++/*@{*/
++
++/*
++ *  ioctl Data Type
++ */
++
++/*!
++  \typedef PTM_CW_IF_ENTRY_T
++  \brief Wrapping of structure "ptm_cw_ifEntry_t".
++ */
++/*!
++  \struct ptm_cw_ifEntry_t
++  \brief Structure used for CodeWord level MIB counters.
++ */
++typedef struct ptm_cw_ifEntry_t {
++    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */
++    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */
++    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */
++    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */
++    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */
++} PTM_CW_IF_ENTRY_T;
++
++/*!
++  \typedef PTM_FRAME_MIB_T
++  \brief Wrapping of structure "ptm_frame_mib_t".
++ */
++/*!
++  \struct ptm_frame_mib_t
++  \brief Structure used for packet level MIB counters.
++ */
++typedef struct ptm_frame_mib_t {
++    uint32_t    RxCorrect;      /*!< output, number of ingress packet */
++    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */
++    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */
++    uint32_t    TxSend;         /*!< output, number of egress packet */
++} PTM_FRAME_MIB_T;
++
++/*!
++  \typedef IFX_PTM_CFG_T
++  \brief Wrapping of structure "ptm_cfg_t".
++ */
++/*!
++  \struct ptm_cfg_t
++  \brief Structure used for ETH/TC CRC configuration.
++ */
++typedef struct ptm_cfg_t {
++    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */
++    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */
++    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */
++    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */
++    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */
++    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */
++    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */
++} IFX_PTM_CFG_T;
++
++/*!
++  \typedef IFX_PTM_PRIO_Q_MAP_T
++  \brief Wrapping of structure "ppe_prio_q_map".
++ */
++/*!
++  \struct ppe_prio_q_map
++  \brief Structure used for Priority Value to TX Queue mapping.
++ */
++typedef struct ppe_prio_q_map {
++    int             pkt_prio;
++    int             qid;
++    int             vpi;    //  ignored in eth interface
++    int             vci;    //  ignored in eth interface
++} IFX_PTM_PRIO_Q_MAP_T;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ *                 API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++    unsigned int    port_num;
++    unsigned int    tx_link_rate[2];
++};
++#endif
++
++
++
++#endif  //  IFX_PTM_H
++
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -13,6 +13,7 @@
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/module.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d)
+ 	}
+ 	raw_spin_unlock_irqrestore(&ltq_icu_lock, flags);
+ }
++EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+ 
+ void ltq_mask_and_ack_irq(struct irq_data *d)
+ {
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -80,6 +80,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+ 
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_wback);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+ 
+ /*
+--- a/include/uapi/linux/atm.h
++++ b/include/uapi/linux/atm.h
+@@ -131,8 +131,14 @@
+ #define ATM_ABR		4
+ #define ATM_ANYCLASS	5		/* compatible with everything */
+ 
++#define ATM_VBR_NRT     ATM_VBR
++#define ATM_VBR_RT      6
++#define ATM_UBR_PLUS    7
++#define ATM_GFR         8
++
+ #define ATM_MAX_PCR	-1		/* maximum available PCR */
+ 
++
+ struct atm_trafprm {
+ 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
+ 	int		max_pcr;	/* maximum PCR in cells per second */
+--- a/net/atm/proc.c
++++ b/net/atm/proc.c
+@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ 	static const char *const class_name[] = {
+-		"off", "UBR", "CBR", "VBR", "ABR"};
++		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ 	static const char *const aal_name[] = {
+ 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
+ 		"???",	"5",	"???",	"???",	/*  4- 7 */
diff --git a/target/linux/lantiq/patches-6.6/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-6.6/0008-MIPS-lantiq-backport-old-timer-code.patch
new file mode 100644
index 0000000000..3e6c267685
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0008-MIPS-lantiq-backport-old-timer-code.patch
@@ -0,0 +1,1076 @@
+From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:30:56 +0200
+Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
+ arch/mips/lantiq/xway/Makefile                   |    2 +-
+ arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
+ 3 files changed, 1001 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+ create mode 100644 arch/mips/lantiq/xway/timer.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+@@ -0,0 +1,155 @@
++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++
++
++/******************************************************************************
++       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
++
++                               No Warranty
++   Because the program is licensed free of charge, there is no warranty for
++   the program, to the extent permitted by applicable law.  Except when
++   otherwise stated in writing the copyright holders and/or other parties
++   provide the program "as is" without warranty of any kind, either
++   expressed or implied, including, but not limited to, the implied
++   warranties of merchantability and fitness for a particular purpose. The
++   entire risk as to the quality and performance of the program is with
++   you.  should the program prove defective, you assume the cost of all
++   necessary servicing, repair or correction.
++
++   In no event unless required by applicable law or agreed to in writing
++   will any copyright holder, or any other party who may modify and/or
++   redistribute the program as permitted above, be liable to you for
++   damages, including any general, special, incidental or consequential
++   damages arising out of the use or inability to use the program
++   (including but not limited to loss of data or data being rendered
++   inaccurate or losses sustained by you or third parties or a failure of
++   the program to operate with any other programs), even if such holder or
++   other party has been advised of the possibility of such damages.
++******************************************************************************/
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*
++ *  Available Timer/Counter Index
++ */
++#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
++#define TIMER_ANY                       0x00
++#define TIMER1A                         TIMER(1, 0)
++#define TIMER1B                         TIMER(1, 1)
++#define TIMER2A                         TIMER(2, 0)
++#define TIMER2B                         TIMER(2, 1)
++#define TIMER3A                         TIMER(3, 0)
++#define TIMER3B                         TIMER(3, 1)
++
++/*
++ *  Flag of Timer/Counter
++ *  These flags specify the way in which timer is configured.
++ */
++/*  Bit size of timer/counter.                      */
++#define TIMER_FLAG_16BIT                0x0000
++#define TIMER_FLAG_32BIT                0x0001
++/*  Switch between timer and counter.               */
++#define TIMER_FLAG_TIMER                0x0000
++#define TIMER_FLAG_COUNTER              0x0002
++/*  Stop or continue when overflowing/underflowing. */
++#define TIMER_FLAG_ONCE                 0x0000
++#define TIMER_FLAG_CYCLIC               0x0004
++/*  Count up or counter down.                       */
++#define TIMER_FLAG_UP                   0x0000
++#define TIMER_FLAG_DOWN                 0x0008
++/*  Count on specific level or edge.                */
++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
++#define TIMER_FLAG_RISE_EDGE            0x0010
++#define TIMER_FLAG_FALL_EDGE            0x0020
++#define TIMER_FLAG_ANY_EDGE             0x0030
++/*  Signal is syncronous to module clock or not.    */
++#define TIMER_FLAG_UNSYNC               0x0000
++#define TIMER_FLAG_SYNC                 0x0080
++/*  Different interrupt handle type.                */
++#define TIMER_FLAG_NO_HANDLE            0x0000
++#if defined(__KERNEL__)
++    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
++#endif  //  defined(__KERNEL__)
++#define TIMER_FLAG_SIGNAL               0x0300
++/*  Internal clock source or external clock source  */
++#define TIMER_FLAG_INT_SRC              0x0000
++#define TIMER_FLAG_EXT_SRC              0x1000
++
++
++/*
++ *  ioctl Command
++ */
++#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
++#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
++#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
++#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
++#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
++#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
++#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
++#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
++
++/*
++ *  Data Type Used to Call ioctl
++ */
++struct gptu_ioctl_param {
++    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
++                                                 *  timer/counter. If it's zero, a timer/counter would  *
++                                                 *  be dynamically allocated and ID would be stored in  *
++                                                 *  this field.                                         *
++                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
++                                                 *  ignored.                                            *
++                                                 *  In other command, this field is ID of timer/counter *
++                                                 *  allocated.                                          */
++    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
++                                                 *  specify how to configure timer/counter.             *
++                                                 *  In command GPTU_START_TIMER, zero indicate start    *
++                                                 *  and non-zero indicate resume timer/counter.         *
++                                                 *  In other command, this field is ignored.            */
++    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
++                                                 *  init/reload value.                                  *
++                                                 *  In command GPTU_SET_TIMER, this field contains      *
++                                                 *  frequency (0.001Hz) of timer.                       *
++                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
++                                                 *  value would be stored in this field.                *
++                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
++                                                 *  contains frequency wanted, and after calculation,   *
++                                                 *  divider would be stored in this field to overwrite  *
++                                                 *  the frequency.                                      *
++                                                 *  In other command, this field is ignored.            */
++    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains process  *
++                                                 *  ID to which signal would be sent.                   *
++                                                 *  In other command, this field is ignored.            */
++    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains signal   *
++                                                 *  number which would be sent.                         *
++                                                 *  In other command, this field is ignored.            */
++};
++
++/*
++ * ####################################
++ *              Data Type
++ * ####################################
++ */
++typedef void (*timer_callback)(unsigned long arg);
++
++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
++extern int lq_free_timer(unsigned int);
++extern int lq_start_timer(unsigned int, int);
++extern int lq_stop_timer(unsigned int);
++extern int lq_reset_counter_flags(u32 timer, u32 flags);
++extern int lq_get_count_value(unsigned int, unsigned long *);
++extern u32 lq_cal_divider(unsigned long);
++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
++extern int lq_set_counter(unsigned int timer, unsigned int flag,
++	u32 reload, unsigned long arg1, unsigned long arg2);
++
++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,4 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o
++
++ifdef CONFIG_SOC_AMAZON_SE
++obj-y += gptu.o
++else
++obj-y += timer.o
++endif
+ 
+ obj-y += vmmc.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/timer.c
+@@ -0,0 +1,887 @@
++#ifndef CONFIG_SOC_AMAZON_SE
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/init.h>
++#include <linux/uaccess.h>
++#include <linux/unistd.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/sched/signal.h>
++
++#include <linux/of_platform.h>
++
++#include <asm/irq.h>
++#include <asm/div64.h>
++#include "../clk.h"
++
++#include <lantiq_soc.h>
++#include <lantiq_irq.h>
++#include <lantiq_timer.h>
++
++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS	6
++
++#ifdef TIMER1A
++#define FIRST_TIMER			TIMER1A
++#else
++#define FIRST_TIMER			2
++#endif
++
++/*
++ *  GPTC divider is set or not.
++ */
++#define GPTU_CLC_RMC_IS_SET		0
++
++/*
++ *  Timer Interrupt (IRQ)
++ */
++/*  Must be adjusted when ICU driver is available */
++#define TIMER_INTERRUPT			(INT_NUM_IM3_IRL0 + 22)
++
++/*
++ *  Bits Operation
++ */
++#define GET_BITS(x, msb, lsb)		\
++	(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
++#define SET_BITS(x, msb, lsb, value)	\
++	(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
++	(((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
++
++/*
++ *  GPTU Register Mapping
++ */
++#define LQ_GPTU			(KSEG1 + 0x1E100A00)
++#define LQ_GPTU_CLC		((volatile u32 *)(LQ_GPTU + 0x0000))
++#define LQ_GPTU_ID			((volatile u32 *)(LQ_GPTU + 0x0008))
++#define LQ_GPTU_CON(n, X)		((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_RUN(n, X)		((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_RELOAD(n, X)	((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_COUNT(n, X)	((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))	/* X must be either A or B */
++#define LQ_GPTU_IRNEN		((volatile u32 *)(LQ_GPTU + 0x00F4))
++#define LQ_GPTU_IRNICR		((volatile u32 *)(LQ_GPTU + 0x00F8))
++#define LQ_GPTU_IRNCR		((volatile u32 *)(LQ_GPTU + 0x00FC))
++
++/*
++ *  Clock Control Register
++ */
++#define GPTU_CLC_SMC			GET_BITS(*LQ_GPTU_CLC, 23, 16)
++#define GPTU_CLC_RMC			GET_BITS(*LQ_GPTU_CLC, 15, 8)
++#define GPTU_CLC_FSOE			(*LQ_GPTU_CLC & (1 << 5))
++#define GPTU_CLC_EDIS			(*LQ_GPTU_CLC & (1 << 3))
++#define GPTU_CLC_SPEN			(*LQ_GPTU_CLC & (1 << 2))
++#define GPTU_CLC_DISS			(*LQ_GPTU_CLC & (1 << 1))
++#define GPTU_CLC_DISR			(*LQ_GPTU_CLC & (1 << 0))
++
++#define GPTU_CLC_SMC_SET(value)		SET_BITS(0, 23, 16, (value))
++#define GPTU_CLC_RMC_SET(value)		SET_BITS(0, 15, 8, (value))
++#define GPTU_CLC_FSOE_SET(value)	((value) ? (1 << 5) : 0)
++#define GPTU_CLC_SBWE_SET(value)	((value) ? (1 << 4) : 0)
++#define GPTU_CLC_EDIS_SET(value)	((value) ? (1 << 3) : 0)
++#define GPTU_CLC_SPEN_SET(value)	((value) ? (1 << 2) : 0)
++#define GPTU_CLC_DISR_SET(value)	((value) ? (1 << 0) : 0)
++
++/*
++ *  ID Register
++ */
++#define GPTU_ID_ID			GET_BITS(*LQ_GPTU_ID, 15, 8)
++#define GPTU_ID_CFG			GET_BITS(*LQ_GPTU_ID, 7, 5)
++#define GPTU_ID_REV			GET_BITS(*LQ_GPTU_ID, 4, 0)
++
++/*
++ *  Control Register of Timer/Counter nX
++ *    n is the index of block (1 based index)
++ *    X is either A or B
++ */
++#define GPTU_CON_SRC_EG(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 10))
++#define GPTU_CON_SRC_EXT(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 9))
++#define GPTU_CON_SYNC(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 8))
++#define GPTU_CON_EDGE(n, X)		GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
++#define GPTU_CON_INV(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 5))
++#define GPTU_CON_EXT(n, X)		(*LQ_GPTU_CON(n, A) & (1 << 4))	/* Timer/Counter B does not have this bit */
++#define GPTU_CON_STP(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 3))
++#define GPTU_CON_CNT(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 2))
++#define GPTU_CON_DIR(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 1))
++#define GPTU_CON_EN(n, X)		(*LQ_GPTU_CON(n, X) & (1 << 0))
++
++#define GPTU_CON_SRC_EG_SET(value)	((value) ? 0 : (1 << 10))
++#define GPTU_CON_SRC_EXT_SET(value)	((value) ? (1 << 9) : 0)
++#define GPTU_CON_SYNC_SET(value)	((value) ? (1 << 8) : 0)
++#define GPTU_CON_EDGE_SET(value)	SET_BITS(0, 7, 6, (value))
++#define GPTU_CON_INV_SET(value)		((value) ? (1 << 5) : 0)
++#define GPTU_CON_EXT_SET(value)		((value) ? (1 << 4) : 0)
++#define GPTU_CON_STP_SET(value)		((value) ? (1 << 3) : 0)
++#define GPTU_CON_CNT_SET(value)		((value) ? (1 << 2) : 0)
++#define GPTU_CON_DIR_SET(value)		((value) ? (1 << 1) : 0)
++
++#define GPTU_RUN_RL_SET(value)		((value) ? (1 << 2) : 0)
++#define GPTU_RUN_CEN_SET(value)		((value) ? (1 << 1) : 0)
++#define GPTU_RUN_SEN_SET(value)		((value) ? (1 << 0) : 0)
++
++#define GPTU_IRNEN_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++#define GPTU_IRNCR_TC_SET(n, X, value)	((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++
++#define TIMER_FLAG_MASK_SIZE(x)		(x & 0x0001)
++#define TIMER_FLAG_MASK_TYPE(x)		(x & 0x0002)
++#define TIMER_FLAG_MASK_STOP(x)		(x & 0x0004)
++#define TIMER_FLAG_MASK_DIR(x)		(x & 0x0008)
++#define TIMER_FLAG_NONE_EDGE		0x0000
++#define TIMER_FLAG_MASK_EDGE(x)		(x & 0x0030)
++#define TIMER_FLAG_REAL			0x0000
++#define TIMER_FLAG_INVERT		0x0040
++#define TIMER_FLAG_MASK_INVERT(x)	(x & 0x0040)
++#define TIMER_FLAG_MASK_TRIGGER(x)	(x & 0x0070)
++#define TIMER_FLAG_MASK_SYNC(x)		(x & 0x0080)
++#define TIMER_FLAG_CALLBACK_IN_HB	0x0200
++#define TIMER_FLAG_MASK_HANDLE(x)	(x & 0x0300)
++#define TIMER_FLAG_MASK_SRC(x)		(x & 0x1000)
++
++struct timer_dev_timer {
++	unsigned int f_irq_on;
++	unsigned int irq;
++	unsigned int flag;
++	unsigned long arg1;
++	unsigned long arg2;
++};
++
++struct timer_dev {
++	struct mutex gptu_mutex;
++	unsigned int number_of_timers;
++	unsigned int occupation;
++	unsigned int f_gptu_on;
++	struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
++};
++
++
++unsigned int ltq_get_fpi_bus_clock(int fpi) {
++	struct clk *clk = clk_get_fpi();
++	return clk_get_rate(clk);
++}
++
++
++static long gptu_ioctl(struct file *, unsigned int, unsigned long);
++static int gptu_open(struct inode *, struct file *);
++static int gptu_release(struct inode *, struct file *);
++
++static struct file_operations gptu_fops = {
++	.owner = THIS_MODULE,
++	.unlocked_ioctl = gptu_ioctl,
++	.open = gptu_open,
++	.release = gptu_release
++};
++
++static struct miscdevice gptu_miscdev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "gptu",
++	.fops = &gptu_fops,
++};
++
++static struct timer_dev timer_dev;
++
++static irqreturn_t timer_irq_handler(int irq, void *p)
++{
++	unsigned int timer;
++	unsigned int flag;
++	struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
++
++	timer = irq - TIMER_INTERRUPT;
++	if (timer < timer_dev.number_of_timers
++		&& dev_timer == &timer_dev.timer[timer]) {
++		/*  Clear interrupt.    */
++		ltq_w32(1 << timer, LQ_GPTU_IRNCR);
++
++		/*  Call user hanler or signal. */
++		flag = dev_timer->flag;
++		if (!(timer & 0x01)
++			|| TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++			/* 16-bit timer or timer A of 32-bit timer  */
++			switch (TIMER_FLAG_MASK_HANDLE(flag)) {
++			case TIMER_FLAG_CALLBACK_IN_IRQ:
++			case TIMER_FLAG_CALLBACK_IN_HB:
++				if (dev_timer->arg1)
++					(*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
++				break;
++			case TIMER_FLAG_SIGNAL:
++				send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
++				break;
++			}
++		}
++	}
++	return IRQ_HANDLED;
++}
++
++static inline void lq_enable_gptu(void)
++{
++	struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++	clk_enable(clk);
++
++	//ltq_pmu_enable(PMU_GPT);
++
++	/*  Set divider as 1, disable write protection for SPEN, enable module. */
++	*LQ_GPTU_CLC =
++		GPTU_CLC_SMC_SET(0x00) |
++		GPTU_CLC_RMC_SET(0x01) |
++		GPTU_CLC_FSOE_SET(0) |
++		GPTU_CLC_SBWE_SET(1) |
++		GPTU_CLC_EDIS_SET(0) |
++		GPTU_CLC_SPEN_SET(0) |
++		GPTU_CLC_DISR_SET(0);
++}
++
++static inline void lq_disable_gptu(void)
++{
++	struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++	ltq_w32(0x00, LQ_GPTU_IRNEN);
++	ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++	/*  Set divider as 0, enable write protection for SPEN, disable module. */
++	*LQ_GPTU_CLC =
++		GPTU_CLC_SMC_SET(0x00) |
++		GPTU_CLC_RMC_SET(0x00) |
++		GPTU_CLC_FSOE_SET(0) |
++		GPTU_CLC_SBWE_SET(0) |
++		GPTU_CLC_EDIS_SET(0) |
++		GPTU_CLC_SPEN_SET(0) |
++		GPTU_CLC_DISR_SET(1);
++
++	clk_enable(clk);
++}
++
++int lq_request_timer(unsigned int timer, unsigned int flag,
++	unsigned long value, unsigned long arg1, unsigned long arg2)
++{
++	int ret = 0;
++	unsigned int con_reg, irnen_reg;
++	int n, X;
++
++	if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
++		timer, flag, value);
++
++	if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
++		value &= 0xFFFF;
++	else
++		timer &= ~0x01;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	/*
++	 *  Allocate timer.
++	 */
++	if (timer < FIRST_TIMER) {
++		unsigned int mask;
++		unsigned int shift;
++		/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
++		unsigned int offset = TIMER2A;
++
++		/*
++		 *  Pick up a free timer.
++		 */
++		if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++			mask = 1 << offset;
++			shift = 1;
++		} else {
++			mask = 3 << offset;
++			shift = 2;
++		}
++		for (timer = offset;
++		     timer < offset + timer_dev.number_of_timers;
++		     timer += shift, mask <<= shift)
++			if (!(timer_dev.occupation & mask)) {
++				timer_dev.occupation |= mask;
++				break;
++			}
++		if (timer >= offset + timer_dev.number_of_timers) {
++			printk("failed![%d]\n", __LINE__);
++			mutex_unlock(&timer_dev.gptu_mutex);
++			return -EINVAL;
++		} else
++			ret = timer;
++	} else {
++		register unsigned int mask;
++
++		/*
++		 *  Check if the requested timer is free.
++		 */
++		mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++		if ((timer_dev.occupation & mask)) {
++			printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
++				__LINE__, mask, timer_dev.occupation);
++			mutex_unlock(&timer_dev.gptu_mutex);
++			return -EBUSY;
++		} else {
++			timer_dev.occupation |= mask;
++			ret = 0;
++		}
++	}
++
++	/*
++	 *  Prepare control register value.
++	 */
++	switch (TIMER_FLAG_MASK_EDGE(flag)) {
++	default:
++	case TIMER_FLAG_NONE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x00);
++		break;
++	case TIMER_FLAG_RISE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x01);
++		break;
++	case TIMER_FLAG_FALL_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x02);
++		break;
++	case TIMER_FLAG_ANY_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x03);
++		break;
++	}
++	if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
++		con_reg |=
++			TIMER_FLAG_MASK_SRC(flag) ==
++			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
++			GPTU_CON_SRC_EXT_SET(0);
++	else
++		con_reg |=
++			TIMER_FLAG_MASK_SRC(flag) ==
++			TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
++			GPTU_CON_SRC_EG_SET(0);
++	con_reg |=
++		TIMER_FLAG_MASK_SYNC(flag) ==
++		TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
++		GPTU_CON_SYNC_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_INVERT(flag) ==
++		TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_SIZE(flag) ==
++		TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
++		GPTU_CON_EXT_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_STOP(flag) ==
++		TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++	con_reg |=
++		TIMER_FLAG_MASK_TYPE(flag) ==
++		TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
++		GPTU_CON_CNT_SET(1);
++	con_reg |=
++		TIMER_FLAG_MASK_DIR(flag) ==
++		TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++	/*
++	 *  Fill up running data.
++	 */
++	timer_dev.timer[timer - FIRST_TIMER].flag = flag;
++	timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
++	timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
++
++	/*
++	 *  Enable GPTU module.
++	 */
++	if (!timer_dev.f_gptu_on) {
++		lq_enable_gptu();
++		timer_dev.f_gptu_on = 1;
++	}
++
++	/*
++	 *  Enable IRQ.
++	 */
++	if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
++		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
++			timer_dev.timer[timer - FIRST_TIMER].arg1 =
++				(unsigned long) find_task_by_vpid((int) arg1);
++
++		irnen_reg = 1 << (timer - FIRST_TIMER);
++
++		if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
++		    || (TIMER_FLAG_MASK_HANDLE(flag) ==
++			TIMER_FLAG_CALLBACK_IN_IRQ
++			&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {
++			enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++			timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
++		}
++	} else
++		irnen_reg = 0;
++
++	/*
++	 *  Write config register, reload value and enable interrupt.
++	 */
++	n = timer >> 1;
++	X = timer & 0x01;
++	*LQ_GPTU_CON(n, X) = con_reg;
++	*LQ_GPTU_RELOAD(n, X) = value;
++	/* printk("reload value = %d\n", (u32)value); */
++	*LQ_GPTU_IRNEN |= irnen_reg;
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++	printk("successful!\n");
++	return ret;
++}
++EXPORT_SYMBOL(lq_request_timer);
++
++int lq_free_timer(unsigned int timer)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	if (GPTU_CON_EN(n, X))
++		*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++	*LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
++	*LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
++
++	if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
++		disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++		timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
++	}
++
++	timer_dev.occupation &= ~mask;
++	if (!timer_dev.occupation && timer_dev.f_gptu_on) {
++		lq_disable_gptu();
++		timer_dev.f_gptu_on = 0;
++	}
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_free_timer);
++
++int lq_start_timer(unsigned int timer, int is_resume)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) ==
++	TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
++
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_start_timer);
++
++int lq_stop_timer(unsigned int timer)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER
++	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_stop_timer);
++
++int lq_reset_counter_flags(u32 timer, u32 flags)
++{
++	unsigned int oflag;
++	unsigned int mask, con_reg;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	switch (TIMER_FLAG_MASK_EDGE(flags)) {
++	default:
++	case TIMER_FLAG_NONE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x00);
++		break;
++	case TIMER_FLAG_RISE_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x01);
++		break;
++	case TIMER_FLAG_FALL_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x02);
++		break;
++	case TIMER_FLAG_ANY_EDGE:
++		con_reg = GPTU_CON_EDGE_SET(0x03);
++		break;
++	}
++	if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
++		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
++	else
++		con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
++	con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
++	con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++	con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
++	con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++	con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
++	con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++	timer_dev.timer[timer - FIRST_TIMER].flag = flags;
++	if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
++		timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*LQ_GPTU_CON(n, X) = con_reg;
++	smp_wmb();
++	mutex_unlock(&timer_dev.gptu_mutex);
++	return 0;
++}
++EXPORT_SYMBOL(lq_reset_counter_flags);
++
++int lq_get_count_value(unsigned int timer, unsigned long *value)
++{
++	unsigned int flag;
++	unsigned int mask;
++	int n, X;
++
++	if (!timer_dev.f_gptu_on)
++		return -EINVAL;
++
++	if (timer < FIRST_TIMER
++	    || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++		return -EINVAL;
++
++	mutex_lock(&timer_dev.gptu_mutex);
++
++	flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++	if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++		timer &= ~0x01;
++
++	mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++	if (((timer_dev.occupation & mask) ^ mask)) {
++		mutex_unlock(&timer_dev.gptu_mutex);
++		return -EINVAL;
++	}
++
++	n = timer >> 1;
++	X = timer & 0x01;
++
++	*value = *LQ_GPTU_COUNT(n, X);
++
++
++	mutex_unlock(&timer_dev.gptu_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL(lq_get_count_value);
++
++u32 lq_cal_divider(unsigned long freq)
++{
++	u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
++	u32 clock_divider = 1;
++	module_freq = fpi * 1000;
++	do_div(module_freq, clock_divider * freq);
++	return module_freq;
++}
++EXPORT_SYMBOL(lq_cal_divider);
++
++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
++	int is_ext_src, unsigned int handle_flag, unsigned long arg1,
++	unsigned long arg2)
++{
++	unsigned long divider;
++	unsigned int flag;
++
++	divider = lq_cal_divider(freq);
++	if (divider == 0)
++		return -EINVAL;
++	flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
++		| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
++		| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
++		| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
++		| TIMER_FLAG_MASK_HANDLE(handle_flag);
++
++	printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
++		timer, freq, divider);
++	return lq_request_timer(timer, flag, divider, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_timer);
++
++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
++	unsigned long arg1, unsigned long arg2)
++{
++	printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
++	return lq_request_timer(timer, flag, reload, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_counter);
++
++static long gptu_ioctl(struct file *file, unsigned int cmd,
++	unsigned long arg)
++{
++	int ret;
++	struct gptu_ioctl_param param;
++
++	if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param)))
++		return -EFAULT;
++	if (copy_from_user(&param, (void __user *)arg, sizeof(param)))
++		return -EFAULT;
++
++	if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
++	       || GPTU_SET_COUNTER) && param.timer < 2)
++	     || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
++	    && !access_ok((void __user *)arg,
++			   sizeof(struct gptu_ioctl_param)))
++		return -EFAULT;
++
++	switch (cmd) {
++	case GPTU_REQUEST_TIMER:
++		ret = lq_request_timer(param.timer, param.flag, param.value,
++				     (unsigned long) param.pid,
++				     (unsigned long) param.sig);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	case GPTU_FREE_TIMER:
++		ret = lq_free_timer(param.timer);
++		break;
++	case GPTU_START_TIMER:
++		ret = lq_start_timer(param.timer, param.flag);
++		break;
++	case GPTU_STOP_TIMER:
++		ret = lq_stop_timer(param.timer);
++		break;
++	case GPTU_GET_COUNT_VALUE:
++		ret = lq_get_count_value(param.timer, &param.value);
++		if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)->
++		    value, &param.value,sizeof(param.value)))
++			ret = -EFAULT;
++		break;
++	case GPTU_CALCULATE_DIVIDER:
++		param.value = lq_cal_divider(param.value);
++		if (param.value == 0)
++			ret = -EINVAL;
++		else if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++				      value, &param.value,
++				      sizeof(param.value)))
++			ret = -EFAULT;
++		else
++			ret = 0;
++		break;
++	case GPTU_SET_TIMER:
++		ret = lq_set_timer(param.timer, param.value,
++				 TIMER_FLAG_MASK_STOP(param.flag) !=
++				 TIMER_FLAG_ONCE ? 1 : 0,
++				 TIMER_FLAG_MASK_SRC(param.flag) ==
++				 TIMER_FLAG_EXT_SRC ? 1 : 0,
++				 TIMER_FLAG_MASK_HANDLE(param.flag) ==
++				 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
++				 TIMER_FLAG_NO_HANDLE,
++				 (unsigned long) param.pid,
++				 (unsigned long) param.sig);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	case GPTU_SET_COUNTER:
++		lq_set_counter(param.timer, param.flag, param.value, 0, 0);
++		if (ret > 0) {
++			if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++					 timer, &ret, sizeof(&ret)))
++				ret = -EFAULT;
++			else
++				ret = 0;
++		}
++		break;
++	default:
++		ret = -ENOTTY;
++	}
++
++	return ret;
++}
++
++static int gptu_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int gptu_release(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int gptu_probe(struct platform_device *pdev)
++{
++	int ret;
++	int i;
++
++	ltq_w32(0, LQ_GPTU_IRNEN);
++	ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++	memset(&timer_dev, 0, sizeof(timer_dev));
++	mutex_init(&timer_dev.gptu_mutex);
++
++	lq_enable_gptu();
++	timer_dev.number_of_timers = GPTU_ID_CFG * 2;
++	lq_disable_gptu();
++	if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
++		timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
++	printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
++
++	ret = misc_register(&gptu_miscdev);
++	if (ret) {
++		printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
++		return ret;
++	} else {
++		printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
++	}
++
++	for (i = 0; i < timer_dev.number_of_timers; i++) {
++		int irq = platform_get_irq(pdev, i);
++		if (irq < 0) {
++			printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++			misc_deregister(&gptu_miscdev);
++			return irq;
++		}
++
++		ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
++		if (ret) {
++			printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
++			for (i--; i >= 0; i--)
++				free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++			misc_deregister(&gptu_miscdev);
++			return ret;
++		} else {
++			timer_dev.timer[i].irq = irq;
++			disable_irq(timer_dev.timer[i].irq);
++			printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
++		}
++	}
++
++	return 0;
++}
++
++static const struct of_device_id gptu_match[] = {
++	{ .compatible = "lantiq,gptu-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, gptu_match);
++
++static struct platform_driver gptu_driver = {
++	.probe = gptu_probe,
++	.driver = {
++		.name = "gptu-xway",
++		.owner = THIS_MODULE,
++		.of_match_table = gptu_match,
++	},
++};
++
++int __init lq_gptu_init(void)
++{
++	int ret = platform_driver_register(&gptu_driver);
++
++	if (ret)
++		pr_info("gptu: Error registering platform driver\n");
++	return ret;
++}
++
++void __exit lq_gptu_exit(void)
++{
++	unsigned int i;
++
++	for (i = 0; i < timer_dev.number_of_timers; i++) {
++		if (timer_dev.timer[i].f_irq_on)
++			disable_irq(timer_dev.timer[i].irq);
++		free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++	}
++	lq_disable_gptu();
++	misc_deregister(&gptu_miscdev);
++}
++
++module_init(lq_gptu_init);
++module_exit(lq_gptu_exit);
++
++#endif
diff --git a/target/linux/lantiq/patches-6.6/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-6.6/0018-MTD-nand-lots-of-xrx200-fixes.patch
new file mode 100644
index 0000000000..90af62364a
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0018-MTD-nand-lots-of-xrx200-fixes.patch
@@ -0,0 +1,121 @@
+From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 23:12:15 +0200
+Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/raw/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -62,6 +62,24 @@
+ #define NAND_CON_CSMUX		(1 << 1)
+ #define NAND_CON_NANDM		1
+ 
++#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
++#define PCI_CR_PR_OFFSET	    (KSEG1+0x1E105400)
++#define PCI_CR_PC_ARB		    (PCI_CR_PR_OFFSET + 0x0080)
++
++/*
++ * req_mask provides a mechanism to prevent interference between
++ * nand and pci (probably only relevant for the BT Home Hub 2B).
++ * Setting it causes the corresponding pci req pins to be masked
++ * during nand access, and also moves ebu locking from the read/write
++ * functions to the chip select function to ensure that the whole
++ * operation runs with interrupts disabled.
++ * In addition it switches on some extra waiting in xway_cmd_ctrl().
++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
++ * which in turn seems to be necessary for the nor chip to be recognised
++ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
++ */
++static __be32 req_mask = 0;
++
+ struct xway_nand_data {
+ 	struct nand_controller	controller;
+ 	struct nand_chip	chip;
+@@ -93,10 +111,22 @@ static void xway_select_chip(struct nand
+ 	case -1:
+ 		ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
++
++		if (req_mask) {
++			/* Unmask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
++		}
++
+ 		spin_unlock_irqrestore(&ebu_lock, data->csflags);
+ 		break;
+ 	case 0:
+ 		spin_lock_irqsave(&ebu_lock, data->csflags);
++
++		if (req_mask) {
++			/* Mask all external PCI request */
++			DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
++		}
++
+ 		ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
+ 		ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
+ 		break;
+@@ -109,6 +139,11 @@ static void xway_cmd_ctrl(struct nand_ch
+ {
+ 	struct mtd_info *mtd = nand_to_mtd(chip);
+ 
++	if (req_mask) {
++		if (cmd != NAND_CMD_STATUS)
++			ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
++	}
++
+ 	if (cmd == NAND_CMD_NONE)
+ 		return;
+ 
+@@ -119,6 +154,24 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ 	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ 		;
++
++	if (req_mask) {
++	       /*
++		* program and erase have their own busy handlers
++		* status and sequential in needs no delay
++		*/
++		switch (cmd) {
++			case NAND_CMD_ERASE1:
++			case NAND_CMD_SEQIN:
++			case NAND_CMD_STATUS:
++			case NAND_CMD_READID:
++			return;
++		}
++
++		/* wait until command is processed */
++		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++			;
++	}
+ }
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+@@ -170,6 +223,7 @@ static int xway_nand_probe(struct platfo
+ 	int err;
+ 	u32 cs;
+ 	u32 cs_flag = 0;
++	const __be32 *req_mask_ptr;
+ 
+ 	/* Allocate memory for the device structure (and zero it) */
+ 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
+@@ -205,6 +259,15 @@ static int xway_nand_probe(struct platfo
+ 	if (!err && cs == 1)
+ 		cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
+ 
++	req_mask_ptr = of_get_property(pdev->dev.of_node,
++					"req-mask", NULL);
++
++	/*
++	 * Load the PCI req lines to mask from the device tree. If the
++	 * property is not present, setting req_mask to 0 disables masking.
++	 */
++	req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
++
+ 	/* setup the EBU to run in NAND mode on our base addr */
+ 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)
+ 		    | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
diff --git a/target/linux/lantiq/patches-6.6/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-6.6/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
new file mode 100644
index 0000000000..ffd07b5f10
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
@@ -0,0 +1,25 @@
+From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:18:00 +0200
+Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/maps/lantiq-flash.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -127,7 +127,11 @@ ltq_mtd_probe(struct platform_device *pd
+ 	if (!ltq_mtd->map)
+ 		return -ENOMEM;
+ 
+-	ltq_mtd->map->phys = ltq_mtd->res->start;
++	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++		ltq_mtd->map->phys = NO_XIP;
++	else
++		ltq_mtd->map->phys = ltq_mtd->res->start;
++	ltq_mtd->res->start;
+ 	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+ 
+ 	ltq_mtd->map->name = ltq_map_name;
diff --git a/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch
new file mode 100644
index 0000000000..fcc760b911
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch
@@ -0,0 +1,294 @@
+From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:15:36 +0200
+Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/Kconfig  |    5 +
+ drivers/net/phy/Makefile |    1 +
+ drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 237 insertions(+)
+ create mode 100644 drivers/net/phy/lantiq.c
+
+--- a/drivers/net/phy/intel-xway.c
++++ b/drivers/net/phy/intel-xway.c
+@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p
+ 			  XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
+ }
+ 
++#if IS_ENABLED(CONFIG_OF_MDIO)
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++	u32 tmp;
++
++	/* store the led values if one was passed by the devicetree */
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H,  tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
++
++	if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
++
++	return 0;
++}
++#else
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++	return 0;
++}
++#endif /* CONFIG_OF_MDIO */
++
+ static int xway_gphy_config_init(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct
+ 	if (err)
+ 		return err;
+ 
++	vr9_gphy_of_reg_init(phydev);
+ 	return 0;
+ }
+ 
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
+@@ -0,0 +1,216 @@
++Lanitq PHY binding
++============================================
++
++This devicetree binding controls the lantiq ethernet phys led functionality.
++
++Example:
++	mdio@0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "lantiq,xrx200-mdio";
++			phy5: ethernet-phy@5 {
++			reg = <0x1>;
++			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
++		};
++		phy11: ethernet-phy@11 {
++			reg = <0x11>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led2h = <0x00>;
++			lantiq,led2l = <0x03>;
++		};
++		phy12: ethernet-phy@12 {
++			reg = <0x12>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led1h = <0x00>;
++			lantiq,led1l = <0x03>;
++		};
++		phy13: ethernet-phy@13 {
++			reg = <0x13>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led2h = <0x00>;
++			lantiq,led2l = <0x03>;
++		};
++		phy14: ethernet-phy@14 {
++			reg = <0x14>;
++			compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++			lantiq,led1h = <0x00>;
++			lantiq,led1l = <0x03>;
++		};
++	};
++
++Register Description
++============================================
++
++LEDCH:
++
++Name	Hardware Reset Value
++LEDCH	0x00C5
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|   FBF   |   SBF   |RES |     NACS     |
++=========================================
++
++Field	Bits	Type	Description
++FBF	7:6	RW	Fast Blink Frequency
++			---
++			0x0 (00b) F02HZ 2 Hz blinking frequency
++			0x1 (01b) F04HZ 4 Hz blinking frequency
++			0x2 (10b) F08HZ 8 Hz blinking frequency
++			0x3 (11b) F16HZ 16 Hz blinking frequency
++
++SBF	5:4	RW	Slow Blink Frequency
++			---
++			0x0 (00b) F02HZ 2 Hz blinking frequency
++			0x1 (01b) F04HZ 4 Hz blinking frequency
++			0x2 (10b) F08HZ 8 Hz blinking frequency
++			0x3 (11b) F16HZ 16 Hz blinking frequency
++
++NACS	2:0	RW	Inverse of Scan Function
++			---
++			0x0 (000b) NONE No Function
++			0x1 (001b) LINK Complex function enabled when link is up
++			0x2 (010b) PDOWN Complex function enabled when device is powered-down
++			0x3 (011b) EEE Complex function enabled when device is in EEE mode
++			0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
++			0x5 (101b) ABIST Complex function enabled when analog self-test is running
++			0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
++			0x7 (111b) TEST Complex function enabled when test mode is running
++
++LEDCL:
++
++Name	Hardware Reset Value
++LEDCL	0x0067
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|RES |     SCAN     |RES |    CBLINK    |
++=========================================
++
++Field	Bits	Type	Description
++SCAN	6:4	RW	Complex Scan Configuration
++			---
++			000 B NONE No Function
++			001 B LINK Complex function enabled when link is up
++			010 B PDOWN Complex function enabled when device is powered-down
++			011 B EEE Complex function enabled when device is in EEE mode
++			100 B ANEG Complex function enabled when auto-negotiation is running
++			101 B ABIST Complex function enabled when analog self-test is running
++			110 B CDIAG Complex function enabled when cable diagnostics are running
++			111 B TEST Complex function enabled when test mode is running
++
++CBLINK	2:0	RW	Complex Blinking Configuration
++			---
++			000 B NONE No Function
++			001 B LINK Complex function enabled when link is up
++			010 B PDOWN Complex function enabled when device is powered-down
++			011 B EEE Complex function enabled when device is in EEE mode
++			100 B ANEG Complex function enabled when auto-negotiation is running
++			101 B ABIST Complex function enabled when analog self-test is running
++			110 B CDIAG Complex function enabled when cable diagnostics are running
++			111 B TEST Complex function enabled when test mode is running
++
++LEDxH:
++
++Name	Hardware Reset Value
++LED0H	0x0070
++LED1H	0x0020
++LED2H	0x0040
++LED3H	0x0040
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|        CON        |       BLINKF      |
++=========================================
++
++Field	Bits	Type	Description
++CON	7:4	RW	Constant On Configuration
++			---
++			0x0 (0000b) NONE LED does not light up constantly
++			0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
++			0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
++			0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN LED is on when device is powered-down
++			0x9 (1001b) EEE LED is on when device is in EEE mode
++			0xA (1010b) ANEG LED is on when auto-negotiation is running
++			0xB (1011b) ABIST LED is on when analog self-test is running
++			0xC (1100b) CDIAG LED is on when cable diagnostics are running
++
++BLINKF	3:0	RW	Fast Blinking Configuration
++			---
++			0x0 (0000b) NONE No Blinking
++			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN Blink when device is powered-down
++			0x9 (1001b) EEE Blink when device is in EEE mode
++			0xA (1010b) ANEG Blink when auto-negotiation is running
++			0xB (1011b) ABIST Blink when analog self-test is running
++			0xC (1100b) CDIAG Blink when cable diagnostics are running
++
++LEDxL:
++
++Name	Hardware Reset Value
++LED0L	0x0003
++LED1L	0x0000
++LED2L	0x0000
++LED3L	0x0020
++
++| 15 |    |    |    |    |    |    |  8 |
++=========================================
++|		RES			|
++=========================================
++
++|  7 |    |    |    |    |    |    |  0 |
++=========================================
++|      BLINKS       |       PULSE       |
++=========================================
++
++Field	Bits	Type	Description
++BLINKS	7:4	RW	Slow Blinkin Configuration
++			---
++			0x0 (0000b) NONE No Blinking
++			0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++			0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++			0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++			0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++			0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++			0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++			0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++			0x8 (1000b) PDOWN Blink when device is powered-down
++			0x9 (1001b) EEE Blink when device is in EEE mode
++			0xA (1010b) ANEG Blink when auto-negotiation is running
++			0xB (1011b) ABIST Blink when analog self-test is running
++			0xC (1100b) CDIAG Blink when cable diagnostics are runningning
++
++PULSE	3:0	RW	Pulsing Configuration
++			The pulse field is a mask field by which certain events can be combined
++			---
++			0x0 (0000b) NONE No pulsing
++			0x1 (0001b) TXACT Transmit activity
++			0x2 (0010b) RXACT Receive activity
++			0x4 (0100b) COL Collision
++			0x8 (1000b) RES Reserved
diff --git a/target/linux/lantiq/patches-6.6/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-6.6/0028-NET-lantiq-various-etop-fixes.patch
new file mode 100644
index 0000000000..8ac1097267
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0028-NET-lantiq-various-etop-fixes.patch
@@ -0,0 +1,886 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 22:45:34 +0200
+Subject: [PATCH 28/36] NET: lantiq: various etop fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+  *
+- *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
+  */
+ 
+ #include <linux/kernel.h>
+@@ -20,12 +20,17 @@
+ #include <linux/mm.h>
+ #include <linux/platform_device.h>
+ #include <linux/ethtool.h>
++#include <linux/if_vlan.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -33,7 +38,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+ 
+-#define LTQ_ETOP_MDIO		0x11804
++#define LTQ_ETOP_MDIO_ACC	0x11804
+ #define MDIO_REQUEST		0x80000000
+ #define MDIO_READ		0x40000000
+ #define MDIO_ADDR_MASK		0x1f
+@@ -42,44 +47,91 @@
+ #define MDIO_REG_OFFSET		0x10
+ #define MDIO_VAL_MASK		0xffff
+ 
+-#define PPE32_CGEN		0x800
+-#define LQ_PPE32_ENET_MAC_CFG	0x1840
++#define LTQ_ETOP_MDIO_CFG       0x11800
++#define MDIO_CFG_MASK           0x6
++
++#define LTQ_ETOP_CFG            0x11808
++#define LTQ_ETOP_IGPLEN         0x11820
++#define LTQ_ETOP_MAC_CFG	0x11840
+ 
+ #define LTQ_ETOP_ENETS0		0x11850
+ #define LTQ_ETOP_MAC_DA0	0x1186C
+ #define LTQ_ETOP_MAC_DA1	0x11870
+-#define LTQ_ETOP_CFG		0x16020
+-#define LTQ_ETOP_IGPLEN		0x16080
++
++#define MAC_CFG_MASK		0xfff
++#define MAC_CFG_CGEN		(1 << 11)
++#define MAC_CFG_DUPLEX		(1 << 2)
++#define MAC_CFG_SPEED		(1 << 1)
++#define MAC_CFG_LINK		(1 << 0)
+ 
+ #define MAX_DMA_CHAN		0x8
+ #define MAX_DMA_CRC_LEN		0x4
+ #define MAX_DMA_DATA_LEN	0x600
+ 
+ #define ETOP_FTCU		BIT(28)
+-#define ETOP_MII_MASK		0xf
+-#define ETOP_MII_NORMAL		0xd
+-#define ETOP_MII_REVERSE	0xe
+ #define ETOP_PLEN_UNDER		0x40
+-#define ETOP_CGEN		0x800
++#define ETOP_CFG_MII0		0x01
+ 
+-/* use 2 static channels for TX/RX */
+-#define LTQ_ETOP_TX_CHANNEL	1
+-#define LTQ_ETOP_RX_CHANNEL	6
+-#define IS_TX(x)		((x) == LTQ_ETOP_TX_CHANNEL)
+-#define IS_RX(x)		((x) == LTQ_ETOP_RX_CHANNEL)
++#define ETOP_CFG_MASK           0xfff
++#define ETOP_CFG_FEN0		(1 << 8)
++#define ETOP_CFG_SEN0		(1 << 6)
++#define ETOP_CFG_OFF1		(1 << 3)
++#define ETOP_CFG_REMII0		(1 << 1)
++#define ETOP_CFG_OFF0		(1 << 0)
++
++#define LTQ_GBIT_MDIO_CTL	0xCC
++#define LTQ_GBIT_MDIO_DATA	0xd0
++#define LTQ_GBIT_GCTL0		0x68
++#define LTQ_GBIT_PMAC_HD_CTL	0x8c
++#define LTQ_GBIT_P0_CTL		0x4
++#define LTQ_GBIT_PMAC_RX_IPG	0xa8
++#define LTQ_GBIT_RGMII_CTL	0x78
++
++#define PMAC_HD_CTL_AS		(1 << 19)
++#define PMAC_HD_CTL_RXSH	(1 << 22)
++
++/* Switch Enable (0=disable, 1=enable) */
++#define GCTL0_SE		0x80000000
++/* Disable MDIO auto polling (0=disable, 1=enable) */
++#define PX_CTL_DMDIO		0x00400000
++
++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
++#define MDC_CLOCK_MASK		0xff000000
++#define MDC_CLOCK_OFFSET	24
++
++/* register information for the gbit's MDIO bus */
++#define MDIO_XR9_REQUEST	0x00008000
++#define MDIO_XR9_READ		0x00000800
++#define MDIO_XR9_WRITE		0x00000400
++#define MDIO_XR9_REG_MASK	0x1f
++#define MDIO_XR9_ADDR_MASK	0x1f
++#define MDIO_XR9_RD_MASK	0xffff
++#define MDIO_XR9_REG_OFFSET	0
++#define MDIO_XR9_ADDR_OFFSET	5
++#define MDIO_XR9_WR_OFFSET	16
+ 
++#define LTQ_DMA_ETOP	((of_machine_is_compatible("lantiq,ase")) ? \
++			(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
++
++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+ #define ltq_etop_r32(x)		ltq_r32(ltq_etop_membase + (x))
+ #define ltq_etop_w32(x, y)	ltq_w32(x, ltq_etop_membase + (y))
+ #define ltq_etop_w32_mask(x, y, z)	\
+ 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
+ 
+-#define DRV_VERSION	"1.0"
++#define ltq_gbit_r32(x)		ltq_r32(ltq_gbit_membase + (x))
++#define ltq_gbit_w32(x, y)	ltq_w32(x, ltq_gbit_membase + (y))
++#define ltq_gbit_w32_mask(x, y, z)	\
++		ltq_w32_mask(x, y, ltq_gbit_membase + (z))
++
++#define DRV_VERSION	"1.2"
+ 
+ static void __iomem *ltq_etop_membase;
++static void __iomem *ltq_gbit_membase;
+ 
+ struct ltq_etop_chan {
+-	int idx;
+ 	int tx_free;
++	int irq;
+ 	struct net_device *netdev;
+ 	struct napi_struct napi;
+ 	struct ltq_dma_channel dma;
+@@ -89,26 +141,39 @@ struct ltq_etop_chan {
+ struct ltq_etop_priv {
+ 	struct net_device *netdev;
+ 	struct platform_device *pdev;
+-	struct ltq_eth_data *pldata;
+ 	struct resource *res;
+ 
+ 	struct mii_bus *mii_bus;
+ 
+-	struct ltq_etop_chan ch[MAX_DMA_CHAN];
+-	int tx_free[MAX_DMA_CHAN >> 1];
++	struct ltq_etop_chan txch;
++	struct ltq_etop_chan rxch;
+ 
+ 	int tx_burst_len;
+ 	int rx_burst_len;
+ 
+-	spinlock_t lock;
++	int tx_irq;
++	int rx_irq;
++
++	unsigned char mac[6];
++	phy_interface_t mii_mode;
++ 
++ 	spinlock_t lock;
++
++	struct clk *clk_ppe;
++	struct clk *clk_switch;
++	struct clk *clk_ephy;
++	struct clk *clk_ephycgu;
+ };
+ 
++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
++				int phy_reg, u16 phy_data);
++
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 
+-	ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
++	ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
+ 	if (!ch->skb[ch->dma.desc])
+ 		return -ENOMEM;
+ 	ch->dma.desc_base[ch->dma.desc].addr =
+@@ -143,8 +208,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	skb_put(skb, len);
++	skb->dev = ch->netdev;
+ 	skb->protocol = eth_type_trans(skb, ch->netdev);
+ 	netif_receive_skb(skb);
++	ch->netdev->stats.rx_packets++;
++	ch->netdev->stats.rx_bytes += len;
+ }
+ 
+ static int
+@@ -152,7 +220,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ {
+ 	struct ltq_etop_chan *ch = container_of(napi,
+ 				struct ltq_etop_chan, napi);
++	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	int work_done = 0;
++	unsigned long flags;
+ 
+ 	while (work_done < budget) {
+ 		struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+@@ -164,7 +234,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ 	}
+ 	if (work_done < budget) {
+ 		napi_complete_done(&ch->napi, work_done);
++		spin_lock_irqsave(&priv->lock, flags);
+ 		ltq_dma_ack_irq(&ch->dma);
++		spin_unlock_irqrestore(&priv->lock, flags);
+ 	}
+ 	return work_done;
+ }
+@@ -176,12 +248,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 		container_of(napi, struct ltq_etop_chan, napi);
+ 	struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ 	struct netdev_queue *txq =
+-		netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
++		netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
+ 	unsigned long flags;
+ 
+ 	spin_lock_irqsave(&priv->lock, flags);
+ 	while ((ch->dma.desc_base[ch->tx_free].ctl &
+ 			(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
++		ch->netdev->stats.tx_packets++;
++		ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
+ 		dev_kfree_skb_any(ch->skb[ch->tx_free]);
+ 		ch->skb[ch->tx_free] = NULL;
+ 		memset(&ch->dma.desc_base[ch->tx_free], 0,
+@@ -194,7 +268,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ 	if (netif_tx_queue_stopped(txq))
+ 		netif_tx_start_queue(txq);
+ 	napi_complete(&ch->napi);
++	spin_lock_irqsave(&priv->lock, flags);
+ 	ltq_dma_ack_irq(&ch->dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
+ 	return 1;
+ }
+ 
+@@ -202,9 +278,10 @@ static irqreturn_t
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ 	struct ltq_etop_priv *priv = _priv;
+-	int ch = irq - LTQ_DMA_CH0_INT;
+-
+-	napi_schedule(&priv->ch[ch].napi);
++	if (irq == priv->txch.dma.irq)
++		napi_schedule(&priv->txch.napi);
++	else
++		napi_schedule(&priv->rxch.napi);
+ 	return IRQ_HANDLED;
+ }
+ 
+@@ -216,7 +293,7 @@ ltq_etop_free_channel(struct net_device
+ 	ltq_dma_free(&ch->dma);
+ 	if (ch->dma.irq)
+ 		free_irq(ch->dma.irq, priv);
+-	if (IS_RX(ch->idx)) {
++	if (ch == &priv->txch) {
+ 		int desc;
+ 
+ 		for (desc = 0; desc < LTQ_DESC_NUM; desc++)
+@@ -228,80 +305,135 @@ static void
+ ltq_etop_hw_exit(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+ 
+-	ltq_pmu_disable(PMU_PPE);
+-	for (i = 0; i < MAX_DMA_CHAN; i++)
+-		if (IS_TX(i) || IS_RX(i))
+-			ltq_etop_free_channel(dev, &priv->ch[i]);
++	clk_disable(priv->clk_ppe);
++
++	if (of_machine_is_compatible("lantiq,ar9"))
++		clk_disable(priv->clk_switch);
++
++	if (of_machine_is_compatible("lantiq,ase")) {
++		clk_disable(priv->clk_ephy);
++		clk_disable(priv->clk_ephycgu);
++	}
++
++	ltq_etop_free_channel(dev, &priv->txch);
++	ltq_etop_free_channel(dev, &priv->rxch);
++}
++
++static void
++ltq_etop_gbit_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++
++	clk_enable(priv->clk_switch);
++
++	/* enable gbit port0 on the SoC */
++	ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
++
++	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
++	/* disable MDIO auto polling mode */
++	ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
++	/* set 1522 packet size */
++	ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
++	/* disable pmac & dmac headers */
++	ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
++		LTQ_GBIT_PMAC_HD_CTL);
++	/* Due to traffic halt when burst length 8,
++		replace default IPG value with 0x3B */
++	ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
++	/* set mdc clock to 2.5 MHz */
++	ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
++		LTQ_GBIT_RGMII_CTL);
+ }
+ 
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
+-	int err;
++	phy_interface_t mii_mode = priv->mii_mode;
+ 
+-	ltq_pmu_enable(PMU_PPE);
++	clk_enable(priv->clk_ppe);
+ 
+-	switch (priv->pldata->mii_mode) {
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		ltq_etop_gbit_init(dev);
++		/* force the etops link to the gbit to MII */
++		mii_mode = PHY_INTERFACE_MODE_MII;
++	}
++	ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
++	ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
++			MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
++
++	switch (mii_mode) {
+ 	case PHY_INTERFACE_MODE_RMII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	case PHY_INTERFACE_MODE_MII:
+-		ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
+-				  LTQ_ETOP_CFG);
++		ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
++			ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	default:
++		if (of_machine_is_compatible("lantiq,ase")) {
++			clk_enable(priv->clk_ephy);
++			/* disable external MII */
++			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
++			/* enable clock for internal PHY */
++			clk_enable(priv->clk_ephycgu);
++			/* we need to write this magic to the internal phy to
++			   make it work */
++			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
++			pr_info("Selected EPHY mode\n");
++			break;
++		}
+ 		netdev_err(dev, "unknown mii mode %d\n",
+-			   priv->pldata->mii_mode);
++			   mii_mode);
+ 		return -ENOTSUPP;
+ 	}
+ 
+-	/* enable crc generation */
+-	ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
++	return 0;
++}
++
++static int
++ltq_etop_dma_init(struct net_device *dev)
++{
++	struct ltq_etop_priv *priv = netdev_priv(dev);
++	int tx = priv->tx_irq - LTQ_DMA_ETOP;
++	int rx = priv->rx_irq - LTQ_DMA_ETOP;
++	int err;
+ 
+ 	ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		int irq = LTQ_DMA_CH0_INT + i;
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		ch->dma.nr = i;
+-		ch->idx = ch->dma.nr;
+-		ch->dma.dev = &priv->pdev->dev;
+-
+-		if (IS_TX(i)) {
+-			ltq_dma_alloc_tx(&ch->dma);
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Tx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
+-		} else if (IS_RX(i)) {
+-			ltq_dma_alloc_rx(&ch->dma);
+-			for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+-					ch->dma.desc++)
+-				if (ltq_etop_alloc_skb(ch))
+-					return -ENOMEM;
+-			ch->dma.desc = 0;
+-			err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
+-			if (err) {
+-				netdev_err(dev,
+-					   "Unable to get Rx DMA IRQ %d\n",
+-					   irq);
+-				return err;
+-			}
++	priv->txch.dma.nr = tx;
++	priv->txch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_tx(&priv->txch.dma);
++	err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
++	if (err) {
++		netdev_err(dev, "failed to allocate tx irq\n");
++		goto err_out;
++	}
++	priv->txch.dma.irq = priv->tx_irq;
++
++	priv->rxch.dma.nr = rx;
++	priv->rxch.dma.dev = &priv->pdev->dev;
++	ltq_dma_alloc_rx(&priv->rxch.dma);
++	for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
++			priv->rxch.dma.desc++) {
++		if (ltq_etop_alloc_skb(&priv->rxch)) {
++			netdev_err(dev, "failed to allocate skbs\n");
++			err = -ENOMEM;
++			goto err_out;
+ 		}
+-		ch->dma.irq = irq;
+ 	}
+-	return 0;
++	priv->rxch.dma.desc = 0;
++	err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
++	if (err)
++		netdev_err(dev, "failed to allocate rx irq\n");
++	else
++		priv->rxch.dma.irq = priv->rx_irq;
++err_out:
++	return err;
+ }
+ 
+ static void
+@@ -320,6 +452,39 @@ static const struct ethtool_ops ltq_etop
+ };
+ 
+ static int
++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
++		int phy_reg, u16 phy_data)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
++		(phy_data << MDIO_XR9_WR_OFFSET) |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	return 0;
++}
++
++static int
++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
++	return val;
++}
++
++static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ 	u32 val = MDIO_REQUEST |
+@@ -327,9 +492,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
+ 		phy_data;
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+ 	return 0;
+ }
+ 
+@@ -340,12 +505,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
+ 		((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
+ 		((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
+ 
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	ltq_etop_w32(val, LTQ_ETOP_MDIO);
+-	while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++	ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
++	while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ 		;
+-	val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
++	val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
+ 	return val;
+ }
+ 
+@@ -361,7 +526,10 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct phy_device *phydev;
+ 
+-	phydev = phy_find_first(priv->mii_bus);
++	if (of_machine_is_compatible("lantiq,ase"))
++		phydev = mdiobus_get_phy(priv->mii_bus, 8);
++	else
++		phydev = mdiobus_get_phy(priv->mii_bus, 0);
+ 
+ 	if (!phydev) {
+ 		netdev_err(dev, "no PHY found\n");
+@@ -369,14 +537,17 @@ ltq_etop_mdio_probe(struct net_device *d
+ 	}
+ 
+ 	phydev = phy_connect(dev, phydev_name(phydev),
+-			     &ltq_etop_mdio_link, priv->pldata->mii_mode);
++			     &ltq_etop_mdio_link, priv->mii_mode);
+ 
+ 	if (IS_ERR(phydev)) {
+ 		netdev_err(dev, "Could not attach to PHY\n");
+ 		return PTR_ERR(phydev);
+ 	}
+ 
+-	phy_set_max_speed(phydev, SPEED_100);
++	if (of_machine_is_compatible("lantiq,ar9"))
++		phy_set_max_speed(phydev, SPEED_1000);
++	else
++		phy_set_max_speed(phydev, SPEED_100);
+ 
+ 	phy_attached_info(phydev);
+ 
+@@ -397,8 +568,13 @@ ltq_etop_mdio_init(struct net_device *de
+ 	}
+ 
+ 	priv->mii_bus->priv = dev;
+-	priv->mii_bus->read = ltq_etop_mdio_rd;
+-	priv->mii_bus->write = ltq_etop_mdio_wr;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
++		priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
++	} else {
++		priv->mii_bus->read = ltq_etop_mdio_rd;
++		priv->mii_bus->write = ltq_etop_mdio_wr;
++	}
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+@@ -435,18 +611,21 @@ static int
+ ltq_etop_open(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
++	napi_enable(&priv->txch.napi);
++	napi_enable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_open(&priv->txch.dma);
++	ltq_dma_enable_irq(&priv->txch.dma);
++	ltq_dma_open(&priv->rxch.dma);
++	ltq_dma_enable_irq(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	if (dev->phydev)
++		phy_start(dev->phydev);
+ 
+-		if (!IS_TX(i) && (!IS_RX(i)))
+-			continue;
+-		ltq_dma_open(&ch->dma);
+-		ltq_dma_enable_irq(&ch->dma);
+-		napi_enable(&ch->napi);
+-	}
+-	phy_start(dev->phydev);
+ 	netif_tx_start_all_queues(dev);
+ 	return 0;
+ }
+@@ -455,18 +634,19 @@ static int
+ ltq_etop_stop(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int i;
++	unsigned long flags;
+ 
+ 	netif_tx_stop_all_queues(dev);
+-	phy_stop(dev->phydev);
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		struct ltq_etop_chan *ch = &priv->ch[i];
+-
+-		if (!IS_RX(i) && !IS_TX(i))
+-			continue;
+-		napi_disable(&ch->napi);
+-		ltq_dma_close(&ch->dma);
+-	}
++	if (dev->phydev)
++		phy_stop(dev->phydev);
++	napi_disable(&priv->txch.napi);
++	napi_disable(&priv->rxch.napi);
++
++	spin_lock_irqsave(&priv->lock, flags);
++	ltq_dma_close(&priv->txch.dma);
++	ltq_dma_close(&priv->rxch.dma);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
+ 	return 0;
+ }
+ 
+@@ -476,15 +656,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	int queue = skb_get_queue_mapping(skb);
+ 	struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+-	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+-	int len;
++	struct ltq_dma_desc *desc =
++		&priv->txch.dma.desc_base[priv->txch.dma.desc];
+ 	unsigned long flags;
+ 	u32 byte_offset;
++	int len;
+ 
+ 	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+ 
+-	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
++	if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
++			priv->txch.skb[priv->txch.dma.desc]) {
+ 		netdev_err(dev, "tx ring full\n");
+ 		netif_tx_stop_queue(txq);
+ 		return NETDEV_TX_BUSY;
+@@ -492,7 +673,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 
+ 	/* dma needs to start on a burst length value aligned address */
+ 	byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
+-	ch->skb[ch->dma.desc] = skb;
++	priv->txch.skb[priv->txch.dma.desc] = skb;
+ 
+ 	netif_trans_update(dev);
+ 
+@@ -503,11 +684,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ 	wmb();
+ 	desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
+ 		LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
+-	ch->dma.desc++;
+-	ch->dma.desc %= LTQ_DESC_NUM;
++	priv->txch.dma.desc++;
++	priv->txch.dma.desc %= LTQ_DESC_NUM;
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+-	if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
++	if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
+ 		netif_tx_stop_queue(txq);
+ 
+ 	return NETDEV_TX_OK;
+@@ -518,11 +699,14 @@ ltq_etop_change_mtu(struct net_device *d
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	unsigned long flags;
++	int max;
+ 
+ 	dev->mtu = new_mtu;
+ 
++	max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
++
+ 	spin_lock_irqsave(&priv->lock, flags);
+-	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
++	ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
+ 	spin_unlock_irqrestore(&priv->lock, flags);
+ 
+ 	return 0;
+@@ -575,6 +759,9 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 	ltq_etop_change_mtu(dev, 1500);
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 
+ 	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+@@ -592,9 +779,10 @@ ltq_etop_init(struct net_device *dev)
+ 		dev->addr_assign_type = NET_ADDR_RANDOM;
+ 
+ 	ltq_etop_set_multicast_list(dev);
+-	err = ltq_etop_mdio_init(dev);
+-	if (err)
+-		goto err_netdev;
++	if (!ltq_etop_mdio_init(dev))
++		dev->ethtool_ops = &ltq_etop_ethtool_ops;
++	else
++		pr_warn("etop: mdio probe failed\n");;
+ 	return 0;
+ 
+ err_netdev:
+@@ -614,6 +802,9 @@ ltq_etop_tx_timeout(struct net_device *d
+ 	err = ltq_etop_hw_init(dev);
+ 	if (err)
+ 		goto err_hw;
++	err = ltq_etop_dma_init(dev);
++	if (err)
++		goto err_hw;
+ 	netif_trans_update(dev);
+ 	netif_wake_queue(dev);
+ 	return;
+@@ -637,14 +828,18 @@ static const struct net_device_ops ltq_e
+ 	.ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+ 
+-static int __init
+-ltq_etop_probe(struct platform_device *pdev)
++static int ltq_etop_probe(struct platform_device *pdev)
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+-	struct resource *res;
++	struct resource *res, *gbit_res, irqres[2];
+ 	int err;
+-	int i;
++
++	err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
++	if (err != 2) {
++		dev_err(&pdev->dev, "failed to get etop irqs\n");
++		return -EINVAL;
++	}
+ 
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (!res) {
+@@ -670,19 +865,55 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_out;
+ 	}
+ 
+-	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+-	if (!dev) {
+-		err = -ENOMEM;
+-		goto err_out;
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++		if (!gbit_res) {
++			dev_err(&pdev->dev, "failed to get gbit resource\n");
++			err = -ENOENT;
++			goto err_out;
++		}
++		ltq_gbit_membase = devm_ioremap(&pdev->dev,
++			gbit_res->start, resource_size(gbit_res));
++		if (!ltq_gbit_membase) {
++			dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
++				pdev->id);
++			err = -ENOMEM;
++			goto err_out;
++		}
+ 	}
++
++	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ 	strcpy(dev->name, "eth%d");
+ 	dev->netdev_ops = &ltq_eth_netdev_ops;
+-	dev->ethtool_ops = &ltq_etop_ethtool_ops;
+ 	priv = netdev_priv(dev);
+ 	priv->res = res;
+ 	priv->pdev = pdev;
+-	priv->pldata = dev_get_platdata(&pdev->dev);
+ 	priv->netdev = dev;
++	priv->tx_irq = irqres[0].start;
++	priv->rx_irq = irqres[1].start;
++	err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode);
++	if (err)
++		pr_err("Can't find phy-mode for port\n");
++
++	of_get_mac_address(pdev->dev.of_node, priv->mac);
++
++	priv->clk_ppe = clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->clk_ppe))
++		return PTR_ERR(priv->clk_ppe);
++	if (of_machine_is_compatible("lantiq,ar9")) {
++		priv->clk_switch = clk_get(&pdev->dev, "switch");
++		if (IS_ERR(priv->clk_switch))
++			return PTR_ERR(priv->clk_switch);
++	}
++	if (of_machine_is_compatible("lantiq,ase")) {
++		priv->clk_ephy = clk_get(&pdev->dev, "ephy");
++		if (IS_ERR(priv->clk_ephy))
++			return PTR_ERR(priv->clk_ephy);
++		priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
++		if (IS_ERR(priv->clk_ephycgu))
++			return PTR_ERR(priv->clk_ephycgu);
++	}
++
+ 	spin_lock_init(&priv->lock);
+ 	SET_NETDEV_DEV(dev, &pdev->dev);
+ 
+@@ -698,15 +929,10 @@ ltq_etop_probe(struct platform_device *p
+ 		goto err_free;
+ 	}
+ 
+-	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		if (IS_TX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_tx, 8);
+-		else if (IS_RX(i))
+-			netif_napi_add_weight(dev, &priv->ch[i].napi,
+-					      ltq_etop_poll_rx, 32);
+-		priv->ch[i].netdev = dev;
+-	}
++	netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
++	netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
++	priv->txch.netdev = dev;
++	priv->rxch.netdev = dev;
+ 
+ 	err = register_netdev(dev);
+ 	if (err)
+@@ -735,31 +961,22 @@ ltq_etop_remove(struct platform_device *
+ 	return 0;
+ }
+ 
++static const struct of_device_id ltq_etop_match[] = {
++	{ .compatible = "lantiq,etop-xway" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ltq_etop_match);
++
+ static struct platform_driver ltq_mii_driver = {
++	.probe = ltq_etop_probe,
+ 	.remove = ltq_etop_remove,
+ 	.driver = {
+ 		.name = "ltq_etop",
++		.of_match_table = ltq_etop_match,
+ 	},
+ };
+ 
+-static int __init
+-init_ltq_etop(void)
+-{
+-	int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
+-
+-	if (ret)
+-		pr_err("ltq_etop: Error registering platform driver!");
+-	return ret;
+-}
+-
+-static void __exit
+-exit_ltq_etop(void)
+-{
+-	platform_driver_unregister(&ltq_mii_driver);
+-}
+-
+-module_init(init_ltq_etop);
+-module_exit(exit_ltq_etop);
++module_platform_driver(ltq_mii_driver);
+ 
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+ MODULE_DESCRIPTION("Lantiq SoC ETOP");
diff --git a/target/linux/lantiq/patches-6.6/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-6.6/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
new file mode 100644
index 0000000000..e3b18be709
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
@@ -0,0 +1,1034 @@
+From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:26:42 +0200
+Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master
+
+This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/i2c/busses/Kconfig      |   10 +
+ drivers/i2c/busses/Makefile     |    1 +
+ drivers/i2c/busses/i2c-lantiq.c |  747 +++++++++++++++++++++++++++++++++++++++
+ drivers/i2c/busses/i2c-lantiq.h |  234 ++++++++++++
+ 4 files changed, 992 insertions(+)
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.c
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.h
+
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -817,6 +817,16 @@ config I2C_MICROCHIP_CORE
+ 	  This driver can also be built as a module. If so, the module will be
+ 	  called i2c-microchip-core.
+ 
++config I2C_LANTIQ
++	tristate "Lantiq I2C interface"
++	depends on LANTIQ && SOC_FALCON
++	help
++	  If you say yes to this option, support will be included for the
++	  Lantiq I2C core.
++
++	  This driver can also be built as a module. If so, the module
++	  will be called i2c-lantiq.
++
+ config I2C_MPC
+ 	tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
+ 	depends on PPC
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C)	+= i2c-imx-l
+ obj-$(CONFIG_I2C_IOP3XX)	+= i2c-iop3xx.o
+ obj-$(CONFIG_I2C_JZ4780)	+= i2c-jz4780.o
+ obj-$(CONFIG_I2C_KEMPLD)	+= i2c-kempld.o
++obj-$(CONFIG_I2C_LANTIQ)	+= i2c-lantiq.o
+ obj-$(CONFIG_I2C_LPC2K)		+= i2c-lpc2k.o
+ obj-$(CONFIG_I2C_LS2X)		+= i2c-ls2x.o
+ obj-$(CONFIG_I2C_MESON)		+= i2c-meson.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.c
+@@ -0,0 +1,747 @@
++
++/*
++ * Lantiq I2C bus adapter
++ *
++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/slab.h> /* for kzalloc, kfree */
++#include <linux/i2c.h>
++#include <linux/errno.h>
++#include <linux/completion.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/of_irq.h>
++
++#include <lantiq_soc.h>
++#include "i2c-lantiq.h"
++
++/*
++ * CURRENT ISSUES:
++ * - no high speed support
++ * - ten bit mode is not tested (no slave devices)
++ */
++
++/* access macros */
++#define i2c_r32(reg)	\
++	__raw_readl(&(priv->membase)->reg)
++#define i2c_w32(val, reg)	\
++	__raw_writel(val, &(priv->membase)->reg)
++#define i2c_w32_mask(clear, set, reg)	\
++	i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)
++
++#define DRV_NAME "i2c-lantiq"
++#define DRV_VERSION "1.00"
++
++#define LTQ_I2C_BUSY_TIMEOUT		20 /* ms */
++
++#ifdef DEBUG
++#define LTQ_I2C_XFER_TIMEOUT		(25*HZ)
++#else
++#define LTQ_I2C_XFER_TIMEOUT		HZ
++#endif
++
++#define LTQ_I2C_IMSC_DEFAULT_MASK	(I2C_IMSC_I2C_P_INT_EN | \
++					 I2C_IMSC_I2C_ERR_INT_EN)
++
++#define LTQ_I2C_ARB_LOST		(1 << 0)
++#define LTQ_I2C_NACK			(1 << 1)
++#define LTQ_I2C_RX_UFL			(1 << 2)
++#define LTQ_I2C_RX_OFL			(1 << 3)
++#define LTQ_I2C_TX_UFL			(1 << 4)
++#define LTQ_I2C_TX_OFL			(1 << 5)
++
++struct ltq_i2c {
++	struct mutex mutex;
++
++
++	/* active clock settings */
++	unsigned int input_clock;	/* clock input for i2c hardware block */
++	unsigned int i2c_clock;		/* approximated bus clock in kHz */
++
++	struct clk *clk_gate;
++	struct clk *clk_input;
++
++
++	/* resources (memory and interrupts) */
++	int irq_lb;				/* last burst irq */
++
++	struct lantiq_reg_i2c __iomem *membase;	/* base of mapped registers */
++
++	struct i2c_adapter adap;
++	struct device *dev;
++
++	struct completion cmd_complete;
++
++
++	/* message transfer data */
++	struct i2c_msg *current_msg;	/* current message */
++	int msgs_num;		/* number of messages to handle */
++	u8 *msg_buf;		/* current buffer */
++	u32 msg_buf_len;	/* remaining length of current buffer */
++	int msg_err;		/* error status of the current transfer */
++
++
++	/* master status codes */
++	enum {
++		STATUS_IDLE,
++		STATUS_ADDR,	/* address phase */
++		STATUS_WRITE,
++		STATUS_READ,
++		STATUS_READ_END,
++		STATUS_STOP
++	} status;
++};
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);
++
++static inline void enable_burst_irq(struct ltq_i2c *priv)
++{
++	i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
++}
++static inline void disable_burst_irq(struct ltq_i2c *priv)
++{
++	i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
++}
++
++static void prepare_msg_send_addr(struct ltq_i2c *priv)
++{
++	struct i2c_msg *msg = priv->current_msg;
++	int rd = !!(msg->flags & I2C_M_RD);	/* extends to 0 or 1 */
++	u16 addr = msg->addr;
++
++	/* new i2c_msg */
++	priv->msg_buf = msg->buf;
++	priv->msg_buf_len = msg->len;
++	if (rd)
++		priv->status = STATUS_READ;
++	else
++		priv->status = STATUS_WRITE;
++
++	/* send slave address */
++	if (msg->flags & I2C_M_TEN) {
++		i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
++		i2c_w32(addr & 0xff, txd);
++	} else {
++		i2c_w32((addr & 0x7f) << 1 | rd, txd);
++	}
++}
++
++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)
++{
++	struct i2c_msg *msg = priv->current_msg;
++	int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
++
++	pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T');
++
++	priv->status = STATUS_ADDR;
++
++	if (!(msg->flags & I2C_M_RD))
++		len += msg->len;
++	else
++		/* set maximum received packet size (before rx int!) */
++		i2c_w32(msg->len, mrps_ctrl);
++	i2c_w32(len, tps_ctrl);
++	enable_burst_irq(priv);
++}
++
++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)
++{
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++	unsigned int input_clock = clk_get_rate(priv->clk_input);
++	u32 dec, inc = 1;
++
++	/* clock changed? */
++	if (priv->input_clock == input_clock)
++		return 0;
++
++	/*
++	 * this formula is only an approximation, found by the recommended
++	 * values in the "I2C Architecture Specification 1.7.1"
++	 */
++	dec = input_clock / (priv->i2c_clock * 2);
++	if (dec <= 6)
++		return -ENXIO;
++
++	i2c_w32(0, fdiv_high_cfg);
++	i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |
++		(dec << I2C_FDIV_CFG_DEC_OFFSET),
++		fdiv_cfg);
++
++	dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n",
++		input_clock, priv->i2c_clock, dec);
++
++	priv->input_clock = input_clock;
++	return 0;
++}
++
++static int ltq_i2c_hw_init(struct i2c_adapter *adap)
++{
++	int ret = 0;
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++
++	/* disable bus */
++	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++#ifndef DEBUG
++	/* set normal operation clock divider */
++	i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
++#else
++	/* for debugging a higher divider value! */
++	i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
++#endif
++
++	/* setup clock */
++	ret = ltq_i2c_hw_set_clock(adap);
++	if (ret != 0) {
++		dev_warn(priv->dev, "invalid clock settings\n");
++		return ret;
++	}
++
++	/* configure fifo */
++	i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
++		I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
++		I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
++		I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
++		I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
++		I2C_FIFO_CFG_RXBS_RXBS0,  /* rx fifo burst size is 1 word */
++		fifo_cfg);
++
++	/* configure address */
++	i2c_w32(I2C_ADDR_CFG_SOPE_EN |	/* generate stop when no more data in
++					   the fifo */
++		I2C_ADDR_CFG_SONA_EN |	/* generate stop when NA received */
++		I2C_ADDR_CFG_MnS_EN |	/* we are master device */
++		0,			/* our slave address (not used!) */
++		addr_cfg);
++
++	/* enable bus */
++	i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
++
++	return 0;
++}
++
++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)
++{
++	unsigned long timeout;
++
++	timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);
++
++	do {
++		u32 stat = i2c_r32(bus_stat);
++
++		if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)
++			return 0;
++
++		cond_resched();
++	} while (!time_after_eq(jiffies, timeout));
++
++	dev_err(priv->dev, "timeout waiting for bus ready\n");
++	return -ETIMEDOUT;
++}
++
++static void ltq_i2c_tx(struct ltq_i2c *priv, int last)
++{
++	if (priv->msg_buf_len && priv->msg_buf) {
++		i2c_w32(*priv->msg_buf, txd);
++
++		if (--priv->msg_buf_len)
++			priv->msg_buf++;
++		else
++			priv->msg_buf = NULL;
++	} else {
++		last = 1;
++	}
++
++	if (last)
++		disable_burst_irq(priv);
++}
++
++static void ltq_i2c_rx(struct ltq_i2c *priv, int last)
++{
++	u32 fifo_stat, timeout;
++	if (priv->msg_buf_len && priv->msg_buf) {
++		timeout = 5000000;
++		do {
++			fifo_stat = i2c_r32(ffs_stat);
++		} while (!fifo_stat && --timeout);
++		if (!timeout) {
++			last = 1;
++			pr_debug("\nrx timeout\n");
++			goto err;
++		}
++		while (fifo_stat) {
++			*priv->msg_buf = i2c_r32(rxd);
++			if (--priv->msg_buf_len) {
++				priv->msg_buf++;
++			} else {
++				priv->msg_buf = NULL;
++				last = 1;
++				break;
++			}
++			/*
++			 * do not read more than burst size, otherwise no "last
++			 * burst" is generated and the transaction is blocked!
++			 */
++			fifo_stat = 0;
++		}
++	} else {
++		last = 1;
++	}
++err:
++	if (last) {
++		disable_burst_irq(priv);
++
++		if (priv->status == STATUS_READ_END) {
++			/* 
++			 * do the STATUS_STOP and complete() here, as sometimes
++			 * the tx_end is already seen before this is finished
++			 */
++			priv->status = STATUS_STOP;
++			complete(&priv->cmd_complete);
++		} else {
++			i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++			priv->status = STATUS_READ_END;
++		}
++	}
++}
++
++static void ltq_i2c_xfer_init(struct ltq_i2c *priv)
++{
++	/* enable interrupts */
++	i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);
++
++	/* trigger transfer of first msg */
++	ltq_i2c_set_tx_len(priv);
++}
++
++static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
++{
++#if defined(DEBUG)
++	int i, j;
++	pr_debug("Messages %d %s\n", num, rx ? "out" : "in");
++	for (i = 0; i < num; i++) {
++		pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i,
++			(msgs[i].flags & I2C_M_RD) ? 'R' : 'T',
++			msgs[i].len, msgs[i].addr);
++		if (!(msgs[i].flags & I2C_M_RD) || rx) {
++			for (j = 0; j < msgs[i].len; j++)
++				pr_debug("%02X ", msgs[i].buf[j]);
++		}
++		pr_debug("\n");
++	}
++#endif
++}
++
++static void ltq_i2c_release_bus(struct ltq_i2c *priv)
++{
++	if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
++		i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++}
++
++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
++			   int num)
++{
++	struct ltq_i2c *priv = i2c_get_adapdata(adap);
++	int ret;
++
++	dev_dbg(priv->dev, "xfer %u messages\n", num);
++	dump_msgs(msgs, num, 0);
++
++	mutex_lock(&priv->mutex);
++
++	init_completion(&priv->cmd_complete);
++	priv->current_msg = msgs;
++	priv->msgs_num = num;
++	priv->msg_err = 0;
++	priv->status = STATUS_IDLE;
++
++	/* wait for the bus to become ready */
++	ret = ltq_i2c_wait_bus_not_busy(priv);
++	if (ret)
++		goto done;
++
++	while (priv->msgs_num) {
++		/* start the transfers */
++		ltq_i2c_xfer_init(priv);
++
++		/* wait for transfers to complete */
++		ret = wait_for_completion_interruptible_timeout(
++			&priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);
++		if (ret == 0) {
++			dev_err(priv->dev, "controller timed out\n");
++			ltq_i2c_hw_init(adap);
++			ret = -ETIMEDOUT;
++			goto done;
++		} else if (ret < 0)
++			goto done;
++
++		if (priv->msg_err) {
++			if (priv->msg_err & LTQ_I2C_NACK)
++				ret = -ENXIO;
++			else
++				ret = -EREMOTEIO;
++			goto done;
++		}
++		if (--priv->msgs_num)
++			priv->current_msg++;
++	}
++	/* no error? */
++	ret = num;
++
++done:
++	ltq_i2c_release_bus(priv);
++
++	mutex_unlock(&priv->mutex);
++
++	if (ret >= 0)
++		dump_msgs(msgs, num, 1);
++
++	pr_debug("XFER ret %d\n", ret);
++	return ret;
++}
++
++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)
++{
++	struct ltq_i2c *priv = dev_id;
++	struct i2c_msg *msg = priv->current_msg;
++	int last = (irq == priv->irq_lb);
++
++	if (last)
++		pr_debug("LB ");
++	else
++		pr_debug("B ");
++
++	if (msg->flags & I2C_M_RD) {
++		switch (priv->status) {
++		case STATUS_ADDR:
++			pr_debug("X");
++			prepare_msg_send_addr(priv);
++			disable_burst_irq(priv);
++			break;
++		case STATUS_READ:
++		case STATUS_READ_END:
++			pr_debug("R");
++			ltq_i2c_rx(priv, last);
++			break;
++		default:
++			disable_burst_irq(priv);
++			pr_warn("Status R %d\n", priv->status);
++			break;
++		}
++	} else {
++		switch (priv->status) {
++		case STATUS_ADDR:
++			pr_debug("x");
++			prepare_msg_send_addr(priv);
++			break;
++		case STATUS_WRITE:
++			pr_debug("w");
++			ltq_i2c_tx(priv, last);
++			break;
++		default:
++			disable_burst_irq(priv);
++			pr_warn("Status W %d\n", priv->status);
++			break;
++		}
++	}
++
++	i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
++	return IRQ_HANDLED;
++}
++
++static void ltq_i2c_isr_prot(struct ltq_i2c *priv)
++{
++	u32 i_pro = i2c_r32(p_irqss);
++
++	pr_debug("i2c-p");
++
++	/* not acknowledge */
++	if (i_pro & I2C_P_IRQSS_NACK) {
++		priv->msg_err |= LTQ_I2C_NACK;
++		pr_debug(" nack");
++	}
++
++	/* arbitration lost */
++	if (i_pro & I2C_P_IRQSS_AL) {
++		priv->msg_err |= LTQ_I2C_ARB_LOST;
++		pr_debug(" arb-lost");
++	}
++	/* tx -> rx switch */
++	if (i_pro & I2C_P_IRQSS_RX)
++		pr_debug(" rx");
++
++	/* tx end */
++	if (i_pro & I2C_P_IRQSS_TX_END)
++		pr_debug(" txend");
++	pr_debug("\n");
++
++	if (!priv->msg_err) {
++		/* tx -> rx switch */
++		if (i_pro & I2C_P_IRQSS_RX) {
++			priv->status = STATUS_READ;
++			enable_burst_irq(priv);
++		}
++		if (i_pro & I2C_P_IRQSS_TX_END) {
++			if (priv->status == STATUS_READ)
++				priv->status = STATUS_READ_END;
++			else {
++				disable_burst_irq(priv);
++				priv->status = STATUS_STOP;
++			}
++		}
++	}
++
++	i2c_w32(i_pro, p_irqsc);
++}
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)
++{
++	u32 i_raw, i_err = 0;
++	struct ltq_i2c *priv = dev_id;
++
++	i_raw = i2c_r32(mis);
++	pr_debug("i_raw 0x%08X\n", i_raw);
++
++	/* error interrupt */
++	if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
++		i_err = i2c_r32(err_irqss);
++		pr_debug("i_err 0x%08X bus_stat 0x%04X\n",
++			i_err, i2c_r32(bus_stat));
++
++		/* tx fifo overflow (8) */
++		if (i_err & I2C_ERR_IRQSS_TXF_OFL)
++			priv->msg_err |= LTQ_I2C_TX_OFL;
++
++		/* tx fifo underflow (4) */
++		if (i_err & I2C_ERR_IRQSS_TXF_UFL)
++			priv->msg_err |= LTQ_I2C_TX_UFL;
++
++		/* rx fifo overflow (2) */
++		if (i_err & I2C_ERR_IRQSS_RXF_OFL)
++			priv->msg_err |= LTQ_I2C_RX_OFL;
++
++		/* rx fifo underflow (1) */
++		if (i_err & I2C_ERR_IRQSS_RXF_UFL)
++			priv->msg_err |= LTQ_I2C_RX_UFL;
++
++		i2c_w32(i_err, err_irqsc);
++	}
++
++	/* protocol interrupt */
++	if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
++		ltq_i2c_isr_prot(priv);
++
++	if ((priv->msg_err) || (priv->status == STATUS_STOP))
++		complete(&priv->cmd_complete);
++
++	return IRQ_HANDLED;
++}
++
++static u32 ltq_i2c_functionality(struct i2c_adapter *adap)
++{
++	return	I2C_FUNC_I2C |
++		I2C_FUNC_10BIT_ADDR |
++		I2C_FUNC_SMBUS_EMUL;
++}
++
++static struct i2c_algorithm ltq_i2c_algorithm = {
++	.master_xfer	= ltq_i2c_xfer,
++	.functionality	= ltq_i2c_functionality,
++};
++
++static int ltq_i2c_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	struct ltq_i2c *priv;
++	struct i2c_adapter *adap;
++	struct resource *mmres, irqres[4];
++	int ret = 0;
++
++	dev_dbg(&pdev->dev, "probing\n");
++
++	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	ret = of_irq_to_resource_table(node, irqres, 4);
++	if (!mmres || (ret != 4)) {
++		dev_err(&pdev->dev, "no resources\n");
++		return -ENODEV;
++	}
++
++	/* allocate private data */
++	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&pdev->dev, "can't allocate private data\n");
++		return -ENOMEM;
++	}
++
++	adap = &priv->adap;
++	i2c_set_adapdata(adap, priv);
++	adap->owner = THIS_MODULE;
++	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++	strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
++	adap->algo = &ltq_i2c_algorithm;
++	adap->dev.parent = &pdev->dev;
++	adap->dev.of_node = pdev->dev.of_node;
++
++	if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) {
++		dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n");
++		priv->i2c_clock = 100000;
++	}
++
++	init_completion(&priv->cmd_complete);
++	mutex_init(&priv->mutex);
++
++	priv->membase = devm_ioremap_resource(&pdev->dev, mmres);
++	if (IS_ERR(priv->membase))
++		return PTR_ERR(priv->membase);
++
++	priv->dev = &pdev->dev;
++	priv->irq_lb = irqres[0].start;
++
++	ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,
++		0x0, "i2c lb", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
++			irqres[0].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,
++		0x0, "i2c b", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get burst IRQ %d\n",
++			irqres[1].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,
++		0x0, "i2c err", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get error IRQ %d\n",
++			irqres[2].start);
++		return -ENODEV;
++	}
++
++	ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,
++		0x0, "i2c p", priv);
++	if (ret) {
++		dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
++			irqres[3].start);
++		return -ENODEV;
++	}
++
++	dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
++	dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start,
++		irqres[1].start, irqres[2].start, irqres[3].start);
++
++	priv->clk_gate = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(priv->clk_gate)) {
++		dev_err(&pdev->dev, "failed to get i2c clk\n");
++		return -ENOENT;
++	}
++
++	/* this is a static clock, which has no refcounting */
++	priv->clk_input = clk_get_fpi();
++	if (IS_ERR(priv->clk_input)) {
++		dev_err(&pdev->dev, "failed to get fpi clk\n");
++		return -ENOENT;
++	}
++
++	clk_activate(priv->clk_gate);
++
++	/* add our adapter to the i2c stack */
++	ret = i2c_add_numbered_adapter(adap);
++	if (ret) {
++		dev_err(&pdev->dev, "can't register I2C adapter\n");
++		goto out;
++	}
++
++	platform_set_drvdata(pdev, priv);
++	i2c_set_adapdata(adap, priv);
++
++	/* print module version information */
++	dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
++		(i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
++		(i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
++
++	/* initialize HW */
++	ret = ltq_i2c_hw_init(adap);
++	if (ret) {
++		dev_err(&pdev->dev, "can't configure adapter\n");
++		i2c_del_adapter(adap);
++		platform_set_drvdata(pdev, NULL);
++		goto out;
++	} else {
++		dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
++	}
++
++out:
++	/* if init failed, we need to deactivate the clock gate */
++	if (ret)
++		clk_deactivate(priv->clk_gate);
++
++	return ret;
++}
++
++static int ltq_i2c_remove(struct platform_device *pdev)
++{
++	struct ltq_i2c *priv = platform_get_drvdata(pdev);
++
++	/* disable bus */
++	i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++	/* power down the core */
++	clk_deactivate(priv->clk_gate);
++
++	/* remove driver */
++	i2c_del_adapter(&priv->adap);
++	kfree(priv);
++
++	dev_dbg(&pdev->dev, "removed\n");
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++static const struct of_device_id ltq_i2c_match[] = {
++	{ .compatible = "lantiq,lantiq-i2c" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ltq_i2c_match);
++
++static struct platform_driver ltq_i2c_driver = {
++	.probe	= ltq_i2c_probe,
++	.remove	= ltq_i2c_remove,
++	.driver	= {
++		.name	= DRV_NAME,
++		.owner	= THIS_MODULE,
++		.of_match_table = ltq_i2c_match,
++	},
++};
++
++module_platform_driver(ltq_i2c_driver);
++
++MODULE_DESCRIPTION("Lantiq I2C bus adapter");
++MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>");
++MODULE_ALIAS("platform:" DRV_NAME);
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRV_VERSION);
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.h
+@@ -0,0 +1,234 @@
++#ifndef I2C_LANTIQ_H
++#define I2C_LANTIQ_H
++
++/* I2C register structure */
++struct lantiq_reg_i2c {
++	/* I2C Kernel Clock Control Register */
++	unsigned int clc; /* 0x00000000 */
++	/* Reserved */
++	unsigned int res_0; /* 0x00000004 */
++	/* I2C Identification Register */
++	unsigned int id; /* 0x00000008 */
++	/* Reserved */
++	unsigned int res_1; /* 0x0000000C */
++	/*
++	 * I2C RUN Control Register
++	 * This register enables and disables the I2C peripheral. Before
++	 * enabling, the I2C has to be configured properly. After enabling
++	 * no configuration is possible
++	 */
++	unsigned int run_ctrl; /* 0x00000010 */
++	/*
++	 * I2C End Data Control Register
++	 * This register is used to either turn around the data transmission
++	 * direction or to address another slave without sending a stop
++	 * condition. Also the software can stop the slave-transmitter by
++	 * sending a not-accolade when working as master-receiver or even
++	 * stop data transmission immediately when operating as
++	 * master-transmitter. The writing to the bits of this control
++	 * register is only effective when in MASTER RECEIVES BYTES, MASTER
++	 * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
++	 */
++	unsigned int endd_ctrl; /* 0x00000014 */
++	/*
++	 * I2C Fractional Divider Configuration Register
++	 * These register is used to program the fractional divider of the I2C
++	 * bus. Before the peripheral is switched on by setting the RUN-bit the
++	 * two (fixed) values for the two operating frequencies are programmed
++	 * into these (configuration) registers. The Register FDIV_HIGH_CFG has
++	 * the same layout as I2C_FDIV_CFG.
++	 */
++	unsigned int fdiv_cfg; /* 0x00000018 */
++	/*
++	 * I2C Fractional Divider (highspeed mode) Configuration Register
++	 * These register is used to program the fractional divider of the I2C
++	 * bus. Before the peripheral is switched on by setting the RUN-bit the
++	 * two (fixed) values for the two operating frequencies are programmed
++	 * into these (configuration) registers. The Register FDIV_CFG has the
++	 * same layout as I2C_FDIV_CFG.
++	 */
++	unsigned int fdiv_high_cfg; /* 0x0000001C */
++	/* I2C Address Configuration Register */
++	unsigned int addr_cfg; /* 0x00000020 */
++	/* I2C Bus Status Register
++	 * This register gives a status information of the I2C. This additional
++	 * information can be used by the software to start proper actions.
++	 */
++	unsigned int bus_stat; /* 0x00000024 */
++	/* I2C FIFO Configuration Register */
++	unsigned int fifo_cfg; /* 0x00000028 */
++	/* I2C Maximum Received Packet Size Register */
++	unsigned int mrps_ctrl; /* 0x0000002C */
++	/* I2C Received Packet Size Status Register */
++	unsigned int rps_stat; /* 0x00000030 */
++	/* I2C Transmit Packet Size Register */
++	unsigned int tps_ctrl; /* 0x00000034 */
++	/* I2C Filled FIFO Stages Status Register */
++	unsigned int ffs_stat; /* 0x00000038 */
++	/* Reserved */
++	unsigned int res_2; /* 0x0000003C */
++	/* I2C Timing Configuration Register */
++	unsigned int tim_cfg; /* 0x00000040 */
++	/* Reserved */
++	unsigned int res_3[7]; /* 0x00000044 */
++	/* I2C Error Interrupt Request Source Mask Register */
++	unsigned int err_irqsm; /* 0x00000060 */
++	/* I2C Error Interrupt Request Source Status Register */
++	unsigned int err_irqss; /* 0x00000064 */
++	/* I2C Error Interrupt Request Source Clear Register */
++	unsigned int err_irqsc; /* 0x00000068 */
++	/* Reserved */
++	unsigned int res_4; /* 0x0000006C */
++	/* I2C Protocol Interrupt Request Source Mask Register */
++	unsigned int p_irqsm; /* 0x00000070 */
++	/* I2C Protocol Interrupt Request Source Status Register */
++	unsigned int p_irqss; /* 0x00000074 */
++	/* I2C Protocol Interrupt Request Source Clear Register */
++	unsigned int p_irqsc; /* 0x00000078 */
++	/* Reserved */
++	unsigned int res_5; /* 0x0000007C */
++	/* I2C Raw Interrupt Status Register */
++	unsigned int ris; /* 0x00000080 */
++	/* I2C Interrupt Mask Control Register */
++	unsigned int imsc; /* 0x00000084 */
++	/* I2C Masked Interrupt Status Register */
++	unsigned int mis; /* 0x00000088 */
++	/* I2C Interrupt Clear Register */
++	unsigned int icr; /* 0x0000008C */
++	/* I2C Interrupt Set Register */
++	unsigned int isr; /* 0x00000090 */
++	/* I2C DMA Enable Register */
++	unsigned int dmae; /* 0x00000094 */
++	/* Reserved */
++	unsigned int res_6[8154]; /* 0x00000098 */
++	/* I2C Transmit Data Register */
++	unsigned int txd; /* 0x00008000 */
++	/* Reserved */
++	unsigned int res_7[4095]; /* 0x00008004 */
++	/* I2C Receive Data Register */
++	unsigned int rxd; /* 0x0000C000 */
++	/* Reserved */
++	unsigned int res_8[4095]; /* 0x0000C004 */
++};
++
++/*
++ * Clock Divider for Normal Run Mode
++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long
++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx
++ * on reading.
++ */
++#define I2C_CLC_RMC_MASK 0x0000FF00
++/* field offset */
++#define I2C_CLC_RMC_OFFSET 8
++
++/* Fields of "I2C Identification Register" */
++/* Module ID */
++#define I2C_ID_ID_MASK 0x0000FF00
++/* field offset */
++#define I2C_ID_ID_OFFSET 8
++/* Revision */
++#define I2C_ID_REV_MASK 0x000000FF
++/* field offset */
++#define I2C_ID_REV_OFFSET 0
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_BREQ_INT_EN 0x00000008
++/* Enable */
++#define I2C_IMSC_LBREQ_INT_EN 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_INC_OFFSET 16
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_I2C_P_INT_EN 0x00000020
++/* Enable */
++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
++
++/* Fields of "I2C Error Interrupt Request Source Status Register" */
++/* TXF_OFL */
++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
++/* TXF_UFL */
++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
++/* RXF_OFL */
++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
++/* RXF_UFL */
++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
++
++/* Fields of "I2C Raw Interrupt Status Register" */
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* TX FIFO Flow Control */
++#define I2C_FIFO_CFG_TXFC 0x00020000
++/* RX FIFO Flow Control */
++#define I2C_FIFO_CFG_RXFC 0x00010000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
++/* 1 word */
++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* 1 word */
++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
++/* Stop on Packet End Enable */
++#define I2C_ADDR_CFG_SOPE_EN 0x00200000
++/* Stop on Not Acknowledge Enable */
++#define I2C_ADDR_CFG_SONA_EN 0x00100000
++/* Enable */
++#define I2C_ADDR_CFG_MnS_EN 0x00080000
++
++/* Fields of "I2C Interrupt Clear Register" */
++/* Clear */
++#define I2C_ICR_BREQ_INT_CLR 0x00000008
++/* Clear */
++#define I2C_ICR_LBREQ_INT_CLR 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_DEC_OFFSET 0
++
++/* Fields of "I2C Bus Status Register" */
++/* Bus Status */
++#define I2C_BUS_STAT_BS_MASK 0x00000003
++/* Read from I2C Bus. */
++#define I2C_BUS_STAT_RNW_READ 0x00000004
++/* I2C Bus is free. */
++#define I2C_BUS_STAT_BS_FREE 0x00000000
++/*
++ * The device is working as master and has claimed the control on the
++ * I2C-bus (busy master).
++ */
++#define I2C_BUS_STAT_BS_BM 0x00000002
++
++/* Fields of "I2C RUN Control Register" */
++/* Enable */
++#define I2C_RUN_CTRL_RUN_EN 0x00000001
++
++/* Fields of "I2C End Data Control Register" */
++/*
++ * Set End of Transmission
++ * Note:Do not write '1' to this bit when bus is free. This will cause an
++ * abort after the first byte when a new transfer is started.
++ */
++#define I2C_ENDD_CTRL_SETEND 0x00000002
++
++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
++/* NACK */
++#define I2C_P_IRQSS_NACK 0x00000010
++/* AL */
++#define I2C_P_IRQSS_AL 0x00000008
++/* RX */
++#define I2C_P_IRQSS_RX 0x00000040
++/* TX_END */
++#define I2C_P_IRQSS_TX_END 0x00000020
++
++
++#endif /* I2C_LANTIQ_H */
diff --git a/target/linux/lantiq/patches-6.6/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-6.6/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
new file mode 100644
index 0000000000..b06c5ab47c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
@@ -0,0 +1,218 @@
+From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Sep 2014 22:42:14 +0200
+Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +
+ arch/mips/lantiq/xway/Makefile                     |   3 +
+ arch/mips/lantiq/xway/ath5k_eep.c                  | 136 +++++++++++++++++++++
+ arch/mips/lantiq/xway/eth_mac.c                    |  25 ++++
+ drivers/net/ethernet/lantiq_etop.c                 |   6 +-
+ 5 files changed, 172 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
+ create mode 100644 arch/mips/lantiq/xway/eth_mac.c
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -99,5 +99,8 @@ extern __iomem void *ltq_cgu_membase;
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
+ 
++/* allow the ethernet driver to load a flash mapped mac addr */
++const u8* ltq_get_eth_mac(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -8,3 +8,6 @@ obj-y += timer.o
+ endif
+ 
+ obj-y += vmmc.o
++
++obj-y += eth_mac.o
++obj-$(CONFIG_PCI) += ath5k_eep.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/ath5k_eep.c
+@@ -0,0 +1,136 @@
++/*
++ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
++ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
++ *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
++ *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/etherdevice.h>
++#include <linux/ath5k_platform.h>
++#include <linux/pci.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <lantiq_soc.h>
++
++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
++struct ath5k_platform_data ath5k_pdata;
++static u8 athxk_eeprom_mac[6];
++
++static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
++{
++	dev->dev.platform_data = &ath5k_pdata;
++	return 0;
++}
++
++static int ath5k_eep_load;
++int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
++	int mac_offset;
++	u32 mac_inc = 0;
++	int i;
++	struct mtd_info *the_mtd;
++	size_t flash_readlen;
++	const __be32 *list;
++	const char *part;
++	phandle phandle;
++
++	list = of_get_property(np, "ath,eep-flash", &i);
++	if (!list || (i != (2 * sizeof(*list))))
++		return -ENODEV;
++
++	phandle = be32_to_cpup(list++);
++	if (phandle)
++		mtd_np = of_find_node_by_phandle(phandle);
++
++	if (!mtd_np)
++		return -ENODEV;
++
++	part = of_get_property(mtd_np, "label", NULL);
++	if (!part)
++		part = mtd_np->name;
++
++	the_mtd = get_mtd_device_nm(part);
++	if (IS_ERR(the_mtd))
++		return -ENODEV;
++
++	ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
++
++	i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
++		&flash_readlen, (void *) ath5k_pdata.eeprom_data);
++
++	if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
++		size_t mac_readlen;
++		mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
++			(void *) athxk_eeprom_mac);
++	}
++	put_mtd_device(the_mtd);
++
++	if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
++		dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
++		return -ENODEV;
++	}
++
++	if (of_find_property(np, "ath,eep-swap", NULL))
++		for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
++			ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
++		ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
++
++	if (!is_valid_ether_addr(athxk_eeprom_mac)) {
++		dev_warn(&pdev->dev, "using random mac\n");
++		eth_random_addr(athxk_eeprom_mac);
++	}
++
++	if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
++		athxk_eeprom_mac[5] += mac_inc;
++
++	ath5k_pdata.macaddr = athxk_eeprom_mac;
++	ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
++
++	dev_info(&pdev->dev, "loaded ath5k eeprom\n");
++
++	return 0;
++}
++
++static struct of_device_id ath5k_eeprom_ids[] = {
++	{ .compatible = "ath5k,eeprom" },
++	{ }
++};
++
++static struct platform_driver ath5k_eeprom_driver = {
++	.driver		= {
++		.name		= "ath5k,eeprom",
++		.owner	= THIS_MODULE,
++		.of_match_table	= of_match_ptr(ath5k_eeprom_ids),
++	},
++};
++
++static int __init of_ath5k_eeprom_init(void)
++{
++	int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++
++	if (ret)
++		ath5k_eep_load = 1;
++
++	return ret;
++}
++
++static int __init of_ath5k_eeprom_init_late(void)
++{
++	if (!ath5k_eep_load)
++		return 0;
++
++	return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++}
++late_initcall(of_ath5k_eeprom_init_late);
++subsys_initcall(of_ath5k_eeprom_init);
+--- /dev/null
++++ b/arch/mips/lantiq/xway/eth_mac.c
+@@ -0,0 +1,25 @@
++/*
++ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/if_ether.h>
++
++static u8 eth_mac[6];
++static int eth_mac_set;
++
++const u8* ltq_get_eth_mac(void)
++{
++	return eth_mac;
++}
++
++static int __init setup_ethaddr(char *str)
++{
++	eth_mac_set = mac_pton(str, eth_mac);
++	return !eth_mac_set;
++}
++early_param("ethaddr", setup_ethaddr);
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -763,7 +763,11 @@ ltq_etop_init(struct net_device *dev)
+ 	if (err)
+ 		goto err_hw;
+ 
+-	memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
++	memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
++
++	if (!is_valid_ether_addr(mac.sa_data))
++		memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
++
+ 	if (!is_valid_ether_addr(mac.sa_data)) {
+ 		pr_warn("etop: invalid MAC, using random\n");
+ 		eth_random_addr(mac.sa_data);
diff --git a/target/linux/lantiq/patches-6.6/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-6.6/0042-arch-mips-increase-io_space_limit.patch
new file mode 100644
index 0000000000..c81222af57
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0042-arch-mips-increase-io_space_limit.patch
@@ -0,0 +1,24 @@
+From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 3 Jun 2016 13:12:20 +0200
+Subject: [PATCH] arch: mips: increase io_space_limit
+
+this value comes from x86 and breaks some pci devices
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/spaces.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __ASM_MACH_LANTIQ_SPACES_H_
++#define __ASM_MACH_LANTIQ_SPACES_H_
++
++#define IO_SPACE_LIMIT  0xffffffff
++
++#include <asm/mach-generic/spaces.h>
++#endif
diff --git a/target/linux/lantiq/patches-6.6/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-6.6/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch
new file mode 100644
index 0000000000..5099c0bb9e
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch
@@ -0,0 +1,80 @@
+From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:55:24 +0100
+Subject: [PATCH 2/2] usb: dwc2:  add support for other Lantiq SoCs
+
+The size of the internal RAM of the DesignWare USB controller changed
+between the different Lantiq SoCs. We have the following sizes:
+
+Amazon + Danube: 8 KByte
+Amazon SE + arx100: 2 KByte
+xrx200 + xrx300: 2.5 KByte
+
+For Danube SoC we do not provide the params and let the driver decide
+to use sane defaults, for the Amazon SE and arx100 we use small fifos
+and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
+The auto detection of max_transfer_size and max_packet_count should
+work, so remove it.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 39 insertions(+), 7 deletions(-)
+
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -132,7 +132,15 @@ static void dwc2_set_rk_params(struct dw
+ 	p->hird_threshold_en = false;
+ }
+ 
+-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
++{
++	struct dwc2_core_params *p = &hsotg->params;
++
++	p->otg_caps.hnp_support = false;
++	p->otg_caps.srp_support = false;
++}
++
++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+ 
+@@ -141,12 +149,21 @@ static void dwc2_set_ltq_params(struct d
+ 	p->host_rx_fifo_size = 288;
+ 	p->host_nperio_tx_fifo_size = 128;
+ 	p->host_perio_tx_fifo_size = 96;
+-	p->max_transfer_size = 65535;
+-	p->max_packet_count = 511;
+ 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ 		GAHBCFG_HBSTLEN_SHIFT;
+ }
+ 
++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
++{
++	struct dwc2_core_params *p = &hsotg->params;
++
++	p->otg_caps.hnp_support = false;
++	p->otg_caps.srp_support = false;
++	p->host_rx_fifo_size = 288;
++	p->host_nperio_tx_fifo_size = 128;
++	p->host_perio_tx_fifo_size = 136;
++}
++
+ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
+ {
+ 	struct dwc2_core_params *p = &hsotg->params;
+@@ -277,8 +294,11 @@ const struct of_device_id dwc2_of_match_
+ 	{ .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
+ 	{ .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
+ 	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
+-	{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
+-	{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
++	{ .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
++	{ .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
++	{ .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
++	{ .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
++	{ .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
+ 	{ .compatible = "snps,dwc2" },
+ 	{ .compatible = "samsung,s3c6400-hsotg",
+ 	  .data = dwc2_set_s3c6400_params },
diff --git a/target/linux/lantiq/patches-6.6/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-6.6/0051-MIPS-lantiq-improve-USB-initialization.patch
new file mode 100644
index 0000000000..29d696af27
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0051-MIPS-lantiq-improve-USB-initialization.patch
@@ -0,0 +1,49 @@
+From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:40:12 +0100
+Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
+
+This adds code to initialize the USB controller and PHY also on Danube,
+Amazon SE and AR10. This code is based on the Vendor driver from
+different UGW versions and compared to the hardware documentation.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/lantiq/xway/sysctrl.c |  20 +++++++
+ 2 files changed, 110 insertions(+), 30 deletions(-)
+
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk)
+ 		pr_warn("deactivating PMU module failed!");
+ }
+ 
++static void usb_set_clock(void)
++{
++	unsigned int val = ltq_cgu_r32(ifccr);
++
++	if (of_machine_is_compatible("lantiq,ar10") ||
++	    of_machine_is_compatible("lantiq,grx390")) {
++		val &= ~0x03; /* XTAL divided by 3 */
++	} else if (of_machine_is_compatible("lantiq,ar9") ||
++		   of_machine_is_compatible("lantiq,vr9")) {
++		/* TODO: this depends on the XTAL frequency */
++		val |= 0x03; /* XTAL divided by 3 */
++	} else if (of_machine_is_compatible("lantiq,ase")) {
++		val |= 0x20; /* from XTAL */
++	} else if (of_machine_is_compatible("lantiq,danube")) {
++		val |= 0x30; /* 12 MHz, generated from 36 MHz */
++	}
++	ltq_cgu_w32(val, ifccr);
++}
++
+ /* the pci enable helper */
+ static int pci_enable(struct clk *clk)
+ {
+@@ -588,4 +607,5 @@ void __init ltq_soc_init(void)
+ 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
+ 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ 	}
++	usb_set_clock();
+ }
diff --git a/target/linux/lantiq/patches-6.6/0101-find_active_root.patch b/target/linux/lantiq/patches-6.6/0101-find_active_root.patch
new file mode 100644
index 0000000000..99e187a012
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0101-find_active_root.patch
@@ -0,0 +1,103 @@
+From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] find active root
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/parsers/ofpart_core.c
++++ b/drivers/mtd/parsers/ofpart_core.c
+@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d
+ 	return of_get_property(pp, "compatible", NULL);
+ }
+ 
++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
++						loff_t offset)
++{
++	static uint8_t root_id;
++	int err, len;
++
++	err = mtd_read(master, offset, 0x01, &len, &root_id);
++
++	if (mtd_is_bitflip(err) || !err)
++		return &root_id;
++
++	return NULL;
++}
++
++static void brnboot_set_active_root_part(struct mtd_partition *pparts,
++					 struct device_node **part_nodes,
++					 int nr_parts,
++					 uint8_t *root_id)
++{
++	int i;
++
++	for (i = 0; i < nr_parts; i++) {
++		int part_root_id;
++
++		if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
++		    && part_root_id == *root_id) {
++			pparts[i].name = "firmware";
++			break;
++		}
++	}
++}
++
+ static int parse_fixed_partitions(struct mtd_info *master,
+ 				  const struct mtd_partition **pparts,
+ 				  struct mtd_part_parser_data *data)
+@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct
+ 	struct device_node *pp;
+ 	int nr_parts, i, ret = 0;
+ 	bool dedicated = true;
++	uint8_t *proot_id = NULL;
++	struct device_node **part_nodes;
+ 
+ 	/* Pull of_node from the master device node */
+ 	mtd_node = mtd_get_of_node(master);
+@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct
+ 		return 0;
+ 
+ 	parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
+-	if (!parts)
++	part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);
++
++	if (!parts || !part_nodes)
+ 		return -ENOMEM;
+ 
+ 	i = 0;
+@@ -166,6 +202,11 @@ static int parse_fixed_partitions(struct
+ 		if (of_property_read_bool(pp, "slc-mode"))
+ 			parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;
+ 
++		if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
++			proot_id = brnboot_get_selected_root_part(master, parts[i].offset);
++
++		part_nodes[i] = pp;
++
+ 		i++;
+ 	}
+ 
+@@ -175,6 +216,11 @@ static int parse_fixed_partitions(struct
+ 	if (quirks && quirks->post_parse)
+ 		quirks->post_parse(master, parts, nr_parts);
+ 
++	if (proot_id)
++		brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);
++
++	kfree(part_nodes);
++
+ 	*pparts = parts;
+ 	return nr_parts;
+ 
+@@ -185,6 +231,7 @@ ofpart_fail:
+ ofpart_none:
+ 	of_node_put(pp);
+ 	kfree(parts);
++	kfree(part_nodes);
+ 	return ret;
+ }
+ 
diff --git a/target/linux/lantiq/patches-6.6/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-6.6/0151-lantiq-ifxmips_pcie-use-of.patch
new file mode 100644
index 0000000000..b83bf992a6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0151-lantiq-ifxmips_pcie-use-of.patch
@@ -0,0 +1,486 @@
+From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 14 Oct 2014 11:04:00 +0000
+Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/Makefile           |   2 +-
+ arch/mips/pci/ifxmips_pcie.c     | 151 +++++++++++++++++++++++++++----
+ arch/mips/pci/ifxmips_pcie_vr9.h | 105 ---------------------
+ 3 files changed, 133 insertions(+), 125 deletions(-)
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,7 +41,7 @@ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+-obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ)	+= ifxmips_pcie.o fixup-lantiq-pcie.o
+ obj-$(CONFIG_PCIE_LANTIQ_MSI)	+= pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+--- a/arch/mips/pci/ifxmips_pcie.c
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -16,8 +16,15 @@
+ #include <asm/paccess.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ 
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++
+ #include "ifxmips_pcie.h"
+ #include "ifxmips_pcie_reg.h"
+ 
+@@ -25,11 +32,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+ 
+-#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +42,30 @@
+ static DEFINE_SPINLOCK(ifx_pcie_lock);
+ 
+ u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++static int pcie_reset_gpio;
++static struct phy *ltq_pcie_phy;
++static struct reset_control *ltq_pcie_reset;
++static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
+ 
+ static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
+     {
+         .ir_irq = {
+-            .irq  = IFX_PCIE_IR,
+             .name = "ifx_pcie_rc0",
+         },
+ 
+         .legacy_irq = {
+             {
+                 .irq_bit = PCIE_IRN_INTA,
+-                .irq     = IFX_PCIE_INTA,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTB,
+-                .irq     = IFX_PCIE_INTB,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTC,
+-                .irq     = IFX_PCIE_INTC,
+             },
+             {
+                 .irq_bit = PCIE_IRN_INTD,
+-                .irq     = IFX_PCIE_INTD,
+             },
+         },
+     },
+@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
+ 	printk("%s", buf);
+ }
+ 
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++	gpio_direction_output(pcie_reset_gpio, 1);
++	gpio_set_value(pcie_reset_gpio, 1);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++	gpio_set_value(pcie_reset_gpio, 0);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++	mdelay(100);
++	gpio_direction_output(pcie_reset_gpio, 1);
++}
+ 
+ static inline int pcie_ltssm_enable(int pcie_port)
+ {
+@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+ 	ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ 		pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ 	if (ret)
+-		printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++		printk(KERN_ERR "%s request irq %d failed\n", __func__,
++		       pcie_irqs[pcie_port].ir_irq.irq);
+ 
+ 	return ret;
+ }
+@@ -988,10 +1007,26 @@ int  ifx_pcie_bios_plat_dev_init(struct
+ static int
+ pcie_rc_initialize(int pcie_port)
+ {
+-	int i;
++	int i, ret;
+ #define IFX_PCIE_PHY_LOOP_CNT  5
+ 
+-	pcie_rcu_endian_setup(pcie_port);
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
++			   IFX_RCU_AHB_BE_PCIE_M);
++
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   IFX_RCU_AHB_BE_PCIE_S);
++       if (switch_pcie_endianess) {
++	        regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++			           IFX_RCU_AHB_BE_XBAR_S);
++       }
++#else
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++			   0x0);
++#endif
++
++	regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
++			   0x0);
+ 
+ 	pcie_ep_gpio_rst_init(pcie_port);
+ 
+@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
+ 	* reset PCIe PHY will solve this issue 
+ 	*/
+ 	for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
+-		/* Disable PCIe PHY Analog part for sanity check */
+-		pcie_phy_pmu_disable(pcie_port);
+-
+-		pcie_phy_rst_assert(pcie_port);
+-		pcie_phy_rst_deassert(pcie_port);
+-
+-		/* Make sure PHY PLL is stable */
+-		udelay(20);
+-
+-		/* PCIe Core reset enabled, low active, sw programmed */
+-		pcie_core_rst_assert(pcie_port);
++		ret = phy_init(ltq_pcie_phy);
++		if (ret)
++			continue;
+ 
+ 		/* Put PCIe EP in reset status */
+ 		pcie_device_rst_assert(pcie_port);
+ 
+-		/* PCI PHY & Core reset disabled, high active, sw programmed */
+-		pcie_core_rst_deassert(pcie_port);
++		udelay(1);
++		reset_control_deassert(ltq_pcie_reset);
+ 
+-		/* Already in a quiet state, program PLL, enable PHY, check ready bit */
+-		pcie_phy_clock_mode_setup(pcie_port);
++		ret = phy_power_on(ltq_pcie_phy);
++		if (ret) {
++			phy_exit(ltq_pcie_phy);
++			continue;
++		}
+ 
+ 		/* Enable PCIe PHY and Clock */
+ 		pcie_core_pmu_setup(pcie_port);
+@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
+ 		/* Once link is up, break out */
+ 		if (pcie_app_loigc_setup(pcie_port) == 0)
+ 			break;
++
++		phy_power_off(ltq_pcie_phy);
++		reset_control_assert(ltq_pcie_reset);
++		phy_exit(ltq_pcie_phy);
+ 	}
+ 	if (i >= IFX_PCIE_PHY_LOOP_CNT) {
+ 		printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
+@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
+ 	return 0;
+ }
+ 
+-static int __init ifx_pcie_bios_init(void)
++static int ifx_pcie_bios_probe(struct platform_device *pdev)
+ {
++    struct device_node *node = pdev->dev.of_node;
+     void __iomem *io_map_base;
+     int pcie_port;
+     int startup_port;
++    struct device_node *np;
++    struct pci_bus *bus;
++
++    /*
++     * In case a PCI device is physical present, the Lantiq PCI driver need
++     * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
++     * will work.
++     *
++     * In case the lantiq PCI driver is enabled in the device tree, check if
++     * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
++     * registered.
++     *
++     * It will fail if there is another PCI controller, this controller is
++     * registered before the Lantiq PCIe driver is probe and the lantiq PCI
++     */
++    np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
++
++    if (of_device_is_available(np)) {
++        bus = pci_find_next_bus(bus);
++
++        if (!bus)
++	     return -EPROBE_DEFER;
++    }
+ 
+     /* Enable AHB Master/ Slave */
+     pcie_ahb_pmu_setup();
+ 
+     startup_port = IFX_PCIE_PORT0;
+-    
++
++    ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
++    if (IS_ERR(ltq_pcie_phy))
++        return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++                             "failed to get the PCIe PHY\n");
++
++    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
++    if (IS_ERR(ltq_pcie_reset)) {
++        dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
++        return PTR_ERR(ltq_pcie_reset);
++    }
++
++    if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++        switch_pcie_endianess = true;
++        dev_info(&pdev->dev, "switch pcie endianess requested\n");
++    } else {
++        switch_pcie_endianess = false;
++    }
++
++    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
++    if (IS_ERR(ltq_rcu_regmap))
++        return PTR_ERR(ltq_rcu_regmap);
++
++    pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
++    if (gpio_is_valid(pcie_reset_gpio)) {
++        int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
++        if (ret) {
++            dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
++            return ret;
++        }
++        gpio_direction_output(pcie_reset_gpio, 1);
++    }
++
+     for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
+ 	if (pcie_rc_initialize(pcie_port) == 0) {
+ 	    IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", 
+@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+                 IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
+                 return -ENOMEM;
+             }
++            pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++            if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++                return pcie_irqs[pcie_port].ir_irq.irq;
++
++            for (int i = 0; i <= 3; i++){
++                pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++                if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++                    return pcie_irqs[pcie_port].legacy_irq[i].irq;
++            }
++
+             ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++            pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
+ 
+             register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
+             /* XXX, clear error status */
+@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi
+ 
+     return 0;
+ }
++
++static const struct of_device_id ifxmips_pcie_match[] = {
++        { .compatible = "lantiq,pcie-xrx200" },
++        {},
++};
++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
++
++static struct platform_driver ltq_pci_driver = {
++        .probe = ifx_pcie_bios_probe,
++        .driver = {
++                .name = "pcie-xrx200",
++                .owner = THIS_MODULE,
++                .of_match_table = ifxmips_pcie_match,
++        },
++};
++
++int __init ifx_pcie_bios_init(void)
++{
++        int ret = platform_driver_register(&ltq_pci_driver);
++        if (ret)
++                pr_info("pcie-xrx200: Error registering platform driver!");
++        return ret;
++}
++
+ arch_initcall(ifx_pcie_bios_init);
+ 
+ MODULE_LICENSE("GPL");
+--- a/arch/mips/pci/ifxmips_pcie_vr9.h
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -22,8 +22,6 @@
+ #include <linux/gpio.h>
+ #include <lantiq_soc.h>
+ 
+-#define IFX_PCIE_GPIO_RESET  494
+-
+ #define IFX_REG_R32    ltq_r32
+ #define IFX_REG_W32    ltq_w32
+ #define CONFIG_IFX_PCIE_HW_SWAP
+@@ -54,21 +52,6 @@
+ #define OUT			((volatile u32*)(IFX_GPIO + 0x0070))
+ 
+ 
+-static inline void pcie_ep_gpio_rst_init(int pcie_port)
+-{
+-
+-	gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-
+-/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
+-}
+-
+ static inline void pcie_ahb_pmu_setup(void) 
+ {
+ 	/* Enable AHB bus master/slave */
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
+     //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_rcu_endian_setup(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-#ifdef CONFIG_IFX_PCIE_HW_SWAP
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg |= IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#else 
+-    reg |= IFX_RCU_AHB_BE_PCIE_M;
+-    reg &= ~IFX_RCU_AHB_BE_PCIE_S;
+-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-    IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
+-}
+-
+ static inline void pcie_phy_pmu_enable(int pcie_port)
+ {
+ 	struct clk *clk;
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
+ //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
+ }
+ 
+-static inline void pcie_pdi_big_endian(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* SRAM2PDI endianness control. */
+-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-    /* Config AHB->PCIe and PDI endianness */
+-    reg |= IFX_RCU_AHB_BE_PCIE_PDI;
+-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-}
+-
+ static inline void pcie_pdi_pmu_enable(int pcie_port)
+ {
+     /* Enable PDI to access PCIe PHY register */
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
+     //PDI_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+ 
+-static inline void pcie_core_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-
+-    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */
+-    reg |= 0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_core_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    /* Reset PCIe PHY & Core, bit 22 */
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00400000;
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_assert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg |= 0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_deassert(int pcie_port)
+-{
+-    u32 reg;
+-
+-    /* Make sure one micro-second delay */
+-    udelay(1);
+-
+-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-    reg &= ~0x00001000; /* Bit 12 */
+-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_device_rst_assert(int pcie_port)
+-{
+-	gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
+-//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+-static inline void pcie_device_rst_deassert(int pcie_port)
+-{
+-    mdelay(100);
+-	gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+ static inline void pcie_core_pmu_setup(int pcie_port)
+ {
+ 	struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+ 
+ typedef struct ifx_pcie_ir_irq {
+-    const unsigned int irq;
++    unsigned int irq;
+     const char name[16];
+ }ifx_pcie_ir_irq_t;
+ 
+ typedef struct ifx_pcie_legacy_irq{
+     const u32 irq_bit;
+-    const int irq;
++    int irq;
+ }ifx_pcie_legacy_irq_t;
+ 
+ typedef struct ifx_pcie_irq {
diff --git a/target/linux/lantiq/patches-6.6/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-6.6/0152-lantiq-VPE.patch
new file mode 100644
index 0000000000..e83094f28c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0152-lantiq-VPE.patch
@@ -0,0 +1,187 @@
+From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Thu, 20 Oct 2016 21:32:00 +0200
+Subject: [PATCH] lantiq: vpe
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/Kconfig                  |  6 ++++
+ arch/mips/include/asm/mipsmtregs.h |  5 ++++
+ arch/mips/include/asm/vpe.h        |  9 ++++++
+ arch/mips/kernel/vpe-mt.c          | 47 ++++++++++++++++++++++++++++++
+ arch/mips/kernel/vpe.c             | 35 ++++++++++++++++++++++
+ arch/mips/lantiq/prom.c            |  4 +++
+ 6 files changed, 106 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2259,6 +2259,12 @@ config MIPS_VPE_LOADER
+ 	  Includes a loader for loading an elf relocatable object
+ 	  onto another VPE and running it.
+ 
++config IFX_VPE_EXT
++	bool "IFX APRP Extensions"
++	depends on MIPS_VPE_LOADER
++	help
++	  IFX included extensions in APRP
++
+ config MIPS_VPE_LOADER_MT
+ 	bool
+ 	default "y"
+--- a/arch/mips/include/asm/mipsmtregs.h
++++ b/arch/mips/include/asm/mipsmtregs.h
+@@ -31,6 +31,9 @@
+ #define read_c0_vpeconf1()		__read_32bit_c0_register($1, 3)
+ #define write_c0_vpeconf1(val)		__write_32bit_c0_register($1, 3, val)
+ 
++#define read_c0_vpeopt()		__read_32bit_c0_register($1, 7)
++#define write_c0_vpeopt(val)		__write_32bit_c0_register($1, 7, val)
++
+ #define read_c0_tcstatus()		__read_32bit_c0_register($2, 1)
+ #define write_c0_tcstatus(val)		__write_32bit_c0_register($2, 1, val)
+ 
+@@ -377,6 +380,8 @@ do {									\
+ #define write_vpe_c0_vpeconf0(val)	mttc0(1, 2, val)
+ #define read_vpe_c0_vpeconf1()		mftc0(1, 3)
+ #define write_vpe_c0_vpeconf1(val)	mttc0(1, 3, val)
++#define read_vpe_c0_vpeopt()		mftc0(1, 7)
++#define write_vpe_c0_vpeopt(val)	mttc0(1, 7, val)
+ #define read_vpe_c0_count()		mftc0(9, 0)
+ #define write_vpe_c0_count(val)		mttc0(9, 0, val)
+ #define read_vpe_c0_status()		mftc0(12, 0)
+--- a/arch/mips/include/asm/vpe.h
++++ b/arch/mips/include/asm/vpe.h
+@@ -119,4 +119,13 @@ void cleanup_tc(struct tc *tc);
+ 
+ int __init vpe_module_init(void);
+ void __exit vpe_module_exit(void);
++
++/* For the explanation of the APIs please refer the section "MT APRP Kernel
++ * Programming" in AR9 SW Architecture Specification
++ */
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
++int32_t vpe1_sw_stop(uint32_t flags);
++uint32_t vpe1_get_load_addr(uint32_t flags);
++uint32_t vpe1_get_max_mem(uint32_t flags);
++
+ #endif /* _ASM_VPE_H */
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -414,6 +414,8 @@ int __init vpe_module_init(void)
+ 			}
+ 
+ 			v->ntcs = hw_tcs - aprp_cpu_index();
++			write_tc_c0_tcbind((read_tc_c0_tcbind() &
++						~TCBIND_CURVPE) | 1);
+ 
+ 			/* add the tc to the list of this vpe's tc's. */
+ 			list_add(&t->tc, &v->tc);
+@@ -517,3 +519,47 @@ void __exit vpe_module_exit(void)
+ 			release_vpe(v);
+ 	}
+ }
++
++#ifdef CONFIG_IFX_VPE_EXT
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
++{
++	enum vpe_state state;
++	struct vpe *v = get_vpe(tclimit);
++	struct vpe_notifications *not;
++
++	if (tcmask || flags) {
++		pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
++		return -1;
++	}
++
++	state = xchg(&v->state, VPE_STATE_INUSE);
++	if (state != VPE_STATE_UNUSED) {
++		vpe_stop(v);
++
++		list_for_each_entry(not, &v->notify, list) {
++			not->stop(tclimit);
++		}
++	}
++
++	v->__start = (unsigned long)sw_start_addr;
++
++	if (!vpe_run(v)) {
++		pr_debug("VPE loader: VPE1 running successfully\n");
++		return 0;
++	}
++	return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_start);
++
++int32_t vpe1_sw_stop(uint32_t flags)
++{
++	struct vpe *v = get_vpe(tclimit);
++
++	if (!vpe_free(v)) {
++		pr_debug("RP Stopped\n");
++		return 0;
++	} else
++		return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_stop);
++#endif
+--- a/arch/mips/kernel/vpe.c
++++ b/arch/mips/kernel/vpe.c
+@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
+ 	.tc_list	= LIST_HEAD_INIT(vpecontrol.tc_list)
+ };
+ 
++#ifdef CONFIG_IFX_VPE_EXT
++unsigned int vpe1_load_addr;
++
++static int __init load_address(char *str)
++{
++	get_option(&str, &vpe1_load_addr);
++	return 1;
++}
++__setup("vpe1_load_addr=", load_address);
++
++static unsigned int vpe1_mem;
++static int __init vpe1mem(char *str)
++{
++	vpe1_mem = memparse(str, &str);
++	return 1;
++}
++__setup("vpe1_mem=", vpe1mem);
++
++uint32_t vpe1_get_load_addr(uint32_t flags)
++{
++	return vpe1_load_addr;
++}
++EXPORT_SYMBOL(vpe1_get_load_addr);
++
++uint32_t vpe1_get_max_mem(uint32_t flags)
++{
++	if (!vpe1_mem)
++		return P_SIZE;
++	else
++		return vpe1_mem;
++}
++EXPORT_SYMBOL(vpe1_get_max_mem);
++
++#endif
++
+ /* get the vpe associated with this minor */
+ struct vpe *get_vpe(int minor)
+ {
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -36,10 +36,14 @@ extern const struct plat_smp_ops vsmp_sm
+ static struct plat_smp_ops lantiq_smp_ops;
+ #endif
+ 
++/* for Multithreading (APRP), vpe.c will use it */
++unsigned long cp0_memsize;
++
+ const char *get_system_type(void)
+ {
+ 	return soc_info.sys_type;
+ }
++EXPORT_SYMBOL(ltq_soc_type);
+ 
+ int ltq_soc_type(void)
+ {
diff --git a/target/linux/lantiq/patches-6.6/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-6.6/0154-lantiq-pci-bar11mask-fix.patch
new file mode 100644
index 0000000000..9214f786d7
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0154-lantiq-pci-bar11mask-fix.patch
@@ -0,0 +1,32 @@
+From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 8 Nov 2016 17:38:00 +0100
+Subject: [PATCH] lantiq: pci: bar11mask fix
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/pci-lantiq.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -59,6 +59,8 @@
+ #define ltq_pci_cfg_w32(x, y)	ltq_w32((x), ltq_pci_mapped_cfg + (y))
+ #define ltq_pci_cfg_r32(x)	ltq_r32(ltq_pci_mapped_cfg + (x))
+ 
++extern u32 max_low_pfn;
++
+ __iomem void *ltq_pci_mapped_cfg;
+ static __iomem void *ltq_pci_membase;
+ 
+@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi
+ 	u32 mem, bar11mask;
+ 
+ 	/* BAR11MASK value depends on available memory on system. */
+-	mem = get_num_physpages() * PAGE_SIZE;
+-	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
++	mem = max_low_pfn << PAGE_SHIFT;
++	bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;
+ 
+ 	return bar11mask;
+ }
diff --git a/target/linux/lantiq/patches-6.6/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-6.6/0155-lantiq-VPE-nosmp.patch
new file mode 100644
index 0000000000..6426ee717b
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0155-lantiq-VPE-nosmp.patch
@@ -0,0 +1,24 @@
+From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Mon, 13 Mar 2017 23:42:00 +0100
+Subject: [PATCH] lantiq: vpe nosmp
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/kernel/vpe-mt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -130,7 +130,10 @@ int vpe_run(struct vpe *v)
+ 	 * kernels need to turn it on, even if that wasn't the pre-dvpe() state.
+ 	 */
+ #ifdef CONFIG_SMP
+-	evpe(vpeflags);
++	if (!setup_max_cpus) /* nosmp is set */
++		evpe(EVPE_ENABLE);
++	else
++		evpe(vpeflags);
+ #else
+ 	evpe(EVPE_ENABLE);
+ #endif
diff --git a/target/linux/lantiq/patches-6.6/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-6.6/0160-owrt-lantiq-multiple-flash.patch
new file mode 100644
index 0000000000..1556a32aa6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0160-owrt-lantiq-multiple-flash.patch
@@ -0,0 +1,228 @@
+From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001
+From: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+Date: Fri, 14 Nov 2014 17:06:00 +0000
+Subject: [PATCH] owrt: lantiq: multiple flash
+
+Concatenate multiple flash chips for lantiq-flash.
+
+Signed-off-by: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+---
+ drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++-----------
+ 1 file changed, 109 insertions(+), 59 deletions(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/cfi.h>
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/mtd/concat.h>
+ #include <linux/of.h>
+ 
+ #include <lantiq_soc.h>
+@@ -36,13 +37,16 @@ enum {
+ 	LTQ_NOR_NORMAL
+ };
+ 
++#define MAX_RESOURCES		4
++
+ struct ltq_mtd {
+-	struct resource *res;
+-	struct mtd_info *mtd;
+-	struct map_info *map;
++	struct mtd_info *mtd[MAX_RESOURCES];
++	struct mtd_info	*cmtd;
++	struct map_info map[MAX_RESOURCES];
+ };
+ 
+ static const char ltq_map_name[] = "ltq_nor";
++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL };
+ 
+ static map_word
+ ltq_read16(struct map_info *map, unsigned long adr)
+@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign
+ }
+ 
+ static int
++ltq_mtd_remove(struct platform_device *pdev)
++{
++	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
++	int i;
++
++	if (ltq_mtd == NULL)
++		return 0;
++
++	if (ltq_mtd->cmtd) {
++		mtd_device_unregister(ltq_mtd->cmtd);
++		if (ltq_mtd->cmtd != ltq_mtd->mtd[0])
++			mtd_concat_destroy(ltq_mtd->cmtd);
++	}
++
++	for (i = 0; i < MAX_RESOURCES; i++) {
++		if (ltq_mtd->mtd[i] != NULL)
++			map_destroy(ltq_mtd->mtd[i]);
++	}
++
++	kfree(ltq_mtd);
++
++	return 0;
++}
++
++static int
+ ltq_mtd_probe(struct platform_device *pdev)
+ {
+ 	struct ltq_mtd *ltq_mtd;
+ 	struct cfi_private *cfi;
+-	int err;
++	int err = 0;
++	int i;
++	int devices_found = 0;
++
++	static const char *rom_probe_types[] = {
++		"cfi_probe", "jedec_probe", NULL
++	};
++	const char **type;
+ 
+ 	ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
+ 	if (!ltq_mtd)
+@@ -118,70 +154,89 @@ ltq_mtd_probe(struct platform_device *pd
+ 
+ 	platform_set_drvdata(pdev, ltq_mtd);
+ 
+-	ltq_mtd->map->virt = devm_platform_get_and_ioremap_resource(pdev, 0, &ltq_mtd->res);
+-	if (IS_ERR(ltq_mtd->map->virt))
+-		return PTR_ERR(ltq_mtd->map->virt);
+-
+-	ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),
+-				    GFP_KERNEL);
+-	if (!ltq_mtd->map)
+-		return -ENOMEM;
+-
+-	if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+-		ltq_mtd->map->phys = NO_XIP;
+-	else
+-		ltq_mtd->map->phys = ltq_mtd->res->start;
+-	ltq_mtd->res->start;
+-	ltq_mtd->map->size = resource_size(ltq_mtd->res);
+-
+-	ltq_mtd->map->name = ltq_map_name;
+-	ltq_mtd->map->bankwidth = 2;
+-	ltq_mtd->map->read = ltq_read16;
+-	ltq_mtd->map->write = ltq_write16;
+-	ltq_mtd->map->copy_from = ltq_copy_from;
+-	ltq_mtd->map->copy_to = ltq_copy_to;
+-
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
+-	ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
+-	ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
+-
+-	if (!ltq_mtd->mtd) {
+-		dev_err(&pdev->dev, "probing failed\n");
+-		return -ENXIO;
++	for (i = 0; i < pdev->num_resources; i++) {
++		printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n",
++		       (unsigned long long)resource_size(&pdev->resource[i]),
++		       (unsigned long long)pdev->resource[i].start);
++	
++		if (!devm_request_mem_region(&pdev->dev,
++			pdev->resource[i].start,
++			resource_size(&pdev->resource[i]),
++			dev_name(&pdev->dev))) {
++			dev_err(&pdev->dev, "Could not reserve memory region\n");
++			return -ENOMEM;
++		}
++
++		ltq_mtd->map[i].name = ltq_map_name;
++		ltq_mtd->map[i].bankwidth = 2;
++		ltq_mtd->map[i].read = ltq_read16;
++		ltq_mtd->map[i].write = ltq_write16;
++		ltq_mtd->map[i].copy_from = ltq_copy_from;
++		ltq_mtd->map[i].copy_to = ltq_copy_to;
++
++		if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++			ltq_mtd->map[i].phys = NO_XIP;
++		else
++			ltq_mtd->map[i].phys = pdev->resource[i].start;
++		ltq_mtd->map[i].size = resource_size(&pdev->resource[i]);
++		ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,
++						 ltq_mtd->map[i].size);
++		if (IS_ERR(ltq_mtd->map[i].virt))
++			return PTR_ERR(ltq_mtd->map[i].virt);
++
++		if (ltq_mtd->map[i].virt == NULL) {
++			dev_err(&pdev->dev, "Failed to ioremap flash region\n");
++			err = PTR_ERR(ltq_mtd->map[i].virt);
++			goto err_out;
++		}
++
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;
++		for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)
++			ltq_mtd->mtd[i] = do_map_probe(*type, &ltq_mtd->map[i]);
++		ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;
++
++		if (!ltq_mtd->mtd[i]) {
++			dev_err(&pdev->dev, "probing failed\n");
++			return -ENXIO;
++		} else {
++			devices_found++;
++		}
++
++		ltq_mtd->mtd[i]->owner = THIS_MODULE;
++		ltq_mtd->mtd[i]->dev.parent = &pdev->dev;
++
++		cfi = ltq_mtd->map[i].fldrv_priv;
++		cfi->addr_unlock1 ^= 1;
++		cfi->addr_unlock2 ^= 1;
+ 	}
+ 
+-	ltq_mtd->mtd->dev.parent = &pdev->dev;
+-	mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);
++	if (devices_found == 1) {
++		ltq_mtd->cmtd = ltq_mtd->mtd[0];
++	} else if (devices_found > 1) {
++		/*
++		 * We detected multiple devices. Concatenate them together.
++		 */
++		ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
++		if (ltq_mtd->cmtd == NULL)
++			err = -ENXIO;
++	}
+ 
+-	cfi = ltq_mtd->map->fldrv_priv;
+-	cfi->addr_unlock1 ^= 1;
+-	cfi->addr_unlock2 ^= 1;
++	ltq_mtd->cmtd->dev.parent = &pdev->dev;
++	mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node);
+ 
+-	err = mtd_device_register(ltq_mtd->mtd, NULL, 0);
++	err = mtd_device_register(ltq_mtd->cmtd, NULL, 0);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "failed to add partitions\n");
+-		goto err_destroy;
++		goto err_out;
+ 	}
+ 
+ 	return 0;
+ 
+-err_destroy:
+-	map_destroy(ltq_mtd->mtd);
++err_out:
++	ltq_mtd_remove(pdev);
+ 	return err;
+ }
+ 
+-static int
+-ltq_mtd_remove(struct platform_device *pdev)
+-{
+-	struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
+-
+-	if (ltq_mtd && ltq_mtd->mtd) {
+-		mtd_device_unregister(ltq_mtd->mtd);
+-		map_destroy(ltq_mtd->mtd);
+-	}
+-	return 0;
+-}
+-
+ static const struct of_device_id ltq_mtd_match[] = {
+ 	{ .compatible = "lantiq,nor" },
+ 	{},
diff --git a/target/linux/lantiq/patches-6.6/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-6.6/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
new file mode 100644
index 0000000000..6db051b6a9
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch
@@ -0,0 +1,99 @@
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -15,6 +15,10 @@
+ 
+ static unsigned int *cp1_base;
+ 
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ 	if (!cp1_base)
+@@ -24,6 +28,33 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+ 
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++	if (!ad0_irq)
++		panic("no ad0 irq was set\n");
++
++	return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++	if (!ad1_irq)
++		panic("no ad1 irq was set\n");
++
++	return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++	if (!vc_irq[idx])
++		panic("no vc%d irq was set\n", idx);
++
++	return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE       (1 << 20)
+@@ -31,11 +62,33 @@ static int vmmc_probe(struct platform_de
+ 	int gpio_count;
+ 	dma_addr_t dma;
+ 	int error;
++	int i;
+ 
+ 	cp1_base =
+ 		(void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ 						    &dma, GFP_KERNEL));
+ 
++	ad0_irq = platform_get_irq(pdev, 4);
++	if (ad0_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++		return ad0_irq;
++	}
++
++	ad1_irq = platform_get_irq(pdev, 5);
++	if (ad1_irq < 0) {
++		dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++		return ad1_irq;
++	}
++
++	for (i = 0; i < 4; i++) {
++	vc_irq[i] = platform_get_irq(pdev, i);
++		if (vc_irq[i] < 0) {
++			dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++				i, vc_irq[i]);
++			return vc_irq[i];
++		}
++	}
++
+ 	gpio_count = gpiod_count(&pdev->dev, NULL);
+ 	while (gpio_count > 0) {
+ 		gpio = devm_gpiod_get_index(&pdev->dev,
diff --git a/target/linux/lantiq/patches-6.6/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-6.6/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
new file mode 100644
index 0000000000..7abe1fbbeb
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch
@@ -0,0 +1,21 @@
+From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001
+From: Matti Laakso <malaakso@elisanet.fi>
+Date: Sat, 14 Feb 2015 20:48:00 +0000
+Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes
+
+Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -40,7 +40,7 @@
+ /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
+ 
+ // debugging, turns off buffer write mode if set to 1
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ /* Intel chips */
+ #define I82802AB	0x00ad
diff --git a/target/linux/lantiq/patches-6.6/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-6.6/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch
new file mode 100644
index 0000000000..459e415e1b
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch
@@ -0,0 +1,40 @@
+From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] xrx200: add gphy clk src device tree binding
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -439,6 +439,20 @@ static void clkdev_add_clkout(void)
+ 	}
+ }
+ 
++static void set_phy_clock_source(struct device_node *np_cgu)
++{
++	u32 phy_clk_src, ifcc;
++
++	if (!np_cgu)
++		return;
++
++	if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
++		return;
++
++	ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
++	ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
++}
++
+ /* bring up all register ranges that we need for basic system control */
+ void __init ltq_soc_init(void)
+ {
+@@ -608,4 +622,6 @@ void __init ltq_soc_init(void)
+ 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ 	}
+ 	usb_set_clock();
++
++	set_phy_clock_source(np_cgu);
+ }
diff --git a/target/linux/lantiq/patches-6.6/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch b/target/linux/lantiq/patches-6.6/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch
new file mode 100644
index 0000000000..1eadb56dd8
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch
@@ -0,0 +1,62 @@
+From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001
+From: Aleksander Jan Bajkowski <olek2@wp.pl>
+Date: Sat, 6 May 2023 14:32:00 +0200
+Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if
+ FORCE_WORD_WRITE is 1
+
+Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1.
+So the compile warning messages are output if FORCE_WORD_WRITE is 1. To
+resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1.
+
+This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f.
+
+Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -62,8 +62,10 @@
+ 
+ static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+ static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *);
++#endif
+ static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_intelext_sync (struct mtd_info *);
+ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+@@ -305,6 +307,7 @@ static void fixup_use_point(struct mtd_i
+ 	}
+ }
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -315,6 +318,7 @@ static void fixup_use_write_buffers(stru
+ 		mtd->_writev = cfi_intelext_writev;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Some chips power-up with all sectors locked by default.
+@@ -1720,6 +1724,7 @@ static int cfi_intelext_write_words (str
+ }
+ 
+ 
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const struct kvec **pvec,
+ 				    unsigned long *pvec_seek, int len)
+@@ -1948,6 +1953,7 @@ static int cfi_intelext_write_buffers (s
+ 
+ 	return cfi_intelext_writev(mtd, &vec, 1, to, retlen);
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
+ 				      unsigned long adr, int len, void *thunk)
diff --git a/target/linux/lantiq/patches-6.6/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch b/target/linux/lantiq/patches-6.6/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch
new file mode 100644
index 0000000000..663b0dbfb3
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch
@@ -0,0 +1,38 @@
+From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001
+From: Thomas Nixon <tom@tomn.co.uk>
+Date: Sun, 26 Mar 2023 11:08:49 +0100
+Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock
+
+The nand driver normally while waiting for the device to become ready;
+this is normally fine, but xway_nand holds the ebu_lock spinlock, and
+this can cause lockups if other threads which use ebu_lock are
+interleaved. Fix this by waiting instead of polling.
+
+This mainly showed up as crashes in ath9k_pci_owl_loader (see
+https://github.com/openwrt/openwrt/issues/9829 ), but turning on
+spinlock debugging shows this happening in other places too.
+
+This doesn't seem to measurably impact boot time.
+
+Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
+---
+ drivers/mtd/nand/raw/xway_nand.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -176,7 +176,13 @@ static void xway_cmd_ctrl(struct nand_ch
+ 
+ static int xway_dev_ready(struct nand_chip *chip)
+ {
+-	return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
++	/*
++	 * wait until ready, as otherwise the driver will yield in nand_wait or
++	 * nand_wait_ready, which is a bad idea when we're holding ebu_lock
++	 */
++	while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++		cpu_relax();
++	return 1;
+ }
+ 
+ static unsigned char xway_read_byte(struct nand_chip *chip)
diff --git a/target/linux/lantiq/patches-6.6/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-6.6/0701-NET-lantiq-etop-of-mido.patch
new file mode 100644
index 0000000000..19c027b9f8
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0701-NET-lantiq-etop-of-mido.patch
@@ -0,0 +1,47 @@
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: Johann Neuhauser <johann@it-neuhauser.de>
+Date: Thu, 17 May 2018 19:12:35 +0200
+Subject: [PATCH] net: lantiq_etop: of mdio
+
+Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
+---
+ drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -31,6 +31,7 @@
+ #include <linux/of_net.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/of_mdio.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -558,7 +559,8 @@ static int
+ ltq_etop_mdio_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+-	int err;
++	struct device_node *mdio_np = NULL;
++	int err, ret;
+ 
+ 	priv->mii_bus = mdiobus_alloc();
+ 	if (!priv->mii_bus) {
+@@ -578,7 +580,15 @@ ltq_etop_mdio_init(struct net_device *de
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ 		 priv->pdev->name, priv->pdev->id);
+-	if (mdiobus_register(priv->mii_bus)) {
++
++	mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
++
++	if (mdio_np)
++		ret = of_mdiobus_register(priv->mii_bus, mdio_np);
++	else
++		ret = mdiobus_register(priv->mii_bus);
++
++	if (ret) {
+ 		err = -ENXIO;
+ 		goto err_out_free_mdiobus;
+ 	}
diff --git a/target/linux/lantiq/patches-6.6/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch b/target/linux/lantiq/patches-6.6/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
new file mode 100644
index 0000000000..c337c564b6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0731-dt-bindings-net-dsa-lantiq_gswip-Add-missing-phy-mod.patch
@@ -0,0 +1,32 @@
+From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:52:25 +0200
+Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing
+ phy-mode and fixed-link
+
+The CPU port has to specify a phy-mode and either a phy or a fixed-link.
+Since GSWIP is connected using a SoC internal protocol there's no PHY
+involved. Add phy-mode = "internal" and a fixed-link to describe the
+communication between the PMAC (Ethernet controller) and GSWIP switch.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+@@ -96,7 +96,13 @@ switch@e108000 {
+ 
+ 		port@6 {
+ 			reg = <0x6>;
++			phy-mode = "internal";
+ 			ethernet = <&eth0>;
++
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/lantiq/patches-6.6/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch b/target/linux/lantiq/patches-6.6/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
new file mode 100644
index 0000000000..4800ee1dd2
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0732-net-dsa-lantiq_gswip-Only-allow-phy-mode-internal-on.patch
@@ -0,0 +1,33 @@
+From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:59:35 +0200
+Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode =
+ "internal" on the CPU port
+
+Add the CPU port to gswip_xrx200_phylink_get_caps() and
+gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus,
+so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1509,6 +1509,7 @@ static void gswip_xrx200_phylink_get_cap
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
+ 		break;
+@@ -1540,6 +1541,7 @@ static void gswip_xrx300_phylink_get_cap
+ 	case 2:
+ 	case 3:
+ 	case 4:
++	case 6:
+ 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ 			  config->supported_interfaces);
+ 		break;
diff --git a/target/linux/lantiq/patches-6.6/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch b/target/linux/lantiq/patches-6.6/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
new file mode 100644
index 0000000000..f30e7ab00c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0733-net-dsa-lantiq_gswip-Use-dev_err_probe-where-appropr.patch
@@ -0,0 +1,145 @@
+From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 31 Jul 2022 22:54:52 +0200
+Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where
+ appropriate
+
+dev_err_probe() can be used to simplify the existing code. Also it means
+we get rid of the following warning which is seen whenever the PMAC
+(Ethernet controller which connects to GSWIP's CPU port) has not been
+probed yet:
+  gswip 1e108000.switch: dsa switch register failed: -517
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------
+ 1 file changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1919,11 +1919,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 	msleep(200);
+ 
+ 	ret = request_firmware(&fw, gphy_fw->fw_name, dev);
+-	if (ret) {
+-		dev_err(dev, "failed to load firmware: %s, error: %i\n",
+-			gphy_fw->fw_name, ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
++				     gphy_fw->fw_name);
+ 
+ 	/* GPHY cores need the firmware code in a persistent and contiguous
+ 	 * memory area with a 16 kB boundary aligned start address.
+@@ -1936,9 +1934,9 @@ static int gswip_gphy_fw_load(struct gsw
+ 		dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ 		memcpy(fw_addr, fw->data, fw->size);
+ 	} else {
+-		dev_err(dev, "failed to alloc firmware memory\n");
+ 		release_firmware(fw);
+-		return -ENOMEM;
++		return dev_err_probe(dev, -ENOMEM,
++				     "failed to alloc firmware memory\n");
+ 	}
+ 
+ 	release_firmware(fw);
+@@ -1965,8 +1963,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 
+ 	gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
+ 	if (IS_ERR(gphy_fw->clk_gate)) {
+-		dev_err(dev, "Failed to lookup gate clock\n");
+-		return PTR_ERR(gphy_fw->clk_gate);
++		return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
++				     "Failed to lookup gate clock\n");
+ 	}
+ 
+ 	ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
+@@ -1986,8 +1984,8 @@ static int gswip_gphy_fw_probe(struct gs
+ 		gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
+ 		break;
+ 	default:
+-		dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+-		return -EINVAL;
++		return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
++				     gphy_mode);
+ 	}
+ 
+ 	gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
+@@ -2038,8 +2036,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 			priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ 			break;
+ 		default:
+-			dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-			return -ENOENT;
++			return dev_err_probe(dev, -ENOENT,
++					     "unknown GSWIP version: 0x%x",
++					     version);
+ 		}
+ 	}
+ 
+@@ -2047,10 +2046,9 @@ static int gswip_gphy_fw_list(struct gsw
+ 	if (match && match->data)
+ 		priv->gphy_fw_name_cfg = match->data;
+ 
+-	if (!priv->gphy_fw_name_cfg) {
+-		dev_err(dev, "GPHY compatible type not supported");
+-		return -ENOENT;
+-	}
++	if (!priv->gphy_fw_name_cfg)
++		return dev_err_probe(dev, -ENOENT,
++				     "GPHY compatible type not supported");
+ 
+ 	priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
+ 	if (!priv->num_gphy_fw)
+@@ -2150,8 +2148,8 @@ static int gswip_probe(struct platform_d
+ 			return -EINVAL;
+ 		break;
+ 	default:
+-		dev_err(dev, "unknown GSWIP version: 0x%x", version);
+-		return -ENOENT;
++		return dev_err_probe(dev, -ENOENT,
++				     "unknown GSWIP version: 0x%x", version);
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2159,10 +2157,9 @@ static int gswip_probe(struct platform_d
+ 	if (gphy_fw_np) {
+ 		err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
+ 		of_node_put(gphy_fw_np);
+-		if (err) {
+-			dev_err(dev, "gphy fw probe failed\n");
+-			return err;
+-		}
++		if (err)
++			return dev_err_probe(dev, err,
++					     "gphy fw probe failed\n");
+ 	}
+ 
+ 	/* bring up the mdio bus */
+@@ -2170,20 +2167,20 @@ static int gswip_probe(struct platform_d
+ 	if (mdio_np) {
+ 		err = gswip_mdio(priv, mdio_np);
+ 		if (err) {
+-			dev_err(dev, "mdio probe failed\n");
++			dev_err_probe(dev, err, "mdio probe failed\n");
+ 			goto put_mdio_node;
+ 		}
+ 	}
+ 
+ 	err = dsa_register_switch(priv->ds);
+ 	if (err) {
+-		dev_err(dev, "dsa switch register failed: %i\n", err);
++		dev_err_probe(dev, err, "dsa switch registration failed\n");
+ 		goto mdio_bus;
+ 	}
+ 	if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
+-		dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
+-			priv->hw_info->cpu_port);
+-		err = -EINVAL;
++		err = dev_err_probe(dev, -EINVAL,
++				    "wrong CPU port defined, HW only supports port: %i",
++				    priv->hw_info->cpu_port);
+ 		goto disable_switch;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.6/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch b/target/linux/lantiq/patches-6.6/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
new file mode 100644
index 0000000000..de8416380a
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0734-net-dsa-lantiq_gswip-Don-t-manually-call-gswip_port_.patch
@@ -0,0 +1,25 @@
+From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 28 Jul 2022 22:37:11 +0200
+Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call
+ gswip_port_enable()
+
+We don't need to manually call gswip_port_enable() from within
+gswip_setup() for the CPU port. DSA does this automatically for us.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -891,8 +891,6 @@ static int gswip_setup(struct dsa_switch
+ 
+ 	ds->mtu_enforcement_ingress = true;
+ 
+-	gswip_port_enable(ds, cpu_port, NULL);
+-
+ 	ds->configure_vlan_while_not_filtering = false;
+ 
+ 	return 0;
diff --git a/target/linux/lantiq/patches-6.6/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch b/target/linux/lantiq/patches-6.6/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
new file mode 100644
index 0000000000..a653c85841
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0735-net-dsa-lantiq_gswip-do-also-enable-or-disable-cpu-p.patch
@@ -0,0 +1,70 @@
+From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Fri, 10 May 2024 13:52:10 +0200
+Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port
+
+Before commit 74be4babe72f ("net: dsa: do not enable or disable non user
+ports"), gswip_port_enable/disable() were also executed for the cpu port
+in gswip_setup() which disabled the cpu port during initialization.
+
+Let's restore this by removing the dsa_is_user_port checks. Also, let's
+clean up the gswip_port_enable() function so that we only have to check
+for the cpu port once.
+
+Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports")
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ drivers/net/dsa/lantiq_gswip.c | 24 ++++++++----------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -688,13 +688,18 @@ static int gswip_port_enable(struct dsa_
+ 	struct gswip_priv *priv = ds->priv;
+ 	int err;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return 0;
+-
+ 	if (!dsa_is_cpu_port(ds, port)) {
++		u32 mdio_phy = 0;
++
+ 		err = gswip_add_single_port_br(priv, port, true);
+ 		if (err)
+ 			return err;
++
++		if (phydev)
++			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
++
++		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
++				GSWIP_MDIO_PHYp(port));
+ 	}
+ 
+ 	/* RMON Counter Enable for port */
+@@ -707,16 +712,6 @@ static int gswip_port_enable(struct dsa_
+ 	gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
+ 			  GSWIP_SDMA_PCTRLp(port));
+ 
+-	if (!dsa_is_cpu_port(ds, port)) {
+-		u32 mdio_phy = 0;
+-
+-		if (phydev)
+-			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
+-
+-		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
+-				GSWIP_MDIO_PHYp(port));
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -724,9 +719,6 @@ static void gswip_port_disable(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 
+-	if (!dsa_is_user_port(ds, port))
+-		return;
+-
+ 	gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
+ 			  GSWIP_FDMA_PCTRLp(port));
+ 	gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
diff --git a/target/linux/lantiq/patches-6.6/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch b/target/linux/lantiq/patches-6.6/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
new file mode 100644
index 0000000000..fd19982264
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0736-net-dsa-lantiq_gswip-Use-dsa_is_cpu_port-in-gswip_po.patch
@@ -0,0 +1,30 @@
+From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 18 May 2022 23:53:09 +0200
+Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in
+ gswip_port_change_mtu()
+
+Make the check for the CPU port in gswip_port_change_mtu() consistent
+with other areas of the driver by using dsa_is_cpu_port().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1457,12 +1457,11 @@ static int gswip_port_max_mtu(struct dsa
+ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ 	struct gswip_priv *priv = ds->priv;
+-	int cpu_port = priv->hw_info->cpu_port;
+ 
+ 	/* CPU port always has maximum mtu of user ports, so use it to set
+ 	 * switch frame size, including 8 byte special header.
+ 	 */
+-	if (port == cpu_port) {
++	if (dsa_is_cpu_port(ds, port)) {
+ 		new_mtu += 8;
+ 		gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
+ 			       GSWIP_MAC_FLEN);
diff --git a/target/linux/lantiq/patches-6.6/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch b/target/linux/lantiq/patches-6.6/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
new file mode 100644
index 0000000000..74e52d1d18
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0737-net-dsa-lantiq_gswip-Change-literal-6-to-ETH_ALEN.patch
@@ -0,0 +1,24 @@
+From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 17 May 2022 22:39:58 +0200
+Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN
+
+The addr variable in gswip_port_fdb_dump() stores a mac address. Use
+ETH_ALEN to make this consistent across other drivers.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1406,7 +1406,7 @@ static int gswip_port_fdb_dump(struct ds
+ {
+ 	struct gswip_priv *priv = ds->priv;
+ 	struct gswip_pce_table_entry mac_bridge = {0,};
+-	unsigned char addr[6];
++	unsigned char addr[ETH_ALEN];
+ 	int i;
+ 	int err;
+ 
diff --git a/target/linux/lantiq/patches-6.6/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch b/target/linux/lantiq/patches-6.6/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
new file mode 100644
index 0000000000..0ea90db483
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0738-net-dsa-lantiq_gswip-Consistently-use-macros-for-the.patch
@@ -0,0 +1,47 @@
+From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 21:23:49 +0200
+Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for
+ the mac bridge table
+
+Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout
+the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT()
+macro. This makes the driver code easier to understand.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -236,7 +236,8 @@
+ #define GSWIP_TABLE_ACTIVE_VLAN		0x01
+ #define GSWIP_TABLE_VLAN_MAPPING	0x02
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+-#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	0x01	/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
++#define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1300,7 +1301,8 @@ static void gswip_port_fast_age(struct d
+ 		if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
+ 			continue;
+ 
+-		if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
++		if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++				      mac_bridge.val[0]))
+ 			continue;
+ 
+ 		mac_bridge.valid = false;
+@@ -1438,7 +1440,8 @@ static int gswip_port_fdb_dump(struct ds
+ 					return err;
+ 			}
+ 		} else {
+-			if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
++			if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++					      mac_bridge.val[0])) {
+ 				err = cb(addr, 0, false, data);
+ 				if (err)
+ 					return err;
diff --git a/target/linux/lantiq/patches-6.6/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch b/target/linux/lantiq/patches-6.6/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
new file mode 100644
index 0000000000..1347a98c5c
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0739-net-dsa-lantiq_gswip-Forbid-gswip_add_single_port_br.patch
@@ -0,0 +1,26 @@
+From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:24:24 +0200
+Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid
+ gswip_add_single_port_br on the CPU port
+
+Calling gswip_add_single_port_br() with the CPU port would be a bug
+because then only the CPU port could talk to itself. Add the CPU port to
+the validation at the beginning of gswip_add_single_port_br().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -650,7 +650,7 @@ static int gswip_add_single_port_br(stru
+ 	unsigned int max_ports = priv->hw_info->max_ports;
+ 	int err;
+ 
+-	if (port >= max_ports) {
++	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+ 		dev_err(priv->dev, "single port for %i supported\n", port);
+ 		return -EIO;
+ 	}
diff --git a/target/linux/lantiq/patches-6.6/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch b/target/linux/lantiq/patches-6.6/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
new file mode 100644
index 0000000000..732588308e
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0740-net-dsa-lantiq_gswip-Fix-error-message-in-gswip_add_.patch
@@ -0,0 +1,26 @@
+From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:26:20 +0200
+Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in
+ gswip_add_single_port_br()
+
+The error message is printed when the port cannot be used. Update the
+error message to reflect that.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -651,7 +651,8 @@ static int gswip_add_single_port_br(stru
+ 	int err;
+ 
+ 	if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+-		dev_err(priv->dev, "single port for %i supported\n", port);
++		dev_err(priv->dev, "single port for %i is not supported\n",
++			port);
+ 		return -EIO;
+ 	}
+ 
diff --git a/target/linux/lantiq/patches-6.6/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch b/target/linux/lantiq/patches-6.6/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
new file mode 100644
index 0000000000..679dd53c47
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0741-net-dsa-lantiq_gswip-Fix-comments-in-gswip_port_vlan.patch
@@ -0,0 +1,36 @@
+From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:06:40 +0200
+Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in
+ gswip_port_vlan_filtering()
+
+Update the comments in gswip_port_vlan_filtering() so it's clear that
+there are two separate cases, one for "tag based VLAN" and another one
+for "port based VLAN".
+
+Suggested-by: Martin Schiller <ms@dev.tdt.de>
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -779,7 +779,7 @@ static int gswip_port_vlan_filtering(str
+ 	}
+ 
+ 	if (vlan_filtering) {
+-		/* Use port based VLAN tag */
++		/* Use tag based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_VSR,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+@@ -788,7 +788,7 @@ static int gswip_port_vlan_filtering(str
+ 		gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
+ 				  GSWIP_PCE_PCTRL_0p(port));
+ 	} else {
+-		/* Use port based VLAN tag */
++		/* Use port based VLAN */
+ 		gswip_switch_mask(priv,
+ 				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+ 				  GSWIP_PCE_VCTRL_VEMR,
diff --git a/target/linux/lantiq/patches-6.6/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch b/target/linux/lantiq/patches-6.6/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
new file mode 100644
index 0000000000..3d284c2ea6
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0742-net-dsa-lantiq_gswip-Add-and-use-a-GSWIP_TABLE_MAC_B.patch
@@ -0,0 +1,33 @@
+From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:19:05 +0200
+Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a
+ GSWIP_TABLE_MAC_BRIDGE_FID macro
+
+Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a
+macro so this becomes obvious when reading the driver code.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -238,6 +238,7 @@
+ #define GSWIP_TABLE_MAC_BRIDGE		0x0b
+ #define  GSWIP_TABLE_MAC_BRIDGE_STATIC	BIT(0)		/* Static not, aging entry */
+ #define  GSWIP_TABLE_MAC_BRIDGE_PORT	GENMASK(7, 4)	/* Port on learned entries */
++#define  GSWIP_TABLE_MAC_BRIDGE_FID	GENMASK(5, 0)	/* Filtering identifier */
+ 
+ #define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+ 
+@@ -1378,7 +1379,7 @@ static int gswip_port_fdb(struct dsa_swi
+ 	mac_bridge.key[0] = addr[5] | (addr[4] << 8);
+ 	mac_bridge.key[1] = addr[3] | (addr[2] << 8);
+ 	mac_bridge.key[2] = addr[1] | (addr[0] << 8);
+-	mac_bridge.key[3] = fid;
++	mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid);
+ 	mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
+ 	mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
+ 	mac_bridge.valid = add;
diff --git a/target/linux/lantiq/patches-6.6/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch b/target/linux/lantiq/patches-6.6/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
new file mode 100644
index 0000000000..5c756c5a19
--- /dev/null
+++ b/target/linux/lantiq/patches-6.6/0743-net-dsa-lantiq_gswip-Improve-error-message-in-gswip_.patch
@@ -0,0 +1,26 @@
+From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 16:31:57 +0200
+Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in
+ gswip_port_fdb()
+
+Print the port which is not found to be part of a bridge so it's easier
+to investigate the underlying issue.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1370,7 +1370,8 @@ static int gswip_port_fdb(struct dsa_swi
+ 	}
+ 
+ 	if (fid == -1) {
+-		dev_err(priv->dev, "Port not part of a bridge\n");
++		dev_err(priv->dev,
++			"Port %d is not known to be part of bridge\n", port);
+ 		return -EINVAL;
+ 	}
+ 
diff --git a/target/linux/lantiq/xrx200/config-5.15 b/target/linux/lantiq/xrx200/config-5.15
index 4dfd55274a..1b87ad65f0 100644
--- a/target/linux/lantiq/xrx200/config-5.15
+++ b/target/linux/lantiq/xrx200/config-5.15
@@ -1,11 +1,9 @@
 CONFIG_AT803X_PHY=y
 CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_MIPSR2_IRQ_VI=y
 CONFIG_CPU_RMAP=y
 CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LZO=y
@@ -20,8 +18,8 @@ CONFIG_ICPLUS_PHY=y
 CONFIG_IFX_VPE_EXT=y
 CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
 CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
 # CONFIG_ISDN is not set
 CONFIG_LANTIQ_XRX200=y
 CONFIG_LZO_COMPRESS=y
@@ -60,6 +58,7 @@ CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_LANTIQ=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
 CONFIG_PHY_LANTIQ_VRX200_PCIE=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_SUPPLY=y
@@ -74,8 +73,7 @@ CONFIG_SENSORS_LTQ_CPUTEMP=y
 CONFIG_SGL_ALLOC=y
 CONFIG_SMP=y
 CONFIG_SMP_UP=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
 CONFIG_SYNC_R4K=y
 CONFIG_SYS_SUPPORTS_SCHED_SMT=y
 CONFIG_SYS_SUPPORTS_SMP=y
diff --git a/target/linux/lantiq/xrx200/config-6.1 b/target/linux/lantiq/xrx200/config-6.1
new file mode 100644
index 0000000000..dc41fe0ca8
--- /dev/null
+++ b/target/linux/lantiq/xrx200/config-6.1
@@ -0,0 +1,96 @@
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GRO_CELLS=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IFX_VPE_EXT=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_FPAFF is not set
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_VPE_APSP_API=y
+CONFIG_MIPS_VPE_APSP_API_MT=y
+CONFIG_MIPS_VPE_LOADER=y
+CONFIG_MIPS_VPE_LOADER_MT=y
+CONFIG_MIPS_VPE_LOADER_TOM=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_LANTIQ_GSWIP=y
+CONFIG_NET_DSA_TAG_GSWIP=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_LANTIQ=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_LANTIQ_VRX200_PCIE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SENSORS_LTQ_CPUTEMP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/lantiq/xrx200/config-6.6 b/target/linux/lantiq/xrx200/config-6.6
new file mode 100644
index 0000000000..4819c962c8
--- /dev/null
+++ b/target/linux/lantiq/xrx200/config-6.6
@@ -0,0 +1,97 @@
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GRO_CELLS=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IFX_VPE_EXT=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_FPAFF is not set
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_VPE_APSP_API=y
+CONFIG_MIPS_VPE_APSP_API_MT=y
+CONFIG_MIPS_VPE_LOADER=y
+CONFIG_MIPS_VPE_LOADER_MT=y
+CONFIG_MIPS_VPE_LOADER_TOM=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_LANTIQ_GSWIP=y
+CONFIG_NET_DSA_TAG_GSWIP=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_LANTIQ=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_LANTIQ_VRX200_PCIE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SENSORS_LTQ_CPUTEMP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/lantiq/xway/config-5.15 b/target/linux/lantiq/xway/config-5.15
index 5a6f15dafd..696ce77860 100644
--- a/target/linux/lantiq/xway/config-5.15
+++ b/target/linux/lantiq/xway/config-5.15
@@ -1,9 +1,7 @@
 CONFIG_ADM6996_PHY=y
 CONFIG_AR8216_PHY=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_AT803X_PHY=y
 CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_MIPSR2_IRQ_VI=y
 CONFIG_CPU_RMAP=y
@@ -13,18 +11,15 @@ CONFIG_CRYPTO_HASH_INFO=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_FWNODE_MDIO=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GPIO_CDEV=y
 CONFIG_HW_RANDOM=y
 CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
 # CONFIG_ISDN is not set
 CONFIG_LANTIQ_ETOP=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
-CONFIG_MIPS_EBPF_JIT=y
 CONFIG_MIPS_MT=y
 CONFIG_MIPS_MT_FPAFF=y
 CONFIG_MIPS_MT_SMP=y
@@ -40,15 +35,14 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_BLOCK=y
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
 CONFIG_NLS=y
 CONFIG_NR_CPUS=2
 CONFIG_PADATA=y
 CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_LANTIQ=y
 CONFIG_PSB6970_PHY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
 CONFIG_REGULATOR=y
@@ -64,8 +58,6 @@ CONFIG_SGL_ALLOC=y
 CONFIG_SMP=y
 CONFIG_SMP_UP=y
 CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
 CONFIG_SWCONFIG=y
 CONFIG_SYNC_R4K=y
 CONFIG_SYS_SUPPORTS_SCHED_SMT=y
diff --git a/target/linux/lantiq/xway/config-6.1 b/target/linux/lantiq/xway/config-6.1
new file mode 100644
index 0000000000..1fc821575e
--- /dev/null
+++ b/target/linux/lantiq/xway/config-6.1
@@ -0,0 +1,81 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_AR8216_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_HW_RANDOM=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PSB6970_PHY=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/lantiq/xway/config-6.6 b/target/linux/lantiq/xway/config-6.6
new file mode 100644
index 0000000000..a51e0f9c2d
--- /dev/null
+++ b/target/linux/lantiq/xway/config-6.6
@@ -0,0 +1,82 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_AR8216_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_HW_RANDOM=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PSB6970_PHY=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/lantiq/xway_legacy/config-5.15 b/target/linux/lantiq/xway_legacy/config-5.15
index c177d2a935..ed3ecd8b4d 100644
--- a/target/linux/lantiq/xway_legacy/config-5.15
+++ b/target/linux/lantiq/xway_legacy/config-5.15
@@ -1,15 +1,13 @@
 CONFIG_ADM6996_PHY=y
 CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
 CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
 # CONFIG_GPIO_SYSFS is not set
 CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
 # CONFIG_ISDN is not set
 CONFIG_LANTIQ_ETOP=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
@@ -17,14 +15,13 @@ CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
 CONFIG_NLS=y
 CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_LANTIQ=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_RTL8306_PHY=y
 CONFIG_SGL_ALLOC=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
 CONFIG_SWCONFIG=y
 CONFIG_USB=y
 CONFIG_USB_COMMON=y
diff --git a/target/linux/lantiq/xway_legacy/config-6.1 b/target/linux/lantiq/xway_legacy/config-6.1
new file mode 100644
index 0000000000..ed3ecd8b4d
--- /dev/null
+++ b/target/linux/lantiq/xway_legacy/config-6.1
@@ -0,0 +1,30 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_NLS=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTL8306_PHY=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SWCONFIG=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/lantiq/xway_legacy/config-6.6 b/target/linux/lantiq/xway_legacy/config-6.6
new file mode 100644
index 0000000000..ed3ecd8b4d
--- /dev/null
+++ b/target/linux/lantiq/xway_legacy/config-6.6
@@ -0,0 +1,30 @@
+CONFIG_ADM6996_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_NLS=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTL8306_PHY=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SWCONFIG=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/layerscape/Makefile b/target/linux/layerscape/Makefile
index 79aa8f1474..30b9fb8f73 100644
--- a/target/linux/layerscape/Makefile
+++ b/target/linux/layerscape/Makefile
@@ -8,6 +8,7 @@ BOARD:=layerscape
 BOARDNAME:=NXP Layerscape
 
 KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
 
 FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part
 SUBTARGETS:=armv8_64b armv7
diff --git a/target/linux/layerscape/armv7/config-6.1 b/target/linux/layerscape/armv7/config-6.1
index a4744623e4..d60e5824db 100644
--- a/target/linux/layerscape/armv7/config-6.1
+++ b/target/linux/layerscape/armv7/config-6.1
@@ -274,8 +274,7 @@ CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_GPIO_MPC8XXX=y
 CONFIG_GPIO_MXC=y
 CONFIG_GPIO_VF610=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
diff --git a/target/linux/layerscape/armv7/config-6.6 b/target/linux/layerscape/armv7/config-6.6
new file mode 100644
index 0000000000..63c49df174
--- /dev/null
+++ b/target/linux/layerscape/armv7/config-6.6
@@ -0,0 +1,706 @@
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
+# CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_APDS9802ALS=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
+# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
+# CONFIG_ARM_IMX_CPUFREQ_DT is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BATTERY_SBS=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CDROM=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_CLK_IMX8MM is not set
+# CONFIG_CLK_IMX8MN is not set
+# CONFIG_CLK_IMX8MP is not set
+# CONFIG_CLK_IMX8MQ is not set
+# CONFIG_CLK_IMX8ULP is not set
+# CONFIG_CLK_IMX93 is not set
+CONFIG_CLK_QORIQ=y
+# CONFIG_CLK_VEXPRESS_OSC is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=64
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DW_DMAC=y
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FAT_FS=y
+# CONFIG_FEC is not set
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+# CONFIG_FSL_PPFE is not set
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_FSL_RCPM=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTRACE=y
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FUSE_FS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GIANFAR=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_VF610=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+# CONFIG_HIST_TRIGGERS is not set
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DEMUX_PINCTRL=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_IMX_LPI2C is not set
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_XILINX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ICS932S401=y
+CONFIG_IMX2_WDT=y
+# CONFIG_IMX7ULP_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+CONFIG_IMX_DMA=y
+# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
+CONFIG_IMX_INTMUX=y
+# CONFIG_IMX_IRQSTEER is not set
+# CONFIG_IMX_MU_MSI is not set
+CONFIG_IMX_SDMA=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_INPUT_BBNSM_PWRKEY is not set
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_ISL29003=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LS_EXTIRQ=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MCPM=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSDOS_FS=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MXC_CLK=y
+# CONFIG_MXS_DMA is not set
+CONFIG_NAMESPACES=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NEON=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=y
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCI_IMX6_HOST is not set
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMX93 is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_BRCMKONA=y
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_BBNSM is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EM3027=y
+CONFIG_RTC_DRV_FSL_FTM_ALARM=y
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_ST_ASC=y
+CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SMSC_PHY=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SLL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_IMX7ULP is not set
+# CONFIG_SOC_IMX8M is not set
+# CONFIG_SOC_IMX9 is not set
+CONFIG_SOC_LS1021A=y
+# CONFIG_SOC_VF610 is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_DYNAMIC=y
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_IMX is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+# CONFIG_SSIF_IPMI_BMC is not set
+CONFIG_STACKTRACE=y
+CONFIG_STAGING_BOARD=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNIX_DIAG=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/layerscape/armv8_64b/config-6.6 b/target/linux/layerscape/armv8_64b/config-6.6
new file mode 100644
index 0000000000..71692ef4ee
--- /dev/null
+++ b/target/linux/layerscape/armv8_64b/config-6.6
@@ -0,0 +1,914 @@
+CONFIG_64BIT=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ASM_MODVERSIONS=y
+CONFIG_ASN1=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_ATA=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BATTERY_BQ27XXX=y
+# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
+CONFIG_BATTERY_BQ27XXX_I2C=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CLK_LS1028A_PLLDIG=y
+CONFIG_CLK_QORIQ=y
+# CONFIG_CLK_VEXPRESS_OSC is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_FSL_FLEXSPI=y
+# CONFIG_COMMON_CLK_FSL_SAI is not set
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC7=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CROS_EC is not set
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XXHASH=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DIMLIB=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+# CONFIG_DMA_NUMA_CMA is not set
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DPAA2_CONSOLE=y
+CONFIG_DPAA_ERRATUM_A050385=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FREEZER=y
+# CONFIG_FSL_BMAN_TEST is not set
+CONFIG_FSL_DPAA=y
+CONFIG_FSL_DPAA2_ETH=y
+CONFIG_FSL_DPAA2_PTP_CLOCK=y
+# CONFIG_FSL_DPAA2_QDMA is not set
+# CONFIG_FSL_DPAA_CHECKING is not set
+CONFIG_FSL_DPAA_ETH=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_ENETC=y
+CONFIG_FSL_ENETC_CORE=y
+CONFIG_FSL_ENETC_IERB=y
+CONFIG_FSL_ENETC_MDIO=y
+CONFIG_FSL_ENETC_PTP_CLOCK=y
+CONFIG_FSL_ENETC_VF=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_FSL_FMAN=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+CONFIG_FSL_MC_BUS=y
+CONFIG_FSL_MC_DPIO=y
+CONFIG_FSL_MC_UAPI_SUPPORT=y
+# CONFIG_FSL_PPFE is not set
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_RCPM=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FUSE_FS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GARP=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_NUMA=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IMX2_WDT=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTERVAL_TREE=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KCMP=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KSM=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LS_EXTIRQ=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMTEST=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MPILIB=y
+CONFIG_MRP=y
+CONFIG_MSCC_OCELOT_SWITCH_LIB=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTIPLEXER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MUX_MMIO=y
+CONFIG_MV_XOR_V2=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MSCC_FELIX=y
+CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=y
+CONFIG_NET_DSA_TAG_OCELOT=y
+CONFIG_NET_DSA_TAG_OCELOT_8021Q=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NODES_SHIFT=2
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=64
+CONFIG_NUMA=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYERSCAPE_SFP=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NUMA=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARAVIRT=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_MOBIVEIL=y
+CONFIG_PCIE_MOBIVEIL_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_LYNX=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_FSL_LYNX_28G is not set
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_PID_NS=y
+CONFIG_PL330_DMA=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROFILING=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID6_PQ=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_FSL_FTM_ALARM=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SECRETMEM=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SC16IS7XX=y
+CONFIG_SERIAL_SC16IS7XX_CORE=y
+# CONFIG_SERIAL_SC16IS7XX_I2C is not set
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+# CONFIG_SQUASHFS_XZ is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWIOTLB_XEN=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THP_SWAP=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UIO=y
+CONFIG_UIO_AEC=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_DMEM_GENIRQ=y
+CONFIG_UIO_MF624=y
+CONFIG_UIO_NETX=y
+CONFIG_UIO_PCI_GENERIC=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+CONFIG_UIO_SERCOS3=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIX_DIAG=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_UTS_NS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFIO=y
+# CONFIG_VFIO_AMBA is not set
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_FSL_MC=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI=y
+CONFIG_VFIO_PCI_CORE=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_VIRTIO_IOMMU is not set
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XEN=y
+CONFIG_XENFS=y
+CONFIG_XEN_AUTO_XLATE=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XEN_BALLOON=y
+# CONFIG_XEN_BLKDEV_BACKEND is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+# CONFIG_XEN_NETDEV_BACKEND is not set
+CONFIG_XEN_NETDEV_FRONTEND=y
+# CONFIG_XEN_PCIDEV_STUB is not set
+CONFIG_XEN_PRIVCMD=y
+# CONFIG_XEN_PVCALLS_BACKEND is not set
+# CONFIG_XEN_SCSI_FRONTEND is not set
+CONFIG_XEN_SYS_HYPERVISOR=y
+# CONFIG_XEN_VIRTIO is not set
+# CONFIG_XEN_WDT is not set
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_XOR_BLOCKS=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/layerscape/image/Makefile b/target/linux/layerscape/image/Makefile
index f2ac9b6f04..a4885e8912 100644
--- a/target/linux/layerscape/image/Makefile
+++ b/target/linux/layerscape/image/Makefile
@@ -33,7 +33,7 @@ define Build/ls-append
 endef
 
 define Build/ls-append-dtb
-	dd if=$(DTS_DIR)/$(1).dtb >> $@
+	dd if=$(DEVICE_DTS_DIR)/$(1).dtb >> $@
 endef
 
 define Build/ls-append-kernel
diff --git a/target/linux/layerscape/image/armv7.mk b/target/linux/layerscape/image/armv7.mk
index fe396212e7..916f92eacf 100644
--- a/target/linux/layerscape/image/armv7.mk
+++ b/target/linux/layerscape/image/armv7.mk
@@ -6,8 +6,13 @@ define Device/Default
   PROFILES := Default
   FILESYSTEMS := squashfs
   IMAGES := firmware.bin sysupgrade.bin
+ifdef CONFIG_LINUX_6_1
+  DEVICE_DTS_DIR := $(DTS_DIR)
+else
+  DEVICE_DTS_DIR := $(DTS_DIR)/nxp/ls
+endif
   KERNEL := kernel-bin | uImage none
-  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
   KERNEL_NAME := zImage
   KERNEL_LOADADDR := 0x80008000
   DEVICE_DTS = $(lastword $(subst _, ,$(1)))
@@ -20,7 +25,7 @@ define Device/Default
 endef
 
 define Device/fsl-sdboot
-  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
   IMAGES := sdcard.img.gz sysupgrade.bin
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
diff --git a/target/linux/layerscape/image/armv8_64b.mk b/target/linux/layerscape/image/armv8_64b.mk
index 259bacee31..4bce779984 100644
--- a/target/linux/layerscape/image/armv8_64b.mk
+++ b/target/linux/layerscape/image/armv8_64b.mk
@@ -5,11 +5,12 @@
 define Device/Default
   PROFILES := Default
   IMAGES := firmware.bin sysupgrade.bin
+  DEVICE_DTS_DIR := $(DTS_DIR)/freescale
+  DEVICE_DTS = $(subst _,-,$(1))
   FILESYSTEMS := squashfs
   KERNEL := kernel-bin | gzip | uImage gzip
-  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
   KERNEL_LOADADDR := 0x80000000
-  DEVICE_DTS = freescale/$(subst _,-,$(1))
   IMAGE_SIZE := 64m
   IMAGE/sysupgrade.bin = \
     ls-append-dtb $$(DEVICE_DTS) | pad-to 1M | \
@@ -19,7 +20,7 @@ define Device/Default
 endef
 
 define Device/fsl-sdboot
-  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
   IMAGES := sdcard.img.gz sysupgrade.bin
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
@@ -45,7 +46,7 @@ define Device/fsl_ls1012a-frdm
     append-kernel | pad-to $$(BLOCKSIZE) | \
     append-rootfs | pad-rootfs | \
     check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata
-  KERNEL := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL := kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
 endef
 TARGET_DEVICES += fsl_ls1012a-frdm
 
@@ -81,7 +82,7 @@ define Device/fsl_ls1012a-frwy-sdboot
     layerscape-ppfe \
     trusted-firmware-a-ls1012a-frwy-sdboot \
     kmod-ppfe
-  DEVICE_DTS := freescale/fsl-ls1012a-frwy
+  DEVICE_DTS := fsl-ls1012a-frwy
   IMAGES += firmware.bin
   IMAGE/firmware.bin := \
     ls-clean | \
@@ -102,8 +103,7 @@ define Device/fsl_ls1028a-rdb
   DEVICE_VENDOR := NXP
   DEVICE_MODEL := LS1028A-RDB
   DEVICE_VARIANT := Default
-  DEVICE_DTS := freescale/fsl-ls1028a-rdb
-  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
   DEVICE_PACKAGES += \
     trusted-firmware-a-ls1028a-rdb \
     kmod-hwmon-ina2xx \
@@ -128,7 +128,7 @@ define Device/fsl_ls1028a-rdb-sdboot
   DEVICE_VENDOR := NXP
   DEVICE_MODEL := LS1028A-RDB
   DEVICE_VARIANT := SD Card Boot
-  DEVICE_DTS := freescale/fsl-ls1028a-rdb
+  DEVICE_DTS := fsl-ls1028a-rdb
   DEVICE_PACKAGES += \
     trusted-firmware-a-ls1028a-rdb-sdboot \
     kmod-hwmon-ina2xx \
@@ -157,7 +157,6 @@ define Device/fsl_ls1043a-rdb
     kmod-ahci-qoriq \
     kmod-hwmon-ina2xx \
     kmod-hwmon-lm90
-  DEVICE_DTS := freescale/fsl-ls1043a-rdb
   IMAGE/firmware.bin := \
     ls-clean | \
     ls-append $(1)-bl2.pbl | pad-to 1M | \
@@ -183,7 +182,7 @@ define Device/fsl_ls1043a-rdb-sdboot
     kmod-ahci-qoriq \
     kmod-hwmon-ina2xx \
     kmod-hwmon-lm90
-  DEVICE_DTS := freescale/fsl-ls1043a-rdb
+  DEVICE_DTS := fsl-ls1043a-rdb
   IMAGE/sdcard.img.gz := \
     ls-clean | \
     ls-append-sdhead $(1) | pad-to 4K | \
@@ -203,7 +202,6 @@ define Device/fsl_ls1046a-frwy
   DEVICE_PACKAGES += \
     layerscape-fman \
     trusted-firmware-a-ls1046a-frwy
-  DEVICE_DTS := freescale/fsl-ls1046a-frwy
   IMAGE/firmware.bin := \
     ls-clean | \
     ls-append $(1)-bl2.pbl | pad-to 1M | \
@@ -224,7 +222,7 @@ define Device/fsl_ls1046a-frwy-sdboot
   DEVICE_PACKAGES += \
     layerscape-fman \
     trusted-firmware-a-ls1046a-frwy-sdboot
-  DEVICE_DTS := freescale/fsl-ls1046a-frwy
+  DEVICE_DTS := fsl-ls1046a-frwy
   IMAGE/sdcard.img.gz := \
     ls-clean | \
     ls-append-sdhead $(1) | pad-to 4K | \
@@ -249,7 +247,6 @@ define Device/fsl_ls1046a-rdb
     kmod-ahci-qoriq \
     kmod-hwmon-ina2xx \
     kmod-hwmon-lm90
-  DEVICE_DTS := freescale/fsl-ls1046a-rdb
   IMAGE/firmware.bin := \
     ls-clean | \
     ls-append $(1)-bl2.pbl | pad-to 1M | \
@@ -275,7 +272,7 @@ define Device/fsl_ls1046a-rdb-sdboot
     kmod-ahci-qoriq \
     kmod-hwmon-ina2xx \
     kmod-hwmon-lm90
-  DEVICE_DTS := freescale/fsl-ls1046a-rdb
+  DEVICE_DTS := fsl-ls1046a-rdb
   IMAGE/sdcard.img.gz := \
     ls-clean | \
     ls-append-sdhead $(1) | pad-to 4K | \
@@ -329,7 +326,7 @@ define Device/fsl_ls1088a-rdb-sdboot
     kmod-ahci-qoriq \
     kmod-hwmon-ina2xx \
     kmod-hwmon-lm90
-  DEVICE_DTS := freescale/fsl-ls1088a-rdb
+  DEVICE_DTS := fsl-ls1088a-rdb
   IMAGE/sdcard.img.gz := \
     ls-clean | \
     ls-append-sdhead $(1) | pad-to 4K | \
@@ -404,7 +401,7 @@ define Device/fsl_lx2160a-rdb-sdboot
     layerscape-ddr-phy \
     trusted-firmware-a-lx2160a-rdb-sdboot \
     restool
-  DEVICE_DTS := freescale/fsl-lx2160a-rdb
+  DEVICE_DTS := fsl-lx2160a-rdb
   IMAGE/sdcard.img.gz := \
     ls-clean | \
     ls-append-sdhead $(1) | pad-to 4K | \
@@ -438,7 +435,7 @@ define Device/traverse_ten64_mtd
   KERNEL_ENTRY_POINT := 0x80000000
   FDT_LOADADDR := 0x90000000
   KERNEL_SUFFIX := -kernel.itb
-  DEVICE_DTS := freescale/fsl-ls1088a-ten64
+  DEVICE_DTS := fsl-ls1088a-ten64
   IMAGES := nand.ubi sysupgrade.bin
   KERNEL := kernel-bin | gzip | traverse-fit-ls1088 gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
diff --git a/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch
new file mode 100644
index 0000000000..bd69aa042d
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch
@@ -0,0 +1,228 @@
+From 008465a02bf29b366ca7a56dba48ad3a85417ba2 Mon Sep 17 00:00:00 2001
+From: Li Yang <leoyang.li@nxp.com>
+Date: Thu, 18 Nov 2021 21:46:21 -0600
+Subject: [PATCH] arm64: dts: ls1012a: add ppfe support to boards
+
+Update ls1012a dtsi and platform dts files with
+support for ppfe.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+---
+ .../boot/dts/freescale/fsl-ls1012a-frdm.dts   | 44 +++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1012a-qds.dts    | 43 ++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1012a-rdb.dts    | 40 +++++++++++++++++
+ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
+ 4 files changed, 156 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -14,6 +14,11 @@
+ 	model = "LS1012A Freedom Board";
+ 	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+ 
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++
+ 	sys_mclk: clock-mclk {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+@@ -110,6 +115,45 @@
+ 	};
+ };
+ 
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	pfe_mac0: ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		phy-handle = <&sgmii_phy1>;
++	};
++
++	pfe_mac1: ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		phy-handle = <&sgmii_phy2>;
++	};
++
++	mdio@0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		sgmii_phy1: ethernet-phy@2 {
++			reg = <0x2>;
++		};
++
++		sgmii_phy2: ethernet-phy@1 {
++			reg = <0x1>;
++		};
++	};
++};
++
+ &sai2 {
+ 	status = "okay";
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -16,6 +16,8 @@
+ 	aliases {
+ 		mmc0 = &esdhc0;
+ 		mmc1 = &esdhc1;
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
+ 	};
+ 
+ 	sys_mclk: clock-mclk {
+@@ -148,6 +150,47 @@
+ 	};
+ };
+ 
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	pfe_mac0: ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x2>;
++		phy-mode = "sgmii-2500";
++		phy-handle = <&sgmii_phy1>;
++	};
++
++	pfe_mac1: ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x3>;
++		phy-mode = "sgmii-2500";
++		phy-handle = <&sgmii_phy2>;
++	};
++
++	mdio@0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		sgmii_phy1: ethernet-phy@1 {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			reg = <0x1>;
++		};
++
++		sgmii_phy2: ethernet-phy@2 {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			reg = <0x2>;
++		};
++	};
++};
++
+ &sai2 {
+ 	status = "okay";
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -18,6 +18,8 @@
+ 		serial0 = &duart0;
+ 		mmc0 = &esdhc0;
+ 		mmc1 = &esdhc1;
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
+ 	};
+ };
+ 
+@@ -104,3 +106,41 @@
+ &sata {
+ 	status = "okay";
+ };
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	pfe_mac0: ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		phy-handle = <&sgmii_phy>;
++	};
++
++	pfe_mac1: ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "rgmii-id";
++		phy-handle = <&rgmii_phy>;
++	};
++	mdio@0 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		sgmii_phy: ethernet-phy@2 {
++			reg = <0x2>;
++		};
++
++		rgmii_phy: ethernet-phy@1 {
++			reg = <0x1>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -568,6 +568,35 @@
+ 		};
+ 	};
+ 
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		pfe_reserved: packetbuffer@83400000 {
++			reg = <0 0x83400000 0 0xc00000>;
++		};
++	};
++
++	pfe: pfe@4000000 {
++		compatible = "fsl,pfe";
++		reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
++			<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
++		reg-names = "pfe", "pfe-ddr";
++		fsl,pfe-num-interfaces = <0x2>;
++		interrupts = <0 172 0x4>,    /* HIF interrupt */
++			     <0 173 0x4>,    /*HIF_NOCPY interrupt */
++			     <0 174 0x4>;    /* WoL interrupt */
++		interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++		memory-region = <&pfe_reserved>;
++		fsl,pfe-scfg = <&scfg 0>;
++		fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++		clocks = <&clockgen 4 0>;
++		clock-names = "pfe";
++
++		status = "okay";
++	};
++
+ 	firmware {
+ 		optee {
+ 			compatible = "linaro,optee-tz";
diff --git a/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch
new file mode 100644
index 0000000000..f42859b7ac
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch
@@ -0,0 +1,41 @@
+From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Fri, 28 Sep 2022 17:14:32 +0200
+Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to
+ single mode
+
+Update rx and tx bus-width to 1 to use single mode to workaround ubifs
+issue found with double mode. (The same method as RDB board)
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++--
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 4 ++--
+ 2 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -110,8 +110,8 @@
+ 		spi-max-frequency = <50000000>;
+ 		m25p,fast-read;
+ 		reg = <0>;
+-		spi-rx-bus-width = <2>;
+-		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <1>;
++		spi-tx-bus-width = <1>;
+ 	};
+ };
+ 
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -145,8 +145,8 @@
+ 		spi-max-frequency = <50000000>;
+ 		m25p,fast-read;
+ 		reg = <0>;
+-		spi-rx-bus-width = <2>;
+-		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <1>;
++		spi-tx-bus-width = <1>;
+ 	};
+ };
+ 
diff --git a/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch
new file mode 100644
index 0000000000..fd1dff747b
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch
@@ -0,0 +1,29 @@
+From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
+From: Kuldeep Singh <kuldeep.singh@nxp.com>
+Date: Tue, 7 Jan 2020 17:14:32 +0530
+Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to
+ single mode
+
+Update rx and tx bus-width to 1 to use single mode to workaround ubifs
+issue found with double mode.
+
+[ Leo: Local workaround ]
+
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -98,8 +98,8 @@
+ 		spi-max-frequency = <50000000>;
+ 		m25p,fast-read;
+ 		reg = <0>;
+-		spi-rx-bus-width = <2>;
+-		spi-tx-bus-width = <2>;
++		spi-rx-bus-width = <1>;
++		spi-tx-bus-width = <1>;
+ 	};
+ };
+ 
diff --git a/target/linux/layerscape/patches-6.6/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch b/target/linux/layerscape/patches-6.6/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch
new file mode 100644
index 0000000000..9bc4e2b520
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch
@@ -0,0 +1,34 @@
+From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001
+From: Kuldeep Singh <kuldeep.singh@nxp.com>
+Date: Fri, 3 Jan 2020 14:49:07 +0530
+Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1
+
+Update rx width from quad mode to single mode as a workaround.
+
+[Leo: Local workaround ]
+
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -104,7 +104,7 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+ 		spi-max-frequency = <50000000>;
+-		spi-rx-bus-width = <4>;
++		spi-rx-bus-width = <1>;
+ 		spi-tx-bus-width = <1>;
+ 		reg = <0>;
+ 	};
+@@ -114,7 +114,7 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+ 		spi-max-frequency = <50000000>;
+-		spi-rx-bus-width = <4>;
++		spi-rx-bus-width = <1>;
+ 		spi-tx-bus-width = <1>;
+ 		reg = <1>;
+ 	};
diff --git a/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch
new file mode 100644
index 0000000000..b85053eba9
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch
@@ -0,0 +1,27 @@
+From bd3fa0b0ed51dd6a6564c01d37b36ff475f87ed4 Mon Sep 17 00:00:00 2001
+From: Han Xu <han.xu@nxp.com>
+Date: Tue, 14 Apr 2020 11:58:44 -0500
+Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s)
+ flash
+
+This is a workaround patch which uses only single bit mode of s25fs512s
+flash
+
+Signed-off-by: Han Xu <han.xu@nxp.com>
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ drivers/mtd/spi-nor/spansion.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/spansion.c
++++ b/drivers/mtd/spi-nor/spansion.c
+@@ -798,8 +798,8 @@ static const struct flash_info spansion_
+ 		MFR_FLAGS(USE_CLSR)
+ 	},
+ 	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
+-		NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ 		MFR_FLAGS(USE_CLSR)
++		FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ 		.fixups = &s25fs_s_nor_fixups, },
+ 	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64) },
+ 	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256) },
diff --git a/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch
new file mode 100644
index 0000000000..764d29f10d
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/701-staging-add-fsl_ppfe-driver.patch
@@ -0,0 +1,11799 @@
+From 9ee016f90af0bbcac576af881f1760ee9d9e38e0 Mon Sep 17 00:00:00 2001
+From: Calvin Johnson <calvin.johnson@nxp.com>
+Date: Sat, 16 Sep 2017 07:05:49 +0530
+Subject: [PATCH] staging: add fsl_ppfe driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is squash of all commits with ppfe driver taken from NXP 6.6 tree:
+https://github.com/nxp-qoriq/linux/tree/lf-6.6.y
+
+net: fsl_ppfe: dts binding for ppfe
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: header files for pfe driver
+
+This patch has all pfe header files.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: introduce pfe driver
+
+	This patch introduces Linux support for NXP's LS1012A Packet
+Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
+engine to provide high performance Ethernet interfaces. The device
+includes two Ethernet ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: fix RGMII tx delay issue
+
+Recently logic to enable RGMII tx delay was changed by
+below patch.
+
+https://patchwork.kernel.org/patch/9447581/
+
+Based on the patch, appropriate change is made in PFE driver.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: remove unused functions
+
+Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: fix read/write/ack idx issue
+
+While fixing checkpatch errors some of the index increments
+were commented out. They are enabled.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void
+
+Make return value void since function never return meaningful value
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: add function to update tmu credits
+
+__hif_lib_update_credit function is used to update the tmu credits.
+If tx_qos is set, tmu credit is updated based on the number of packets
+transmitted by tmu.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid packet drop at TMU queues
+
+Added flow control between TMU queues and PFE Linux driver,
+based on TMU credits availability.
+Added tx_qos module parameter to control this behavior.
+Use queue-0 as default queue to transmit packets.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Akhila Kavi <akhila.kavi@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: Enable PFE in clause 45 mode
+
+when we opearate in clause 45 mode, we need to call
+the function get_phy_device() with its 3rd argument as
+"true" and then the resultant phy device needs to be
+register with phy layer via phy_device_register()
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+
+staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII
+
+PCS initialization sequence for 2.5G SGMII interface governs
+auto negotiation to be in disabled mode
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+
+staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN
+
+pfe packet size was calculated without considering skb data alignment
+and this resulted in jumbo frames crashing kernel when the
+cacheline size increased from 64 to 128 bytes with
+commit 97303480753e ("arm64: Increase the max granular size").
+
+Modify pfe packet size caclulation to include skb data alignment of
+sizeof(struct skb_shared_info).
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: support for userspace networking
+
+This patch adds the userspace mode support to fsl_ppfe network driver.
+In the new mode, basic hardware initialization is performed in kernel, while
+the datapath and HIF handling is the responsibility of the userspace.
+
+The new command line parameter is added to initialize the ppfe module
+in userspace mode. By default the module remains in kernelspace networking
+mode.
+To enable userspace mode, use "insmod pfe.ko us=1"
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
+
+staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit
+
+rmmod pfe.ko throws below warning:
+
+kernfs: can not remove 'phydev', no directory
+------------[ cut here ]------------
+WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481
+kernfs_remove_by_name_ns+0x90/0xa0
+
+This is caused when the unregistered netdev structure is accessed to
+disconnect phy.
+
+Resolve the issue by unregistering netdev after disconnecting phy.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: HW parse results for DPDK
+
+HW Parse results are included in the packet headroom.
+Length and Offset calculation now accommodates parse info size.
+
+Signed-off-by: Archana Madhavan <archana.madhavan@nxp.com>
+
+staging: fsl_ppfe/eth: reorganize pfe_netdev_ops
+
+Reorganize members of struct pfe_netdev_ops to match with the order
+of members in struct net_device_ops defined in include/linux/netdevice.h
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use mask for rx max frame len
+
+Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame
+length of MAC Receive Control Register.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: define pfe ndo_change_mtu function
+
+Define ndo_change_mtu function for pfe. This sets the max Rx frame
+length to the new mtu.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init
+
+MAC Receive Control Register was configured to allow jumbo frames.
+This is removed as jumbo frames can be supported anytime by changing
+mtu which will in turn modify MAX_FL field of MAC RCR.
+Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to
+erratum A-010897.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: disable CRC removal
+
+Disable CRC removal from the packet, so that packets are forwarded
+as is to Linux.
+CRC configuration in MAC will be reflected in the packet received
+to Linux.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: handle ls1012a errata_a010897
+
+On LS1012A rev 1.0, Jumbo frames are not supported as it causes
+the PFE controller to hang. A reset of the entire chip is required
+to resume normal operation.
+
+To handle this errata, frames with length > 1900 are truncated for
+rev 1.0 of LS1012A.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: replace magic numbers
+
+Replace magic numbers and some cosmetic changes.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: resolve indentation warning
+
+Resolve the following indentation warning:
+
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:
+In function ‘pfe_get_gemac_if_proprties’:
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2:
+warning: this ‘else’ clause does not guard...
+[-Wmisleading-indentation]
+  else
+  ^~~~
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3:
+note: ...this statement, but the latter is misleadingly indented as
+if it were guarded by the ‘else’
+   pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
+   ^~~~~
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: add fixed-link support
+
+In cases where MAC is not connected to a normal MDIO-managed PHY
+device, and instead to a switch, it is configured as a "fixed-link".
+Code to handle this scenario is added here.
+
+phy_node in the dtb is checked to identify a fixed-link.
+On identification of a fixed-link, it is registered and connected.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe: add support for a char dev for link status
+
+Read and IOCTL support is added. Application would need to open,
+read/ioctl the /dev/pfe_us_cdev device.
+select is pending as it requires a wait_queue.
+
+Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe: enable hif event from userspace
+
+HIF interrupts are enabled using ioctl from user space,
+and epoll wait from user space wakes up when there is an HIF
+interrupt.
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+
+staging: fsl_ppfe: performance tuning for user space
+
+interrupt coalescing of 100 usec is added.
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
+
+staging: fsl_ppfe/eth: Update to use SPDX identifiers
+
+Replace license text with corresponding SPDX identifiers and update the
+format of existing SPDX identifiers to follow the new guideline
+Documentation/process/license-rules.rst.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: misc clean up
+
+- remove redundant hwfeature init
+- remove unused vars from ls1012a_eth_platform_data
+- To handle ls1012a errata_a010897, PPFE driver requires GUTS driver
+to be compiled in. Select FSL_GUTS when PPFE driver is compiled.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: reorganize platform phy parameters
+
+- Use "phy-handle" and of_* functions to get phy node and fixed-link
+parameters
+
+- Reorganize phy parameters and initialize them only if phy-handle
+or fixed-link is defined in the dtb.
+
+- correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: support single interface initialization
+
+- arrange members of struct mii_bus in sequence matching phy.h
+- if mdio node is defined, use of_mdiobus_register to register
+  child nodes (phy devices) available on the mdio bus.
+- remove of_phy_register_fixed_link from pfe_phy_init as it is being
+  handled in pfe_get_gemac_if_properties
+- remove mdio enabled check
+- skip phy init, if no PHY or fixed-link
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+net: fsl_ppfe: update dts properties for phy
+
+Use commonly used phy-handle property and mdio subnode to handle
+phy properties.
+
+Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove unused code
+
+- remove gemac-bus-id related code that is unused.
+- remove unused prototype gemac_set_mdc_div.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: separate mdio init from mac init
+
+- separate mdio initialization from mac initialization
+- Define pfe_mdio_priv_s structure to hold mii_bus structure and other
+  related data.
+- Modify functions to work with the separted mdio init model.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: adapt to link mode based phydev changes
+
+Setting link mode bits have changed with the integration of
+commit (3c1bcc8 net: ethernet: Convert phydev advertize and
+supported from u32 to link mode). Adapt to the new method of
+setting and clearing the link mode bits.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr()
+
+Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has
+made fsl_guts_get_svr() static and hence use generic soc_device
+infrastructure to check SoC revision.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE
+
+RAM area used by PFE should be mapped using memremap() instead of
+directly traslating physical addr to virtual. This will ensure proper
+checks are done before the area is used.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue()
+
+To be consistent with upstream API change.
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/
+
+Currently, the rules for configuring search paths in Kbuild have
+changed: https://lkml.org/lkml/2019/5/13/37
+
+This will lead the below error:
+
+fatal error: pfe/pfe.h: No such file or directory
+
+Fix it by adding $(srctree)/ prefix to the search paths.
+
+Signed-off-by: Ting Liu <ting.liu@nxp.com>
+
+staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+[ Aisheng: fix minor conflict due to removed VBOXSF_FS ]
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe/eth: Disable termination of CRC fwd.
+
+LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x.
+The issue is triggered by the (spec-compliant) operation of the AR803x PHY
+on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error
+packet by MAC, so for these error packets FCS should be validated and
+discard only real error packets in PFE Rx packet path.
+
+Signed-off-by: Nagesh Koneti <koneti.nagesh@nxp.com>
+Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”>
+
+net: ppfe: Cope with of_get_phy_mode() API change
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe/eth: Enhance error checking in platform probe
+
+Fix the kernel crash when MAC addr is not passed in dtb.
+
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: reject unsupported coalescing params
+
+Set ethtool_ops->supported_coalesce_params to let
+the core reject unsupported coalescing parameters.
+
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties()
+
+It has been observed that the function pfe_get_gemac_if_properties() is
+been called blindly for the next two child nodes. There might be some
+cases where it may go wrong and that lead to missing interfaces.
+with these changes it is ensured thats not the case.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions
+
+firmware structure's data variable is the actual elf data. It has been
+dereferenced in multiple functions and this has been reduced.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT
+
+FDT prepared in uboot now has pfe firmware part of it.
+These changes will read the firmware by default from it and tries to load
+the elf into the PFE PEs. This help build the pfe driver pasrt of kernel.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: proper handling for RGMII delay mode
+
+The correct setting for the RGMII ports on LS1012ARDB is to
+enable delay on both Tx and Rx. So the phy mode to be matched
+is PHY_INTERFACE_MODE_RGMII_ID.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help'
+
+Update Kconfig to cope with upstream change
+commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
+'---help---'").
+
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe/eth: Nesting level does not match indentation
+
+corrected nesting level
+LF-1661 and Coverity CID: 8879316
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Initialized scalar variable
+
+Proper initialization of scalar variable
+LF-1657 and Coverity CID: 3335133
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: misspelt variable name
+
+variable name corrected
+LF-1656 and Coverity CID: 3335119
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding out-of-bound writes
+
+avoid out-of-bound writes with proper error handling
+LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Initializing scalar variable
+
+proper initialization of scalar variable.
+LF-1653 and Coverity CID: 3335101
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: checking return value
+
+proper checks added and handled for return value.
+LF-1644 and Coverity CID: 241888
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid out-of-bound access
+
+proper handling to avoid out-of-bound access
+LF-1642, LF-1641 and Coverity CID: 240910, 240891
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding out-of-bound writes
+
+avoid out-of-bound writes with proper error handling
+LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: return value init in error case
+
+proper err return in error case.
+LF-1806 and Coverity CID: 10468592
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid recursion in header inclusion
+
+Avoiding header inclusions that are not necessary and also that are
+causing header inclusion recursion.
+
+LF-2102 and Coverity CID: 240838
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding return value overwrite
+
+avoid return value overwrite at the end of function.
+LF-2136, LF-2137 and Coverity CID: 8879341, 8879364
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT
+
+The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load
+the firmware from FDT by default. Enabling the macro will load the
+firmware from filesystem.
+
+Also, the Makefile is now tuned to build pfe as per the config option
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter
+
+Due to carrier extended bug the phy counter IEEE_rx_drop counter is
+incremented some times and phy reports the packet has crc error.
+Because of this PFE revalidates all the packets that are marked crc
+error by phy. Now, the counter phy reports is till bogus and this
+patch decrements the counter by pfe revalidated (and are crc ok)
+counter amount.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: PFE firmware load enhancements
+
+PFE driver enhancements to load the PE firmware from filesystem
+when the firmware is not found in FDT.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: deal with upstream API change of of_get_mac_address()
+
+Uptream commit 83216e398 changed the of_get_mac_address() API, update
+the user accordingly.
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe: update coalesce setting uAPI usage
+
+API changed since:
+f3ccfda19319 ("ethtool: extend coalesce setting uAPI with CQE mode")
+
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe: Addressed build warnings
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: Addressed build warnings
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: Remove C45 check and related code in driver
+
+The MDIO core will not pass a C45 request via the C22 API call any
+more. So, removed the code. The old way of C45 muxed addresses is
+removed from the upstream kernel after clear seperation of C45 and
+C22.
+Upstream kernel commit details for reference:
+99d5fe9c7f3d net: mdio: Remove support for building C45 muxed addresses
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: update class_create() usage
+
+Cope with API change:
+1aaba11da9aa ("driver core: class: remove module * from class_create()")
+
+Signed-off-by: Krishna Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+LF-10777-2 staging: fsl_ppfe: remove unused pfe_eth_mdio_write_addr
+
+Fix the following build warning:
+drivers/staging/fsl_ppfe/pfe_eth.c:887:12: warning: ‘pfe_eth_mdio_write_addr’ defined but not used [-Wunused-function]
+  887 | static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id,
+
+The only user of this API is MII_ADDR_C45 checking logic which
+was removed since the commit 9d95b13bd084 ("staging: fsl_ppfe: Remove
+C45 check and related code in driver"). So this API should be removed
+together as no users anymore.
+
+Fixes: 9d95b13bd084 ("staging: fsl_ppfe: Remove C45 check and related code in driver")
+Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+---
+ .../devicetree/bindings/net/fsl_ppfe/pfe.txt  |  199 ++
+ MAINTAINERS                                   |    8 +
+ drivers/staging/Kconfig                       |    2 +
+ drivers/staging/Makefile                      |    1 +
+ drivers/staging/fsl_ppfe/Kconfig              |   21 +
+ drivers/staging/fsl_ppfe/Makefile             |   20 +
+ drivers/staging/fsl_ppfe/TODO                 |    2 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus.h   |   78 +
+ .../staging/fsl_ppfe/include/pfe/cbus/bmu.h   |   55 +
+ .../fsl_ppfe/include/pfe/cbus/class_csr.h     |  289 ++
+ .../fsl_ppfe/include/pfe/cbus/emac_mtip.h     |  242 ++
+ .../staging/fsl_ppfe/include/pfe/cbus/gpi.h   |   86 +
+ .../staging/fsl_ppfe/include/pfe/cbus/hif.h   |  100 +
+ .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h     |   50 +
+ .../fsl_ppfe/include/pfe/cbus/tmu_csr.h       |  168 ++
+ .../fsl_ppfe/include/pfe/cbus/util_csr.h      |   61 +
+ drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  372 +++
+ drivers/staging/fsl_ppfe/pfe_cdev.c           |  258 ++
+ drivers/staging/fsl_ppfe/pfe_cdev.h           |   41 +
+ drivers/staging/fsl_ppfe/pfe_ctrl.c           |  226 ++
+ drivers/staging/fsl_ppfe/pfe_ctrl.h           |  100 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.c        |   99 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.h        |   13 +
+ drivers/staging/fsl_ppfe/pfe_eth.c            | 2550 +++++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_eth.h            |  175 ++
+ drivers/staging/fsl_ppfe/pfe_firmware.c       |  398 +++
+ drivers/staging/fsl_ppfe/pfe_firmware.h       |   21 +
+ drivers/staging/fsl_ppfe/pfe_hal.c            | 1517 ++++++++++
+ drivers/staging/fsl_ppfe/pfe_hif.c            | 1063 +++++++
+ drivers/staging/fsl_ppfe/pfe_hif.h            |  199 ++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.c        |  628 ++++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.h        |  229 ++
+ drivers/staging/fsl_ppfe/pfe_hw.c             |  164 ++
+ drivers/staging/fsl_ppfe/pfe_hw.h             |   15 +
+ .../staging/fsl_ppfe/pfe_ls1012a_platform.c   |  383 +++
+ drivers/staging/fsl_ppfe/pfe_mod.c            |  158 +
+ drivers/staging/fsl_ppfe/pfe_mod.h            |  103 +
+ drivers/staging/fsl_ppfe/pfe_perfmon.h        |   26 +
+ drivers/staging/fsl_ppfe/pfe_sysfs.c          |  840 ++++++
+ drivers/staging/fsl_ppfe/pfe_sysfs.h          |   17 +
+ 40 files changed, 10977 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
+ create mode 100644 drivers/staging/fsl_ppfe/Kconfig
+ create mode 100644 drivers/staging/fsl_ppfe/Makefile
+ create mode 100644 drivers/staging/fsl_ppfe/TODO
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
+@@ -0,0 +1,199 @@
++=============================================================================
++NXP Programmable Packet Forwarding Engine Device Bindings
++
++CONTENTS
++  - PFE Node
++  - Ethernet Node
++
++=============================================================================
++PFE Node
++
++DESCRIPTION
++
++PFE Node has all the properties associated with Packet Forwarding Engine block.
++
++PROPERTIES
++
++- compatible
++		Usage: required
++		Value type: <stringlist>
++		Definition: Must include "fsl,pfe"
++
++- reg
++		Usage: required
++		Value type: <prop-encoded-array>
++		Definition: A standard property.
++		Specifies the offset of the following registers:
++		- PFE configuration registers
++		- DDR memory used by PFE
++
++- fsl,pfe-num-interfaces
++		Usage: required
++		Value type: <u32>
++		Definition: Must be present. Value can be either one or two.
++
++- interrupts
++		Usage: required
++		Value type: <prop-encoded-array>
++		Definition: Three interrupts are specified in this property.
++		- HIF interrupt
++		- HIF NO COPY interrupt
++		- Wake On LAN interrupt
++
++- interrupt-names
++		Usage: required
++		Value type: <stringlist>
++		Definition: Following strings are defined for the 3 interrupts.
++		"pfe_hif" - HIF interrupt
++		"pfe_hif_nocpy" - HIF NO COPY interrupt
++		"pfe_wol" - Wake On LAN interrupt
++
++- memory-region
++		Usage: required
++		Value type: <phandle>
++		Definition: phandle to a node describing reserved memory used by pfe.
++		Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
++
++- fsl,pfe-scfg
++		Usage: required
++		Value type: <phandle>
++		Definition: phandle for scfg.
++
++- fsl,rcpm-wakeup
++		Usage: required
++		Value type: <phandle>
++		Definition: phandle for rcpm.
++
++- clocks
++		Usage: required
++		Value type: <phandle>
++		Definition: phandle for clockgen.
++
++- clock-names
++		Usage: required
++		Value type: <string>
++		Definition: phandle for clock name.
++
++EXAMPLE
++
++pfe: pfe@04000000 {
++	compatible = "fsl,pfe";
++	reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
++		<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
++	reg-names = "pfe", "pfe-ddr";
++	fsl,pfe-num-interfaces = <0x2>;
++	interrupts = <0 172 0x4>,    /* HIF interrupt */
++		     <0 173 0x4>,    /*HIF_NOCPY interrupt */
++		     <0 174 0x4>;    /* WoL interrupt */
++	interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++	memory-region = <&pfe_reserved>;
++	fsl,pfe-scfg = <&scfg 0>;
++	fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++	clocks = <&clockgen 4 0>;
++	clock-names = "pfe";
++
++	status = "okay";
++	pfe_mac0: ethernet@0 {
++	};
++
++	pfe_mac1: ethernet@1 {
++	};
++};
++
++=============================================================================
++Ethernet Node
++
++DESCRIPTION
++
++Ethernet Node has all the properties associated with PFE used by platforms to
++connect to PHY:
++
++PROPERTIES
++
++- compatible
++		Usage: required
++		Value type: <stringlist>
++		Definition: Must include "fsl,pfe-gemac-port"
++
++- reg
++		Usage: required
++		Value type: <prop-encoded-array>
++		Definition: A standard property.
++		Specifies the gemacid of the interface.
++
++- fsl,gemac-bus-id
++		Usage: required
++		Value type: <u32>
++		Definition: Must be present. Value should be the id of the bus
++		connected to gemac.
++
++- fsl,gemac-phy-id (deprecated binding)
++               Usage: required
++               Value type: <u32>
++               Definition: This binding shouldn't be used with new platforms.
++	       Must be present. Value should be the id of the phy
++               connected to gemac.
++
++- fsl,mdio-mux-val
++		Usage: required
++		Value type: <u32>
++		Definition: Must be present. Value can be either 0 or 2 or 3.
++		This value is used to configure the mux to enable mdio.
++
++- phy-mode
++		Usage: required
++		Value type: <string>
++		Definition: Must include "sgmii"
++
++- fsl,pfe-phy-if-flags (deprecated binding)
++               Usage: required
++               Value type: <u32>
++               Definition: This binding shouldn't be used with new platforms.
++               Must be present. Value should be 0 by default.
++               If there is not phy connected, this need to be 1.
++
++- phy-handle
++		Usage: optional
++		Value type: <phandle>
++		Definition: phandle to the PHY device connected to this device.
++
++- mdio : A required subnode which specifies the mdio bus in the PFE and used as
++a container for phy nodes according to ../phy.txt.
++
++EXAMPLE
++
++ethernet@0 {
++	compatible = "fsl,pfe-gemac-port";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	reg = <0x0>;	/* GEM_ID */
++	fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++	fsl,mdio-mux-val = <0x0>;
++	phy-mode = "sgmii";
++	phy-handle = <&sgmii_phy1>;
++};
++
++
++ethernet@1 {
++	compatible = "fsl,pfe-gemac-port";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	reg = <0x1>;	/* GEM_ID */
++	fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
++	fsl,mdio-mux-val = <0x0>;
++	phy-mode = "sgmii";
++	phy-handle = <&sgmii_phy2>;
++};
++
++mdio@0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	sgmii_phy1: ethernet-phy@2 {
++		reg = <0x2>;
++	};
++
++	sgmii_phy2: ethernet-phy@1 {
++		reg = <0x1>;
++	};
++};
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -8359,6 +8359,14 @@ F:	drivers/ptp/ptp_qoriq.c
+ F:	drivers/ptp/ptp_qoriq_debugfs.c
+ F:	include/linux/fsl/ptp_qoriq.h
+ 
++FREESCALE QORIQ PPFE ETHERNET DRIVER
++M:	Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
++M:	Calvin Johnson <calvin.johnson@nxp.com>
++L:	netdev@vger.kernel.org
++S:	Maintained
++F:	drivers/staging/fsl_ppfe
++F:	Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
++
+ FREESCALE QUAD SPI DRIVER
+ M:	Han Xu <han.xu@nxp.com>
+ L:	linux-spi@vger.kernel.org
+--- a/drivers/staging/Kconfig
++++ b/drivers/staging/Kconfig
+@@ -78,4 +78,6 @@ source "drivers/staging/qlge/Kconfig"
+ 
+ source "drivers/staging/vme_user/Kconfig"
+ 
++source "drivers/staging/fsl_ppfe/Kconfig"
++
+ endif # STAGING
+--- a/drivers/staging/Makefile
++++ b/drivers/staging/Makefile
+@@ -28,3 +28,4 @@ obj-$(CONFIG_PI433)		+= pi433/
+ obj-$(CONFIG_XIL_AXIS_FIFO)	+= axis-fifo/
+ obj-$(CONFIG_FIELDBUS_DEV)     += fieldbus/
+ obj-$(CONFIG_QLGE)		+= qlge/
++obj-$(CONFIG_FSL_PPFE)		+= fsl_ppfe/
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Kconfig
+@@ -0,0 +1,21 @@
++#
++# Freescale Programmable Packet Forwarding Engine driver
++#
++config FSL_PPFE
++	tristate "Freescale PPFE Driver"
++	select FSL_GUTS
++	default n
++	help
++	Freescale LS1012A SoC has a Programmable Packet Forwarding Engine.
++	It provides two high performance ethernet interfaces.
++	This driver initializes, programs and controls the PPFE.
++	Use this driver to enable network connectivity on LS1012A platforms.
++
++if FSL_PPFE
++
++config FSL_PPFE_UTIL_DISABLED
++	bool "Disable PPFE UTIL Processor Engine"
++	help
++	UTIL PE has to be enabled only if required.
++
++endif # FSL_PPFE
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Makefile
+@@ -0,0 +1,20 @@
++#
++# Makefile for Freesecale PPFE driver
++#
++
++ccflags-y +=  -I $(srctree)/$(src)/include  -I $(srctree)/$(src)
++
++obj-$(CONFIG_FSL_PPFE) += pfe.o
++
++pfe-y += pfe_mod.o \
++	pfe_hw.o \
++	pfe_firmware.o \
++	pfe_ctrl.o \
++	pfe_hif.o \
++	pfe_hif_lib.o\
++	pfe_eth.o \
++	pfe_sysfs.o \
++	pfe_debugfs.o \
++	pfe_ls1012a_platform.o \
++	pfe_hal.o \
++	pfe_cdev.o
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/TODO
+@@ -0,0 +1,2 @@
++TODO:
++	- provide pfe pe monitoring support
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h
+@@ -0,0 +1,78 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CBUS_H_
++#define _CBUS_H_
++
++#define EMAC1_BASE_ADDR	(CBUS_BASE_ADDR + 0x200000)
++#define EGPI1_BASE_ADDR	(CBUS_BASE_ADDR + 0x210000)
++#define EMAC2_BASE_ADDR	(CBUS_BASE_ADDR + 0x220000)
++#define EGPI2_BASE_ADDR	(CBUS_BASE_ADDR + 0x230000)
++#define BMU1_BASE_ADDR	(CBUS_BASE_ADDR + 0x240000)
++#define BMU2_BASE_ADDR	(CBUS_BASE_ADDR + 0x250000)
++#define ARB_BASE_ADDR	(CBUS_BASE_ADDR + 0x260000)
++#define DDR_CONFIG_BASE_ADDR	(CBUS_BASE_ADDR + 0x270000)
++#define HIF_BASE_ADDR	(CBUS_BASE_ADDR + 0x280000)
++#define HGPI_BASE_ADDR	(CBUS_BASE_ADDR + 0x290000)
++#define LMEM_BASE_ADDR	(CBUS_BASE_ADDR + 0x300000)
++#define LMEM_SIZE	0x10000
++#define LMEM_END	(LMEM_BASE_ADDR + LMEM_SIZE)
++#define TMU_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x310000)
++#define CLASS_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x320000)
++#define HIF_NOCPY_BASE_ADDR	(CBUS_BASE_ADDR + 0x350000)
++#define UTIL_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x360000)
++#define CBUS_GPT_BASE_ADDR	(CBUS_BASE_ADDR + 0x370000)
++
++/*
++ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
++ * XXX_MEM_ACCESS_ADDR register bit definitions.
++ */
++#define PE_MEM_ACCESS_WRITE	BIT(31)	/* Internal Memory Write. */
++#define PE_MEM_ACCESS_IMEM	BIT(15)
++#define PE_MEM_ACCESS_DMEM	BIT(16)
++
++/* Byte Enables of the Internal memory access. These are interpred in BE */
++#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)	\
++	({ typeof(size) size_ = (size);		\
++	(((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
++
++#include "cbus/emac_mtip.h"
++#include "cbus/gpi.h"
++#include "cbus/bmu.h"
++#include "cbus/hif.h"
++#include "cbus/tmu_csr.h"
++#include "cbus/class_csr.h"
++#include "cbus/hif_nocpy.h"
++#include "cbus/util_csr.h"
++
++/* PFE cores states */
++#define CORE_DISABLE	0x00000000
++#define CORE_ENABLE	0x00000001
++#define CORE_SW_RESET	0x00000002
++
++/* LMEM defines */
++#define LMEM_HDR_SIZE	0x0010
++#define LMEM_BUF_SIZE_LN2	0x7
++#define LMEM_BUF_SIZE	BIT(LMEM_BUF_SIZE_LN2)
++
++/* DDR defines */
++#define DDR_HDR_SIZE	0x0100
++#define DDR_BUF_SIZE_LN2	0xb
++#define DDR_BUF_SIZE	BIT(DDR_BUF_SIZE_LN2)
++
++#endif /* _CBUS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _BMU_H_
++#define _BMU_H_
++
++#define BMU_VERSION	0x000
++#define BMU_CTRL	0x004
++#define BMU_UCAST_CONFIG	0x008
++#define BMU_UCAST_BASE_ADDR	0x00c
++#define BMU_BUF_SIZE	0x010
++#define BMU_BUF_CNT	0x014
++#define BMU_THRES	0x018
++#define BMU_INT_SRC	0x020
++#define BMU_INT_ENABLE	0x024
++#define BMU_ALLOC_CTRL	0x030
++#define BMU_FREE_CTRL	0x034
++#define BMU_FREE_ERR_ADDR	0x038
++#define BMU_CURR_BUF_CNT	0x03c
++#define BMU_MCAST_CNT	0x040
++#define BMU_MCAST_ALLOC_CTRL	0x044
++#define BMU_REM_BUF_CNT	0x048
++#define BMU_LOW_WATERMARK	0x050
++#define BMU_HIGH_WATERMARK	0x054
++#define BMU_INT_MEM_ACCESS	0x100
++
++struct BMU_CFG {
++	unsigned long baseaddr;
++	u32 count;
++	u32 size;
++	u32 low_watermark;
++	u32 high_watermark;
++};
++
++#define BMU1_BUF_SIZE	LMEM_BUF_SIZE_LN2
++#define BMU2_BUF_SIZE	DDR_BUF_SIZE_LN2
++
++#define BMU2_MCAST_ALLOC_CTRL	(BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)
++
++#endif /* _BMU_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+@@ -0,0 +1,289 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CLASS_CSR_H_
++#define _CLASS_CSR_H_
++
++/* @file class_csr.h.
++ * class_csr - block containing all the classifier control and status register.
++ * Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define CLASS_VERSION	(CLASS_CSR_BASE_ADDR + 0x000)
++#define CLASS_TX_CTRL	(CLASS_CSR_BASE_ADDR + 0x004)
++#define CLASS_INQ_PKTPTR	(CLASS_CSR_BASE_ADDR + 0x010)
++
++/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
++#define CLASS_HDR_SIZE	(CLASS_CSR_BASE_ADDR + 0x014)
++
++/* LMEM header size for the Classifier block.\ Data in the LMEM
++ * is written from this offset.
++ */
++#define CLASS_HDR_SIZE_LMEM(off)	((off) & 0x3f)
++
++/* DDR header size for the Classifier block.\ Data in the DDR
++ * is written from this offset.
++ */
++#define CLASS_HDR_SIZE_DDR(off)	(((off) & 0x1ff) << 16)
++
++#define CLASS_PE0_QB_DM_ADDR0	(CLASS_CSR_BASE_ADDR + 0x020)
++
++/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
++#define CLASS_PE0_QB_DM_ADDR1	(CLASS_CSR_BASE_ADDR + 0x024)
++
++/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
++#define CLASS_PE0_RO_DM_ADDR0	(CLASS_CSR_BASE_ADDR + 0x060)
++
++/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
++#define CLASS_PE0_RO_DM_ADDR1	(CLASS_CSR_BASE_ADDR + 0x064)
++
++/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
++
++/* @name Class PE memory access. Allows external PE's and HOST to
++ * read/write PMEM/DMEM memory ranges for each classifier PE.
++ */
++/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},
++ * See \ref XXX_MEM_ACCESS_ADDR for details.
++ */
++#define CLASS_MEM_ACCESS_ADDR	(CLASS_CSR_BASE_ADDR + 0x100)
++
++/* Internal Memory Access Write Data [31:0] */
++#define CLASS_MEM_ACCESS_WDATA	(CLASS_CSR_BASE_ADDR + 0x104)
++
++/* Internal Memory Access Read Data [31:0] */
++#define CLASS_MEM_ACCESS_RDATA	(CLASS_CSR_BASE_ADDR + 0x108)
++#define CLASS_TM_INQ_ADDR	(CLASS_CSR_BASE_ADDR + 0x114)
++#define CLASS_PE_STATUS	(CLASS_CSR_BASE_ADDR + 0x118)
++
++#define CLASS_PHY1_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x11c)
++#define CLASS_PHY1_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x120)
++#define CLASS_PHY1_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x124)
++#define CLASS_PHY1_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x128)
++#define CLASS_PHY1_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x12c)
++#define CLASS_PHY1_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x130)
++#define CLASS_PHY1_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x134)
++#define CLASS_PHY1_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x138)
++#define CLASS_PHY1_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x13c)
++#define CLASS_PHY1_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x140)
++#define CLASS_PHY2_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x144)
++#define CLASS_PHY2_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x148)
++#define CLASS_PHY2_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x14c)
++#define CLASS_PHY2_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x150)
++#define CLASS_PHY2_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x154)
++#define CLASS_PHY2_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x158)
++#define CLASS_PHY2_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x15c)
++#define CLASS_PHY2_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x160)
++#define CLASS_PHY2_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x164)
++#define CLASS_PHY2_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x168)
++#define CLASS_PHY3_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x16c)
++#define CLASS_PHY3_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x170)
++#define CLASS_PHY3_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x174)
++#define CLASS_PHY3_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x178)
++#define CLASS_PHY3_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x17c)
++#define CLASS_PHY3_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x180)
++#define CLASS_PHY3_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x184)
++#define CLASS_PHY3_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x188)
++#define CLASS_PHY3_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x18c)
++#define CLASS_PHY3_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x190)
++#define CLASS_PHY1_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x194)
++#define CLASS_PHY1_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x198)
++#define CLASS_PHY1_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x19c)
++#define CLASS_PHY1_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a0)
++#define CLASS_PHY2_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a4)
++#define CLASS_PHY2_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1a8)
++#define CLASS_PHY2_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1ac)
++#define CLASS_PHY2_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b0)
++#define CLASS_PHY3_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b4)
++#define CLASS_PHY3_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1b8)
++#define CLASS_PHY3_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1bc)
++#define CLASS_PHY3_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c0)
++#define CLASS_PHY4_ICMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c4)
++#define CLASS_PHY4_IGMP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1c8)
++#define CLASS_PHY4_TCP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1cc)
++#define CLASS_PHY4_UDP_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d0)
++#define CLASS_PHY4_RX_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d4)
++#define CLASS_PHY4_TX_PKTS	(CLASS_CSR_BASE_ADDR + 0x1d8)
++#define CLASS_PHY4_LP_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1dc)
++#define CLASS_PHY4_INTF_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e0)
++#define CLASS_PHY4_INTF_MATCH_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e4)
++#define CLASS_PHY4_L3_FAIL_PKTS	(CLASS_CSR_BASE_ADDR + 0x1e8)
++#define CLASS_PHY4_V4_PKTS	(CLASS_CSR_BASE_ADDR + 0x1ec)
++#define CLASS_PHY4_V6_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f0)
++#define CLASS_PHY4_CHKSUM_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f4)
++#define CLASS_PHY4_TTL_ERR_PKTS	(CLASS_CSR_BASE_ADDR + 0x1f8)
++
++#define CLASS_PE_SYS_CLK_RATIO	(CLASS_CSR_BASE_ADDR + 0x200)
++#define CLASS_AFULL_THRES	(CLASS_CSR_BASE_ADDR + 0x204)
++#define CLASS_GAP_BETWEEN_READS	(CLASS_CSR_BASE_ADDR + 0x208)
++#define CLASS_MAX_BUF_CNT	(CLASS_CSR_BASE_ADDR + 0x20c)
++#define CLASS_TSQ_FIFO_THRES	(CLASS_CSR_BASE_ADDR + 0x210)
++#define CLASS_TSQ_MAX_CNT	(CLASS_CSR_BASE_ADDR + 0x214)
++#define CLASS_IRAM_DATA_0	(CLASS_CSR_BASE_ADDR + 0x218)
++#define CLASS_IRAM_DATA_1	(CLASS_CSR_BASE_ADDR + 0x21c)
++#define CLASS_IRAM_DATA_2	(CLASS_CSR_BASE_ADDR + 0x220)
++#define CLASS_IRAM_DATA_3	(CLASS_CSR_BASE_ADDR + 0x224)
++
++#define CLASS_BUS_ACCESS_ADDR	(CLASS_CSR_BASE_ADDR + 0x228)
++
++#define CLASS_BUS_ACCESS_WDATA	(CLASS_CSR_BASE_ADDR + 0x22c)
++#define CLASS_BUS_ACCESS_RDATA	(CLASS_CSR_BASE_ADDR + 0x230)
++
++/* (route_entry_size[9:0], route_hash_size[23:16]
++ * (this is actually ln2(size)))
++ */
++#define CLASS_ROUTE_HASH_ENTRY_SIZE	(CLASS_CSR_BASE_ADDR + 0x234)
++
++#define CLASS_ROUTE_ENTRY_SIZE(size)	 ((size) & 0x1ff)
++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
++
++#define CLASS_ROUTE_TABLE_BASE	(CLASS_CSR_BASE_ADDR + 0x238)
++
++#define CLASS_ROUTE_MULTI	(CLASS_CSR_BASE_ADDR + 0x23c)
++#define CLASS_SMEM_OFFSET	(CLASS_CSR_BASE_ADDR + 0x240)
++#define CLASS_LMEM_BUF_SIZE	(CLASS_CSR_BASE_ADDR + 0x244)
++#define CLASS_VLAN_ID	(CLASS_CSR_BASE_ADDR + 0x248)
++#define CLASS_BMU1_BUF_FREE	(CLASS_CSR_BASE_ADDR + 0x24c)
++#define CLASS_USE_TMU_INQ	(CLASS_CSR_BASE_ADDR + 0x250)
++#define CLASS_VLAN_ID1	(CLASS_CSR_BASE_ADDR + 0x254)
++
++#define CLASS_BUS_ACCESS_BASE	(CLASS_CSR_BASE_ADDR + 0x258)
++#define CLASS_BUS_ACCESS_BASE_MASK	(0xFF000000)
++/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
++
++#define CLASS_HIF_PARSE	(CLASS_CSR_BASE_ADDR + 0x25c)
++
++#define CLASS_HOST_PE0_GP	(CLASS_CSR_BASE_ADDR + 0x260)
++#define CLASS_PE0_GP	(CLASS_CSR_BASE_ADDR + 0x264)
++#define CLASS_HOST_PE1_GP	(CLASS_CSR_BASE_ADDR + 0x268)
++#define CLASS_PE1_GP	(CLASS_CSR_BASE_ADDR + 0x26c)
++#define CLASS_HOST_PE2_GP	(CLASS_CSR_BASE_ADDR + 0x270)
++#define CLASS_PE2_GP	(CLASS_CSR_BASE_ADDR + 0x274)
++#define CLASS_HOST_PE3_GP	(CLASS_CSR_BASE_ADDR + 0x278)
++#define CLASS_PE3_GP	(CLASS_CSR_BASE_ADDR + 0x27c)
++#define CLASS_HOST_PE4_GP	(CLASS_CSR_BASE_ADDR + 0x280)
++#define CLASS_PE4_GP	(CLASS_CSR_BASE_ADDR + 0x284)
++#define CLASS_HOST_PE5_GP	(CLASS_CSR_BASE_ADDR + 0x288)
++#define CLASS_PE5_GP	(CLASS_CSR_BASE_ADDR + 0x28c)
++
++#define CLASS_PE_INT_SRC	(CLASS_CSR_BASE_ADDR + 0x290)
++#define CLASS_PE_INT_ENABLE	(CLASS_CSR_BASE_ADDR + 0x294)
++
++#define CLASS_TPID0_TPID1	(CLASS_CSR_BASE_ADDR + 0x298)
++#define CLASS_TPID2	(CLASS_CSR_BASE_ADDR + 0x29c)
++
++#define CLASS_L4_CHKSUM_ADDR	(CLASS_CSR_BASE_ADDR + 0x2a0)
++
++#define CLASS_PE0_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2a4)
++#define CLASS_PE1_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2a8)
++#define CLASS_PE2_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2ac)
++#define CLASS_PE3_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b0)
++#define CLASS_PE4_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b4)
++#define CLASS_PE5_DEBUG	(CLASS_CSR_BASE_ADDR + 0x2b8)
++
++#define CLASS_STATE	(CLASS_CSR_BASE_ADDR + 0x2bc)
++
++/* CLASS defines */
++#define CLASS_PBUF_SIZE	0x100	/* Fixed by hardware */
++#define CLASS_PBUF_HEADER_OFFSET	0x80	/* Can be configured */
++
++/* Can be configured */
++#define CLASS_PBUF0_BASE_ADDR	0x000
++/* Can be configured */
++#define CLASS_PBUF1_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
++/* Can be configured */
++#define CLASS_PBUF2_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
++/* Can be configured */
++#define CLASS_PBUF3_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
++
++#define CLASS_PBUF0_HEADER_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + \
++						CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF1_HEADER_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + \
++						CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF2_HEADER_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + \
++						CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF3_HEADER_BASE_ADDR	(CLASS_PBUF3_BASE_ADDR + \
++						CLASS_PBUF_HEADER_OFFSET)
++
++#define CLASS_PE0_RO_DM_ADDR0_VAL	((CLASS_PBUF1_BASE_ADDR << 16) | \
++						CLASS_PBUF0_BASE_ADDR)
++#define CLASS_PE0_RO_DM_ADDR1_VAL	((CLASS_PBUF3_BASE_ADDR << 16) | \
++						CLASS_PBUF2_BASE_ADDR)
++
++#define CLASS_PE0_QB_DM_ADDR0_VAL	((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\
++						CLASS_PBUF0_HEADER_BASE_ADDR)
++#define CLASS_PE0_QB_DM_ADDR1_VAL	((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\
++						CLASS_PBUF2_HEADER_BASE_ADDR)
++
++#define CLASS_ROUTE_SIZE	128
++#define CLASS_MAX_ROUTE_SIZE	256
++#define CLASS_ROUTE_HASH_BITS	20
++#define CLASS_ROUTE_HASH_MASK	(BIT(CLASS_ROUTE_HASH_BITS) - 1)
++
++/* Can be configured */
++#define	CLASS_ROUTE0_BASE_ADDR	0x400
++/* Can be configured */
++#define CLASS_ROUTE1_BASE_ADDR	(CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)
++/* Can be configured */
++#define CLASS_ROUTE2_BASE_ADDR	(CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)
++/* Can be configured */
++#define CLASS_ROUTE3_BASE_ADDR	(CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)
++
++#define CLASS_SA_SIZE	128
++#define CLASS_IPSEC_SA0_BASE_ADDR	0x600
++/* not used */
++#define CLASS_IPSEC_SA1_BASE_ADDR  (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)
++/* not used */
++#define CLASS_IPSEC_SA2_BASE_ADDR  (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)
++/* not used */
++#define CLASS_IPSEC_SA3_BASE_ADDR  (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)
++
++/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
++#define CLASS_GP_DMEM_BUF_SIZE	(2048 - (CLASS_PBUF_SIZE * 4) - \
++				(CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))
++#define CLASS_GP_DMEM_BUF	((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \
++					CLASS_SA_SIZE))
++
++#define TWO_LEVEL_ROUTE		BIT(0)
++#define PHYNO_IN_HASH		BIT(1)
++#define HW_ROUTE_FETCH		BIT(3)
++#define HW_BRIDGE_FETCH		BIT(5)
++#define IP_ALIGNED		BIT(6)
++#define ARC_HIT_CHECK_EN	BIT(7)
++#define CLASS_TOE		BIT(11)
++#define HASH_NORMAL		(0 << 12)
++#define HASH_CRC_PORT		BIT(12)
++#define HASH_CRC_IP		(2 << 12)
++#define HASH_CRC_PORT_IP	(3 << 12)
++#define QB2BUS_LE		BIT(15)
++
++#define TCP_CHKSUM_DROP		BIT(0)
++#define UDP_CHKSUM_DROP		BIT(1)
++#define IPV4_CHKSUM_DROP	BIT(9)
++
++/*CLASS_HIF_PARSE bits*/
++#define HIF_PKT_CLASS_EN	BIT(0)
++#define HIF_PKT_OFFSET(ofst)	(((ofst) & 0xF) << 1)
++
++struct class_cfg {
++	u32 toe_mode;
++	unsigned long route_table_baseaddr;
++	u32 route_table_hash_bits;
++	u32 pe_sys_clk_ratio;
++	u32 resume;
++};
++
++#endif /* _CLASS_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+@@ -0,0 +1,242 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _EMAC_H_
++#define _EMAC_H_
++
++#include <linux/ethtool.h>
++
++#define EMAC_IEVENT_REG		0x004
++#define EMAC_IMASK_REG		0x008
++#define EMAC_R_DES_ACTIVE_REG	0x010
++#define EMAC_X_DES_ACTIVE_REG	0x014
++#define EMAC_ECNTRL_REG		0x024
++#define EMAC_MII_DATA_REG	0x040
++#define EMAC_MII_CTRL_REG	0x044
++#define EMAC_MIB_CTRL_STS_REG	0x064
++#define EMAC_RCNTRL_REG		0x084
++#define EMAC_TCNTRL_REG		0x0C4
++#define EMAC_PHY_ADDR_LOW	0x0E4
++#define EMAC_PHY_ADDR_HIGH	0x0E8
++#define EMAC_GAUR		0x120
++#define EMAC_GALR		0x124
++#define EMAC_TFWR_STR_FWD	0x144
++#define EMAC_RX_SECTION_FULL	0x190
++#define EMAC_RX_SECTION_EMPTY	0x194
++#define EMAC_TX_SECTION_EMPTY	0x1A0
++#define EMAC_TRUNC_FL		0x1B0
++
++#define RMON_T_DROP	0x200 /* Count of frames not cntd correctly */
++#define RMON_T_PACKETS	0x204 /* RMON TX packet count */
++#define RMON_T_BC_PKT	0x208 /* RMON TX broadcast pkts */
++#define RMON_T_MC_PKT	0x20c /* RMON TX multicast pkts */
++#define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
++#define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
++#define RMON_T_OVERSIZE	0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
++#define RMON_T_FRAG	0x21c /* RMON TX pkts < 64 bytes, bad CRC */
++#define RMON_T_JAB	0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
++#define RMON_T_COL	0x224 /* RMON TX collision count */
++#define RMON_T_P64	0x228 /* RMON TX 64 byte pkts */
++#define RMON_T_P65TO127	0x22c /* RMON TX 65 to 127 byte pkts */
++#define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
++#define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
++#define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
++#define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
++#define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
++#define RMON_T_OCTETS	0x244 /* RMON TX octets */
++#define IEEE_T_DROP	0x248 /* Count of frames not counted crtly */
++#define IEEE_T_FRAME_OK	0x24c /* Frames tx'd OK */
++#define IEEE_T_1COL	0x250 /* Frames tx'd with single collision */
++#define IEEE_T_MCOL	0x254 /* Frames tx'd with multiple collision */
++#define IEEE_T_DEF	0x258 /* Frames tx'd after deferral delay */
++#define IEEE_T_LCOL	0x25c /* Frames tx'd with late collision */
++#define IEEE_T_EXCOL	0x260 /* Frames tx'd with excesv collisions */
++#define IEEE_T_MACERR	0x264 /* Frames tx'd with TX FIFO underrun */
++#define IEEE_T_CSERR	0x268 /* Frames tx'd with carrier sense err */
++#define IEEE_T_SQE	0x26c /* Frames tx'd with SQE err */
++#define IEEE_T_FDXFC	0x270 /* Flow control pause frames tx'd */
++#define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
++#define RMON_R_PACKETS	0x284 /* RMON RX packet count */
++#define RMON_R_BC_PKT	0x288 /* RMON RX broadcast pkts */
++#define RMON_R_MC_PKT	0x28c /* RMON RX multicast pkts */
++#define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
++#define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
++#define RMON_R_OVERSIZE	0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
++#define RMON_R_FRAG	0x29c /* RMON RX pkts < 64 bytes, bad CRC */
++#define RMON_R_JAB	0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
++#define RMON_R_RESVD_O	0x2a4 /* Reserved */
++#define RMON_R_P64	0x2a8 /* RMON RX 64 byte pkts */
++#define RMON_R_P65TO127	0x2ac /* RMON RX 65 to 127 byte pkts */
++#define RMON_R_P128TO255	0x2b0 /* RMON RX 128 to 255 byte pkts */
++#define RMON_R_P256TO511	0x2b4 /* RMON RX 256 to 511 byte pkts */
++#define RMON_R_P512TO1023	0x2b8 /* RMON RX 512 to 1023 byte pkts */
++#define RMON_R_P1024TO2047	0x2bc /* RMON RX 1024 to 2047 byte pkts */
++#define RMON_R_P_GTE2048	0x2c0 /* RMON RX pkts > 2048 bytes */
++#define RMON_R_OCTETS	0x2c4 /* RMON RX octets */
++#define IEEE_R_DROP	0x2c8 /* Count frames not counted correctly */
++#define IEEE_R_FRAME_OK	0x2cc /* Frames rx'd OK */
++#define IEEE_R_CRC	0x2d0 /* Frames rx'd with CRC err */
++#define IEEE_R_ALIGN	0x2d4 /* Frames rx'd with alignment err */
++#define IEEE_R_MACERR	0x2d8 /* Receive FIFO overflow count */
++#define IEEE_R_FDXFC	0x2dc /* Flow control pause frames rx'd */
++#define IEEE_R_OCTETS_OK	0x2e0 /* Octet cnt for frames rx'd w/o err */
++
++#define EMAC_SMAC_0_0	0x500 /*Supplemental MAC Address 0 (RW).*/
++#define EMAC_SMAC_0_1	0x504 /*Supplemental MAC Address 0 (RW).*/
++
++/* GEMAC definitions and settings */
++
++#define EMAC_PORT_0	0
++#define EMAC_PORT_1	1
++
++/* GEMAC Bit definitions */
++#define EMAC_IEVENT_HBERR		 0x80000000
++#define EMAC_IEVENT_BABR		 0x40000000
++#define EMAC_IEVENT_BABT		 0x20000000
++#define EMAC_IEVENT_GRA			 0x10000000
++#define EMAC_IEVENT_TXF			 0x08000000
++#define EMAC_IEVENT_TXB			 0x04000000
++#define EMAC_IEVENT_RXF			 0x02000000
++#define EMAC_IEVENT_RXB			 0x01000000
++#define EMAC_IEVENT_MII			 0x00800000
++#define EMAC_IEVENT_EBERR		 0x00400000
++#define EMAC_IEVENT_LC			 0x00200000
++#define EMAC_IEVENT_RL			 0x00100000
++#define EMAC_IEVENT_UN			 0x00080000
++
++#define EMAC_IMASK_HBERR                 0x80000000
++#define EMAC_IMASK_BABR                  0x40000000
++#define EMAC_IMASKT_BABT                 0x20000000
++#define EMAC_IMASK_GRA                   0x10000000
++#define EMAC_IMASKT_TXF                  0x08000000
++#define EMAC_IMASK_TXB                   0x04000000
++#define EMAC_IMASKT_RXF                  0x02000000
++#define EMAC_IMASK_RXB                   0x01000000
++#define EMAC_IMASK_MII                   0x00800000
++#define EMAC_IMASK_EBERR                 0x00400000
++#define EMAC_IMASK_LC                    0x00200000
++#define EMAC_IMASKT_RL                   0x00100000
++#define EMAC_IMASK_UN                    0x00080000
++
++#define EMAC_RCNTRL_MAX_FL_SHIFT         16
++#define EMAC_RCNTRL_LOOP                 0x00000001
++#define EMAC_RCNTRL_DRT                  0x00000002
++#define EMAC_RCNTRL_MII_MODE             0x00000004
++#define EMAC_RCNTRL_PROM                 0x00000008
++#define EMAC_RCNTRL_BC_REJ               0x00000010
++#define EMAC_RCNTRL_FCE                  0x00000020
++#define EMAC_RCNTRL_RGMII                0x00000040
++#define EMAC_RCNTRL_SGMII                0x00000080
++#define EMAC_RCNTRL_RMII                 0x00000100
++#define EMAC_RCNTRL_RMII_10T             0x00000200
++#define EMAC_RCNTRL_CRC_FWD		 0x00004000
++
++#define EMAC_TCNTRL_GTS                  0x00000001
++#define EMAC_TCNTRL_HBC                  0x00000002
++#define EMAC_TCNTRL_FDEN                 0x00000004
++#define EMAC_TCNTRL_TFC_PAUSE            0x00000008
++#define EMAC_TCNTRL_RFC_PAUSE            0x00000010
++
++#define EMAC_ECNTRL_RESET                0x00000001      /* reset the EMAC */
++#define EMAC_ECNTRL_ETHER_EN             0x00000002      /* enable the EMAC */
++#define EMAC_ECNTRL_MAGIC_ENA		 0x00000004
++#define EMAC_ECNTRL_SLEEP		 0x00000008
++#define EMAC_ECNTRL_SPEED                0x00000020
++#define EMAC_ECNTRL_DBSWAP               0x00000100
++
++#define EMAC_X_WMRK_STRFWD               0x00000100
++
++#define EMAC_X_DES_ACTIVE_TDAR           0x01000000
++#define EMAC_R_DES_ACTIVE_RDAR           0x01000000
++
++#define EMAC_RX_SECTION_EMPTY_V		0x00010006
++/*
++ * The possible operating speeds of the MAC, currently supporting 10, 100 and
++ * 1000Mb modes.
++ */
++enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
++
++/* MII-related definitios */
++#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
++#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
++#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */
++#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
++#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */
++#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
++#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
++#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
++#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
++
++#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
++#define EMAC_MII_DATA_RA_MASK	 0x1F      /* MII Register address mask */
++#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
++#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
++
++#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
++				EMAC_MII_DATA_RA_SHIFT)
++#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
++				EMAC_MII_DATA_PA_SHIFT)
++#define EMAC_MII_DATA(v)    ((v) & 0xffff)
++
++#define EMAC_MII_SPEED_SHIFT	1
++#define EMAC_HOLDTIME_SHIFT	8
++#define EMAC_HOLDTIME_MASK	0x7
++#define EMAC_HOLDTIME(v)	(((v) & EMAC_HOLDTIME_MASK) << \
++					EMAC_HOLDTIME_SHIFT)
++
++/*
++ * The Address organisation for the MAC device.  All addresses are split into
++ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
++ * the address and the other field are the high order bits - this may be 16-bits
++ * in the case of MAC addresses, or 32-bits for the hash address.
++ * In terms of memory storage, the first item (bottom) is assumed to be at a
++ * lower address location than 'top'. i.e. top should be at address location of
++ * 'bottom' + 4 bytes.
++ */
++struct pfe_mac_addr {
++	u32 bottom;     /* Lower 32-bits of address. */
++	u32 top;        /* Upper 32-bits of address. */
++};
++
++/*
++ * The following is the organisation of the address filters section of the MAC
++ * registers.  The Cadence MAC contains four possible specific address match
++ * addresses, if an incoming frame corresponds to any one of these four
++ * addresses then the frame will be copied to memory.
++ * It is not necessary for all four of the address match registers to be
++ * programmed, this is application dependent.
++ */
++struct spec_addr {
++	struct pfe_mac_addr one;        /* Specific address register 1. */
++	struct pfe_mac_addr two;        /* Specific address register 2. */
++	struct pfe_mac_addr three;      /* Specific address register 3. */
++	struct pfe_mac_addr four;       /* Specific address register 4. */
++};
++
++struct gemac_cfg {
++	u32 mode;
++	u32 speed;
++	u32 duplex;
++};
++
++/* EMAC Hash size */
++#define EMAC_HASH_REG_BITS       64
++
++#define EMAC_SPEC_ADDR_MAX	4
++
++#endif /* _EMAC_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+@@ -0,0 +1,86 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _GPI_H_
++#define _GPI_H_
++
++#define GPI_VERSION	0x00
++#define GPI_CTRL	0x04
++#define GPI_RX_CONFIG	0x08
++#define GPI_HDR_SIZE	0x0c
++#define GPI_BUF_SIZE	0x10
++#define GPI_LMEM_ALLOC_ADDR	0x14
++#define GPI_LMEM_FREE_ADDR	0x18
++#define GPI_DDR_ALLOC_ADDR	0x1c
++#define GPI_DDR_FREE_ADDR	0x20
++#define GPI_CLASS_ADDR	0x24
++#define GPI_DRX_FIFO	0x28
++#define GPI_TRX_FIFO	0x2c
++#define GPI_INQ_PKTPTR	0x30
++#define GPI_DDR_DATA_OFFSET	0x34
++#define GPI_LMEM_DATA_OFFSET	0x38
++#define GPI_TMLF_TX	0x4c
++#define GPI_DTX_ASEQ	0x50
++#define GPI_FIFO_STATUS	0x54
++#define GPI_FIFO_DEBUG	0x58
++#define GPI_TX_PAUSE_TIME	0x5c
++#define GPI_LMEM_SEC_BUF_DATA_OFFSET	0x60
++#define GPI_DDR_SEC_BUF_DATA_OFFSET	0x64
++#define GPI_TOE_CHKSUM_EN	0x68
++#define GPI_OVERRUN_DROPCNT	0x6c
++#define GPI_CSR_MTIP_PAUSE_REG		0x74
++#define GPI_CSR_MTIP_PAUSE_QUANTUM	0x78
++#define GPI_CSR_RX_CNT			0x7c
++#define GPI_CSR_TX_CNT			0x80
++#define GPI_CSR_DEBUG1			0x84
++#define GPI_CSR_DEBUG2			0x88
++
++struct gpi_cfg {
++	u32 lmem_rtry_cnt;
++	u32 tmlf_txthres;
++	u32 aseq_len;
++	u32 mtip_pause_reg;
++};
++
++/* GPI commons defines */
++#define GPI_LMEM_BUF_EN	0x1
++#define GPI_DDR_BUF_EN	0x1
++
++/* EGPI 1 defines */
++#define EGPI1_LMEM_RTRY_CNT	0x40
++#define EGPI1_TMLF_TXTHRES	0xBC
++#define EGPI1_ASEQ_LEN	0x50
++
++/* EGPI 2 defines */
++#define EGPI2_LMEM_RTRY_CNT	0x40
++#define EGPI2_TMLF_TXTHRES	0xBC
++#define EGPI2_ASEQ_LEN	0x40
++
++/* EGPI 3 defines */
++#define EGPI3_LMEM_RTRY_CNT	0x40
++#define EGPI3_TMLF_TXTHRES	0xBC
++#define EGPI3_ASEQ_LEN	0x40
++
++/* HGPI defines */
++#define HGPI_LMEM_RTRY_CNT	0x40
++#define HGPI_TMLF_TXTHRES	0xBC
++#define HGPI_ASEQ_LEN	0x40
++
++#define EGPI_PAUSE_TIME		0x000007D0
++#define EGPI_PAUSE_ENABLE	0x40000000
++#endif /* _GPI_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+@@ -0,0 +1,100 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HIF_H_
++#define _HIF_H_
++
++/* @file hif.h.
++ * hif - PFE hif block control and status register.
++ * Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define HIF_VERSION	(HIF_BASE_ADDR + 0x00)
++#define HIF_TX_CTRL	(HIF_BASE_ADDR + 0x04)
++#define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)
++#define HIF_TX_ALLOC	(HIF_BASE_ADDR + 0x0c)
++#define HIF_TX_BDP_ADDR	(HIF_BASE_ADDR + 0x10)
++#define HIF_TX_STATUS	(HIF_BASE_ADDR + 0x14)
++#define HIF_RX_CTRL	(HIF_BASE_ADDR + 0x20)
++#define HIF_RX_BDP_ADDR	(HIF_BASE_ADDR + 0x24)
++#define HIF_RX_STATUS	(HIF_BASE_ADDR + 0x30)
++#define HIF_INT_SRC	(HIF_BASE_ADDR + 0x34)
++#define HIF_INT_ENABLE	(HIF_BASE_ADDR + 0x38)
++#define HIF_POLL_CTRL	(HIF_BASE_ADDR + 0x3c)
++#define HIF_RX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x40)
++#define HIF_RX_ALLOC	(HIF_BASE_ADDR + 0x44)
++#define HIF_TX_DMA_STATUS	(HIF_BASE_ADDR + 0x48)
++#define HIF_RX_DMA_STATUS	(HIF_BASE_ADDR + 0x4c)
++#define HIF_INT_COAL	(HIF_BASE_ADDR + 0x50)
++
++/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
++#define HIF_INT		BIT(0)
++#define HIF_RXBD_INT	BIT(1)
++#define HIF_RXPKT_INT	BIT(2)
++#define HIF_TXBD_INT	BIT(3)
++#define HIF_TXPKT_INT	BIT(4)
++
++/* HIF_TX_CTRL bits */
++#define HIF_CTRL_DMA_EN			BIT(0)
++#define HIF_CTRL_BDP_POLL_CTRL_EN	BIT(1)
++#define HIF_CTRL_BDP_CH_START_WSTB	BIT(2)
++
++/* HIF_RX_STATUS bits */
++#define BDP_CSR_RX_DMA_ACTV     BIT(16)
++
++/* HIF_INT_ENABLE bits */
++#define HIF_INT_EN		BIT(0)
++#define HIF_RXBD_INT_EN		BIT(1)
++#define HIF_RXPKT_INT_EN	BIT(2)
++#define HIF_TXBD_INT_EN		BIT(3)
++#define HIF_TXPKT_INT_EN	BIT(4)
++
++/* HIF_POLL_CTRL bits*/
++#define HIF_RX_POLL_CTRL_CYCLE	0x0400
++#define HIF_TX_POLL_CTRL_CYCLE	0x0400
++
++/* HIF_INT_COAL bits*/
++#define HIF_INT_COAL_ENABLE	BIT(31)
++
++/* Buffer descriptor control bits */
++#define BD_CTRL_BUFLEN_MASK	0x3fff
++#define BD_BUF_LEN(x)	((x) & BD_CTRL_BUFLEN_MASK)
++#define BD_CTRL_CBD_INT_EN	BIT(16)
++#define BD_CTRL_PKT_INT_EN	BIT(17)
++#define BD_CTRL_LIFM		BIT(18)
++#define BD_CTRL_LAST_BD		BIT(19)
++#define BD_CTRL_DIR		BIT(20)
++#define BD_CTRL_LMEM_CPY	BIT(21) /* Valid only for HIF_NOCPY */
++#define BD_CTRL_PKT_XFER	BIT(24)
++#define BD_CTRL_DESC_EN		BIT(31)
++#define BD_CTRL_PARSE_DISABLE	BIT(25)
++#define BD_CTRL_BRFETCH_DISABLE	BIT(26)
++#define BD_CTRL_RTFETCH_DISABLE	BIT(27)
++
++/* Buffer descriptor status bits*/
++#define BD_STATUS_CONN_ID(x)	((x) & 0xffff)
++#define BD_STATUS_DIR_PROC_ID	BIT(16)
++#define BD_STATUS_CONN_ID_EN	BIT(17)
++#define BD_STATUS_PE2PROC_ID(x)	(((x) & 7) << 18)
++#define BD_STATUS_LE_DATA	BIT(21)
++#define BD_STATUS_CHKSUM_EN	BIT(22)
++
++/* HIF Buffer descriptor status bits */
++#define DIR_PROC_ID	BIT(16)
++#define PROC_ID(id)	((id) << 18)
++
++#endif /* _HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HIF_NOCPY_H_
++#define _HIF_NOCPY_H_
++
++#define HIF_NOCPY_VERSION	(HIF_NOCPY_BASE_ADDR + 0x00)
++#define HIF_NOCPY_TX_CTRL	(HIF_NOCPY_BASE_ADDR + 0x04)
++#define HIF_NOCPY_TX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x08)
++#define HIF_NOCPY_TX_ALLOC	(HIF_NOCPY_BASE_ADDR + 0x0c)
++#define HIF_NOCPY_TX_BDP_ADDR	(HIF_NOCPY_BASE_ADDR + 0x10)
++#define HIF_NOCPY_TX_STATUS	(HIF_NOCPY_BASE_ADDR + 0x14)
++#define HIF_NOCPY_RX_CTRL	(HIF_NOCPY_BASE_ADDR + 0x20)
++#define HIF_NOCPY_RX_BDP_ADDR	(HIF_NOCPY_BASE_ADDR + 0x24)
++#define HIF_NOCPY_RX_STATUS	(HIF_NOCPY_BASE_ADDR + 0x30)
++#define HIF_NOCPY_INT_SRC	(HIF_NOCPY_BASE_ADDR + 0x34)
++#define HIF_NOCPY_INT_ENABLE	(HIF_NOCPY_BASE_ADDR + 0x38)
++#define HIF_NOCPY_POLL_CTRL	(HIF_NOCPY_BASE_ADDR + 0x3c)
++#define HIF_NOCPY_RX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x40)
++#define HIF_NOCPY_RX_ALLOC	(HIF_NOCPY_BASE_ADDR + 0x44)
++#define HIF_NOCPY_TX_DMA_STATUS	(HIF_NOCPY_BASE_ADDR + 0x48)
++#define HIF_NOCPY_RX_DMA_STATUS	(HIF_NOCPY_BASE_ADDR + 0x4c)
++#define HIF_NOCPY_RX_INQ0_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x50)
++#define HIF_NOCPY_RX_INQ1_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x54)
++#define HIF_NOCPY_TX_PORT_NO	(HIF_NOCPY_BASE_ADDR + 0x60)
++#define HIF_NOCPY_LMEM_ALLOC_ADDR	(HIF_NOCPY_BASE_ADDR + 0x64)
++#define HIF_NOCPY_CLASS_ADDR	(HIF_NOCPY_BASE_ADDR + 0x68)
++#define HIF_NOCPY_TMU_PORT0_ADDR	(HIF_NOCPY_BASE_ADDR + 0x70)
++#define HIF_NOCPY_TMU_PORT1_ADDR	(HIF_NOCPY_BASE_ADDR + 0x74)
++#define HIF_NOCPY_TMU_PORT2_ADDR	(HIF_NOCPY_BASE_ADDR + 0x7c)
++#define HIF_NOCPY_TMU_PORT3_ADDR	(HIF_NOCPY_BASE_ADDR + 0x80)
++#define HIF_NOCPY_TMU_PORT4_ADDR	(HIF_NOCPY_BASE_ADDR + 0x84)
++#define HIF_NOCPY_INT_COAL	(HIF_NOCPY_BASE_ADDR + 0x90)
++
++#endif /* _HIF_NOCPY_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+@@ -0,0 +1,168 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _TMU_CSR_H_
++#define _TMU_CSR_H_
++
++#define TMU_VERSION	(TMU_CSR_BASE_ADDR + 0x000)
++#define TMU_INQ_WATERMARK	(TMU_CSR_BASE_ADDR + 0x004)
++#define TMU_PHY_INQ_PKTPTR	(TMU_CSR_BASE_ADDR + 0x008)
++#define TMU_PHY_INQ_PKTINFO	(TMU_CSR_BASE_ADDR + 0x00c)
++#define TMU_PHY_INQ_FIFO_CNT	(TMU_CSR_BASE_ADDR + 0x010)
++#define TMU_SYS_GENERIC_CONTROL	(TMU_CSR_BASE_ADDR + 0x014)
++#define TMU_SYS_GENERIC_STATUS	(TMU_CSR_BASE_ADDR + 0x018)
++#define TMU_SYS_GEN_CON0	(TMU_CSR_BASE_ADDR + 0x01c)
++#define TMU_SYS_GEN_CON1	(TMU_CSR_BASE_ADDR + 0x020)
++#define TMU_SYS_GEN_CON2	(TMU_CSR_BASE_ADDR + 0x024)
++#define TMU_SYS_GEN_CON3	(TMU_CSR_BASE_ADDR + 0x028)
++#define TMU_SYS_GEN_CON4	(TMU_CSR_BASE_ADDR + 0x02c)
++#define TMU_TEQ_DISABLE_DROPCHK	(TMU_CSR_BASE_ADDR + 0x030)
++#define TMU_TEQ_CTRL	(TMU_CSR_BASE_ADDR + 0x034)
++#define TMU_TEQ_QCFG	(TMU_CSR_BASE_ADDR + 0x038)
++#define TMU_TEQ_DROP_STAT	(TMU_CSR_BASE_ADDR + 0x03c)
++#define TMU_TEQ_QAVG	(TMU_CSR_BASE_ADDR + 0x040)
++#define TMU_TEQ_WREG_PROB	(TMU_CSR_BASE_ADDR + 0x044)
++#define TMU_TEQ_TRANS_STAT	(TMU_CSR_BASE_ADDR + 0x048)
++#define TMU_TEQ_HW_PROB_CFG0	(TMU_CSR_BASE_ADDR + 0x04c)
++#define TMU_TEQ_HW_PROB_CFG1	(TMU_CSR_BASE_ADDR + 0x050)
++#define TMU_TEQ_HW_PROB_CFG2	(TMU_CSR_BASE_ADDR + 0x054)
++#define TMU_TEQ_HW_PROB_CFG3	(TMU_CSR_BASE_ADDR + 0x058)
++#define TMU_TEQ_HW_PROB_CFG4	(TMU_CSR_BASE_ADDR + 0x05c)
++#define TMU_TEQ_HW_PROB_CFG5	(TMU_CSR_BASE_ADDR + 0x060)
++#define TMU_TEQ_HW_PROB_CFG6	(TMU_CSR_BASE_ADDR + 0x064)
++#define TMU_TEQ_HW_PROB_CFG7	(TMU_CSR_BASE_ADDR + 0x068)
++#define TMU_TEQ_HW_PROB_CFG8	(TMU_CSR_BASE_ADDR + 0x06c)
++#define TMU_TEQ_HW_PROB_CFG9	(TMU_CSR_BASE_ADDR + 0x070)
++#define TMU_TEQ_HW_PROB_CFG10	(TMU_CSR_BASE_ADDR + 0x074)
++#define TMU_TEQ_HW_PROB_CFG11	(TMU_CSR_BASE_ADDR + 0x078)
++#define TMU_TEQ_HW_PROB_CFG12	(TMU_CSR_BASE_ADDR + 0x07c)
++#define TMU_TEQ_HW_PROB_CFG13	(TMU_CSR_BASE_ADDR + 0x080)
++#define TMU_TEQ_HW_PROB_CFG14	(TMU_CSR_BASE_ADDR + 0x084)
++#define TMU_TEQ_HW_PROB_CFG15	(TMU_CSR_BASE_ADDR + 0x088)
++#define TMU_TEQ_HW_PROB_CFG16	(TMU_CSR_BASE_ADDR + 0x08c)
++#define TMU_TEQ_HW_PROB_CFG17	(TMU_CSR_BASE_ADDR + 0x090)
++#define TMU_TEQ_HW_PROB_CFG18	(TMU_CSR_BASE_ADDR + 0x094)
++#define TMU_TEQ_HW_PROB_CFG19	(TMU_CSR_BASE_ADDR + 0x098)
++#define TMU_TEQ_HW_PROB_CFG20	(TMU_CSR_BASE_ADDR + 0x09c)
++#define TMU_TEQ_HW_PROB_CFG21	(TMU_CSR_BASE_ADDR + 0x0a0)
++#define TMU_TEQ_HW_PROB_CFG22	(TMU_CSR_BASE_ADDR + 0x0a4)
++#define TMU_TEQ_HW_PROB_CFG23	(TMU_CSR_BASE_ADDR + 0x0a8)
++#define TMU_TEQ_HW_PROB_CFG24	(TMU_CSR_BASE_ADDR + 0x0ac)
++#define TMU_TEQ_HW_PROB_CFG25	(TMU_CSR_BASE_ADDR + 0x0b0)
++#define TMU_TDQ_IIFG_CFG	(TMU_CSR_BASE_ADDR + 0x0b4)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY0
++ */
++#define TMU_TDQ0_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x0b8)
++
++#define TMU_LLM_CTRL	(TMU_CSR_BASE_ADDR + 0x0bc)
++#define TMU_LLM_BASE_ADDR	(TMU_CSR_BASE_ADDR + 0x0c0)
++#define TMU_LLM_QUE_LEN	(TMU_CSR_BASE_ADDR + 0x0c4)
++#define TMU_LLM_QUE_HEADPTR	(TMU_CSR_BASE_ADDR + 0x0c8)
++#define TMU_LLM_QUE_TAILPTR	(TMU_CSR_BASE_ADDR + 0x0cc)
++#define TMU_LLM_QUE_DROPCNT	(TMU_CSR_BASE_ADDR + 0x0d0)
++#define TMU_INT_EN	(TMU_CSR_BASE_ADDR + 0x0d4)
++#define TMU_INT_SRC	(TMU_CSR_BASE_ADDR + 0x0d8)
++#define TMU_INQ_STAT	(TMU_CSR_BASE_ADDR + 0x0dc)
++#define TMU_CTRL	(TMU_CSR_BASE_ADDR + 0x0e0)
++
++/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
++ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
++ * the internal memory. This address is used to access both the PM and DM of
++ * all the PE's
++ */
++#define TMU_MEM_ACCESS_ADDR	(TMU_CSR_BASE_ADDR + 0x0e4)
++
++/* Internal Memory Access Write Data */
++#define TMU_MEM_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x0e8)
++/* Internal Memory Access Read Data. The commands are blocked
++ * at the mem_access only
++ */
++#define TMU_MEM_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x0ec)
++
++/* [31:0] PHY0 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY0_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f0)
++/* [31:0] PHY1 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY1_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f4)
++/* [31:0] PHY2 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY2_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0f8)
++/* [31:0] PHY3 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY3_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x0fc)
++#define TMU_BMU_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x100)
++#define TMU_TX_CTRL	(TMU_CSR_BASE_ADDR + 0x104)
++
++#define TMU_BUS_ACCESS_WDATA	(TMU_CSR_BASE_ADDR + 0x108)
++#define TMU_BUS_ACCESS	(TMU_CSR_BASE_ADDR + 0x10c)
++#define TMU_BUS_ACCESS_RDATA	(TMU_CSR_BASE_ADDR + 0x110)
++
++#define TMU_PE_SYS_CLK_RATIO	(TMU_CSR_BASE_ADDR + 0x114)
++#define TMU_PE_STATUS	(TMU_CSR_BASE_ADDR + 0x118)
++#define TMU_TEQ_MAX_THRESHOLD	(TMU_CSR_BASE_ADDR + 0x11c)
++/* [31:0] PHY4 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY4_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x134)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY1
++ */
++#define TMU_TDQ1_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x138)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY2
++ */
++#define TMU_TDQ2_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x13c)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY3
++ */
++#define TMU_TDQ3_SCH_CTRL	(TMU_CSR_BASE_ADDR + 0x140)
++#define TMU_BMU_BUF_SIZE	(TMU_CSR_BASE_ADDR + 0x144)
++/* [31:0] PHY5 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY5_INQ_ADDR	(TMU_CSR_BASE_ADDR + 0x148)
++
++#define SW_RESET		BIT(0)	/* Global software reset */
++#define INQ_RESET		BIT(2)
++#define TEQ_RESET		BIT(3)
++#define TDQ_RESET		BIT(4)
++#define PE_RESET		BIT(5)
++#define MEM_INIT		BIT(6)
++#define MEM_INIT_DONE		BIT(7)
++#define LLM_INIT		BIT(8)
++#define LLM_INIT_DONE		BIT(9)
++#define ECC_MEM_INIT_DONE	BIT(10)
++
++struct tmu_cfg {
++	u32 pe_sys_clk_ratio;
++	unsigned long llm_base_addr;
++	u32 llm_queue_len;
++};
++
++/* Not HW related for pfe_ctrl / pfe common defines */
++#define DEFAULT_MAX_QDEPTH	80
++#define DEFAULT_Q0_QDEPTH	511 /*We keep one large queue for host tx qos */
++#define DEFAULT_TMU3_QDEPTH	127
++
++#endif /* _TMU_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _UTIL_CSR_H_
++#define _UTIL_CSR_H_
++
++#define UTIL_VERSION	(UTIL_CSR_BASE_ADDR + 0x000)
++#define UTIL_TX_CTRL	(UTIL_CSR_BASE_ADDR + 0x004)
++#define UTIL_INQ_PKTPTR	(UTIL_CSR_BASE_ADDR + 0x010)
++
++#define UTIL_HDR_SIZE	(UTIL_CSR_BASE_ADDR + 0x014)
++
++#define UTIL_PE0_QB_DM_ADDR0	(UTIL_CSR_BASE_ADDR + 0x020)
++#define UTIL_PE0_QB_DM_ADDR1	(UTIL_CSR_BASE_ADDR + 0x024)
++#define UTIL_PE0_RO_DM_ADDR0	(UTIL_CSR_BASE_ADDR + 0x060)
++#define UTIL_PE0_RO_DM_ADDR1	(UTIL_CSR_BASE_ADDR + 0x064)
++
++#define UTIL_MEM_ACCESS_ADDR	(UTIL_CSR_BASE_ADDR + 0x100)
++#define UTIL_MEM_ACCESS_WDATA	(UTIL_CSR_BASE_ADDR + 0x104)
++#define UTIL_MEM_ACCESS_RDATA	(UTIL_CSR_BASE_ADDR + 0x108)
++
++#define UTIL_TM_INQ_ADDR	(UTIL_CSR_BASE_ADDR + 0x114)
++#define UTIL_PE_STATUS	(UTIL_CSR_BASE_ADDR + 0x118)
++
++#define UTIL_PE_SYS_CLK_RATIO	(UTIL_CSR_BASE_ADDR + 0x200)
++#define UTIL_AFULL_THRES	(UTIL_CSR_BASE_ADDR + 0x204)
++#define UTIL_GAP_BETWEEN_READS	(UTIL_CSR_BASE_ADDR + 0x208)
++#define UTIL_MAX_BUF_CNT	(UTIL_CSR_BASE_ADDR + 0x20c)
++#define UTIL_TSQ_FIFO_THRES	(UTIL_CSR_BASE_ADDR + 0x210)
++#define UTIL_TSQ_MAX_CNT	(UTIL_CSR_BASE_ADDR + 0x214)
++#define UTIL_IRAM_DATA_0	(UTIL_CSR_BASE_ADDR + 0x218)
++#define UTIL_IRAM_DATA_1	(UTIL_CSR_BASE_ADDR + 0x21c)
++#define UTIL_IRAM_DATA_2	(UTIL_CSR_BASE_ADDR + 0x220)
++#define UTIL_IRAM_DATA_3	(UTIL_CSR_BASE_ADDR + 0x224)
++
++#define UTIL_BUS_ACCESS_ADDR	(UTIL_CSR_BASE_ADDR + 0x228)
++#define UTIL_BUS_ACCESS_WDATA	(UTIL_CSR_BASE_ADDR + 0x22c)
++#define UTIL_BUS_ACCESS_RDATA	(UTIL_CSR_BASE_ADDR + 0x230)
++
++#define UTIL_INQ_AFULL_THRES	(UTIL_CSR_BASE_ADDR + 0x234)
++
++struct util_cfg {
++	u32 pe_sys_clk_ratio;
++};
++
++#endif /* _UTIL_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
+@@ -0,0 +1,372 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _PFE_H_
++#define _PFE_H_
++
++#include "cbus.h"
++
++#define CLASS_DMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
++/*
++ * Only valid for mem access register interface
++ */
++#define CLASS_IMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
++#define CLASS_DMEM_SIZE	0x00002000
++#define CLASS_IMEM_SIZE	0x00008000
++
++#define TMU_DMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
++/*
++ * Only valid for mem access register interface
++ */
++#define TMU_IMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
++#define TMU_DMEM_SIZE	0x00000800
++#define TMU_IMEM_SIZE	0x00002000
++
++#define UTIL_DMEM_BASE_ADDR	0x00000000
++#define UTIL_DMEM_SIZE	0x00002000
++
++#define PE_LMEM_BASE_ADDR	0xc3010000
++#define PE_LMEM_SIZE	0x8000
++#define PE_LMEM_END	(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++
++#define DMEM_BASE_ADDR	0x00000000
++#define DMEM_SIZE	0x2000	/* TMU has less... */
++#define DMEM_END	(DMEM_BASE_ADDR + DMEM_SIZE)
++
++#define PMEM_BASE_ADDR	0x00010000
++#define PMEM_SIZE	0x8000	/* TMU has less... */
++#define PMEM_END	(PMEM_BASE_ADDR + PMEM_SIZE)
++
++/* These check memory ranges from PE point of view/memory map */
++#define IS_DMEM(addr, len)				\
++	({ typeof(addr) addr_ = (addr);			\
++	((unsigned long)(addr_) >= DMEM_BASE_ADDR) &&	\
++	(((unsigned long)(addr_) + (len)) <= DMEM_END); })
++
++#define IS_PMEM(addr, len)				\
++	({ typeof(addr) addr_ = (addr);			\
++	((unsigned long)(addr_) >= PMEM_BASE_ADDR) &&	\
++	(((unsigned long)(addr_) + (len)) <= PMEM_END); })
++
++#define IS_PE_LMEM(addr, len)				\
++	({ typeof(addr) addr_ = (addr);			\
++	((unsigned long)(addr_) >=			\
++	PE_LMEM_BASE_ADDR) &&				\
++	(((unsigned long)(addr_) +			\
++	(len)) <= PE_LMEM_END); })
++
++#define IS_PFE_LMEM(addr, len)				\
++	({ typeof(addr) addr_ = (addr);			\
++	((unsigned long)(addr_) >=			\
++	CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&		\
++	(((unsigned long)(addr_) + (len)) <=		\
++	CBUS_VIRT_TO_PFE(LMEM_END)); })
++
++#define __IS_PHYS_DDR(addr, len)			\
++	({ typeof(addr) addr_ = (addr);			\
++	((unsigned long)(addr_) >=			\
++	DDR_PHYS_BASE_ADDR) &&				\
++	(((unsigned long)(addr_) + (len)) <=		\
++	DDR_PHYS_END); })
++
++#define IS_PHYS_DDR(addr, len)	__IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
++
++/*
++ * If using a run-time virtual address for the cbus base address use this code
++ */
++extern void *cbus_base_addr;
++extern void *ddr_base_addr;
++extern unsigned long ddr_phys_base_addr;
++extern unsigned int ddr_size;
++
++#define CBUS_BASE_ADDR	cbus_base_addr
++#define DDR_PHYS_BASE_ADDR	ddr_phys_base_addr
++#define DDR_BASE_ADDR	ddr_base_addr
++#define DDR_SIZE	ddr_size
++
++#define DDR_PHYS_END	(DDR_PHYS_BASE_ADDR + DDR_SIZE)
++
++#define LS1012A_PFE_RESET_WA	/*
++				 * PFE doesn't have global reset and re-init
++				 * should takecare few things to make PFE
++				 * functional after reset
++				 */
++#define PFE_CBUS_PHYS_BASE_ADDR	0xc0000000	/* CBUS physical base address
++						 * as seen by PE's.
++						 */
++/* CBUS physical base address as seen by PE's. */
++#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE	0xc0000000
++
++#define DDR_PHYS_TO_PFE(p)	(((unsigned long int)(p)) & 0x7FFFFFFF)
++#define DDR_PFE_TO_PHYS(p)	(((unsigned long int)(p)) | 0x80000000)
++#define CBUS_PHYS_TO_PFE(p)	(((p) - PFE_CBUS_PHYS_BASE_ADDR) + \
++				PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)
++/* Translates to PFE address map */
++
++#define DDR_PHYS_TO_VIRT(p)	(((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
++#define DDR_VIRT_TO_PHYS(v)	(((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
++#define DDR_VIRT_TO_PFE(p)	(DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
++
++#define CBUS_VIRT_TO_PFE(v)	(((v) - CBUS_BASE_ADDR) + \
++				PFE_CBUS_PHYS_BASE_ADDR)
++#define CBUS_PFE_TO_VIRT(p)	(((unsigned long int)(p) - \
++				PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
++
++/* The below part of the code is used in QOS control driver from host */
++#define TMU_APB_BASE_ADDR       0xc1000000      /* TMU base address seen by
++						 * pe's
++						 */
++
++enum {
++	CLASS0_ID = 0,
++	CLASS1_ID,
++	CLASS2_ID,
++	CLASS3_ID,
++	CLASS4_ID,
++	CLASS5_ID,
++	TMU0_ID,
++	TMU1_ID,
++	TMU2_ID,
++	TMU3_ID,
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	UTIL_ID,
++#endif
++	MAX_PE
++};
++
++#define CLASS_MASK	(BIT(CLASS0_ID) | BIT(CLASS1_ID) |\
++			BIT(CLASS2_ID) | BIT(CLASS3_ID) |\
++			BIT(CLASS4_ID) | BIT(CLASS5_ID))
++#define CLASS_MAX_ID	CLASS5_ID
++
++#define TMU_MASK	(BIT(TMU0_ID) | BIT(TMU1_ID) |\
++			BIT(TMU3_ID))
++
++#define TMU_MAX_ID	TMU3_ID
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++#define UTIL_MASK	BIT(UTIL_ID)
++#endif
++
++struct pe_status {
++	u32	cpu_state;
++	u32	activity_counter;
++	u32	rx;
++	union {
++	u32	tx;
++	u32	tmu_qstatus;
++	};
++	u32	drop;
++#if defined(CFG_PE_DEBUG)
++	u32	debug_indicator;
++	u32	debug[16];
++#endif
++} __aligned(16);
++
++struct pe_sync_mailbox {
++	u32 stop;
++	u32 stopped;
++};
++
++/* Drop counter definitions */
++
++#define	CLASS_NUM_DROP_COUNTERS	13
++#define	UTIL_NUM_DROP_COUNTERS	8
++
++/* PE information.
++ * Structure containing PE's specific information. It is used to create
++ * generic C functions common to all PE's.
++ * Before using the library functions this structure needs to be initialized
++ * with the different registers virtual addresses
++ * (according to the ARM MMU mmaping). The default initialization supports a
++ * virtual == physical mapping.
++ */
++struct pe_info {
++	u32 dmem_base_addr;	/* PE's dmem base address */
++	u32 pmem_base_addr;	/* PE's pmem base address */
++	u32 pmem_size;	/* PE's pmem size */
++
++	void *mem_access_wdata;	/* PE's _MEM_ACCESS_WDATA register
++				 * address
++				 */
++	void *mem_access_addr;	/* PE's _MEM_ACCESS_ADDR register
++				 * address
++				 */
++	void *mem_access_rdata;	/* PE's _MEM_ACCESS_RDATA register
++				 * address
++				 */
++};
++
++void pe_lmem_read(u32 *dst, u32 len, u32 offset);
++void pe_lmem_write(u32 *src, u32 len, u32 offset);
++
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++
++u32 pe_pmem_read(int id, u32 addr, u8 size);
++
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
++u32 pe_dmem_read(int id, u32 addr, u8 size);
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
++void class_bus_write(u32 val, u32 addr, u8 size);
++u32 class_bus_read(u32 addr, u8 size);
++
++#define class_bus_readl(addr)	class_bus_read(addr, 4)
++#define class_bus_readw(addr)	class_bus_read(addr, 2)
++#define class_bus_readb(addr)	class_bus_read(addr, 1)
++
++#define class_bus_writel(val, addr)	class_bus_write(val, addr, 4)
++#define class_bus_writew(val, addr)	class_bus_write(val, addr, 2)
++#define class_bus_writeb(val, addr)	class_bus_write(val, addr, 1)
++
++#define pe_dmem_readl(id, addr)	pe_dmem_read(id, addr, 4)
++#define pe_dmem_readw(id, addr)	pe_dmem_read(id, addr, 2)
++#define pe_dmem_readb(id, addr)	pe_dmem_read(id, addr, 1)
++
++#define pe_dmem_writel(id, val, addr)	pe_dmem_write(id, val, addr, 4)
++#define pe_dmem_writew(id, val, addr)	pe_dmem_write(id, val, addr, 2)
++#define pe_dmem_writeb(id, val, addr)	pe_dmem_write(id, val, addr, 1)
++
++/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */
++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
++			struct device *dev);
++
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
++		  unsigned int ddr_size);
++void bmu_init(void *base, struct BMU_CFG *cfg);
++void bmu_reset(void *base);
++void bmu_enable(void *base);
++void bmu_disable(void *base);
++void bmu_set_config(void *base, struct BMU_CFG *cfg);
++
++/*
++ * An enumerated type for loopback values.  This can be one of three values, no
++ * loopback -normal operation, local loopback with internal loopback module of
++ * MAC or PHY loopback which is through the external PHY.
++ */
++#ifndef __MAC_LOOP_ENUM__
++#define __MAC_LOOP_ENUM__
++enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};
++#endif
++
++void gemac_init(void *base, void *config);
++void gemac_disable_rx_checksum_offload(void *base);
++void gemac_enable_rx_checksum_offload(void *base);
++void gemac_set_speed(void *base, enum mac_speed gem_speed);
++void gemac_set_duplex(void *base, int duplex);
++void gemac_set_mode(void *base, int mode);
++void gemac_enable(void *base);
++void gemac_tx_disable(void *base);
++void gemac_tx_enable(void *base);
++void gemac_disable(void *base);
++void gemac_reset(void *base);
++void gemac_set_address(void *base, struct spec_addr *addr);
++struct spec_addr gemac_get_address(void *base);
++void gemac_set_loop(void *base, enum mac_loop gem_loop);
++void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
++		      unsigned int entry_index);
++void gemac_clear_laddr1(void *base);
++void gemac_clear_laddr2(void *base);
++void gemac_clear_laddr3(void *base);
++void gemac_clear_laddr4(void *base);
++void gemac_clear_laddrN(void *base, unsigned int entry_index);
++struct pfe_mac_addr gemac_get_hash(void *base);
++void gemac_set_hash(void *base, struct pfe_mac_addr *hash);
++struct pfe_mac_addr gem_get_laddr1(void *base);
++struct pfe_mac_addr gem_get_laddr2(void *base);
++struct pfe_mac_addr gem_get_laddr3(void *base);
++struct pfe_mac_addr gem_get_laddr4(void *base);
++struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);
++void gemac_set_config(void *base, struct gemac_cfg *cfg);
++void gemac_allow_broadcast(void *base);
++void gemac_no_broadcast(void *base);
++void gemac_enable_1536_rx(void *base);
++void gemac_disable_1536_rx(void *base);
++void gemac_set_rx_max_fl(void *base, int mtu);
++void gemac_enable_rx_jmb(void *base);
++void gemac_disable_rx_jmb(void *base);
++void gemac_enable_stacked_vlan(void *base);
++void gemac_disable_stacked_vlan(void *base);
++void gemac_enable_pause_rx(void *base);
++void gemac_disable_pause_rx(void *base);
++void gemac_enable_copy_all(void *base);
++void gemac_disable_copy_all(void *base);
++void gemac_set_bus_width(void *base, int width);
++void gemac_set_wol(void *base, u32 wol_conf);
++
++void gpi_init(void *base, struct gpi_cfg *cfg);
++void gpi_reset(void *base);
++void gpi_enable(void *base);
++void gpi_disable(void *base);
++void gpi_set_config(void *base, struct gpi_cfg *cfg);
++
++void class_init(struct class_cfg *cfg);
++void class_reset(void);
++void class_enable(void);
++void class_disable(void);
++void class_set_config(struct class_cfg *cfg);
++
++void tmu_reset(void);
++void tmu_init(struct tmu_cfg *cfg);
++void tmu_enable(u32 pe_mask);
++void tmu_disable(u32 pe_mask);
++u32  tmu_qstatus(u32 if_id);
++u32  tmu_pkts_processed(u32 if_id);
++
++void util_init(struct util_cfg *cfg);
++void util_reset(void);
++void util_enable(void);
++void util_disable(void);
++
++void hif_init(void);
++void hif_tx_enable(void);
++void hif_tx_disable(void);
++void hif_rx_enable(void);
++void hif_rx_disable(void);
++
++/* Get Chip Revision level
++ *
++ */
++static inline unsigned int CHIP_REVISION(void)
++{
++	/*For LS1012A return always 1 */
++	return 1;
++}
++
++/* Start HIF rx DMA
++ *
++ */
++static inline void hif_rx_dma_start(void)
++{
++	writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
++}
++
++/* Start HIF tx DMA
++ *
++ */
++static inline void hif_tx_dma_start(void)
++{
++	writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
++}
++
++#endif /* _PFE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c
+@@ -0,0 +1,258 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2018 NXP
++ */
++
++/* @pfe_cdev.c.
++ *  Dummy device representing the PFE US in userspace.
++ *  - used for interacting with the kernel layer for link status
++ */
++
++#include <linux/eventfd.h>
++#include <linux/irqreturn.h>
++#include <linux/io.h>
++#include <asm/irq.h>
++
++#include "pfe_cdev.h"
++#include "pfe_mod.h"
++
++static int pfe_majno;
++static struct class *pfe_char_class;
++static struct device *pfe_char_dev;
++struct eventfd_ctx *g_trigger;
++
++struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
++
++static int pfe_cdev_open(struct inode *inp, struct file *fp)
++{
++	pr_debug("PFE CDEV device opened.\n");
++	return 0;
++}
++
++static ssize_t pfe_cdev_read(struct file *fp, char *buf,
++			     size_t len, loff_t *off)
++{
++	int ret = 0;
++
++	pr_info("PFE CDEV attempt copying (%lu) size of user.\n",
++		sizeof(link_states));
++
++	pr_debug("Dump link_state on screen before copy_to_user\n");
++	for (; ret < PFE_CDEV_ETH_COUNT; ret++) {
++		pr_debug("%u  %u", link_states[ret].phy_id,
++			 link_states[ret].state);
++		pr_debug("\n");
++	}
++
++	/* Copy to user the value in buffer sized len */
++	ret = copy_to_user(buf, &link_states, sizeof(link_states));
++	if (ret != 0) {
++		pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
++		       ret, len);
++		return -EFAULT;
++	}
++
++	/* offset set back to 0 as there is contextual reading offset */
++	*off = 0;
++	pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
++
++	return sizeof(link_states);
++}
++
++/**
++ * This function is for getting some commands from user through non-IOCTL
++ * channel. It can used to configure the device.
++ * TODO: To be filled in future, if require duplex communication with user
++ * space.
++ */
++static ssize_t pfe_cdev_write(struct file *fp, const char *buf,
++			      size_t len, loff_t *off)
++{
++	pr_info("PFE CDEV Write operation not supported!\n");
++
++	return -EFAULT;
++}
++
++static int pfe_cdev_release(struct inode *inp, struct file *fp)
++{
++	if (g_trigger) {
++		free_irq(pfe->hif_irq, g_trigger);
++		eventfd_ctx_put(g_trigger);
++		g_trigger = NULL;
++	}
++
++	pr_info("PFE_CDEV: Device successfully closed\n");
++	return 0;
++}
++
++/*
++ * hif_us_isr-
++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
++ */
++static irqreturn_t hif_us_isr(int irq, void *arg)
++{
++	struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg;
++	int int_status;
++	int int_enable_mask;
++
++	/*Read hif interrupt source register */
++	int_status = readl_relaxed(HIF_INT_SRC);
++	int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
++
++	if ((int_status & HIF_INT) == 0)
++		return IRQ_NONE;
++
++	if (int_status & HIF_RXPKT_INT) {
++		int_enable_mask &= ~(HIF_RXPKT_INT);
++		/* Disable interrupts, they will be enabled after
++		 * they are serviced
++		 */
++		writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
++
++		eventfd_signal(trigger, 1);
++	}
++
++	return IRQ_HANDLED;
++}
++
++#define PFE_INTR_COAL_USECS	100
++static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd,
++			   unsigned long arg)
++{
++	int ret = -EFAULT;
++	int __user *argp = (int __user *)arg;
++
++	pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd);
++
++	switch (cmd) {
++	case PFE_CDEV_ETH0_STATE_GET:
++		/* Return an unsigned int (link state) for ETH0 */
++		*argp = link_states[0].state;
++		pr_debug("Returning state=%d for ETH0\n", *argp);
++		ret = 0;
++		break;
++	case PFE_CDEV_ETH1_STATE_GET:
++		/* Return an unsigned int (link state) for ETH0 */
++		*argp = link_states[1].state;
++		pr_debug("Returning state=%d for ETH1\n", *argp);
++		ret = 0;
++		break;
++	case PFE_CDEV_HIF_INTR_EN:
++		/* Return success/failure */
++		g_trigger = eventfd_ctx_fdget(*argp);
++		if (IS_ERR(g_trigger))
++			return PTR_ERR(g_trigger);
++		ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif",
++				  g_trigger);
++		if (ret) {
++			pr_err("%s: failed to get the hif IRQ = %d\n",
++			       __func__, pfe->hif_irq);
++			eventfd_ctx_put(g_trigger);
++			g_trigger = NULL;
++		}
++		writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) |
++			HIF_INT_COAL_ENABLE, HIF_INT_COAL);
++
++		pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq);
++		ret = 0;
++		break;
++	default:
++		pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd);
++		break;
++	};
++
++	return ret;
++}
++
++static unsigned int pfe_cdev_poll(struct file *fp,
++				  struct poll_table_struct *wait)
++{
++	pr_info("PFE CDEV poll method not supported\n");
++	return 0;
++}
++
++static const struct file_operations pfe_cdev_fops = {
++	.open = pfe_cdev_open,
++	.read = pfe_cdev_read,
++	.write = pfe_cdev_write,
++	.release = pfe_cdev_release,
++	.unlocked_ioctl = pfe_cdev_ioctl,
++	.poll = pfe_cdev_poll,
++};
++
++int pfe_cdev_init(void)
++{
++	int ret;
++
++	pr_debug("PFE CDEV initialization begin\n");
++
++	/* Register the major number for the device */
++	pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops);
++	if (pfe_majno < 0) {
++		pr_err("Unable to register PFE CDEV. PFE CDEV not available\n");
++		ret = pfe_majno;
++		goto cleanup;
++	}
++
++	pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno);
++
++	/* Register the class for the device */
++	pfe_char_class = class_create(PFE_CLASS_NAME);
++	if (IS_ERR(pfe_char_class)) {
++		pr_err(
++		"Failed to init class for PFE CDEV. PFE CDEV not available.\n");
++		ret = PTR_ERR(pfe_char_class);
++		goto cleanup;
++	}
++
++	pr_debug("PFE CDEV Class created successfully.\n");
++
++	/* Create the device without any parent and without any callback data */
++	    pfe_char_dev = device_create(pfe_char_class, NULL,
++					 MKDEV(pfe_majno, 0), NULL,
++					 PFE_CDEV_NAME);
++	if (IS_ERR(pfe_char_dev)) {
++		pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n");
++		ret = PTR_ERR(pfe_char_dev);
++		goto cleanup;
++	}
++
++	/* Information structure being shared with the userspace */
++	memset(link_states, 0, sizeof(struct pfe_shared_info) *
++			PFE_CDEV_ETH_COUNT);
++
++	pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME);
++
++	ret = 0;
++	return ret;
++
++cleanup:
++	if (!IS_ERR(pfe_char_class))
++		class_destroy(pfe_char_class);
++
++	if (pfe_majno > 0)
++		unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
++
++	return ret;
++}
++
++void pfe_cdev_exit(void)
++{
++	if (!IS_ERR(pfe_char_dev))
++		device_destroy(pfe_char_class, MKDEV(pfe_majno, 0));
++
++	if (!IS_ERR(pfe_char_class)) {
++		class_unregister(pfe_char_class);
++		class_destroy(pfe_char_class);
++	}
++
++	if (pfe_majno > 0)
++		unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
++
++	/* reset the variables */
++	pfe_majno = 0;
++	pfe_char_class = NULL;
++	pfe_char_dev = NULL;
++
++	pr_info("PFE CDEV Removed.\n");
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.h
+@@ -0,0 +1,41 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2018 NXP
++ */
++
++#ifndef _PFE_CDEV_H_
++#define _PFE_CDEV_H_
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/uaccess.h>
++#include <linux/poll.h>
++
++#define  PFE_CDEV_NAME "pfe_us_cdev"
++#define  PFE_CLASS_NAME  "ppfe_us"
++
++/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are
++ * supported by PFE driver. Should be updated if number of eth devices are
++ * changed.
++ */
++#define PFE_CDEV_ETH_COUNT 3
++
++struct pfe_shared_info {
++	uint32_t phy_id; /* Link phy ID */
++	uint8_t state;  /* Has either 0 or 1 */
++};
++
++extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
++
++/* IOCTL Commands */
++#define PFE_CDEV_ETH0_STATE_GET		_IOR('R', 0, int)
++#define PFE_CDEV_ETH1_STATE_GET		_IOR('R', 1, int)
++#define PFE_CDEV_HIF_INTR_EN		_IOWR('R', 2, int)
++
++int pfe_cdev_init(void);
++void pfe_cdev_exit(void);
++
++#endif /* _PFE_CDEV_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c
+@@ -0,0 +1,226 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++
++#include "pfe_mod.h"
++#include "pfe_ctrl.h"
++
++#define TIMEOUT_MS	1000
++
++int relax(unsigned long end)
++{
++	if (time_after(jiffies, end)) {
++		if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000))
++			return -1;
++
++		if (need_resched())
++			schedule();
++	}
++
++	return 0;
++}
++
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl)
++{
++	int id;
++
++	mutex_lock(&ctrl->mutex);
++
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++		pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4);
++
++	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++		if (id == TMU2_ID)
++			continue;
++		pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4);
++	}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4);
++#endif
++	mutex_unlock(&ctrl->mutex);
++}
++
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl)
++{
++	int pe_mask = CLASS_MASK | TMU_MASK;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	pe_mask |= UTIL_MASK;
++#endif
++	mutex_lock(&ctrl->mutex);
++	pe_start(&pfe->ctrl, pe_mask);
++	mutex_unlock(&ctrl->mutex);
++}
++
++/* PE sync stop.
++ * Stops packet processing for a list of PE's (specified using a bitmask).
++ * The caller must hold ctrl->mutex.
++ *
++ * @param ctrl		Control context
++ * @param pe_mask	Mask of PE id's to stop
++ *
++ */
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask)
++{
++	struct pe_sync_mailbox *mbox;
++	int pe_stopped = 0;
++	unsigned long end = jiffies + 2;
++	int i;
++
++	pe_mask &= 0x2FF;  /*Exclude Util + TMU2 */
++
++	for (i = 0; i < MAX_PE; i++)
++		if (pe_mask & (1 << i)) {
++			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++			pe_dmem_write(i, cpu_to_be32(0x1), (unsigned
++					long)&mbox->stop, 4);
++		}
++
++	while (pe_stopped != pe_mask) {
++		for (i = 0; i < MAX_PE; i++)
++			if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
++				mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++				if (pe_dmem_read(i, (unsigned
++					long)&mbox->stopped, 4) &
++					cpu_to_be32(0x1))
++					pe_stopped |= (1 << i);
++			}
++
++		if (relax(end) < 0)
++			goto err;
++	}
++
++	return 0;
++
++err:
++	pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
++
++	for (i = 0; i < MAX_PE; i++)
++		if (pe_mask & (1 << i)) {
++			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++			pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
++					long)&mbox->stop, 4);
++	}
++
++	return -EIO;
++}
++
++/* PE start.
++ * Starts packet processing for a list of PE's (specified using a bitmask).
++ * The caller must hold ctrl->mutex.
++ *
++ * @param ctrl		Control context
++ * @param pe_mask	Mask of PE id's to start
++ *
++ */
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask)
++{
++	struct pe_sync_mailbox *mbox;
++	int i;
++
++	for (i = 0; i < MAX_PE; i++)
++		if (pe_mask & (1 << i)) {
++			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++			pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
++					long)&mbox->stop, 4);
++		}
++}
++
++/* This function will ensure all PEs are put in to idle state */
++int pe_reset_all(struct pfe_ctrl *ctrl)
++{
++	struct pe_sync_mailbox *mbox;
++	int pe_stopped = 0;
++	unsigned long end = jiffies + 2;
++	int i;
++	int pe_mask  = CLASS_MASK | TMU_MASK;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	pe_mask |= UTIL_MASK;
++#endif
++
++	for (i = 0; i < MAX_PE; i++)
++		if (pe_mask & (1 << i)) {
++			mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++			pe_dmem_write(i, cpu_to_be32(0x2), (unsigned
++					long)&mbox->stop, 4);
++		}
++
++	while (pe_stopped != pe_mask) {
++		for (i = 0; i < MAX_PE; i++)
++			if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
++				mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++				if (pe_dmem_read(i, (unsigned long)
++							&mbox->stopped, 4) &
++						cpu_to_be32(0x1))
++					pe_stopped |= (1 << i);
++			}
++
++		if (relax(end) < 0)
++			goto err;
++	}
++
++	return 0;
++
++err:
++	pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
++	return -EIO;
++}
++
++int pfe_ctrl_init(struct pfe *pfe)
++{
++	struct pfe_ctrl *ctrl = &pfe->ctrl;
++	int id;
++
++	pr_info("%s\n", __func__);
++
++	mutex_init(&ctrl->mutex);
++	spin_lock_init(&ctrl->lock);
++
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++		ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX;
++		ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX;
++	}
++
++	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++		if (id == TMU2_ID)
++			continue;
++		ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX;
++		ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX;
++	}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX;
++	ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX;
++#endif
++
++	ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR;
++	ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr +
++						ROUTE_TABLE_BASEADDR;
++
++	ctrl->dev = pfe->dev;
++
++	pr_info("%s finished\n", __func__);
++
++	return 0;
++}
++
++void pfe_ctrl_exit(struct pfe *pfe)
++{
++	pr_info("%s\n", __func__);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h
+@@ -0,0 +1,100 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_CTRL_H_
++#define _PFE_CTRL_H_
++
++#include <linux/dmapool.h>
++
++#include "pfe/pfe.h"
++
++#define DMA_BUF_SIZE_128	0x80	/* enough for 1 conntracks */
++#define DMA_BUF_SIZE_256	0x100
++/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */
++#define DMA_BUF_SIZE_512	0x200
++/* 512bytes dma allocated buffers used by rtp relay feature */
++#define DMA_BUF_MIN_ALIGNMENT	8
++#define DMA_BUF_BOUNDARY	(4 * 1024)
++/* bursts can not cross 4k boundary */
++
++#define CMD_TX_ENABLE	0x0501
++#define CMD_TX_DISABLE	0x0502
++
++#define CMD_RX_LRO		0x0011
++#define CMD_PKTCAP_ENABLE       0x0d01
++#define CMD_QM_EXPT_RATE	0x020c
++
++#define CLASS_DM_SH_STATIC		(0x800)
++#define CLASS_DM_CPU_TICKS		(CLASS_DM_SH_STATIC)
++#define CLASS_DM_SYNC_MBOX		(0x808)
++#define CLASS_DM_MSG_MBOX		(0x810)
++#define CLASS_DM_DROP_CNTR		(0x820)
++#define CLASS_DM_RESUME			(0x854)
++#define CLASS_DM_PESTATUS		(0x860)
++#define CLASS_DM_CRC_VALIDATED		(0x14b0)
++
++#define TMU_DM_SH_STATIC		(0x80)
++#define TMU_DM_CPU_TICKS		(TMU_DM_SH_STATIC)
++#define TMU_DM_SYNC_MBOX		(0x88)
++#define TMU_DM_MSG_MBOX			(0x90)
++#define TMU_DM_RESUME			(0xA0)
++#define TMU_DM_PESTATUS			(0xB0)
++#define TMU_DM_CONTEXT			(0x300)
++#define TMU_DM_TX_TRANS			(0x480)
++
++#define UTIL_DM_SH_STATIC		(0x0)
++#define UTIL_DM_CPU_TICKS		(UTIL_DM_SH_STATIC)
++#define UTIL_DM_SYNC_MBOX		(0x8)
++#define UTIL_DM_MSG_MBOX		(0x10)
++#define UTIL_DM_DROP_CNTR		(0x20)
++#define UTIL_DM_RESUME			(0x40)
++#define UTIL_DM_PESTATUS		(0x50)
++
++struct pfe_ctrl {
++	struct mutex mutex; /* to serialize pfe control access */
++	spinlock_t lock;
++
++	void *dma_pool;
++	void *dma_pool_512;
++	void *dma_pool_128;
++
++	struct device *dev;
++
++	void *hash_array_baseaddr;		/*
++						 * Virtual base address of
++						 * the conntrack hash array
++						 */
++	unsigned long hash_array_phys_baseaddr; /*
++						 * Physical base address of
++						 * the conntrack hash array
++						 */
++
++	int (*event_cb)(u16, u16, u16*);
++
++	unsigned long sync_mailbox_baseaddr[MAX_PE]; /*
++						      * Sync mailbox PFE
++						      * internal address,
++						      * initialized
++						      * when parsing elf images
++						      */
++	unsigned long msg_mailbox_baseaddr[MAX_PE]; /*
++						     * Msg mailbox PFE internal
++						     * address, initialized
++						     * when parsing elf images
++						     */
++	unsigned int sys_clk;			/* AXI clock value, in KHz */
++};
++
++int pfe_ctrl_init(struct pfe *pfe);
++void pfe_ctrl_exit(struct pfe *pfe);
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask);
++int pe_reset_all(struct pfe_ctrl *ctrl);
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl);
++int relax(unsigned long end);
++
++#endif /* _PFE_CTRL_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c
+@@ -0,0 +1,99 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++
++static int dmem_show(struct seq_file *s, void *unused)
++{
++	u32 dmem_addr, val;
++	int id = (long int)s->private;
++	int i;
++
++	for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) {
++		seq_printf(s, "%04x:", dmem_addr);
++
++		for (i = 0; i < 8; i++) {
++			val = pe_dmem_read(id, dmem_addr + i * 4, 4);
++			seq_printf(s, " %02x %02x %02x %02x", val & 0xff,
++				   (val >> 8) & 0xff, (val >> 16) & 0xff,
++				   (val >> 24) & 0xff);
++		}
++
++		seq_puts(s, "\n");
++	}
++
++	return 0;
++}
++
++static int dmem_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, dmem_show, inode->i_private);
++}
++
++static const struct file_operations dmem_fops = {
++	.open		= dmem_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++int pfe_debugfs_init(struct pfe *pfe)
++{
++	struct dentry *d;
++
++	pr_info("%s\n", __func__);
++
++	pfe->dentry = debugfs_create_dir("pfe", NULL);
++	if (IS_ERR_OR_NULL(pfe->dentry))
++		goto err_dir;
++
++	d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5,
++				&dmem_fops);
++	if (IS_ERR_OR_NULL(d))
++		goto err_pe;
++
++	return 0;
++
++err_pe:
++	debugfs_remove_recursive(pfe->dentry);
++
++err_dir:
++	return -1;
++}
++
++void pfe_debugfs_exit(struct pfe *pfe)
++{
++	debugfs_remove_recursive(pfe->dentry);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_DEBUGFS_H_
++#define _PFE_DEBUGFS_H_
++
++int pfe_debugfs_init(struct pfe *pfe);
++void pfe_debugfs_exit(struct pfe *pfe);
++
++#endif /* _PFE_DEBUGFS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.c
+@@ -0,0 +1,2550 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++/* @pfe_eth.c.
++ *  Ethernet driver for to handle exception path for PFE.
++ *  - uses HIF functions to send/receive packets.
++ *  - uses ctrl function to start/stop interfaces.
++ *  - uses direct register accesses to control phy operation.
++ */
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/timer.h>
++#include <linux/hrtimer.h>
++#include <linux/platform_device.h>
++
++#include <net/ip.h>
++#include <net/sock.h>
++
++#include <linux/of.h>
++#include <linux/of_mdio.h>
++
++#include <linux/io.h>
++#include <asm/irq.h>
++#include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/i2c.h>
++#include <linux/sys_soc.h>
++
++#if defined(CONFIG_NF_CONNTRACK_MARK)
++#include <net/netfilter/nf_conntrack.h>
++#endif
++
++#include "pfe_mod.h"
++#include "pfe_eth.h"
++#include "pfe_cdev.h"
++
++#define LS1012A_REV_1_0		0x87040010
++
++bool pfe_use_old_dts_phy;
++bool pfe_errata_a010897;
++
++static void *cbus_emac_base[3];
++static void *cbus_gpi_base[3];
++
++/* Forward Declaration */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv);
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv);
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
++				from_tx, int n_desc);
++
++/* MDIO registers */
++#define MDIO_SGMII_CR			0x00
++#define MDIO_SGMII_SR			0x01
++#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
++#define MDIO_SGMII_LINK_TMR_L		0x12
++#define MDIO_SGMII_LINK_TMR_H		0x13
++#define MDIO_SGMII_IF_MODE		0x14
++
++/* SGMII Control defines */
++#define SGMII_CR_RST			0x8000
++#define SGMII_CR_AN_EN			0x1000
++#define SGMII_CR_RESTART_AN		0x0200
++#define SGMII_CR_FD			0x0100
++#define SGMII_CR_SPEED_SEL1_1G		0x0040
++#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
++					 SGMII_CR_SPEED_SEL1_1G)
++
++/* SGMII IF Mode */
++#define SGMII_DUPLEX_HALF		0x10
++#define SGMII_SPEED_10MBPS		0x00
++#define SGMII_SPEED_100MBPS		0x04
++#define SGMII_SPEED_1GBPS		0x08
++#define SGMII_USE_SGMII_AN		0x02
++#define SGMII_EN			0x01
++
++/* SGMII Device Ability for SGMII */
++#define SGMII_DEV_ABIL_ACK		0x4000
++#define SGMII_DEV_ABIL_EEE_CLK_STP_EN	0x0100
++#define SGMII_DEV_ABIL_SGMII		0x0001
++
++unsigned int gemac_regs[] = {
++	0x0004, /* Interrupt event */
++	0x0008, /* Interrupt mask */
++	0x0024, /* Ethernet control */
++	0x0064, /* MIB Control/Status */
++	0x0084, /* Receive control/status */
++	0x00C4, /* Transmit control */
++	0x00E4, /* Physical address low */
++	0x00E8, /* Physical address high */
++	0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/
++	0x0190, /* Receive FIFO Section Full Threshold */
++	0x01A0, /* Transmit FIFO Section Empty Threshold */
++	0x01B0, /* Frame Truncation Length */
++};
++
++const struct soc_device_attribute ls1012a_rev1_soc_attr[] = {
++	{ .family = "QorIQ LS1012A",
++	  .soc_id = "svr:0x87040010",
++	  .revision = "1.0",
++	  .data = NULL },
++	{ },
++};
++
++/********************************************************************/
++/*                   SYSFS INTERFACE				    */
++/********************************************************************/
++
++#ifdef PFE_ETH_NAPI_STATS
++/*
++ * pfe_eth_show_napi_stats
++ */
++static ssize_t pfe_eth_show_napi_stats(struct device *dev,
++				       struct device_attribute *attr,
++				       char *buf)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	ssize_t len = 0;
++
++	len += sprintf(buf + len, "sched:  %u\n",
++			priv->napi_counters[NAPI_SCHED_COUNT]);
++	len += sprintf(buf + len, "poll:   %u\n",
++			priv->napi_counters[NAPI_POLL_COUNT]);
++	len += sprintf(buf + len, "packet: %u\n",
++			priv->napi_counters[NAPI_PACKET_COUNT]);
++	len += sprintf(buf + len, "budget: %u\n",
++			priv->napi_counters[NAPI_FULL_BUDGET_COUNT]);
++	len += sprintf(buf + len, "desc:   %u\n",
++			priv->napi_counters[NAPI_DESC_COUNT]);
++
++	return len;
++}
++
++/*
++ * pfe_eth_set_napi_stats
++ */
++static ssize_t pfe_eth_set_napi_stats(struct device *dev,
++				      struct device_attribute *attr,
++				      const char *buf, size_t count)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++
++	memset(priv->napi_counters, 0, sizeof(priv->napi_counters));
++
++	return count;
++}
++#endif
++#ifdef PFE_ETH_TX_STATS
++/* pfe_eth_show_tx_stats
++ *
++ */
++static ssize_t pfe_eth_show_tx_stats(struct device *dev,
++				     struct device_attribute *attr,
++				     char *buf)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	ssize_t len = 0;
++	int i;
++
++	len += sprintf(buf + len, "TX queues stats:\n");
++
++	for (i = 0; i < emac_txq_cnt; i++) {
++		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++									i);
++
++		len += sprintf(buf + len, "\n");
++		__netif_tx_lock_bh(tx_queue);
++
++		hif_tx_lock(&pfe->hif);
++		len += sprintf(buf + len,
++				"Queue %2d :  credits               = %10d\n"
++				, i, hif_lib_tx_credit_avail(pfe, priv->id, i));
++		len += sprintf(buf + len,
++				 "            tx packets            = %10d\n"
++				,  pfe->tmu_credit.tx_packets[priv->id][i]);
++		hif_tx_unlock(&pfe->hif);
++
++		/* Don't output additionnal stats if queue never used */
++		if (!pfe->tmu_credit.tx_packets[priv->id][i])
++			goto skip;
++
++		len += sprintf(buf + len,
++				 "            clean_fail            = %10d\n"
++				, priv->clean_fail[i]);
++		len += sprintf(buf + len,
++				 "            stop_queue            = %10d\n"
++				, priv->stop_queue_total[i]);
++		len += sprintf(buf + len,
++				 "            stop_queue_hif        = %10d\n"
++				, priv->stop_queue_hif[i]);
++		len += sprintf(buf + len,
++				"            stop_queue_hif_client = %10d\n"
++				, priv->stop_queue_hif_client[i]);
++		len += sprintf(buf + len,
++				 "            stop_queue_credit     = %10d\n"
++				, priv->stop_queue_credit[i]);
++skip:
++		__netif_tx_unlock_bh(tx_queue);
++	}
++	return len;
++}
++
++/* pfe_eth_set_tx_stats
++ *
++ */
++static ssize_t pfe_eth_set_tx_stats(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t count)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	int i;
++
++	for (i = 0; i < emac_txq_cnt; i++) {
++		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++									i);
++
++		__netif_tx_lock_bh(tx_queue);
++		priv->clean_fail[i] = 0;
++		priv->stop_queue_total[i] = 0;
++		priv->stop_queue_hif[i] = 0;
++		priv->stop_queue_hif_client[i] = 0;
++		priv->stop_queue_credit[i] = 0;
++		__netif_tx_unlock_bh(tx_queue);
++	}
++
++	return count;
++}
++#endif
++/* pfe_eth_show_txavail
++ *
++ */
++static ssize_t pfe_eth_show_txavail(struct device *dev,
++				    struct device_attribute *attr,
++				    char *buf)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	ssize_t len = 0;
++	int i;
++
++	for (i = 0; i < emac_txq_cnt; i++) {
++		struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++									i);
++
++		__netif_tx_lock_bh(tx_queue);
++
++		len += sprintf(buf + len, "%d",
++				hif_lib_tx_avail(&priv->client, i));
++
++		__netif_tx_unlock_bh(tx_queue);
++
++		if (i == (emac_txq_cnt - 1))
++			len += sprintf(buf + len, "\n");
++		else
++			len += sprintf(buf + len, " ");
++	}
++
++	return len;
++}
++
++/* pfe_eth_show_default_priority
++ *
++ */
++static ssize_t pfe_eth_show_default_priority(struct device *dev,
++					     struct device_attribute *attr,
++						char *buf)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	unsigned long flags;
++	int rc;
++
++	spin_lock_irqsave(&priv->lock, flags);
++	rc = sprintf(buf, "%d\n", priv->default_priority);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return rc;
++}
++
++/* pfe_eth_set_default_priority
++ *
++ */
++
++static ssize_t pfe_eth_set_default_priority(struct device *dev,
++					    struct device_attribute *attr,
++					    const char *buf, size_t count)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->lock, flags);
++	priv->default_priority = kstrtoul(buf, 0, 0);
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	return count;
++}
++
++static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL);
++static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority,
++			pfe_eth_set_default_priority);
++
++#ifdef PFE_ETH_NAPI_STATS
++static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats,
++			pfe_eth_set_napi_stats);
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats,
++			pfe_eth_set_tx_stats);
++#endif
++
++/*
++ * pfe_eth_sysfs_init
++ *
++ */
++static int pfe_eth_sysfs_init(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int err;
++
++	/* Initialize the default values */
++
++	/*
++	 * By default, packets without conntrack will use this default low
++	 * priority queue
++	 */
++	priv->default_priority = 0;
++
++	/* Create our sysfs files */
++	err = device_create_file(&ndev->dev, &dev_attr_default_priority);
++	if (err) {
++		netdev_err(ndev,
++			   "failed to create default_priority sysfs files\n");
++		goto err_priority;
++	}
++
++	err = device_create_file(&ndev->dev, &dev_attr_txavail);
++	if (err) {
++		netdev_err(ndev,
++			   "failed to create default_priority sysfs files\n");
++		goto err_txavail;
++	}
++
++#ifdef PFE_ETH_NAPI_STATS
++	err = device_create_file(&ndev->dev, &dev_attr_napi_stats);
++	if (err) {
++		netdev_err(ndev, "failed to create napi stats sysfs files\n");
++		goto err_napi;
++	}
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++	err = device_create_file(&ndev->dev, &dev_attr_tx_stats);
++	if (err) {
++		netdev_err(ndev, "failed to create tx stats sysfs files\n");
++		goto err_tx;
++	}
++#endif
++
++	return 0;
++
++#ifdef PFE_ETH_TX_STATS
++err_tx:
++#endif
++#ifdef PFE_ETH_NAPI_STATS
++	device_remove_file(&ndev->dev, &dev_attr_napi_stats);
++
++err_napi:
++#endif
++	device_remove_file(&ndev->dev, &dev_attr_txavail);
++
++err_txavail:
++	device_remove_file(&ndev->dev, &dev_attr_default_priority);
++
++err_priority:
++	return -1;
++}
++
++/* pfe_eth_sysfs_exit
++ *
++ */
++void pfe_eth_sysfs_exit(struct net_device *ndev)
++{
++#ifdef PFE_ETH_TX_STATS
++	device_remove_file(&ndev->dev, &dev_attr_tx_stats);
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++	device_remove_file(&ndev->dev, &dev_attr_napi_stats);
++#endif
++	device_remove_file(&ndev->dev, &dev_attr_txavail);
++	device_remove_file(&ndev->dev, &dev_attr_default_priority);
++}
++
++/*************************************************************************/
++/*		ETHTOOL INTERCAE					 */
++/*************************************************************************/
++
++/*MTIP GEMAC */
++static const struct fec_stat {
++	char name[ETH_GSTRING_LEN];
++	u16 offset;
++} fec_stats[] = {
++	/* RMON TX */
++	{ "tx_dropped", RMON_T_DROP },
++	{ "tx_packets", RMON_T_PACKETS },
++	{ "tx_broadcast", RMON_T_BC_PKT },
++	{ "tx_multicast", RMON_T_MC_PKT },
++	{ "tx_crc_errors", RMON_T_CRC_ALIGN },
++	{ "tx_undersize", RMON_T_UNDERSIZE },
++	{ "tx_oversize", RMON_T_OVERSIZE },
++	{ "tx_fragment", RMON_T_FRAG },
++	{ "tx_jabber", RMON_T_JAB },
++	{ "tx_collision", RMON_T_COL },
++	{ "tx_64byte", RMON_T_P64 },
++	{ "tx_65to127byte", RMON_T_P65TO127 },
++	{ "tx_128to255byte", RMON_T_P128TO255 },
++	{ "tx_256to511byte", RMON_T_P256TO511 },
++	{ "tx_512to1023byte", RMON_T_P512TO1023 },
++	{ "tx_1024to2047byte", RMON_T_P1024TO2047 },
++	{ "tx_GTE2048byte", RMON_T_P_GTE2048 },
++	{ "tx_octets", RMON_T_OCTETS },
++
++	/* IEEE TX */
++	{ "IEEE_tx_drop", IEEE_T_DROP },
++	{ "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++	{ "IEEE_tx_1col", IEEE_T_1COL },
++	{ "IEEE_tx_mcol", IEEE_T_MCOL },
++	{ "IEEE_tx_def", IEEE_T_DEF },
++	{ "IEEE_tx_lcol", IEEE_T_LCOL },
++	{ "IEEE_tx_excol", IEEE_T_EXCOL },
++	{ "IEEE_tx_macerr", IEEE_T_MACERR },
++	{ "IEEE_tx_cserr", IEEE_T_CSERR },
++	{ "IEEE_tx_sqe", IEEE_T_SQE },
++	{ "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++	{ "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++	/* RMON RX */
++	{ "rx_packets", RMON_R_PACKETS },
++	{ "rx_broadcast", RMON_R_BC_PKT },
++	{ "rx_multicast", RMON_R_MC_PKT },
++	{ "rx_crc_errors", RMON_R_CRC_ALIGN },
++	{ "rx_undersize", RMON_R_UNDERSIZE },
++	{ "rx_oversize", RMON_R_OVERSIZE },
++	{ "rx_fragment", RMON_R_FRAG },
++	{ "rx_jabber", RMON_R_JAB },
++	{ "rx_64byte", RMON_R_P64 },
++	{ "rx_65to127byte", RMON_R_P65TO127 },
++	{ "rx_128to255byte", RMON_R_P128TO255 },
++	{ "rx_256to511byte", RMON_R_P256TO511 },
++	{ "rx_512to1023byte", RMON_R_P512TO1023 },
++	{ "rx_1024to2047byte", RMON_R_P1024TO2047 },
++	{ "rx_GTE2048byte", RMON_R_P_GTE2048 },
++	{ "rx_octets", RMON_R_OCTETS },
++
++	/* IEEE RX */
++	{ "IEEE_rx_drop", IEEE_R_DROP },
++	{ "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++	{ "IEEE_rx_crc", IEEE_R_CRC },
++	{ "IEEE_rx_align", IEEE_R_ALIGN },
++	{ "IEEE_rx_macerr", IEEE_R_MACERR },
++	{ "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++	{ "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats
++				*stats, u64 *data)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int i;
++	u64 pfe_crc_validated = 0;
++	int id;
++
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++		pfe_crc_validated += be32_to_cpu(pe_dmem_read(id,
++			CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4));
++	}
++
++	for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
++		data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset);
++
++		if (fec_stats[i].offset == IEEE_R_DROP)
++			data[i] -= pfe_crc_validated;
++	}
++}
++
++static void pfe_eth_gstrings(struct net_device *netdev,
++			     u32 stringset, u8 *data)
++{
++	int i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++			memcpy(data + i * ETH_GSTRING_LEN,
++			       fec_stats[i].name, ETH_GSTRING_LEN);
++		break;
++	}
++}
++
++static int pfe_eth_stats_count(struct net_device *ndev, int sset)
++{
++	switch (sset) {
++	case ETH_SS_STATS:
++		return ARRAY_SIZE(fec_stats);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++/*
++ * pfe_eth_gemac_reglen - Return the length of the register structure.
++ *
++ */
++static int pfe_eth_gemac_reglen(struct net_device *ndev)
++{
++	pr_info("%s()\n", __func__);
++	return (sizeof(gemac_regs) / sizeof(u32));
++}
++
++/*
++ * pfe_eth_gemac_get_regs - Return the gemac register structure.
++ *
++ */
++static void  pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs
++					*regs, void *regbuf)
++{
++	int i;
++
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	u32 *buf = (u32 *)regbuf;
++
++	pr_info("%s()\n", __func__);
++	for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++)
++		buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]);
++}
++
++/*
++ * pfe_eth_set_wol - Set the magic packet option, in WoL register.
++ *
++ */
++static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	if (wol->wolopts & ~WAKE_MAGIC)
++		return -EOPNOTSUPP;
++
++	/* for MTIP we store wol->wolopts */
++	priv->wol = wol->wolopts;
++
++	device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
++
++	return 0;
++}
++
++/*
++ *
++ * pfe_eth_get_wol - Get the WoL options.
++ *
++ */
++static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo
++				*wol)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = 0;
++
++	if (priv->wol & WAKE_MAGIC)
++		wol->wolopts = WAKE_MAGIC;
++
++	memset(&wol->sopass, 0, sizeof(wol->sopass));
++}
++
++/*
++ * pfe_eth_get_drvinfo -  Fills in the drvinfo structure with some basic info
++ *
++ */
++static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo
++				*drvinfo)
++{
++	strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
++	strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
++	strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
++	strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info));
++}
++
++/*
++ * pfe_eth_set_settings - Used to send commands to PHY.
++ *
++ */
++static int pfe_eth_set_settings(struct net_device *ndev,
++				const struct ethtool_link_ksettings *cmd)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct phy_device *phydev = priv->phydev;
++
++	if (!phydev)
++		return -ENODEV;
++
++	return phy_ethtool_ksettings_set(phydev, cmd);
++}
++
++/*
++ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd
++ * structure.
++ *
++ */
++static int pfe_eth_get_settings(struct net_device *ndev,
++				struct ethtool_link_ksettings *cmd)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct phy_device *phydev = priv->phydev;
++
++	if (!phydev)
++		return -ENODEV;
++
++	phy_ethtool_ksettings_get(phydev, cmd);
++
++	return 0;
++}
++
++/*
++ * pfe_eth_get_msglevel - Gets the debug message mask.
++ *
++ */
++static uint32_t pfe_eth_get_msglevel(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	return priv->msg_enable;
++}
++
++/*
++ * pfe_eth_set_msglevel - Sets the debug message mask.
++ *
++ */
++static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	priv->msg_enable = data;
++}
++
++#define HIF_RX_COAL_MAX_CLKS		(~(1 << 31))
++#define HIF_RX_COAL_CLKS_PER_USEC	(pfe->ctrl.sys_clk / 1000)
++#define HIF_RX_COAL_MAX_USECS		(HIF_RX_COAL_MAX_CLKS	/ \
++						HIF_RX_COAL_CLKS_PER_USEC)
++
++/*
++ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer.
++ *
++ */
++static int pfe_eth_set_coalesce(struct net_device *ndev,
++				struct ethtool_coalesce *ec,
++				struct kernel_ethtool_coalesce *kernel_coal,
++				struct netlink_ext_ack *extack)
++{
++	if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS)
++		return -EINVAL;
++
++	if (!ec->rx_coalesce_usecs) {
++		writel(0, HIF_INT_COAL);
++		return 0;
++	}
++
++	writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) |
++			HIF_INT_COAL_ENABLE, HIF_INT_COAL);
++
++	return 0;
++}
++
++/*
++ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value.
++ *
++ */
++static int pfe_eth_get_coalesce(struct net_device *ndev,
++				struct ethtool_coalesce *ec,
++				struct kernel_ethtool_coalesce *kernel_coal,
++				struct netlink_ext_ack *extack)
++{
++	int reg_val = readl(HIF_INT_COAL);
++
++	if (reg_val & HIF_INT_COAL_ENABLE)
++		ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) /
++						HIF_RX_COAL_CLKS_PER_USEC;
++	else
++		ec->rx_coalesce_usecs = 0;
++
++	return 0;
++}
++
++/*
++ * pfe_eth_set_pauseparam - Sets pause parameters
++ *
++ */
++static int pfe_eth_set_pauseparam(struct net_device *ndev,
++				  struct ethtool_pauseparam *epause)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	if (epause->tx_pause != epause->rx_pause) {
++		netdev_info(ndev,
++			    "hardware only support enable/disable both tx and rx\n");
++		return -EINVAL;
++	}
++
++	priv->pause_flag = 0;
++	priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0;
++	priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0;
++
++	if (epause->rx_pause || epause->autoneg) {
++		gemac_enable_pause_rx(priv->EMAC_baseaddr);
++		writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) |
++					EGPI_PAUSE_ENABLE),
++				priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
++		if (priv->phydev) {
++			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++					 priv->phydev->supported);
++			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++					 priv->phydev->supported);
++			linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++					 priv->phydev->advertising);
++			linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++					 priv->phydev->advertising);
++		}
++	} else {
++		gemac_disable_pause_rx(priv->EMAC_baseaddr);
++		writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) &
++					~EGPI_PAUSE_ENABLE),
++				priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
++		if (priv->phydev) {
++			linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++					   priv->phydev->supported);
++			linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++					   priv->phydev->supported);
++			linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++					   priv->phydev->advertising);
++			linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++					   priv->phydev->advertising);
++		}
++	}
++
++	return 0;
++}
++
++/*
++ * pfe_eth_get_pauseparam - Gets pause parameters
++ *
++ */
++static void pfe_eth_get_pauseparam(struct net_device *ndev,
++				   struct ethtool_pauseparam *epause)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0;
++	epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0;
++	epause->rx_pause = epause->tx_pause;
++}
++
++/*
++ * pfe_eth_get_hash
++ */
++#define PFE_HASH_BITS	6		/* #bits in hash */
++#define CRC32_POLY	0xEDB88320
++
++static int pfe_eth_get_hash(u8 *addr)
++{
++	unsigned int i, bit, data, crc, hash;
++
++	/* calculate crc32 value of mac address */
++	crc = 0xffffffff;
++
++	for (i = 0; i < 6; i++) {
++		data = addr[i];
++		for (bit = 0; bit < 8; bit++, data >>= 1) {
++			crc = (crc >> 1) ^
++				(((crc ^ data) & 1) ? CRC32_POLY : 0);
++		}
++	}
++
++	/*
++	 * only upper 6 bits (PFE_HASH_BITS) are used
++	 * which point to specific bit in the hash registers
++	 */
++	hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f;
++
++	return hash;
++}
++
++const struct ethtool_ops pfe_ethtool_ops = {
++	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
++	.get_drvinfo = pfe_eth_get_drvinfo,
++	.get_regs_len = pfe_eth_gemac_reglen,
++	.get_regs = pfe_eth_gemac_get_regs,
++	.get_link = ethtool_op_get_link,
++	.get_wol  = pfe_eth_get_wol,
++	.set_wol  = pfe_eth_set_wol,
++	.set_pauseparam = pfe_eth_set_pauseparam,
++	.get_pauseparam = pfe_eth_get_pauseparam,
++	.get_strings = pfe_eth_gstrings,
++	.get_sset_count = pfe_eth_stats_count,
++	.get_ethtool_stats = pfe_eth_fill_stats,
++	.get_msglevel = pfe_eth_get_msglevel,
++	.set_msglevel = pfe_eth_set_msglevel,
++	.set_coalesce = pfe_eth_set_coalesce,
++	.get_coalesce = pfe_eth_get_coalesce,
++	.get_link_ksettings = pfe_eth_get_settings,
++	.set_link_ksettings = pfe_eth_set_settings,
++};
++
++/* pfe_eth_mdio_reset
++ */
++int pfe_eth_mdio_reset(struct mii_bus *bus)
++{
++	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++	u32 phy_speed;
++
++
++	mutex_lock(&bus->mdio_lock);
++
++	/*
++	 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
++	 *
++	 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
++	 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.
++	 */
++	phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000)
++		     << EMAC_MII_SPEED_SHIFT);
++	phy_speed |= EMAC_HOLDTIME(0x5);
++	__raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG);
++
++	mutex_unlock(&bus->mdio_lock);
++
++	return 0;
++}
++
++/* pfe_eth_mdio_timeout
++ *
++ */
++static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout)
++{
++	while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) &
++			EMAC_IEVENT_MII)) {
++		if (timeout-- <= 0)
++			return -1;
++		usleep_range(10, 20);
++	}
++	__raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG);
++	return 0;
++}
++
++static int pfe_eth_mdio_mux(u8 muxval)
++{
++	struct i2c_adapter *a;
++	struct i2c_msg msg;
++	unsigned char buf[2];
++	int ret;
++
++	a = i2c_get_adapter(0);
++	if (!a)
++		return -ENODEV;
++
++	/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
++	buf[0] = 0x54; /* reg number */
++	buf[1] = (muxval << 6) | 0x3; /* data */
++	msg.addr = 0x66;
++	msg.buf = buf;
++	msg.len = 2;
++	msg.flags = 0;
++	ret = i2c_transfer(a, &msg, 1);
++	i2c_put_adapter(a);
++	if (ret != 1)
++		return -ENODEV;
++	return 0;
++}
++
++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
++			      u16 value)
++{
++	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++
++	/*To access external PHYs on QDS board mux needs to be configured*/
++	if ((mii_id) && (pfe->mdio_muxval[mii_id]))
++		pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
++
++	/* start a write op */
++	__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
++		     EMAC_MII_DATA_PA(mii_id) |
++		     EMAC_MII_DATA_RA(regnum) |
++		     EMAC_MII_DATA_TA | EMAC_MII_DATA(value),
++		     priv->mdio_base + EMAC_MII_DATA_REG);
++
++	if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
++		dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__);
++		return -1;
++	}
++	return 0;
++}
++
++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
++{
++	struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++	u16 value = 0;
++
++	/*To access external PHYs on QDS board mux needs to be configured*/
++	if ((mii_id) && (pfe->mdio_muxval[mii_id]))
++		pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
++
++	/* start a read op */
++	__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
++		     EMAC_MII_DATA_PA(mii_id) |
++		     EMAC_MII_DATA_RA(regnum) |
++		     EMAC_MII_DATA_TA, priv->mdio_base +
++		     EMAC_MII_DATA_REG);
++
++	if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
++		dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__);
++		return -1;
++	}
++
++	value = EMAC_MII_DATA(__raw_readl(priv->mdio_base +
++						EMAC_MII_DATA_REG));
++	return value;
++}
++
++static int pfe_eth_mdio_init(struct pfe *pfe,
++			     struct ls1012a_pfe_platform_data *pfe_info,
++			     int ii)
++{
++	struct pfe_mdio_priv_s *priv = NULL;
++	struct ls1012a_mdio_platform_data *mdio_info;
++	struct mii_bus *bus;
++	struct device_node *mdio_node;
++	int rc = 0;
++
++	mdio_info = (struct ls1012a_mdio_platform_data *)
++					pfe_info->ls1012a_mdio_pdata;
++	mdio_info->id = ii;
++
++	bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s));
++	if (!bus) {
++		pr_err("mdiobus_alloc() failed\n");
++		rc = -ENOMEM;
++		goto err_mdioalloc;
++	}
++
++	bus->name = "ls1012a MDIO Bus";
++	snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id);
++
++	bus->read = &pfe_eth_mdio_read;
++	bus->write = &pfe_eth_mdio_write;
++	bus->reset = &pfe_eth_mdio_reset;
++	bus->parent = pfe->dev;
++	bus->phy_mask = mdio_info->phy_mask;
++	bus->irq[0] = mdio_info->irq[0];
++	priv = bus->priv;
++	priv->mdio_base = cbus_emac_base[ii];
++
++	priv->mdc_div = mdio_info->mdc_div;
++	if (!priv->mdc_div)
++		priv->mdc_div = 64;
++
++	dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n",
++		 __func__, priv->mdc_div, bus->phy_mask);
++	mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio");
++	if ((mdio_info->id == 0) && mdio_node) {
++		rc = of_mdiobus_register(bus, mdio_node);
++		of_node_put(mdio_node);
++	} else {
++		rc = mdiobus_register(bus);
++	}
++
++	if (rc) {
++		dev_err(bus->parent, "mdiobus_register(%s) failed\n",
++			bus->name);
++		goto err_mdioregister;
++	}
++
++	priv->mii_bus = bus;
++	pfe->mdio.mdio_priv[ii] = priv;
++
++	pfe_eth_mdio_reset(bus);
++
++	return 0;
++
++err_mdioregister:
++	mdiobus_free(bus);
++err_mdioalloc:
++	return rc;
++}
++
++/* pfe_eth_mdio_exit
++ */
++static void pfe_eth_mdio_exit(struct pfe *pfe,
++			      int ii)
++{
++	struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii];
++	struct mii_bus *bus = mdio_priv->mii_bus;
++
++	if (!bus)
++		return;
++	mdiobus_unregister(bus);
++	mdiobus_free(bus);
++}
++
++/* pfe_get_phydev_speed
++ */
++static int pfe_get_phydev_speed(struct phy_device *phydev)
++{
++	switch (phydev->speed) {
++	case 10:
++			return SPEED_10M;
++	case 100:
++			return SPEED_100M;
++	case 1000:
++	default:
++			return SPEED_1000M;
++	}
++}
++
++/* pfe_set_rgmii_speed
++ */
++#define RGMIIPCR	0x434
++/* RGMIIPCR bit definitions*/
++#define SCFG_RGMIIPCR_EN_AUTO           (0x00000008)
++#define SCFG_RGMIIPCR_SETSP_1000M       (0x00000004)
++#define SCFG_RGMIIPCR_SETSP_100M        (0x00000000)
++#define SCFG_RGMIIPCR_SETSP_10M         (0x00000002)
++#define SCFG_RGMIIPCR_SETFD             (0x00000001)
++
++#define MDIOSELCR	0x484
++#define MDIOSEL_SERDES	0x0
++#define MDIOSEL_EXTPHY  0x80000000
++
++static void pfe_set_rgmii_speed(struct phy_device *phydev)
++{
++	u32 rgmii_pcr;
++
++	regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr);
++	rgmii_pcr  &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
++
++	switch (phydev->speed) {
++	case 10:
++			rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
++			break;
++	case 1000:
++			rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
++			break;
++	case 100:
++	default:
++			/* Default is 100M */
++			break;
++	}
++	regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr);
++}
++
++/* pfe_get_phydev_duplex
++ */
++static int pfe_get_phydev_duplex(struct phy_device *phydev)
++{
++	/*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */
++	return DUPLEX_FULL;
++}
++
++/* pfe_eth_adjust_link
++ */
++static void pfe_eth_adjust_link(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	unsigned long flags;
++	struct phy_device *phydev = priv->phydev;
++	int new_state = 0;
++
++	netif_info(priv, drv, ndev, "%s\n", __func__);
++
++	spin_lock_irqsave(&priv->lock, flags);
++
++	if (phydev->link) {
++		/*
++		 * Now we make sure that we can be in full duplex mode.
++		 * If not, we operate in half-duplex mode.
++		 */
++		if (phydev->duplex != priv->oldduplex) {
++			new_state = 1;
++			gemac_set_duplex(priv->EMAC_baseaddr,
++					 pfe_get_phydev_duplex(phydev));
++			priv->oldduplex = phydev->duplex;
++		}
++
++		if (phydev->speed != priv->oldspeed) {
++			new_state = 1;
++			gemac_set_speed(priv->EMAC_baseaddr,
++					pfe_get_phydev_speed(phydev));
++			if (priv->einfo->mii_config ==
++					PHY_INTERFACE_MODE_RGMII_ID)
++				pfe_set_rgmii_speed(phydev);
++			priv->oldspeed = phydev->speed;
++		}
++
++		if (!priv->oldlink) {
++			new_state = 1;
++			priv->oldlink = 1;
++		}
++
++	} else if (priv->oldlink) {
++		new_state = 1;
++		priv->oldlink = 0;
++		priv->oldspeed = 0;
++		priv->oldduplex = -1;
++	}
++
++	if (new_state && netif_msg_link(priv))
++		phy_print_status(phydev);
++
++	spin_unlock_irqrestore(&priv->lock, flags);
++
++	/* Now, dump the details to the cdev.
++	 * XXX: Locking would be required? (uniprocess arch)
++	 *      Or, maybe move it in spinlock above
++	 */
++	if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) {
++		pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n",
++			 link_states[priv->einfo->gem_id].state,
++			 phydev->link,
++			 priv->einfo->gem_id);
++		link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id;
++		link_states[priv->einfo->gem_id].state = phydev->link;
++	}
++}
++
++/* pfe_phy_exit
++ */
++static void pfe_phy_exit(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	netif_info(priv, drv, ndev, "%s\n", __func__);
++
++	phy_disconnect(priv->phydev);
++	priv->phydev = NULL;
++}
++
++/* pfe_eth_stop
++ */
++static void pfe_eth_stop(struct net_device *ndev, int wake)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	netif_info(priv, drv, ndev, "%s\n", __func__);
++
++	if (wake) {
++		gemac_tx_disable(priv->EMAC_baseaddr);
++	} else {
++		gemac_disable(priv->EMAC_baseaddr);
++		gpi_disable(priv->GPI_baseaddr);
++
++		if (priv->phydev)
++			phy_stop(priv->phydev);
++	}
++}
++
++/* pfe_eth_start
++ */
++static int pfe_eth_start(struct pfe_eth_priv_s *priv)
++{
++	netif_info(priv, drv, priv->ndev, "%s\n", __func__);
++
++	if (priv->phydev)
++		phy_start(priv->phydev);
++
++	gpi_enable(priv->GPI_baseaddr);
++	gemac_enable(priv->EMAC_baseaddr);
++
++	return 0;
++}
++
++/*
++ * Configure on chip serdes through mdio
++ */
++static void ls1012a_configure_serdes(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev);
++	struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id];
++	int sgmii_2500 = 0;
++	struct mii_bus *bus = mdio_priv->mii_bus;
++	u16 value = 0;
++
++	if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII)
++		sgmii_2500 = 1;
++
++	netif_info(eth_priv, drv, ndev, "%s\n", __func__);
++	/* PCS configuration done with corresponding GEMAC */
++
++	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
++	pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
++
++	pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
++
++	if (sgmii_2500) {
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
++							       | SGMII_EN);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
++				   SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
++		/* Autonegotiation need to be disabled for 2.5G SGMII mode*/
++		value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
++	} else {
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
++				   SGMII_SPEED_1GBPS
++				   | SGMII_USE_SGMII_AN
++				   | SGMII_EN);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
++				   SGMII_DEV_ABIL_EEE_CLK_STP_EN
++				   | 0xa0
++				   | SGMII_DEV_ABIL_SGMII);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
++		value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
++		pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
++	}
++}
++
++/*
++ * pfe_phy_init
++ *
++ */
++static int pfe_phy_init(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct phy_device *phydev;
++	char phy_id[MII_BUS_ID_SIZE + 3];
++	char bus_id[MII_BUS_ID_SIZE];
++	phy_interface_t interface;
++
++	priv->oldlink = 0;
++	priv->oldspeed = 0;
++	priv->oldduplex = -1;
++
++	snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0);
++	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
++		 priv->einfo->phy_id);
++	netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id);
++	interface = priv->einfo->mii_config;
++	if ((interface == PHY_INTERFACE_MODE_SGMII) ||
++	    (interface == PHY_INTERFACE_MODE_2500SGMII)) {
++		/*Configure SGMII PCS */
++		if (pfe->scfg) {
++			/* Config MDIO from serdes */
++			regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
++		}
++		ls1012a_configure_serdes(ndev);
++	}
++
++	if (pfe->scfg) {
++		/*Config MDIO from PAD */
++		regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
++	}
++
++	priv->oldlink = 0;
++	priv->oldspeed = 0;
++	priv->oldduplex = -1;
++	pr_info("%s interface %x\n", __func__, interface);
++
++	if (priv->phy_node) {
++		phydev = of_phy_connect(ndev, priv->phy_node,
++					pfe_eth_adjust_link, 0,
++					priv->einfo->mii_config);
++		if (!(phydev)) {
++			netdev_err(ndev, "Unable to connect to phy\n");
++			return -ENODEV;
++		}
++
++	} else {
++		phydev = phy_connect(ndev, phy_id,
++				     &pfe_eth_adjust_link, interface);
++		if (IS_ERR(phydev)) {
++			netdev_err(ndev, "Unable to connect to phy\n");
++			return PTR_ERR(phydev);
++		}
++	}
++
++	priv->phydev = phydev;
++	phydev->irq = PHY_POLL;
++
++	return 0;
++}
++
++/* pfe_gemac_init
++ */
++static int pfe_gemac_init(struct pfe_eth_priv_s *priv)
++{
++	struct gemac_cfg cfg;
++
++	netif_info(priv, ifup, priv->ndev, "%s\n", __func__);
++
++	cfg.mode = 0;
++	cfg.speed = SPEED_1000M;
++	cfg.duplex = DUPLEX_FULL;
++
++	gemac_set_config(priv->EMAC_baseaddr, &cfg);
++	gemac_allow_broadcast(priv->EMAC_baseaddr);
++	gemac_enable_1536_rx(priv->EMAC_baseaddr);
++	gemac_enable_stacked_vlan(priv->EMAC_baseaddr);
++	gemac_enable_pause_rx(priv->EMAC_baseaddr);
++	gemac_set_bus_width(priv->EMAC_baseaddr, 64);
++
++	/*GEM will perform checksum verifications*/
++	if (priv->ndev->features & NETIF_F_RXCSUM)
++		gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++	else
++		gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++
++	return 0;
++}
++
++/* pfe_eth_event_handler
++ */
++static int pfe_eth_event_handler(void *data, int event, int qno)
++{
++	struct pfe_eth_priv_s *priv = data;
++
++	switch (event) {
++	case EVENT_RX_PKT_IND:
++
++		if (qno == 0) {
++			if (napi_schedule_prep(&priv->high_napi)) {
++				netif_info(priv, intr, priv->ndev,
++					   "%s: schedule high prio poll\n"
++					   , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++				priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++
++				__napi_schedule(&priv->high_napi);
++			}
++		} else if (qno == 1) {
++			if (napi_schedule_prep(&priv->low_napi)) {
++				netif_info(priv, intr, priv->ndev,
++					   "%s: schedule low prio poll\n"
++					   , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++				priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++				__napi_schedule(&priv->low_napi);
++			}
++		} else if (qno == 2) {
++			if (napi_schedule_prep(&priv->lro_napi)) {
++				netif_info(priv, intr, priv->ndev,
++					   "%s: schedule lro prio poll\n"
++					   , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++				priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++				__napi_schedule(&priv->lro_napi);
++			}
++		}
++
++		break;
++
++	case EVENT_TXDONE_IND:
++		pfe_eth_flush_tx(priv);
++		hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0);
++		break;
++	case EVENT_HIGH_RX_WM:
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	ndev->mtu = new_mtu;
++	new_mtu += ETH_HLEN + ETH_FCS_LEN;
++	gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu);
++
++	return 0;
++}
++
++/* pfe_eth_open
++ */
++static int pfe_eth_open(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct hif_client_s *client;
++	int rc;
++
++	netif_info(priv, ifup, ndev, "%s\n", __func__);
++
++	/* Register client driver with HIF */
++	client = &priv->client;
++	memset(client, 0, sizeof(*client));
++	client->id = PFE_CL_GEM0 + priv->id;
++	client->tx_qn = emac_txq_cnt;
++	client->rx_qn = EMAC_RXQ_CNT;
++	client->priv = priv;
++	client->pfe = priv->pfe;
++	client->event_handler = pfe_eth_event_handler;
++
++	client->tx_qsize = EMAC_TXQ_DEPTH;
++	client->rx_qsize = EMAC_RXQ_DEPTH;
++
++	rc = hif_lib_client_register(client);
++	if (rc) {
++		netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n",
++			   __func__, client->id);
++		goto err0;
++	}
++
++	netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__,
++		   client);
++
++	pfe_gemac_init(priv);
++
++	if (!is_valid_ether_addr(ndev->dev_addr)) {
++		netdev_err(ndev, "%s: invalid MAC address\n", __func__);
++		rc = -EADDRNOTAVAIL;
++		goto err1;
++	}
++
++	gemac_set_laddrN(priv->EMAC_baseaddr,
++			 (struct pfe_mac_addr *)ndev->dev_addr, 1);
++
++	napi_enable(&priv->high_napi);
++	napi_enable(&priv->low_napi);
++	napi_enable(&priv->lro_napi);
++
++	rc = pfe_eth_start(priv);
++
++	netif_tx_wake_all_queues(ndev);
++
++	return rc;
++
++err1:
++	hif_lib_client_unregister(&priv->client);
++
++err0:
++	return rc;
++}
++
++/*
++ *  pfe_eth_shutdown
++ */
++int pfe_eth_shutdown(struct net_device *ndev, int wake)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int i, qstatus, id;
++	unsigned long next_poll = jiffies + 1, end = jiffies +
++				(TX_POLL_TIMEOUT_MS * HZ) / 1000;
++	int tx_pkts, prv_tx_pkts;
++
++	netif_info(priv, ifdown, ndev, "%s\n", __func__);
++
++	for (i = 0; i < emac_txq_cnt; i++)
++		hrtimer_cancel(&priv->fast_tx_timeout[i].timer);
++
++	netif_tx_stop_all_queues(ndev);
++
++	do {
++		tx_pkts = 0;
++		pfe_eth_flush_tx(priv);
++
++		for (i = 0; i < emac_txq_cnt; i++)
++			tx_pkts += hif_lib_tx_pending(&priv->client, i);
++
++		if (tx_pkts) {
++			/*Don't wait forever, break if we cross max timeout */
++			if (time_after(jiffies, end)) {
++				pr_err(
++					"(%s)Tx is not complete after %dmsec\n",
++					ndev->name, TX_POLL_TIMEOUT_MS);
++				break;
++			}
++
++			pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n"
++				, __func__, ndev->name, tx_pkts);
++			if (need_resched())
++				schedule();
++		}
++
++	} while (tx_pkts);
++
++	end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;
++
++	prv_tx_pkts = tmu_pkts_processed(priv->id);
++	/*
++	 * Wait till TMU transmits all pending packets
++	 * poll tmu_qstatus and pkts processed by TMU for every 10ms
++	 * Consider TMU is busy, If we see TMU qeueu pending or any packets
++	 * processed by TMU
++	 */
++	while (1) {
++		if (time_after(jiffies, next_poll)) {
++			tx_pkts = tmu_pkts_processed(priv->id);
++			qstatus = tmu_qstatus(priv->id) & 0x7ffff;
++
++			if (!qstatus && (tx_pkts == prv_tx_pkts))
++				break;
++			/* Don't wait forever, break if we cross max
++			 * timeout(TX_POLL_TIMEOUT_MS)
++			 */
++			if (time_after(jiffies, end)) {
++				pr_err("TMU%d is busy after %dmsec\n",
++				       priv->id, TX_POLL_TIMEOUT_MS);
++				break;
++			}
++			prv_tx_pkts = tx_pkts;
++			next_poll++;
++		}
++		if (need_resched())
++			schedule();
++	}
++	/* Wait for some more time to complete transmitting packet if any */
++	next_poll = jiffies + 1;
++	while (1) {
++		if (time_after(jiffies, next_poll))
++			break;
++		if (need_resched())
++			schedule();
++	}
++
++	pfe_eth_stop(ndev, wake);
++
++	napi_disable(&priv->lro_napi);
++	napi_disable(&priv->low_napi);
++	napi_disable(&priv->high_napi);
++
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++		pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED
++			      + (priv->id * 4), 4);
++	}
++
++	hif_lib_client_unregister(&priv->client);
++
++	return 0;
++}
++
++/* pfe_eth_close
++ *
++ */
++static int pfe_eth_close(struct net_device *ndev)
++{
++	pfe_eth_shutdown(ndev, 0);
++
++	return 0;
++}
++
++/* pfe_eth_suspend
++ *
++ * return value : 1 if netdevice is configured to wakeup system
++ *                0 otherwise
++ */
++int pfe_eth_suspend(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int retval = 0;
++
++	if (priv->wol) {
++		gemac_set_wol(priv->EMAC_baseaddr, priv->wol);
++		retval = 1;
++	}
++	pfe_eth_shutdown(ndev, priv->wol);
++
++	return retval;
++}
++
++/* pfe_eth_resume
++ *
++ */
++int pfe_eth_resume(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	if (priv->wol)
++		gemac_set_wol(priv->EMAC_baseaddr, 0);
++	gemac_tx_enable(priv->EMAC_baseaddr);
++
++	return pfe_eth_open(ndev);
++}
++
++/* pfe_eth_get_queuenum
++ */
++static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff
++					*skb)
++{
++	int queuenum = 0;
++	unsigned long flags;
++
++	/* Get the Fast Path queue number */
++	/*
++	 * Use conntrack mark (if conntrack exists), then packet mark (if any),
++	 * then fallback to default
++	 */
++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
++	if (skb->_nfct) {
++		enum ip_conntrack_info cinfo;
++		struct nf_conn *ct;
++
++		ct = nf_ct_get(skb, &cinfo);
++
++		if (ct) {
++			u32 connmark;
++
++			connmark = ct->mark;
++
++			if ((connmark & 0x80000000) && priv->id != 0)
++				connmark >>= 16;
++
++			queuenum = connmark & EMAC_QUEUENUM_MASK;
++		}
++	} else  {/* continued after #endif ... */
++#endif
++		if (skb->mark) {
++			queuenum = skb->mark & EMAC_QUEUENUM_MASK;
++		} else {
++			spin_lock_irqsave(&priv->lock, flags);
++			queuenum = priv->default_priority & EMAC_QUEUENUM_MASK;
++			spin_unlock_irqrestore(&priv->lock, flags);
++		}
++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
++	}
++#endif
++	return queuenum;
++}
++
++/* pfe_eth_might_stop_tx
++ *
++ */
++static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum,
++				 struct netdev_queue *tx_queue,
++				 unsigned int n_desc,
++				 unsigned int n_segs)
++{
++	ktime_t kt;
++	int tried = 0;
++
++try_again:
++	if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) ||
++	(hif_lib_tx_avail(&priv->client, queuenum) < n_desc) ||
++	(hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) {
++		if (!tried) {
++			__hif_lib_update_credit(&priv->client, queuenum);
++			tried = 1;
++			goto try_again;
++		}
++#ifdef PFE_ETH_TX_STATS
++		if (__hif_tx_avail(&pfe->hif) < n_desc) {
++			priv->stop_queue_hif[queuenum]++;
++		} else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) {
++			priv->stop_queue_hif_client[queuenum]++;
++		} else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) <
++			n_segs) {
++			priv->stop_queue_credit[queuenum]++;
++		}
++		priv->stop_queue_total[queuenum]++;
++#endif
++		netif_tx_stop_queue(tx_queue);
++
++		kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS *
++				NSEC_PER_MSEC);
++		hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt,
++			      HRTIMER_MODE_REL);
++		return -1;
++	} else {
++		return 0;
++	}
++}
++
++#define SA_MAX_OP 2
++/* pfe_hif_send_packet
++ *
++ * At this level if TX fails we drop the packet
++ */
++static void pfe_hif_send_packet(struct sk_buff *skb, struct  pfe_eth_priv_s
++					*priv, int queuenum)
++{
++	struct skb_shared_info *sh = skb_shinfo(skb);
++	unsigned int nr_frags;
++	u32 ctrl = 0;
++
++	netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__);
++
++	if (skb_is_gso(skb)) {
++		priv->stats.tx_dropped++;
++		return;
++	}
++
++	if (skb->ip_summed == CHECKSUM_PARTIAL)
++		ctrl = HIF_CTRL_TX_CHECKSUM;
++
++	nr_frags = sh->nr_frags;
++
++	if (nr_frags) {
++		skb_frag_t *f;
++		int i;
++
++		__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
++				   skb_headlen(skb), ctrl, HIF_FIRST_BUFFER,
++				   skb);
++
++		for (i = 0; i < nr_frags - 1; i++) {
++			f = &sh->frags[i];
++			__hif_lib_xmit_pkt(&priv->client, queuenum,
++					   skb_frag_address(f),
++					   skb_frag_size(f),
++					   0x0, 0x0, skb);
++		}
++
++		f = &sh->frags[i];
++
++		__hif_lib_xmit_pkt(&priv->client, queuenum,
++				   skb_frag_address(f), skb_frag_size(f),
++				   0x0, HIF_LAST_BUFFER | HIF_DATA_VALID,
++				   skb);
++
++		netif_info(priv, tx_queued, priv->ndev,
++			   "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n",
++			   __func__, skb, nr_frags, skb->len);
++	} else {
++		__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
++				   skb->len, ctrl, HIF_FIRST_BUFFER |
++				   HIF_LAST_BUFFER | HIF_DATA_VALID,
++				   skb);
++		netif_info(priv, tx_queued, priv->ndev,
++			   "%s: pkt sent successfully skb:%p len:%d\n",
++			   __func__, skb, skb->len);
++	}
++	hif_tx_dma_start();
++	priv->stats.tx_packets++;
++	priv->stats.tx_bytes += skb->len;
++	hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1);
++}
++
++/* pfe_eth_flush_txQ
++ */
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
++				from_tx, int n_desc)
++{
++	struct sk_buff *skb;
++	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++								tx_q_num);
++	unsigned int flags;
++
++	netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
++
++	if (!from_tx)
++		__netif_tx_lock_bh(tx_queue);
++
++	/* Clean HIF and client queue */
++	while ((skb = hif_lib_tx_get_next_complete(&priv->client,
++						   tx_q_num, &flags,
++						   HIF_TX_DESC_NT))) {
++		if (flags & HIF_DATA_VALID)
++			dev_kfree_skb_any(skb);
++	}
++	if (!from_tx)
++		__netif_tx_unlock_bh(tx_queue);
++}
++
++/* pfe_eth_flush_tx
++ */
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv)
++{
++	int ii;
++
++	netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
++
++	for (ii = 0; ii < emac_txq_cnt; ii++) {
++		pfe_eth_flush_txQ(priv, ii, 0, 0);
++		__hif_lib_update_credit(&priv->client, ii);
++	}
++}
++
++void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int
++				*n_segs)
++{
++	struct skb_shared_info *sh = skb_shinfo(skb);
++
++	/* Scattered data */
++	if (sh->nr_frags) {
++		*n_desc = sh->nr_frags + 1;
++		*n_segs = 1;
++	/* Regular case */
++	} else {
++		*n_desc = 1;
++		*n_segs = 1;
++	}
++}
++
++/* pfe_eth_send_packet
++ */
++static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int tx_q_num = skb_get_queue_mapping(skb);
++	int n_desc, n_segs;
++	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++								tx_q_num);
++
++	netif_info(priv, tx_queued, ndev, "%s\n", __func__);
++
++	if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ +
++			sizeof(unsigned long)))) {
++		netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n",
++			   __func__);
++
++		if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned
++					long)), 0, GFP_ATOMIC)) {
++			/* No need to re-transmit, no way to recover*/
++			kfree_skb(skb);
++			priv->stats.tx_dropped++;
++			return NETDEV_TX_OK;
++		}
++	}
++
++	pfe_tx_get_req_desc(skb, &n_desc, &n_segs);
++
++	hif_tx_lock(&pfe->hif);
++	if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc,
++					   n_segs))) {
++#ifdef PFE_ETH_TX_STATS
++		if (priv->was_stopped[tx_q_num]) {
++			priv->clean_fail[tx_q_num]++;
++			priv->was_stopped[tx_q_num] = 0;
++		}
++#endif
++		hif_tx_unlock(&pfe->hif);
++		return NETDEV_TX_BUSY;
++	}
++
++	pfe_hif_send_packet(skb, priv, tx_q_num);
++
++	hif_tx_unlock(&pfe->hif);
++
++	tx_queue->trans_start = jiffies;
++
++#ifdef PFE_ETH_TX_STATS
++	priv->was_stopped[tx_q_num] = 0;
++#endif
++
++	return NETDEV_TX_OK;
++}
++
++/* pfe_eth_select_queue
++ *
++ */
++static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb,
++				struct net_device *sb_dev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	return pfe_eth_get_queuenum(priv, skb);
++}
++
++/* pfe_eth_get_stats
++ */
++static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++	netif_info(priv, drv, ndev, "%s\n", __func__);
++
++	return &priv->stats;
++}
++
++/* pfe_eth_set_mac_address
++ */
++static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct sockaddr *sa = addr;
++
++	netif_info(priv, drv, ndev, "%s\n", __func__);
++
++	if (!is_valid_ether_addr(sa->sa_data))
++		return -EADDRNOTAVAIL;
++
++	dev_addr_set(ndev, sa->sa_data);
++
++	gemac_set_laddrN(priv->EMAC_baseaddr,
++			 (struct pfe_mac_addr *)ndev->dev_addr, 1);
++
++	return 0;
++}
++
++/* pfe_eth_enet_addr_byte_mac
++ */
++int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr,
++			       struct pfe_mac_addr *enet_addr)
++{
++	if (!enet_byte_addr || !enet_addr) {
++		return -1;
++
++	} else {
++		enet_addr->bottom = enet_byte_addr[0] |
++			(enet_byte_addr[1] << 8) |
++			(enet_byte_addr[2] << 16) |
++			(enet_byte_addr[3] << 24);
++		enet_addr->top = enet_byte_addr[4] |
++			(enet_byte_addr[5] << 8);
++		return 0;
++	}
++}
++
++/* pfe_eth_set_multi
++ */
++static void pfe_eth_set_multi(struct net_device *ndev)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	struct pfe_mac_addr    hash_addr; /* hash register structure */
++	/* specific mac address	register structure */
++	struct pfe_mac_addr    spec_addr;
++	int		result; /* index into hash register to set.. */
++	int		uc_count = 0;
++	struct netdev_hw_addr *ha;
++
++	if (ndev->flags & IFF_PROMISC) {
++		netif_info(priv, drv, ndev, "entering promiscuous mode\n");
++
++		priv->promisc = 1;
++		gemac_enable_copy_all(priv->EMAC_baseaddr);
++	} else {
++		priv->promisc = 0;
++		gemac_disable_copy_all(priv->EMAC_baseaddr);
++	}
++
++	/* Enable broadcast frame reception if required. */
++	if (ndev->flags & IFF_BROADCAST) {
++		gemac_allow_broadcast(priv->EMAC_baseaddr);
++	} else {
++		netif_info(priv, drv, ndev,
++			   "disabling broadcast frame reception\n");
++
++		gemac_no_broadcast(priv->EMAC_baseaddr);
++	}
++
++	if (ndev->flags & IFF_ALLMULTI) {
++		/* Set the hash to rx all multicast frames */
++		hash_addr.bottom = 0xFFFFFFFF;
++		hash_addr.top = 0xFFFFFFFF;
++		gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++		netdev_for_each_uc_addr(ha, ndev) {
++			if (uc_count >= MAX_UC_SPEC_ADDR_REG)
++				break;
++			pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr);
++			gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr,
++					 uc_count + 2);
++			uc_count++;
++		}
++	} else if ((netdev_mc_count(ndev) > 0)  || (netdev_uc_count(ndev))) {
++		u8 *addr;
++
++		hash_addr.bottom = 0;
++		hash_addr.top = 0;
++
++		netdev_for_each_mc_addr(ha, ndev) {
++			addr = ha->addr;
++
++			netif_info(priv, drv, ndev,
++				   "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n",
++				addr[0], addr[1], addr[2],
++				addr[3], addr[4], addr[5]);
++
++			result = pfe_eth_get_hash(addr);
++
++			if (result < EMAC_HASH_REG_BITS) {
++				if (result < 32)
++					hash_addr.bottom |= (1 << result);
++				else
++					hash_addr.top |= (1 << (result - 32));
++			} else {
++				break;
++			}
++		}
++
++		uc_count = -1;
++		netdev_for_each_uc_addr(ha, ndev) {
++			addr = ha->addr;
++
++			if (++uc_count < MAX_UC_SPEC_ADDR_REG)   {
++				netdev_info(ndev,
++					    "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n",
++					    addr[0], addr[1], addr[2],
++					    addr[3], addr[4], addr[5]);
++				pfe_eth_enet_addr_byte_mac(addr, &spec_addr);
++				gemac_set_laddrN(priv->EMAC_baseaddr,
++						 &spec_addr, uc_count + 2);
++			} else {
++				netif_info(priv, drv, ndev,
++					   "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n",
++					   addr[0], addr[1], addr[2],
++					   addr[3], addr[4], addr[5]);
++
++				result = pfe_eth_get_hash(addr);
++				if (result >= EMAC_HASH_REG_BITS) {
++					break;
++
++				} else {
++					if (result < 32)
++						hash_addr.bottom |= (1 <<
++								result);
++					else
++						hash_addr.top |= (1 <<
++								(result - 32));
++				}
++			}
++		}
++
++		gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++	}
++
++	if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) {
++		/*
++		 *  Check if there are any specific address HW registers that
++		 * need to be flushed
++		 */
++		for (uc_count = netdev_uc_count(ndev); uc_count <
++			MAX_UC_SPEC_ADDR_REG; uc_count++)
++			gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2);
++	}
++
++	if (ndev->flags & IFF_LOOPBACK)
++		gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL);
++}
++
++/* pfe_eth_set_features
++ */
++static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t
++					features)
++{
++	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++	int rc = 0;
++
++	if (features & NETIF_F_RXCSUM)
++		gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++	else
++		gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++	return rc;
++}
++
++/* pfe_eth_fast_tx_timeout
++ */
++static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer)
++{
++	struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct
++							pfe_eth_fast_timer,
++							timer);
++	struct pfe_eth_priv_s *priv =  container_of(fast_tx_timeout->base,
++							struct pfe_eth_priv_s,
++							fast_tx_timeout);
++	struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++						fast_tx_timeout->queuenum);
++
++	if (netif_tx_queue_stopped(tx_queue)) {
++#ifdef PFE_ETH_TX_STATS
++		priv->was_stopped[fast_tx_timeout->queuenum] = 1;
++#endif
++		netif_tx_wake_queue(tx_queue);
++	}
++
++	return HRTIMER_NORESTART;
++}
++
++/* pfe_eth_fast_tx_timeout_init
++ */
++static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv)
++{
++	int i;
++
++	for (i = 0; i < emac_txq_cnt; i++) {
++		priv->fast_tx_timeout[i].queuenum = i;
++		hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC,
++			     HRTIMER_MODE_REL);
++		priv->fast_tx_timeout[i].timer.function =
++				pfe_eth_fast_tx_timeout;
++		priv->fast_tx_timeout[i].base = priv->fast_tx_timeout;
++	}
++}
++
++static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev,
++				      struct	pfe_eth_priv_s *priv,
++				      unsigned int qno)
++{
++	void *buf_addr;
++	unsigned int rx_ctrl;
++	unsigned int desc_ctrl = 0;
++	struct hif_ipsec_hdr *ipsec_hdr = NULL;
++	struct sk_buff *skb;
++	struct sk_buff *skb_frag, *skb_frag_last = NULL;
++	int length = 0, offset;
++
++	skb = priv->skb_inflight[qno];
++
++	if (skb) {
++		skb_frag_last = skb_shinfo(skb)->frag_list;
++		if (skb_frag_last) {
++			while (skb_frag_last->next)
++				skb_frag_last = skb_frag_last->next;
++		}
++	}
++
++	while (!(desc_ctrl & CL_DESC_LAST)) {
++		buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length,
++					       &offset, &rx_ctrl, &desc_ctrl,
++					       (void **)&ipsec_hdr);
++		if (!buf_addr)
++			goto incomplete;
++
++#ifdef PFE_ETH_NAPI_STATS
++		priv->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++
++		/* First frag */
++		if (desc_ctrl & CL_DESC_FIRST) {
++			skb = build_skb(buf_addr, 0);
++			if (unlikely(!skb))
++				goto pkt_drop;
++
++			skb_reserve(skb, offset);
++			skb_put(skb, length);
++			skb->dev = ndev;
++
++			if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl &
++					HIF_CTRL_RX_CHECKSUMMED))
++				skb->ip_summed = CHECKSUM_UNNECESSARY;
++			else
++				skb_checksum_none_assert(skb);
++
++		} else {
++			/* Next frags */
++			if (unlikely(!skb)) {
++				pr_err("%s: NULL skb_inflight\n",
++				       __func__);
++				goto pkt_drop;
++			}
++
++			skb_frag = build_skb(buf_addr, 0);
++
++			if (unlikely(!skb_frag)) {
++				kfree(buf_addr);
++				goto pkt_drop;
++			}
++
++			skb_reserve(skb_frag, offset);
++			skb_put(skb_frag, length);
++
++			skb_frag->dev = ndev;
++
++			if (skb_shinfo(skb)->frag_list)
++				skb_frag_last->next = skb_frag;
++			else
++				skb_shinfo(skb)->frag_list = skb_frag;
++
++			skb->truesize += skb_frag->truesize;
++			skb->data_len += length;
++			skb->len += length;
++			skb_frag_last = skb_frag;
++		}
++	}
++
++	priv->skb_inflight[qno] = NULL;
++	return skb;
++
++incomplete:
++	priv->skb_inflight[qno] = skb;
++	return NULL;
++
++pkt_drop:
++	priv->skb_inflight[qno] = NULL;
++
++	if (skb)
++		kfree_skb(skb);
++	else
++		kfree(buf_addr);
++
++	priv->stats.rx_errors++;
++
++	return NULL;
++}
++
++/* pfe_eth_poll
++ */
++static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi,
++			unsigned int qno, int budget)
++{
++	struct net_device *ndev = priv->ndev;
++	struct sk_buff *skb;
++	int work_done = 0;
++	unsigned int len;
++
++	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++	priv->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++	do {
++		skb = pfe_eth_rx_skb(ndev, priv, qno);
++
++		if (!skb)
++			break;
++
++		len = skb->len;
++
++		/* Packet will be processed */
++		skb->protocol = eth_type_trans(skb, ndev);
++
++		netif_receive_skb(skb);
++
++		priv->stats.rx_packets++;
++		priv->stats.rx_bytes += len;
++
++		work_done++;
++
++#ifdef PFE_ETH_NAPI_STATS
++		priv->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++
++	} while (work_done < budget);
++
++	/*
++	 * If no Rx receive nor cleanup work was done, exit polling mode.
++	 * No more netif_running(dev) check is required here , as this is
++	 * checked in net/core/dev.c (2.6.33.5 kernel specific).
++	 */
++	if (work_done < budget) {
++		napi_complete(napi);
++
++		hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND,
++					    qno);
++	}
++#ifdef PFE_ETH_NAPI_STATS
++	else
++		priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++	return work_done;
++}
++
++/*
++ * pfe_eth_lro_poll
++ */
++static int pfe_eth_lro_poll(struct napi_struct *napi, int budget)
++{
++	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++							lro_napi);
++
++	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++	return pfe_eth_poll(priv, napi, 2, budget);
++}
++
++/* pfe_eth_low_poll
++ */
++static int pfe_eth_low_poll(struct napi_struct *napi, int budget)
++{
++	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++							low_napi);
++
++	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++	return pfe_eth_poll(priv, napi, 1, budget);
++}
++
++/* pfe_eth_high_poll
++ */
++static int pfe_eth_high_poll(struct napi_struct *napi, int budget)
++{
++	struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++							high_napi);
++
++	netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++	return pfe_eth_poll(priv, napi, 0, budget);
++}
++
++static const struct net_device_ops pfe_netdev_ops = {
++	.ndo_open = pfe_eth_open,
++	.ndo_stop = pfe_eth_close,
++	.ndo_start_xmit = pfe_eth_send_packet,
++	.ndo_select_queue = pfe_eth_select_queue,
++	.ndo_set_rx_mode = pfe_eth_set_multi,
++	.ndo_set_mac_address = pfe_eth_set_mac_address,
++	.ndo_validate_addr = eth_validate_addr,
++	.ndo_change_mtu = pfe_eth_change_mtu,
++	.ndo_get_stats = pfe_eth_get_stats,
++	.ndo_set_features = pfe_eth_set_features,
++};
++
++/* pfe_eth_init_one
++ */
++static int pfe_eth_init_one(struct pfe *pfe,
++			    struct ls1012a_pfe_platform_data *pfe_info,
++			    int id)
++{
++	struct net_device *ndev = NULL;
++	struct pfe_eth_priv_s *priv = NULL;
++	struct ls1012a_eth_platform_data *einfo;
++	int err;
++
++	einfo = (struct ls1012a_eth_platform_data *)
++				pfe_info->ls1012a_eth_pdata;
++
++	/* einfo never be NULL, but no harm in having this check */
++	if (!einfo) {
++		pr_err(
++			"%s: pfe missing additional gemacs platform data\n"
++			, __func__);
++		err = -ENODEV;
++		goto err0;
++	}
++
++	if (us)
++		emac_txq_cnt = EMAC_TXQ_CNT;
++	/* Create an ethernet device instance */
++	ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);
++
++	if (!ndev) {
++		pr_err("%s: gemac %d device allocation failed\n",
++		       __func__, einfo[id].gem_id);
++		err = -ENOMEM;
++		goto err0;
++	}
++
++	priv = netdev_priv(ndev);
++	priv->ndev = ndev;
++	priv->id = einfo[id].gem_id;
++	priv->pfe = pfe;
++	priv->phy_node = einfo[id].phy_node;
++
++	SET_NETDEV_DEV(priv->ndev, priv->pfe->dev);
++
++	pfe->eth.eth_priv[id] = priv;
++
++	/* Set the info in the priv to the current info */
++	priv->einfo = &einfo[id];
++	priv->EMAC_baseaddr = cbus_emac_base[id];
++	priv->GPI_baseaddr = cbus_gpi_base[id];
++
++	spin_lock_init(&priv->lock);
++
++	pfe_eth_fast_tx_timeout_init(priv);
++
++	/* Copy the station address into the dev structure, */
++	dev_addr_set(ndev, einfo[id].mac_addr);
++
++	if (us)
++		goto phy_init;
++
++	ndev->mtu = 1500;
++
++	/* Set MTU limits */
++	ndev->min_mtu = ETH_MIN_MTU;
++
++/*
++ * Jumbo frames are not supported on LS1012A rev-1.0.
++ * So max mtu should be restricted to supported frame length.
++ */
++	if (pfe_errata_a010897)
++		ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;
++	else
++		ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;
++
++	/*Enable after checksum offload is validated */
++	ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
++		NETIF_F_IPV6_CSUM | NETIF_F_SG;
++
++	/* enabled by default */
++	ndev->features = ndev->hw_features;
++
++	priv->usr_features = ndev->features;
++
++	ndev->netdev_ops = &pfe_netdev_ops;
++
++	ndev->ethtool_ops = &pfe_ethtool_ops;
++
++	/* Enable basic messages by default */
++	priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK |
++				NETIF_MSG_PROBE;
++
++	netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll);
++	netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll);
++	netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll);
++
++	err = register_netdev(ndev);
++	if (err) {
++		netdev_err(ndev, "register_netdev() failed\n");
++		goto err1;
++	}
++
++	if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
++	    ((pfe_use_old_dts_phy) &&
++	      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
++		pr_info("%s: No PHY or fixed-link\n", __func__);
++		goto skip_phy_init;
++	}
++
++phy_init:
++	device_init_wakeup(&ndev->dev, true);
++
++	err = pfe_phy_init(ndev);
++	if (err) {
++		netdev_err(ndev, "%s: pfe_phy_init() failed\n",
++			   __func__);
++		goto err2;
++	}
++
++	if (us) {
++		if (priv->phydev)
++			phy_start(priv->phydev);
++		return 0;
++	}
++
++	netif_carrier_on(ndev);
++
++skip_phy_init:
++	/* Create all the sysfs files */
++	if (pfe_eth_sysfs_init(ndev))
++		goto err3;
++
++	netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n",
++		   __func__, priv->EMAC_baseaddr);
++
++	return 0;
++
++err3:
++	pfe_phy_exit(priv->ndev);
++err2:
++	if (us)
++		goto err1;
++	unregister_netdev(ndev);
++err1:
++	free_netdev(priv->ndev);
++err0:
++	return err;
++}
++
++/* pfe_eth_init
++ */
++int pfe_eth_init(struct pfe *pfe)
++{
++	int ii = 0;
++	int err;
++	struct ls1012a_pfe_platform_data *pfe_info;
++
++	pr_info("%s\n", __func__);
++
++	cbus_emac_base[0] = EMAC1_BASE_ADDR;
++	cbus_emac_base[1] = EMAC2_BASE_ADDR;
++
++	cbus_gpi_base[0] = EGPI1_BASE_ADDR;
++	cbus_gpi_base[1] = EGPI2_BASE_ADDR;
++
++	pfe_info = (struct ls1012a_pfe_platform_data *)
++					pfe->dev->platform_data;
++	if (!pfe_info) {
++		pr_err("%s: pfe missing additional platform data\n", __func__);
++		err = -ENODEV;
++		goto err_pdata;
++	}
++
++	for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
++		err = pfe_eth_mdio_init(pfe, pfe_info, ii);
++		if (err) {
++			pr_err("%s: pfe_eth_mdio_init() failed\n", __func__);
++			goto err_mdio_init;
++		}
++	}
++
++	if (soc_device_match(ls1012a_rev1_soc_attr))
++		pfe_errata_a010897 = true;
++	else
++		pfe_errata_a010897 = false;
++
++	for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
++		err = pfe_eth_init_one(pfe, pfe_info, ii);
++		if (err)
++			goto err_eth_init;
++	}
++
++	return 0;
++
++err_eth_init:
++	while (ii--) {
++		pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
++		pfe_eth_mdio_exit(pfe, ii);
++	}
++
++err_mdio_init:
++err_pdata:
++	return err;
++}
++
++/* pfe_eth_exit_one
++ */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv)
++{
++	netif_info(priv, probe, priv->ndev, "%s\n", __func__);
++
++	if (!us)
++		pfe_eth_sysfs_exit(priv->ndev);
++
++	if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
++	    ((pfe_use_old_dts_phy) &&
++	      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
++		pr_info("%s: No PHY or fixed-link\n", __func__);
++		goto skip_phy_exit;
++	}
++
++	pfe_phy_exit(priv->ndev);
++
++skip_phy_exit:
++	if (!us)
++		unregister_netdev(priv->ndev);
++
++	free_netdev(priv->ndev);
++}
++
++/* pfe_eth_exit
++ */
++void pfe_eth_exit(struct pfe *pfe)
++{
++	int ii;
++
++	pr_info("%s\n", __func__);
++
++	for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
++		pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
++
++	for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
++		pfe_eth_mdio_exit(pfe, ii);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.h
+@@ -0,0 +1,175 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_ETH_H_
++#define _PFE_ETH_H_
++#include <linux/kernel.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/time.h>
++
++#define PFE_ETH_NAPI_STATS
++#define PFE_ETH_TX_STATS
++
++#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE)
++#define LRO_LEN_COUNT_MAX	32
++#define LRO_NB_COUNT_MAX	32
++
++#define PFE_PAUSE_FLAG_ENABLE		1
++#define PFE_PAUSE_FLAG_AUTONEG		2
++
++/* GEMAC configured by SW */
++/* GEMAC configured by phy lines (not for MII/GMII) */
++
++#define GEMAC_SW_FULL_DUPLEX    BIT(9)
++#define GEMAC_SW_SPEED_10M      (0 << 12)
++#define GEMAC_SW_SPEED_100M     BIT(12)
++#define GEMAC_SW_SPEED_1G       (2 << 12)
++
++#define GEMAC_NO_PHY            BIT(0)
++
++struct ls1012a_eth_platform_data {
++	/* board specific information */
++	phy_interface_t mii_config;
++	u32 phy_flags;
++	u32 gem_id;
++	u32 phy_id;
++	u32 mdio_muxval;
++	u8 mac_addr[ETH_ALEN];
++	struct device_node	*phy_node;
++};
++
++struct ls1012a_mdio_platform_data {
++	int id;
++	int irq[32];
++	u32 phy_mask;
++	int mdc_div;
++};
++
++struct ls1012a_pfe_platform_data {
++	struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
++	struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
++};
++
++#define NUM_GEMAC_SUPPORT	2
++#define DRV_NAME		"pfe-eth"
++#define DRV_VERSION		"1.0"
++
++#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS	3
++#define TX_POLL_TIMEOUT_MS	1000
++
++#define EMAC_TXQ_CNT	16
++#define EMAC_TXQ_DEPTH	(HIF_TX_DESC_NT)
++
++#define JUMBO_FRAME_SIZE_V1	1900
++#define JUMBO_FRAME_SIZE_V2	10258
++/*
++ * Client Tx queue threshold, for txQ flush condition.
++ * It must be smaller than the queue size (in case we ever change it in the
++ * future).
++ */
++#define HIF_CL_TX_FLUSH_MARK	32
++
++/*
++ * Max number of TX resources (HIF descriptors or skbs) that will be released
++ * in a single go during batch recycling.
++ * Should be lower than the flush mark so the SW can provide the HW with a
++ * continuous stream of packets instead of bursts.
++ */
++#define TX_FREE_MAX_COUNT 16
++#define EMAC_RXQ_CNT	3
++#define EMAC_RXQ_DEPTH	HIF_RX_DESC_NT
++/* make sure clients can receive a full burst of packets */
++#define EMAC_RMON_TXBYTES_POS	0x00
++#define EMAC_RMON_RXBYTES_POS	0x14
++
++#define EMAC_QUEUENUM_MASK      (emac_txq_cnt - 1)
++#define EMAC_MDIO_TIMEOUT	1000
++#define MAX_UC_SPEC_ADDR_REG 31
++
++struct pfe_eth_fast_timer {
++	int queuenum;
++	struct hrtimer timer;
++	void *base;
++};
++
++struct  pfe_eth_priv_s {
++	struct pfe		*pfe;
++	struct hif_client_s	client;
++	struct napi_struct	lro_napi;
++	struct napi_struct	low_napi;
++	struct napi_struct	high_napi;
++	int			low_tmu_q;
++	int			high_tmu_q;
++	struct net_device_stats stats;
++	struct net_device	*ndev;
++	int			id;
++	int			promisc;
++	unsigned int		msg_enable;
++	unsigned int		usr_features;
++
++	spinlock_t		lock; /* protect member variables */
++	unsigned int		event_status;
++	int			irq;
++	void			*EMAC_baseaddr;
++	void			*GPI_baseaddr;
++	/* PHY stuff */
++	struct phy_device	*phydev;
++	int			oldspeed;
++	int			oldduplex;
++	int			oldlink;
++	struct device_node	*phy_node;
++	struct clk		*gemtx_clk;
++	int			wol;
++	int			pause_flag;
++
++	int			default_priority;
++	struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];
++
++	struct ls1012a_eth_platform_data *einfo;
++	struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];
++
++#ifdef PFE_ETH_TX_STATS
++	unsigned int stop_queue_total[EMAC_TXQ_CNT];
++	unsigned int stop_queue_hif[EMAC_TXQ_CNT];
++	unsigned int stop_queue_hif_client[EMAC_TXQ_CNT];
++	unsigned int stop_queue_credit[EMAC_TXQ_CNT];
++	unsigned int clean_fail[EMAC_TXQ_CNT];
++	unsigned int was_stopped[EMAC_TXQ_CNT];
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++	unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++	unsigned int frags_inflight[EMAC_RXQ_CNT + 6];
++};
++
++struct pfe_eth {
++	struct pfe_eth_priv_s *eth_priv[3];
++};
++
++struct pfe_mdio_priv_s {
++	void __iomem *mdio_base;
++	int			mdc_div;
++	struct mii_bus		*mii_bus;
++};
++
++struct pfe_mdio {
++	struct pfe_mdio_priv_s *mdio_priv[3];
++};
++
++int pfe_eth_init(struct pfe *pfe);
++void pfe_eth_exit(struct pfe *pfe);
++int pfe_eth_suspend(struct net_device *dev);
++int pfe_eth_resume(struct net_device *dev);
++int pfe_eth_mdio_reset(struct mii_bus *bus);
++
++#endif /* _PFE_ETH_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.c
+@@ -0,0 +1,398 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++/*
++ * @file
++ * Contains all the functions to handle parsing and loading of PE firmware
++ * files.
++ */
++#include <linux/firmware.h>
++
++#include "pfe_mod.h"
++#include "pfe_firmware.h"
++#include "pfe/pfe.h"
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++
++static struct elf32_shdr *get_elf_section_header(const u8 *fw,
++						 const char *section)
++{
++	struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
++	struct elf32_shdr *shdr;
++	struct elf32_shdr *shdr_shstr;
++	Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff);
++	Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize);
++	Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum);
++	Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx);
++	Elf32_Off shstr_offset;
++	Elf32_Word sh_name;
++	const char *name;
++	int i;
++
++	/* Section header strings */
++	shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx
++					* e_shentsize);
++	shstr_offset = be32_to_cpu(shdr_shstr->sh_offset);
++
++	for (i = 0; i < e_shnum; i++) {
++		shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff
++					     + i * e_shentsize);
++
++		sh_name = be32_to_cpu(shdr->sh_name);
++
++		name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name);
++
++		if (!strcmp(name, section))
++			return shdr;
++	}
++
++	pr_err("%s: didn't find section %s\n", __func__, section);
++
++	return NULL;
++}
++
++#if defined(CFG_DIAGS)
++static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info
++				*diags_info)
++{
++	struct elf32_shdr *shdr;
++	unsigned long offset, size;
++
++	shdr = get_elf_section_header(fw, ".pfe_diags_str");
++	if (shdr) {
++		offset = be32_to_cpu(shdr->sh_offset);
++		size = be32_to_cpu(shdr->sh_size);
++		diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr);
++		diags_info->diags_str_size = size;
++		diags_info->diags_str_array = kmalloc(size, GFP_KERNEL);
++		memcpy(diags_info->diags_str_array, fw + offset, size);
++
++		return 0;
++	} else {
++		return -1;
++	}
++}
++#endif
++
++static void pfe_check_version_info(const u8 *fw)
++{
++	/*static char *version = NULL;*/
++	const u8 *elf_data = fw;
++	static char *version;
++
++	struct elf32_shdr *shdr = get_elf_section_header(fw, ".version");
++
++	if (shdr) {
++		if (!version) {
++			/*
++			 * this is the first fw we load, use its version
++			 * string as reference (whatever it is)
++			 */
++			version = (char *)(elf_data +
++					be32_to_cpu(shdr->sh_offset));
++
++			pr_info("PFE binary version: %s\n", version);
++		} else {
++			/*
++			 * already have loaded at least one firmware, check
++			 * sequence can start now
++			 */
++			if (strcmp(version, (char *)(elf_data +
++				be32_to_cpu(shdr->sh_offset)))) {
++				pr_info(
++				"WARNING: PFE firmware binaries from incompatible version\n");
++			}
++		}
++	} else {
++		/*
++		 * version cannot be verified, a potential issue that should
++		 * be reported
++		 */
++		pr_info(
++			 "WARNING: PFE firmware binaries from incompatible version\n");
++	}
++}
++
++/* PFE elf firmware loader.
++ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
++ *
++ * @param pe_mask	Mask of PE id's to load firmware to
++ * @param fw		Pointer to the firmware image
++ *
++ * @return		0 on success, a negative value on error
++ *
++ */
++int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe)
++{
++	struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
++	Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
++	struct elf32_shdr *shdr = (struct elf32_shdr *)(fw +
++					be32_to_cpu(elf_hdr->e_shoff));
++	int id, section;
++	int rc;
++
++	pr_info("%s\n", __func__);
++
++	/* Some sanity checks */
++	if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
++		pr_err("%s: incorrect elf magic number\n", __func__);
++		return -EINVAL;
++	}
++
++	if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
++		pr_err("%s: incorrect elf class(%x)\n", __func__,
++		       elf_hdr->e_ident[EI_CLASS]);
++		return -EINVAL;
++	}
++
++	if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
++		pr_err("%s: incorrect elf data(%x)\n", __func__,
++		       elf_hdr->e_ident[EI_DATA]);
++		return -EINVAL;
++	}
++
++	if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
++		pr_err("%s: incorrect elf file type(%x)\n", __func__,
++		       be16_to_cpu(elf_hdr->e_type));
++		return -EINVAL;
++	}
++
++	for (section = 0; section < sections; section++, shdr++) {
++		if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
++			SHF_EXECINSTR)))
++			continue;
++
++		for (id = 0; id < MAX_PE; id++)
++			if (pe_mask & (1 << id)) {
++				rc = pe_load_elf_section(id, elf_hdr, shdr,
++							 pfe->dev);
++				if (rc < 0)
++					goto err;
++			}
++	}
++
++	pfe_check_version_info(fw);
++
++	return 0;
++
++err:
++	return rc;
++}
++
++int get_firmware_in_fdt(const u8 **pe_fw, const char *name)
++{
++	struct device_node *np;
++	const unsigned int *len;
++	const void *data;
++
++	if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) {
++		/* The firmware should be inside the device tree. */
++		np = of_find_compatible_node(NULL, NULL,
++					     "fsl,pfe-class-firmware");
++		if (!np) {
++			pr_info("Failed to find the node\n");
++			return -ENOENT;
++		}
++
++		data = of_get_property(np, "fsl,class-firmware", NULL);
++		if (data) {
++			len = of_get_property(np, "length", NULL);
++			pr_info("CLASS fw of length %d bytes loaded from FDT.\n",
++				be32_to_cpu(*len));
++		} else {
++			pr_info("fsl,class-firmware not found!!!!\n");
++			return -ENOENT;
++		}
++		of_node_put(np);
++		*pe_fw = data;
++	} else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) {
++		np = of_find_compatible_node(NULL, NULL,
++					     "fsl,pfe-tmu-firmware");
++		if (!np) {
++			pr_info("Failed to find the node\n");
++			return -ENOENT;
++		}
++
++		data = of_get_property(np, "fsl,tmu-firmware", NULL);
++		if (data) {
++			len = of_get_property(np, "length", NULL);
++			pr_info("TMU fw of length %d bytes loaded from FDT.\n",
++				be32_to_cpu(*len));
++		} else {
++			pr_info("fsl,tmu-firmware not found!!!!\n");
++			return -ENOENT;
++		}
++		of_node_put(np);
++		*pe_fw = data;
++	} else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) {
++		np = of_find_compatible_node(NULL, NULL,
++					     "fsl,pfe-util-firmware");
++		if (!np) {
++			pr_info("Failed to find the node\n");
++			return -ENOENT;
++		}
++
++		data = of_get_property(np, "fsl,util-firmware", NULL);
++		if (data) {
++			len = of_get_property(np, "length", NULL);
++			pr_info("UTIL fw of length %d bytes loaded from FDT.\n",
++				be32_to_cpu(*len));
++		} else {
++			pr_info("fsl,util-firmware not found!!!!\n");
++			return -ENOENT;
++		}
++		of_node_put(np);
++		*pe_fw = data;
++	} else {
++		pr_err("firmware:%s not known\n", name);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/* PFE firmware initialization.
++ * Loads different firmware files from filesystem.
++ * Initializes PE IMEM/DMEM and UTIL-PE DDR
++ * Initializes control path symbol addresses (by looking them up in the elf
++ * firmware files
++ * Takes PE's out of reset
++ *
++ * @return	0 on success, a negative value on error
++ *
++ */
++int pfe_firmware_init(struct pfe *pfe)
++{
++	const struct firmware *class_fw, *tmu_fw;
++	const u8 *class_elf_fw, *tmu_elf_fw;
++	int rc = 0, fs_load = 0;
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	const struct firmware *util_fw;
++	const u8 *util_elf_fw;
++
++#endif
++
++	pr_info("%s\n", __func__);
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
++	    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) ||
++	    get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME))
++#else
++	if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
++	    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME))
++#endif
++	{
++		pr_info("%s:PFE firmware not found in FDT.\n", __func__);
++		pr_info("%s:Trying to load firmware from filesystem...!\n", __func__);
++
++		/* look for firmware in filesystem...!*/
++		fs_load = 1;
++		if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) {
++			pr_err("%s: request firmware %s failed\n", __func__,
++			       CLASS_FIRMWARE_FILENAME);
++			rc = -ETIMEDOUT;
++			goto err0;
++		}
++		class_elf_fw = class_fw->data;
++
++		if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) {
++			pr_err("%s: request firmware %s failed\n", __func__,
++			       TMU_FIRMWARE_FILENAME);
++			rc = -ETIMEDOUT;
++			goto err1;
++		}
++		tmu_elf_fw = tmu_fw->data;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++		if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) {
++			pr_err("%s: request firmware %s failed\n", __func__,
++			       UTIL_FIRMWARE_FILENAME);
++			rc = -ETIMEDOUT;
++			goto err2;
++		}
++		util_elf_fw = util_fw->data;
++#endif
++	}
++
++	rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe);
++	if (rc < 0) {
++		pr_err("%s: class firmware load failed\n", __func__);
++		goto err3;
++	}
++
++#if defined(CFG_DIAGS)
++	rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info);
++	if (rc < 0) {
++		pr_warn(
++			"PFE diags won't be available for class PEs\n");
++		rc = 0;
++	}
++#endif
++
++	rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe);
++	if (rc < 0) {
++		pr_err("%s: tmu firmware load failed\n", __func__);
++		goto err3;
++	}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe);
++	if (rc < 0) {
++		pr_err("%s: util firmware load failed\n", __func__);
++		goto err3;
++	}
++
++#if defined(CFG_DIAGS)
++	rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info);
++	if (rc < 0) {
++		pr_warn(
++			"PFE diags won't be available for util PE\n");
++		rc = 0;
++	}
++#endif
++
++	util_enable();
++#endif
++
++	tmu_enable(0xf);
++	class_enable();
++
++err3:
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (fs_load)
++		release_firmware(util_fw);
++err2:
++#endif
++	if (fs_load)
++		release_firmware(tmu_fw);
++
++err1:
++	if (fs_load)
++		release_firmware(class_fw);
++
++err0:
++	return rc;
++}
++
++/* PFE firmware cleanup
++ * Puts PE's in reset
++ *
++ *
++ */
++void pfe_firmware_exit(struct pfe *pfe)
++{
++	pr_info("%s\n", __func__);
++
++	if (pe_reset_all(&pfe->ctrl) != 0)
++		pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n");
++
++	class_disable();
++	tmu_disable(0xf);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	util_disable();
++#endif
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.h
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_FIRMWARE_H_
++#define _PFE_FIRMWARE_H_
++
++#define CLASS_FIRMWARE_FILENAME		"ppfe_class_ls1012a.elf"
++#define TMU_FIRMWARE_FILENAME		"ppfe_tmu_ls1012a.elf"
++#define UTIL_FIRMWARE_FILENAME		"ppfe_util_ls1012a.elf"
++
++#define PFE_FW_CHECK_PASS		0
++#define PFE_FW_CHECK_FAIL		1
++#define NUM_PFE_FW				3
++
++int pfe_firmware_init(struct pfe *pfe);
++void pfe_firmware_exit(struct pfe *pfe);
++
++#endif /* _PFE_FIRMWARE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hal.c
+@@ -0,0 +1,1517 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include "pfe_mod.h"
++#include "pfe/pfe.h"
++
++/* A-010897: Jumbo frame is not supported */
++extern bool pfe_errata_a010897;
++
++#define PFE_RCR_MAX_FL_MASK	0xC000FFFF
++
++void *cbus_base_addr;
++void *ddr_base_addr;
++unsigned long ddr_phys_base_addr;
++unsigned int ddr_size;
++
++static struct pe_info pe[MAX_PE];
++
++/* Initializes the PFE library.
++ * Must be called before using any of the library functions.
++ *
++ * @param[in] cbus_base		CBUS virtual base address (as mapped in
++ * the host CPU address space)
++ * @param[in] ddr_base		PFE DDR range virtual base address (as
++ * mapped in the host CPU address space)
++ * @param[in] ddr_phys_base	PFE DDR range physical base address (as
++ * mapped in platform)
++ * @param[in] size		PFE DDR range size (as defined by the host
++ * software)
++ */
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
++		  unsigned int size)
++{
++	cbus_base_addr = cbus_base;
++	ddr_base_addr = ddr_base;
++	ddr_phys_base_addr = ddr_phys_base;
++	ddr_size = size;
++
++	pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
++	pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
++	pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
++	pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
++	pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
++	pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
++	pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
++	pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
++	pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
++	pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
++	pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
++	pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
++	pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
++	pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++	pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++	pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++	pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
++	pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
++	pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
++	pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++	pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++	pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++	pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
++	pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
++	pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
++	pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++	pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++	pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++	pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
++	pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
++	pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
++	pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++	pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++	pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
++	pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
++	pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
++	pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
++#endif
++}
++
++/* Writes a buffer to PE internal memory from the host
++ * through indirect access registers.
++ *
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] src		Buffer source address
++ * @param[in] mem_access_addr	DMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len		Number of bytes to copy
++ */
++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned
++int len)
++{
++	u32 offset = 0, val, addr;
++	unsigned int len32 = len >> 2;
++	int i;
++
++	addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
++		PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
++
++	for (i = 0; i < len32; i++, offset += 4, src += 4) {
++		val = *(u32 *)src;
++		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++		writel(addr + offset, pe[id].mem_access_addr);
++	}
++
++	len = (len & 0x3);
++	if (len) {
++		val = 0;
++
++		addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
++			PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
++
++		for (i = 0; i < len; i++, src++)
++			val |= (*(u8 *)src) << (8 * i);
++
++		writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++		writel(addr, pe[id].mem_access_addr);
++	}
++}
++
++/* Writes a buffer to PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] src		Buffer source address
++ * @param[in] dst		DMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len		Number of bytes to copy
++ */
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++	pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst |
++				PE_MEM_ACCESS_DMEM, src, len);
++}
++
++/* Writes a buffer to PE internal program memory (PMEM) from the host
++ * through indirect access registers.
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., TMU3_ID)
++ * @param[in] src		Buffer source address
++ * @param[in] dst		PMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len		Number of bytes to copy
++ */
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++	pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
++				- 1)) | PE_MEM_ACCESS_IMEM, src, len);
++}
++
++/* Reads PE internal program memory (IMEM) from the host
++ * through indirect access registers.
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., TMU3_ID)
++ * @param[in] addr		PMEM read address (must be aligned on size)
++ * @param[in] size		Number of bytes to read (maximum 4, must not
++ * cross 32bit boundaries)
++ * @return			the data read (in PE endianness, i.e BE).
++ */
++u32 pe_pmem_read(int id, u32 addr, u8 size)
++{
++	u32 offset = addr & 0x3;
++	u32 mask = 0xffffffff >> ((4 - size) << 3);
++	u32 val;
++
++	addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
++		| PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++	writel(addr, pe[id].mem_access_addr);
++	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++	return (val >> (offset << 3)) & mask;
++}
++
++/* Writes PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] addr		DMEM write address (must be aligned on size)
++ * @param[in] val		Value to write (in PE endianness, i.e BE)
++ * @param[in] size		Number of bytes to write (maximum 4, must not
++ * cross 32bit boundaries)
++ */
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
++{
++	u32 offset = addr & 0x3;
++
++	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
++		PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++	/* Indirect access interface is byte swapping data being written */
++	writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
++	writel(addr, pe[id].mem_access_addr);
++}
++
++/* Reads PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] addr		DMEM read address (must be aligned on size)
++ * @param[in] size		Number of bytes to read (maximum 4, must not
++ * cross 32bit boundaries)
++ * @return			the data read (in PE endianness, i.e BE).
++ */
++u32 pe_dmem_read(int id, u32 addr, u8 size)
++{
++	u32 offset = addr & 0x3;
++	u32 mask = 0xffffffff >> ((4 - size) << 3);
++	u32 val;
++
++	addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM |
++			PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++	writel(addr, pe[id].mem_access_addr);
++
++	/* Indirect access interface is byte swapping data being read */
++	val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++	return (val >> (offset << 3)) & mask;
++}
++
++/* This function is used to write to CLASS internal bus peripherals (ccu,
++ * pe-lem) from the host
++ * through indirect access registers.
++ * @param[in]	val	value to write
++ * @param[in]	addr	Address to write to (must be aligned on size)
++ * @param[in]	size	Number of bytes to write (1, 2 or 4)
++ *
++ */
++void class_bus_write(u32 val, u32 addr, u8 size)
++{
++	u32 offset = addr & 0x3;
++
++	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++	addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
++			(size << 24);
++
++	writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
++	writel(addr, CLASS_BUS_ACCESS_ADDR);
++}
++
++/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
++ * through indirect access registers.
++ * @param[in] addr	Address to read from (must be aligned on size)
++ * @param[in] size	Number of bytes to read (1, 2 or 4)
++ * @return		the read data
++ *
++ */
++u32 class_bus_read(u32 addr, u8 size)
++{
++	u32 offset = addr & 0x3;
++	u32 mask = 0xffffffff >> ((4 - size) << 3);
++	u32 val;
++
++	writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++	addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
++
++	writel(addr, CLASS_BUS_ACCESS_ADDR);
++	val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
++
++	return (val >> (offset << 3)) & mask;
++}
++
++/* Writes data to the cluster memory (PE_LMEM)
++ * @param[in] dst	PE LMEM destination address (must be 32bit aligned)
++ * @param[in] src	Buffer source address
++ * @param[in] len	Number of bytes to copy
++ */
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
++{
++	u32 len32 = len >> 2;
++	int i;
++
++	for (i = 0; i < len32; i++, src += 4, dst += 4)
++		class_bus_write(*(u32 *)src, dst, 4);
++
++	if (len & 0x2) {
++		class_bus_write(*(u16 *)src, dst, 2);
++		src += 2;
++		dst += 2;
++	}
++
++	if (len & 0x1) {
++		class_bus_write(*(u8 *)src, dst, 1);
++		src++;
++		dst++;
++	}
++}
++
++/* Writes value to the cluster memory (PE_LMEM)
++ * @param[in] dst	PE LMEM destination address (must be 32bit aligned)
++ * @param[in] val	Value to write
++ * @param[in] len	Number of bytes to write
++ */
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
++{
++	u32 len32 = len >> 2;
++	int i;
++
++	val = val | (val << 8) | (val << 16) | (val << 24);
++
++	for (i = 0; i < len32; i++, dst += 4)
++		class_bus_write(val, dst, 4);
++
++	if (len & 0x2) {
++		class_bus_write(val, dst, 2);
++		dst += 2;
++	}
++
++	if (len & 0x1) {
++		class_bus_write(val, dst, 1);
++		dst++;
++	}
++}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++
++/* Writes UTIL program memory (DDR) from the host.
++ *
++ * @param[in] addr	Address to write (virtual, must be aligned on size)
++ * @param[in] val		Value to write (in PE endianness, i.e BE)
++ * @param[in] size		Number of bytes to write (2 or 4)
++ */
++static void util_pmem_write(u32 val, void *addr, u8 size)
++{
++	void *addr64 = (void *)((unsigned long)addr & ~0x7);
++	unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
++
++	/*
++	 * IMEM should  be loaded as a 64bit swapped value in a 64bit aligned
++	 * location
++	 */
++	if (size == 4)
++		writel(be32_to_cpu(val), addr64 + off);
++	else
++		writew(be16_to_cpu((u16)val), addr64 + off);
++}
++
++/* Writes a buffer to UTIL program memory (DDR) from the host.
++ *
++ * @param[in] dst	Address to write (virtual, must be at least 16bit
++ * aligned)
++ * @param[in] src	Buffer to write (in PE endianness, i.e BE, must have
++ * same alignment as dst)
++ * @param[in] len	Number of bytes to write (must be at least 16bit
++ * aligned)
++ */
++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
++{
++	unsigned int len32;
++	int i;
++
++	if ((unsigned long)src & 0x2) {
++		util_pmem_write(*(u16 *)src, dst, 2);
++		src += 2;
++		dst += 2;
++		len -= 2;
++	}
++
++	len32 = len >> 2;
++
++	for (i = 0; i < len32; i++, dst += 4, src += 4)
++		util_pmem_write(*(u32 *)src, dst, 4);
++
++	if (len & 0x2)
++		util_pmem_write(*(u16 *)src, dst, len & 0x2);
++}
++#endif
++
++/* Loads an elf section into pmem
++ * Code needs to be at least 16bit aligned and only PROGBITS sections are
++ * supported
++ *
++ * @param[in] id	PE identification (CLASS0_ID, ..., TMU0_ID, ...,
++ * TMU3_ID)
++ * @param[in] data	pointer to the elf firmware
++ * @param[in] shdr	pointer to the elf section header
++ *
++ */
++static int pe_load_pmem_section(int id, const void *data,
++				struct elf32_shdr *shdr)
++{
++	u32 offset = be32_to_cpu(shdr->sh_offset);
++	u32 addr = be32_to_cpu(shdr->sh_addr);
++	u32 size = be32_to_cpu(shdr->sh_size);
++	u32 type = be32_to_cpu(shdr->sh_type);
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (id == UTIL_ID) {
++		pr_err("%s: unsupported pmem section for UTIL\n",
++		       __func__);
++		return -EINVAL;
++	}
++#endif
++
++	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++		pr_err(
++			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++			, __func__, addr, (unsigned long)data + offset);
++
++		return -EINVAL;
++	}
++
++	if (addr & 0x1) {
++		pr_err("%s: load address(%x) is not 16bit aligned\n",
++		       __func__, addr);
++		return -EINVAL;
++	}
++
++	if (size & 0x1) {
++		pr_err("%s: load size(%x) is not 16bit aligned\n",
++		       __func__, size);
++		return -EINVAL;
++	}
++
++	switch (type) {
++	case SHT_PROGBITS:
++		pe_pmem_memcpy_to32(id, addr, data + offset, size);
++
++		break;
++
++	default:
++		pr_err("%s: unsupported section type(%x)\n", __func__,
++		       type);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/* Loads an elf section into dmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data		pointer to the elf firmware
++ * @param[in] shdr		pointer to the elf section header
++ *
++ */
++static int pe_load_dmem_section(int id, const void *data,
++				struct elf32_shdr *shdr)
++{
++	u32 offset = be32_to_cpu(shdr->sh_offset);
++	u32 addr = be32_to_cpu(shdr->sh_addr);
++	u32 size = be32_to_cpu(shdr->sh_size);
++	u32 type = be32_to_cpu(shdr->sh_type);
++	u32 size32 = size >> 2;
++	int i;
++
++	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++		pr_err(
++			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++			__func__, addr, (unsigned long)data + offset);
++
++		return -EINVAL;
++	}
++
++	if (addr & 0x3) {
++		pr_err("%s: load address(%x) is not 32bit aligned\n",
++		       __func__, addr);
++		return -EINVAL;
++	}
++
++	switch (type) {
++	case SHT_PROGBITS:
++		pe_dmem_memcpy_to32(id, addr, data + offset, size);
++		break;
++
++	case SHT_NOBITS:
++		for (i = 0; i < size32; i++, addr += 4)
++			pe_dmem_write(id, 0, addr, 4);
++
++		if (size & 0x3)
++			pe_dmem_write(id, 0, addr, size & 0x3);
++
++		break;
++
++	default:
++		pr_err("%s: unsupported section type(%x)\n", __func__,
++		       type);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/* Loads an elf section into DDR
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data		pointer to the elf firmware
++ * @param[in] shdr		pointer to the elf section header
++ *
++ */
++static int pe_load_ddr_section(int id, const void *data,
++			       struct elf32_shdr *shdr,
++			       struct device *dev) {
++	u32 offset = be32_to_cpu(shdr->sh_offset);
++	u32 addr = be32_to_cpu(shdr->sh_addr);
++	u32 size = be32_to_cpu(shdr->sh_size);
++	u32 type = be32_to_cpu(shdr->sh_type);
++	u32 flags = be32_to_cpu(shdr->sh_flags);
++
++	switch (type) {
++	case SHT_PROGBITS:
++		if (flags & SHF_EXECINSTR) {
++			if (id <= CLASS_MAX_ID) {
++				/* DO the loading only once in DDR */
++				if (id == CLASS0_ID) {
++					pr_err(
++						"%s: load address(%x) and elf file address(%lx) rcvd\n",
++						__func__, addr,
++						(unsigned long)data + offset);
++					if (((unsigned long)(data + offset)
++						& 0x3) != (addr & 0x3)) {
++						pr_err(
++							"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++							, __func__, addr,
++						(unsigned long)data + offset);
++
++						return -EINVAL;
++					}
++
++					if (addr & 0x1) {
++						pr_err(
++							"%s: load address(%x) is not 16bit aligned\n"
++							, __func__, addr);
++						return -EINVAL;
++					}
++
++					if (size & 0x1) {
++						pr_err(
++							"%s: load length(%x) is not 16bit aligned\n"
++							, __func__, size);
++						return -EINVAL;
++					}
++					memcpy(DDR_PHYS_TO_VIRT(
++						DDR_PFE_TO_PHYS(addr)),
++						data + offset, size);
++				}
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++			} else if (id == UTIL_ID) {
++				if (((unsigned long)(data + offset) & 0x3)
++					!= (addr & 0x3)) {
++					pr_err(
++						"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++						, __func__, addr,
++						(unsigned long)data + offset);
++
++					return -EINVAL;
++				}
++
++				if (addr & 0x1) {
++					pr_err(
++						"%s: load address(%x) is not 16bit aligned\n"
++						, __func__, addr);
++					return -EINVAL;
++				}
++
++				if (size & 0x1) {
++					pr_err(
++						"%s: load length(%x) is not 16bit aligned\n"
++						, __func__, size);
++					return -EINVAL;
++				}
++
++				util_pmem_memcpy(DDR_PHYS_TO_VIRT(
++							DDR_PFE_TO_PHYS(addr)),
++							data + offset, size);
++			}
++#endif
++			} else {
++				pr_err(
++					"%s: unsupported ddr section type(%x) for PE(%d)\n"
++						, __func__, type, id);
++				return -EINVAL;
++			}
++
++		} else {
++			memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data
++				+ offset, size);
++		}
++
++		break;
++
++	case SHT_NOBITS:
++		memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size);
++
++		break;
++
++	default:
++		pr_err("%s: unsupported section type(%x)\n", __func__,
++		       type);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/* Loads an elf section into pe lmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id		PE identification (CLASS0_ID,..., CLASS5_ID)
++ * @param[in] data		pointer to the elf firmware
++ * @param[in] shdr		pointer to the elf section header
++ *
++ */
++static int pe_load_pe_lmem_section(int id, const void *data,
++				   struct elf32_shdr *shdr)
++{
++	u32 offset = be32_to_cpu(shdr->sh_offset);
++	u32 addr = be32_to_cpu(shdr->sh_addr);
++	u32 size = be32_to_cpu(shdr->sh_size);
++	u32 type = be32_to_cpu(shdr->sh_type);
++
++	if (id > CLASS_MAX_ID) {
++		pr_err(
++			"%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
++			 __func__, type, id);
++		return -EINVAL;
++	}
++
++	if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++		pr_err(
++			"%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++			__func__, addr, (unsigned long)data + offset);
++
++		return -EINVAL;
++	}
++
++	if (addr & 0x3) {
++		pr_err("%s: load address(%x) is not 32bit aligned\n",
++		       __func__, addr);
++		return -EINVAL;
++	}
++
++	switch (type) {
++	case SHT_PROGBITS:
++		class_pe_lmem_memcpy_to32(addr, data + offset, size);
++		break;
++
++	case SHT_NOBITS:
++		class_pe_lmem_memset(addr, 0, size);
++		break;
++
++	default:
++		pr_err("%s: unsupported section type(%x)\n", __func__,
++		       type);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++/* Loads an elf section into a PE
++ * For now only supports loading a section to dmem (all PE's), pmem (class and
++ * tmu PE's),
++ * DDDR (util PE code)
++ *
++ * @param[in] id		PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data		pointer to the elf firmware
++ * @param[in] shdr		pointer to the elf section header
++ *
++ */
++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
++			struct device *dev) {
++	u32 addr = be32_to_cpu(shdr->sh_addr);
++	u32 size = be32_to_cpu(shdr->sh_size);
++
++	if (IS_DMEM(addr, size))
++		return pe_load_dmem_section(id, data, shdr);
++	else if (IS_PMEM(addr, size))
++		return pe_load_pmem_section(id, data, shdr);
++	else if (IS_PFE_LMEM(addr, size))
++		return 0;
++	else if (IS_PHYS_DDR(addr, size))
++		return pe_load_ddr_section(id, data, shdr, dev);
++	else if (IS_PE_LMEM(addr, size))
++		return pe_load_pe_lmem_section(id, data, shdr);
++
++	pr_err("%s: unsupported memory range(%x)\n", __func__,
++	       addr);
++	return 0;
++}
++
++/**************************** BMU ***************************/
++
++/* Initializes a BMU block.
++ * @param[in] base	BMU block base address
++ * @param[in] cfg	BMU configuration
++ */
++void bmu_init(void *base, struct BMU_CFG *cfg)
++{
++	bmu_disable(base);
++
++	bmu_set_config(base, cfg);
++
++	bmu_reset(base);
++}
++
++/* Resets a BMU block.
++ * @param[in] base	BMU block base address
++ */
++void bmu_reset(void *base)
++{
++	writel(CORE_SW_RESET, base + BMU_CTRL);
++
++	/* Wait for self clear */
++	while (readl(base + BMU_CTRL) & CORE_SW_RESET)
++		;
++}
++
++/* Enabled a BMU block.
++ * @param[in] base	BMU block base address
++ */
++void bmu_enable(void *base)
++{
++	writel(CORE_ENABLE, base + BMU_CTRL);
++}
++
++/* Disables a BMU block.
++ * @param[in] base	BMU block base address
++ */
++void bmu_disable(void *base)
++{
++	writel(CORE_DISABLE, base + BMU_CTRL);
++}
++
++/* Sets the configuration of a BMU block.
++ * @param[in] base	BMU block base address
++ * @param[in] cfg	BMU configuration
++ */
++void bmu_set_config(void *base, struct BMU_CFG *cfg)
++{
++	writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
++	writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
++	writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
++
++	/* Interrupts are never used */
++	writel(cfg->low_watermark, base + BMU_LOW_WATERMARK);
++	writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK);
++	writel(0x0, base + BMU_INT_ENABLE);
++}
++
++/**************************** MTIP GEMAC ***************************/
++
++/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
++ *   TCP or UDP checksums are discarded
++ *
++ * @param[in] base	GEMAC base address.
++ */
++void gemac_enable_rx_checksum_offload(void *base)
++{
++	/*Do not find configuration to do this */
++}
++
++/* Disable Rx Checksum Engine.
++ *
++ * @param[in] base	GEMAC base address.
++ */
++void gemac_disable_rx_checksum_offload(void *base)
++{
++	/*Do not find configuration to do this */
++}
++
++/* GEMAC set speed.
++ * @param[in] base	GEMAC base address
++ * @param[in] speed	GEMAC speed (10, 100 or 1000 Mbps)
++ */
++void gemac_set_speed(void *base, enum mac_speed gem_speed)
++{
++	u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
++	u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
++
++	switch (gem_speed) {
++	case SPEED_10M:
++			rcr |= EMAC_RCNTRL_RMII_10T;
++			break;
++
++	case SPEED_1000M:
++			ecr |= EMAC_ECNTRL_SPEED;
++			break;
++
++	case SPEED_100M:
++	default:
++			/*It is in 100M mode */
++			break;
++	}
++	writel(ecr, (base + EMAC_ECNTRL_REG));
++	writel(rcr, (base + EMAC_RCNTRL_REG));
++}
++
++/* GEMAC set duplex.
++ * @param[in] base	GEMAC base address
++ * @param[in] duplex	GEMAC duplex mode (Full, Half)
++ */
++void gemac_set_duplex(void *base, int duplex)
++{
++	if (duplex == DUPLEX_HALF) {
++		writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base
++			+ EMAC_TCNTRL_REG);
++		writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base
++			+ EMAC_RCNTRL_REG));
++	} else{
++		writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base
++			+ EMAC_TCNTRL_REG);
++		writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base
++			+ EMAC_RCNTRL_REG));
++	}
++}
++
++/* GEMAC set mode.
++ * @param[in] base	GEMAC base address
++ * @param[in] mode	GEMAC operation mode (MII, RMII, RGMII, SGMII)
++ */
++void gemac_set_mode(void *base, int mode)
++{
++	u32 val = readl(base + EMAC_RCNTRL_REG);
++
++	/*Remove loopbank*/
++	val &= ~EMAC_RCNTRL_LOOP;
++
++	/* Enable flow control and MII mode.PFE firmware always expects
++       CRC should be forwarded by MAC to validate CRC in software.*/
++	val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
++
++	writel(val, base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_enable(void *base)
++{
++	writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +
++		EMAC_ECNTRL_REG);
++}
++
++/* GEMAC disable function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_disable(void *base)
++{
++	writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +
++		EMAC_ECNTRL_REG);
++}
++
++/* GEMAC TX disable function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_tx_disable(void *base)
++{
++	writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +
++		EMAC_TCNTRL_REG);
++}
++
++void gemac_tx_enable(void *base)
++{
++	writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +
++			EMAC_TCNTRL_REG);
++}
++
++/* Sets the hash register of the MAC.
++ * This register is used for matching unicast and multicast frames.
++ *
++ * @param[in] base	GEMAC base address.
++ * @param[in] hash	64-bit hash to be configured.
++ */
++void gemac_set_hash(void *base, struct pfe_mac_addr *hash)
++{
++	writel(hash->bottom,  base + EMAC_GALR);
++	writel(hash->top, base + EMAC_GAUR);
++}
++
++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
++		      unsigned int entry_index)
++{
++	if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
++		return;
++
++	entry_index = entry_index - 1;
++	if (entry_index < 1) {
++		writel(htonl(address->bottom),  base + EMAC_PHY_ADDR_LOW);
++		writel((htonl(address->top) | 0x8808), base +
++			EMAC_PHY_ADDR_HIGH);
++	} else {
++		writel(htonl(address->bottom),  base + ((entry_index - 1) * 8)
++			+ EMAC_SMAC_0_0);
++		writel((htonl(address->top) | 0x8808), base + ((entry_index -
++			1) * 8) + EMAC_SMAC_0_1);
++	}
++}
++
++void gemac_clear_laddrN(void *base, unsigned int entry_index)
++{
++	if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
++		return;
++
++	entry_index = entry_index - 1;
++	if (entry_index < 1) {
++		writel(0, base + EMAC_PHY_ADDR_LOW);
++		writel(0, base + EMAC_PHY_ADDR_HIGH);
++	} else {
++		writel(0,  base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
++		writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
++	}
++}
++
++/* Set the loopback mode of the MAC.  This can be either no loopback for
++ * normal operation, local loopback through MAC internal loopback module or PHY
++ *   loopback for external loopback through a PHY.  This asserts the external
++ * loop pin.
++ *
++ * @param[in] base	GEMAC base address.
++ * @param[in] gem_loop	Loopback mode to be enabled. LB_LOCAL - MAC
++ * Loopback,
++ *			LB_EXT - PHY Loopback.
++ */
++void gemac_set_loop(void *base, enum mac_loop gem_loop)
++{
++	pr_info("%s()\n", __func__);
++	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +
++		EMAC_RCNTRL_REG));
++}
++
++/* GEMAC allow frames
++ * @param[in] base	GEMAC base address
++ */
++void gemac_enable_copy_all(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +
++		EMAC_RCNTRL_REG));
++}
++
++/* GEMAC do not allow frames
++ * @param[in] base	GEMAC base address
++ */
++void gemac_disable_copy_all(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +
++		EMAC_RCNTRL_REG));
++}
++
++/* GEMAC allow broadcast function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_allow_broadcast(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +
++		EMAC_RCNTRL_REG);
++}
++
++/* GEMAC no broadcast function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_no_broadcast(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +
++		EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable 1536 rx function.
++ * @param[in]	base	GEMAC base address
++ */
++void gemac_enable_1536_rx(void *base)
++{
++	/* Set 1536 as Maximum frame length */
++	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
++		| (1536 << 16), base +	EMAC_RCNTRL_REG);
++}
++
++/* GEMAC set rx Max frame length.
++ * @param[in]	base	GEMAC base address
++ * @param[in]	mtu	new mtu
++ */
++void gemac_set_rx_max_fl(void *base, int mtu)
++{
++	/* Set mtu as Maximum frame length */
++	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
++		| (mtu << 16), base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable stacked vlan function.
++ * @param[in]	base	GEMAC base address
++ */
++void gemac_enable_stacked_vlan(void *base)
++{
++	/* MTIP doesn't support stacked vlan */
++}
++
++/* GEMAC enable pause rx function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_enable_pause_rx(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,
++	       base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC disable pause rx function.
++ * @param[in] base	GEMAC base address
++ */
++void gemac_disable_pause_rx(void *base)
++{
++	writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,
++	       base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable pause tx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_pause_tx(void *base)
++{
++	writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);
++}
++
++/* GEMAC disable pause tx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_pause_tx(void *base)
++{
++	writel(0x0, base + EMAC_RX_SECTION_EMPTY);
++}
++
++/* GEMAC wol configuration
++ * @param[in] base	GEMAC base address
++ * @param[in] wol_conf	WoL register configuration
++ */
++void gemac_set_wol(void *base, u32 wol_conf)
++{
++	u32  val = readl(base + EMAC_ECNTRL_REG);
++
++	if (wol_conf)
++		val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
++	else
++		val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
++	writel(val, base + EMAC_ECNTRL_REG);
++}
++
++/* Sets Gemac bus width to 64bit
++ * @param[in] base       GEMAC base address
++ * @param[in] width     gemac bus width to be set possible values are 32/64/128
++ */
++void gemac_set_bus_width(void *base, int width)
++{
++}
++
++/* Sets Gemac configuration.
++ * @param[in] base	GEMAC base address
++ * @param[in] cfg	GEMAC configuration
++ */
++void gemac_set_config(void *base, struct gemac_cfg *cfg)
++{
++	/*GEMAC config taken from VLSI */
++	writel(0x00000004, base + EMAC_TFWR_STR_FWD);
++	writel(0x00000005, base + EMAC_RX_SECTION_FULL);
++
++	if (pfe_errata_a010897)
++		writel(0x0000076c, base + EMAC_TRUNC_FL);
++	else
++		writel(0x00003fff, base + EMAC_TRUNC_FL);
++
++	writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
++	writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
++
++	gemac_set_mode(base, cfg->mode);
++
++	gemac_set_speed(base, cfg->speed);
++
++	gemac_set_duplex(base, cfg->duplex);
++}
++
++/**************************** GPI ***************************/
++
++/* Initializes a GPI block.
++ * @param[in] base	GPI base address
++ * @param[in] cfg	GPI configuration
++ */
++void gpi_init(void *base, struct gpi_cfg *cfg)
++{
++	gpi_reset(base);
++
++	gpi_disable(base);
++
++	gpi_set_config(base, cfg);
++}
++
++/* Resets a GPI block.
++ * @param[in] base	GPI base address
++ */
++void gpi_reset(void *base)
++{
++	writel(CORE_SW_RESET, base + GPI_CTRL);
++}
++
++/* Enables a GPI block.
++ * @param[in] base	GPI base address
++ */
++void gpi_enable(void *base)
++{
++	writel(CORE_ENABLE, base + GPI_CTRL);
++}
++
++/* Disables a GPI block.
++ * @param[in] base	GPI base address
++ */
++void gpi_disable(void *base)
++{
++	writel(CORE_DISABLE, base + GPI_CTRL);
++}
++
++/* Sets the configuration of a GPI block.
++ * @param[in] base	GPI base address
++ * @param[in] cfg	GPI configuration
++ */
++void gpi_set_config(void *base, struct gpi_cfg *cfg)
++{
++	writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),	base
++		+ GPI_LMEM_ALLOC_ADDR);
++	writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),	base
++		+ GPI_LMEM_FREE_ADDR);
++	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),	base
++		+ GPI_DDR_ALLOC_ADDR);
++	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),	base
++		+ GPI_DDR_FREE_ADDR);
++	writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
++	writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
++	writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
++	writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
++	writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
++	writel((DDR_HDR_SIZE << 16) |	LMEM_HDR_SIZE,	base + GPI_HDR_SIZE);
++	writel((DDR_BUF_SIZE << 16) |	LMEM_BUF_SIZE,	base + GPI_BUF_SIZE);
++
++	writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
++		GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
++	writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
++	writel(cfg->aseq_len,	base + GPI_DTX_ASEQ);
++	writel(1, base + GPI_TOE_CHKSUM_EN);
++
++	if (cfg->mtip_pause_reg) {
++		writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);
++		writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);
++	}
++}
++
++/**************************** CLASSIFIER ***************************/
++
++/* Initializes CLASSIFIER block.
++ * @param[in] cfg	CLASSIFIER configuration
++ */
++void class_init(struct class_cfg *cfg)
++{
++	class_reset();
++
++	class_disable();
++
++	class_set_config(cfg);
++}
++
++/* Resets CLASSIFIER block.
++ *
++ */
++void class_reset(void)
++{
++	writel(CORE_SW_RESET, CLASS_TX_CTRL);
++}
++
++/* Enables all CLASS-PE's cores.
++ *
++ */
++void class_enable(void)
++{
++	writel(CORE_ENABLE, CLASS_TX_CTRL);
++}
++
++/* Disables all CLASS-PE's cores.
++ *
++ */
++void class_disable(void)
++{
++	writel(CORE_DISABLE, CLASS_TX_CTRL);
++}
++
++/*
++ * Sets the configuration of the CLASSIFIER block.
++ * @param[in] cfg	CLASSIFIER configuration
++ */
++void class_set_config(struct class_cfg *cfg)
++{
++	u32 val;
++
++	/* Initialize route table */
++	if (!cfg->resume)
++		memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 <<
++		cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++	writel(cfg->pe_sys_clk_ratio,	CLASS_PE_SYS_CLK_RATIO);
++#endif
++
++	writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,	CLASS_HDR_SIZE);
++	writel(LMEM_BUF_SIZE,				CLASS_LMEM_BUF_SIZE);
++	writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
++		CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
++		CLASS_ROUTE_HASH_ENTRY_SIZE);
++	writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)),
++	       CLASS_HIF_PARSE);
++
++	val = HASH_CRC_PORT_IP | QB2BUS_LE;
++
++#if defined(CONFIG_IP_ALIGNED)
++	val |= IP_ALIGNED;
++#endif
++
++	/*
++	 *  Class PE packet steering will only work if TOE mode, bridge fetch or
++	 * route fetch are enabled (see class/qb_fet.v). Route fetch would
++	 * trigger additional memory copies (likely from DDR because of hash
++	 * table size, which cannot be reduced because PE software still
++	 * relies on hash value computed in HW), so when not in TOE mode we
++	 * simply enable HW bridge fetch even though we don't use it.
++	 */
++	if (cfg->toe_mode)
++		val |= CLASS_TOE;
++	else
++		val |= HW_BRIDGE_FETCH;
++
++	writel(val, CLASS_ROUTE_MULTI);
++
++	writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr),
++	       CLASS_ROUTE_TABLE_BASE);
++	writel(CLASS_PE0_RO_DM_ADDR0_VAL,		CLASS_PE0_RO_DM_ADDR0);
++	writel(CLASS_PE0_RO_DM_ADDR1_VAL,		CLASS_PE0_RO_DM_ADDR1);
++	writel(CLASS_PE0_QB_DM_ADDR0_VAL,		CLASS_PE0_QB_DM_ADDR0);
++	writel(CLASS_PE0_QB_DM_ADDR1_VAL,		CLASS_PE0_QB_DM_ADDR1);
++	writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),	CLASS_TM_INQ_ADDR);
++
++	writel(23, CLASS_AFULL_THRES);
++	writel(23, CLASS_TSQ_FIFO_THRES);
++
++	writel(24, CLASS_MAX_BUF_CNT);
++	writel(24, CLASS_TSQ_MAX_CNT);
++}
++
++/**************************** TMU ***************************/
++
++void tmu_reset(void)
++{
++	writel(SW_RESET, TMU_CTRL);
++}
++
++/* Initializes TMU block.
++ * @param[in] cfg	TMU configuration
++ */
++void tmu_init(struct tmu_cfg *cfg)
++{
++	int q, phyno;
++
++	tmu_disable(0xF);
++	mdelay(10);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++	/* keep in soft reset */
++	writel(SW_RESET, TMU_CTRL);
++#endif
++	writel(0x3, TMU_SYS_GENERIC_CONTROL);
++	writel(750, TMU_INQ_WATERMARK);
++	writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR +
++		GPI_INQ_PKTPTR),	TMU_PHY0_INQ_ADDR);
++	writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR +
++		GPI_INQ_PKTPTR),	TMU_PHY1_INQ_ADDR);
++	writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR +
++		GPI_INQ_PKTPTR),	TMU_PHY3_INQ_ADDR);
++	writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
++	writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
++	writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
++	       TMU_BMU_INQ_ADDR);
++
++	writel(0x3FF,	TMU_TDQ0_SCH_CTRL);	/*
++						 * enabling all 10
++						 * schedulers [9:0] of each TDQ
++						 */
++	writel(0x3FF,	TMU_TDQ1_SCH_CTRL);
++	writel(0x3FF,	TMU_TDQ3_SCH_CTRL);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++	writel(cfg->pe_sys_clk_ratio,	TMU_PE_SYS_CLK_RATIO);
++#endif
++
++#if !defined(LS1012A_PFE_RESET_WA)
++	writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr),	TMU_LLM_BASE_ADDR);
++	/* Extra packet pointers will be stored from this address onwards */
++
++	writel(cfg->llm_queue_len,	TMU_LLM_QUE_LEN);
++	writel(5,			TMU_TDQ_IIFG_CFG);
++	writel(DDR_BUF_SIZE,		TMU_BMU_BUF_SIZE);
++
++	writel(0x0,			TMU_CTRL);
++
++	/* MEM init */
++	pr_info("%s: mem init\n", __func__);
++	writel(MEM_INIT,	TMU_CTRL);
++
++	while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
++		;
++
++	/* LLM init */
++	pr_info("%s: lmem init\n", __func__);
++	writel(LLM_INIT,	TMU_CTRL);
++
++	while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
++		;
++#endif
++	/* set up each queue for tail drop */
++	for (phyno = 0; phyno < 4; phyno++) {
++		if (phyno == 2)
++			continue;
++		for (q = 0; q < 16; q++) {
++			u32 qdepth;
++
++			writel((phyno << 8) | q, TMU_TEQ_CTRL);
++			writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */
++
++			if (phyno == 3)
++				qdepth = DEFAULT_TMU3_QDEPTH;
++			else
++				qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH :
++						DEFAULT_MAX_QDEPTH;
++
++			/* LOG: 68855 */
++			/*
++			 * The following is a workaround for the reordered
++			 * packet and BMU2 buffer leakage issue.
++			 */
++			if (CHIP_REVISION() == 0)
++				qdepth = 31;
++
++			writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2);
++			writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3);
++		}
++	}
++
++#ifdef CFG_LRO
++	/* Set TMU-3 queue 5 (LRO) in no-drop mode */
++	writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL);
++	writel(0, TMU_TEQ_QCFG);
++#endif
++
++	writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
++
++	writel(0x0, TMU_CTRL);
++}
++
++/* Enables TMU-PE cores.
++ * @param[in] pe_mask	TMU PE mask
++ */
++void tmu_enable(u32 pe_mask)
++{
++	writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/* Disables TMU cores.
++ * @param[in] pe_mask	TMU PE mask
++ */
++void tmu_disable(u32 pe_mask)
++{
++	writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/* This will return the tmu queue status
++ * @param[in] if_id	gem interface id or TMU index
++ * @return		returns the bit mask of busy queues, zero means all
++ * queues are empty
++ */
++u32 tmu_qstatus(u32 if_id)
++{
++	return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
++		offsetof(struct pe_status, tmu_qstatus), 4));
++}
++
++u32 tmu_pkts_processed(u32 if_id)
++{
++	return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
++		offsetof(struct pe_status, rx), 4));
++}
++
++/**************************** UTIL ***************************/
++
++/* Resets UTIL block.
++ */
++void util_reset(void)
++{
++	writel(CORE_SW_RESET, UTIL_TX_CTRL);
++}
++
++/* Initializes UTIL block.
++ * @param[in] cfg	UTIL configuration
++ */
++void util_init(struct util_cfg *cfg)
++{
++	writel(cfg->pe_sys_clk_ratio,   UTIL_PE_SYS_CLK_RATIO);
++}
++
++/* Enables UTIL-PE core.
++ *
++ */
++void util_enable(void)
++{
++	writel(CORE_ENABLE, UTIL_TX_CTRL);
++}
++
++/* Disables UTIL-PE core.
++ *
++ */
++void util_disable(void)
++{
++	writel(CORE_DISABLE, UTIL_TX_CTRL);
++}
++
++/**************************** HIF ***************************/
++/* Initializes HIF copy block.
++ *
++ */
++void hif_init(void)
++{
++	/*Initialize HIF registers*/
++	writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,
++	       HIF_POLL_CTRL);
++}
++
++/* Enable hif tx DMA and interrupt
++ *
++ */
++void hif_tx_enable(void)
++{
++	writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
++	writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),
++	       HIF_INT_ENABLE);
++}
++
++/* Disable hif tx DMA and interrupt
++ *
++ */
++void hif_tx_disable(void)
++{
++	u32	hif_int;
++
++	writel(0, HIF_TX_CTRL);
++
++	hif_int = readl(HIF_INT_ENABLE);
++	hif_int &= HIF_TXPKT_INT_EN;
++	writel(hif_int, HIF_INT_ENABLE);
++}
++
++/* Enable hif rx DMA and interrupt
++ *
++ */
++void hif_rx_enable(void)
++{
++	hif_rx_dma_start();
++	writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),
++	       HIF_INT_ENABLE);
++}
++
++/* Disable hif rx DMA and interrupt
++ *
++ */
++void hif_rx_disable(void)
++{
++	u32	hif_int;
++
++	writel(0, HIF_RX_CTRL);
++
++	hif_int = readl(HIF_INT_ENABLE);
++	hif_int &= HIF_RXPKT_INT_EN;
++	writel(hif_int, HIF_INT_ENABLE);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.c
+@@ -0,0 +1,1063 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++
++#include <linux/io.h>
++#include <asm/irq.h>
++
++#include "pfe_mod.h"
++
++#define HIF_INT_MASK	(HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT)
++
++unsigned char napi_first_batch;
++
++static void pfe_tx_do_cleanup(unsigned long data);
++
++static int pfe_hif_alloc_descr(struct pfe_hif *hif)
++{
++	void *addr;
++	dma_addr_t dma_addr;
++	int err = 0;
++
++	pr_info("%s\n", __func__);
++	addr = dma_alloc_coherent(pfe->dev,
++				  HIF_RX_DESC_NT * sizeof(struct hif_desc) +
++				  HIF_TX_DESC_NT * sizeof(struct hif_desc),
++				  &dma_addr, GFP_KERNEL);
++
++	if (!addr) {
++		pr_err("%s: Could not allocate buffer descriptors!\n"
++			, __func__);
++		err = -ENOMEM;
++		goto err0;
++	}
++
++	hif->descr_baseaddr_p = dma_addr;
++	hif->descr_baseaddr_v = addr;
++	hif->rx_ring_size = HIF_RX_DESC_NT;
++	hif->tx_ring_size = HIF_TX_DESC_NT;
++
++	return 0;
++
++err0:
++	return err;
++}
++
++#if defined(LS1012A_PFE_RESET_WA)
++static void pfe_hif_disable_rx_desc(struct pfe_hif *hif)
++{
++	int ii;
++	struct hif_desc	*desc = hif->rx_base;
++
++	/*Mark all descriptors as LAST_BD */
++	for (ii = 0; ii < hif->rx_ring_size; ii++) {
++		desc->ctrl |= BD_CTRL_LAST_BD;
++		desc++;
++	}
++}
++
++struct class_rx_hdr_t {
++	u32     next_ptr;       /* ptr to the start of the first DDR buffer */
++	u16     length;         /* total packet length */
++	u16     phyno;          /* input physical port number */
++	u32     status;         /* gemac status bits */
++	u32     status2;            /* reserved for software usage */
++};
++
++/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled)
++ * except overflow
++ */
++#define STATUS_BAD_FRAME_ERR            BIT(16)
++#define STATUS_LENGTH_ERR               BIT(17)
++#define STATUS_CRC_ERR                  BIT(18)
++#define STATUS_TOO_SHORT_ERR            BIT(19)
++#define STATUS_TOO_LONG_ERR             BIT(20)
++#define STATUS_CODE_ERR                 BIT(21)
++#define STATUS_MC_HASH_MATCH            BIT(22)
++#define STATUS_CUMULATIVE_ARC_HIT       BIT(23)
++#define STATUS_UNICAST_HASH_MATCH       BIT(24)
++#define STATUS_IP_CHECKSUM_CORRECT      BIT(25)
++#define STATUS_TCP_CHECKSUM_CORRECT     BIT(26)
++#define STATUS_UDP_CHECKSUM_CORRECT     BIT(27)
++#define STATUS_OVERFLOW_ERR             BIT(28) /* GPI error */
++#define MIN_PKT_SIZE			64
++
++static inline void copy_to_lmem(u32 *dst, u32 *src, int len)
++{
++	int i;
++
++	for (i = 0; i < len; i += sizeof(u32))	{
++		*dst = htonl(*src);
++		dst++; src++;
++	}
++}
++
++static void send_dummy_pkt_to_hif(void)
++{
++	void *lmem_ptr, *ddr_ptr, *lmem_virt_addr;
++	u32 physaddr;
++	struct class_rx_hdr_t local_hdr;
++	static u32 dummy_pkt[] =  {
++		0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
++		0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
++		0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
++		0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
++
++	ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
++	if (!ddr_ptr)
++		return;
++
++	lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
++	if (!lmem_ptr)
++		return;
++
++	pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr);
++	physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr);
++
++	lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr);
++
++	local_hdr.phyno = htons(0); /* RX_PHY_0 */
++	local_hdr.length = htons(MIN_PKT_SIZE);
++
++	local_hdr.next_ptr = htonl((u32)physaddr);
++	/*Mark checksum is correct */
++	local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT |
++				STATUS_UDP_CHECKSUM_CORRECT |
++				STATUS_TCP_CHECKSUM_CORRECT |
++				STATUS_UNICAST_HASH_MATCH |
++				STATUS_CUMULATIVE_ARC_HIT));
++	local_hdr.status2 = 0;
++
++	copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr,
++		     sizeof(local_hdr));
++
++	copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt,
++		     0x40);
++
++	writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR);
++}
++
++void pfe_hif_rx_idle(struct pfe_hif *hif)
++{
++	int hif_stop_loop = 10;
++	u32 rx_status;
++
++	pfe_hif_disable_rx_desc(hif);
++	pr_info("Bringing hif to idle state...");
++	writel(0, HIF_INT_ENABLE);
++	/*If HIF Rx BDP is busy send a dummy packet */
++	do {
++		rx_status = readl(HIF_RX_STATUS);
++		if (rx_status & BDP_CSR_RX_DMA_ACTV)
++			send_dummy_pkt_to_hif();
++
++		usleep_range(100, 150);
++	} while (--hif_stop_loop);
++
++	if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
++		pr_info("Failed\n");
++	else
++		pr_info("Done\n");
++}
++#endif
++
++static void pfe_hif_free_descr(struct pfe_hif *hif)
++{
++	pr_info("%s\n", __func__);
++
++	dma_free_coherent(pfe->dev,
++			  hif->rx_ring_size * sizeof(struct hif_desc) +
++			  hif->tx_ring_size * sizeof(struct hif_desc),
++			  hif->descr_baseaddr_v, hif->descr_baseaddr_p);
++}
++
++void pfe_hif_desc_dump(struct pfe_hif *hif)
++{
++	struct hif_desc	*desc;
++	unsigned long desc_p;
++	int ii = 0;
++
++	pr_info("%s\n", __func__);
++
++	desc = hif->rx_base;
++	desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
++			hif->descr_baseaddr_p);
++
++	pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p);
++	for (ii = 0; ii < hif->rx_ring_size; ii++) {
++		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++			readl(&desc->status), readl(&desc->ctrl),
++			readl(&desc->data), readl(&desc->next));
++			desc++;
++	}
++
++	desc = hif->tx_base;
++	desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
++			hif->descr_baseaddr_p);
++
++	pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p);
++	for (ii = 0; ii < hif->tx_ring_size; ii++) {
++		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++			readl(&desc->status), readl(&desc->ctrl),
++			readl(&desc->data), readl(&desc->next));
++		desc++;
++	}
++}
++
++/* pfe_hif_release_buffers */
++static void pfe_hif_release_buffers(struct pfe_hif *hif)
++{
++	struct hif_desc	*desc;
++	int i = 0;
++
++	hif->rx_base = hif->descr_baseaddr_v;
++
++	pr_info("%s\n", __func__);
++
++	/*Free Rx buffers */
++	desc = hif->rx_base;
++	for (i = 0; i < hif->rx_ring_size; i++) {
++		if (readl(&desc->data)) {
++			if ((i < hif->shm->rx_buf_pool_cnt) &&
++			    (!hif->shm->rx_buf_pool[i])) {
++				/*
++				 * dma_unmap_single(hif->dev, desc->data,
++				 * hif->rx_buf_len[i], DMA_FROM_DEVICE);
++				 */
++				dma_unmap_single(hif->dev,
++						 DDR_PFE_TO_PHYS(
++						 readl(&desc->data)),
++						 hif->rx_buf_len[i],
++						 DMA_FROM_DEVICE);
++				hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i];
++			} else {
++				pr_err("%s: buffer pool already full\n"
++					, __func__);
++			}
++		}
++
++		writel(0, &desc->data);
++		writel(0, &desc->status);
++		writel(0, &desc->ctrl);
++		desc++;
++	}
++}
++
++/*
++ * pfe_hif_init_buffers
++ * This function initializes the HIF Rx/Tx ring descriptors and
++ * initialize Rx queue with buffers.
++ */
++static int pfe_hif_init_buffers(struct pfe_hif *hif)
++{
++	struct hif_desc	*desc, *first_desc_p;
++	u32 data;
++	int i = 0;
++
++	pr_info("%s\n", __func__);
++
++	/* Check enough Rx buffers available in the shared memory */
++	if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size)
++		return -ENOMEM;
++
++	hif->rx_base = hif->descr_baseaddr_v;
++	memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc));
++
++	/*Initialize Rx descriptors */
++	desc = hif->rx_base;
++	first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;
++
++	for (i = 0; i < hif->rx_ring_size; i++) {
++		/* Initialize Rx buffers from the shared memory */
++
++		data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i],
++				pfe_pkt_size, DMA_FROM_DEVICE);
++		hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i];
++		hif->rx_buf_len[i] = pfe_pkt_size;
++		hif->shm->rx_buf_pool[i] = NULL;
++
++		if (likely(dma_mapping_error(hif->dev, data) == 0)) {
++			writel(DDR_PHYS_TO_PFE(data), &desc->data);
++		} else {
++			pr_err("%s : low on mem\n",  __func__);
++
++			goto err;
++		}
++
++		writel(0, &desc->status);
++
++		/*
++		 * Ensure everything else is written to DDR before
++		 * writing bd->ctrl
++		 */
++		wmb();
++
++		writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM
++			| BD_CTRL_DIR | BD_CTRL_DESC_EN
++			| BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl);
++
++		/* Chain descriptors */
++		writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
++		desc++;
++	}
++
++	/* Overwrite last descriptor to chain it to first one*/
++	desc--;
++	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
++
++	hif->rxtoclean_index = 0;
++
++	/*Initialize Rx buffer descriptor ring base address */
++	writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);
++
++	hif->tx_base = hif->rx_base + hif->rx_ring_size;
++	first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p +
++				hif->rx_ring_size;
++	memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc));
++
++	/*Initialize tx descriptors */
++	desc = hif->tx_base;
++
++	for (i = 0; i < hif->tx_ring_size; i++) {
++		/* Chain descriptors */
++		writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
++		writel(0, &desc->ctrl);
++		desc++;
++	}
++
++	/* Overwrite last descriptor to chain it to first one */
++	desc--;
++	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
++	hif->txavail = hif->tx_ring_size;
++	hif->txtosend = 0;
++	hif->txtoclean = 0;
++	hif->txtoflush = 0;
++
++	/*Initialize Tx buffer descriptor ring base address */
++	writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);
++
++	return 0;
++
++err:
++	pfe_hif_release_buffers(hif);
++	return -ENOMEM;
++}
++
++/*
++ * pfe_hif_client_register
++ *
++ * This function used to register a client driver with the HIF driver.
++ *
++ * Return value:
++ * 0 - on Successful registration
++ */
++static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id,
++				   struct hif_client_shm *client_shm)
++{
++	struct hif_client *client = &hif->client[client_id];
++	u32 i, cnt;
++	struct rx_queue_desc *rx_qbase;
++	struct tx_queue_desc *tx_qbase;
++	struct hif_rx_queue *rx_queue;
++	struct hif_tx_queue *tx_queue;
++	int err = 0;
++
++	pr_info("%s\n", __func__);
++
++	spin_lock_bh(&hif->tx_lock);
++
++	if (test_bit(client_id, &hif->shm->g_client_status[0])) {
++		pr_err("%s: client %d already registered\n",
++		       __func__, client_id);
++		err = -1;
++		goto unlock;
++	}
++
++	memset(client, 0, sizeof(struct hif_client));
++
++	/* Initialize client Rx queues baseaddr, size */
++
++	cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl);
++	/* Check if client is requesting for more queues than supported */
++	if (cnt > HIF_CLIENT_QUEUES_MAX)
++		cnt = HIF_CLIENT_QUEUES_MAX;
++
++	client->rx_qn = cnt;
++	rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase;
++	for (i = 0; i < cnt; i++) {
++		rx_queue = &client->rx_q[i];
++		rx_queue->base = rx_qbase + i * client_shm->rx_qsize;
++		rx_queue->size = client_shm->rx_qsize;
++		rx_queue->write_idx = 0;
++	}
++
++	/* Initialize client Tx queues baseaddr, size */
++	cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl);
++
++	/* Check if client is requesting for more queues than supported */
++	if (cnt > HIF_CLIENT_QUEUES_MAX)
++		cnt = HIF_CLIENT_QUEUES_MAX;
++
++	client->tx_qn = cnt;
++	tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase;
++	for (i = 0; i < cnt; i++) {
++		tx_queue = &client->tx_q[i];
++		tx_queue->base = tx_qbase + i * client_shm->tx_qsize;
++		tx_queue->size = client_shm->tx_qsize;
++		tx_queue->ack_idx = 0;
++	}
++
++	set_bit(client_id, &hif->shm->g_client_status[0]);
++
++unlock:
++	spin_unlock_bh(&hif->tx_lock);
++
++	return err;
++}
++
++/*
++ * pfe_hif_client_unregister
++ *
++ * This function used to unregister a client  from the HIF driver.
++ *
++ */
++static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id)
++{
++	pr_info("%s\n", __func__);
++
++	/*
++	 * Mark client as no longer available (which prevents further packet
++	 * receive for this client)
++	 */
++	spin_lock_bh(&hif->tx_lock);
++
++	if (!test_bit(client_id, &hif->shm->g_client_status[0])) {
++		pr_err("%s: client %d not registered\n", __func__,
++		       client_id);
++
++		spin_unlock_bh(&hif->tx_lock);
++		return;
++	}
++
++	clear_bit(client_id, &hif->shm->g_client_status[0]);
++
++	spin_unlock_bh(&hif->tx_lock);
++}
++
++/*
++ * client_put_rxpacket-
++ * This functions puts the Rx pkt  in the given client Rx queue.
++ * It actually swap the Rx pkt in the client Rx descriptor buffer
++ * and returns the free buffer from it.
++ *
++ * If the function returns NULL means client Rx queue is full and
++ * packet couldn't send to client queue.
++ */
++static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len,
++				 u32 flags, u32 client_ctrl, u32 *rem_len)
++{
++	void *free_pkt = NULL;
++	struct rx_queue_desc *desc = queue->base + queue->write_idx;
++
++	if (readl(&desc->ctrl) & CL_DESC_OWN) {
++		if (page_mode) {
++			int rem_page_size = PAGE_SIZE -
++					PRESENT_OFST_IN_PAGE(pkt);
++			int cur_pkt_size = ROUND_MIN_RX_SIZE(len +
++					pfe_pkt_headroom);
++			*rem_len = (rem_page_size - cur_pkt_size);
++			if (*rem_len) {
++				free_pkt = pkt + cur_pkt_size;
++				get_page(virt_to_page(free_pkt));
++			} else {
++				free_pkt = (void
++				*)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE);
++				*rem_len = pfe_pkt_size;
++			}
++		} else {
++			free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC |
++					GFP_DMA_PFE);
++			*rem_len = PFE_BUF_SIZE - pfe_pkt_headroom;
++		}
++
++		if (free_pkt) {
++			desc->data = pkt;
++			desc->client_ctrl = client_ctrl;
++			/*
++			 * Ensure everything else is written to DDR before
++			 * writing bd->ctrl
++			 */
++			smp_wmb();
++			writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl);
++			queue->write_idx = (queue->write_idx + 1)
++					    & (queue->size - 1);
++
++			free_pkt += pfe_pkt_headroom;
++		}
++	}
++
++	return free_pkt;
++}
++
++/*
++ * pfe_hif_rx_process-
++ * This function does pfe hif rx queue processing.
++ * Dequeue packet from Rx queue and send it to corresponding client queue
++ */
++static int pfe_hif_rx_process(struct pfe_hif *hif, int budget)
++{
++	struct hif_desc	*desc;
++	struct hif_hdr *pkt_hdr;
++	struct __hif_hdr hif_hdr;
++	void *free_buf;
++	int rtc, len, rx_processed = 0;
++	struct __hif_desc local_desc;
++	int flags;
++	unsigned int desc_p;
++	unsigned int buf_size = 0;
++
++	spin_lock_bh(&hif->lock);
++
++	rtc = hif->rxtoclean_index;
++
++	while (rx_processed < budget) {
++		desc = hif->rx_base + rtc;
++
++		__memcpy12(&local_desc, desc);
++
++		/* ACK pending Rx interrupt */
++		if (local_desc.ctrl & BD_CTRL_DESC_EN) {
++			writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC);
++
++			if (rx_processed == 0) {
++				if (napi_first_batch == 1) {
++					desc_p = hif->descr_baseaddr_p +
++					((unsigned long int)(desc) -
++					(unsigned long
++					int)hif->descr_baseaddr_v);
++					napi_first_batch = 0;
++				}
++			}
++
++			__memcpy12(&local_desc, desc);
++
++			if (local_desc.ctrl & BD_CTRL_DESC_EN)
++				break;
++		}
++
++		napi_first_batch = 0;
++
++#ifdef HIF_NAPI_STATS
++		hif->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++		len = BD_BUF_LEN(local_desc.ctrl);
++		/*
++		 * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
++		 * hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++		 */
++		dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
++				 hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++
++		pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc];
++
++		/* Track last HIF header received */
++		if (!hif->started) {
++			hif->started = 1;
++
++			__memcpy8(&hif_hdr, pkt_hdr);
++
++			hif->qno = hif_hdr.hdr.q_num;
++			hif->client_id = hif_hdr.hdr.client_id;
++			hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) |
++						hif_hdr.hdr.client_ctrl;
++			flags = CL_DESC_FIRST;
++
++		} else {
++			flags = 0;
++		}
++
++		if (local_desc.ctrl & BD_CTRL_LIFM)
++			flags |= CL_DESC_LAST;
++
++		/* Check for valid client id and still registered */
++		if ((hif->client_id >= HIF_CLIENTS_MAX) ||
++		    !(test_bit(hif->client_id,
++			&hif->shm->g_client_status[0]))) {
++			printk_ratelimited("%s: packet with invalid client id %d q_num %d\n",
++					   __func__,
++					   hif->client_id,
++					   hif->qno);
++
++			free_buf = pkt_hdr;
++
++			goto pkt_drop;
++		}
++
++		/* Check to valid queue number */
++		if (hif->client[hif->client_id].rx_qn <= hif->qno) {
++			pr_info("%s: packet with invalid queue: %d\n"
++				, __func__, hif->qno);
++			hif->qno = 0;
++		}
++
++		free_buf =
++		client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],
++				    (void *)pkt_hdr, len, flags,
++			hif->client_ctrl, &buf_size);
++
++		hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND,
++					hif->qno);
++
++		if (unlikely(!free_buf)) {
++#ifdef HIF_NAPI_STATS
++			hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++;
++#endif
++			/*
++			 * If we want to keep in polling mode to retry later,
++			 * we need to tell napi that we consumed
++			 * the full budget or we will hit a livelock scenario.
++			 * The core code keeps this napi instance
++			 * at the head of the list and none of the other
++			 * instances get to run
++			 */
++			rx_processed = budget;
++
++			if (flags & CL_DESC_FIRST)
++				hif->started = 0;
++
++			break;
++		}
++
++pkt_drop:
++		/*Fill free buffer in the descriptor */
++		hif->rx_buf_addr[rtc] = free_buf;
++		hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size);
++		writel((DDR_PHYS_TO_PFE
++			((u32)dma_map_single(hif->dev,
++			free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))),
++			&desc->data);
++		/*
++		 * Ensure everything else is written to DDR before
++		 * writing bd->ctrl
++		 */
++		wmb();
++		writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |
++			BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])),
++			&desc->ctrl);
++
++		rtc = (rtc + 1) & (hif->rx_ring_size - 1);
++
++		if (local_desc.ctrl & BD_CTRL_LIFM) {
++			if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) {
++				rx_processed++;
++
++#ifdef HIF_NAPI_STATS
++				hif->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++			}
++			hif->started = 0;
++		}
++	}
++
++	hif->rxtoclean_index = rtc;
++	spin_unlock_bh(&hif->lock);
++
++	/* we made some progress, re-start rx dma in case it stopped */
++	hif_rx_dma_start();
++
++	return rx_processed;
++}
++
++/*
++ * client_ack_txpacket-
++ * This function ack the Tx packet in the give client Tx queue by resetting
++ * ownership bit in the descriptor.
++ */
++static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id,
++			       unsigned int q_no)
++{
++	struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no];
++	struct tx_queue_desc *desc = queue->base + queue->ack_idx;
++
++	if (readl(&desc->ctrl) & CL_DESC_OWN) {
++		writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl);
++		queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1);
++
++		return 0;
++
++	} else {
++		/*This should not happen */
++		pr_err("%s: %d %d %d %d %d %p %d\n", __func__,
++		       hif->txtosend, hif->txtoclean, hif->txavail,
++			client_id, q_no, queue, queue->ack_idx);
++		WARN(1, "%s: doesn't own this descriptor", __func__);
++		return 1;
++	}
++}
++
++void __hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++	struct hif_desc *desc;
++	struct hif_desc_sw *desc_sw;
++	int ttc, tx_avl;
++	int pkts_done[HIF_CLIENTS_MAX] = {0, 0};
++
++	ttc = hif->txtoclean;
++	tx_avl = hif->txavail;
++
++	while ((tx_avl < hif->tx_ring_size) && count--) {
++		desc = hif->tx_base + ttc;
++
++		if (readl(&desc->ctrl) & BD_CTRL_DESC_EN)
++			break;
++
++		desc_sw = &hif->tx_sw_queue[ttc];
++
++		if (desc_sw->data) {
++			/*
++			 * dmap_unmap_single(hif->dev, desc_sw->data,
++			 * desc_sw->len, DMA_TO_DEVICE);
++			 */
++			dma_unmap_single(hif->dev, desc_sw->data,
++					 desc_sw->len, DMA_TO_DEVICE);
++		}
++
++		if (desc_sw->client_id >= HIF_CLIENTS_MAX) {
++			pr_err("Invalid cl id %d\n", desc_sw->client_id);
++			break;
++		}
++
++		pkts_done[desc_sw->client_id]++;
++
++		client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no);
++
++		ttc = (ttc + 1) & (hif->tx_ring_size - 1);
++		tx_avl++;
++	}
++
++	if (pkts_done[0])
++		hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0);
++	if (pkts_done[1])
++		hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0);
++
++	hif->txtoclean = ttc;
++	hif->txavail = tx_avl;
++
++	if (!count) {
++		tasklet_schedule(&hif->tx_cleanup_tasklet);
++	} else {
++		/*Enable Tx done interrupt */
++		writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT,
++		       HIF_INT_ENABLE);
++	}
++}
++
++static void pfe_tx_do_cleanup(unsigned long data)
++{
++	struct pfe_hif *hif = (struct pfe_hif *)data;
++
++	writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC);
++
++	hif_tx_done_process(hif, 64);
++}
++
++/*
++ * __hif_xmit_pkt -
++ * This function puts one packet in the HIF Tx queue
++ */
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
++			q_no, void *data, u32 len, unsigned int flags)
++{
++	struct hif_desc	*desc;
++	struct hif_desc_sw *desc_sw;
++
++	desc = hif->tx_base + hif->txtosend;
++	desc_sw = &hif->tx_sw_queue[hif->txtosend];
++
++	desc_sw->len = len;
++	desc_sw->client_id = client_id;
++	desc_sw->q_no = q_no;
++	desc_sw->flags = flags;
++
++	if (flags & HIF_DONT_DMA_MAP) {
++		desc_sw->data = 0;
++		writel((u32)DDR_PHYS_TO_PFE(data), &desc->data);
++	} else {
++		desc_sw->data = dma_map_single(hif->dev, data, len,
++						DMA_TO_DEVICE);
++		writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data);
++	}
++
++	hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1);
++	hif->txavail--;
++
++	if ((!((flags & HIF_DATA_VALID) && (flags &
++				HIF_LAST_BUFFER))))
++		goto skip_tx;
++
++	/*
++	 * Ensure everything else is written to DDR before
++	 * writing bd->ctrl
++	 */
++	wmb();
++
++	do {
++		desc_sw = &hif->tx_sw_queue[hif->txtoflush];
++		desc = hif->tx_base + hif->txtoflush;
++
++		if (desc_sw->flags & HIF_LAST_BUFFER) {
++			writel((BD_CTRL_LIFM |
++			       BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE
++			       | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN |
++				BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)),
++				&desc->ctrl);
++		} else {
++			writel((BD_CTRL_DESC_EN |
++				BD_BUF_LEN(desc_sw->len)), &desc->ctrl);
++		}
++		hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1);
++	}
++	while (hif->txtoflush != hif->txtosend)
++		;
++
++skip_tx:
++	return;
++}
++
++static irqreturn_t wol_isr(int irq, void *dev_id)
++{
++	pr_info("WoL\n");
++	gemac_set_wol(EMAC1_BASE_ADDR, 0);
++	gemac_set_wol(EMAC2_BASE_ADDR, 0);
++	return IRQ_HANDLED;
++}
++
++/*
++ * hif_isr-
++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
++ */
++static irqreturn_t hif_isr(int irq, void *dev_id)
++{
++	struct pfe_hif *hif = (struct pfe_hif *)dev_id;
++	int int_status;
++	int int_enable_mask;
++
++	/*Read hif interrupt source register */
++	int_status = readl_relaxed(HIF_INT_SRC);
++	int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
++
++	if ((int_status & HIF_INT) == 0)
++		return IRQ_NONE;
++
++	int_status &= ~(HIF_INT);
++
++	if (int_status & HIF_RXPKT_INT) {
++		int_status &= ~(HIF_RXPKT_INT);
++		int_enable_mask &= ~(HIF_RXPKT_INT);
++
++		napi_first_batch = 1;
++
++		if (napi_schedule_prep(&hif->napi)) {
++#ifdef HIF_NAPI_STATS
++			hif->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++			__napi_schedule(&hif->napi);
++		}
++	}
++
++	if (int_status & HIF_TXPKT_INT) {
++		int_status &= ~(HIF_TXPKT_INT);
++		int_enable_mask &= ~(HIF_TXPKT_INT);
++		/*Schedule tx cleanup tassklet */
++		tasklet_schedule(&hif->tx_cleanup_tasklet);
++	}
++
++	/*Disable interrupts, they will be enabled after they are serviced */
++	writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
++
++	if (int_status) {
++		pr_info("%s : Invalid interrupt : %d\n", __func__,
++			int_status);
++		writel(int_status, HIF_INT_SRC);
++	}
++
++	return IRQ_HANDLED;
++}
++
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2)
++{
++	unsigned int client_id = data1;
++
++	if (client_id >= HIF_CLIENTS_MAX) {
++		pr_err("%s: client id %d out of bounds\n", __func__,
++		       client_id);
++		return;
++	}
++
++	switch (req) {
++	case REQUEST_CL_REGISTER:
++			/* Request for register a client */
++			pr_info("%s: register client_id %d\n",
++				__func__, client_id);
++			pfe_hif_client_register(hif, client_id, (struct
++				hif_client_shm *)&hif->shm->client[client_id]);
++			break;
++
++	case REQUEST_CL_UNREGISTER:
++			pr_info("%s: unregister client_id %d\n",
++				__func__, client_id);
++
++			/* Request for unregister a client */
++			pfe_hif_client_unregister(hif, client_id);
++
++			break;
++
++	default:
++			pr_err("%s: unsupported request %d\n",
++			       __func__, req);
++			break;
++	}
++
++	/*
++	 * Process client Tx queues
++	 * Currently we don't have checking for tx pending
++	 */
++}
++
++/*
++ * pfe_hif_rx_poll
++ *  This function is NAPI poll function to process HIF Rx queue.
++ */
++static int pfe_hif_rx_poll(struct napi_struct *napi, int budget)
++{
++	struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi);
++	int work_done;
++
++#ifdef HIF_NAPI_STATS
++	hif->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++	work_done = pfe_hif_rx_process(hif, budget);
++
++	if (work_done < budget) {
++		napi_complete(napi);
++		writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT,
++		       HIF_INT_ENABLE);
++	}
++#ifdef HIF_NAPI_STATS
++	else
++		hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++	return work_done;
++}
++
++/*
++ * pfe_hif_init
++ * This function initializes the baseaddresses and irq, etc.
++ */
++int pfe_hif_init(struct pfe *pfe)
++{
++	struct pfe_hif *hif = &pfe->hif;
++	int err;
++
++	pr_info("%s\n", __func__);
++
++	hif->dev = pfe->dev;
++	hif->irq = pfe->hif_irq;
++
++	err = pfe_hif_alloc_descr(hif);
++	if (err)
++		goto err0;
++
++	if (pfe_hif_init_buffers(hif)) {
++		pr_err("%s: Could not initialize buffer descriptors\n"
++			, __func__);
++		err = -ENOMEM;
++		goto err1;
++	}
++
++	/* Initialize NAPI for Rx processing */
++	init_dummy_netdev(&hif->dummy_dev);
++	netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll);
++	napi_enable(&hif->napi);
++
++	spin_lock_init(&hif->tx_lock);
++	spin_lock_init(&hif->lock);
++
++	hif_init();
++	hif_rx_enable();
++	hif_tx_enable();
++
++	/* Disable tx done interrupt */
++	writel(HIF_INT_MASK, HIF_INT_ENABLE);
++
++	gpi_enable(HGPI_BASE_ADDR);
++
++	err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif);
++	if (err) {
++		pr_err("%s: failed to get the hif IRQ = %d\n",
++		       __func__, hif->irq);
++		goto err1;
++	}
++
++	err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe);
++	if (err) {
++		pr_err("%s: failed to get the wol IRQ = %d\n",
++		       __func__, pfe->wol_irq);
++		goto err1;
++	}
++
++	tasklet_init(&hif->tx_cleanup_tasklet,
++		     (void(*)(unsigned long))pfe_tx_do_cleanup,
++		     (unsigned long)hif);
++
++	return 0;
++err1:
++	pfe_hif_free_descr(hif);
++err0:
++	return err;
++}
++
++/* pfe_hif_exit- */
++void pfe_hif_exit(struct pfe *pfe)
++{
++	struct pfe_hif *hif = &pfe->hif;
++
++	pr_info("%s\n", __func__);
++
++	tasklet_kill(&hif->tx_cleanup_tasklet);
++
++	spin_lock_bh(&hif->lock);
++	hif->shm->g_client_status[0] = 0;
++	/* Make sure all clients are disabled*/
++	hif->shm->g_client_status[1] = 0;
++
++	spin_unlock_bh(&hif->lock);
++
++	/*Disable Rx/Tx */
++	gpi_disable(HGPI_BASE_ADDR);
++	hif_rx_disable();
++	hif_tx_disable();
++
++	napi_disable(&hif->napi);
++	netif_napi_del(&hif->napi);
++
++	free_irq(pfe->wol_irq, pfe);
++	free_irq(hif->irq, hif);
++
++	pfe_hif_release_buffers(hif);
++	pfe_hif_free_descr(hif);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.h
+@@ -0,0 +1,199 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HIF_H_
++#define _PFE_HIF_H_
++
++#include <linux/netdevice.h>
++
++#define HIF_NAPI_STATS
++
++#define HIF_CLIENT_QUEUES_MAX	16
++#define HIF_RX_POLL_WEIGHT	64
++
++#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */
++#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)
++#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \
++					& HIF_RX_PKT_MIN_SIZE_MASK)
++#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \
++					- 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
++
++enum {
++	NAPI_SCHED_COUNT = 0,
++	NAPI_POLL_COUNT,
++	NAPI_PACKET_COUNT,
++	NAPI_DESC_COUNT,
++	NAPI_FULL_BUDGET_COUNT,
++	NAPI_CLIENT_FULL_COUNT,
++	NAPI_MAX_COUNT
++};
++
++/*
++ * HIF_TX_DESC_NT value should be always greter than 4,
++ * Otherwise HIF_TX_POLL_MARK will become zero.
++ */
++#define HIF_RX_DESC_NT		256
++#define HIF_TX_DESC_NT		2048
++
++#define HIF_FIRST_BUFFER	BIT(0)
++#define HIF_LAST_BUFFER		BIT(1)
++#define HIF_DONT_DMA_MAP	BIT(2)
++#define HIF_DATA_VALID		BIT(3)
++#define HIF_TSO			BIT(4)
++
++enum {
++	PFE_CL_GEM0 = 0,
++	PFE_CL_GEM1,
++	HIF_CLIENTS_MAX
++};
++
++/*structure to store client queue info */
++struct hif_rx_queue {
++	struct rx_queue_desc *base;
++	u32	size;
++	u32	write_idx;
++};
++
++struct hif_tx_queue {
++	struct tx_queue_desc *base;
++	u32	size;
++	u32	ack_idx;
++};
++
++/*Structure to store the client info */
++struct hif_client {
++	int	rx_qn;
++	struct hif_rx_queue	rx_q[HIF_CLIENT_QUEUES_MAX];
++	int	tx_qn;
++	struct hif_tx_queue	tx_q[HIF_CLIENT_QUEUES_MAX];
++};
++
++/*HIF hardware buffer descriptor */
++struct hif_desc {
++	u32 ctrl;
++	u32 status;
++	u32 data;
++	u32 next;
++};
++
++struct __hif_desc {
++	u32 ctrl;
++	u32 status;
++	u32 data;
++};
++
++struct hif_desc_sw {
++	dma_addr_t data;
++	u16 len;
++	u8 client_id;
++	u8 q_no;
++	u16 flags;
++};
++
++struct hif_hdr {
++	u8 client_id;
++	u8 q_num;
++	u16 client_ctrl;
++	u16 client_ctrl1;
++};
++
++struct __hif_hdr {
++	union {
++		struct hif_hdr hdr;
++		u32 word[2];
++	};
++};
++
++struct hif_ipsec_hdr {
++	u16	sa_handle[2];
++} __packed;
++
++/*  HIF_CTRL_TX... defines */
++#define HIF_CTRL_TX_CHECKSUM		BIT(2)
++
++/*  HIF_CTRL_RX... defines */
++#define HIF_CTRL_RX_OFFSET_OFST         (24)
++#define HIF_CTRL_RX_CHECKSUMMED		BIT(2)
++#define HIF_CTRL_RX_CONTINUED		BIT(1)
++
++struct pfe_hif {
++	/* To store registered clients in hif layer */
++	struct hif_client client[HIF_CLIENTS_MAX];
++	struct hif_shm *shm;
++	int	irq;
++
++	void	*descr_baseaddr_v;
++	unsigned long	descr_baseaddr_p;
++
++	struct hif_desc *rx_base;
++	u32	rx_ring_size;
++	u32	rxtoclean_index;
++	void	*rx_buf_addr[HIF_RX_DESC_NT];
++	int	rx_buf_len[HIF_RX_DESC_NT];
++	unsigned int qno;
++	unsigned int client_id;
++	unsigned int client_ctrl;
++	unsigned int started;
++
++	struct hif_desc *tx_base;
++	u32	tx_ring_size;
++	u32	txtosend;
++	u32	txtoclean;
++	u32	txavail;
++	u32	txtoflush;
++	struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];
++
++/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */
++	spinlock_t tx_lock;
++/* lock synchronizes hif rx queue processing */
++	spinlock_t lock;
++	struct net_device	dummy_dev;
++	struct napi_struct	napi;
++	struct device *dev;
++
++#ifdef HIF_NAPI_STATS
++	unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++	struct tasklet_struct	tx_cleanup_tasklet;
++};
++
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
++			q_no, void *data, u32 len, unsigned int flags);
++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no,
++		 void *data, unsigned int len);
++void __hif_tx_done_process(struct pfe_hif *hif, int count);
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int
++				data2);
++int pfe_hif_init(struct pfe *pfe);
++void pfe_hif_exit(struct pfe *pfe);
++void pfe_hif_rx_idle(struct pfe_hif *hif);
++static inline void hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++	spin_lock_bh(&hif->tx_lock);
++	__hif_tx_done_process(hif, count);
++	spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_lock(struct pfe_hif *hif)
++{
++	spin_lock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_unlock(struct pfe_hif *hif)
++{
++	spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline int __hif_tx_avail(struct pfe_hif *hif)
++{
++	return hif->txavail;
++}
++
++#define __memcpy8(dst, src)		memcpy(dst, src, 8)
++#define __memcpy12(dst, src)		memcpy(dst, src, 12)
++#define __memcpy(dst, src, len)		memcpy(dst, src, len)
++
++#endif /* _PFE_HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
+@@ -0,0 +1,628 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/workqueue.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/skbuff.h>
++#include <linux/moduleparam.h>
++#include <linux/cpu.h>
++
++#include "pfe_mod.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++
++unsigned int lro_mode;
++unsigned int page_mode;
++unsigned int tx_qos = 1;
++module_param(tx_qos, uint, 0444);
++MODULE_PARM_DESC(tx_qos, "0: disable ,\n"
++			 "1: enable (default), guarantee no packet drop at TMU level\n");
++unsigned int pfe_pkt_size;
++unsigned int pfe_pkt_headroom;
++unsigned int emac_txq_cnt;
++
++/*
++ * @pfe_hal_lib.c.
++ * Common functions used by HIF client drivers
++ */
++
++/*HIF shared memory Global variable */
++struct hif_shm ghif_shm;
++
++/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.
++ * This function should be called after pfe_hif_exit
++ *
++ * @param[in] hif_shm		Shared memory address location in DDR
++ */
++static void pfe_hif_shm_clean(struct hif_shm *hif_shm)
++{
++	int i;
++	void *pkt;
++
++	for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++		pkt = hif_shm->rx_buf_pool[i];
++		if (pkt) {
++			hif_shm->rx_buf_pool[i] = NULL;
++			pkt -= pfe_pkt_headroom;
++
++			if (page_mode)
++				put_page(virt_to_page(pkt));
++			else
++				kfree(pkt);
++		}
++	}
++}
++
++/* Initialize shared memory used between HIF driver and clients,
++ * allocate rx_buffer_pool required for HIF Rx descriptors.
++ * This function should be called before initializing HIF driver.
++ *
++ * @param[in] hif_shm		Shared memory address location in DDR
++ * @rerurn			0 - on succes, <0 on fail to initialize
++ */
++static int pfe_hif_shm_init(struct hif_shm *hif_shm)
++{
++	int i;
++	void *pkt;
++
++	memset(hif_shm, 0, sizeof(struct hif_shm));
++	hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;
++
++	for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++		if (page_mode) {
++			pkt = (void *)__get_free_page(GFP_KERNEL |
++				GFP_DMA_PFE);
++		} else {
++			pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE);
++		}
++
++		if (pkt)
++			hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom;
++		else
++			goto err0;
++	}
++
++	return 0;
++
++err0:
++	pr_err("%s Low memory\n", __func__);
++	pfe_hif_shm_clean(hif_shm);
++	return -ENOMEM;
++}
++
++/*This function sends indication to HIF driver
++ *
++ * @param[in] hif	hif context
++ */
++static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int
++					data2)
++{
++	hif_process_client_req(hif, req, data1, data2);
++}
++
++void hif_lib_indicate_client(int client_id, int event_type, int qno)
++{
++	struct hif_client_s *client = pfe->hif_client[client_id];
++
++	if (!client || (event_type >= HIF_EVENT_MAX) || (qno >=
++		HIF_CLIENT_QUEUES_MAX))
++		return;
++
++	if (!test_and_set_bit(qno, &client->queue_mask[event_type]))
++		client->event_handler(client->priv, event_type, qno);
++}
++
++/*This function releases Rx queue descriptors memory and pre-filled buffers
++ *
++ * @param[in] client	hif_client context
++ */
++static void hif_lib_client_release_rx_buffers(struct hif_client_s *client)
++{
++	struct rx_queue_desc *desc;
++	int qno, ii;
++	void *buf;
++
++	for (qno = 0; qno < client->rx_qn; qno++) {
++		desc = client->rx_q[qno].base;
++
++		for (ii = 0; ii < client->rx_q[qno].size; ii++) {
++			buf = (void *)desc->data;
++			if (buf) {
++				buf -= pfe_pkt_headroom;
++
++				if (page_mode)
++					free_page((unsigned long)buf);
++				else
++					kfree(buf);
++
++				desc->ctrl = 0;
++			}
++
++			desc++;
++		}
++	}
++
++	kfree(client->rx_qbase);
++}
++
++/*This function allocates memory for the rxq descriptors and pre-fill rx queues
++ * with buffers.
++ * @param[in] client	client context
++ * @param[in] q_size	size of the rxQ, all queues are of same size
++ */
++static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int
++						q_size)
++{
++	struct rx_queue_desc *desc;
++	struct hif_client_rx_queue *queue;
++	int ii, qno;
++
++	/*Allocate memory for the client queues */
++	client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct
++				rx_queue_desc), GFP_KERNEL);
++	if (!client->rx_qbase)
++		goto err;
++
++	for (qno = 0; qno < client->rx_qn; qno++) {
++		queue = &client->rx_q[qno];
++
++		queue->base = client->rx_qbase + qno * q_size * sizeof(struct
++				rx_queue_desc);
++		queue->size = q_size;
++		queue->read_idx = 0;
++		queue->write_idx = 0;
++
++		pr_debug("rx queue: %d, base: %p, size: %d\n", qno,
++			 queue->base, queue->size);
++	}
++
++	for (qno = 0; qno < client->rx_qn; qno++) {
++		queue = &client->rx_q[qno];
++		desc = queue->base;
++
++		for (ii = 0; ii < queue->size; ii++) {
++			desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) |
++					CL_DESC_OWN;
++			desc++;
++		}
++	}
++
++	return 0;
++
++err:
++	return 1;
++}
++
++
++static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue)
++{
++	pr_debug("%s\n", __func__);
++
++	/*
++	 * Check if there are any pending packets. Client must flush the tx
++	 * queues before unregistering, by calling by calling
++	 * hif_lib_tx_get_next_complete()
++	 *
++	 * Hif no longer calls since we are no longer registered
++	 */
++	if (queue->tx_pending)
++		pr_err("%s: pending transmit packets\n", __func__);
++}
++
++static void hif_lib_client_release_tx_buffers(struct hif_client_s *client)
++{
++	int qno;
++
++	pr_debug("%s\n", __func__);
++
++	for (qno = 0; qno < client->tx_qn; qno++)
++		hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]);
++
++	kfree(client->tx_qbase);
++}
++
++static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int
++						q_size)
++{
++	struct hif_client_tx_queue *queue;
++	int qno;
++
++	client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct
++					tx_queue_desc), GFP_KERNEL);
++	if (!client->tx_qbase)
++		return 1;
++
++	for (qno = 0; qno < client->tx_qn; qno++) {
++		queue = &client->tx_q[qno];
++
++		queue->base = client->tx_qbase + qno * q_size * sizeof(struct
++				tx_queue_desc);
++		queue->size = q_size;
++		queue->read_idx = 0;
++		queue->write_idx = 0;
++		queue->tx_pending = 0;
++		queue->nocpy_flag = 0;
++		queue->prev_tmu_tx_pkts = 0;
++		queue->done_tmu_tx_pkts = 0;
++
++		pr_debug("tx queue: %d, base: %p, size: %d\n", qno,
++			 queue->base, queue->size);
++	}
++
++	return 0;
++}
++
++static int hif_lib_event_dummy(void *priv, int event_type, int qno)
++{
++	return 0;
++}
++
++int hif_lib_client_register(struct hif_client_s *client)
++{
++	struct hif_shm *hif_shm;
++	struct hif_client_shm *client_shm;
++	int err, i;
++	/* int loop_cnt = 0; */
++
++	pr_debug("%s\n", __func__);
++
++	/*Allocate memory before spin_lock*/
++	if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) {
++		err = -ENOMEM;
++		goto err_rx;
++	}
++
++	if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) {
++		err = -ENOMEM;
++		goto err_tx;
++	}
++
++	spin_lock_bh(&pfe->hif.lock);
++	if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) ||
++	    (pfe->hif_client[client->id])) {
++		err = -EINVAL;
++		goto err;
++	}
++
++	hif_shm = client->pfe->hif.shm;
++
++	if (!client->event_handler)
++		client->event_handler = hif_lib_event_dummy;
++
++	/*Initialize client specific shared memory */
++	client_shm = (struct hif_client_shm *)&hif_shm->client[client->id];
++	client_shm->rx_qbase = (unsigned long int)client->rx_qbase;
++	client_shm->rx_qsize = client->rx_qsize;
++	client_shm->tx_qbase = (unsigned long int)client->tx_qbase;
++	client_shm->tx_qsize = client->tx_qsize;
++	client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) |
++				(client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST);
++	/* spin_lock_init(&client->rx_lock); */
++
++	for (i = 0; i < HIF_EVENT_MAX; i++) {
++		client->queue_mask[i] = 0;  /*
++					     * By default all events are
++					     * unmasked
++					     */
++	}
++
++	/*Indicate to HIF driver*/
++	hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0);
++
++	pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n",
++		 __func__, client, client->id, client->tx_qsize,
++		 client->rx_qsize);
++
++	client->cpu_id = -1;
++
++	pfe->hif_client[client->id] = client;
++	spin_unlock_bh(&pfe->hif.lock);
++
++	return 0;
++
++err:
++	spin_unlock_bh(&pfe->hif.lock);
++	hif_lib_client_release_tx_buffers(client);
++
++err_tx:
++	hif_lib_client_release_rx_buffers(client);
++
++err_rx:
++	return err;
++}
++
++int hif_lib_client_unregister(struct hif_client_s *client)
++{
++	struct pfe *pfe = client->pfe;
++	u32 client_id = client->id;
++
++	pr_info(
++		"%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n"
++		, __func__, client, client->id, client->tx_qsize,
++		client->rx_qsize);
++
++	spin_lock_bh(&pfe->hif.lock);
++	hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0);
++
++	hif_lib_client_release_tx_buffers(client);
++	hif_lib_client_release_rx_buffers(client);
++	pfe->hif_client[client_id] = NULL;
++	spin_unlock_bh(&pfe->hif.lock);
++
++	return 0;
++}
++
++int hif_lib_event_handler_start(struct hif_client_s *client, int event,
++				int qno)
++{
++	struct hif_client_rx_queue *queue = &client->rx_q[qno];
++	struct rx_queue_desc *desc = queue->base + queue->read_idx;
++
++	if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) {
++		pr_debug("%s: Unsupported event : %d  queue number : %d\n",
++			 __func__, event, qno);
++		return -1;
++	}
++
++	test_and_clear_bit(qno, &client->queue_mask[event]);
++
++	switch (event) {
++	case EVENT_RX_PKT_IND:
++		if (!(desc->ctrl & CL_DESC_OWN))
++			hif_lib_indicate_client(client->id,
++						EVENT_RX_PKT_IND, qno);
++		break;
++
++	case EVENT_HIGH_RX_WM:
++	case EVENT_TXDONE_IND:
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++/*
++ * This function gets one packet from the specified client queue
++ * It also refill the rx buffer
++ */
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
++				*ofst, unsigned int *rx_ctrl,
++				unsigned int *desc_ctrl, void **priv_data)
++{
++	struct hif_client_rx_queue *queue = &client->rx_q[qno];
++	struct rx_queue_desc *desc;
++	void *pkt = NULL;
++
++	/*
++	 * Following lock is to protect rx queue access from,
++	 * hif_lib_event_handler_start.
++	 * In general below lock is not required, because hif_lib_xmit_pkt and
++	 * hif_lib_event_handler_start are called from napi poll and which is
++	 * not re-entrant. But if some client use in different way this lock is
++	 * required.
++	 */
++	/*spin_lock_irqsave(&client->rx_lock, flags); */
++	desc = queue->base + queue->read_idx;
++	if (!(desc->ctrl & CL_DESC_OWN)) {
++		pkt = desc->data - pfe_pkt_headroom;
++
++		*rx_ctrl = desc->client_ctrl;
++		*desc_ctrl = desc->ctrl;
++
++		if (desc->ctrl & CL_DESC_FIRST) {
++			u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
++
++			if (size) {
++				size += PFE_PARSE_INFO_SIZE;
++				*len = CL_DESC_BUF_LEN(desc->ctrl) -
++						PFE_PKT_HEADER_SZ - size;
++				*ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ
++								+ size;
++				*priv_data = desc->data + PFE_PKT_HEADER_SZ;
++			} else {
++				*len = CL_DESC_BUF_LEN(desc->ctrl) -
++				       PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;
++				*ofst = pfe_pkt_headroom
++					+ PFE_PKT_HEADER_SZ
++					+ PFE_PARSE_INFO_SIZE;
++				*priv_data = NULL;
++			}
++
++		} else {
++			*len = CL_DESC_BUF_LEN(desc->ctrl);
++			*ofst = pfe_pkt_headroom;
++		}
++
++		/*
++		 * Needed so we don't free a buffer/page
++		 * twice on module_exit
++		 */
++		desc->data = NULL;
++
++		/*
++		 * Ensure everything else is written to DDR before
++		 * writing bd->ctrl
++		 */
++		smp_wmb();
++
++		desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;
++		queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
++	}
++
++	/*spin_unlock_irqrestore(&client->rx_lock, flags); */
++	return pkt;
++}
++
++static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int
++					client_id, unsigned int qno,
++					u32 client_ctrl)
++{
++	/* Optimize the write since the destinaton may be non-cacheable */
++	if (!((unsigned long)pkt_hdr & 0x3)) {
++		((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) |
++					client_id;
++	} else {
++		((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF);
++		((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF);
++	}
++}
++
++/*This function puts the given packet in the specific client queue */
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
++				*data, unsigned int len, u32 client_ctrl,
++				unsigned int flags, void *client_data)
++{
++	struct hif_client_tx_queue *queue = &client->tx_q[qno];
++	struct tx_queue_desc *desc = queue->base + queue->write_idx;
++
++	/* First buffer */
++	if (flags & HIF_FIRST_BUFFER) {
++		data -= sizeof(struct hif_hdr);
++		len += sizeof(struct hif_hdr);
++
++		hif_hdr_write(data, client->id, qno, client_ctrl);
++	}
++
++	desc->data = client_data;
++	desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags);
++
++	__hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags);
++
++	queue->write_idx = (queue->write_idx + 1) & (queue->size - 1);
++	queue->tx_pending++;
++	queue->jiffies_last_packet = jiffies;
++}
++
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
++				   unsigned int *flags, int count)
++{
++	struct hif_client_tx_queue *queue = &client->tx_q[qno];
++	struct tx_queue_desc *desc = queue->base + queue->read_idx;
++
++	pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno,
++		 queue->read_idx, queue->tx_pending);
++
++	if (!queue->tx_pending)
++		return NULL;
++
++	if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) {
++		u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID +
++			client->id, TMU_DM_TX_TRANS, 4));
++
++		if (queue->prev_tmu_tx_pkts > tmu_tx_pkts)
++			queue->done_tmu_tx_pkts = UINT_MAX -
++				queue->prev_tmu_tx_pkts + tmu_tx_pkts;
++		else
++			queue->done_tmu_tx_pkts = tmu_tx_pkts -
++						queue->prev_tmu_tx_pkts;
++
++		queue->prev_tmu_tx_pkts  = tmu_tx_pkts;
++
++		if (!queue->done_tmu_tx_pkts)
++			return NULL;
++	}
++
++	if (desc->ctrl & CL_DESC_OWN)
++		return NULL;
++
++	queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
++	queue->tx_pending--;
++
++	*flags = CL_DESC_GET_FLAGS(desc->ctrl);
++
++	if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER))
++		queue->done_tmu_tx_pkts--;
++
++	return desc->data;
++}
++
++static void hif_lib_tmu_credit_init(struct pfe *pfe)
++{
++	int i, q;
++
++	for (i = 0; i < NUM_GEMAC_SUPPORT; i++)
++		for (q = 0; q < emac_txq_cnt; q++) {
++			pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ?
++					DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
++			pfe->tmu_credit.tx_credit[i][q] =
++					pfe->tmu_credit.tx_credit_max[i][q];
++		}
++}
++
++/* __hif_lib_update_credit
++ *
++ * @param[in] client	hif client context
++ * @param[in] queue	queue number in match with TMU
++ */
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)
++{
++	unsigned int tmu_tx_packets, tmp;
++
++	if (tx_qos) {
++		tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID +
++			client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4));
++
++		/* tx_packets counter overflowed */
++		if (tmu_tx_packets >
++		    pfe->tmu_credit.tx_packets[client->id][queue]) {
++			tmp = UINT_MAX - tmu_tx_packets +
++			pfe->tmu_credit.tx_packets[client->id][queue];
++
++			pfe->tmu_credit.tx_credit[client->id][queue] =
++			pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp;
++		} else {
++		/* TMU tx <= pfe_eth tx, normal case or both OF since
++		 * last time
++		 */
++			pfe->tmu_credit.tx_credit[client->id][queue] =
++			pfe->tmu_credit.tx_credit_max[client->id][queue] -
++			(pfe->tmu_credit.tx_packets[client->id][queue] -
++			tmu_tx_packets);
++		}
++	}
++}
++
++int pfe_hif_lib_init(struct pfe *pfe)
++{
++	int rc;
++
++	pr_info("%s\n", __func__);
++
++	if (lro_mode) {
++		page_mode = 1;
++		pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE);
++		pfe_pkt_headroom = 0;
++	} else {
++		page_mode = 0;
++		pfe_pkt_size = PFE_PKT_SIZE;
++		pfe_pkt_headroom = PFE_PKT_HEADROOM;
++	}
++
++	if (tx_qos)
++		emac_txq_cnt = EMAC_TXQ_CNT / 2;
++	else
++		emac_txq_cnt = EMAC_TXQ_CNT;
++
++	hif_lib_tmu_credit_init(pfe);
++	pfe->hif.shm = &ghif_shm;
++	rc = pfe_hif_shm_init(pfe->hif.shm);
++
++	return rc;
++}
++
++void pfe_hif_lib_exit(struct pfe *pfe)
++{
++	pr_info("%s\n", __func__);
++
++	pfe_hif_shm_clean(pfe->hif.shm);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
+@@ -0,0 +1,229 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HIF_LIB_H_
++#define _PFE_HIF_LIB_H_
++
++#include "pfe_hif.h"
++
++#define HIF_CL_REQ_TIMEOUT	10
++#define GFP_DMA_PFE 0
++#define PFE_PARSE_INFO_SIZE	16
++
++enum {
++	REQUEST_CL_REGISTER = 0,
++	REQUEST_CL_UNREGISTER,
++	HIF_REQUEST_MAX
++};
++
++enum {
++	/* Event to indicate that client rx queue is reached water mark level */
++	EVENT_HIGH_RX_WM = 0,
++	/* Event to indicate that, packet received for client */
++	EVENT_RX_PKT_IND,
++	/* Event to indicate that, packet tx done for client */
++	EVENT_TXDONE_IND,
++	HIF_EVENT_MAX
++};
++
++/*structure to store client queue info */
++
++/*structure to store client queue info */
++struct hif_client_rx_queue {
++	struct rx_queue_desc *base;
++	u32	size;
++	u32	read_idx;
++	u32	write_idx;
++};
++
++struct hif_client_tx_queue {
++	struct tx_queue_desc *base;
++	u32	size;
++	u32	read_idx;
++	u32	write_idx;
++	u32	tx_pending;
++	unsigned long jiffies_last_packet;
++	u32	nocpy_flag;
++	u32	prev_tmu_tx_pkts;
++	u32	done_tmu_tx_pkts;
++};
++
++struct hif_client_s {
++	int	id;
++	int	tx_qn;
++	int	rx_qn;
++	void	*rx_qbase;
++	void	*tx_qbase;
++	int	tx_qsize;
++	int	rx_qsize;
++	int	cpu_id;
++	struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
++	struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
++	int (*event_handler)(void *priv, int event, int data);
++	unsigned long queue_mask[HIF_EVENT_MAX];
++	struct pfe *pfe;
++	void *priv;
++};
++
++/*
++ * Client specific shared memory
++ * It contains number of Rx/Tx queues, base addresses and queue sizes
++ */
++struct hif_client_shm {
++	u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
++	unsigned long rx_qbase; /*Rx queue base address */
++	u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
++	unsigned long tx_qbase; /* Tx queue base address */
++	u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
++};
++
++/*Client shared memory ctrl bit description */
++#define CLIENT_CTRL_RX_Q_CNT_OFST	0
++#define CLIENT_CTRL_TX_Q_CNT_OFST	8
++#define CLIENT_CTRL_RX_Q_CNT(ctrl)	(((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \
++						& 0xFF)
++#define CLIENT_CTRL_TX_Q_CNT(ctrl)	(((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \
++						& 0xFF)
++
++/*
++ * Shared memory used to communicate between HIF driver and host/client drivers
++ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
++ * initialized with host buffers and buffers count in the pool.
++ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
++ *
++ */
++struct hif_shm {
++	u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
++	/*Rx buffers required to initialize HIF rx descriptors */
++	void *rx_buf_pool[HIF_RX_DESC_NT];
++	unsigned long g_client_status[2]; /*Global client status bit mask */
++	/* Client specific shared memory */
++	struct hif_client_shm client[HIF_CLIENTS_MAX];
++};
++
++#define CL_DESC_OWN	BIT(31)
++/* This sets owner ship to HIF driver */
++#define CL_DESC_LAST	BIT(30)
++/* This indicates last packet for multi buffers handling */
++#define CL_DESC_FIRST	BIT(29)
++/* This indicates first packet for multi buffers handling */
++
++#define CL_DESC_BUF_LEN(x)		((x) & 0xFFFF)
++#define CL_DESC_FLAGS(x)		(((x) & 0xF) << 16)
++#define CL_DESC_GET_FLAGS(x)		(((x) >> 16) & 0xF)
++
++struct rx_queue_desc {
++	void *data;
++	u32	ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++	u32	client_ctrl;
++};
++
++struct tx_queue_desc {
++	void *data;
++	u32	ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++};
++
++/* HIF Rx is not working properly for 2-byte aligned buffers and
++ * ip_header should be 4byte aligned for better iperformance.
++ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
++ */
++#define PFE_PKT_HEADER_SZ	sizeof(struct hif_hdr)
++/* must be big enough for headroom, pkt size and skb shared info */
++#define PFE_BUF_SIZE		2048
++#define PFE_PKT_HEADROOM	128
++
++#define SKB_SHARED_INFO_SIZE   SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
++#define PFE_PKT_SIZE		(PFE_BUF_SIZE - PFE_PKT_HEADROOM \
++				 - SKB_SHARED_INFO_SIZE)
++#define MAX_L2_HDR_SIZE		14	/* Not correct for VLAN/PPPoE */
++#define MAX_L3_HDR_SIZE		20	/* Not correct for IPv6 */
++#define MAX_L4_HDR_SIZE		60	/* TCP with maximum options */
++#define MAX_HDR_SIZE		(MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \
++				 + MAX_L4_HDR_SIZE)
++/* Used in page mode to clamp packet size to the maximum supported by the hif
++ *hw interface (<16KiB)
++ */
++#define MAX_PFE_PKT_SIZE	16380UL
++
++extern unsigned int pfe_pkt_size;
++extern unsigned int pfe_pkt_headroom;
++extern unsigned int page_mode;
++extern unsigned int lro_mode;
++extern unsigned int tx_qos;
++extern unsigned int emac_txq_cnt;
++
++int pfe_hif_lib_init(struct pfe *pfe);
++void pfe_hif_lib_exit(struct pfe *pfe);
++int hif_lib_client_register(struct hif_client_s *client);
++int hif_lib_client_unregister(struct  hif_client_s *client);
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
++				*data, unsigned int len, u32 client_ctrl,
++				unsigned int flags, void *client_data);
++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data,
++		     unsigned int len, u32 client_ctrl, void *client_data);
++void hif_lib_indicate_client(int cl_id, int event, int data);
++int hif_lib_event_handler_start(struct hif_client_s *client, int event, int
++					data);
++int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno);
++int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno);
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
++				   unsigned int *flags, int count);
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
++				*ofst, unsigned int *rx_ctrl,
++				unsigned int *desc_ctrl, void **priv_data);
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue);
++void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);
++void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int
++					enable);
++static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int
++					qno)
++{
++	struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++	return (queue->size - queue->tx_pending);
++}
++
++static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned
++						int qno)
++{
++	struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++	return queue->write_idx;
++}
++
++static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int
++					qno)
++{
++	struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++	return queue->tx_pending;
++}
++
++#define hif_lib_tx_credit_avail(pfe, id, qno) \
++				((pfe)->tmu_credit.tx_credit[id][qno])
++
++#define hif_lib_tx_credit_max(pfe, id, qno) \
++				((pfe)->tmu_credit.tx_credit_max[id][qno])
++
++/*
++ * Test comment
++ */
++#define hif_lib_tx_credit_use(pfe, id, qno, credit)			\
++	({ typeof(pfe) pfe_ = pfe;					\
++		typeof(id) id_ = id;					\
++		typeof(qno) qno_ = qno;					\
++		typeof(credit) credit_ = credit;			\
++		do {							\
++			if (tx_qos) {					\
++				(pfe_)->tmu_credit.tx_credit[id_][qno_]\
++					 -= credit_;			\
++				(pfe_)->tmu_credit.tx_packets[id_][qno_]\
++					+= credit_;			\
++			}						\
++		} while (0);						\
++	})
++
++#endif /* _PFE_HIF_LIB_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.c
+@@ -0,0 +1,164 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include "pfe_mod.h"
++#include "pfe_hw.h"
++
++/* Functions to handle most of pfe hw register initialization */
++int pfe_hw_init(struct pfe *pfe, int resume)
++{
++	struct class_cfg class_cfg = {
++		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++		.route_table_baseaddr = pfe->ddr_phys_baseaddr +
++					ROUTE_TABLE_BASEADDR,
++		.route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
++	};
++
++	struct tmu_cfg tmu_cfg = {
++		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++		.llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
++		.llm_queue_len = TMU_LLM_QUEUE_LEN,
++	};
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	struct util_cfg util_cfg = {
++		.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++	};
++#endif
++
++	struct BMU_CFG bmu1_cfg = {
++		.baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
++						BMU1_LMEM_BASEADDR),
++		.count = BMU1_BUF_COUNT,
++		.size = BMU1_BUF_SIZE,
++		.low_watermark = 10,
++		.high_watermark = 15,
++	};
++
++	struct BMU_CFG bmu2_cfg = {
++		.baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr +
++						BMU2_DDR_BASEADDR),
++		.count = BMU2_BUF_COUNT,
++		.size = BMU2_BUF_SIZE,
++		.low_watermark = 250,
++		.high_watermark = 253,
++	};
++
++	struct gpi_cfg egpi1_cfg = {
++		.lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
++		.tmlf_txthres = EGPI1_TMLF_TXTHRES,
++		.aseq_len = EGPI1_ASEQ_LEN,
++		.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR +
++						EMAC_TCNTRL_REG),
++	};
++
++	struct gpi_cfg egpi2_cfg = {
++		.lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
++		.tmlf_txthres = EGPI2_TMLF_TXTHRES,
++		.aseq_len = EGPI2_ASEQ_LEN,
++		.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR +
++						EMAC_TCNTRL_REG),
++	};
++
++	struct gpi_cfg hgpi_cfg = {
++		.lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
++		.tmlf_txthres = HGPI_TMLF_TXTHRES,
++		.aseq_len = HGPI_ASEQ_LEN,
++		.mtip_pause_reg = 0,
++	};
++
++	pr_info("%s\n", __func__);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++	/* LS1012A needs this to make PE work correctly */
++	writel(0x3,     CLASS_PE_SYS_CLK_RATIO);
++	writel(0x3,     TMU_PE_SYS_CLK_RATIO);
++	writel(0x3,     UTIL_PE_SYS_CLK_RATIO);
++	usleep_range(10, 20);
++#endif
++
++	pr_info("CLASS version: %x\n", readl(CLASS_VERSION));
++	pr_info("TMU version: %x\n", readl(TMU_VERSION));
++
++	pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR +
++		BMU_VERSION));
++	pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR +
++		BMU_VERSION));
++
++	pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR +
++		GPI_VERSION));
++	pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR +
++		GPI_VERSION));
++	pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR +
++		GPI_VERSION));
++
++	pr_info("HIF version: %x\n", readl(HIF_VERSION));
++	pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION));
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	pr_info("UTIL version: %x\n", readl(UTIL_VERSION));
++#endif
++	while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE))
++		;
++
++	hif_rx_disable();
++	hif_tx_disable();
++
++	bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
++
++	pr_info("bmu_init(1) done\n");
++
++	bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
++
++	pr_info("bmu_init(2) done\n");
++
++	class_cfg.resume = resume ? 1 : 0;
++
++	class_init(&class_cfg);
++
++	pr_info("class_init() done\n");
++
++	tmu_init(&tmu_cfg);
++
++	pr_info("tmu_init() done\n");
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	util_init(&util_cfg);
++
++	pr_info("util_init() done\n");
++#endif
++	gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
++
++	pr_info("gpi_init(1) done\n");
++
++	gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
++
++	pr_info("gpi_init(2) done\n");
++
++	gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
++
++	pr_info("gpi_init(hif) done\n");
++
++	bmu_enable(BMU1_BASE_ADDR);
++
++	pr_info("bmu_enable(1) done\n");
++
++	bmu_enable(BMU2_BASE_ADDR);
++
++	pr_info("bmu_enable(2) done\n");
++
++	return 0;
++}
++
++void pfe_hw_exit(struct pfe *pfe)
++{
++	pr_info("%s\n", __func__);
++
++	bmu_disable(BMU1_BASE_ADDR);
++	bmu_reset(BMU1_BASE_ADDR);
++
++	bmu_disable(BMU2_BASE_ADDR);
++	bmu_reset(BMU2_BASE_ADDR);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HW_H_
++#define _PFE_HW_H_
++
++#define PE_SYS_CLK_RATIO	1	/* SYS/AXI = 250MHz, HFE = 500MHz */
++
++int pfe_hw_init(struct pfe *pfe, int resume);
++void pfe_hw_exit(struct pfe *pfe);
++
++#endif /* _PFE_HW_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+@@ -0,0 +1,383 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/of_address.h>
++#include <linux/of_mdio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
++
++#include "pfe_mod.h"
++
++extern bool pfe_use_old_dts_phy;
++struct ls1012a_pfe_platform_data pfe_platform_data;
++
++static int pfe_get_gemac_if_properties(struct device_node *gem,
++				       int port,
++				       struct ls1012a_pfe_platform_data	*pdata)
++{
++	struct device_node *phy_node = NULL;
++	int size;
++	int phy_id = 0;
++	const u32 *addr;
++	int err;
++
++	addr = of_get_property(gem, "reg", &size);
++	if (addr)
++		port = be32_to_cpup(addr);
++	else
++		goto err;
++
++	pdata->ls1012a_eth_pdata[port].gem_id = port;
++
++	err = of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr);
++
++	phy_node = of_parse_phandle(gem, "phy-handle", 0);
++	pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
++	if (phy_node) {
++		pfe_use_old_dts_phy = false;
++		goto process_phynode;
++	} else if (of_phy_is_fixed_link(gem)) {
++		pfe_use_old_dts_phy = false;
++		if (of_phy_register_fixed_link(gem) < 0) {
++			pr_err("broken fixed-link specification\n");
++			goto err;
++		}
++		phy_node = of_node_get(gem);
++		pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
++	} else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) {
++		pfe_use_old_dts_phy = true;
++		/* Use old dts properties for phy handling */
++		addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size);
++		pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr);
++
++		addr = of_get_property(gem, "fsl,gemac-phy-id", &size);
++		if (!addr) {
++			pr_err("%s:%d Invalid gemac-phy-id....\n", __func__,
++			       __LINE__);
++		} else {
++			phy_id = be32_to_cpup(addr);
++			pdata->ls1012a_eth_pdata[port].phy_id = phy_id;
++			pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id);
++		}
++
++		/* If PHY is enabled, read mdio properties */
++		if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY)
++			goto done;
++
++	} else {
++		pr_info("%s: No PHY or fixed-link\n", __func__);
++		return 0;
++	}
++
++process_phynode:
++	err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config);
++	if (err)
++		pr_err("%s:%d Incorrect Phy mode....\n", __func__,
++		       __LINE__);
++
++	addr = of_get_property(gem, "fsl,mdio-mux-val", &size);
++	if (!addr) {
++		pr_err("%s: Invalid mdio-mux-val....\n", __func__);
++	} else {
++		phy_id = be32_to_cpup(addr);
++		pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
++	}
++
++	if (pdata->ls1012a_eth_pdata[port].phy_id < 32)
++		pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] =
++			 pdata->ls1012a_eth_pdata[port].mdio_muxval;
++
++
++	pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL;
++
++done:
++	return 0;
++
++err:
++	return -1;
++}
++
++/*
++ *
++ * pfe_platform_probe -
++ *
++ *
++ */
++static int pfe_platform_probe(struct platform_device *pdev)
++{
++	struct resource res;
++	int ii = 0, rc, interface_count = 0, size = 0;
++	const u32 *prop;
++	struct device_node *np, *gem = NULL;
++	struct clk *pfe_clk;
++
++	np = pdev->dev.of_node;
++
++	if (!np) {
++		pr_err("Invalid device node\n");
++		return -EINVAL;
++	}
++
++	pfe = kzalloc(sizeof(*pfe), GFP_KERNEL);
++	if (!pfe) {
++		rc = -ENOMEM;
++		goto err_alloc;
++	}
++
++	platform_set_drvdata(pdev, pfe);
++
++	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
++		rc = -ENOMEM;
++		pr_err("unable to configure DMA mask.\n");
++		goto err_ddr;
++	}
++
++	if (of_address_to_resource(np, 1, &res)) {
++		rc = -ENOMEM;
++		pr_err("failed to get ddr resource\n");
++		goto err_ddr;
++	}
++
++	pfe->ddr_phys_baseaddr = res.start;
++	pfe->ddr_size = resource_size(&res);
++
++	pfe->ddr_baseaddr = memremap(res.start, resource_size(&res),
++				     MEMREMAP_WB);
++	if (!pfe->ddr_baseaddr) {
++		pr_err("memremap() ddr failed\n");
++		rc = -ENOMEM;
++		goto err_ddr;
++	}
++
++	pfe->scfg =
++		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++						"fsl,pfe-scfg");
++	if (IS_ERR(pfe->scfg)) {
++		dev_err(&pdev->dev, "No syscfg phandle specified\n");
++		return PTR_ERR(pfe->scfg);
++	}
++
++	pfe->cbus_baseaddr = of_iomap(np, 0);
++	if (!pfe->cbus_baseaddr) {
++		rc = -ENOMEM;
++		pr_err("failed to get axi resource\n");
++		goto err_axi;
++	}
++
++	pfe->hif_irq = platform_get_irq(pdev, 0);
++	if (pfe->hif_irq < 0) {
++		pr_err("platform_get_irq for hif failed\n");
++		rc = pfe->hif_irq;
++		goto err_hif_irq;
++	}
++
++	pfe->wol_irq = platform_get_irq(pdev, 2);
++	if (pfe->wol_irq < 0) {
++		pr_err("platform_get_irq for WoL failed\n");
++		rc = pfe->wol_irq;
++		goto err_hif_irq;
++	}
++
++	/* Read interface count */
++	prop = of_get_property(np, "fsl,pfe-num-interfaces", &size);
++	if (!prop) {
++		pr_err("Failed to read number of interfaces\n");
++		rc = -ENXIO;
++		goto err_prop;
++	}
++
++	interface_count = be32_to_cpup(prop);
++	if (interface_count <= 0) {
++		pr_err("No ethernet interface count : %d\n",
++		       interface_count);
++		rc = -ENXIO;
++		goto err_prop;
++	}
++
++	pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff;
++
++	while ((gem = of_get_next_child(np, gem))) {
++		if (of_find_property(gem, "reg", &size)) {
++			pfe_get_gemac_if_properties(gem, ii,
++						&pfe_platform_data);
++			ii++;
++		}
++	}
++
++	if (interface_count != ii)
++		pr_info("missing some of gemac interface properties.\n");
++
++	pfe->dev = &pdev->dev;
++
++	pfe->dev->platform_data = &pfe_platform_data;
++
++	/* declare WoL capabilities */
++	device_init_wakeup(&pdev->dev, true);
++
++	/* find the clocks */
++	pfe_clk = devm_clk_get(pfe->dev, "pfe");
++	if (IS_ERR(pfe_clk))
++		return PTR_ERR(pfe_clk);
++
++	/* PFE clock is (platform clock / 2) */
++	/* save sys_clk value as KHz */
++	pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000);
++
++	rc = pfe_probe(pfe);
++	if (rc < 0)
++		goto err_probe;
++
++	return 0;
++
++err_probe:
++err_prop:
++err_hif_irq:
++	iounmap(pfe->cbus_baseaddr);
++
++err_axi:
++	memunmap(pfe->ddr_baseaddr);
++
++err_ddr:
++	platform_set_drvdata(pdev, NULL);
++
++	kfree(pfe);
++
++err_alloc:
++	return rc;
++}
++
++/*
++ * pfe_platform_remove -
++ */
++static int pfe_platform_remove(struct platform_device *pdev)
++{
++	struct pfe *pfe = platform_get_drvdata(pdev);
++	int rc;
++
++	pr_info("%s\n", __func__);
++
++	rc = pfe_remove(pfe);
++
++	iounmap(pfe->cbus_baseaddr);
++
++	memunmap(pfe->ddr_baseaddr);
++
++	platform_set_drvdata(pdev, NULL);
++
++	kfree(pfe);
++
++	return rc;
++}
++
++#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
++int pfe_platform_suspend(struct device *dev)
++{
++	struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++	struct net_device *netdev;
++	int i;
++
++	pfe->wake = 0;
++
++	for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
++		netdev = pfe->eth.eth_priv[i]->ndev;
++
++		netif_device_detach(netdev);
++
++		if (netif_running(netdev))
++			if (pfe_eth_suspend(netdev))
++				pfe->wake = 1;
++	}
++
++	/* Shutdown PFE only if we're not waking up the system */
++	if (!pfe->wake) {
++#if defined(LS1012A_PFE_RESET_WA)
++		pfe_hif_rx_idle(&pfe->hif);
++#endif
++		pfe_ctrl_suspend(&pfe->ctrl);
++		pfe_firmware_exit(pfe);
++
++		pfe_hif_exit(pfe);
++		pfe_hif_lib_exit(pfe);
++
++		pfe_hw_exit(pfe);
++	}
++
++	return 0;
++}
++
++static int pfe_platform_resume(struct device *dev)
++{
++	struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++	struct net_device *netdev;
++	int i;
++
++	if (!pfe->wake) {
++		pfe_hw_init(pfe, 1);
++		pfe_hif_lib_init(pfe);
++		pfe_hif_init(pfe);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++		util_enable();
++#endif
++		tmu_enable(0xf);
++		class_enable();
++		pfe_ctrl_resume(&pfe->ctrl);
++	}
++
++	for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
++		netdev = pfe->eth.eth_priv[i]->ndev;
++
++		if (pfe->mdio.mdio_priv[i]->mii_bus)
++			pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus);
++
++		if (netif_running(netdev))
++			pfe_eth_resume(netdev);
++
++		netif_device_attach(netdev);
++	}
++	return 0;
++}
++#else
++#define pfe_platform_suspend NULL
++#define pfe_platform_resume NULL
++#endif
++
++static const struct dev_pm_ops pfe_platform_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume)
++};
++#endif
++
++static const struct of_device_id pfe_match[] = {
++	{
++		.compatible = "fsl,pfe",
++	},
++	{},
++};
++MODULE_DEVICE_TABLE(of, pfe_match);
++
++static struct platform_driver pfe_platform_driver = {
++	.probe = pfe_platform_probe,
++	.remove = pfe_platform_remove,
++	.driver = {
++		.name = "pfe",
++		.of_match_table = pfe_match,
++#ifdef CONFIG_PM
++		.pm = &pfe_platform_pm_ops,
++#endif
++	},
++};
++
++module_platform_driver(pfe_platform_driver);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("PFE Ethernet driver");
++MODULE_AUTHOR("NXP DNCPE");
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.c
+@@ -0,0 +1,158 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/dma-mapping.h>
++#include "pfe_mod.h"
++#include "pfe_cdev.h"
++
++unsigned int us;
++module_param(us, uint, 0444);
++MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n"
++			"1: module enabled for userspace networking\n");
++struct pfe *pfe;
++
++/*
++ * pfe_probe -
++ */
++int pfe_probe(struct pfe *pfe)
++{
++	int rc;
++
++	if (pfe->ddr_size < DDR_MAX_SIZE) {
++		pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n",
++		       __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size);
++		rc = -ENOMEM;
++		goto err_hw;
++	}
++
++	if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) &
++			(8 * SZ_1M - 1)) != 0) {
++		pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n",
++		       __func__, (int)pfe->ddr_phys_baseaddr +
++			BMU2_DDR_BASEADDR);
++		rc = -ENOMEM;
++		goto err_hw;
++	}
++
++	pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n",
++		(unsigned long)pfe->cbus_baseaddr,
++		(unsigned long)pfe->ddr_baseaddr,
++		pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++	pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr,
++		     pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++	rc = pfe_hw_init(pfe, 0);
++	if (rc < 0)
++		goto err_hw;
++
++	if (us)
++		goto firmware_init;
++
++	rc = pfe_hif_lib_init(pfe);
++	if (rc < 0)
++		goto err_hif_lib;
++
++	rc = pfe_hif_init(pfe);
++	if (rc < 0)
++		goto err_hif;
++
++firmware_init:
++	rc = pfe_firmware_init(pfe);
++	if (rc < 0)
++		goto err_firmware;
++
++	rc = pfe_ctrl_init(pfe);
++	if (rc < 0)
++		goto err_ctrl;
++
++	rc = pfe_eth_init(pfe);
++	if (rc < 0)
++		goto err_eth;
++
++	rc = pfe_sysfs_init(pfe);
++	if (rc < 0)
++		goto err_sysfs;
++
++	rc = pfe_debugfs_init(pfe);
++	if (rc < 0)
++		goto err_debugfs;
++
++	if (us) {
++		/* Creating a character device */
++		rc = pfe_cdev_init();
++		if (rc < 0)
++			goto err_cdev;
++	}
++
++	return 0;
++
++err_cdev:
++	pfe_debugfs_exit(pfe);
++
++err_debugfs:
++	pfe_sysfs_exit(pfe);
++
++err_sysfs:
++	pfe_eth_exit(pfe);
++
++err_eth:
++	pfe_ctrl_exit(pfe);
++
++err_ctrl:
++	pfe_firmware_exit(pfe);
++
++err_firmware:
++	if (us)
++		goto err_hif_lib;
++
++	pfe_hif_exit(pfe);
++
++err_hif:
++	pfe_hif_lib_exit(pfe);
++
++err_hif_lib:
++	pfe_hw_exit(pfe);
++
++err_hw:
++	return rc;
++}
++
++/*
++ * pfe_remove -
++ */
++int pfe_remove(struct pfe *pfe)
++{
++	pr_info("%s\n", __func__);
++
++	if (us)
++		pfe_cdev_exit();
++
++	pfe_debugfs_exit(pfe);
++
++	pfe_sysfs_exit(pfe);
++
++	pfe_eth_exit(pfe);
++
++	pfe_ctrl_exit(pfe);
++
++#if defined(LS1012A_PFE_RESET_WA)
++	pfe_hif_rx_idle(&pfe->hif);
++#endif
++	pfe_firmware_exit(pfe);
++
++	if (us)
++		goto hw_exit;
++
++	pfe_hif_exit(pfe);
++
++	pfe_hif_lib_exit(pfe);
++
++hw_exit:
++	pfe_hw_exit(pfe);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.h
+@@ -0,0 +1,103 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_MOD_H_
++#define _PFE_MOD_H_
++
++#include <linux/device.h>
++#include <linux/elf.h>
++
++extern unsigned int us;
++
++struct pfe;
++
++#include "pfe_hw.h"
++#include "pfe_firmware.h"
++#include "pfe_ctrl.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++#include "pfe_eth.h"
++#include "pfe_sysfs.h"
++#include "pfe_perfmon.h"
++#include "pfe_debugfs.h"
++
++#define PHYID_MAX_VAL 32
++
++struct pfe_tmu_credit {
++	/* Number of allowed TX packet in-flight, matches TMU queue size */
++	unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++	unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++	unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++};
++
++struct pfe {
++	struct regmap	*scfg;
++	unsigned long ddr_phys_baseaddr;
++	void *ddr_baseaddr;
++	unsigned int ddr_size;
++	void *cbus_baseaddr;
++	void *apb_baseaddr;
++	unsigned long iram_phys_baseaddr;
++	void *iram_baseaddr;
++	unsigned long ipsec_phys_baseaddr;
++	void *ipsec_baseaddr;
++	int hif_irq;
++	int wol_irq;
++	int hif_client_irq;
++	struct device *dev;
++	struct dentry *dentry;
++	struct pfe_ctrl ctrl;
++	struct pfe_hif hif;
++	struct pfe_eth eth;
++	struct pfe_mdio mdio;
++	struct hif_client_s *hif_client[HIF_CLIENTS_MAX];
++#if defined(CFG_DIAGS)
++	struct pfe_diags diags;
++#endif
++	struct pfe_tmu_credit tmu_credit;
++	struct pfe_cpumon cpumon;
++	struct pfe_memmon memmon;
++	int wake;
++	int mdio_muxval[PHYID_MAX_VAL];
++	struct clk *hfe_clock;
++};
++
++extern struct pfe *pfe;
++
++int pfe_probe(struct pfe *pfe);
++int pfe_remove(struct pfe *pfe);
++
++/* DDR Mapping in reserved memory*/
++#define ROUTE_TABLE_BASEADDR	0
++#define ROUTE_TABLE_HASH_BITS	15	/* 32K entries */
++#define ROUTE_TABLE_SIZE	((1 << ROUTE_TABLE_HASH_BITS) \
++				  * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT		(4096 - 256)
++/* This is to get a total DDR size of 12MiB */
++#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define UTIL_CODE_BASEADDR	(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define UTIL_CODE_SIZE		(128 * SZ_1K)
++#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
++#define TMU_LLM_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define TMU_LLM_QUEUE_LEN	(8 * 512)
++/* Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)
++/* (4 TMU's x 16 queues x queue_len) */
++
++#define DDR_MAX_SIZE		(TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++
++/* LMEM Mapping */
++#define BMU1_LMEM_BASEADDR	0
++#define BMU1_BUF_COUNT		256
++#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
++
++#endif /* _PFE_MOD_H */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h
+@@ -0,0 +1,26 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_PERFMON_H_
++#define _PFE_PERFMON_H_
++
++#include "pfe/pfe.h"
++
++#define	CT_CPUMON_INTERVAL	(1 * TIMER_TICKS_PER_SEC)
++
++struct pfe_cpumon {
++	u32 cpu_usage_pct[MAX_PE];
++	u32 class_usage_pct;
++};
++
++struct pfe_memmon {
++	u32 kernel_memory_allocated;
++};
++
++int pfe_perfmon_init(struct pfe *pfe);
++void pfe_perfmon_exit(struct pfe *pfe);
++
++#endif /* _PFE_PERFMON_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
+@@ -0,0 +1,840 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++
++#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8
++#define NUM_QUEUES		16
++
++static char register_name[20][5] = {
++	"EPC", "ECAS", "EID", "ED",
++	"r0", "r1", "r2", "r3",
++	"r4", "r5", "r6", "r7",
++	"r8", "r9", "r10", "r11",
++	"r12", "r13", "r14", "r15",
++};
++
++static char exception_name[14][20] = {
++	"Reset",
++	"HardwareFailure",
++	"NMI",
++	"InstBreakpoint",
++	"DataBreakpoint",
++	"Unsupported",
++	"PrivilegeViolation",
++	"InstBusError",
++	"DataBusError",
++	"AlignmentError",
++	"ArithmeticError",
++	"SystemCall",
++	"MemoryManagement",
++	"Interrupt",
++};
++
++static unsigned long class_do_clear;
++static unsigned long tmu_do_clear;
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static unsigned long util_do_clear;
++#endif
++
++static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long
++					do_clear)
++{
++	ssize_t len = 0;
++	u32 val;
++	char statebuf[5];
++	struct pfe_cpumon *cpumon = &pfe->cpumon;
++	u32 debug_indicator;
++	u32 debug[20];
++
++	if (id < CLASS0_ID || id >= MAX_PE)
++		return len;
++
++	*(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4);
++	dmem_addr += 4;
++
++	statebuf[4] = '\0';
++	len += sprintf(buf + len, "state=%4s ", statebuf);
++
++	val = pe_dmem_read(id, dmem_addr, 4);
++	dmem_addr += 4;
++	len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val));
++
++	val = pe_dmem_read(id, dmem_addr, 4);
++	if (do_clear && val)
++		pe_dmem_write(id, 0, dmem_addr, 4);
++	dmem_addr += 4;
++	len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val));
++
++	val = pe_dmem_read(id, dmem_addr, 4);
++	if (do_clear && val)
++		pe_dmem_write(id, 0, dmem_addr, 4);
++	dmem_addr += 4;
++	if (id >= TMU0_ID && id <= TMU_MAX_ID)
++		len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val));
++	else
++		len += sprintf(buf + len, "tx=%u", cpu_to_be32(val));
++
++	val = pe_dmem_read(id, dmem_addr, 4);
++	if (do_clear && val)
++		pe_dmem_write(id, 0, dmem_addr, 4);
++	dmem_addr += 4;
++	if (val)
++		len += sprintf(buf + len, " drop=%u", cpu_to_be32(val));
++
++	len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]);
++
++	len += sprintf(buf + len, "\n");
++
++	debug_indicator = pe_dmem_read(id, dmem_addr, 4);
++	dmem_addr += 4;
++	if (!strncmp((char *)&debug_indicator, "DBUG", 4)) {
++		int j, last = 0;
++
++		for (j = 0; j < 16; j++) {
++			debug[j] = pe_dmem_read(id, dmem_addr, 4);
++			if (debug[j]) {
++				if (do_clear)
++					pe_dmem_write(id, 0, dmem_addr, 4);
++				last = j + 1;
++			}
++			dmem_addr += 4;
++		}
++		for (j = 0; j < last; j++) {
++			len += sprintf(buf + len, "%08x%s",
++			cpu_to_be32(debug[j]),
++			(j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
++		}
++	}
++
++	if (!strncmp(statebuf, "DEAD", 4)) {
++		u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS;
++
++		len += sprintf(buf + len, "Exception details:\n");
++		for (i = 0; i < 20; i++) {
++			debug[i] = pe_dmem_read(id, dump, 4);
++			dump += 4;
++			if (i == 2)
++				len += sprintf(buf + len, "%4s = %08x (=%s) ",
++				register_name[i], cpu_to_be32(debug[i]),
++				exception_name[min((u32)
++				cpu_to_be32(debug[i]), (u32)13)]);
++			else
++				len += sprintf(buf + len, "%4s = %08x%s",
++				register_name[i], cpu_to_be32(debug[i]),
++				(i & 0x3) == 0x3 || i == 19 ? "\n" : " ");
++		}
++	}
++
++	return len;
++}
++
++static ssize_t class_phy_stats(char *buf, int phy)
++{
++	ssize_t len = 0;
++	int off1 = phy * 0x28;
++	int off2 = phy * 0x10;
++
++	if (phy == 3)
++		off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS;
++
++	len += sprintf(buf + len, "phy: %d\n", phy);
++	len += sprintf(buf + len,
++			"  rx:   %10u, tx:   %10u, intf:  %10u, ipv4:    %10u, ipv6: %10u\n",
++			readl(CLASS_PHY1_RX_PKTS + off1),
++			readl(CLASS_PHY1_TX_PKTS + off1),
++			readl(CLASS_PHY1_INTF_MATCH_PKTS + off1),
++			readl(CLASS_PHY1_V4_PKTS + off1),
++			readl(CLASS_PHY1_V6_PKTS + off1));
++
++	len += sprintf(buf + len,
++			"  icmp: %10u, igmp: %10u, tcp:   %10u, udp:     %10u\n",
++			readl(CLASS_PHY1_ICMP_PKTS + off2),
++			readl(CLASS_PHY1_IGMP_PKTS + off2),
++			readl(CLASS_PHY1_TCP_PKTS + off2),
++			readl(CLASS_PHY1_UDP_PKTS + off2));
++
++	len += sprintf(buf + len, "  err\n");
++	len += sprintf(buf + len,
++			"  lp:   %10u, intf: %10u, l3:    %10u, chcksum: %10u, ttl:  %10u\n",
++			readl(CLASS_PHY1_LP_FAIL_PKTS + off1),
++			readl(CLASS_PHY1_INTF_FAIL_PKTS + off1),
++			readl(CLASS_PHY1_L3_FAIL_PKTS + off1),
++			readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1),
++			readl(CLASS_PHY1_TTL_ERR_PKTS + off1));
++
++	return len;
++}
++
++/* qm_read_drop_stat
++ * This function is used to read the drop statistics from the TMU
++ * hw drop counter.  Since the hw counter is always cleared afer
++ * reading, this function maintains the previous drop count, and
++ * adds the new value to it.  That value can be retrieved by
++ * passing a pointer to it with the total_drops arg.
++ *
++ * @param tmu		TMU number (0 - 3)
++ * @param queue		queue number (0 - 15)
++ * @param total_drops	pointer to location to store total drops (or NULL)
++ * @param do_reset	if TRUE, clear total drops after updating
++ */
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
++{
++	static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
++	u32 val;
++
++	writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++	writel((tmu << 8) | queue, TMU_LLM_CTRL);
++	val = readl(TMU_TEQ_DROP_STAT);
++	qtotal[tmu][queue] += val;
++	if (total_drops)
++		*total_drops = qtotal[tmu][queue];
++	if (do_reset)
++		qtotal[tmu][queue] = 0;
++	return val;
++}
++
++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
++{
++	ssize_t len = 0;
++	u32 drops;
++
++	len += sprintf(buf + len, "%d-%02d, ", tmu, queue);
++
++	drops = qm_read_drop_stat(tmu, queue, NULL, 0);
++
++	/* Select queue */
++	writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++	writel((tmu << 8) | queue, TMU_LLM_CTRL);
++
++	len += sprintf(buf + len,
++			"(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
++		drops, readl(TMU_TEQ_TRANS_STAT),
++		readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
++		readl(TMU_LLM_QUE_DROPCNT));
++
++	return len;
++}
++
++static ssize_t tmu_queues(char *buf, int tmu)
++{
++	ssize_t len = 0;
++	int queue;
++
++	for (queue = 0; queue < 16; queue++)
++		len += tmu_queue_stats(buf + len, tmu, queue);
++
++	return len;
++}
++
++static ssize_t block_version(char *buf, void *addr)
++{
++	ssize_t len = 0;
++	u32 val;
++
++	val = readl(addr);
++	len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n",
++		(val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff);
++
++	return len;
++}
++
++static ssize_t bmu(char *buf, int id, void *base)
++{
++	ssize_t len = 0;
++
++	len += sprintf(buf + len, "%s: %d\n  ", __func__, id);
++
++	len += block_version(buf + len, base + BMU_VERSION);
++
++	len += sprintf(buf + len, "  buf size:  %x\n", (1 << readl(base +
++			BMU_BUF_SIZE)));
++	len += sprintf(buf + len, "  buf count: %x\n", readl(base +
++			BMU_BUF_CNT));
++	len += sprintf(buf + len, "  buf rem:   %x\n", readl(base +
++			BMU_REM_BUF_CNT));
++	len += sprintf(buf + len, "  buf curr:  %x\n", readl(base +
++			BMU_CURR_BUF_CNT));
++	len += sprintf(buf + len, "  free err:  %x\n", readl(base +
++			BMU_FREE_ERR_ADDR));
++
++	return len;
++}
++
++static ssize_t gpi(char *buf, int id, void *base)
++{
++	ssize_t len = 0;
++	u32 val;
++
++	len += sprintf(buf + len, "%s%d:\n  ", __func__, id);
++	len += block_version(buf + len, base + GPI_VERSION);
++
++	len += sprintf(buf + len, "  tx under stick: %x\n", readl(base +
++			GPI_FIFO_STATUS));
++	val = readl(base + GPI_FIFO_DEBUG);
++	len += sprintf(buf + len, "  tx pkts:        %x\n", (val >> 23) &
++			0x3f);
++	len += sprintf(buf + len, "  rx pkts:        %x\n", (val >> 18) &
++			0x3f);
++	len += sprintf(buf + len, "  tx bytes:       %x\n", (val >> 9) &
++			0x1ff);
++	len += sprintf(buf + len, "  rx bytes:       %x\n", (val >> 0) &
++			0x1ff);
++	len += sprintf(buf + len, "  overrun:        %x\n", readl(base +
++			GPI_OVERRUN_DROPCNT));
++
++	return len;
++}
++
++static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr,
++			     const char *buf, size_t count)
++{
++	class_do_clear = kstrtoul(buf, 0, 0);
++	return count;
++}
++
++static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr,
++			      char *buf)
++{
++	ssize_t len = 0;
++	int id;
++	u32 val;
++	struct pfe_cpumon *cpumon = &pfe->cpumon;
++
++	len += block_version(buf + len, CLASS_VERSION);
++
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++		len += sprintf(buf + len, "%d: ", id - CLASS0_ID);
++
++		val = readl(CLASS_PE0_DEBUG + id * 4);
++		len += sprintf(buf + len, "pc=1%04x ", val & 0xffff);
++
++		len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS,
++						class_do_clear);
++	}
++	len += sprintf(buf + len, "aggregate load=%d%%\n\n",
++			cpumon->class_usage_pct);
++
++	len += sprintf(buf + len, "pe status:   0x%x\n",
++			readl(CLASS_PE_STATUS));
++	len += sprintf(buf + len, "max buf cnt: 0x%x   afull thres: 0x%x\n",
++			readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES));
++	len += sprintf(buf + len, "tsq max cnt: 0x%x   tsq fifo thres: 0x%x\n",
++			readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES));
++	len += sprintf(buf + len, "state:       0x%x\n", readl(CLASS_STATE));
++
++	len += class_phy_stats(buf + len, 0);
++	len += class_phy_stats(buf + len, 1);
++	len += class_phy_stats(buf + len, 2);
++	len += class_phy_stats(buf + len, 3);
++
++	return len;
++}
++
++static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr,
++			   const char *buf, size_t count)
++{
++	tmu_do_clear = kstrtoul(buf, 0, 0);
++	return count;
++}
++
++static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr,
++			    char *buf)
++{
++	ssize_t len = 0;
++	int id;
++	u32 val;
++
++	len += block_version(buf + len, TMU_VERSION);
++
++	for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++		if (id == TMU2_ID)
++			continue;
++		len += sprintf(buf + len, "%d: ", id - TMU0_ID);
++
++		len += display_pe_status(buf + len, id, TMU_DM_PESTATUS,
++						tmu_do_clear);
++	}
++
++	len += sprintf(buf + len, "pe status:    %x\n", readl(TMU_PE_STATUS));
++	len += sprintf(buf + len, "inq fifo cnt: %x\n",
++			readl(TMU_PHY_INQ_FIFO_CNT));
++	val = readl(TMU_INQ_STAT);
++	len += sprintf(buf + len, "inq wr ptr:     %x\n", val & 0x3ff);
++	len += sprintf(buf + len, "inq rd ptr:     %x\n", val >> 10);
++
++	return len;
++}
++
++static unsigned long drops_do_clear;
++static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS];
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS];
++#endif
++
++char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = {
++	"ICC",
++	"Host Pkt Error",
++	"Rx Error",
++	"IPsec Outbound",
++	"IPsec Inbound",
++	"EXPT IPsec Error",
++	"Reassembly",
++	"Fragmenter",
++	"NAT-T",
++	"Socket",
++	"Multicast",
++	"NAT-PT",
++	"Tx Disabled",
++};
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = {
++	"IPsec Outbound",
++	"IPsec Inbound",
++	"IPsec Rate Limiter",
++	"Fragmenter",
++	"Socket",
++	"Tx Disabled",
++	"Rx Error",
++};
++#endif
++
++static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr,
++			     const char *buf, size_t count)
++{
++	drops_do_clear = kstrtoul(buf, 0, 0);
++	return count;
++}
++
++static u32 tmu_drops[4][16];
++static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr,
++			      char *buf)
++{
++	ssize_t len = 0;
++	int id, dropnum;
++	int tmu, queue;
++	u32 val;
++	u32 dmem_addr;
++	int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0;
++	struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++	memset(class_drop_counter, 0, sizeof(class_drop_counter));
++	for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++		if (drops_do_clear)
++			pe_sync_stop(ctrl, (1 << id));
++		for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
++			dropnum++) {
++			dmem_addr = CLASS_DM_DROP_CNTR;
++			val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
++			class_drop_counter[dropnum] += val;
++			num_class_drops += val;
++			if (drops_do_clear)
++				pe_dmem_write(id, 0, dmem_addr, 4);
++		}
++		if (drops_do_clear)
++			pe_start(ctrl, (1 << id));
++	}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (drops_do_clear)
++		pe_sync_stop(ctrl, (1 << UTIL_ID));
++	for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
++		dmem_addr = UTIL_DM_DROP_CNTR;
++		val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));
++		util_drop_counter[dropnum] = val;
++		num_util_drops += val;
++		if (drops_do_clear)
++			pe_dmem_write(UTIL_ID, 0, dmem_addr, 4);
++	}
++	if (drops_do_clear)
++		pe_start(ctrl, (1 << UTIL_ID));
++#endif
++	for (tmu = 0; tmu < 4; tmu++) {
++		for (queue = 0; queue < 16; queue++) {
++			qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue],
++					  drops_do_clear);
++			num_tmu_drops += tmu_drops[tmu][queue];
++		}
++	}
++
++	if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0)
++		len += sprintf(buf + len, "No PE drops\n\n");
++
++	if (num_class_drops > 0) {
++		len += sprintf(buf + len, "Class PE drops --\n");
++		for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
++			dropnum++) {
++			if (class_drop_counter[dropnum] > 0)
++				len += sprintf(buf + len, "  %s: %d\n",
++					class_drop_description[dropnum],
++					class_drop_counter[dropnum]);
++		}
++		len += sprintf(buf + len, "\n");
++	}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (num_util_drops > 0) {
++		len += sprintf(buf + len, "Util PE drops --\n");
++		for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
++			if (util_drop_counter[dropnum] > 0)
++				len += sprintf(buf + len, "  %s: %d\n",
++					util_drop_description[dropnum],
++					util_drop_counter[dropnum]);
++		}
++		len += sprintf(buf + len, "\n");
++	}
++#endif
++	if (num_tmu_drops > 0) {
++		len += sprintf(buf + len, "TMU drops --\n");
++		for (tmu = 0; tmu < 4; tmu++) {
++			for (queue = 0; queue < 16; queue++) {
++				if (tmu_drops[tmu][queue] > 0)
++					len += sprintf(buf + len,
++						"  TMU%d-Q%d: %d\n"
++					, tmu, queue, tmu_drops[tmu][queue]);
++			}
++		}
++		len += sprintf(buf + len, "\n");
++	}
++
++	return len;
++}
++
++static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute
++					*attr, char *buf)
++{
++	return tmu_queues(buf, 0);
++}
++
++static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute
++					*attr, char *buf)
++{
++	return tmu_queues(buf, 1);
++}
++
++static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute
++					*attr, char *buf)
++{
++	return tmu_queues(buf, 2);
++}
++
++static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute
++					*attr, char *buf)
++{
++	return tmu_queues(buf, 3);
++}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,
++			    const char *buf, size_t count)
++{
++	util_do_clear = kstrtoul(buf, NULL, 0);
++	return count;
++}
++
++static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr,
++			     char *buf)
++{
++	ssize_t len = 0;
++	struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++	len += block_version(buf + len, UTIL_VERSION);
++
++	pe_sync_stop(ctrl, (1 << UTIL_ID));
++	len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS,
++					util_do_clear);
++	pe_start(ctrl, (1 << UTIL_ID));
++
++	len += sprintf(buf + len, "pe status:   %x\n", readl(UTIL_PE_STATUS));
++	len += sprintf(buf + len, "max buf cnt: %x\n",
++			readl(UTIL_MAX_BUF_CNT));
++	len += sprintf(buf + len, "tsq max cnt: %x\n",
++			readl(UTIL_TSQ_MAX_CNT));
++
++	return len;
++}
++#endif
++
++static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr,
++			    char *buf)
++{
++	ssize_t len = 0;
++
++	len += bmu(buf + len, 1, BMU1_BASE_ADDR);
++	len += bmu(buf + len, 2, BMU2_BASE_ADDR);
++
++	return len;
++}
++
++static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr,
++			    char *buf)
++{
++	ssize_t len = 0;
++
++	len += sprintf(buf + len, "hif:\n  ");
++	len += block_version(buf + len, HIF_VERSION);
++
++	len += sprintf(buf + len, "  tx curr bd:    %x\n",
++			readl(HIF_TX_CURR_BD_ADDR));
++	len += sprintf(buf + len, "  tx status:     %x\n",
++			readl(HIF_TX_STATUS));
++	len += sprintf(buf + len, "  tx dma status: %x\n",
++			readl(HIF_TX_DMA_STATUS));
++
++	len += sprintf(buf + len, "  rx curr bd:    %x\n",
++			readl(HIF_RX_CURR_BD_ADDR));
++	len += sprintf(buf + len, "  rx status:     %x\n",
++			readl(HIF_RX_STATUS));
++	len += sprintf(buf + len, "  rx dma status: %x\n",
++			readl(HIF_RX_DMA_STATUS));
++
++	len += sprintf(buf + len, "hif nocopy:\n  ");
++	len += block_version(buf + len, HIF_NOCPY_VERSION);
++
++	len += sprintf(buf + len, "  tx curr bd:    %x\n",
++			readl(HIF_NOCPY_TX_CURR_BD_ADDR));
++	len += sprintf(buf + len, "  tx status:     %x\n",
++			readl(HIF_NOCPY_TX_STATUS));
++	len += sprintf(buf + len, "  tx dma status: %x\n",
++			readl(HIF_NOCPY_TX_DMA_STATUS));
++
++	len += sprintf(buf + len, "  rx curr bd:    %x\n",
++			readl(HIF_NOCPY_RX_CURR_BD_ADDR));
++	len += sprintf(buf + len, "  rx status:     %x\n",
++			readl(HIF_NOCPY_RX_STATUS));
++	len += sprintf(buf + len, "  rx dma status: %x\n",
++			readl(HIF_NOCPY_RX_DMA_STATUS));
++
++	return len;
++}
++
++static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr,
++			    char *buf)
++{
++	ssize_t len = 0;
++
++	len += gpi(buf + len, 0, EGPI1_BASE_ADDR);
++	len += gpi(buf + len, 1, EGPI2_BASE_ADDR);
++	len += gpi(buf + len, 3, HGPI_BASE_ADDR);
++
++	return len;
++}
++
++static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute
++				*attr, char *buf)
++{
++	ssize_t len = 0;
++	struct pfe_memmon *memmon = &pfe->memmon;
++
++	len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n",
++		memmon->kernel_memory_allocated,
++		(memmon->kernel_memory_allocated + 1023) / 1024);
++
++	return len;
++}
++
++static ssize_t pfe_show_crc_revalidated(struct device *dev,
++					struct device_attribute *attr,
++					char *buf)
++{
++	u64 crc_validated = 0;
++	ssize_t len = 0;
++	int id, phyid;
++
++	len += sprintf(buf + len, "FCS re-validated by PFE:\n");
++
++	for (phyid = 0; phyid < 2; phyid++) {
++		crc_validated = 0;
++		for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++			crc_validated += be32_to_cpu(pe_dmem_read(id,
++				CLASS_DM_CRC_VALIDATED + (phyid * 4), 4));
++		}
++		len += sprintf(buf + len, "MAC %d:\n    count:%10llu\n",
++			       phyid, crc_validated);
++	}
++
++	return len;
++}
++
++#ifdef HIF_NAPI_STATS
++static ssize_t pfe_show_hif_napi_stats(struct device *dev,
++				       struct device_attribute *attr,
++				       char *buf)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct pfe *pfe = platform_get_drvdata(pdev);
++	ssize_t len = 0;
++
++	len += sprintf(buf + len, "sched:  %u\n",
++			pfe->hif.napi_counters[NAPI_SCHED_COUNT]);
++	len += sprintf(buf + len, "poll:   %u\n",
++			pfe->hif.napi_counters[NAPI_POLL_COUNT]);
++	len += sprintf(buf + len, "packet: %u\n",
++			pfe->hif.napi_counters[NAPI_PACKET_COUNT]);
++	len += sprintf(buf + len, "budget: %u\n",
++			pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]);
++	len += sprintf(buf + len, "desc:   %u\n",
++			pfe->hif.napi_counters[NAPI_DESC_COUNT]);
++	len += sprintf(buf + len, "full:   %u\n",
++			pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]);
++
++	return len;
++}
++
++static ssize_t pfe_set_hif_napi_stats(struct device *dev,
++				      struct device_attribute *attr,
++					const char *buf, size_t count)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct pfe *pfe = platform_get_drvdata(pdev);
++
++	memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters));
++
++	return count;
++}
++
++static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats,
++			pfe_set_hif_napi_stats);
++#endif
++
++static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class);
++static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util);
++#endif
++static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL);
++static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL);
++static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL);
++static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops);
++static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL);
++static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL);
++static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL);
++static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL);
++static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL);
++static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL);
++
++int pfe_sysfs_init(struct pfe *pfe)
++{
++	if (device_create_file(pfe->dev, &dev_attr_class))
++		goto err_class;
++
++	if (device_create_file(pfe->dev, &dev_attr_tmu))
++		goto err_tmu;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	if (device_create_file(pfe->dev, &dev_attr_util))
++		goto err_util;
++#endif
++
++	if (device_create_file(pfe->dev, &dev_attr_bmu))
++		goto err_bmu;
++
++	if (device_create_file(pfe->dev, &dev_attr_hif))
++		goto err_hif;
++
++	if (device_create_file(pfe->dev, &dev_attr_gpi))
++		goto err_gpi;
++
++	if (device_create_file(pfe->dev, &dev_attr_drops))
++		goto err_drops;
++
++	if (device_create_file(pfe->dev, &dev_attr_tmu0_queues))
++		goto err_tmu0_queues;
++
++	if (device_create_file(pfe->dev, &dev_attr_tmu1_queues))
++		goto err_tmu1_queues;
++
++	if (device_create_file(pfe->dev, &dev_attr_tmu2_queues))
++		goto err_tmu2_queues;
++
++	if (device_create_file(pfe->dev, &dev_attr_tmu3_queues))
++		goto err_tmu3_queues;
++
++	if (device_create_file(pfe->dev, &dev_attr_pfemem))
++		goto err_pfemem;
++
++	if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated))
++		goto err_crc_revalidated;
++
++#ifdef HIF_NAPI_STATS
++	if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats))
++		goto err_hif_napi_stats;
++#endif
++
++	return 0;
++
++#ifdef HIF_NAPI_STATS
++err_hif_napi_stats:
++	device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
++#endif
++
++err_crc_revalidated:
++	device_remove_file(pfe->dev, &dev_attr_pfemem);
++
++err_pfemem:
++	device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++
++err_tmu3_queues:
++	device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++
++err_tmu2_queues:
++	device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++
++err_tmu1_queues:
++	device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++
++err_tmu0_queues:
++	device_remove_file(pfe->dev, &dev_attr_drops);
++
++err_drops:
++	device_remove_file(pfe->dev, &dev_attr_gpi);
++
++err_gpi:
++	device_remove_file(pfe->dev, &dev_attr_hif);
++
++err_hif:
++	device_remove_file(pfe->dev, &dev_attr_bmu);
++
++err_bmu:
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	device_remove_file(pfe->dev, &dev_attr_util);
++
++err_util:
++#endif
++	device_remove_file(pfe->dev, &dev_attr_tmu);
++
++err_tmu:
++	device_remove_file(pfe->dev, &dev_attr_class);
++
++err_class:
++	return -1;
++}
++
++void pfe_sysfs_exit(struct pfe *pfe)
++{
++#ifdef HIF_NAPI_STATS
++	device_remove_file(pfe->dev, &dev_attr_hif_napi_stats);
++#endif
++	device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
++	device_remove_file(pfe->dev, &dev_attr_pfemem);
++	device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++	device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++	device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++	device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++	device_remove_file(pfe->dev, &dev_attr_drops);
++	device_remove_file(pfe->dev, &dev_attr_gpi);
++	device_remove_file(pfe->dev, &dev_attr_hif);
++	device_remove_file(pfe->dev, &dev_attr_bmu);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++	device_remove_file(pfe->dev, &dev_attr_util);
++#endif
++	device_remove_file(pfe->dev, &dev_attr_tmu);
++	device_remove_file(pfe->dev, &dev_attr_class);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_SYSFS_H_
++#define _PFE_SYSFS_H_
++
++#include <linux/proc_fs.h>
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);
++
++int pfe_sysfs_init(struct pfe *pfe);
++void pfe_sysfs_exit(struct pfe *pfe);
++
++#endif /* _PFE_SYSFS_H_ */
diff --git a/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch
new file mode 100644
index 0000000000..abb0a1e5ed
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/702-phy-Add-2.5G-SGMII-interface-mode.patch
@@ -0,0 +1,62 @@
+From 3823e4e1078a95e26b9a69e88c9bf862b0267e1c Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Date: Wed, 29 Nov 2017 15:27:57 +0530
+Subject: [PATCH] phy: Add 2.5G SGMII interface mode
+
+Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
+in existing phy_interface list
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+---
+ drivers/net/phy/phy-core.c | 1 +
+ drivers/net/phy/phylink.c  | 2 ++
+ include/linux/phy.h        | 3 +++
+ 3 files changed, 6 insertions(+)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -138,6 +138,7 @@ int phy_interface_num_ports(phy_interfac
+ 	case PHY_INTERFACE_MODE_RXAUI:
+ 	case PHY_INTERFACE_MODE_XAUI:
+ 	case PHY_INTERFACE_MODE_1000BASEKX:
++	case PHY_INTERFACE_MODE_2500SGMII:
+ 		return 1;
+ 	case PHY_INTERFACE_MODE_QSGMII:
+ 	case PHY_INTERFACE_MODE_QUSGMII:
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
+ 		return SPEED_1000;
+ 
+ 	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_2500SGMII:
+ 		return SPEED_2500;
+ 
+ 	case PHY_INTERFACE_MODE_5GBASER:
+@@ -526,6 +527,7 @@ unsigned long phylink_get_capabilities(p
+ 		break;
+ 
+ 	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_2500SGMII:
+ 		caps |= MAC_2500FD;
+ 		break;
+ 
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -165,6 +165,7 @@ typedef enum {
+ 	PHY_INTERFACE_MODE_10GKR,
+ 	PHY_INTERFACE_MODE_QUSGMII,
+ 	PHY_INTERFACE_MODE_1000BASEKX,
++	PHY_INTERFACE_MODE_2500SGMII,
+ 	PHY_INTERFACE_MODE_MAX,
+ } phy_interface_t;
+ 
+@@ -286,6 +287,8 @@ static inline const char *phy_modes(phy_
+ 		return "100base-x";
+ 	case PHY_INTERFACE_MODE_QUSGMII:
+ 		return "qusgmii";
++	case PHY_INTERFACE_MODE_2500SGMII:
++		return "sgmii-2500";
+ 	default:
+ 		return "unknown";
+ 	}
diff --git a/target/linux/layerscape/patches-6.6/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch b/target/linux/layerscape/patches-6.6/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch
new file mode 100644
index 0000000000..d49488ab4c
--- /dev/null
+++ b/target/linux/layerscape/patches-6.6/703-layerscape-6.1-fix-compilation-warning-for-fsl-ppfe-.patch
@@ -0,0 +1,239 @@
+From 1dc3a2e216d99adc2df022ab37eab32f61d80e0e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 8 May 2023 19:26:48 +0200
+Subject: [PATCH]  layerscape: 6.1: fix compilation warning for fsl ppfe driver
+
+Rework some desc dump and dummy pkt function to fix compilation warning.
+Fix compilation warning:
+drivers/staging/fsl_ppfe/pfe_hif.c: In function 'send_dummy_pkt_to_hif':
+drivers/staging/fsl_ppfe/pfe_hif.c:118:19: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
+  118 |         ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
+      |                   ^
+drivers/staging/fsl_ppfe/pfe_hif.c:122:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
+  122 |         lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
+      |                    ^
+drivers/staging/fsl_ppfe/pfe_hif.c: In function 'pfe_hif_desc_dump':
+drivers/staging/fsl_ppfe/pfe_hif.c:195:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+  195 |         desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
+      |                        ^
+drivers/staging/fsl_ppfe/pfe_hif.c:195:36: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+  195 |         desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
+      |                                    ^
+drivers/staging/fsl_ppfe/pfe_hif.c:207:19: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+  207 |         desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
+      |                   ^
+drivers/staging/fsl_ppfe/pfe_hif.c:207:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+  207 |         desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
+      |                               ^
+cc1: all warnings being treated as errors
+
+In file included from ./include/linux/kernel.h:19,
+                 from ./include/linux/list.h:9,
+                 from ./include/linux/wait.h:7,
+                 from ./include/linux/eventfd.h:13,
+                 from drivers/staging/fsl_ppfe/pfe_cdev.c:11:
+drivers/staging/fsl_ppfe/pfe_cdev.c: In function 'pfe_cdev_read':
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'int' [-Werror=format=]
+    5 | #define KERN_SOH        "\001"          /* ASCII Start Of Header */
+      |                         ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+  422 |                 _p_func(_fmt, ##__VA_ARGS__);                           \
+      |                         ^~~~
+./include/linux/printk.h:132:17: note: in expansion of macro 'printk'
+  132 |                 printk(fmt, ##__VA_ARGS__);             \
+      |                 ^~~~~~
+./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk'
+  580 |         no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+      |         ^~~~~~~~~
+./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH'
+   15 | #define KERN_DEBUG      KERN_SOH "7"    /* debug-level messages */
+      |                         ^~~~~~~~
+./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG'
+  580 |         no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+      |                   ^~~~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:42:17: note: in expansion of macro 'pr_debug'
+   42 |                 pr_debug("%u  %lu", link_states[ret].phy_id,
+      |                 ^~~~~~~~
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
+    5 | #define KERN_SOH        "\001"          /* ASCII Start Of Header */
+      |                         ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+  422 |                 _p_func(_fmt, ##__VA_ARGS__);                           \
+      |                         ^~~~
+./include/linux/printk.h:493:9: note: in expansion of macro 'printk'
+  493 |         printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+      |         ^~~~~~
+./include/linux/kern_levels.h:11:25: note: in expansion of macro 'KERN_SOH'
+   11 | #define KERN_ERR        KERN_SOH "3"    /* error conditions */
+      |                         ^~~~~~~~
+./include/linux/printk.h:493:16: note: in expansion of macro 'KERN_ERR'
+  493 |         printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+      |                ^~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:50:17: note: in expansion of macro 'pr_err'
+   50 |                 pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
+      |                 ^~~~~~
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 2 has type 'unsigned int' [-Werror=format=]
+    5 | #define KERN_SOH        "\001"          /* ASCII Start Of Header */
+      |                         ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+  422 |                 _p_func(_fmt, ##__VA_ARGS__);                           \
+      |                         ^~~~
+./include/linux/printk.h:132:17: note: in expansion of macro 'printk'
+  132 |                 printk(fmt, ##__VA_ARGS__);             \
+      |                 ^~~~~~
+./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk'
+  580 |         no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+      |         ^~~~~~~~~
+./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH'
+   15 | #define KERN_DEBUG      KERN_SOH "7"    /* debug-level messages */
+      |                         ^~~~~~~~
+./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG'
+  580 |         no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+      |                   ^~~~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:57:9: note: in expansion of macro 'pr_debug'
+   57 |         pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
+      |         ^~~~~~~~
+cc1: all warnings being treated as errors
+
+In file included from ./include/uapi/linux/posix_types.h:5,
+                 from ./include/uapi/linux/types.h:14,
+                 from ./include/linux/types.h:6,
+                 from ./include/linux/list.h:5,
+                 from ./include/linux/module.h:12,
+                 from drivers/staging/fsl_ppfe/pfe_sysfs.c:7:
+drivers/staging/fsl_ppfe/pfe_sysfs.c: In function 'pfe_set_util':
+./include/linux/stddef.h:8:14: error: passing argument 2 of 'kstrtoul' makes integer from pointer without a cast [-Werror=int-conversion]
+    8 | #define NULL ((void *)0)
+      |              ^~~~~~~~~~~
+      |              |
+      |              void *
+drivers/staging/fsl_ppfe/pfe_sysfs.c:538:39: note: in expansion of macro 'NULL'
+  538 |         util_do_clear = kstrtoul(buf, NULL, 0);
+      |                                       ^~~~
+In file included from ./include/linux/kernel.h:13,
+                 from ./include/linux/list.h:9:
+./include/linux/kstrtox.h:30:69: note: expected 'unsigned int' but argument is of type 'void *'
+   30 | static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigned long *res)
+      |                                                        ~~~~~~~~~~~~~^~~~
+cc1: all warnings being treated as errors
+
+With UTIL compiled on, fix compilation warning:
+drivers/staging/fsl_ppfe/pfe_hal.c: In function 'pe_load_ddr_section':
+drivers/staging/fsl_ppfe/pfe_hal.c:617:19: error: 'else' without a previous 'if'
+  617 |                 } else {
+      |                   ^~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:622:17: error: break statement not within loop or switch
+  622 |                 break;
+      |                 ^~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:624:9: error: case label not within a switch statement
+  624 |         case SHT_NOBITS:
+      |         ^~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:627:17: error: break statement not within loop or switch
+  627 |                 break;
+      |                 ^~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:629:9: error: 'default' label not within a switch statement
+  629 |         default:
+      |         ^~~~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c: At top level:
+drivers/staging/fsl_ppfe/pfe_hal.c:635:9: error: expected identifier or '(' before 'return'
+  635 |         return 0;
+      |         ^~~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:636:1: error: expected identifier or '(' before '}' token
+  636 | }
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ drivers/staging/fsl_ppfe/pfe_cdev.c  |  6 +++---
+ drivers/staging/fsl_ppfe/pfe_hif.c   | 14 +++++++-------
+ drivers/staging/fsl_ppfe/pfe_sysfs.c |  2 +-
+ 3 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/staging/fsl_ppfe/pfe_cdev.c
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c
+@@ -34,7 +34,7 @@ static ssize_t pfe_cdev_read(struct file
+ {
+ 	int ret = 0;
+ 
+-	pr_info("PFE CDEV attempt copying (%lu) size of user.\n",
++	pr_info("PFE CDEV attempt copying (%zu) size of user.\n",
+ 		sizeof(link_states));
+ 
+ 	pr_debug("Dump link_state on screen before copy_to_user\n");
+@@ -47,14 +47,14 @@ static ssize_t pfe_cdev_read(struct file
+ 	/* Copy to user the value in buffer sized len */
+ 	ret = copy_to_user(buf, &link_states, sizeof(link_states));
+ 	if (ret != 0) {
+-		pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
++		pr_err("Failed to send (%d)bytes of (%zu) requested.\n",
+ 		       ret, len);
+ 		return -EFAULT;
+ 	}
+ 
+ 	/* offset set back to 0 as there is contextual reading offset */
+ 	*off = 0;
+-	pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
++	pr_debug("Read of (%zu) bytes performed.\n", sizeof(link_states));
+ 
+ 	return sizeof(link_states);
+ }
+--- a/drivers/staging/fsl_ppfe/pfe_hif.c
++++ b/drivers/staging/fsl_ppfe/pfe_hif.c
+@@ -115,11 +115,11 @@ static void send_dummy_pkt_to_hif(void)
+ 		0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
+ 		0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
+ 
+-	ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
++	ddr_ptr = (void *)((uintptr_t)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
+ 	if (!ddr_ptr)
+ 		return;
+ 
+-	lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
++	lmem_ptr = (void *)((uintptr_t)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
+ 	if (!lmem_ptr)
+ 		return;
+ 
+@@ -186,16 +186,16 @@ static void pfe_hif_free_descr(struct pf
+ void pfe_hif_desc_dump(struct pfe_hif *hif)
+ {
+ 	struct hif_desc	*desc;
+-	unsigned long desc_p;
++	u64 desc_p;
+ 	int ii = 0;
+ 
+ 	pr_info("%s\n", __func__);
+ 
+ 	desc = hif->rx_base;
+-	desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
++	desc_p = ((void *)desc - hif->descr_baseaddr_v +
+ 			hif->descr_baseaddr_p);
+ 
+-	pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p);
++	pr_info("HIF Rx desc base %p physical %llx\n", desc, desc_p);
+ 	for (ii = 0; ii < hif->rx_ring_size; ii++) {
+ 		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
+ 			readl(&desc->status), readl(&desc->ctrl),
+@@ -204,10 +204,10 @@ void pfe_hif_desc_dump(struct pfe_hif *h
+ 	}
+ 
+ 	desc = hif->tx_base;
+-	desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
++	desc_p = ((void *)desc - hif->descr_baseaddr_v +
+ 			hif->descr_baseaddr_p);
+ 
+-	pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p);
++	pr_info("HIF Tx desc base %p physical %llx\n", desc, desc_p);
+ 	for (ii = 0; ii < hif->tx_ring_size; ii++) {
+ 		pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
+ 			readl(&desc->status), readl(&desc->ctrl),
+--- a/drivers/staging/fsl_ppfe/pfe_sysfs.c
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
+@@ -535,7 +535,7 @@ static ssize_t pfe_show_tmu3_queues(stru
+ static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,
+ 			    const char *buf, size_t count)
+ {
+-	util_do_clear = kstrtoul(buf, NULL, 0);
++	util_do_clear = kstrtoul(buf, 0, 0);
+ 	return count;
+ }
+ 
diff --git a/target/linux/loongarch64/Makefile b/target/linux/loongarch64/Makefile
new file mode 100644
index 0000000000..f8401c2b2e
--- /dev/null
+++ b/target/linux/loongarch64/Makefile
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+
+ARCH:=loongarch64
+BOARD:=loongarch64
+BOARDNAME:=Loongson LoongArch
+FEATURES:=audio display ext4 pcie boot-part rootfs-part rtc usb targz
+SUBTARGETS:=generic
+
+KERNEL_PATCHVER:=6.6
+
+KERNELNAME:=vmlinuz.efi dtbs
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+	partx-utils blkid e2fsprogs grub2-efi-loongarch64
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/loongarch64/base-files.mk b/target/linux/loongarch64/base-files.mk
new file mode 100644
index 0000000000..e2b7d05f57
--- /dev/null
+++ b/target/linux/loongarch64/base-files.mk
@@ -0,0 +1,8 @@
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL))
+ifeq ($(GRUB_SERIAL),)
+$(error This platform requires CONFIG_TARGET_SERIAL be set!)
+endif
+
+define Package/base-files/install-target
+	$(SED) "s#@GRUB_SERIAL@#$(GRUB_SERIAL)#" $(1)/etc/inittab
+endef
diff --git a/target/linux/loongarch64/base-files/etc/inittab b/target/linux/loongarch64/base-files/etc/inittab
new file mode 100644
index 0000000000..584a4114d4
--- /dev/null
+++ b/target/linux/loongarch64/base-files/etc/inittab
@@ -0,0 +1,4 @@
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+@GRUB_SERIAL@::askfirst:/usr/libexec/login.sh
+tty0::askfirst:/usr/libexec/login.sh
diff --git a/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi
new file mode 100644
index 0000000000..4d9e92e544
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+sanitize_name_loongarch64() {
+	sed -e '
+		y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/;
+		s/[^a-z0-9_-]\+/-/g;
+		s/^-//;
+		s/-$//;
+	' "$@"
+}
+
+do_sysinfo_loongarch64() {
+	local vendor product file
+
+	for file in sys_vendor board_vendor; do
+		vendor="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor" in
+		empty | \
+		System\ manufacturer | \
+		To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		esac
+		[ -n "$vendor" ] && break
+	done
+
+	for file in product_name board_name; do
+		product="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+		case "$vendor:$product" in
+		?*:empty | \
+		?*:System\ Product\ Name | \
+		?*:To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+			continue
+			;;
+		?*:?*)
+			break
+			;;
+		esac
+	done
+
+	[ -d "/sys/firmware/devicetree/base" ] && return
+
+	[ -n "$vendor" -a -n "$product" ] || return
+
+	mkdir -p /tmp/sysinfo
+
+	echo "$vendor $product" > /tmp/sysinfo/model
+
+	sanitize_name_loongarch64 /tmp/sysinfo/model > /tmp/sysinfo/board_name
+}
+
+boot_hook_add preinit_main do_sysinfo_loongarch64
diff --git a/target/linux/loongarch64/base-files/lib/preinit/79_move_config b/target/linux/loongarch64/base-files/lib/preinit/79_move_config
new file mode 100644
index 0000000000..864d4dfa64
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/preinit/79_move_config
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+move_config() {
+	local partdev parttype=ext4
+
+	. /lib/upgrade/common.sh
+
+	if export_bootdevice && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		if mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt; then
+			if [ -f "/mnt/$BACKUP_FILE" ]; then
+				mv -f "/mnt/$BACKUP_FILE" /
+			fi
+			umount /mnt
+		fi
+	fi
+}
+
+boot_hook_add preinit_mount_root move_config
diff --git a/target/linux/loongarch64/base-files/lib/upgrade/platform.sh b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh
new file mode 100644
index 0000000000..a0d4c2dcec
--- /dev/null
+++ b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+RAMFS_COPY_BIN="/usr/sbin/blkid"
+
+platform_check_image() {
+	local board=$(board_name)
+	local diskdev partdev diff
+	[ "$#" -gt 1 ] && return 1
+
+	v "Board is ${board}"
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_check_image: Unable to determine upgrade device"
+		return 1
+	}
+
+	get_partitions "/dev/$diskdev" bootdisk
+
+	v "Extract boot sector from the image"
+	get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+	get_partitions /tmp/image.bs image
+
+	#compare tables
+	diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+
+	rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
+
+	if [ -n "$diff" ]; then
+		v "Partition layout has changed. Full image will be written."
+		ask_bool 0 "Abort" && exit 1
+		return 0
+	fi
+}
+
+platform_copy_config() {
+	local partdev parttype=ext4
+
+	if export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
+		umount /mnt
+	else
+		v "ERROR: Unable to find partition to copy config data to"
+	fi
+
+	sleep 5
+}
+
+# To avoid writing over any firmware
+# files (e.g ubootefi.var or firmware/X/ aka EBBR)
+# Copy efi/openwrt and efi/boot from the new image
+# to the existing ESP
+platform_do_upgrade_efi_system_partition() {
+	local image_file=$1
+	local target_partdev=$2
+	local image_efisp_start=$3
+	local image_efisp_size=$4
+
+	v "Updating ESP on ${target_partdev}"
+	NEW_ESP_DIR="/mnt/new_esp_loop"
+	CUR_ESP_DIR="/mnt/cur_esp"
+	mkdir "${NEW_ESP_DIR}"
+	mkdir "${CUR_ESP_DIR}"
+
+	get_image_dd "$image_file" of="/tmp/new_efi_sys_part.img" \
+		skip="$image_efisp_start" count="$image_efisp_size"
+
+	mount -t vfat -o loop -o ro /tmp/new_efi_sys_part.img "${NEW_ESP_DIR}"
+	if [ ! -d "${NEW_ESP_DIR}/efi/boot" ]; then
+		v "ERROR: Image does not contain EFI boot files (/efi/boot)"
+		return 1
+	fi
+
+	mount -t vfat "/dev/$partdev" "${CUR_ESP_DIR}"
+
+	for d in $(find "${NEW_ESP_DIR}/efi/" -mindepth 1 -maxdepth 1 -type d); do
+		v "Copying ${d}"
+		newdir_bname=$(basename "${d}")
+		rm -rf "${CUR_ESP_DIR}/efi/${newdir_bname}"
+		cp -r "${d}" "${CUR_ESP_DIR}/efi"
+		v "rm -rf \"${CUR_ESP_DIR}/efi/${newdir_bname}\""
+		v "cp -r \"${d}\" \"${CUR_ESP_DIR}/efi\""
+	done
+
+	umount "${NEW_ESP_DIR}"
+	umount "${CUR_ESP_DIR}"
+}
+
+platform_do_upgrade() {
+	local board=$(board_name)
+	local diskdev partdev diff
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		v "platform_do_upgrade: Unable to determine upgrade device"
+		return 1
+	}
+
+	sync
+
+	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+		get_partitions "/dev/$diskdev" bootdisk
+
+		v "Extract boot sector from the image"
+		get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+		get_partitions /tmp/image.bs image
+
+		#compare tables
+		diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+	else
+		diff=1
+	fi
+
+	# Only change the partition table if sysupgrade -p is set,
+	# otherwise doing so could interfere with embedded "single storage"
+	# (e.g SoC boot from SD card) setups, as well as other user
+	# created storage (like uvol)
+	if [ -n "$diff" ] && [ "${UPGRADE_OPT_SAVE_PARTITIONS}" = "0" ]; then
+		# Need to remove partitions before dd, otherwise the partitions
+		# that are added after will have minor numbers offset
+		partx -d - "/dev/$diskdev"
+
+		get_image_dd "$1" of="/dev/$diskdev" bs=4096 conv=fsync
+
+		# Separate removal and addtion is necessary; otherwise, partition 1
+		# will be missing if it overlaps with the old partition 2
+		partx -a - "/dev/$diskdev"
+
+		return 0
+	fi
+
+	#iterate over each partition from the image and write it to the boot disk
+	while read part start size; do
+		if export_partdevice partdev $part; then
+			v "Writing image to /dev/$partdev..."
+			if [ "$part" = "1" ]; then
+				platform_do_upgrade_efi_system_partition \
+					$1 $partdev $start $size || return 1
+			else
+				v "Normal partition, doing DD"
+				get_image_dd "$1" of="/dev/$partdev" ibs=512 obs=1M skip="$start" \
+					count="$size" conv=fsync
+			fi
+		else
+			v "Unable to find partition $part device, skipped."
+		fi
+	done < /tmp/partmap.image
+
+	local parttype=ext4
+
+	if (blkid > /dev/null) && export_partdevice partdev 1; then
+		part_magic_fat "/dev/$partdev" && parttype=vfat
+		mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+		if export_partdevice partdev 2; then
+			THIS_PART_BLKID=$(blkid -o value -s PARTUUID "/dev/${partdev}")
+			v "Setting rootfs PARTUUID=${THIS_PART_BLKID}"
+			sed -i "s/\(PARTUUID=\)[a-f0-9-]\+/\1${THIS_PART_BLKID}/ig" \
+				/mnt/efi/openwrt/grub.cfg
+		fi
+		umount /mnt
+	fi
+	# Provide time for the storage medium to flush before system reset
+	# (despite the sync/umount it appears NVMe etc. do it in the background)
+	sleep 5
+}
diff --git a/target/linux/loongarch64/config-6.6 b/target/linux/loongarch64/config-6.6
new file mode 100644
index 0000000000..596301f0f4
--- /dev/null
+++ b/target/linux/loongarch64/config-6.6
@@ -0,0 +1,806 @@
+# CONFIG_16KB_2LEVEL is not set
+CONFIG_16KB_3LEVEL=y
+# CONFIG_4KB_3LEVEL is not set
+# CONFIG_4KB_4LEVEL is not set
+CONFIG_64BIT=y
+# CONFIG_64KB_2LEVEL is not set
+# CONFIG_64KB_3LEVEL is not set
+CONFIG_AC97_BUS=y
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_FFH is not set
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_MCFG=y
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_SLEEP=y
+# CONFIG_ACPI_SPCR_TABLE is not set
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_DISABLE_KASAN_INLINE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_IOREMAP is not set
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=12
+CONFIG_ARCH_MMAP_RND_BITS_MAX=18
+CONFIG_ARCH_MMAP_RND_BITS_MIN=12
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STRICT_ALIGN=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+# CONFIG_ARCH_WRITECOMBINE is not set
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_FORCE=y
+# CONFIG_ATA_SFF is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_SED_OPAL=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CDROM=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_BPF is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_HUGETLB is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_LOONGSON2 is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_VC3 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_HAS_FPU=y
+CONFIG_CPU_HAS_LASX=y
+CONFIG_CPU_HAS_LBT=y
+CONFIG_CPU_HAS_LSX=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_LOONGARCH is not set
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_DCB=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
+# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
+# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+# CONFIG_DMAPOOL_TEST is not set
+CONFIG_DMA_CMA=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DRM=y
+# CONFIG_DRM_ACCEL is not set
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_LOONGSON=y
+CONFIG_DRM_PANEL=y
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+CONFIG_DRM_TTM=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+CONFIG_EFI_ZBOOT=y
+CONFIG_ELF_CORE=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_FAILOVER=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FANOTIFY=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_EFI=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_6x10 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_SUN8x16 is not set
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_CACHE=y
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+# CONFIG_GPIO_DS4520 is not set
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LOONGSON_64BIT is not set
+CONFIG_HAMRADIO=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_LS2X is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_STACK_ALL_ZERO=y
+# CONFIG_INIT_STACK_NONE is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_LOONGARCH_CPU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+CONFIG_KCMP=y
+CONFIG_KEYS=y
+CONFIG_KSM=y
+CONFIG_L1_CACHE_SHIFT=6
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_GROUP_MULTICOLOR is not set
+# CONFIG_LEDS_LM3697 is not set
+# CONFIG_LEDS_PCA995X is not set
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBFDT=y
+CONFIG_LIST_HARDENED=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOONGARCH=y
+CONFIG_LOONGARCH_PLATFORM_DEVICES=y
+# CONFIG_LOONGSON2_GUTS is not set
+# CONFIG_LOONGSON2_PM is not set
+# CONFIG_LOONGSON2_THERMAL is not set
+CONFIG_LOONGSON_EIOINTC=y
+CONFIG_LOONGSON_HTVEC=y
+CONFIG_LOONGSON_LAPTOP=y
+CONFIG_LOONGSON_LIOINTC=y
+CONFIG_LOONGSON_PCH_LPC=y
+CONFIG_LOONGSON_PCH_MSI=y
+CONFIG_LOONGSON_PCH_PIC=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo,bpf"
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_LOONGSON64=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+# CONFIG_MAX31827 is not set
+CONFIG_MAX_SKB_FRAGS=17
+# CONFIG_MEMCG is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+# CONFIG_MFD_MAX5970 is not set
+# CONFIG_MFD_MAX77541 is not set
+# CONFIG_MFD_RK8XX_I2C is not set
+# CONFIG_MFD_RK8XX_SPI is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+CONFIG_MIGRATION=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MODULE_DEBUG is not set
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=64
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_VERBOSE_ERRORS=y
+# CONFIG_N_HDLC is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OID_REGISTRY=y
+# CONFIG_OVERLAY_FS_DEBUG is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_EXTENSION=y
+CONFIG_PAGE_POISONING=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DPC=y
+# CONFIG_PCIE_EDR is not set
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+# CONFIG_PCI_DYNAMIC_OF_NODES is not set
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOONGSON=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCPU_DEV_REFCNT=y
+# CONFIG_PDS_CORE is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_3LEVEL=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_DEBUG=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+# CONFIG_RANDOM_KMALLOC_CACHES is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_LOONGSON=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_HOST=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SENSORS_HS3001 is not set
+# CONFIG_SENSORS_MC34VR500 is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+# CONFIG_SLAB_DEPRECATED is not set
+# CONFIG_SLUB_TINY is not set
+CONFIG_SMP=y
+CONFIG_SND=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_CTL_LED=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_HDA=y
+# CONFIG_SND_HDA_CODEC_ANALOG is not set
+# CONFIG_SND_HDA_CODEC_CA0110 is not set
+# CONFIG_SND_HDA_CODEC_CA0132 is not set
+# CONFIG_SND_HDA_CODEC_CIRRUS is not set
+# CONFIG_SND_HDA_CODEC_CMEDIA is not set
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+# CONFIG_SND_HDA_CODEC_REALTEK is not set
+# CONFIG_SND_HDA_CODEC_SI3054 is not set
+# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
+# CONFIG_SND_HDA_CODEC_VIA is not set
+CONFIG_SND_HDA_CORE=y
+# CONFIG_SND_HDA_CTL_DEV_ID is not set
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_HWDEP=y
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+CONFIG_SND_HDA_INTEL=y
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_RECONFIG is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
+# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
+CONFIG_SND_HWDEP=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQ_DEVICE=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_SEQ_MIDI=y
+CONFIG_SND_SEQ_MIDI_EVENT=y
+CONFIG_SND_SEQ_VIRMIDI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_LOONGSON_CARD=y
+CONFIG_SND_SOC_LOONGSON_I2S_PCI=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_VIRMIDI=y
+CONFIG_SND_VMASTER=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_LOONGSON_CORE=y
+CONFIG_SPI_LOONGSON_PCI=y
+CONFIG_SPI_LOONGSON_PLATFORM=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_PCI1XXXX is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+# CONFIG_SWIOTLB_DYNAMIC is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y
+CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+# CONFIG_TEST_DHRY is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_QUOTA is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UCS2_STRING=y
+# CONFIG_UEVENT_HELPER is not set
+# CONFIG_UNWINDER_GUESS is not set
+CONFIG_UNWINDER_PROLOGUE=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UAS=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USERFAULTFD=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+# CONFIG_VCAP is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIRTIO_VSOCKETS_COMMON=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VSOCKETS=y
+CONFIG_VSOCKETS_LOOPBACK=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WPCM450_SOC is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+# CONFIG_ZONEFS_FS is not set
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/loongarch64/generic/target.mk b/target/linux/loongarch64/generic/target.mk
new file mode 100644
index 0000000000..f5cb1fb19b
--- /dev/null
+++ b/target/linux/loongarch64/generic/target.mk
@@ -0,0 +1 @@
+BOARDNAME:=Generic
diff --git a/target/linux/loongarch64/image/Makefile b/target/linux/loongarch64/image/Makefile
new file mode 100644
index 0000000000..7000356292
--- /dev/null
+++ b/target/linux/loongarch64/image/Makefile
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+GRUB2_VARIANT =
+GRUB_TERMINALS =
+GRUB_SERIAL_CONFIG =
+GRUB_TERMINAL_CONFIG =
+GRUB_CONSOLE_CMDLINE =
+
+ifneq ($(CONFIG_GRUB_CONSOLE),)
+  GRUB_CONSOLE_CMDLINE += console=tty0
+  GRUB_TERMINALS += console
+endif
+
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL))
+
+GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8$(if $(CONFIG_GRUB_FLOWCONTROL),r,)
+GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off)
+GRUB_TERMINALS += serial
+
+GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)
+
+ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+ROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02)
+GPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+GPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/'))
+
+GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))
+GRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE))
+
+BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))
+
+define Build/combined
+	$(INSTALL_DIR) $@.boot/
+	$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/efi/openwrt/
+	$(INSTALL_DIR) $@.boot/efi/boot
+	$(CP) $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi $@.boot/efi/boot/
+	KERNELPARTTYPE=ef FAT_TYPE="32" PADDING="1" SIGNATURE="$(IMG_PART_SIGNATURE)" \
+		GUID="$(IMG_PART_DISKGUID)" $(SCRIPT_DIR)/gen_image_generic.sh \
+		$@ \
+		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		256
+endef
+
+define Build/grub-config
+	rm -fR $@.boot
+	$(INSTALL_DIR) $@.boot/efi/openwrt/
+	sed \
+		-e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
+		-e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
+		-e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \
+		-e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \
+		-e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \
+		-e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
+		-e 's#@TITLE@#$(GRUB_TITLE)#g' \
+		-e 's#@KERNEL_NAME@#$(KERNEL_NAME)#g' \
+		./grub-$(1).cfg > $@.boot/efi/openwrt/grub.cfg
+endef
+
+define Device/Default
+  KERNEL_INSTALL := 1
+  ARTIFACTS := $$(ARTIFACTS-y)
+  SUPPORTED_DEVICES :=
+endef
+
+define Device/generic
+  DEVICE_VENDOR := Generic
+  DEVICE_MODEL := LoongArch64
+  DEVICE_PACKAGES += kmod-r8169 kmod-drm-amdgpu
+  KERNEL := kernel-bin
+  KERNEL_NAME := vmlinuz.efi
+  IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE)
+  IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip
+  IMAGE/combined-efi.img := grub-config efi | combined | append-metadata
+  IMAGE/combined-efi.img.gz := grub-config efi | combined | gzip | append-metadata
+  ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y)
+    IMAGES-y := rootfs.img.gz
+    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img.gz
+  else
+    IMAGES-y := rootfs.img
+    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img
+  endif
+  IMAGES := $$(IMAGES-y)
+endef
+TARGET_DEVICES += generic
+
+$(eval $(call BuildImage))
diff --git a/target/linux/loongarch64/image/grub-efi.cfg b/target/linux/loongarch64/image/grub-efi.cfg
new file mode 100644
index 0000000000..fd329e41e0
--- /dev/null
+++ b/target/linux/loongarch64/image/grub-efi.cfg
@@ -0,0 +1,14 @@
+@SERIAL_CONFIG@
+@TERMINAL_CONFIG@
+
+set default="0"
+set timeout="@TIMEOUT@"
+
+menuentry "@TITLE@" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
+menuentry "@TITLE@ (failsafe)" {
+	search --set=root --label kernel
+	linux /efi/openwrt/@KERNEL_NAME@ failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile
index f98aedf577..319e06579e 100644
--- a/target/linux/malta/Makefile
+++ b/target/linux/malta/Makefile
@@ -10,7 +10,7 @@ SUBTARGETS:=le be le64 be64
 INITRAMFS_EXTRA_FILES:=
 FEATURES:=cpiogz ext4 ramdisk squashfs targz
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/malta/config-6.1 b/target/linux/malta/config-6.1
deleted file mode 100644
index 9ce439ee38..0000000000
--- a/target/linux/malta/config-6.1
+++ /dev/null
@@ -1,265 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ATA=y
-CONFIG_ATA_PIIX=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_BOOT_ELF32=y
-CONFIG_BUILTIN_DTB=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-# CONFIG_CPU_HAS_SMARTMIPS is not set
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_MICROMIPS is not set
-# CONFIG_CPU_MIPS32 is not set
-# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS32_R5 is not set
-# CONFIG_CPU_MIPS32_R5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R6 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_MIPS64_R6 is not set
-# CONFIG_CPU_MIPSR1 is not set
-# CONFIG_CPU_MIPSR2 is not set
-# CONFIG_CPU_MIPSR2_IRQ_EI is not set
-# CONFIG_CPU_MIPSR2_IRQ_VI is not set
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-# CONFIG_CPU_NEVADA is not set
-CONFIG_CPU_R4K_CACHE_TLB=y
-# CONFIG_CPU_RM7000 is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_I8259=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MD=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_BONITO64=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_EXTERNAL_TIMER=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MALTA=y
-CONFIG_MIPS_MSC=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-CONFIG_MIPS_NO_APPENDED_DTB=y
-CONFIG_MIPS_NR_CPU_NR_MAP=2
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CFI_STAA=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_PADATA=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_LEGACY=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PCI_GT64XXX_PCI0=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_PIIX4_POWEROFF=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QFMT_V2=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_TREE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELAY=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SATA_HOST=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SRCU=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R6=y
-CONFIG_SYS_HAS_CPU_MIPS64_R1=y
-CONFIG_SYS_HAS_CPU_MIPS64_R2=y
-CONFIG_SYS_HAS_CPU_MIPS64_R6=y
-CONFIG_SYS_HAS_CPU_NEVADA=y
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MICROMIPS=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_RELOCATABLE=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMARTMIPS=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_VPE_LOADER=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_VXFS_FS=y
-CONFIG_WAR_ICACHE_REFILLS=y
-CONFIG_XPS=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/malta/config-6.6 b/target/linux/malta/config-6.6
new file mode 100644
index 0000000000..7c72f49265
--- /dev/null
+++ b/target/linux/malta/config-6.6
@@ -0,0 +1,285 @@
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ATA=y
+CONFIG_ATA_PIIX=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_DTB=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_CPU_HAS_SMARTMIPS is not set
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_MICROMIPS is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS32_R5 is not set
+# CONFIG_CPU_MIPS32_R5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R6 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_MIPS64_R6 is not set
+# CONFIG_CPU_MIPSR1 is not set
+# CONFIG_CPU_MIPSR2 is not set
+# CONFIG_CPU_MIPSR2_IRQ_EI is not set
+# CONFIG_CPU_MIPSR2_IRQ_VI is not set
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+# CONFIG_CPU_NEVADA is not set
+CONFIG_CPU_R4K_CACHE_TLB=y
+# CONFIG_CPU_RM7000 is not set
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_I8253=y
+CONFIG_I8253_LOCK=y
+CONFIG_I8259=y
+CONFIG_INPUT=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MD=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_BONITO64=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_GIC=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+CONFIG_MIPS_MALTA=y
+CONFIG_MIPS_MSC=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NO_APPENDED_DTB=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PATA_LEGACY=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PCI_GT64XXX_PCI0=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QFMT_V2=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_TREE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SATA_HOST=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R6=y
+CONFIG_SYS_HAS_CPU_MIPS64_R1=y
+CONFIG_SYS_HAS_CPU_MIPS64_R2=y
+CONFIG_SYS_HAS_CPU_MIPS64_R6=y
+CONFIG_SYS_HAS_CPU_NEVADA=y
+CONFIG_SYS_HAS_CPU_RM7000=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MICROMIPS=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_RELOCATABLE=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMARTMIPS=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VXFS_FS=y
+CONFIG_WAR_ICACHE_REFILLS=y
+CONFIG_XPS=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile
index 288fb537a7..f667081253 100644
--- a/target/linux/mediatek/Makefile
+++ b/target/linux/mediatek/Makefile
@@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM
 SUBTARGETS:=mt7622 mt7623 mt7629 filogic
 FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += \
diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
index f58f709e1c..e9cb4f921d 100644
--- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
+++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh
@@ -10,7 +10,9 @@ unielec,u7623-02)
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	;;
 bananapi,bpi-r3|\
-bananapi,bpi-r3-mini)
+bananapi,bpi-r3-mini|\
+bananapi,bpi-r4|\
+bananapi,bpi-r4-poe)
 	[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
 		fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
 	[ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] &&
diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
index 2bff09b2b2..6dfa52c291 100644
--- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
+++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface
@@ -1,10 +1,7 @@
 set_preinit_iface() {
 	case $(board_name) in
-	smartrg,sdg-8622|\
-	smartrg,sdg-8632)
-		ip link set lan up
-		ifname=lan
-		;;
+	cudy,m3000-v1|\
+	cudy,tr3000-v1|\
 	glinet,gl-mt3000)
 		ip link set eth1 up
 		ifname=eth1
@@ -15,6 +12,11 @@ set_preinit_iface() {
 		ip link set eth0 up
 		ifname=eth0
 		;;
+	smartrg,sdg-8622|\
+	smartrg,sdg-8632)
+		ip link set lan up
+		ifname=lan
+		;;
 	xiaomi,mi-router-ax3000t|\
 	xiaomi,mi-router-ax3000t-ubootmod|\
 	xiaomi,mi-router-wr30u-stock|\
diff --git a/target/linux/mediatek/dts/mt7622-netgear-wax206.dts b/target/linux/mediatek/dts/mt7622-netgear-wax206.dts
index ce1cd46d2d..524a498740 100644
--- a/target/linux/mediatek/dts/mt7622-netgear-wax206.dts
+++ b/target/linux/mediatek/dts/mt7622-netgear-wax206.dts
@@ -143,13 +143,13 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		switch@0 {
+		switch@1f {
 			compatible = "mediatek,mt7531";
+			reg = <31>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			interrupt-parent = <&pio>;
 			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
-			reg = <0>;
 			reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
 
 			ports {
diff --git a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi
index a4e443a0fb..fedf8b8596 100644
--- a/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi
+++ b/target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi
@@ -121,17 +121,16 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		mt7530: switch@0 {
-			compatible = "mediatek,mt7530";
+		mt7530: switch@1f {
 		};
 	};
 };
 
 &mt7530 {
 	compatible = "mediatek,mt7530";
+	reg = <31>;
 	#address-cells = <1>;
 	#size-cells = <0>;
-	reg = <0>;
 	pinctrl-names = "default";
 	mediatek,mcm;
 	resets = <&ethsys 2>;
diff --git a/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts
new file mode 100644
index 0000000000..85bdabe474
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-cudy-m3000-v1.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "mt7981.dtsi"
+
+/ {
+	model = "Cudy M3000 v1";
+	compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb";
+
+	aliases {
+		label-mac-device = &gmac0;
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: internet-white {
+			function = LED_FUNCTION_WAN_ONLINE;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		internet-red {
+			function = LED_FUNCTION_WAN_ONLINE;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		wan {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		lan {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+		phy-handle = <&rtl8221b_phy>;
+
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_bdinfo_de00 1>;
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_bdinfo_de00 0>;
+	};
+};
+
+&mdio_bus {
+	rtl8221b_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <1>;
+
+		reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+
+		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <100000>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+
+	status = "okay";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mediatek,nmbm;
+			mediatek,bmt-max-ratio = <1>;
+			mediatek,bmt-max-reserved-blocks = <64>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x0000000 0x0100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x0180000 0x0200000>;
+				read-only;
+			};
+
+			bdinfo: partition@380000 {
+				label = "bdinfo";
+				reg = <0x0380000 0x0040000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_bdinfo_de00: macaddr@de00 {
+						#nvmem-cell-cells = <1>;
+						compatible = "mac-base";
+						reg = <0xde00 0x6>;
+					};
+				};
+			};
+
+			partition@3c0000 {
+				label = "FIP";
+				reg = <0x03c0000 0x0200000>;
+			};
+
+			partition@5c0000 {
+				label = "ubi";
+				reg = <0x05c0000 0x4000000>;
+			};
+		};
+	};
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+	mediatek,mtd-eeprom = <&factory 0x0>;
+};
diff --git a/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts
new file mode 100644
index 0000000000..2d18af860e
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v1.dts
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "mt7981.dtsi"
+
+/ {
+	model = "Cudy TR3000 v1";
+	compatible = "cudy,tr3000-v1", "mediatek,mt7981-spim-snand-rfb";
+
+	aliases {
+		label-mac-device = &gmac1;
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		mode {
+			label = "mode";
+			linux,input-type = <EV_SW>;
+			linux,code = <BTN_0>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: led_0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led_1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+	};
+
+	usb_vbus: regulator-usb {
+		compatible = "regulator-fixed";
+
+		regulator-name = "usb-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&pio 9 GPIO_ACTIVE_LOW>;
+		regulator-boot-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+		phy-handle = <&phy1>;
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_bdinfo_de00 1>;
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_bdinfo_de00 0>;
+	};
+};
+
+&mdio_bus {
+	phy1: phy@1 {
+		reg = <1>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		phy-mode = "2500base-x";
+		reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <100000>;
+		realtek,aldps-enable;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+		spi-cal-addrlen = <5>;
+		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		mediatek,nmbm;
+		mediatek,bmt-max-ratio = <1>;
+		mediatek,bmt-max-reserved-blocks = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x00000 0x0100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+				read-only;
+			};
+
+			factory: partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x0200000>;
+				read-only;
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+				};
+			};
+
+			partition@380000 {
+				label = "bdinfo";
+				reg = <0x380000 0x0040000>;
+				read-only;
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_bdinfo_de00: macaddr@de00 {
+						compatible = "mac-base";
+						reg = <0xde00 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+
+			};
+
+			partition@3C0000 {
+				label = "FIP";
+				reg = <0x3C0000 0x0200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x5C0000 0x4000000>;
+				compatible = "linux,ubi";
+			};
+		};
+	};
+};
+
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&xhci {
+	status = "okay";
+	vbus-supply = <&usb_vbus>;
+};
+
+&wifi {
+	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+};
diff --git a/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts
new file mode 100644
index 0000000000..1ac815d8b4
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-nokia-ea0326gmp.dts
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "mt7981.dtsi"
+
+/ {
+	model = "Nokia EA0326GMP";
+	compatible = "nokia,ea0326gmp", "mediatek,mt7981";
+
+	aliases {
+		led-boot = &power_led;
+		led-running = &power_led;
+		led-failsafe = &power_led;
+		led-upgrade = &power_led;
+		label-mac-device = &gmac1;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		rootdisk = <&ubi_rootdisk>;
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		reg = <0 0x40000000 0 0x10000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		button-wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		power_led: led-0 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		led-2 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		led-3 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		led-4 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led-5 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WPS;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		nvmem-cells = <&macaddr_factory_28 0>;
+		nvmem-cell-names = "mac-address";
+
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+
+		nvmem-cells = <&macaddr_factory_28 3>;
+		nvmem-cell-names = "mac-address";
+	};
+};
+
+&mdio_bus {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000 0x0100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+			};
+
+			partition@180000 {
+				label = "factory";
+				reg = <0x180000 0x0200000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+
+					macaddr_factory_28: macaddr@28 {
+						compatible = "mac-base";
+						reg = <0x28 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@380000 {
+				label = "fip";
+				reg = <0x380000 0x0200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "config";
+				reg = <0x580000 0x200000>;
+				read-only;
+			};
+
+			partition@780000 {
+				label = "config2";
+				reg = <0x780000 0x200000>;
+				read-only;
+			};
+
+			partition@980000 {
+				compatible = "linux,ubi";
+				label = "ubi";
+				reg = <0x980000 0x7680000>;
+
+				volumes {
+					ubi_rootdisk: ubi-volume-fit {
+						volname = "fit";
+					};
+				};
+			};
+		};
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			label = "lan1";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan2";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan3";
+		};
+
+		port@6 {
+			reg = <6>;
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+	status = "okay";
+};
diff --git a/target/linux/mediatek/dts/mt7981b-openwrt-one.dts b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts
new file mode 100644
index 0000000000..b2223f8d76
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7981b-openwrt-one.dts
@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include "mt7981.dtsi"
+
+/ {
+	model = "OpenWrt One";
+	compatible = "openwrt,one", "mediatek,mt7981";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		serial0 = &uart0;
+		led-boot = &led_status_white;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_green;
+		led-upgrade = &led_status_green;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		rootdisk = <&ubi_fit_volume>;
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		user {
+			label = "user";
+			linux,code = <BTN_0>;
+			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		led_status_white: led-0 {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+			pwms = <&pwm 0 10000>;
+			linux,default-trigger = "pattern";
+			led-pattern = <0 500 25 500>;
+		};
+
+		led_status_green: led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			pwms = <&pwm 1 10000>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_status_red: led-0 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_AMBER>;
+			gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+		};
+
+		led-2 {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-export {
+		compatible = "gpio-export";
+
+		 gpio-0 {
+			gpio-export,name = "mikrobus-reset";
+			gpio-export,output = <1>;
+			gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		gpio-1 {
+			gpio-export,name = "watchdog-enable";
+			gpio-export,output = <1>;
+			gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		gpio-2 {
+			gpio-export,name = "usb-enable";
+			gpio-export,output = <1>;
+			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-watchdog {
+		compatible = "linux,wdt-gpio";
+		gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+		hw_algo = "toggle";
+		hw_margin_ms = <25000>;
+		always-running;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-handle = <&phy15>;
+		phy-mode = "2500base-x";
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_factory_4>;
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_factory_a>;
+	};
+};
+
+&mdio_bus {
+	phy15: phy@f {
+		reg = <0xf>;
+
+		airoha,pnswap-rx;
+
+		interrupt-parent = <&pio>;
+		interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+		reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <20000>;
+
+		phy-mode = "2500base-x";
+		full-duplex;
+		pause;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@0 {
+				reg = <0>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_AMBER>;
+			};
+
+			led@1 {
+				reg = <1>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_GREEN>;
+			};
+		};
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&pio {
+	spi0_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+	spi1_flash_pins: spi1-pins {
+		mux {
+			function = "spi";
+			groups = "spi1_1";
+		};
+
+		conf-pu {
+			pins = "SPI1_CS";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+	spi2_flash_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2";
+		};
+
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+
+	i2c_pins: i2c-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c0_0";
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		mux {
+			function = "uart";
+			groups = "uart2_0_tx_rx";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0_0", "pwm1_1";
+		};
+	};
+
+	pcie_pins: pcie-pins {
+		mux {
+			function = "pcie";
+			groups = "pcie_pereset";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c_pins>;
+	status = "okay";
+
+	rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	cs-gpios = <0>, <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <1>;
+		spi-max-frequency = <52000000>;
+
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+		spi-cal-addrlen = <5>;
+		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x100000 0x7F00000>;
+				compatible = "linux,ubi";
+
+				volumes {
+					ubi_fit_volume: ubi-volume-fit {
+						volname = "fit";
+					};
+				};
+			};
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_flash_pins>;
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_flash_pins>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2-nor";
+				reg = <0x00000 0x40000>;
+			};
+
+			partition@40000 {
+				label = "factory";
+				reg = <0x40000 0xc0000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+
+					macaddr_factory_4: macaddr@4 {
+						compatible = "mac-base";
+						reg = <0x24 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+
+					macaddr_factory_a: macaddr@a {
+						compatible = "mac-base";
+						reg = <0x2a 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@100000 {
+				label = "fip-nor";
+				reg = <0x100000 0x80000>;
+			};
+
+			partition@180000 {
+				label = "recovery";
+				reg = <0x180000 0xc80000>;
+			};
+		};
+	};
+};
+
+&xhci {
+	phys = <&u2port0 PHY_TYPE_USB2>;
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&reg_5v>;
+	mediatek,u3p-dis-msk = <0x01>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+	status = "okay";
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
+};
+
+&sgmiisys0 {
+	/delete-node/ mediatek,pnswap;
+};
diff --git a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts
index 4e6e834276..8b716e8742 100644
--- a/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts
+++ b/target/linux/mediatek/dts/mt7981b-yuncore-ax835.dts
@@ -9,7 +9,6 @@
 	model = "YunCore AX835";
 
 	aliases {
-		ethernet0 = &gmac0;
 		led-boot = &led_system;
 		led-failsafe = &led_system;
 		led-running = &led_system;
diff --git a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
index 1cdfb5f155..891d56853b 100644
--- a/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
+++ b/target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
@@ -296,26 +296,26 @@
 		#size-cells = <0>;
 
 		port@1 {
-			reg = <4>;
-			label = "lan1";
+			reg = <1>;
+			label = "lan4";
 			phy-handle = <&swphy1>;
 		};
 
 		port@2 {
-			reg = <3>;
-			label = "lan2";
+			reg = <2>;
+			label = "lan3";
 			phy-handle = <&swphy2>;
 		};
 
 		port@3 {
-			reg = <2>;
-			label = "lan3";
+			reg = <3>;
+			label = "lan2";
 			phy-handle = <&swphy3>;
 		};
 
 		port@4 {
-			reg = <1>;
-			label = "lan4";
+			reg = <4>;
+			label = "lan1";
 			phy-handle = <&swphy4>;
 		};
 
diff --git a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts
index b62c2f4215..93a5bb86f3 100644
--- a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts
+++ b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts
@@ -23,7 +23,9 @@
 	};
 
 	chosen {
+		bootargs-override = "root=/dev/fit0 rootwait";
 		stdout-path = "serial0:115200n8";
+		rootdisk = <&emmc_rootdisk>;
 	};
 
 	memory@40000000 {
@@ -157,6 +159,20 @@
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	status = "okay";
+
+	card@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+			partitions {
+				emmc_rootdisk: block-partition-production {
+					partname = "production";
+				};
+			};
+		};
+	};
 };
 
 &pio {
diff --git a/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts
new file mode 100644
index 0000000000..80b614ac22
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+	compatible = "ruijie,rg-x60-pro", "mediatek,mt7986a";
+	model = "Ruijie RG-X60 Pro";
+
+	aliases {
+		serial0 = &uart0;
+		led-boot = &led_system;
+		led-failsafe = &led_alarm;
+		led-running = &led_system;
+		led-upgrade = &led_alarm;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x11002000";
+	};
+
+	memory@40000000 {
+		reg = <0 0x40000000 0 0x20000000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-0 {
+			label = "reset";
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		button-1 {
+			label = "mesh";
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_MISC>;
+		};
+	};
+
+	leds-gpio {
+		compatible = "gpio-leds";
+
+		led_system: led-0 {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 22 GPIO_ACTIVE_LOW>;
+		};
+
+		led_alarm: led-1 {
+			color = <LED_COLOR_ID_PURPLE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+		fixed-link {
+			speed = <2500>;
+			full-duplex;
+			pause;
+		};
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy7>;
+		phy-mode = "2500base-x";
+	};
+
+	mdio: mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
+
+&mdio {
+	switch: switch@1f {
+		compatible = "mediatek,mt7531";
+		reg = <31>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&pio>;
+		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	phy7: phy@7 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <7>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+		realtek,aldps-enable;
+	};
+};
+
+&pio {
+	spi_flash_pins: spi-flash-pins-33-to-38 {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <8>;
+			mediatek,pull-up-adv = <0>; /* bias-disable */
+		};
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <8>;
+			mediatek,pull-down-adv = <0>; /* bias-disable */
+		};
+	};
+
+	wf_2g_5g_pins: wf_2g_5g-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_2g", "wf_5g";
+		};
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <4>;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <20000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		mediatek,nmbm;
+		mediatek,bmt-max-ratio = <1>;
+		mediatek,bmt-max-reserved-blocks = <64>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x000000 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x100000 0x80000>;
+				read-only;
+			};
+
+			partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x200000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+				};
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x380000 0x200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "product_info";
+				reg = <0x580000 0x80000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "kdump";
+				reg = <0x600000 0x80000>;
+				read-only;
+			};
+
+			partition@680000 {
+				label = "ubi";
+				reg = <0x680000 0x3f00000>;
+			};
+		};
+	};
+};
+
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+		};
+
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+		};
+
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+		};
+
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+		};
+
+		port@6 {
+			reg = <6>;
+			label = "cpu";
+			ethernet = <&gmac0>;
+			phy-mode = "2500base-x";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+				pause;
+			};
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&wf_2g_5g_pins>;
+
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts
new file mode 100644
index 0000000000..c8c58271a3
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8733.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7988a-smartrg-mt-stuart.dtsi"
+
+/ {
+	model = "SmartRG SDG-8733";
+	compatible = "smartrg,sdg-8733", "mediatek,mt7988a";
+};
+
+&gmac1 {
+	phy-connection-type = "usxgmii";
+	phy = <&phy0>;
+};
diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts
new file mode 100644
index 0000000000..6eeb4993f5
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7988a-smartrg-SDG-8734.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7988a-smartrg-mt-stuart.dtsi"
+
+/ {
+	model = "SmartRG SDG-8734";
+	compatible = "smartrg,sdg-8734", "mediatek,mt7988a";
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sfp_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = "sfp";
+			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		};
+
+		sfp_red {
+			color = <LED_COLOR_ID_RED>;
+			function = "sfp";
+			gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	i2c_sfp1: i2c-gpio-0 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&sfp_i2c_pins>;
+
+		compatible = "i2c-gpio";
+		sda-gpios = <&pio 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&pio 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		i2c-gpio,delay-us = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+		rate-select0-gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
+		rate-select1-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
+		tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 37 GPIO_ACTIVE_HIGH>;
+		maximum-power-milliwatt = <4000>;
+	};
+};
+
+&gmac1 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+};
diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi
new file mode 100644
index 0000000000..2b468f9bb3
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi
@@ -0,0 +1,684 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		led-boot = &led_sys_green;
+		led-failsafe = &led_sys_blue;
+		led-running = &led_sys_white;
+		led-upgrade = &led_sys_red;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf root=PARTLABEL=rootfs";
+	};
+
+	memory {
+		reg = <0x0 0x40000000 0x0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/delete-node/ramoops@42ff0000;
+
+		bootdata@45000000 {
+			no-map;
+			reg = <0x0 0x45000000 0x0 0x00001000>;
+		};
+
+		ramoops_reserved: ramoops@45001000 {
+			no-map;
+			compatible = "ramoops";
+			reg = <0x0 0x45001000 0x0 0x00140000>;
+			ftrace-size = <0x20000>;
+			record-size = <0x20000>;
+			console-size = <0x20000>;
+			pmsg-size = <0x80000>;
+		};
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&button_pins>;
+
+		factory {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "sync";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-export {
+		compatible = "gpio-export";
+
+		bluetooth_reset {
+			gpio-export,name = "bt_reset";
+			gpio-export,direction_may_change;
+			gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		bluetooth_txrx_ctl {
+			gpio-export,name = "bt_txrx_ctl";
+			gpio-export,direction_may_change;
+			gpios = <&pio 74 GPIO_ACTIVE_HIGH>;
+		};
+
+		gps_enable {
+			gpio-export,name = "gps_enable";
+			gpio-export,output = <1>;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		slic_interrupt {
+			gpio-export,name = "slic_interrupt";
+			gpio-export,direction_may_change;
+			gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		};
+
+		slic_reset {
+			gpio-export,name = "slic_reset";
+			gpio-export,output = <0>;
+			gpios = <&pio 72 GPIO_ACTIVE_HIGH>;
+		};
+
+		usb_enable {
+			gpio-export,name = "usb_enable";
+			gpio-export,output = <1>;
+			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu_thermal {
+	/delete-node/cooling-maps;
+	/delete-node/trips;
+
+	trips {
+		cpu_trip_crit: crit {
+			temperature = <125000>;
+			hysteresis = <2000>;
+			type = "critical";
+		};
+
+		cpu_trip_hot: hot {
+			temperature = <120000>;
+			hysteresis = <2000>;
+			type = "hot";
+		};
+
+		cpu_trip_active_high: active-high {
+			temperature = <110000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_med: active-med {
+			temperature = <80000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_low: active-low {
+			temperature = <60000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_silent: active-silent {
+			temperature = <40000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		cpu-active-high {
+			/* active: set fan to cooling level 3 */
+			cooling-device = <&fan 3 3>;
+			trip = <&cpu_trip_active_high>;
+		};
+
+		cpu-active-med {
+			/* active: set fan to cooling level 2 */
+			cooling-device = <&fan 2 2>;
+			trip = <&cpu_trip_active_med>;
+		};
+
+		cpu-active-low {
+			/* active: set fan to cooling level 1 */
+			cooling-device = <&fan 1 1>;
+			trip = <&cpu_trip_active_low>;
+		};
+
+		cpu-active-silent {
+			/* active: set fan to cooling level 0 */
+			cooling-device = <&fan 0 0>;
+			trip = <&cpu_trip_active_silent>;
+		};
+	};
+};
+
+&eth {
+	pinctrl-0 = <&mdio0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&fan {
+	pwms = <&pwm 0 40000 0>;
+
+	/**
+	 * set fan speed
+	 *
+	 * 0 = off
+	 * 61 = 24% duty cycle
+	 * 77 = 30% duty cycle
+	 * 102 = 40% duty cycle
+	 * 128 - 50% duty cycle
+	 * 255 = 100% duty cycle
+	 */
+	cooling-levels = <61 77 102 128>;
+
+	interrupt-parent = <&pio>;
+	interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+	pulses-per-revolution = <2>;
+
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	label = "wan";
+	status = "okay";
+	phy-mode = "usxgmii";
+};
+
+&gmac2 {
+	label = "lan1";
+	status = "okay";
+	phy-mode = "usxgmii";
+	phy-connection-type = "usxgmii";
+	phy = <&phy8>;
+};
+
+&gsw_phy0 {
+	status = "disabled";
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>, <&gbe1_led1_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1_led1 {
+	status = "okay";
+	color = <LED_COLOR_ID_AMBER>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>, <&gbe2_led1_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2_led1 {
+	status = "okay";
+	color = <LED_COLOR_ID_AMBER>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>, <&gbe3_led1_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3_led1 {
+	status = "okay";
+	color = <LED_COLOR_ID_AMBER>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+
+	system-leds {
+		compatible = "srg,sysled";
+		reg = <0x30>;
+
+		led_sys_red: system_red {
+			label = "red";
+			reg = <1>;
+		};
+
+		led_sys_green: system_green {
+			label = "green";
+			reg = <2>;
+		};
+
+		led_sys_blue: system_blue {
+			label = "blue";
+			reg = <3>;
+		};
+
+		led_sys_white: system_white {
+			label = "white";
+			reg = <4>;
+		};
+	};
+};
+
+&mdio_bus {
+	phy0: ethernet-phy@0 {
+		/* AQR113C */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <0>;
+
+		reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <1000000>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@0 {
+				reg = <0>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_GREEN>;
+			};
+
+			led@1 {
+				reg = <1>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_ORANGE>;
+			};
+
+			led@2 {
+				reg = <2>;
+				function = LED_FUNCTION_WAN;
+				color = <LED_COLOR_ID_WHITE>;
+				active-low;
+			};
+		};
+	};
+
+	phy8: ethernet-phy@8 {
+		/* AQR113C */
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+
+		reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <100000>;
+		reset-deassert-us = <1000000>;
+
+		leds {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			led@0 {
+				reg = <0>;
+				function = LED_FUNCTION_LAN;
+				color = <LED_COLOR_ID_GREEN>;
+			};
+
+			led@1 {
+				reg = <1>;
+				function = LED_FUNCTION_LAN;
+				color = <LED_COLOR_ID_ORANGE>;
+			};
+
+			led@2 {
+				reg = <2>;
+				function = LED_FUNCTION_LAN;
+				color = <LED_COLOR_ID_WHITE>;
+				active-low;
+			};
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_emmc_51>;
+	pinctrl-1 = <&mmc0_pins_emmc_51>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	hs400-ds-delay = <0x12814>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	card@0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+		compatible = "mmc-card";
+		reg = <0>;
+
+		block {
+			compatible = "block-device";
+
+			partitions {
+				block-partition-factory {
+					partname = "factory";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom_factory_0: eeprom@0 {
+							reg = <0x0 0x1e00>;
+						};
+					};
+				};
+			};
+		};
+	};
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_1_pins>;
+	reset-gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x0000 0 0 0 0>;
+
+		mt7996@0,0 {
+			reg = <0x0000 0 0 0 0>;
+			nvmem-cells = <&eeprom_factory_0>;
+			nvmem-cell-names = "eeprom";
+			ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>, <5945000 7125000>;
+		};
+	};
+};
+
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+&pcie2 {
+	status = "disabled";
+};
+
+&pcie3 {
+	status = "disabled";
+};
+
+&pio {
+	button_pins: button-pins {
+		pins = "GPIO_RESET", "GPIO_WPS";
+		mediatek,pull-down-adv = <0>; /* bias-disable */
+	};
+
+	pcie0_1_pins: pcie0-pins-g1 {
+		mux {
+			function = "pcie";
+			groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0";
+		};
+	};
+
+	pwm_pins: pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0", "pwm1";
+		};
+	};
+
+	sfp_i2c_pins: sfp-i2c-pins {
+		conf-scl {
+			pins = "LED_A";
+			drive-strength =  <8>;
+			mediatek,pull-up-adv = <1>;
+		};
+		conf-sda {
+			pins = "LED_E";
+			drive-strength =  <8>;
+			mediatek,pull-up-adv = <0>;
+		};
+	};
+
+	uart1_pins: uart1-pins {
+		mux {
+			function = "uart";
+			groups = "uart1_2";
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		mux {
+			function = "uart";
+			groups = "uart2";
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "disabled";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+	};
+
+};
+
+&ssusb0 {
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+
+	ports {
+		port@0 {
+			status = "disabled";
+		};
+
+		port@1 {
+			label = "lan2";
+		};
+
+		port@2 {
+			label = "lan3";
+		};
+
+		port@3 {
+			label = "lan4";
+		};
+	};
+};
+
+&tphy {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+
+	/* Airoha AG3352 GPS */
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+
+	/* DA14531MOD Bluetooth */
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xphy {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
deleted file mode 100644
index 4d0e5c0406..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
deleted file mode 100644
index 710e6c0bcf..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&sw_p5>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-			reset-delay-us = <600>;
-			reset-post-delay-us = <20000>;
-
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
deleted file mode 100644
index 5b51dfd671..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			spi_nand: spi_nand@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "spi-nand";
-				reg = <1>;
-				spi-max-frequency = <10000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					factory: partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0200000>;
-					};
-
-					partition@380000 {
-						label = "FIP";
-						reg = <0x380000 0x0200000>;
-					};
-
-					partition@580000 {
-						label = "ubi";
-						reg = <0x580000 0x4000000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&wifi>;
-		__overlay__ {
-			mediatek,mtd-eeprom = <&factory 0x0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
deleted file mode 100644
index b2bb692956..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts
+++ /dev/null
@@ -1,188 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7981.dtsi"
-
-/ {
-	model = "MediaTek MT7981 RFB";
-	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x20000000>;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
-		};
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "gmii";
-		phy-handle = <&int_gbe_phy>;
-	};
-};
-
-&mdio_bus {
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&pio>;
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&pio {
-	spi0_flash_pins: spi0-pins {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
-		};
-		conf-pd {
-			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
-			drive-strength = <MTK_DRIVE_8mA>;
-			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
-		};
-	};
-
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		sw_p5: port@5 {
-			reg = <5>;
-			label = "lan5";
-			status = "disabled";
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&xhci {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
deleted file mode 100644
index 54cfd0b4b9..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ /dev/null
@@ -1,822 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
-	compatible = "mediatek,mt7981";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			compatible = "arm,cortex-a53";
-			reg = <0x0>;
-			device_type = "cpu";
-			enable-method = "psci";
-		};
-
-		cpu@1 {
-			compatible = "arm,cortex-a53";
-			reg = <0x1>;
-			device_type = "cpu";
-			enable-method = "psci";
-		};
-	};
-
-	ice: ice_debug {
-		compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
-		clocks = <&infracfg CLK_INFRA_DBG_CK>;
-		clock-names = "ice_dbg";
-	};
-
-	clk40m: oscillator-40m {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		clock-output-names = "clkxtal";
-		#clock-cells = <0>;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
-		cooling-levels = <0 63 95 127 159 191 223 255>;
-		#cooling-cells = <2>;
-		status = "disabled";
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		/* 64 KiB reserved for ramoops/pstore */
-		ramoops@42ff0000 {
-			compatible = "ramoops";
-			reg = <0 0x42ff0000 0 0x10000>;
-			record-size = <0x1000>;
-		};
-
-		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x30000>;
-			no-map;
-		};
-
-		wmcpu_emi: wmcpu-reserved@47c80000 {
-			reg = <0 0x47c80000 0 0x100000>;
-			no-map;
-		};
-
-		wo_emi0: wo-emi@47d80000 {
-			reg = <0 0x47d80000 0 0x40000>;
-			no-map;
-		};
-
-		wo_data: wo-data@47dc0000 {
-			reg = <0 0x47dc0000 0 0x240000>;
-			no-map;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>; /* GICR */
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		consys: consys@10000000 {
-			compatible = "mediatek,mt7981-consys";
-			reg = <0 0x10000000 0 0x8600000>;
-			memory-region = <&wmcpu_emi>;
-		};
-
-		infracfg: clock-controller@10001000 {
-			compatible = "mediatek,mt7981-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		wed_pcie: wed_pcie@10003000 {
-			compatible = "mediatek,wed_pcie";
-			reg = <0 0x10003000 0 0x10>;
-		};
-
-		topckgen: clock-controller@1001b000 {
-			compatible = "mediatek,mt7981-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7986-wdt",
-				     "mediatek,mt6589-wdt";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-			status = "disabled";
-		};
-
-		apmixedsys: clock-controller@1001e000 {
-			compatible = "mediatek,mt7981-apmixedsys", "syscon";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7981-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_PWM_STA>,
-				 <&infracfg CLK_INFRA_PWM_HCK>,
-				 <&infracfg CLK_INFRA_PWM1_CK>,
-				 <&infracfg CLK_INFRA_PWM2_CK>,
-				 <&infracfg CLK_INFRA_PWM3_CK>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
-			#pwm-cells = <2>;
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
-			reg = <0 0x10060000 0 0x1000>;
-			mediatek,pnswap;
-			#clock-cells = <1>;
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
-			reg = <0 0x10070000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		crypto: crypto@10320000 {
-			compatible = "inside-secure,safexcel-eip97";
-			reg = <0 0x10320000 0 0x40000>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			clocks = <&topckgen CLK_TOP_EIP97B>;
-			clock-names = "top_eip97_ck";
-			assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
-		};
-
-		uart0: serial@11002000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11002000 0 0x400>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
-				 <&infracfg CLK_INFRA_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-0 = <&uart0_pins>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		uart1: serial@11003000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11003000 0 0x400>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
-				 <&infracfg CLK_INFRA_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11004000 {
-			compatible = "mediatek,mt6577-uart";
-			reg = <0 0x11004000 0 0x400>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
-				 <&infracfg CLK_INFRA_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		snand: snfi@11005000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
-			reg-names = "nfi", "ecc";
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
-				 <&infracfg CLK_INFRA_NFI1_CK>,
-				 <&infracfg CLK_INFRA_NFI_HCK_CK>;
-			clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
-						 <&topckgen CLK_TOP_CB_M_D8>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c0: i2c@11007000 {
-			compatible = "mediatek,mt7981-i2c";
-			reg = <0 0x11007000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-				 <&infracfg CLK_INFRA_AP_DMA_CK>,
-				 <&infracfg CLK_INFRA_I2C_MCK_CK>,
-				 <&infracfg CLK_INFRA_I2C_PCK_CK>;
-			clock-names = "main", "dma", "arb", "pmic";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI2_CK>,
-				 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@1100a000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x1100a000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_SPI0_CK>,
-				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@1100b000 {
-			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-			reg = <0 0x1100b000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_CB_M_D2>,
-				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-				 <&infracfg CLK_INFRA_SPI1_CK>,
-				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		thermal: thermal@1100c800 {
-			compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
-			reg = <0 0x1100c800 0 0x800>;
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-				 <&infracfg CLK_INFRA_ADC_26M_CK>;
-			clock-names = "therm", "auxadc";
-			nvmem-cells = <&thermal_calibration>;
-			nvmem-cell-names = "calibration-data";
-			#thermal-sensor-cells = <1>;
-			mediatek,auxadc = <&auxadc>;
-			mediatek,apmixedsys = <&apmixedsys>;
-		};
-
-		auxadc: adc@1100d000 {
-			compatible = "mediatek,mt7981-auxadc",
-				     "mediatek,mt7986-auxadc",
-				     "mediatek,mt7622-auxadc";
-			reg = <0 0x1100d000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
-				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-			clock-names = "main", "32k";
-			#io-channel-cells = <1>;
-		};
-
-		xhci: usb@11200000 {
-			compatible = "mediatek,mt7986-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-				 <&infracfg CLK_INFRA_IUSB_CK>,
-				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-			clock-names = "sys_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck",
-				      "xhci_ck";
-			phys = <&u2port0 PHY_TYPE_USB2>,
-			       <&u3port0 PHY_TYPE_USB3>;
-			vusb33-supply = <&reg_3p3v>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-				 <&infracfg CLK_INFRA_AUD_26M_CK>,
-				 <&infracfg CLK_INFRA_AUD_L_CK>,
-				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-				 <&infracfg CLK_INFRA_AUD_EG2_CK>,
-				 <&topckgen CLK_TOP_AUD_SEL>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&topckgen CLK_TOP_CB_APLL2_196M>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC_CK>,
-				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-				 <&infracfg CLK_INFRA_MSDC_66M_CK>,
-				 <&infracfg CLK_INFRA_MSDC_133M_CK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
-						 <&topckgen CLK_TOP_CB_NET2_D2>;
-			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
-			status = "disabled";
-		};
-
-		pcie: pcie@11280000 {
-			compatible = "mediatek,mt7981-pcie",
-				     "mediatek,mt7986-pcie";
-			reg = <0 0x11280000 0 0x4000>;
-			reg-names = "pcie-mac";
-			ranges = <0x82000000 0 0x20000000
-				  0x0 0x20000000 0 0x10000000>;
-			device_type = "pci";
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
-				 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-				 <&infracfg CLK_INFRA_IPCIER_CK>,
-				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-			phys = <&u3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			#interrupt-cells = <1>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc: interrupt-controller {
-				interrupt-controller;
-				#interrupt-cells = <1>;
-				#address-cells = <0>;
-			};
-		};
-
-		pio: pinctrl@11d00000 {
-			compatible = "mediatek,mt7981-pinctrl";
-			reg = <0 0x11d00000 0 0x1000>,
-			      <0 0x11c00000 0 0x1000>,
-			      <0 0x11c10000 0 0x1000>,
-			      <0 0x11d20000 0 0x1000>,
-			      <0 0x11e00000 0 0x1000>,
-			      <0 0x11e20000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x11f10000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio", "iocfg_rt", "iocfg_rm",
-				    "iocfg_rb", "iocfg_lb", "iocfg_bl",
-				    "iocfg_tm", "iocfg_tl", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 56>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio_pins: mdc-mdio-pins {
-				mux {
-					function = "eth";
-					groups = "smi_mdc_mdio";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups = "uart0";
-				};
-			};
-
-			wifi_dbdc_pins: wifi-dbdc-pins {
-				mux {
-					function = "eth";
-					groups = "wf0_mode1";
-				};
-
-				conf {
-					pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
-					       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
-					       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
-					       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
-					       "WF_CBA_RESETB", "WF_DIG_RESETB";
-					drive-strength = <4>;
-				};
-			};
-
-			gbe_led0_pins: gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe_led0";
-				};
-			};
-
-			gbe_led1_pins: gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe_led1";
-				};
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7981-topmisc", "syscon";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-		};
-
-		usb_phy: usb-phy@11e10000 {
-			compatible = "mediatek,mt7981",
-				     "mediatek,generic-tphy-v2";
-			ranges = <0 0 0x11e10000 0x1700>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "disabled";
-
-			u2port0: usb-phy@0 {
-				reg = <0x0 0x700>;
-				clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			u3port0: usb-phy@700 {
-				reg = <0x700 0x900>;
-				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-				status = "okay";
-			};
-		};
-
-		efuse: efuse@11f20000 {
-			compatible = "mediatek,mt7981-efuse",
-				     "mediatek,efuse";
-			reg = <0 0x11f20000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "okay";
-
-			thermal_calibration: thermal-calib@274 {
-				reg = <0x274 0xc>;
-			};
-
-			phy_calibration: phy-calib@8dc {
-				reg = <0x8dc 0x10>;
-			};
-
-			comb_rx_imp_p0: usb3-rx-imp@8c8 {
-				reg = <0x8c8 1>;
-				bits = <0 5>;
-			};
-
-			comb_tx_imp_p0: usb3-tx-imp@8c8 {
-				reg = <0x8c8 2>;
-				bits = <5 5>;
-			};
-
-			comb_intr_p0: usb3-intr@8c9 {
-				reg = <0x8c9 1>;
-				bits = <2 6>;
-			};
-		};
-
-		ethsys: clock-controller@15000000 {
-			compatible = "mediatek,mt7981-ethsys",
-				     "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-		};
-
-		wed: wed@15010000 {
-			compatible = "mediatek,mt7981-wed",
-				     "mediatek,mt7986-wed",
-				     "syscon";
-			reg = <0 0x15010000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wo_emi0>, <&wo_data>;
-			memory-region-names = "wo-emi", "wo-data";
-			mediatek,wo-ccif = <&wo_ccif0>;
-			mediatek,wo-ilm = <&wo_ilm0>;
-			mediatek,wo-dlm = <&wo_dlm0>;
-			mediatek,wo-cpuboot = <&wo_cpuboot>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7981-eth";
-			reg = <0 0x15100000 0 0x80000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETH_FE_EN>,
-				<&ethsys CLK_ETH_GP2_EN>,
-				<&ethsys CLK_ETH_GP1_EN>,
-				<&ethsys CLK_ETH_WOCPU0_EN>,
-				<&sgmiisys0 CLK_SGM0_TX_EN>,
-				<&sgmiisys0 CLK_SGM0_RX_EN>,
-				<&sgmiisys0 CLK_SGM0_CK0_EN>,
-				<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
-				<&sgmiisys1 CLK_SGM1_TX_EN>,
-				<&sgmiisys1 CLK_SGM1_RX_EN>,
-				<&sgmiisys1 CLK_SGM1_CK1_EN>,
-				<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
-				<&topckgen CLK_TOP_SGM_REG>,
-				<&topckgen CLK_TOP_NETSYS_SEL>,
-				<&topckgen CLK_TOP_NETSYS_500M_SEL>;
-			clock-names = "fe", "gp2", "gp1", "wocpu0",
-						"sgmii_tx250m", "sgmii_rx250m",
-						"sgmii_cdr_ref", "sgmii_cdr_fb",
-						"sgmii2_tx250m", "sgmii2_rx250m",
-						"sgmii2_cdr_ref", "sgmii2_cdr_fb",
-						"sgmii_ck", "netsys0", "netsys1";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_SGM_325M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
-						 <&topckgen CLK_TOP_CB_SGM_325M>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
-			mediatek,infracfg = <&topmisc>;
-			mediatek,wed = <&wed>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				int_gbe_phy: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "gmii";
-					phy-is-integrated;
-					nvmem-cells = <&phy_calibration>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						int_gbe_phy_led0: int-gbe-phy-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						int_gbe_phy_led1: int-gbe-phy-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		wdma: wdma@15104800 {
-			compatible = "mediatek,wed-wdma";
-			reg = <0 0x15104800 0 0x400>,
-			      <0 0x15104c00 0 0x400>;
-		};
-
-		wo_cpuboot: syscon@15194000 {
-			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-			reg = <0 0x15194000 0 0x1000>;
-		};
-
-		ap2woccif: ap2woccif@151a5000 {
-			compatible = "mediatek,ap2woccif";
-			reg = <0 0x151a5000 0 0x1000>,
-			      <0 0x151ad000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ccif0: syscon@151a5000 {
-			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-			reg = <0 0x151a5000 0 0x1000>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		wo_ilm0: syscon@151e0000 {
-			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-			reg = <0 0x151e0000 0 0x8000>;
-		};
-
-		wo_dlm0: syscon@151e8000 {
-			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-			reg = <0 0x151e8000 0 0x2000>;
-		};
-
-		wifi: wifi@18000000 {
-			compatible = "mediatek,mt7981-wmac";
-			reg = <0 0x18000000 0 0x1000000>,
-			      <0 0x10003000 0 0x1000>,
-			      <0 0x11d10000 0 0x1000>;
-			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
-			reset-names = "consys";
-			pinctrl-0 = <&wifi_dbdc_pins>;
-			pinctrl-names = "dbdc";
-			clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
-				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
-			clock-names = "mcu", "ap2conn";
-			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-			memory-region = <&wmcpu_emi>;
-			status = "disabled";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				cpu_trip_active_highest: active-highest {
-					temperature = <70000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_lowest: active-lowest {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-highest {
-					/* active: set fan to cooling level 7 */
-					cooling-device = <&fan 7 7>;
-					trip = <&cpu_trip_active_highest>;
-				};
-
-				cpu-active-high {
-					/* active: set fan to cooling level 5 */
-					cooling-device = <&fan 5 5>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-med {
-					/* active: set fan to cooling level 3 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-active-low {
-					/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_low>;
-				};
-
-				cpu-active-lowest {
-					/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_lowest>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		clock-frequency = <13000000>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
-	};
-
-	trng {
-		compatible = "mediatek,mt7981-rng";
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
deleted file mode 100644
index ce007099d2..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-nand";
-		reg = <1>;
-		spi-max-frequency = <10000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "BL2";
-				reg = <0x00000 0x0100000>;
-				read-only;
-			};
-			partition@100000 {
-				label = "u-boot-env";
-				reg = <0x0100000 0x0080000>;
-			};
-			factory: partition@180000 {
-				label = "Factory";
-				reg = <0x180000 0x0200000>;
-			};
-			partition@380000 {
-				label = "FIP";
-				reg = <0x380000 0x0200000>;
-			};
-			partition@580000 {
-				label = "ubi";
-				reg = <0x580000 0x4000000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
deleted file mode 100644
index ea148315f0..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
-	compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
-	status = "okay";
-
-	spi_nor: spi_nor@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@00000 {
-				label = "BL2";
-				reg = <0x00000 0x0040000>;
-			};
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x40000 0x0010000>;
-			};
-			factory: partition@50000 {
-				label = "Factory";
-				reg = <0x50000 0x00B0000>;
-			};
-			partition@100000 {
-				label = "FIP";
-				reg = <0x100000 0x0080000>;
-			};
-			partition@180000 {
-				label = "firmware";
-				reg = <0x180000 0xE00000>;
-			};
-		};
-	};
-};
-
-&wifi {
-	mediatek,mtd-eeprom = <&factory 0>;
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
deleted file mode 100644
index 26d560bd4b..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
-	model = "MediaTek MT7986a RFB";
-	compatible = "mediatek,mt7986a-rfb";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&eth {
-	status = "okay";
-
-	gmac0: mac@0 {
-		compatible = "mediatek,eth-mac";
-		reg = <0>;
-		phy-mode = "2500base-x";
-
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-			pause;
-		};
-	};
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-mode = "2500base-x";
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&wifi {
-	status = "okay";
-	pinctrl-names = "default", "dbdc";
-	pinctrl-0 = <&wf_2g_5g_pins>;
-	pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
-	phy5: phy@5 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <5>;
-
-		reset-gpios = <&pio 6 1>;
-		reset-deassert-us = <20000>;
-	};
-
-	phy6: phy@6 {
-		compatible = "ethernet-phy-id67c9.de0a";
-		reg = <6>;
-	};
-
-	switch: switch@1f {
-		compatible = "mediatek,mt7531";
-		reg = <31>;
-		reset-gpios = <&pio 5 0>;
-	};
-};
-
-&crypto {
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&mmc0_pins_default>;
-	pinctrl-1 = <&mmc0_pins_uhs>;
-	bus-width = <8>;
-	max-frequency = <200000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	hs400-ds-delay = <0x14014>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_pins>;
-	status = "okay";
-};
-
-&pcie_phy {
-	status = "okay";
-};
-
-&pio {
-	mmc0_pins_default: mmc0-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	mmc0_pins_uhs: mmc0-uhs-pins {
-		mux {
-			function = "emmc";
-			groups = "emmc_51";
-		};
-		conf-cmd-dat {
-			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-			input-enable;
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-		conf-clk {
-			pins = "EMMC_CK";
-			drive-strength = <6>;
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-ds {
-			pins = "EMMC_DSL";
-			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
-		};
-		conf-rst {
-			pins = "EMMC_RSTB";
-			drive-strength = <4>;
-			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
-		};
-	};
-
-	pcie_pins: pcie-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-		};
-	};
-
-	spic_pins_g2: spic-pins-29-to-32 {
-		mux {
-			function = "spi";
-			groups = "spi1_2";
-		};
-	};
-
-	spi_flash_pins: spi-flash-pins-33-to-38 {
-		mux {
-			function = "spi";
-			groups = "spi0", "spi0_wp_hold";
-		};
-		conf-pu {
-			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
-			drive-strength = <8>;
-			mediatek,pull-up-adv = <0>;	/* bias-disable */
-		};
-		conf-pd {
-			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
-			drive-strength = <8>;
-			mediatek,pull-down-adv = <0>;	/* bias-disable */
-		};
-	};
-
-	uart1_pins: uart1-pins {
-		mux {
-			function = "uart";
-			groups = "uart1";
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2";
-		};
-	};
-
-	wf_2g_5g_pins: wf_2g_5g-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_2g", "wf_5g";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-
-	wf_dbdc_pins: wf_dbdc-pins {
-		mux {
-			function = "wifi";
-			groups = "wf_dbdc";
-		};
-		conf {
-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
-		};
-	};
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_flash_pins>;
-	cs-gpios = <0>, <0>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic_pins_g2>;
-	status = "okay";
-
-	proslic_spi: proslic_spi@0 {
-		compatible = "silabs,proslic_spi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		spi-cpha = <1>;
-		spi-cpol = <1>;
-		channel_count = <1>;
-		debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
-		reset_gpio = <&pio 7 0>;
-		ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
-	};
-};
-
-&gmac1 {
-	phy-mode = "2500base-x";
-	phy-connection-type = "2500base-x";
-	phy-handle = <&phy6>;
-};
-
-&switch {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-		};
-
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-		};
-
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-		};
-
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-		};
-
-		port@4 {
-			reg = <4>;
-			label = "wan";
-		};
-
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-
-			phy-mode = "2500base-x";
-			phy-handle = <&phy5>;
-		};
-
-		port@6 {
-			reg = <6>;
-			ethernet = <&gmac0>;
-			phy-mode = "2500base-x";
-
-			fixed-link {
-				speed = <2500>;
-				full-duplex;
-				pause;
-			};
-		};
-	};
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&usb_phy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
deleted file mode 100644
index 4945185d69..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			card@0 {
-				compatible = "mmc-card";
-				reg = <0>;
-
-				block {
-					compatible = "block-device";
-					partitions {
-						block-partition-env {
-							partname = "ubootenv";
-							nvmem-layout {
-								compatible = "u-boot,env-layout";
-							};
-						};
-						emmc_rootfs: block-partition-production {
-							partname = "production";
-						};
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target-path = "/chosen";
-		__overlay__ {
-			rootdisk-emmc = <&emmc_rootfs>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
deleted file mode 100644
index 39910b8cfe..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&pcf8563>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
deleted file mode 100644
index 1f5e1491a4..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = "/soc/mmc@11230000";
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			card@0 {
-				compatible = "mmc-card";
-				reg = <0>;
-
-				block {
-					compatible = "block-device";
-					partitions {
-						block-partition-env {
-							partname = "ubootenv";
-							nvmem-layout {
-								compatible = "u-boot,env-layout";
-							};
-						};
-						sd_rootfs: block-partition-production {
-							partname = "production";
-						};
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target-path = "/chosen";
-		__overlay__ {
-			rootdisk-sd = <&sd_rootfs>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
deleted file mode 100644
index 8a029b149f..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
-	fragment@0 {
-		target-path = "/";
-		__overlay__ {
-			wifi_12v: regulator-wifi-12v {
-				compatible = "regulator-fixed";
-				regulator-name = "wifi";
-				regulator-min-microvolt = <12000000>;
-				regulator-max-microvolt = <12000000>;
-				gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
-				enable-active-high;
-				regulator-always-on;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&i2c_wifi>;
-		__overlay__ {
-			// 5G WIFI MAC Address EEPROM
-			wifi_eeprom@51 {
-				compatible = "atmel,24c02";
-				reg = <0x51>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_5g: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-				};
-			};
-
-			// 6G WIFI MAC Address EEPROM
-			wifi_eeprom@52 {
-				compatible = "atmel,24c02";
-				reg = <0x52>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_6g: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&pcie0>;
-		__overlay__ {
-			pcie@0,0 {
-				reg = <0x0000 0 0 0 0>;
-
-				wifi@0,0 {
-					compatible = "mediatek,mt76";
-					reg = <0x0000 0 0 0 0>;
-					nvmem-cell-names = "mac-address";
-					nvmem-cells = <&macaddr_5g>;
-				};
-			};
-		};
-	};
-
-	fragment@3 {
-		target = <&pcie1>;
-		__overlay__ {
-			pcie@0,0 {
-				reg = <0x0000 0 0 0 0>;
-
-				wifi@0,0 {
-					compatible = "mediatek,mt76";
-					reg = <0x0000 0 0 0 0>;
-					nvmem-cell-names = "mac-address";
-					nvmem-cells = <&macaddr_6g>;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
deleted file mode 100644
index deae4378de..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ /dev/null
@@ -1,407 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "Bananapi BPI-R4";
-	compatible = "bananapi,bpi-r4",
-		     "mediatek,mt7988a";
-
-	aliases {
-		serial0 = &uart0;
-		led-boot = &led_green;
-		led-failsafe = &led_green;
-		led-running = &led_green;
-		led-upgrade = &led_green;
-	};
-
-	chosen {
-		stdout-path = &uart0;
-		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
-		rootdisk-spim-nand = <&ubi_rootfs>;
-	};
-
-	memory {
-		reg = <0x00 0x40000000 0x00 0x10000000>;
-	};
-
-	/* SFP1 cage (WAN) */
-	sfp1: sfp1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	/* SFP2 cage (LAN) */
-	sfp2: sfp2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp2>;
-		los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
-		maximum-power-milliwatt = <3000>;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "WPS";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		led_green: led-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led_blue: led-blue {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&gmac1 {
-	sfp = <&sfp2>;
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-	status = "okay";
-};
-
-&gmac2 {
-	sfp = <&sfp1>;
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_port0 {
-	label = "wan";
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_1_pins>;
-	status = "okay";
-
-	pca9545: i2c-switch@70 {
-		reg = <0x70>;
-		compatible = "nxp,pca9545";
-		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			eeprom@57 {
-				compatible = "atmel,24c02";
-				reg = <0x57>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			pcf8563: rtc@51 {
-				compatible = "nxp,pcf8563";
-				reg = <0x51>;
-				status = "disabled";
-			};
-		};
-
-		i2c_sfp1: i2c@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-		};
-
-		i2c_sfp2: i2c@2 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <2>;
-		};
-
-		i2c_wifi: i2c@3 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <3>;
-		};
-	};
-};
-
-/* mPCIe SIM2 */
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>;
-	status = "okay";
-};
-
-/* mPCIe SIM3 */
-&pcie1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie1_pins>;
-	status = "okay";
-};
-
-/* M.2 key-B SIM1 */
-&pcie2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie2_pins>;
-	status = "okay";
-};
-
-/* M.2 key-M SSD */
-&pcie3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3_pins>;
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		compatible = "spi-nand";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-buswidth = <4>;
-		spi-rx-buswidth = <4>;
-	};
-};
-
-&spi_nand {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "bl2";
-			reg = <0x0 0x200000>;
-			read-only;
-		};
-
-		partition@200000 {
-			label = "ubi";
-			reg = <0x200000 0x7e00000>;
-			compatible = "linux,ubi";
-
-			volumes {
-				ubi-volume-ubootenv {
-					volname = "ubootenv";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool-layout";
-					};
-				};
-
-				ubi-volume-ubootenv2 {
-					volname = "ubootenv2";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool-layout";
-					};
-				};
-
-				ubi_rootfs: ubi-volume-fit {
-					volname = "fit";
-				};
-			};
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_2_lite_pins>;
-};
-
-&uart2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_3_pins>;
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
deleted file mode 100644
index 3f8ac2ae38..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_emmc_51>;
-			pinctrl-1 = <&mmc0_pins_emmc_51>;
-			bus-width = <8>;
-			max-frequency = <200000000>;
-			cap-mmc-highspeed;
-			mmc-hs200-1_8v;
-			mmc-hs400-1_8v;
-			hs400-ds-delay = <0x12814>;
-			vqmmc-supply = <&reg_1p8v>;
-			vmmc-supply = <&reg_3p3v>;
-			non-removable;
-			no-sd;
-			no-sdio;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
deleted file mode 100644
index d21a61ad19..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy0: ethernet-phy@0 {
-				reg = <0>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
deleted file mode 100644
index 86ab7566dc..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "internal";
-			phy-connection-type = "internal";
-			phy = <&int_2p5g_phy>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target = <&int_2p5g_phy>;
-		__overlay__ {
-			pinctrl-names = "i2p5gbe-led";
-			pinctrl-0 = <&i2p5gbe_led0_pins>;
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
deleted file mode 100644
index 34a23bbd7e..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy13: ethernet-phy@13 {
-				reg = <13>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy13>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
deleted file mode 100644
index ba40a119cb..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_0_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp1: sfp@1 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c2>;
-				mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac1>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp1>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
deleted file mode 100644
index 140391fc45..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Aquantia AQR113C */
-			phy8: ethernet-phy@8 {
-				reg = <8>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
-				reset-assert-us = <100000>;
-				reset-deassert-us = <221000>;
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "usxgmii";
-			phy-connection-type = "usxgmii";
-			phy = <&phy8>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
deleted file mode 100644
index 19e0b2799f..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&mdio_bus>;
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* external Maxlinear GPY211C */
-			phy5: ethernet-phy@5 {
-				reg = <5>;
-				compatible = "ethernet-phy-ieee802.3-c45";
-				phy-mode = "2500base-x";
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "2500base-x";
-			phy-connection-type = "2500base-x";
-			phy = <&phy5>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
deleted file mode 100644
index b9aabd2726..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&i2c1>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_sfp_pins>;
-			status = "okay";
-		};
-	};
-
-	fragment@1 {
-		target-path = "/";
-		__overlay__ {
-			sfp_esp0: sfp@0 {
-				compatible = "sff,sfp";
-				i2c-bus = <&i2c1>;
-				mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
-				los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
-				tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
-				maximum-power-milliwatt = <3000>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target = <&gmac2>;
-		__overlay__ {
-			phy-mode = "10gbase-r";
-			managed = "in-band-status";
-			sfp = <&sfp_esp0>;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
deleted file mode 100644
index 04472cc12d..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@1 {
-		target-path = <&mmc0>;
-		__overlay__ {
-			pinctrl-names = "default", "state_uhs";
-			pinctrl-0 = <&mmc0_pins_sdcard>;
-			pinctrl-1 = <&mmc0_pins_sdcard>;
-			cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
-			bus-width = <4>;
-			max-frequency = <52000000>;
-			cap-sd-highspeed;
-			vmmc-supply = <&reg_3p3v>;
-			vqmmc-supply = <&reg_3p3v>;
-			no-mmc;
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
deleted file mode 100644
index 86b0042f64..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&snand>;
-		__overlay__ {
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target = <&bch>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
deleted file mode 100644
index a9eca00d44..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi0>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				compatible = "spi-nand";
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
-
-				partitions {
-					compatible = "fixed-partitions";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					partition@0 {
-						label = "BL2";
-						reg = <0x00000 0x0100000>;
-						read-only;
-					};
-
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
-
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
-
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
-
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
-					};
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
deleted file mode 100644
index 33bd57b3fb..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
-	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
-	fragment@0 {
-		target = <&spi2>;
-		__overlay__ {
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi2_flash_pins>;
-			status = "okay";
-
-			flash@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "jedec,spi-nor";
-				spi-cal-enable;
-				spi-cal-mode = "read-data";
-				spi-cal-datalen = <7>;
-				spi-cal-data = /bits/ 8 <
-					0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
-				spi-cal-addrlen = <1>;
-				spi-cal-addr = /bits/ 32 <0x0>;
-				reg = <0>;
-				spi-max-frequency = <52000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-
-				partition@00000 {
-					label = "BL2";
-					reg = <0x00000 0x0040000>;
-				};
-				partition@40000 {
-					label = "u-boot-env";
-					reg = <0x40000 0x0010000>;
-				};
-				partition@50000 {
-					label = "Factory";
-					reg = <0x50000 0x0200000>;
-				};
-				partition@250000 {
-					label = "FIP";
-					reg = <0x250000 0x0080000>;
-				};
-				partition@2D0000 {
-					label = "firmware";
-					reg = <0x2D0000 0x1D30000>;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
deleted file mode 100644
index 5012e7a498..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
-	model = "MediaTek MT7988A Reference Board";
-	compatible = "mediatek,mt7988a-rfb",
-		     "mediatek,mt7988a";
-
-	chosen {
-		bootargs = "console=ttyS0,115200n1 loglevel=8  \
-			    earlycon=uart8250,mmio32,0x11000000 \
-			    pci=pcie_bus_perf";
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-};
-
-&eth {
-	pinctrl-0 = <&mdio0_pins>;
-	pinctrl-names = "default";
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&eth {
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&pcie1 {
-	status = "okay";
-};
-
-&pcie2 {
-	status = "disabled";
-};
-
-&pcie3 {
-	status = "okay";
-};
-
-&ssusb0 {
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
deleted file mode 100644
index caad6e5577..0000000000
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ /dev/null
@@ -1,1573 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/* TOPRGU resets */
-#define MT7988_TOPRGU_SGMII0_GRST		1
-#define MT7988_TOPRGU_SGMII1_GRST		2
-#define MT7988_TOPRGU_XFI0_GRST			12
-#define MT7988_TOPRGU_XFI1_GRST			13
-#define MT7988_TOPRGU_XFI_PEXTP0_GRST		14
-#define MT7988_TOPRGU_XFI_PEXTP1_GRST		15
-#define MT7988_TOPRGU_XFI_PLL_GRST		16
-
-/ {
-	compatible = "mediatek,mt7988a";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cci: cci {
-		compatible = "mediatek,mt7988-cci",
-			     "mediatek,mt8183-cci";
-		clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
-			 <&topckgen CLK_TOP_XTAL>;
-		clock-names = "cci", "intermediate";
-		operating-points-v2 = <&cci_opp>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a73";
-			reg = <0x0>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a73";
-			reg = <0x1>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a73";
-			reg = <0x2>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a73";
-			reg = <0x3>;
-			device_type = "cpu";
-			enable-method = "psci";
-			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
-				 <&topckgen CLK_TOP_XTAL>;
-			clock-names = "cpu", "intermediate";
-			operating-points-v2 = <&cluster0_opp>;
-			mediatek,cci = <&cci>;
-		};
-
-		cluster0_opp: opp_table0 {
-			compatible = "operating-points-v2";
-			opp-shared;
-
-			opp00 {
-				opp-hz = /bits/ 64 <800000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp01 {
-				opp-hz = /bits/ 64 <1100000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp02 {
-				opp-hz = /bits/ 64 <1500000000>;
-				opp-microvolt = <850000>;
-			};
-
-			opp03 {
-				opp-hz = /bits/ 64 <1800000000>;
-				opp-microvolt = <900000>;
-			};
-		};
-	};
-
-	cci_opp: opp_table_cci {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp00 {
-			opp-hz = /bits/ 64 <480000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp01 {
-			opp-hz = /bits/ 64 <660000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp02 {
-			opp-hz = /bits/ 64 <900000000>;
-			opp-microvolt = <850000>;
-		};
-
-		opp03 {
-			opp-hz = /bits/ 64 <1080000000>;
-			opp-microvolt = <900000>;
-		};
-	};
-
-	clk40m: oscillator@0 {
-		compatible = "fixed-clock";
-		clock-frequency = <40000000>;
-		#clock-cells = <0>;
-		clock-output-names = "clkxtal";
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-		cooling-levels = <0 128 255>;
-		#cooling-cells = <2>;
-		#thermal-sensor-cells = <1>;
-		status = "disabled";
-	};
-
-	pmu {
-		compatible = "arm,cortex-a73-pmu";
-		interrupt-parent = <&gic>;
-		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
-		secmon_reserved: secmon@43000000 {
-			reg = <0 0x43000000 0 0x50000>;
-			no-map;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		gic: interrupt-controller@c000000 {
-			compatible = "arm,gic-v3";
-			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
-			      <0 0x0c080000 0 0x200000>, /* GICR */
-			      <0 0x0c400000 0 0x2000>,   /* GICC */
-			      <0 0x0c410000 0 0x1000>,   /* GICH */
-			      <0 0x0c420000 0 0x2000>;   /* GICV */
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		phyfw: phy-firmware@f000000 {
-			compatible = "mediatek,2p5gphy-fw";
-			reg = <0 0x0f100000 0 0x20000>,
-			      <0 0x0f0f0018 0 0x20>;
-		};
-
-		infracfg: infracfg@10001000 {
-			compatible = "mediatek,mt7988-infracfg", "syscon";
-			reg = <0 0x10001000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		topckgen: topckgen@1001b000 {
-			compatible = "mediatek,mt7988-topckgen", "syscon";
-			reg = <0 0x1001b000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		watchdog: watchdog@1001c000 {
-			compatible = "mediatek,mt7988-wdt",
-				     "mediatek,mt6589-wdt",
-				     "syscon";
-			reg = <0 0x1001c000 0 0x1000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			#reset-cells = <1>;
-		};
-
-		apmixedsys: apmixedsys@1001e000 {
-			compatible = "mediatek,mt7988-apmixedsys";
-			reg = <0 0x1001e000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		pio: pinctrl@1001f000 {
-			compatible = "mediatek,mt7988-pinctrl", "syscon";
-			reg = <0 0x1001f000 0 0x1000>,
-			      <0 0x11c10000 0 0x1000>,
-			      <0 0x11d00000 0 0x1000>,
-			      <0 0x11d20000 0 0x1000>,
-			      <0 0x11e00000 0 0x1000>,
-			      <0 0x11f00000 0 0x1000>,
-			      <0 0x1000b000 0 0x1000>;
-			reg-names = "gpio_base", "iocfg_tr_base",
-				    "iocfg_br_base", "iocfg_rb_base",
-				    "iocfg_lb_base", "iocfg_tl_base", "eint";
-			gpio-controller;
-			#gpio-cells = <2>;
-			gpio-ranges = <&pio 0 0 84>;
-			interrupt-controller;
-			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
-			#interrupt-cells = <2>;
-
-			mdio0_pins: mdio0-pins {
-				mux {
-					function = "eth";
-					groups = "mdc_mdio0";
-				};
-
-				conf {
-					groups = "mdc_mdio0";
-					drive-strength = <MTK_DRIVE_8mA>;
-				};
-			};
-
-			i2c0_pins: i2c0-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c0_1";
-				};
-			};
-
-			i2c1_pins: i2c1-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_0";
-				};
-			};
-
-			i2c1_sfp_pins: i2c1-sfp-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c1_sfp";
-				};
-			};
-
-			i2c2_pins: i2c2-pins {
-				mux {
-					function = "i2c";
-					groups = "i2c2";
-				};
-			};
-
-			i2c2_0_pins: i2c2-pins-g0 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_0";
-				};
-			};
-
-			i2c2_1_pins: i2c2-pins-g1 {
-				mux {
-					function = "i2c";
-					groups = "i2c2_1";
-				};
-			};
-
-			gbe0_led0_pins: gbe0-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led0";
-				};
-			};
-
-			gbe1_led0_pins: gbe1-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led0";
-				};
-			};
-
-			gbe2_led0_pins: gbe2-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led0";
-				};
-			};
-
-			gbe3_led0_pins: gbe3-led0-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led0";
-				};
-			};
-
-			gbe0_led1_pins: gbe0-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe0_led1";
-				};
-			};
-
-			gbe1_led1_pins: gbe1-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe1_led1";
-				};
-			};
-
-			gbe2_led1_pins: gbe2-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe2_led1";
-				};
-			};
-
-			gbe3_led1_pins: gbe3-led1-pins {
-				mux {
-					function = "led";
-					groups = "gbe3_led1";
-				};
-			};
-
-			i2p5gbe_led0_pins: 2p5gbe-led0-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led0";
-				};
-			};
-
-			i2p5gbe_led1_pins: 2p5gbe-led1-pins {
-				mux {
-					function = "led";
-					groups = "2p5gbe_led1";
-				};
-			};
-
-			mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
-				mux {
-					function = "flash";
-					groups = "emmc_45";
-				};
-			};
-
-			mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
-				mux {
-					function = "flash";
-					groups = "emmc_51";
-				};
-			};
-
-			mmc0_pins_sdcard: mmc0-pins-sdcard {
-				mux {
-					function = "flash";
-					groups = "sdcard";
-				};
-			};
-
-			uart0_pins: uart0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart0";
-				};
-			};
-
-			uart1_0_pins: uart1-0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart1_0";
-				};
-			};
-
-			uart1_1_pins: uart1-1-pins {
-				mux {
-					function = "uart";
-					groups =  "uart1_1";
-				};
-			};
-
-			uart1_2_pins: uart1-2-pins {
-				mux {
-					function = "uart";
-					groups =  "uart1_2";
-				};
-			};
-
-			uart1_2_lite_pins: uart1-2-lite-pins {
-				mux {
-					function = "uart";
-					groups =  "uart1_2_lite";
-				};
-			};
-
-			uart2_pins: uart2-pins {
-				mux {
-					function = "uart";
-					groups =  "uart2";
-				};
-			};
-
-			uart2_0_pins: uart2-0-pins {
-				mux {
-					function = "uart";
-					groups =  "uart2_0";
-				};
-			};
-
-			uart2_1_pins: uart2-1-pins {
-				mux {
-					function = "uart";
-					groups =  "uart2_1";
-				};
-			};
-
-			uart2_2_pins: uart2-2-pins {
-				mux {
-					function = "uart";
-					groups =  "uart2_2";
-				};
-			};
-
-			uart2_3_pins: uart2-3-pins {
-				mux {
-					function = "uart";
-					groups =  "uart2_3";
-				};
-			};
-
-			snfi_pins: snfi-pins {
-				mux {
-					function = "flash";
-					groups = "snfi";
-				};
-			};
-
-			spi0_pins: spi0-pins {
-				mux {
-					function = "spi";
-					groups = "spi0";
-				};
-			};
-
-			spi0_flash_pins: spi0-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi0", "spi0_wp_hold";
-				};
-			};
-
-			spi1_pins: spi1-pins {
-				mux {
-					function = "spi";
-					groups = "spi1";
-				};
-			};
-
-			spi2_pins: spi2-pins {
-				mux {
-					function = "spi";
-					groups = "spi2";
-				};
-			};
-
-			spi2_flash_pins: spi2-flash-pins {
-				mux {
-					function = "spi";
-					groups = "spi2", "spi2_wp_hold";
-				};
-			};
-
-			pcie0_pins: pcie0-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
-						 "pcie_wake_n0_0";
-				};
-			};
-
-			pcie1_pins: pcie1-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
-						 "pcie_wake_n1_0";
-				};
-			};
-
-			pcie2_pins: pcie2-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
-						 "pcie_wake_n2_0";
-				};
-			};
-
-			pcie3_pins: pcie3-pins {
-				mux {
-					function = "pcie";
-					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
-						 "pcie_wake_n3_0";
-				};
-			};
-		};
-
-		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
-			reg = <0 0x10048000 0 0x1000>;
-			#pwm-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
-				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
-			status = "disabled";
-		};
-
-		sgmiisys0: syscon@10060000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys0",
-				     "syscon",
-				     "simple-mfd";
-			reg = <0 0x10060000 0 0x1000>;
-			resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
-			#clock-cells = <1>;
-
-			sgmiipcs0: pcs {
-				compatible = "mediatek,mt7988-sgmii";
-				clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
-					 <&sgmiisys0 CLK_SGM0_TX_EN>,
-					 <&sgmiisys0 CLK_SGM0_RX_EN>;
-				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
-			};
-		};
-
-		sgmiisys1: syscon@10070000 {
-			compatible = "mediatek,mt7988-sgmiisys",
-				     "mediatek,mt7988-sgmiisys1",
-				     "syscon",
-				     "simple-mfd";
-			reg = <0 0x10070000 0 0x1000>;
-			resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
-			#clock-cells = <1>;
-
-			sgmiipcs1: pcs {
-				compatible = "mediatek,mt7988-sgmii";
-				clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
-					 <&sgmiisys1 CLK_SGM1_TX_EN>,
-					 <&sgmiisys1 CLK_SGM1_RX_EN>;
-				clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
-			};
-		};
-
-		usxgmiisys0: pcs@10080000 {
-			compatible = "mediatek,mt7988-usxgmiisys";
-			reg = <0 0x10080000 0 0x1000>;
-			resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
-			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
-		};
-
-		usxgmiisys1: pcs@10081000 {
-			compatible = "mediatek,mt7988-usxgmiisys";
-			reg = <0 0x10081000 0 0x1000>;
-			resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
-			clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
-		};
-
-		mcusys: mcusys@100e0000 {
-			compatible = "mediatek,mt7988-mcusys", "syscon";
-			reg = <0 0x100e0000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		uart0: serial@11000000 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000000 0 0x100>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART0_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&uart0_pins>;
-			status = "disabled";
-		};
-
-		uart1: serial@11000100 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000100 0 0x100>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART1_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART1_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		uart2: serial@11000200 {
-			compatible = "mediatek,mt7986-uart",
-				     "mediatek,mt6577-uart";
-			reg = <0 0x11000200 0 0x100>;
-			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-			 * 8250-mtk driver don't control "baud" clock since commit
-			 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
-			 * still need to be passed to the driver to prevent probe fail
-			 */
-			clocks = <&topckgen CLK_TOP_UART_SEL>,
-				 <&infracfg CLK_INFRA_52M_UART2_CK>;
-			clock-names = "baud", "bus";
-			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
-					  <&infracfg CLK_INFRA_MUX_UART2_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
-						 <&topckgen CLK_TOP_UART_SEL>;
-			status = "disabled";
-		};
-
-		snand: spi@11001000 {
-			compatible = "mediatek,mt7986-snand";
-			reg = <0 0x11001000 0 0x1000>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_SPINFI>,
-				 <&infracfg CLK_INFRA_NFI>;
-			clock-names = "pad_clk", "nfi_clk";
-			assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
-					  <&topckgen CLK_TOP_NFI1X_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
-						 <&topckgen CLK_TOP_MPLL_D8>;
-			nand-ecc-engine = <&bch>;
-			mediatek,quad-spi;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&snfi_pins>;
-			status = "disabled";
-		};
-
-		bch: ecc@11002000 {
-			compatible = "mediatek,mt7686-ecc";
-			reg = <0 0x11002000 0 0x1000>;
-			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
-			clock-names = "nfiecc_clk";
-			status = "disabled";
-		};
-
-		i2c0: i2c@11003000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11003000 0 0x1000>,
-			      <0 0x10217080 0 0x80>;
-			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c1: i2c@11004000 {
-			compatible = "mediatek,mt7988-i2c",
-				     "mediatek,mt7981-i2c";
-			reg = <0 0x11004000 0 0x1000>,
-			      <0 0x10217100 0 0x80>;
-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@11005000 {
-			compatible = "mediatek,mt7988-i2c",
-				"mediatek,mt7981-i2c";
-			reg = <0 0x11005000 0 0x1000>,
-			      <0 0x10217180 0 0x80>;
-			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-			clock-div = <1>;
-			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
-				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
-			clock-names = "main", "dma";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi0: spi@11007000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11007000 0 0x100>;
-			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI0>,
-				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		spi1: spi@11008000 {
-			compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
-			reg = <0 0x11008000 0 0x100>;
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI1>,
-				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi1_pins>;
-			status = "disabled";
-		};
-
-		spi2: spi@11009000 {
-			compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
-			reg = <0 0x11009000 0 0x100>;
-			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
-				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
-				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
-			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		lvts: lvts@1100a000 {
-			compatible = "mediatek,mt7988-lvts-ap";
-			reg = <0 0x1100a000 0 0x1000>;
-			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
-			clock-names = "lvts_clk";
-			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
-			nvmem-cells = <&lvts_calibration>;
-			nvmem-cell-names = "lvts-calib-data-1";
-			#thermal-sensor-cells = <1>;
-		};
-
-		ssusb0: usb@11190000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11190000 0 0x2e00>,
-			      <0 0x11193e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&xphyu2port0 PHY_TYPE_USB2>,
-			       <&xphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS>,
-				 <&infracfg CLK_INFRA_USB_XHCI>,
-				 <&infracfg CLK_INFRA_USB_REF>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			mediatek,p0_speed_fixup;
-			status = "disabled";
-		};
-
-		ssusb1: usb@11200000 {
-			compatible = "mediatek,mt7988-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x2e00>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&tphyu2port0 PHY_TYPE_USB2>,
-			       <&tphyu3port0 PHY_TYPE_USB3>;
-			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
-				 <&infracfg CLK_INFRA_USB_CK_P1>,
-				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
-			clock-names = "sys_ck",
-				      "xhci_ck",
-				      "ref_ck",
-				      "mcu_ck",
-				      "dma_ck";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-		};
-
-		afe: audio-controller@11210000 {
-			compatible = "mediatek,mt79xx-audio";
-			reg = <0 0x11210000 0 0x9000>;
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
-				 <&infracfg CLK_INFRA_AUD_26M>,
-				 <&infracfg CLK_INFRA_AUD_L>,
-				 <&infracfg CLK_INFRA_AUD_AUD>,
-				 <&infracfg CLK_INFRA_AUD_EG2>,
-				 <&topckgen CLK_TOP_AUD_SEL>,
-				 <&topckgen CLK_TOP_AUD_I2S_M>;
-			clock-names = "aud_bus_ck",
-				      "aud_26m_ck",
-				      "aud_l_ck",
-				      "aud_aud_ck",
-				      "aud_eg2_ck",
-				      "aud_sel",
-				      "aud_i2s_m";
-			assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
-					  <&topckgen CLK_TOP_A1SYS_SEL>,
-					  <&topckgen CLK_TOP_AUD_L_SEL>,
-					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>,
-						 <&apmixedsys CLK_APMIXED_APLL2>,
-						 <&topckgen CLK_TOP_APLL2_D4>;
-			status = "disabled";
-		};
-
-		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt7986-mmc",
-				     "mediatek,mt7981-mmc";
-			reg = <0 0x11230000 0 0x1000>,
-			      <0 0x11D60000 0 0x1000>;
-			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&infracfg CLK_INFRA_MSDC400>,
-				 <&infracfg CLK_INFRA_MSDC2_HCK>,
-				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
-				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
-			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
-					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
-						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
-			clock-names = "source",
-				      "hclk",
-				      "axi_cg",
-				      "ahb_cg";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		pcie2: pcie@11280000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11280000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x20000000 0x00
-				  0x20000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x20200000 0x00
-				  0x20200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <3>;
-			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
-				 <&topckgen CLK_TOP_PEXTP_P2_SEL>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m", "pextp_clk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie2_pins>;
-			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
-			phy-names = "pcie-phy";
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
-					<0 0 0 2 &pcie_intc2 1>,
-					<0 0 0 3 &pcie_intc2 2>,
-					<0 0 0 4 &pcie_intc2 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc2: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie3: pcie@11290000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11290000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x28000000 0x00
-				  0x28000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x28200000 0x00
-				  0x28200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <2>;
-			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
-				 <&topckgen CLK_TOP_PEXTP_P3_SEL>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m", "pextp_clk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie3_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
-					<0 0 0 2 &pcie_intc3 1>,
-					<0 0 0 3 &pcie_intc3 2>,
-					<0 0 0 4 &pcie_intc3 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc3: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie0: pcie@11300000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11300000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x30000000 0x00
-				  0x30000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x30200000 0x00
-				  0x30200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <0>;
-			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
-				 <&topckgen CLK_TOP_PEXTP_P0_SEL>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m", "pextp_clk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie0_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-					<0 0 0 2 &pcie_intc0 1>,
-					<0 0 0 3 &pcie_intc0 2>,
-					<0 0 0 4 &pcie_intc0 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc0: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		pcie1: pcie@11310000 {
-			compatible = "mediatek,mt7988-pcie",
-				     "mediatek,mt7986-pcie",
-				     "mediatek,mt8192-pcie";
-			reg = <0 0x11310000 0 0x2000>;
-			reg-names = "pcie-mac";
-			ranges = <0x81000000 0x00 0x38000000 0x00
-				  0x38000000 0x00 0x00200000>,
-				 <0x82000000 0x00 0x38200000 0x00
-				  0x38200000 0x00 0x07e00000>;
-			device_type = "pci";
-			linux,pci-domain = <1>;
-			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-			bus-range = <0x00 0xff>;
-			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
-				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
-				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
-				 <&topckgen CLK_TOP_PEXTP_P1_SEL>;
-			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m", "pextp_clk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pcie1_pins>;
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0x7>;
-			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-					<0 0 0 2 &pcie_intc1 1>,
-					<0 0 0 3 &pcie_intc1 2>,
-					<0 0 0 4 &pcie_intc1 3>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			pcie_intc1: interrupt-controller {
-				#address-cells = <0>;
-				#interrupt-cells = <1>;
-				interrupt-controller;
-			};
-		};
-
-		tphy: tphy@11c50000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,generic-tphy-v2";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			tphyu2port0: usb-phy@11c50000 {
-				reg = <0 0x11c50000 0 0x700>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			tphyu3port0: usb-phy@11c50700 {
-				reg = <0 0x11c50700 0 0x900>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,usb3-pll-ssc-delta;
-				mediatek,usb3-pll-ssc-delta1;
-			};
-		};
-
-		topmisc: topmisc@11d10000 {
-			compatible = "mediatek,mt7988-topmisc", "syscon",
-				     "mediatek,mt7988-power-controller";
-			reg = <0 0x11d10000 0 0x10000>;
-			#clock-cells = <1>;
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		xphy: xphy@11e10000 {
-			compatible = "mediatek,mt7988",
-				     "mediatek,xsphy";
-			ranges;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			status = "disabled";
-
-			xphyu2port0: usb-phy@11e10000 {
-				reg = <0 0x11e10000 0 0x400>;
-				clocks = <&infracfg CLK_INFRA_USB_UTMI>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-			};
-
-			xphyu3port0: usb-phy@11e13000 {
-				reg = <0 0x11e13400 0 0x500>;
-				clocks = <&infracfg CLK_INFRA_USB_PIPE>;
-				clock-names = "ref";
-				#phy-cells = <1>;
-				mediatek,syscon-type = <&topmisc 0x218 0>;
-			};
-		};
-
-		xfi_tphy0: phy@11f20000 {
-			compatible = "mediatek,mt7988-xfi-tphy";
-			reg = <0 0x11f20000 0 0x10000>;
-			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
-			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
-			clock-names = "xfipll", "topxtal";
-			mediatek,usxgmii-performance-errata;
-			#phy-cells = <0>;
-		};
-
-		xfi_tphy1: phy@11f30000 {
-			compatible = "mediatek,mt7988-xfi-tphy";
-			reg = <0 0x11f30000 0 0x10000>;
-			resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
-			clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
-			clock-names = "xfipll", "topxtal";
-			#phy-cells = <0>;
-		};
-
-		xfi_pll: clock-controller@11f40000 {
-			compatible = "mediatek,mt7988-xfi-pll";
-			reg = <0 0x11f40000 0 0x1000>;
-			resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
-			#clock-cells = <1>;
-		};
-
-		efuse: efuse@11f50000 {
-			compatible = "mediatek,efuse";
-			reg = <0 0x11f50000 0 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			lvts_calibration: calib@918 {
-				reg = <0x918 0x28>;
-			};
-
-			phy_calibration_p0: calib@940 {
-				reg = <0x940 0x10>;
-			};
-
-			phy_calibration_p1: calib@954 {
-				reg = <0x954 0x10>;
-			};
-
-			phy_calibration_p2: calib@968 {
-				reg = <0x968 0x10>;
-			};
-
-			phy_calibration_p3: calib@97c {
-				reg = <0x97c 0x10>;
-			};
-
-			cpufreq_calibration: calib@278 {
-				reg = <0x278 0x1>;
-			};
-		};
-
-		ethsys: syscon@15000000 {
-			compatible = "mediatek,mt7988-ethsys", "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-		};
-
-		switch: switch@15020000 {
-			compatible = "mediatek,mt7988-switch";
-			reg = <0 0x15020000 0 0x8000>;
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				gsw_port0: port@0 {
-					reg = <0>;
-					label = "lan0";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy0>;
-				};
-
-				gsw_port1: port@1 {
-					reg = <1>;
-					label = "lan1";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy1>;
-				};
-
-				gsw_port2: port@2 {
-					reg = <2>;
-					label = "lan2";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy2>;
-				};
-
-				gsw_port3: port@3 {
-					reg = <3>;
-					label = "lan3";
-					phy-mode = "internal";
-					phy-handle = <&gsw_phy3>;
-				};
-
-				port@6 {
-					reg = <6>;
-					ethernet = <&gmac0>;
-					phy-mode = "internal";
-
-					fixed-link {
-						speed = <10000>;
-						full-duplex;
-						pause;
-					};
-				};
-			};
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				mediatek,pio = <&pio>;
-
-				gsw_phy0: ethernet-phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <0>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p0>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy0_led0: gsw-phy0-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy0_led1: gsw-phy0-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy1: ethernet-phy@1 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <1>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p1>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy1_led0: gsw-phy1-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy1_led1: gsw-phy1-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy2: ethernet-phy@2 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <2>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p2>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy2_led0: gsw-phy2-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy2_led1: gsw-phy2-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-
-				gsw_phy3: ethernet-phy@3 {
-					compatible = "ethernet-phy-ieee802.3-c22";
-					reg = <3>;
-					phy-mode = "internal";
-					nvmem-cells = <&phy_calibration_p3>;
-					nvmem-cell-names = "phy-cal-data";
-
-					leds {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						gsw_phy3_led0: gsw-phy3-led0@0 {
-							reg = <0>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-
-						gsw_phy3_led1: gsw-phy3-led1@1 {
-							reg = <1>;
-							function = LED_FUNCTION_LAN;
-							status = "disabled";
-						};
-					};
-				};
-			};
-		};
-
-		ethwarp: clock-controller@15031000 {
-			compatible = "mediatek,mt7988-ethwarp";
-			reg = <0 0x15031000 0 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		eth: ethernet@15100000 {
-			compatible = "mediatek,mt7988-eth";
-			reg = <0 0x15100000 0 0x80000>,
-			      <0 0x15400000 0 0x380000>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
-				 <&ethsys CLK_ETHDMA_XGP2_EN>,
-				 <&ethsys CLK_ETHDMA_XGP3_EN>,
-				 <&ethsys CLK_ETHDMA_FE_EN>,
-				 <&ethsys CLK_ETHDMA_GP2_EN>,
-				 <&ethsys CLK_ETHDMA_GP1_EN>,
-				 <&ethsys CLK_ETHDMA_GP3_EN>,
-				 <&ethsys CLK_ETHDMA_ESW_EN>,
-				 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
-				 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
-				 <&topckgen CLK_TOP_ETH_GMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
-				 <&topckgen CLK_TOP_ETH_SYS_SEL>,
-				 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
-				 <&topckgen CLK_TOP_ETH_MII_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
-				 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
-			clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
-				      "gp3", "esw", "crypto",
-				      "ethwarp_wocpu2", "ethwarp_wocpu1",
-				      "ethwarp_wocpu0", "top_eth_gmii_sel",
-				      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
-				      "top_eth_sys_sel", "top_eth_xgmii_sel",
-				      "top_eth_mii_sel", "top_netsys_sel",
-				      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
-				      "top_netsys_sync_250m_sel",
-				      "top_netsys_ppefb_250m_sel",
-				      "top_netsys_warp_sel";
-			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
-					  <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
-					  <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
-					  <&topckgen CLK_TOP_SGM_0_SEL>,
-					  <&topckgen CLK_TOP_SGM_1_SEL>;
-			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
-						 <&topckgen CLK_TOP_NET1PLL_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>,
-						 <&apmixedsys CLK_APMIXED_SGMPLL>;
-			mediatek,ethsys = <&ethsys>;
-			mediatek,infracfg = <&topmisc>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gmac0: mac@0 {
-				compatible = "mediatek,eth-mac";
-				reg = <0>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-
-			gmac1: mac@1 {
-				compatible = "mediatek,eth-mac";
-				reg = <1>;
-				status = "disabled";
-				pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
-				phys = <&xfi_tphy1>;
-			};
-
-			gmac2: mac@2 {
-				compatible = "mediatek,eth-mac";
-				reg = <2>;
-				status = "disabled";
-				pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
-				phys = <&xfi_tphy0>;
-			};
-
-			mdio_bus: mdio-bus {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* internal 2.5G PHY */
-				int_2p5g_phy: ethernet-phy@15 {
-					compatible = "ethernet-phy-ieee802.3-c45";
-					reg = <15>;
-					phy-mode = "internal";
-				};
-			};
-		};
-
-		crypto: crypto@15600000 {
-			compatible = "inside-secure,safexcel-eip197b";
-			reg = <0 0x15600000 0 0x180000>;
-			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-			status = "okay";
-		};
-	};
-
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <1000>;
-			polling-delay = <1000>;
-			thermal-sensors = <&lvts 0>;
-
-			trips {
-				cpu_trip_crit: crit {
-					temperature = <125000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-
-				cpu_trip_hot: hot {
-					temperature = <120000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-
-				cpu_trip_active_high: active-high {
-					temperature = <115000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_med: active-med {
-					temperature = <85000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-
-				cpu_trip_active_low: active-low {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-			};
-
-			cooling-maps {
-				cpu-active-high {
-				/* active: set fan to cooling level 2 */
-					cooling-device = <&fan 3 3>;
-					trip = <&cpu_trip_active_high>;
-				};
-
-				cpu-active-low {
-				/* active: set fan to cooling level 1 */
-					cooling-device = <&fan 2 2>;
-					trip = <&cpu_trip_active_med>;
-				};
-
-				cpu-passive {
-				/* passive: set fan to cooling level 0 */
-					cooling-device = <&fan 1 1>;
-					trip = <&cpu_trip_active_low>;
-				};
-			};
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
deleted file mode 100644
index e2e06d1eca..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c
+++ /dev/null
@@ -1,316 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-
-#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
-
-#define MD32_EN					BIT(0)
-#define PMEM_PRIORITY				BIT(8)
-#define DMEM_PRIORITY				BIT(16)
-
-#define BASE100T_STATUS_EXTEND			0x10
-#define BASE1000T_STATUS_EXTEND			0x11
-#define EXTEND_CTRL_AND_STATUS			0x16
-
-#define PHY_AUX_CTRL_STATUS			0x1d
-#define   PHY_AUX_DPX_MASK			GENMASK(5, 5)
-#define   PHY_AUX_SPEED_MASK			GENMASK(4, 2)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC		0xa2
-#define   MTK_PHY_FDX_ENABLE			BIT(5)
-
-#define MTK_PHY_LPI_PCS_DSP_CTRL		0x121
-#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL			0x24
-#define   MTK_PHY_LED0_ON_LINK1000		BIT(0)
-#define   MTK_PHY_LED0_ON_LINK100		BIT(1)
-#define   MTK_PHY_LED0_ON_LINK10		BIT(2)
-#define   MTK_PHY_LED0_ON_LINK2500		BIT(7)
-#define   MTK_PHY_LED0_POLARITY			BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL			0x26
-#define   MTK_PHY_LED1_ON_FDX			BIT(4)
-#define   MTK_PHY_LED1_ON_HDX			BIT(5)
-#define   MTK_PHY_LED1_POLARITY			BIT(14)
-
-#define MTK_EXT_PAGE_ACCESS			0x1f
-#define MTK_PHY_PAGE_STANDARD			0x0000
-#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
-
-struct mtk_i2p5ge_phy_priv {
-	bool fw_loaded;
-};
-
-enum {
-	PHY_AUX_SPD_10 = 0,
-	PHY_AUX_SPD_100,
-	PHY_AUX_SPD_1000,
-	PHY_AUX_SPD_2500,
-};
-
-static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
-{
-	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
-{
-	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
-static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
-{
-	struct mtk_i2p5ge_phy_priv *phy_priv;
-
-	phy_priv = devm_kzalloc(&phydev->mdio.dev,
-				sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
-	if (!phy_priv)
-		return -ENOMEM;
-
-	phydev->priv = phy_priv;
-
-	return 0;
-}
-
-static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
-{
-	int ret, i;
-	const struct firmware *fw;
-	struct device *dev = &phydev->mdio.dev;
-	struct device_node *np;
-	void __iomem *pmb_addr;
-	void __iomem *md32_en_cfg_base;
-	struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
-	u16 reg;
-	struct pinctrl *pinctrl;
-
-	if (!phy_priv->fw_loaded) {
-		np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
-		if (!np)
-			return -ENOENT;
-		pmb_addr = of_iomap(np, 0);
-		if (!pmb_addr)
-			return -ENOMEM;
-		md32_en_cfg_base = of_iomap(np, 1);
-		if (!md32_en_cfg_base)
-			return -ENOMEM;
-
-		ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
-		if (ret) {
-			dev_err(dev, "failed to load firmware: %s, ret: %d\n",
-				MT7988_2P5GE_PMB, ret);
-			return ret;
-		}
-
-		reg = readw(md32_en_cfg_base);
-		if (reg & MD32_EN) {
-			phy_set_bits(phydev, 0, BIT(15));
-			usleep_range(10000, 11000);
-		}
-		phy_set_bits(phydev, 0, BIT(11));
-
-		/* Write magic number to safely stall MCU */
-		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
-		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
-
-		for (i = 0; i < fw->size - 1; i += 4)
-			writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
-		release_firmware(fw);
-
-		writew(reg & ~MD32_EN, md32_en_cfg_base);
-		writew(reg | MD32_EN, md32_en_cfg_base);
-		phy_set_bits(phydev, 0, BIT(15));
-		dev_info(dev, "Firmware loading/trigger ok.\n");
-
-		phy_priv->fw_loaded = true;
-	}
-
-	/* Setup LED */
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
-			 MTK_PHY_LED0_ON_LINK10 |
-			 MTK_PHY_LED0_ON_LINK100 |
-			 MTK_PHY_LED0_ON_LINK1000 |
-			 MTK_PHY_LED0_ON_LINK2500);
-	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
-			 MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
-
-	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
-	if (IS_ERR(pinctrl)) {
-		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
-		return PTR_ERR(pinctrl);
-	}
-
-	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
-		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
-
-	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
-	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-	__phy_write(phydev, 0x11, 0xfbfa);
-	__phy_write(phydev, 0x12, 0xc3);
-	__phy_write(phydev, 0x10, 0x87f8);
-	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-	return 0;
-}
-
-static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
-{
-	bool changed = false;
-	u32 adv;
-	int ret;
-
-	if (phydev->autoneg == AUTONEG_DISABLE) {
-		/* Configure half duplex with genphy_setup_forced,
-		 * because genphy_c45_pma_setup_forced does not support.
-		 */
-		return phydev->duplex != DUPLEX_FULL
-			? genphy_setup_forced(phydev)
-			: genphy_c45_pma_setup_forced(phydev);
-	}
-
-	ret = genphy_c45_an_config_aneg(phydev);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
-	ret = phy_modify_changed(phydev, MII_CTRL1000,
-				 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
-				 adv);
-	if (ret < 0)
-		return ret;
-	if (ret > 0)
-		changed = true;
-
-	return genphy_c45_check_and_restart_aneg(phydev, changed);
-}
-
-static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_read_abilities(phydev);
-	if (ret)
-		return ret;
-
-	/* We don't support HDX at MAC layer on mt7988.
-	 * So mask phy's HDX capabilities, too.
-	 */
-	linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported);
-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-
-	return 0;
-}
-
-static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = genphy_update_link(phydev);
-	if (ret)
-		return ret;
-
-	phydev->speed = SPEED_UNKNOWN;
-	phydev->duplex = DUPLEX_UNKNOWN;
-	phydev->pause = 0;
-	phydev->asym_pause = 0;
-
-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
-		ret = genphy_c45_read_lpa(phydev);
-		if (ret < 0)
-			return ret;
-
-		/* Read the link partner's 1G advertisement */
-		ret = phy_read(phydev, MII_STAT1000);
-		if (ret < 0)
-			return ret;
-		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
-	} else if (phydev->autoneg == AUTONEG_DISABLE) {
-		linkmode_zero(phydev->lp_advertising);
-	}
-
-	ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
-	if (ret < 0)
-		return ret;
-
-	switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
-	case PHY_AUX_SPD_10:
-		phydev->speed = SPEED_10;
-		break;
-	case PHY_AUX_SPD_100:
-		phydev->speed = SPEED_100;
-		break;
-	case PHY_AUX_SPD_1000:
-		phydev->speed = SPEED_1000;
-		break;
-	case PHY_AUX_SPD_2500:
-		phydev->speed = SPEED_2500;
-		break;
-	}
-
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
-	if (ret < 0)
-		return ret;
-
-	phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
-	/* FIXME: The current firmware always enables rate adaptation mode. */
-	phydev->rate_matching = RATE_MATCH_PAUSE;
-
-	return 0;
-}
-
-static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
-					      phy_interface_t iface)
-{
-	return RATE_MATCH_PAUSE;
-}
-
-static struct phy_driver mtk_gephy_driver[] = {
-	{
-		PHY_ID_MATCH_MODEL(0x00339c11),
-		.name		= "MediaTek MT798x 2.5GbE PHY",
-		.probe		= mt7988_2p5ge_phy_probe,
-		.config_init	= mt7988_2p5ge_phy_config_init,
-		.config_aneg    = mt7988_2p5ge_phy_config_aneg,
-		.get_features	= mt7988_2p5ge_phy_get_features,
-		.read_status	= mt7988_2p5ge_phy_read_status,
-		.get_rate_matching	= mt7988_2p5ge_phy_get_rate_matching,
-		.suspend	= genphy_suspend,
-		.resume		= genphy_resume,
-		.read_page	= mtk_2p5ge_phy_read_page,
-		.write_page	= mtk_2p5ge_phy_write_page,
-	},
-};
-
-module_phy_driver(mtk_gephy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
-	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
-	{ }
-};
-
-MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MT7988_2P5GE_PMB);
diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
deleted file mode 100644
index 9f92911245..0000000000
--- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
+++ /dev/null
@@ -1,1517 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7988 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-enum MT7988_PINCTRL_REG_PAGE {
-	GPIO_BASE,
-	IOCFG_TR_BASE,
-	IOCFG_BR_BASE,
-	IOCFG_RB_BASE,
-	IOCFG_LB_BASE,
-	IOCFG_TL_BASE,
-};
-
-#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits)                                                \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
-			_x_bits)                                               \
-	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
-		       _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
-	PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
-	PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
-	PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
-	PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
-	PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
-	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
-	PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
-	PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
-	PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
-	PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
-
-	PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
-	PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
-	PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
-	PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
-	PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
-	PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
-	PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
-	PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
-	PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
-	PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
-	PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
-	PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
-	PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
-	PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
-	PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
-	PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
-	PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
-	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
-	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
-	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
-	PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
-	PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
-	PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
-	PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
-	PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
-	PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
-	PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
-	PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
-	PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
-	PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
-	PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
-	PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
-	PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
-	PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
-	PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
-	PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
-	PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
-	PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
-	PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
-	PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
-	PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
-	PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
-	PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
-	PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
-	PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
-	PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
-	PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
-
-	PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
-	PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
-
-	PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
-	PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
-
-	PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
-	PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
-	PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
-	PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
-	PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
-	PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
-	PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
-	PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
-	PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
-	PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
-	PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
-	PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
-	PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
-	PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
-	PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
-	PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
-	PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
-	PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
-	PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
-	PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
-	PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
-	PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
-	PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
-	PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
-	PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
-	PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
-	PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
-	PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
-	PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
-	PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
-	PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
-	PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
-	PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
-	PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-
-	PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
-	PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
-	PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
-	PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
-	PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
-	PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
-	PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
-	PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
-	PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
-	PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
-	PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
-	PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
-	PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
-
-	PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
-	PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
-
-	PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
-	PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-
-	PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
-	PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
-	PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
-	PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
-};
-
-static const unsigned int mt7988_pull_type[] = {
-	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,    /*7*/
-	MTK_PULL_PU_PD_TYPE,    /*8*/ MTK_PULL_PU_PD_TYPE,    /*9*/
-	MTK_PULL_PU_PD_TYPE,    /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,    /*13*/
-	MTK_PULL_PU_PD_TYPE,    /*14*/ MTK_PULL_PD_TYPE,       /*15*/
-	MTK_PULL_PD_TYPE,       /*16*/ MTK_PULL_PD_TYPE,       /*17*/
-	MTK_PULL_PD_TYPE,       /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,    /*63*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE,       /*71*/
-	MTK_PULL_PD_TYPE,       /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,    /*75*/
-	MTK_PULL_PU_PD_TYPE,    /*76*/ MTK_PULL_PU_PD_TYPE,    /*77*/
-	MTK_PULL_PU_PD_TYPE,    /*78*/ MTK_PULL_PU_PD_TYPE,    /*79*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
-	MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
-};
-
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
-	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
-	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
-	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
-	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
-	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
-	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
-	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
-	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
-	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
-	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
-	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
-	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7988_pins[] = {
-	MT7988_PIN(0, "UART2_RXD"),
-	MT7988_PIN(1, "UART2_TXD"),
-	MT7988_PIN(2, "UART2_CTS"),
-	MT7988_PIN(3, "UART2_RTS"),
-	MT7988_PIN(4, "GPIO_A"),
-	MT7988_PIN(5, "SMI_0_MDC"),
-	MT7988_PIN(6, "SMI_0_MDIO"),
-	MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
-	MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
-	MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
-	MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
-	MT7988_PIN(11, "GPIO_P"),
-	MT7988_PIN(12, "WATCHDOG"),
-	MT7988_PIN(13, "GPIO_RESET"),
-	MT7988_PIN(14, "GPIO_WPS"),
-	MT7988_PIN(15, "PMIC_I2C_SCL"),
-	MT7988_PIN(16, "PMIC_I2C_SDA"),
-	MT7988_PIN(17, "I2C_1_SCL"),
-	MT7988_PIN(18, "I2C_1_SDA"),
-	MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
-	MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
-	MT7988_PIN(21, "PWMD1"),
-	MT7988_PIN(22, "SPI0_WP"),
-	MT7988_PIN(23, "SPI0_HOLD"),
-	MT7988_PIN(24, "SPI0_CSB"),
-	MT7988_PIN(25, "SPI0_MISO"),
-	MT7988_PIN(26, "SPI0_MOSI"),
-	MT7988_PIN(27, "SPI0_CLK"),
-	MT7988_PIN(28, "SPI1_CSB"),
-	MT7988_PIN(29, "SPI1_MISO"),
-	MT7988_PIN(30, "SPI1_MOSI"),
-	MT7988_PIN(31, "SPI1_CLK"),
-	MT7988_PIN(32, "SPI2_CLK"),
-	MT7988_PIN(33, "SPI2_MOSI"),
-	MT7988_PIN(34, "SPI2_MISO"),
-	MT7988_PIN(35, "SPI2_CSB"),
-	MT7988_PIN(36, "SPI2_HOLD"),
-	MT7988_PIN(37, "SPI2_WP"),
-	MT7988_PIN(38, "EMMC_RSTB"),
-	MT7988_PIN(39, "EMMC_DSL"),
-	MT7988_PIN(40, "EMMC_CK"),
-	MT7988_PIN(41, "EMMC_CMD"),
-	MT7988_PIN(42, "EMMC_DATA_7"),
-	MT7988_PIN(43, "EMMC_DATA_6"),
-	MT7988_PIN(44, "EMMC_DATA_5"),
-	MT7988_PIN(45, "EMMC_DATA_4"),
-	MT7988_PIN(46, "EMMC_DATA_3"),
-	MT7988_PIN(47, "EMMC_DATA_2"),
-	MT7988_PIN(48, "EMMC_DATA_1"),
-	MT7988_PIN(49, "EMMC_DATA_0"),
-	MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
-	MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
-	MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
-	MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
-	MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
-	MT7988_PIN(55, "UART0_RXD"),
-	MT7988_PIN(56, "UART0_TXD"),
-	MT7988_PIN(57, "PWMD0"),
-	MT7988_PIN(58, "JTAG_JTDI"),
-	MT7988_PIN(59, "JTAG_JTDO"),
-	MT7988_PIN(60, "JTAG_JTMS"),
-	MT7988_PIN(61, "JTAG_JTCLK"),
-	MT7988_PIN(62, "JTAG_JTRST_N"),
-	MT7988_PIN(63, "USB_DRV_VBUS_P1"),
-	MT7988_PIN(64, "LED_A"),
-	MT7988_PIN(65, "LED_B"),
-	MT7988_PIN(66, "LED_C"),
-	MT7988_PIN(67, "LED_D"),
-	MT7988_PIN(68, "LED_E"),
-	MT7988_PIN(69, "GPIO_B"),
-	MT7988_PIN(70, "GPIO_C"),
-	MT7988_PIN(71, "I2C_2_SCL"),
-	MT7988_PIN(72, "I2C_2_SDA"),
-	MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
-	MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
-	MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
-	MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
-	MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
-	MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
-	MT7988_PIN(79, "USB_DRV_VBUS_P0"),
-	MT7988_PIN(80, "UART1_RXD"),
-	MT7988_PIN(81, "UART1_TXD"),
-	MT7988_PIN(82, "UART1_CTS"),
-	MT7988_PIN(83, "UART1_RTS"),
-};
-
-/* jtag */
-static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-
-static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-
-static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-
-static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-
-static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-
-static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* int_usxgmii */
-static int mt7988_int_usxgmii_pins[] = { 2, 3 };
-static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-
-/* pwm */
-static int mt7988_pwm0_pins[] = { 57 };
-static int mt7988_pwm0_funcs[] = { 1 };
-
-static int mt7988_pwm1_pins[] = { 21 };
-static int mt7988_pwm1_funcs[] = { 1 };
-
-static int mt7988_pwm2_pins[] = { 80 };
-static int mt7988_pwm2_funcs[] = { 2 };
-
-static int mt7988_pwm3_pins[] = { 81 };
-static int mt7988_pwm3_funcs[] = { 2 };
-
-static int mt7988_pwm4_pins[] = { 82 };
-static int mt7988_pwm4_funcs[] = { 2 };
-
-static int mt7988_pwm5_pins[] = { 83 };
-static int mt7988_pwm5_funcs[] = { 2 };
-
-static int mt7988_pwm6_pins[] = { 69 };
-static int mt7988_pwm6_funcs[] = { 3 };
-
-static int mt7988_pwm7_pins[] = { 70 };
-static int mt7988_pwm7_funcs[] = { 3 };
-
-/* dfd */
-static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2c */
-static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_0_pins[] = { 5, 6 };
-static int mt7988_i2c0_0_funcs[] = { 2, 2 };
-
-static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-
-static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_1_pins[] = { 15, 16 };
-static int mt7988_i2c0_1_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-
-static int mt7988_i2c1_0_pins[] = { 17, 18 };
-static int mt7988_i2c1_0_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-
-static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c1_2_pins[] = { 69, 70 };
-static int mt7988_i2c1_2_funcs[] = { 2, 2 };
-
-static int mt7988_i2c2_0_pins[] = { 69, 70 };
-static int mt7988_i2c2_0_funcs[] = { 4, 4 };
-
-static int mt7988_i2c2_1_pins[] = { 71, 72 };
-static int mt7988_i2c2_1_funcs[] = { 1, 1 };
-
-/* eth */
-static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-
-static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-
-/* pcie */
-static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-
-static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-
-/* pmic */
-static int mt7988_pmic_pins[] = { 11 };
-static int mt7988_pmic_funcs[] = { 1 };
-
-/* watchdog */
-static int mt7988_watchdog_pins[] = { 12 };
-static int mt7988_watchdog_funcs[] = { 1 };
-
-/* spi */
-static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-
-static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-
-/* flash */
-static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-static int mt7988_emmc_45_pins[] = {
-	21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
-};
-static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
-static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
-				     44, 45, 46, 47, 48, 49 };
-static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* uart */
-static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-
-static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-
-static int mt7988_uart0_pins[] = { 55, 56 };
-static int mt7988_uart0_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-
-static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
-static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
-
-static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-
-/* udi */
-static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2s */
-static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
-
-/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
-
-/* led */
-static int mt7988_gbe0_led1_pins[] = { 58 };
-static int mt7988_gbe0_led1_funcs[] = { 6 };
-static int mt7988_gbe1_led1_pins[] = { 59 };
-static int mt7988_gbe1_led1_funcs[] = { 6 };
-static int mt7988_gbe2_led1_pins[] = { 60 };
-static int mt7988_gbe2_led1_funcs[] = { 6 };
-static int mt7988_gbe3_led1_pins[] = { 61 };
-static int mt7988_gbe3_led1_funcs[] = { 6 };
-
-static int mt7988_2p5gbe_led1_pins[] = { 62 };
-static int mt7988_2p5gbe_led1_funcs[] = { 6 };
-
-static int mt7988_gbe0_led0_pins[] = { 64 };
-static int mt7988_gbe0_led0_funcs[] = { 1 };
-static int mt7988_gbe1_led0_pins[] = { 65 };
-static int mt7988_gbe1_led0_funcs[] = { 1 };
-static int mt7988_gbe2_led0_pins[] = { 66 };
-static int mt7988_gbe2_led0_funcs[] = { 1 };
-static int mt7988_gbe3_led0_pins[] = { 67 };
-static int mt7988_gbe3_led0_funcs[] = { 1 };
-
-static int mt7988_2p5gbe_led0_pins[] = { 68 };
-static int mt7988_2p5gbe_led0_funcs[] = { 1 };
-
-/* usb */
-static int mt7988_drv_vbus_p1_pins[] = { 63 };
-static int mt7988_drv_vbus_p1_funcs[] = { 1 };
-
-static int mt7988_drv_vbus_pins[] = { 79 };
-static int mt7988_drv_vbus_funcs[] = { 1 };
-
-static const struct group_desc mt7988_groups[] = {
-	/*  @GPIO(0,1,2,3): uart2 */
-	PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
-	/*  @GPIO(0,1,2,3,4): tops_jtag0_0 */
-	PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
-	/*  @GPIO(2,3): int_usxgmii */
-	PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
-	/*  @GPIO(0,1,2,3,4): dfd */
-	PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
-	/*  @GPIO(0,1): xfi_phy0_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
-	/*  @GPIO(0,1): xfi_phy1_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c0 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
-	/*  @GPIO(3,4): xfi_phy_pll_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
-	/*  @GPIO(5,6) i2c0_0 */
-	PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
-	/*  @GPIO(5,6) i2c1_sfp */
-	PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
-	/*  @GPIO(5,6) xfi_pextp_phy0_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
-	/*  @GPIO(5,6) xfi_pextp_phy1_i2c */
-	PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
-	/*  @GPIO(5,6) mdc_mdio0 */
-	PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
-	/*  @GPIO(7): pcie_wake_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
-	/*  @GPIO(8): pcie_clk_req_n0_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
-	/*  @GPIO(9): pcie_wake_n3_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
-	/*  @GPIO(10): pcie_clk_req_n3 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
-	/*  @GPIO(10): pcie_clk_req_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
-	/*  @GPIO(7,8) pcie_p0_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
-	/*  @GPIO(7,8) pcie_p1_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
-	/*  @GPIO(7,8) pcie_p2_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
-	/*  @GPIO(9,10) pcie_p3_phy_i2c */
-	PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
-	/*  @GPIO(9,10) ckm_phy_i2c */
-	PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
-	/*  @GPIO(11): pmic */
-	PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
-	/*  @GPIO(12): watchdog */
-	PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
-	/*  @GPIO(13): pcie_wake_n0_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
-	/*  @GPIO(14): pcie_wake_n3_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
-	/*  @GPIO(15,16) i2c0_1 */
-	PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
-	/*  @GPIO(15,16) u30_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
-	/*  @GPIO(15,16) u32_phy_i2c0 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
-	/*  @GPIO(15,16) xfi_phy0_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
-	/*  @GPIO(15,16) xfi_phy1_i2c1 */
-	PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
-	/*  @GPIO(15,16) xfi_phy_pll_i2c2 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
-	/*  @GPIO(17,18) i2c1_0 */
-	PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
-	/*  @GPIO(17,18) u30_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
-	/*  @GPIO(17,18) u32_phy_i2c1 */
-	PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
-	/*  @GPIO(17,18) xfi_phy_pll_i2c3 */
-	PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
-	/*  @GPIO(17,18) sgmii0_i2c */
-	PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
-	/*  @GPIO(17,18) sgmii1_i2c */
-	PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
-	/*  @GPIO(19): pcie_2l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
-	/*  @GPIO(20): pcie_1l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
-	/*  @GPIO(21): pwm1 */
-	PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
-	/*  @GPIO(22,23) spi0_wp_hold */
-	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
-	/*  @GPIO(24,25,26,27) spi0 */
-	PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
-	/*  @GPIO(28,29,30,31) spi1 */
-	PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
-	/*  @GPIO(32,33,34,35) spi2 */
-	PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
-	/*  @GPIO(36,37) spi2_wp_hold */
-	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
-	/*  @GPIO(22,23,24,25,26,27) snfi */
-	PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
-	/*  @GPIO(22,23) tops_uart0_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
-	/*  @GPIO(28,29,30,31) uart2_0 */
-	PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
-	/*  @GPIO(32,33,34,35) uart1_0 */
-	PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
-	/*  @GPIO(32,33,34,35) uart2_1 */
-	PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
-	/*  @GPIO(28) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(29) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(30) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(28,29) tops_uart1_0 */
-	PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
-	/*  @GPIO(30,31) tops_uart0_1 */
-	PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
-	/*  @GPIO(36,37) tops_uart1_1 */
-	PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
-	/*  @GPIO(32,33,34,35,36) udi */
-	PINCTRL_PIN_GROUP("udi", mt7988_udi),
-	/*  @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
-	PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
-	/*  @GPIO(32,33,34,35,36,37) sdcard */
-	PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
-	/*  @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
-	PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
-	/*  @GPIO(28,29) 2p5g_ext_mdio */
-	PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
-	/*  @GPIO(30,31) gbe_ext_mdio */
-	PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
-	/*  @GPIO(50,51,52,53,54) i2s */
-	PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
-	/*  @GPIO(50,51,52,53) pcm */
-	PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
-	/*  @GPIO(55,56) uart0 */
-	PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
-	/*  @GPIO(55,56) tops_uart0_2 */
-	PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
-	/*  @GPIO(50,51,52,53) uart2_2 */
-	PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
-	/*  @GPIO(50,51,52,53,54) wo0_jtag */
-	PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
-	/*  @GPIO(50,51,52,53,54) wo1-wo1_jtag */
-	PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
-	/*  @GPIO(50,51,52,53,54) wo2_jtag */
-	PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
-	/*  @GPIO(57) pwm0 */
-	PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
-	/*  @GPIO(58,59,60,61,62) jtag */
-	PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
-	/*  @GPIO(58,59,60,61,62) tops_jtag0_1 */
-	PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
-	/*  @GPIO(58,59,60,61) uart2_3 */
-	PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
-	/*  @GPIO(58,59,60,61) uart1_1 */
-	PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
-	/*  @GPIO(58,59,60,61) gbe_led1 */
-	PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
-	PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
-	PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
-	PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
-	/*  @GPIO(62) 2p5gbe_led1 */
-	PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
-	/*  @GPIO(64,65,66,67) gbe_led0 */
-	PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
-	PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
-	PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
-	PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
-	/*  @GPIO(68) 2p5gbe_led0 */
-	PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
-	/*  @GPIO(63) drv_vbus_p1 */
-	PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
-	/*  @GPIO(63) pcie_clk_req_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
-	/*  @GPIO(69, 70) mdc_mdio1 */
-	PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
-	/*  @GPIO(69, 70) i2c1_2 */
-	PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
-	/*  @GPIO(69) pwm6 */
-	PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
-	/*  @GPIO(70) pwm7 */
-	PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
-	/*  @GPIO(69,70) i2c2_0 */
-	PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
-	/*  @GPIO(71,72) i2c2_1 */
-	PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
-	/*  @GPIO(73) pcie_2l_1_pereset */
-	PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
-	/*  @GPIO(74) pcie_1l_0_pereset */
-	PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
-	/*  @GPIO(75) pcie_wake_n1_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
-	/*  @GPIO(76) pcie_clk_req_n1 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
-	/*  @GPIO(77) pcie_wake_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
-	/*  @GPIO(78) pcie_clk_req_n2_0 */
-	PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
-	/*  @GPIO(79) drv_vbus */
-	PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
-	/*  @GPIO(79) pcie_wake_n2_1 */
-	PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
-	/*  @GPIO(80,81,82,83) uart1_2 */
-	PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
-	/*  @GPIO(80,81) uart1_2_lite */
-	PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
-	/*  @GPIO(80) pwm2 */
-	PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
-	/*  @GPIO(81) pwm3 */
-	PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
-	/*  @GPIO(82) pwm4 */
-	PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
-	/*  @GPIO(83) pwm5 */
-	PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
-	/*  @GPIO(80) net_wo0_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
-	/*  @GPIO(81) net_wo1_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
-	/*  @GPIO(82) net_wo2_uart_txd_0 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
-	/*  @GPIO(80,81) tops_uart1_2 */
-	PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
-	/*  @GPIO(80) net_wo0_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
-	/*  @GPIO(81) net_wo1_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
-	/*  @GPIO(82) net_wo2_uart_txd_1 */
-	PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char * const mt7988_jtag_groups[] = {
-	"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
-	"wo2_jtag",	"jtag",	    "tops_jtag0_1",
-};
-static const char * const mt7988_int_usxgmii_groups[] = {
-	"int_usxgmii",
-};
-static const char * const mt7988_pwm_groups[] = {
-	"pwm0", "pwm1", "pwm2", "pwm3", "pwm4",	"pwm5",	"pwm6", "pwm7"
-};
-static const char * const mt7988_dfd_groups[] = {
-	"dfd",
-};
-static const char * const mt7988_i2c_groups[] = {
-	"xfi_phy0_i2c0",
-	"xfi_phy1_i2c0",
-	"xfi_phy_pll_i2c0",
-	"xfi_phy_pll_i2c1",
-	"i2c0_0",
-	"i2c1_sfp",
-	"xfi_pextp_phy0_i2c",
-	"xfi_pextp_phy1_i2c",
-	"i2c0_1",
-	"u30_phy_i2c0",
-	"u32_phy_i2c0",
-	"xfi_phy0_i2c1",
-	"xfi_phy1_i2c1",
-	"xfi_phy_pll_i2c2",
-	"i2c1_0",
-	"u30_phy_i2c1",
-	"u32_phy_i2c1",
-	"xfi_phy_pll_i2c3",
-	"sgmii0_i2c",
-	"sgmii1_i2c",
-	"i2c1_2",
-	"i2c2_0",
-	"i2c2_1",
-};
-static const char * const mt7988_ethernet_groups[] = {
-	"mdc_mdio0",
-	"2p5g_ext_mdio",
-	"gbe_ext_mdio",
-	"mdc_mdio1",
-};
-static const char * const mt7988_pcie_groups[] = {
-	"pcie_wake_n0_0",    "pcie_clk_req_n0_0", "pcie_wake_n3_0",
-	"pcie_clk_req_n3",   "pcie_p0_phy_i2c",	  "pcie_p1_phy_i2c",
-	"pcie_p3_phy_i2c",   "pcie_p2_phy_i2c",	  "ckm_phy_i2c",
-	"pcie_wake_n0_1",    "pcie_wake_n3_1",	  "pcie_2l_0_pereset",
-	"pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
-	"pcie_1l_0_pereset", "pcie_wake_n1_0",	  "pcie_clk_req_n1",
-	"pcie_wake_n2_0",    "pcie_clk_req_n2_0", "pcie_wake_n2_1",
-	"pcie_clk_req_n0_1"
-};
-static const char * const mt7988_pmic_groups[] = {
-	"pmic",
-};
-static const char * const mt7988_wdt_groups[] = {
-	"watchdog",
-};
-static const char * const mt7988_spi_groups[] = {
-	"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
-};
-static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
-						    "emmc_51" };
-static const char * const mt7988_uart_groups[] = {
-	"uart2",
-	"tops_uart0_0",
-	"uart2_0",
-	"uart1_0",
-	"uart2_1",
-	"net_wo0_uart_txd_0",
-	"net_wo1_uart_txd_0",
-	"net_wo2_uart_txd_0",
-	"tops_uart1_0",
-	"ops_uart0_1",
-	"ops_uart1_1",
-	"uart0",
-	"tops_uart0_2",
-	"uart1_1",
-	"uart2_3",
-	"uart1_2",
-	"uart1_2_lite",
-	"tops_uart1_2",
-	"net_wo0_uart_txd_1",
-	"net_wo1_uart_txd_1",
-	"net_wo2_uart_txd_1",
-};
-static const char * const mt7988_udi_groups[] = {
-	"udi",
-};
-static const char * const mt7988_audio_groups[] = {
-	"i2s", "pcm",
-};
-static const char * const mt7988_led_groups[] = {
-	"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
-	"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
-	"wf5g_led0",   "wf5g_led1",
-};
-static const char * const mt7988_usb_groups[] = {
-	"drv_vbus",
-	"drv_vbus_p1",
-};
-
-static const struct function_desc mt7988_functions[] = {
-	{ "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
-	{ "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
-	{ "int_usxgmii", mt7988_int_usxgmii_groups,
-	  ARRAY_SIZE(mt7988_int_usxgmii_groups) },
-	{ "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
-	{ "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
-	{ "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
-	{ "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
-	{ "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
-	{ "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
-	{ "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
-	{ "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
-	{ "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
-	{ "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
-	{ "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
-	{ "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
-	{ "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
-};
-
-static const struct mtk_eint_hw mt7988_eint_hw = {
-	.port_mask = 7,
-	.ports = 7,
-	.ap_num = ARRAY_SIZE(mt7988_pins),
-	.db_cnt = 16,
-};
-
-static const char * const mt7988_pinctrl_register_base_names[] = {
-	"gpio_base",	 "iocfg_tr_base", "iocfg_br_base",
-	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-};
-
-static struct mtk_pin_soc mt7988_data = {
-	.reg_cal = mt7988_reg_cals,
-	.pins = mt7988_pins,
-	.npins = ARRAY_SIZE(mt7988_pins),
-	.grps = mt7988_groups,
-	.ngrps = ARRAY_SIZE(mt7988_groups),
-	.funcs = mt7988_functions,
-	.nfuncs = ARRAY_SIZE(mt7988_functions),
-	.eint_hw = &mt7988_eint_hw,
-	.gpio_m = 0,
-	.ies_present = false,
-	.base_names = mt7988_pinctrl_register_base_names,
-	.nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
-	.bias_disable_set = mtk_pinconf_bias_disable_set,
-	.bias_disable_get = mtk_pinconf_bias_disable_get,
-	.bias_set = mtk_pinconf_bias_set,
-	.bias_get = mtk_pinconf_bias_get,
-	.pull_type = mt7988_pull_type,
-	.bias_set_combo = mtk_pinconf_bias_set_combo,
-	.bias_get_combo = mtk_pinconf_bias_get_combo,
-	.drive_set = mtk_pinconf_drive_set_rev1,
-	.drive_get = mtk_pinconf_drive_get_rev1,
-	.adv_pull_get = mtk_pinconf_adv_pull_get,
-	.adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7988_pinctrl_of_match[] = {
-	{
-		.compatible = "mediatek,mt7988-pinctrl",
-	},
-	{}
-};
-
-static int mt7988_pinctrl_probe(struct platform_device *pdev)
-{
-	return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
-}
-
-static struct platform_driver mt7988_pinctrl_driver = {
-	.driver = {
-		.name = "mt7988-pinctrl",
-		.of_match_table = mt7988_pinctrl_of_match,
-	},
-	.probe = mt7988_pinctrl_probe,
-};
-
-static int __init mt7988_pinctrl_init(void)
-{
-	return platform_driver_register(&mt7988_pinctrl_driver);
-}
-arch_initcall(mt7988_pinctrl_init);
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi
index 54cfd0b4b9..012c6e4e5b 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7981.dtsi
@@ -416,7 +416,7 @@
 
 		pcie: pcie@11280000 {
 			compatible = "mediatek,mt7981-pcie",
-				     "mediatek,mt7986-pcie";
+				     "mediatek,mt8192-pcie";
 			reg = <0 0x11280000 0 0x4000>;
 			reg-names = "pcie-mac";
 			ranges = <0x82000000 0 0x20000000
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts
new file mode 100644
index 0000000000..efcf0ec358
--- /dev/null
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+/ {
+	model = "Bananapi BPI-R4 2.5GE PoE";
+	compatible = "bananapi,bpi-r4-poe",
+		     "mediatek,mt7988a";
+};
+
+&gmac1 {
+	phy-mode = "internal";
+	phy-connection-type = "internal";
+	phy = <&int_2p5g_phy>;
+	status = "okay";
+};
+
+&int_2p5g_phy {
+	pinctrl-names = "i2p5gbe-led";
+	pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
index d72051d187..d2c223b4ef 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -4,48 +4,13 @@
  * Author: Sam.Shih <sam.shih@mediatek.com>
  */
 
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+#include "mt7988a-bananapi-bpi-r4.dtsi"
 
 / {
 	model = "Bananapi BPI-R4";
 	compatible = "bananapi,bpi-r4",
 		     "mediatek,mt7988a";
 
-	aliases {
-		serial0 = &uart0;
-		led-boot = &led_green;
-		led-failsafe = &led_green;
-		led-running = &led_green;
-		led-upgrade = &led_green;
-	};
-
-	chosen {
-		stdout-path = &uart0;
-		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
-		rootdisk-spim-nand = <&ubi_rootfs>;
-	};
-
-	memory {
-		reg = <0x00 0x40000000 0x00 0x10000000>;
-	};
-
-	/* SFP1 cage (WAN) */
-	sfp1: sfp1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c_sfp1>;
-		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
-		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
-		maximum-power-milliwatt = <3000>;
-	};
-
 	/* SFP2 cage (LAN) */
 	sfp2: sfp2 {
 		compatible = "sff,sfp";
@@ -57,42 +22,6 @@
 		rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
 		maximum-power-milliwatt = <3000>;
 	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "WPS";
-			linux,code = <KEY_RESTART>;
-			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		led_green: led-green {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led_blue: led-blue {
-			function = LED_FUNCTION_WPS;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-};
-
-&eth {
-	status = "okay";
-};
-
-&gmac0 {
-	status = "okay";
 };
 
 &gmac1 {
@@ -102,306 +31,10 @@
 	status = "okay";
 };
 
-&gmac2 {
-	sfp = <&sfp1>;
-	managed = "in-band-status";
-	phy-mode = "usxgmii";
-	status = "okay";
-};
-
-&switch {
-	status = "okay";
-};
-
-&gsw_phy0 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_port0 {
-	label = "wan";
-};
-
-&gsw_phy0_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
-	pinctrl-names = "gbe-led";
-	pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
-	status = "okay";
-	color = <LED_COLOR_ID_GREEN>;
-};
-
-&cpu0 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
-	proc-supply = <&rt5190_buck3>;
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	rt5190a_64: rt5190a@64 {
-		compatible = "richtek,rt5190a";
-		reg = <0x64>;
-		vin2-supply = <&rt5190_buck1>;
-		vin3-supply = <&rt5190_buck1>;
-		vin4-supply = <&rt5190_buck1>;
-
-		regulators {
-			rt5190_buck1: buck1 {
-				regulator-name = "rt5190a-buck1";
-				regulator-min-microvolt = <5090000>;
-				regulator-max-microvolt = <5090000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			buck2 {
-				regulator-name = "vcore";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			rt5190_buck3: buck3 {
-				regulator-name = "vproc";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-			};
-			buck4 {
-				regulator-name = "rt5190a-buck4";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-allowed-modes =
-				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-			ldo {
-				regulator-name = "rt5190a-ldo";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_1_pins>;
-	status = "okay";
-
-	pca9545: i2c-switch@70 {
-		reg = <0x70>;
-		compatible = "nxp,pca9545";
-		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+&pca9545 {
+	i2c_sfp2: i2c@2 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-
-		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			eeprom@57 {
-				compatible = "atmel,24c02";
-				reg = <0x57>;
-				address-bits = <8>;
-				page-size = <8>;
-				size = <256>;
-			};
-
-			pcf8563: rtc@51 {
-				compatible = "nxp,pcf8563";
-				reg = <0x51>;
-				status = "disabled";
-			};
-		};
-
-		i2c_sfp1: i2c@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-		};
-
-		i2c_sfp2: i2c@2 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <2>;
-		};
-
-		i2c_wifi: i2c@3 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <3>;
-		};
-	};
-};
-
-/* mPCIe SIM2 */
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>;
-	status = "okay";
-};
-
-/* mPCIe SIM3 */
-&pcie1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie1_pins>;
-	status = "okay";
-};
-
-/* M.2 key-B SIM1 */
-&pcie2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie2_pins>;
-	status = "okay";
-};
-
-/* M.2 key-M SSD */
-&pcie3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3_pins>;
-	status = "okay";
-};
-
-&ssusb1 {
-	status = "okay";
-};
-
-&tphy {
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_flash_pins>;
-	status = "okay";
-
-	spi_nand: spi_nand@0 {
-		compatible = "spi-nand";
-		reg = <0>;
-		spi-max-frequency = <52000000>;
-		spi-tx-buswidth = <4>;
-		spi-rx-buswidth = <4>;
-	};
-};
-
-&spi_nand {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "bl2";
-			reg = <0x0 0x200000>;
-			read-only;
-		};
-
-		partition@200000 {
-			label = "ubi";
-			reg = <0x200000 0x7e00000>;
-			compatible = "linux,ubi";
-
-			volumes {
-				ubi-volume-ubootenv {
-					volname = "ubootenv";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool-layout";
-					};
-				};
-
-				ubi-volume-ubootenv2 {
-					volname = "ubootenv2";
-					nvmem-layout {
-						compatible = "u-boot,env-redundant-bool-layout";
-					};
-				};
-
-				ubi_rootfs: ubi-volume-fit {
-					volname = "fit";
-				};
-			};
-		};
+		reg = <2>;
 	};
 };
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_2_lite_pins>;
-};
-
-&uart2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_3_pins>;
-};
-
-&watchdog {
-	status = "okay";
-};
-
-&xphy {
-	status = "okay";
-};
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
new file mode 100644
index 0000000000..14c615b67c
--- /dev/null
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+	model = "Bananapi BPI-R4";
+	compatible = "bananapi,bpi-r4",
+		     "mediatek,mt7988a";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		led-boot = &led_green;
+		led-failsafe = &led_green;
+		led-running = &led_green;
+		led-upgrade = &led_green;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
+		rootdisk-spim-nand = <&ubi_rootfs>;
+	};
+
+	memory {
+		reg = <0x00 0x40000000 0x00 0x10000000>;
+	};
+
+	/* SFP1 cage (WAN) */
+	sfp1: sfp1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c_sfp1>;
+		los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+		tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+		maximum-power-milliwatt = <3000>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "WPS";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_green: led-green {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led_blue: led-blue {
+			function = LED_FUNCTION_WPS;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&eth {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac2 {
+	sfp = <&sfp1>;
+	managed = "in-band-status";
+	phy-mode = "usxgmii";
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+};
+
+&gsw_phy0 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+	label = "wan";
+};
+
+&gsw_phy0_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+	pinctrl-names = "gbe-led";
+	pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+	status = "okay";
+	color = <LED_COLOR_ID_GREEN>;
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_1_pins>;
+	status = "okay";
+
+	pca9545: i2c-switch@70 {
+		reg = <0x70>;
+		compatible = "nxp,pca9545";
+		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c_rtc: i2c@0 { //eeprom,rtc,ngff
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c02";
+				reg = <0x57>;
+				address-bits = <8>;
+				page-size = <8>;
+				size = <256>;
+			};
+
+			pcf8563: rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+				status = "disabled";
+			};
+		};
+
+		i2c_sfp1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_wifi: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+	status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+	status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_pins>;
+	status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_pins>;
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&fan {
+	pwms = <&pwm 0 50000>;
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_flash_pins>;
+	status = "okay";
+
+	spi_nand: spi_nand@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+		spi-tx-buswidth = <4>;
+		spi-rx-buswidth = <4>;
+	};
+};
+
+&spi_nand {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "bl2";
+			reg = <0x0 0x200000>;
+			read-only;
+		};
+
+		partition@200000 {
+			label = "ubi";
+			reg = <0x200000 0x7e00000>;
+			compatible = "linux,ubi";
+
+			volumes {
+				ubi-volume-ubootenv {
+					volname = "ubootenv";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi-volume-ubootenv2 {
+					volname = "ubootenv2";
+					nvmem-layout {
+						compatible = "u-boot,env-redundant-bool-layout";
+					};
+				};
+
+				ubi_rootfs: ubi-volume-fit {
+					volname = "fit";
+				};
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_2_lite_pins>;
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_3_pins>;
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&xphy {
+	status = "okay";
+};
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
index d21a61ad19..c471b9ed91 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
@@ -22,6 +22,7 @@
 			phy0: ethernet-phy@0 {
 				reg = <0>;
 				compatible = "ethernet-phy-ieee802.3-c45";
+				firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
 				reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
 				reset-assert-us = <100000>;
 				reset-deassert-us = <221000>;
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
index 140391fc45..1490f055b5 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
@@ -22,6 +22,7 @@
 			phy8: ethernet-phy@8 {
 				reg = <8>;
 				compatible = "ethernet-phy-ieee802.3-c45";
+				firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
 				reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
 				reset-assert-us = <100000>;
 				reset-deassert-us = <221000>;
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso
new file mode 100644
index 0000000000..3fe75aca36
--- /dev/null
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+	fragment@0 {
+		target = <&ubi_part>;
+
+		__overlay__ {
+			volumes {
+				ubi_factory: ubi-volume-factory {
+					volname = "factory";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						eeprom_wmac: eeprom@0 {
+							reg = <0x0 0x1e00>;
+						};
+
+						gmac2_mac: eeprom@fffee {
+							reg = <0xfffee 0x6>;
+						};
+
+						gmac1_mac: eeprom@ffff4 {
+							reg = <0xffff4 0x6>;
+						};
+
+						gmac0_mac: eeprom@ffffa {
+							reg = <0xffffa 0x6>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&pcie0>;
+		__overlay__ {
+			pcie@0,0 {
+				reg = <0x0000 0 0 0 0>;
+
+				wifi@0,0 {
+					compatible = "mediatek,mt76";
+					reg = <0x0000 0 0 0 0>;
+					nvmem-cell-names = "eeprom";
+					nvmem-cells = <&eeprom_wmac>;
+				};
+			};
+		};
+	};
+
+	fragment@2 {
+		target = <&gmac0>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac0_mac>;
+		};
+	};
+
+	fragment@3 {
+		target = <&gmac1>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac1_mac>;
+		};
+	};
+
+	fragment@4 {
+		target = <&gmac2>;
+		__overlay__ {
+			nvmem-cell-names = "mac-address";
+			nvmem-cells = <&gmac2_mac>;
+		};
+	};
+};
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
index a9eca00d44..b5a67c725b 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
@@ -23,9 +23,6 @@
 				spi-max-frequency = <52000000>;
 				spi-tx-bus-width = <4>;
 				spi-rx-bus-width = <4>;
-				mediatek,nmbm;
-				mediatek,bmt-max-ratio = <1>;
-				mediatek,bmt-max-reserved-blocks = <64>;
 
 				partitions {
 					compatible = "fixed-partitions";
@@ -34,31 +31,45 @@
 
 					partition@0 {
 						label = "BL2";
-						reg = <0x00000 0x0100000>;
+						reg = <0x00000 0x0200000>;
 						read-only;
 					};
 
-					partition@100000 {
-						label = "u-boot-env";
-						reg = <0x0100000 0x0080000>;
-					};
+					ubi_part: partition@200000 {
+						label = "ubi";
+						reg = <0x0200000 0x7e00000>;
+						compatible = "linux,ubi";
 
-					partition@180000 {
-						label = "Factory";
-						reg = <0x180000 0x0400000>;
-					};
+						volumes {
+							ubi-volume-ubootenv {
+								volname = "ubootenv";
+								nvmem-layout {
+									compatible = "u-boot,env-redundant-bool-layout";
+								};
+							};
 
-					partition@580000 {
-						label = "FIP";
-						reg = <0x580000 0x0200000>;
-					};
+							ubi-volume-ubootenv2 {
+								volname = "ubootenv2";
+								nvmem-layout {
+									compatible = "u-boot,env-redundant-bool-layout";
+								};
+							};
 
-					partition@780000 {
-						label = "ubi";
-						reg = <0x780000 0x7080000>;
+							ubi_root: ubi-volume-fit {
+								volname = "fit";
+							};
+
+						};
 					};
 				};
 			};
 		};
 	};
+
+	fragment@1 {
+		target-path = "/chosen";
+		__overlay__ {
+			rootdisk-spim-nand = <&ubi_root>;
+		};
+	};
 };
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index caad6e5577..9ad068fe05 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -149,8 +149,8 @@
 
 	fan: pwm-fan {
 		compatible = "pwm-fan";
-		/* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
-		cooling-levels = <0 128 255>;
+		/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+		cooling-levels = <0 80 128 255>;
 		#cooling-cells = <2>;
 		#thermal-sensor-cells = <1>;
 		status = "disabled";
@@ -159,7 +159,7 @@
 	pmu {
 		compatible = "arm,cortex-a73-pmu";
 		interrupt-parent = <&gic>;
-		interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	psci {
@@ -1282,6 +1282,7 @@
 				gsw_phy0: ethernet-phy@0 {
 					compatible = "ethernet-phy-ieee802.3-c22";
 					reg = <0>;
+					interrupts = <0>;
 					phy-mode = "internal";
 					nvmem-cells = <&phy_calibration_p0>;
 					nvmem-cell-names = "phy-cal-data";
@@ -1307,6 +1308,7 @@
 				gsw_phy1: ethernet-phy@1 {
 					compatible = "ethernet-phy-ieee802.3-c22";
 					reg = <1>;
+					interrupts = <1>;
 					phy-mode = "internal";
 					nvmem-cells = <&phy_calibration_p1>;
 					nvmem-cell-names = "phy-cal-data";
@@ -1332,6 +1334,7 @@
 				gsw_phy2: ethernet-phy@2 {
 					compatible = "ethernet-phy-ieee802.3-c22";
 					reg = <2>;
+					interrupts = <2>;
 					phy-mode = "internal";
 					nvmem-cells = <&phy_calibration_p2>;
 					nvmem-cell-names = "phy-cal-data";
@@ -1357,6 +1360,7 @@
 				gsw_phy3: ethernet-phy@3 {
 					compatible = "ethernet-phy-ieee802.3-c22";
 					reg = <3>;
+					interrupts = <3>;
 					phy-mode = "internal";
 					nvmem-cells = <&phy_calibration_p3>;
 					nvmem-cell-names = "phy-cal-data";
diff --git a/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c
index e2e06d1eca..d1d01190ed 100644
--- a/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c
+++ b/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c
@@ -137,6 +137,11 @@ static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
 	}
 
 	/* Setup LED */
+
+	/* Set polarity of led0 to active-high for BPI-R4 */
+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+			 MTK_PHY_LED0_POLARITY);
+
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
 			 MTK_PHY_LED0_ON_LINK10 |
 			 MTK_PHY_LED0_ON_LINK100 |
diff --git a/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c b/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c
index 7736905704..5e1e3a3542 100644
--- a/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c
+++ b/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c
@@ -7,7 +7,6 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/of.h>
-#include <linux/version.h>
 
 /**
  * Driver for SmartRG RGBW LED microcontroller.
@@ -160,11 +159,7 @@ srg_led_init_led(struct srg_led_ctrl *sysled_ctrl, struct device_node *np)
 
 static int
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(6,6,0)
-srg_led_probe(struct i2c_client *client, const struct i2c_device_id *id)
-#else
 srg_led_probe(struct i2c_client *client)
-#endif
 {
 	struct device_node *np = client->dev.of_node, *child;
 	struct srg_led_ctrl *sysled_ctrl;
@@ -198,21 +193,13 @@ static void srg_led_disable(struct i2c_client *client)
 		srg_led_i2c_write(sysled_ctrl, i, 0);
 }
 
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0)
 static void
-#else
-static int
-#endif
 srg_led_remove(struct i2c_client *client)
 {
 	struct srg_led_ctrl *sysled_ctrl = i2c_get_clientdata(client);
 
 	srg_led_disable(client);
 	mutex_destroy(&sysled_ctrl->lock);
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0)
-	return 0;
-#endif
 }
 
 static const struct i2c_device_id srg_led_id[] = {
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
index 7f75de8b3b..50ffb7e5d9 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds
@@ -20,7 +20,8 @@ bananapi,bpi-r3-mini)
 	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0"
 	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0"
 	;;
-bananapi,bpi-r4)
+bananapi,bpi-r4|\
+bananapi,bpi-r4-poe)
 	ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx"
 	ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx"
 	ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx"
@@ -54,10 +55,21 @@ netgear,wax220)
 	ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"
 	ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0"
 	;;
+nokia,ea0326gmp)
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" "link"
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "br-lan" "link"
+	ucidef_set_led_netdev "wlan" "WLAN" "green:wlan" "phy1-ap0" "link"
+	;;
 openembed,som7981)
 	ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
 	ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
 	;;
+openwrt,one)
+	ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:0f:green:wan" "eth0" "rx tx"
+	ucidef_set_led_netdev "wanlink" "WANLINK" "mdio-bus:0f:amber:wan" "eth0" "link"
+	ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
+	ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
+	;;
 routerich,ax3000)
 	ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx"
 	ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx"
@@ -65,6 +77,21 @@ routerich,ax3000)
 	ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
 	ucidef_set_led_netdev "wan-off" "wan-off" "red:wan" "wan" "link"
 	;;
+smartrg,sdg-8733|\
+smartrg,sdg-8734)
+	ucidef_set_led_netdev "lan-1-green" "LAN1" "mdio-bus:08:green:lan" "lan1" "link_2500 link_5000"
+	ucidef_set_led_netdev "lan-1-orange" "LAN1" "mdio-bus:08:orange:lan" "lan1" "link_100 link_1000"
+	ucidef_set_led_netdev "lan-1-white" "LAN1" "mdio-bus:08:white:lan" "lan1" "link_10000"
+	ucidef_set_led_netdev "lan-2-green" "LAN2" "mt7530-0:01:green:lan" "lan2" "link_1000"
+	ucidef_set_led_netdev "lan-2-amber" "LAN2" "mt7530-0:01:amber:lan" "lan2" "link_100 link_10"
+	ucidef_set_led_netdev "lan-3-green" "LAN3" "mt7530-0:02:green:lan" "lan3" "link_1000"
+	ucidef_set_led_netdev "lan-3-amber" "LAN3" "mt7530-0:02:amber:lan" "lan3" "link_100 link_10"
+	ucidef_set_led_netdev "lan-4-green" "LAN4" "mt7530-0:03:green:lan" "lan4" "link_1000"
+	ucidef_set_led_netdev "lan-4-amber" "LAN4" "mt7530-0:03:amber:lan" "lan4" "link_100 link_10"
+	ucidef_set_led_netdev "wan-green" "WAN" "mdio-bus:00:green:wan" "wan" "link_2500 link_5000"
+	ucidef_set_led_netdev "wan-orange" "WAN" "mdio-bus:00:orange:wan" "wan" "link_100 link_1000"
+	ucidef_set_led_netdev "wan-white" "WAN" "mdio-bus:00:white:wan" "wan" "link_10000"
+	;;
 xiaomi,mi-router-wr30u-stock|\
 xiaomi,mi-router-wr30u-ubootmod)
 	ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
index 51e02efb39..10dabc965a 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -27,6 +27,7 @@ mediatek_setup_interfaces()
 	jdcloud,re-cp-03|\
 	mediatek,mt7981-rfb|\
 	netcore,n60|\
+	ruijie,rg-x60-pro|\
 	unielec,u7981-01*|\
 	zbtlink,zbt-z8102ax)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
@@ -41,27 +42,32 @@ mediatek_setup_interfaces()
 	edgecore,eap111)
 		ucidef_set_interfaces_lan_wan eth0 eth1
 		;;
-	bananapi,bpi-r4)
+	bananapi,bpi-r4|\
+	bananapi,bpi-r4-poe)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2"
 		;;
 	cmcc,rax3000m|\
 	h3c,magic-nx30-pro|\
+	nokia,ea0326gmp|\
 	zbtlink,zbt-z8103ax)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1
 		;;
 	comfast,cf-e393ax)
 		ucidef_set_interfaces_lan_wan "lan1" eth1
 		;;
-	dlink,aquila-pro-ai-m30-a1)
-		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet
-		;;
+	cudy,m3000-v1|\
+	cudy,tr3000-v1|\
 	glinet,gl-mt2500|\
 	glinet,gl-mt3000|\
 	glinet,gl-x3000|\
 	glinet,gl-xe3000|\
-	openembed,som7981)
+	openembed,som7981|\
+	openwrt,one)
 		ucidef_set_interfaces_lan_wan eth1 eth0
 		;;
+	dlink,aquila-pro-ai-m30-a1)
+		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet
+		;;
 	glinet,gl-mt6000|\
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6088)
@@ -119,7 +125,9 @@ mediatek_setup_macs()
 	local label_mac=""
 
 	case $board in
-	bananapi,bpi-r3)
+	bananapi,bpi-r3|\
+	bananapi,bpi-r3-mini|\
+	bananapi,bpi-r4)
 		wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1)
 		;;
 	cmcc,rax3000m)
@@ -154,10 +162,17 @@ mediatek_setup_macs()
 		wan_mac=$(macaddr_add "$lan_mac" 1)
 		label_mac=$wan_mac
 		;;
+	ruijie,rg-x60-pro)
+		label_mac=$(mtd_get_mac_ascii product_info ethaddr)
+		wan_mac=$label_mac
+		lan_mac=$(macaddr_add "$label_mac" 1)
+		;;
 	smartrg,sdg-8612|\
 	smartrg,sdg-8614|\
 	smartrg,sdg-8622|\
-	smartrg,sdg-8632)
+	smartrg,sdg-8632|\
+	smartrg,sdg-8733|\
+	smartrg,sdg-8734)
 		label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC)
 		wan_mac=$label_mac
 		lan_mac=$(macaddr_add "$label_mac" 1)
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
index bd68ef7415..27a16e0fb7 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
@@ -31,6 +31,9 @@ case "$FIRMWARE" in
 			;;
 		esac
 		;;
+	openwrt,one)
+		caldata_extract "factory" 0x0 0x1000
+		;;
 	ubnt,unifi-6-plus)
 		caldata_extract_mmc "factory" 0x0 0x1000
 		;;
diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index bd6e775963..334d221e21 100644
--- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -36,11 +36,19 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress
 		;;
-	bananapi,bpi-r3)
+	bananapi,bpi-r3|\
+	bananapi,bpi-r3-mini)
 		addr=$(cat /sys/class/net/eth0/address)
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
+	bananapi,bpi-r4|\
+	bananapi,bpi-r4-poe)
+		addr=$(cat /sys/class/net/eth0/address)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+		;;
 	cetron,ct3003)
 		addr=$(mtd_get_mac_binary "art" 0)
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
@@ -61,11 +69,13 @@ case "$board" in
 		addr=$(mtd_get_mac_binary "Factory" 0x8000)
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
 		;;
+	cudy,tr3000-v1|\
 	cudy,re3000-v1)
 		addr=$(mtd_get_mac_binary bdinfo 0xde00)
 		[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
 		;;
+	cudy,m3000-v1|\
 	cudy,wr3000-v1)
 		addr=$(mtd_get_mac_binary bdinfo 0xde00)
 		# Originally, phy0 is phy1 mac with LA bit set. However, this would conflict
@@ -109,6 +119,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 3 > /sys${DEVPATH}/macaddress
 		;;
+	nokia,ea0326gmp)
+		addr=$(cat /sys/class/net/eth0/address)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+		;;
 	openembed,som7981)
 		[ "$PHYNBR" = "1" ] && cat /sys/class/net/eth0/address > /sys${DEVPATH}/macaddress
 		;;
@@ -117,6 +132,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		;;
+	ruijie,rg-x60-pro)
+		addr=$(mtd_get_mac_ascii product_info ethaddr)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+		;;
 	smartrg,sdg-8612|\
 	smartrg,sdg-8614|\
 	smartrg,sdg-8622|\
@@ -126,6 +146,13 @@ case "$board" in
 		[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
 		;;
+	smartrg,sdg-8733|\
+	smartrg,sdg-8634)
+		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+		[ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress
+		;;
 	tplink,tl-xdr4288|\
 	tplink,tl-xdr6086|\
 	tplink,tl-xdr6088)
diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label b/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label
index f8b6f155de..110e023b96 100644
--- a/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label
+++ b/target/linux/mediatek/filogic/base-files/lib/preinit/04_set_netdev_label
@@ -5,8 +5,8 @@ set_netdev_labels() {
 
 	for dir in /sys/class/net/*; do
 		[ -r "$dir/of_node/label" ] || continue
-		label="$(cat "$dir/of_node/label")"
-		netdev="$(basename $dir)"
+		read -r label < "$dir/of_node/label"
+		netdev="${dir##*/}"
 		[ "$netdev" = "$label" ] && continue
 		ip link set "$netdev" name "$label"
 	done
diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh
index 37b5be1334..2fe48b0ccf 100644
--- a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh
+++ b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh
@@ -22,7 +22,9 @@ preinit_set_mac_address() {
 		ip link set dev eth1 address "$(macaddr_add $addr 1)"
 		;;
 	smartrg,sdg-8612|\
-	smartrg,sdg-8614)
+	smartrg,sdg-8614|\
+	smartrg,sdg-8733|\
+	smartrg,sdg-8734)
 		addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
 		lan_addr=$(macaddr_add $addr 1)
 		ip link set dev wan address "$addr"
diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
index 6f69706d79..7e105b1089 100755
--- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
@@ -68,7 +68,9 @@ platform_do_upgrade() {
 	smartrg,sdg-8612|\
 	smartrg,sdg-8614|\
 	smartrg,sdg-8622|\
-	smartrg,sdg-8632)
+	smartrg,sdg-8632|\
+	smartrg,sdg-8733|\
+	smartrg,sdg-8734)
 		CI_KERNPART="kernel"
 		CI_ROOTPART="rootfs"
 		emmc_do_upgrade "$1"
@@ -83,10 +85,10 @@ platform_do_upgrade() {
 	bananapi,bpi-r3|\
 	bananapi,bpi-r3-mini|\
 	bananapi,bpi-r4|\
-	tplink,tl-xdr4288|\
-	tplink,tl-xdr6086|\
-	tplink,tl-xdr6088|\
-	xiaomi,redmi-router-ax6000-ubootmod)
+	bananapi,bpi-r4-poe|\
+	jdcloud,re-cp-03|\
+	mediatek,mt7988a-rfb|\
+	openwrt,one)
 		[ -e /dev/fit0 ] && fitblk /dev/fit0
 		[ -e /dev/fitrw ] && fitblk /dev/fitrw
 		bootdev="$(fitblk_get_bootdev)"
@@ -140,14 +142,20 @@ platform_do_upgrade() {
 		CI_KERNPART="fit"
 		nand_do_upgrade "$1"
 		;;
-	jdcloud,re-cp-03)
-		CI_KERNPART="production"
-		emmc_do_upgrade "$1"
-		;;
 	mercusys,mr90x-v1)
 		CI_UBIPART="ubi0"
 		nand_do_upgrade "$1"
 		;;
+	nokia,ea0326gmp|\
+	tplink,tl-xdr4288|\
+	tplink,tl-xdr6086|\
+	tplink,tl-xdr6088|\
+	xiaomi,redmi-router-ax6000-ubootmod)
+		[ -e /dev/fit0 ] && fitblk /dev/fit0
+		[ -e /dev/fitrw ] && fitblk /dev/fitrw
+		CI_KERNPART="fit"
+		nand_do_upgrade "$1"
+		;;
 	ubnt,unifi-6-plus)
 		CI_KERNPART="kernel0"
 		EMMC_ROOT_DEV="$(cmdline_get_var root)"
@@ -199,6 +207,7 @@ platform_check_image() {
 	case "$board" in
 	bananapi,bpi-r3|\
 	bananapi,bpi-r4|\
+	bananapi,bpi-r4-poe|\
 	cmcc,rax3000m)
 		[ "$magic" != "d00dfeed" ] && {
 			echo "Invalid image type."
@@ -226,7 +235,8 @@ platform_copy_config() {
 		;;
 	bananapi,bpi-r3|\
 	bananapi,bpi-r3-mini|\
-	bananapi,bpi-r4)
+	bananapi,bpi-r4|\
+	bananapi,bpi-r4-poe)
 		case "$(fitblk_get_bootdev)" in
 		mmcblk*)
 			emmc_copy_config
@@ -239,6 +249,12 @@ platform_copy_config() {
 	glinet,gl-x3000|\
 	glinet,gl-xe3000|\
 	jdcloud,re-cp-03|\
+	smartrg,sdg-8612|\
+	smartrg,sdg-8614|\
+	smartrg,sdg-8622|\
+	smartrg,sdg-8632|\
+	smartrg,sdg-8733|\
+	smartrg,sdg-8734|\
 	ubnt,unifi-6-plus)
 		emmc_copy_config
 		;;
diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1
deleted file mode 100644
index 663bb054a2..0000000000
--- a/target/linux/mediatek/filogic/config-6.1
+++ /dev/null
@@ -1,486 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AIROHA_EN8801SC_PHY=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_NVMEM=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2712 is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7981=y
-CONFIG_COMMON_CLK_MT7981_ETHSYS=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_COMMON_CLK_MT7988=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8186 is not set
-# CONFIG_COMMON_CLK_MT8195 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA3=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_SMARTRG_LED=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_2P5G_PHY=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_GE_SOC_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_NVMEM=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-CONFIG_MTK_LVTS_THERMAL=y
-CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-CONFIG_NET_DSA_MT7530_MMIO=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PCS_MTK_USXGMII=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-CONFIG_PHY_MTK_XFI_TPHY=y
-CONFIG_PHY_MTK_XSPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6795 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-# CONFIG_PINCTRL_MT7622 is not set
-CONFIG_PINCTRL_MT7981=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT7988=y
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-# CONFIG_PINCTRL_MT8186 is not set
-# CONFIG_PINCTRL_MT8188 is not set
-# CONFIG_PINCTRL_MT8516 is not set
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POLYNOMIAL=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_REGULATOR_RT5190A=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPI_MTK_SNFI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UIMAGE_FIT_BLK=y
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/filogic/config-6.6 b/target/linux/mediatek/filogic/config-6.6
index 110f6e7550..5f4e42ac0f 100644
--- a/target/linux/mediatek/filogic/config-6.6
+++ b/target/linux/mediatek/filogic/config-6.6
@@ -228,6 +228,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y
 CONFIG_IRQ_WORK=y
 CONFIG_JBD2=y
 CONFIG_JUMP_LABEL=y
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_SMARTRG_LED=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
diff --git a/target/linux/mediatek/filogic/target.mk b/target/linux/mediatek/filogic/target.mk
index c87552f196..d1637e06af 100644
--- a/target/linux/mediatek/filogic/target.mk
+++ b/target/linux/mediatek/filogic/target.mk
@@ -2,7 +2,7 @@ ARCH:=aarch64
 SUBTARGET:=filogic
 BOARDNAME:=Filogic 8x0 (MT798x)
 CPU_TYPE:=cortex-a53
-DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel kmod-mt7915e wpad-basic-mbedtls uboot-envtools
+DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel wpad-basic-mbedtls uboot-envtools
 KERNELNAME:=Image dtbs
 
 define Target/Description
diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
index f99a73ac74..884ededd32 100644
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -110,7 +110,7 @@ define Device/acelink_ew-7886cax
   DEVICE_MODEL := EW-7886CAX
   DEVICE_DTS := mt7986a-acelink-ew-7886cax
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -128,7 +128,7 @@ define Device/acer_predator-w6
   DEVICE_DTS := mt7986a-acer-predator-w6
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x47000000
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware kmod-mt7916-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
   IMAGES := sysupgrade.bin
   KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
   KERNEL_INITRAMFS := kernel-bin | lzma | \
@@ -140,8 +140,7 @@ TARGET_DEVICES += acer_predator-w6
 define Device/adtran_smartrg
   DEVICE_VENDOR := Adtran
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan \
-		     kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 
@@ -149,6 +148,7 @@ define Device/smartrg_sdg-8612
 $(call Device/adtran_smartrg)
   DEVICE_MODEL := SDG-8612
   DEVICE_DTS := mt7986a-smartrg-SDG-8612
+  DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
 endef
 TARGET_DEVICES += smartrg_sdg-8612
 
@@ -156,6 +156,7 @@ define Device/smartrg_sdg-8614
 $(call Device/adtran_smartrg)
   DEVICE_MODEL := SDG-8614
   DEVICE_DTS := mt7986a-smartrg-SDG-8614
+  DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
 endef
 TARGET_DEVICES += smartrg_sdg-8614
 
@@ -163,7 +164,7 @@ define Device/smartrg_sdg-8622
 $(call Device/adtran_smartrg)
   DEVICE_MODEL := SDG-8622
   DEVICE_DTS := mt7986a-smartrg-SDG-8622
-  DEVICE_PACKAGES += kmod-mt7915-firmware
+  DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware
 endef
 TARGET_DEVICES += smartrg_sdg-8622
 
@@ -171,16 +172,32 @@ define Device/smartrg_sdg-8632
 $(call Device/adtran_smartrg)
   DEVICE_MODEL := SDG-8632
   DEVICE_DTS := mt7986a-smartrg-SDG-8632
-  DEVICE_PACKAGES += kmod-mt7915-firmware
+  DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware
 endef
 TARGET_DEVICES += smartrg_sdg-8632
 
+define Device/smartrg_sdg-8733
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8733
+  DEVICE_DTS := mt7988a-smartrg-SDG-8733
+  DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-usb3
+endef
+TARGET_DEVICES += smartrg_sdg-8733
+
+define Device/smartrg_sdg-8734
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8734
+  DEVICE_DTS := mt7988a-smartrg-SDG-8734
+  DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-sfp kmod-usb3
+endef
+TARGET_DEVICES += smartrg_sdg-8734
+
 define Device/asus_rt-ax59u
   DEVICE_VENDOR := ASUS
   DEVICE_MODEL := RT-AX59U
   DEVICE_DTS := mt7986a-asus-rt-ax59u
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 TARGET_DEVICES += asus_rt-ax59u
@@ -191,7 +208,7 @@ define Device/asus_tuf-ax4200
   DEVICE_DTS := mt7986a-asus-tuf-ax4200
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x47000000
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   IMAGES := sysupgrade.bin
   KERNEL := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
@@ -207,7 +224,7 @@ define Device/asus_tuf-ax6000
   DEVICE_DTS := mt7986a-asus-tuf-ax6000
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x47000000
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   IMAGES := sysupgrade.bin
   KERNEL := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
@@ -227,7 +244,7 @@ define Device/bananapi_bpi-r3
 		       mt7986a-bananapi-bpi-r3-respeaker-2mics
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 \
+  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7915e kmod-mt7986-firmware kmod-sfp kmod-usb3 \
 		     e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
   IMAGES := sysupgrade.itb
   KERNEL_LOADADDR := 0x44000000
@@ -280,7 +297,7 @@ define Device/bananapi_bpi-r3-mini
   DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3-mini
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7986-firmware kmod-phy-airoha-en8811h \
+  DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7915e kmod-mt7986-firmware kmod-phy-airoha-en8811h \
 		     kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
@@ -318,11 +335,8 @@ endif
 endef
 TARGET_DEVICES += bananapi_bpi-r3-mini
 
-define Device/bananapi_bpi-r4
+define Device/bananapi_bpi-r4-common
   DEVICE_VENDOR := Bananapi
-  DEVICE_MODEL := BPi-R4
-  DEVICE_DTS := mt7988a-bananapi-bpi-r4
-  DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTS_LOADADDR := 0x45f00000
   DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a
@@ -337,19 +351,19 @@ define Device/bananapi_bpi-r4
 	       sdcard.img.gz \
 	       snand-preloader.bin snand-bl31-uboot.fip
   ARTIFACT/emmc-preloader.bin	:= mt7988-bl2 emmc-comb
-  ARTIFACT/emmc-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-emmc
+  ARTIFACT/emmc-bl31-uboot.fip	:= mt7988-bl31-uboot $$(DEVICE_NAME)-emmc
   ARTIFACT/snand-preloader.bin	:= mt7988-bl2 spim-nand-ubi-comb
-  ARTIFACT/snand-bl31-uboot.fip	:= mt7988-bl31-uboot bananapi_bpi-r4-snand
+  ARTIFACT/snand-bl31-uboot.fip	:= mt7988-bl31-uboot $$(DEVICE_NAME)-snand
   ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
 				   pad-to 17k | mt7988-bl2 sdmmc-comb |\
-				   pad-to 6656k | mt7988-bl31-uboot bananapi_bpi-r4-sdmmc |\
+				   pad-to 6656k | mt7988-bl31-uboot $$(DEVICE_NAME)-sdmmc |\
 				$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
 				   pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
 				) \
 				   pad-to 44M | mt7988-bl2 spim-nand-ubi-comb |\
-				   pad-to 45M | mt7988-bl31-uboot bananapi_bpi-r4-snand |\
+				   pad-to 45M | mt7988-bl31-uboot $$(DEVICE_NAME)-snand |\
 				   pad-to 51M | mt7988-bl2 emmc-comb |\
-				   pad-to 52M | mt7988-bl31-uboot bananapi_bpi-r4-emmc |\
+				   pad-to 52M | mt7988-bl31-uboot $$(DEVICE_NAME)-emmc |\
 				   pad-to 56M | mt798x-gpt emmc |\
 				$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
 				   pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
@@ -361,15 +375,31 @@ define Device/bananapi_bpi-r4
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
 endef
+
+define Device/bananapi_bpi-r4
+  DEVICE_MODEL := BPi-R4
+  DEVICE_DTS := mt7988a-bananapi-bpi-r4
+  DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
+  $(call Device/bananapi_bpi-r4-common)
+endef
 TARGET_DEVICES += bananapi_bpi-r4
 
+define Device/bananapi_bpi-r4-poe
+  DEVICE_MODEL := BPi-R4 2.5GE
+  DEVICE_DTS := mt7988a-bananapi-bpi-r4-poe
+  DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4-poe
+  $(call Device/bananapi_bpi-r4-common)
+  DEVICE_PACKAGES += mt7988-2p5g-phy-firmware
+endef
+TARGET_DEVICES += bananapi_bpi-r4-poe
+
 define Device/cetron_ct3003
   DEVICE_VENDOR := Cetron
   DEVICE_MODEL := CT3003
   DEVICE_DTS := mt7981b-cetron-ct3003
   DEVICE_DTS_DIR := ../dts
   SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -388,7 +418,7 @@ define Device/cmcc_rax3000m
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \
 	e2fsprogs f2fsck mkf2fs
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
@@ -420,7 +450,7 @@ define Device/comfast_cf-e393ax
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   KERNEL_LOADADDR := 0x44000000
   KERNEL = kernel-bin | lzma | \
        fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
@@ -449,10 +479,32 @@ define Device/confiabits_mt7981
   IMAGE_SIZE := 65536k
   KERNEL_IN_UBI := 1
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
-  DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 endef
 TARGET_DEVICES += confiabits_mt7981
 
+define Device/cudy_m3000-v1
+  DEVICE_VENDOR := Cudy
+  DEVICE_MODEL := M3000
+  DEVICE_VARIANT := v1
+  DEVICE_DTS := mt7981b-cudy-m3000-v1
+  DEVICE_DTS_DIR := ../dts
+  SUPPORTED_DEVICES += R37
+  DEVICE_DTS_LOADADDR := 0x44000000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_IN_UBI := 1
+  KERNEL := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGES := sysupgrade.bin
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += cudy_m3000-v1
+
 define Device/cudy_re3000-v1
   DEVICE_VENDOR := Cudy
   DEVICE_MODEL := RE3000
@@ -468,10 +520,27 @@ define Device/cudy_re3000-v1
   KERNEL_INITRAMFS := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 endef
 TARGET_DEVICES += cudy_re3000-v1
 
+define Device/cudy_tr3000-v1
+  DEVICE_VENDOR := Cudy
+  DEVICE_MODEL := TR3000
+  DEVICE_VARIANT := v1
+  DEVICE_DTS := mt7981b-cudy-tr3000-v1
+  DEVICE_DTS_DIR := ../dts
+  SUPPORTED_DEVICES += R47
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_IN_UBI := 1
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += cudy_tr3000-v1
+
 define Device/cudy_wr3000-v1
   DEVICE_VENDOR := Cudy
   DEVICE_MODEL := WR3000
@@ -487,7 +556,7 @@ define Device/cudy_wr3000-v1
   KERNEL_INITRAMFS := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 endef
 TARGET_DEVICES += cudy_wr3000-v1
 
@@ -497,7 +566,7 @@ define Device/dlink_aquila-pro-ai-m30-a1
   DEVICE_VARIANT := A1
   DEVICE_DTS := mt7981b-dlink-aquila-pro-ai-m30-a1
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-leds-gca230718 kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-leds-gca230718 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   KERNEL_IN_UBI := 1
   IMAGES += recovery.bin
   IMAGE_SIZE := 51200k
@@ -520,7 +589,7 @@ define Device/edgecore_eap111
   IMAGES := sysupgrade.bin factory.bin
   IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 endef
 TARGET_DEVICES += edgecore_eap111
 
@@ -530,7 +599,7 @@ define Device/glinet_gl-mt2500
   DEVICE_DTS := mt7981b-glinet-gl-mt2500
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTS_LOADADDR := 0x47000000
-  DEVICE_PACKAGES := -kmod-mt7915e -wpad-basic-mbedtls e2fsprogs f2fsck mkf2fs kmod-usb3
+  DEVICE_PACKAGES := -wpad-basic-mbedtls e2fsprogs f2fsck mkf2fs kmod-usb3
   SUPPORTED_DEVICES += glinet,mt2500-emmc
   IMAGES := sysupgrade.bin
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
@@ -543,7 +612,7 @@ define Device/glinet_gl-mt3000
   DEVICE_DTS := mt7981b-glinet-gl-mt3000
   DEVICE_DTS_DIR := ../dts
   SUPPORTED_DEVICES += glinet,mt3000-snand
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -558,7 +627,7 @@ define Device/glinet_gl-mt6000
   DEVICE_MODEL := GL-MT6000
   DEVICE_DTS := mt7986a-glinet-gl-mt6000
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   IMAGES += factory.bin
   IMAGE/factory.bin := append-kernel | pad-to 32M | append-rootfs
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
@@ -571,7 +640,7 @@ TARGET_DEVICES += glinet_gl-mt6000
 define Device/glinet_gl-x3000-xe3000-common
   DEVICE_VENDOR := GL.iNet
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware mkf2fs \
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware mkf2fs \
     kmod-fs-f2fs kmod-hwmon-pwmfan kmod-usb3 kmod-usb-serial-option \
     kmod-usb-storage kmod-usb-net-qmi-wwan uqmi
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
@@ -611,7 +680,7 @@ define Device/h3c_magic-nx30-pro
         fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | \
         fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   ARTIFACTS := preloader.bin bl31-uboot.fip
   ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
   ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot h3c_magic-nx30-pro
@@ -635,7 +704,7 @@ define Device/jcg_q30-pro
         fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | \
         fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   ARTIFACTS := preloader.bin bl31-uboot.fip
   ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
   ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot jcg_q30-pro
@@ -649,7 +718,7 @@ define Device/jdcloud_re-cp-03
   DEVICE_DTS_DIR := ../dts
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware \
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware \
 	e2fsprogs f2fsck mkf2fs
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
@@ -679,7 +748,7 @@ define Device/mediatek_mt7981-rfb
   DEVICE_DTS_DIR := $(DTS_DIR)/
   DEVICE_DTC_FLAGS := --pad 4096
   DEVICE_DTS_LOADADDR := 0x43f00000
-  DEVICE_PACKAGES := kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
   KERNEL_LOADADDR := 0x44000000
   KERNEL := kernel-bin | gzip
   KERNEL_INITRAMFS := kernel-bin | lzma | \
@@ -728,7 +797,7 @@ define Device/mediatek_mt7986a-rfb-nand
   DEVICE_MODEL := MT7986 rfba AP (NAND)
   DEVICE_DTS := mt7986a-rfb-spim-nand
   DEVICE_DTS_DIR := $(DTS_DIR)/
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
@@ -750,7 +819,7 @@ define Device/mediatek_mt7986b-rfb
   DEVICE_MODEL := MTK7986 rfbb AP
   DEVICE_DTS := mt7986b-rfb
   DEVICE_DTS_DIR := $(DTS_DIR)/
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   SUPPORTED_DEVICES := mediatek,mt7986b-rfb
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
@@ -772,6 +841,7 @@ define Device/mediatek_mt7988a-rfb
 	mt7988a-rfb-sd \
 	mt7988a-rfb-snfi-nand \
 	mt7988a-rfb-spim-nand \
+	mt7988a-rfb-spim-nand-factory \
 	mt7988a-rfb-spim-nor \
 	mt7988a-rfb-eth1-aqr \
 	mt7988a-rfb-eth1-i2p5g-phy \
@@ -803,7 +873,7 @@ define Device/mediatek_mt7988a-rfb
   ARTIFACT/emmc-bl31-uboot.fip	:= mt7988-bl31-uboot rfb-emmc
   ARTIFACT/nor-preloader.bin	:= mt7988-bl2 nor-comb
   ARTIFACT/nor-bl31-uboot.fip	:= mt7988-bl31-uboot rfb-nor
-  ARTIFACT/snand-preloader.bin	:= mt7988-bl2 spim-nand-comb
+  ARTIFACT/snand-preloader.bin	:= mt7988-bl2 spim-nand-ubi-comb
   ARTIFACT/snand-bl31-uboot.fip	:= mt7988-bl31-uboot rfb-snand
   ARTIFACT/sdcard.img.gz	:= mt798x-gpt sdmmc |\
 				   pad-to 17k | mt7988-bl2 sdmmc-comb |\
@@ -830,7 +900,7 @@ define Device/mercusys_mr90x-v1
   DEVICE_MODEL := MR90X v1
   DEVICE_DTS := mt7986b-mercusys-mr90x-v1
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -856,7 +926,7 @@ define Device/netcore_n60
         fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | \
         fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   ARTIFACTS := preloader.bin bl31-uboot.fip
   ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
   ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot netcore_n60
@@ -870,7 +940,7 @@ define Device/netgear_wax220
   DEVICE_DTS_DIR := ../dts
   NETGEAR_ENC_MODEL := WAX220
   NETGEAR_ENC_REGION := US
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   IMAGE_SIZE := 32768k
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
@@ -881,12 +951,36 @@ define Device/netgear_wax220
 endef
 TARGET_DEVICES += netgear_wax220
 
+define Device/nokia_ea0326gmp
+  DEVICE_VENDOR := Nokia
+  DEVICE_MODEL := EA0326GMP
+  DEVICE_DTS := mt7981b-nokia-ea0326gmp
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  UBOOTENV_IN_UBI := 1
+  IMAGES := sysupgrade.itb
+  KERNEL_INITRAMFS_SUFFIX := -recovery.itb
+  KERNEL := kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+        fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  IMAGE/sysupgrade.itb := append-kernel | \
+        fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
+  ARTIFACTS := preloader.bin bl31-uboot.fip
+  ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
+  ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot nokia_ea0326gmp
+endef
+TARGET_DEVICES += nokia_ea0326gmp
+
 define Device/openembed_som7981
   DEVICE_VENDOR := OpenEmbed
   DEVICE_MODEL := SOM7981
   DEVICE_DTS := mt7981b-openembed-som7981
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -898,6 +992,54 @@ define Device/openembed_som7981
 endef
 TARGET_DEVICES += openembed_som7981
 
+define Build/append-openwrt-one-eeprom
+        dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
+endef
+
+define Device/openwrt_one
+  DEVICE_VENDOR := OpenWrt
+  DEVICE_MODEL := One
+  DEVICE_DTS := mt7981b-openwrt-one
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTC_FLAGS := --pad 4096
+  DEVICE_DTS_LOADADDR := 0x43f00000
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-rtc-pcf8563 kmod-usb3 kmod-nvme kmod-phy-airoha-en8811h
+  KERNEL_LOADADDR := 0x44000000
+  KERNEL := kernel-bin | gzip
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+  KERNEL_INITRAMFS_SUFFIX := .itb
+  KERNEL_IN_UBI := 1
+  UBOOTENV_IN_UBI := 1
+  IMAGES := sysupgrade.itb
+  IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+  ARTIFACTS := \
+	nor-preloader.bin nor-bl31-uboot.fip \
+	snand-preloader.bin snand-bl31-uboot.fip \
+	factory.ubi snand-factory.bin nor-factory.bin
+  ARTIFACT/nor-preloader.bin		:= mt7981-bl2 nor-ddr4
+  ARTIFACT/nor-bl31-uboot.fip		:= mt7981-bl31-uboot openwrt_one-nor
+  ARTIFACT/snand-preloader.bin		:= mt7981-bl2 spim-nand-ubi-ddr4
+  ARTIFACT/snand-bl31-uboot.fip		:= mt7981-bl31-uboot openwrt_one-snand
+  ARTIFACT/factory.ubi			:= ubinize-image fit squashfs-sysupgrade.itb
+  ARTIFACT/snand-factory.bin		:= mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \
+					   mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \
+					   mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \
+					   mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 1024k | \
+					   ubinize-image fit squashfs-sysupgrade.itb
+  ARTIFACT/nor-factory.bin		:= mt7981-bl2 nor-ddr4 | pad-to 256k | \
+					   append-openwrt-one-eeprom | pad-to 1024k | \
+					   mt7981-bl31-uboot openwrt_one-nor | pad-to 512k | \
+					   append-image-stage initramfs.itb
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7981_openwrt_one-snand-u-boot.fip recovery=:$(KDIR)/tmp/openwrt-mediatek-filogic-openwrt_one-initramfs.itb \
+		   $(if $(wildcard $(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb), calibration=:$(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb)
+endef
+TARGET_DEVICES += openwrt_one
+
 define Device/qihoo_360t7
   DEVICE_VENDOR := Qihoo
   DEVICE_MODEL := 360T7
@@ -915,7 +1057,7 @@ define Device/qihoo_360t7
         fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | \
         fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   ARTIFACTS := preloader.bin bl31-uboot.fip
   ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
   ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot qihoo_360t7
@@ -927,12 +1069,22 @@ define Device/routerich_ax3000
   DEVICE_MODEL := AX3000
   DEVICE_DTS := mt7981b-routerich-ax3000
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
   SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
 endef
 TARGET_DEVICES += routerich_ax3000
 
+define Device/ruijie_rg-x60-pro
+  DEVICE_VENDOR := Ruijie
+  DEVICE_MODEL := RG-X60 Pro
+  DEVICE_DTS := mt7986a-ruijie-rg-x60-pro
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += ruijie_rg-x60-pro
+
 define Device/tplink_tl-xdr-common
   DEVICE_VENDOR := TP-Link
   DEVICE_DTS_DIR := ../dts
@@ -948,7 +1100,7 @@ define Device/tplink_tl-xdr-common
         fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.itb := append-kernel | \
         fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata
-  DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   ARTIFACTS := preloader.bin bl31-uboot.fip
   ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
 endef
@@ -982,7 +1134,7 @@ define Device/ubnt_unifi-6-plus
   DEVICE_MODEL := UniFi 6 Plus
   DEVICE_DTS := mt7981a-ubnt-unifi-6-plus
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 TARGET_DEVICES += ubnt_unifi-6-plus
@@ -991,7 +1143,7 @@ define Device/unielec_u7981-01
   DEVICE_VENDOR := Unielec
   DEVICE_MODEL := U7981-01
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs fdisk partx-utils
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs fdisk partx-utils
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 
@@ -1017,7 +1169,7 @@ define Device/xiaomi_mi-router-ax3000t
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
   ARTIFACTS := initramfs-factory.ubi
   ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
@@ -1034,7 +1186,7 @@ define Device/xiaomi_mi-router-ax3000t-ubootmod
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   KERNEL_IN_UBI := 1
   UBOOTENV_IN_UBI := 1
   IMAGES := sysupgrade.itb
@@ -1062,7 +1214,7 @@ define Device/xiaomi_mi-router-wr30u-stock
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
   ARTIFACTS := initramfs-factory.ubi
   ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
@@ -1079,7 +1231,7 @@ define Device/xiaomi_mi-router-wr30u-ubootmod
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   KERNEL_IN_UBI := 1
   UBOOTENV_IN_UBI := 1
   IMAGES := sysupgrade.itb
@@ -1104,7 +1256,7 @@ define Device/xiaomi_redmi-router-ax6000-stock
   DEVICE_MODEL := Redmi Router AX6000 (stock layout)
   DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-stock
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -1121,7 +1273,7 @@ define Device/xiaomi_redmi-router-ax6000-ubootmod
   DEVICE_MODEL := Redmi Router AX6000 (OpenWrt U-Boot layout)
   DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-ubootmod
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   IMAGES := sysupgrade.itb
   UBINIZE_OPTS := -E 5
@@ -1158,7 +1310,7 @@ define Device/yuncore_ax835
   KERNEL_INITRAMFS := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
 endef
 TARGET_DEVICES += yuncore_ax835
 
@@ -1168,7 +1320,7 @@ define Device/zbtlink_zbt-z8102ax
   DEVICE_MODEL := ZBT-Z8102AX
   DEVICE_DTS := mt7981b-zbtlink-zbt-z8102ax
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option
   KERNEL_IN_UBI := 1
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
@@ -1185,7 +1337,7 @@ define Device/zbtlink_zbt-z8103ax
   DEVICE_MODEL := ZBT-Z8103AX
   DEVICE_DTS := mt7981b-zbtlink-zbt-z8103ax
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
   KERNEL_IN_UBI := 1
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
@@ -1203,7 +1355,7 @@ define Device/zyxel_ex5601-t0-stock
   DEVICE_VARIANT := (stock layout)
   DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
   SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256k
@@ -1226,7 +1378,7 @@ define Device/zyxel_ex5601-t0-ubootmod
   DEVICE_VARIANT := (OpenWrt U-Boot layout)
   DEVICE_DTS := mt7986a-zyxel-ex5601-t0-ubootmod
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
   KERNEL_INITRAMFS_SUFFIX := -recovery.itb
   IMAGES := sysupgrade.itb
   UBINIZE_OPTS := -E 5
@@ -1254,7 +1406,7 @@ define Device/zyxel_ex5700-telenor
   DEVICE_MODEL := EX5700 (Telenor)
   DEVICE_DTS := mt7986a-zyxel-ex5700-telenor
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7916-firmware kmod-ubootenv-nvram kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+  DEVICE_PACKAGES := kmod-ubootenv-nvram kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
   PAGESIZE := 2048
@@ -1268,7 +1420,7 @@ define Device/zyxel_nwa50ax-pro
   DEVICE_MODEL := NWA50AX Pro
   DEVICE_DTS := mt7981b-zyxel-nwa50ax-pro
   DEVICE_DTS_DIR := ../dts
-  DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig
   DEVICE_DTS_LOADADDR := 0x44000000
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 128k
diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk
index 441e29a1dc..f91720479a 100644
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@@ -8,27 +8,6 @@ define Image/Prepare
 	echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark
 endef
 
-define Build/buffalo-trx
-	$(eval magic=$(word 1,$(1)))
-	$(eval kern_bin=$(if $(1),$(IMAGE_KERNEL),$@))
-	$(eval rtfs_bin=$(word 2,$(1)))
-	$(eval apnd_bin=$(word 3,$(1)))
-	$(eval kern_size=$(if $(KERNEL_SIZE),$(KERNEL_SIZE),0x400000))
-
-	$(if $(rtfs_bin),touch $(rtfs_bin))
-	$(STAGING_DIR_HOST)/bin/otrx create $@.new \
-		$(if $(magic),-M $(magic),) \
-		-f $(kern_bin) \
-		$(if $(rtfs_bin),\
-			-a 0x20000 \
-			-b $$(( $(call exp_units,$(kern_size)) )) \
-			-f $(rtfs_bin),) \
-		$(if $(apnd_bin),\
-			-A $(apnd_bin) \
-			-a 0x20000)
-	mv $@.new $@
-endef
-
 define Build/bl2
 	cat $(STAGING_DIR_IMAGE)/mt7622-$1-bl2.img >> $@
 endef
diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1
deleted file mode 100644
index 68bdd87074..0000000000
--- a/target/linux/mediatek/mt7622/config-6.1
+++ /dev/null
@@ -1,479 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-# CONFIG_AIROHA_EN8801SC_PHY is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8186 is not set
-# CONFIG_COMMON_CLK_MT8195 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MEDIATEK_2P5G_PHY is not set
-CONFIG_MEDIATEK_GE_PHY=y
-# CONFIG_MEDIATEK_GE_SOC_PHY is not set
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_NVMEM=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-# CONFIG_MTK_LVTS_THERMAL is not set
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6795 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT7981 is not set
-# CONFIG_PINCTRL_MT7986 is not set
-# CONFIG_PINCTRL_MT7988 is not set
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-# CONFIG_PINCTRL_MT8186 is not set
-# CONFIG_PINCTRL_MT8188 is not set
-# CONFIG_PINCTRL_MT8516 is not set
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTL8367S_GSW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UIMAGE_FIT_BLK=y
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1
deleted file mode 100644
index 1407188e2e..0000000000
--- a/target/linux/mediatek/mt7623/config-6.1
+++ /dev/null
@@ -1,615 +0,0 @@
-# CONFIG_AIO is not set
-# CONFIG_AIROHA_EN8801SC_PHY is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_LED=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT7629 is not set
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_DMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_LIMA=y
-CONFIG_DRM_LVDS_CODEC=y
-CONFIG_DRM_MEDIATEK=y
-# CONFIG_DRM_MEDIATEK_DP is not set
-CONFIG_DRM_MEDIATEK_HDMI=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_NOMODESET=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_ELF_CORE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=1024
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-# CONFIG_KEYBOARD_MT6779 is not set
-CONFIG_KEYBOARD_MTK_PMIC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_MT6323=y
-# CONFIG_LEDS_QCOM_LPG is not set
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT7629 is not set
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_ADSP_MBOX is not set
-CONFIG_MTK_CMDQ=y
-CONFIG_MTK_CMDQ_MBOX=y
-CONFIG_MTK_CQDMA=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_IOMMU=y
-CONFIG_MTK_IOMMU_V1=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_SMI=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-# CONFIG_MTK_LVTS_THERMAL is not set
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MTK_EFUSE=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MTK_DP is not set
-CONFIG_PHY_MTK_HDMI=y
-CONFIG_PHY_MTK_MIPI_DSI=y
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-# CONFIG_PINCTRL_MT6397 is not set
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MT6323 is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6331 is not set
-# CONFIG_REGULATOR_MT6332 is not set
-# CONFIG_REGULATOR_MT6358 is not set
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-# CONFIG_SPMI_MTK_PMIF is not set
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UIMAGE_FIT_BLK=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-# CONFIG_USB_G_MULTI_RNDIS is not set
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_MEDIATEK=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1
deleted file mode 100644
index 5a15286c46..0000000000
--- a/target/linux/mediatek/mt7629/config-6.1
+++ /dev/null
@@ -1,353 +0,0 @@
-# CONFIG_AIROHA_EN8801SC_PHY is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2701 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7629=y
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
-CONFIG_DIMLIB=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_WARN=1024
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LIBFDT=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-# CONFIG_MACH_MT7623 is not set
-CONFIG_MACH_MT7629=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MTK_EFUSE is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch
deleted file mode 100644
index 17c5c6098a..0000000000
--- a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
-From: Andrew Davis <afd@ti.com>
-Date: Mon, 24 Oct 2022 12:34:28 -0500
-Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
- files
-
-Currently DTB Overlays (.dtbo) are build from source files with the same
-extension (.dts) as the base DTs (.dtb). This may become confusing and
-even lead to wrong results. For example, a composite DTB (created from a
-base DTB and a set of overlays) might have the same name as one of the
-overlays that create it.
-
-Different files should be generated from differently named sources.
- .dtb  <-> .dts
- .dtbo <-> .dtso
-
-We do not remove the ability to compile DTBO files from .dts files here,
-only add a new rule allowing the .dtso file name. The current .dts named
-overlays can be renamed with time. After all have been renamed we can
-remove the other rule.
-
-Signed-off-by: Andrew Davis <afd@ti.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Frank Rowand <frowand.list@gmail.com>
-Tested-by: Frank Rowand <frowand.list@gmail.com>
-Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com
-Signed-off-by: Rob Herring <robh@kernel.org>
----
- scripts/Makefile.lib | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/scripts/Makefile.lib
-+++ b/scripts/Makefile.lib
-@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
- $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
- 	$(call if_changed_dep,dtc)
- 
-+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
-+	$(call if_changed_dep,dtc)
-+
- dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
- 
- # Bzip2
diff --git a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch b/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch
deleted file mode 100644
index e6c6eb6166..0000000000
--- a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 5 Nov 2022 23:36:16 +0100
-Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
- Wireless Ethernet Dispatch
-
-Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
-Dispatch to offload traffic received by the wlan interface to lan/wan
-one.
-
-Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
-Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
- 1 file changed, 65 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -76,6 +76,47 @@
- 			no-map;
- 			reg = <0 0x4fc00000 0 0x00100000>;
- 		};
-+
-+		wo_emi0: wo-emi@4fd00000 {
-+			reg = <0 0x4fd00000 0 0x40000>;
-+			no-map;
-+		};
-+
-+		wo_emi1: wo-emi@4fd40000 {
-+			reg = <0 0x4fd40000 0 0x40000>;
-+			no-map;
-+		};
-+
-+		wo_ilm0: wo-ilm@151e0000 {
-+			reg = <0 0x151e0000 0 0x8000>;
-+			no-map;
-+		};
-+
-+		wo_ilm1: wo-ilm@151f0000 {
-+			reg = <0 0x151f0000 0 0x8000>;
-+			no-map;
-+		};
-+
-+		wo_data: wo-data@4fd80000 {
-+			reg = <0 0x4fd80000 0 0x240000>;
-+			no-map;
-+		};
-+
-+		wo_dlm0: wo-dlm@151e8000 {
-+			reg = <0 0x151e8000 0 0x2000>;
-+			no-map;
-+		};
-+
-+		wo_dlm1: wo-dlm@151f8000 {
-+			reg = <0 0x151f8000 0 0x2000>;
-+			no-map;
-+		};
-+
-+		wo_boot: wo-boot@15194000 {
-+			reg = <0 0x15194000 0 0x1000>;
-+			no-map;
-+		};
-+
- 	};
- 
- 	timer {
-@@ -240,6 +281,11 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-+			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-+					<&wo_data>, <&wo_boot>;
-+			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-+					      "wo-data", "wo-boot";
-+			mediatek,wo-ccif = <&wo_ccif0>;
- 		};
- 
- 		wed1: wed@15011000 {
-@@ -248,6 +294,25 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-+			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-+					<&wo_data>, <&wo_boot>;
-+			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-+					      "wo-data", "wo-boot";
-+			mediatek,wo-ccif = <&wo_ccif1>;
-+		};
-+
-+		wo_ccif0: syscon@151a5000 {
-+			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-+			reg = <0 0x151a5000 0 0x1000>;
-+			interrupt-parent = <&gic>;
-+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		wo_ccif1: syscon@151ad000 {
-+			compatible = "mediatek,mt7986-wo-ccif", "syscon";
-+			reg = <0 0x151ad000 0 0x1000>;
-+			interrupt-parent = <&gic>;
-+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
- 		eth: ethernet@15100000 {
diff --git a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch b/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch
deleted file mode 100644
index b5091687a3..0000000000
--- a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:50:24 +0100
-Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
-
-This arrange device tree nodes in alphabetical order.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
- 2 files changed, 58 insertions(+), 58 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -54,6 +54,53 @@
- 	};
- };
- 
-+&pio {
-+	uart1_pins: uart1-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart1";
-+		};
-+	};
-+
-+	uart2_pins: uart2-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart2";
-+		};
-+	};
-+
-+	wf_2g_5g_pins: wf-2g-5g-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_2g", "wf_5g";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+
-+	wf_dbdc_pins: wf-dbdc-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_dbdc";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+};
-+
- &switch {
- 	ports {
- 		#address-cells = <1>;
-@@ -121,50 +168,3 @@
- 	pinctrl-0 = <&wf_2g_5g_pins>;
- 	pinctrl-1 = <&wf_dbdc_pins>;
- };
--
--&pio {
--	uart1_pins: uart1-pins {
--		mux {
--			function = "uart";
--			groups = "uart1";
--		};
--	};
--
--	uart2_pins: uart2-pins {
--		mux {
--			function = "uart";
--			groups = "uart2";
--		};
--	};
--
--	wf_2g_5g_pins: wf-2g-5g-pins {
--		mux {
--			function = "wifi";
--			groups = "wf_2g", "wf_5g";
--		};
--		conf {
--			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
--			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
--			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
--			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
--			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
--			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
--			       "WF1_TOP_CLK", "WF1_TOP_DATA";
--			drive-strength = <4>;
--		};
--	};
--
--	wf_dbdc_pins: wf-dbdc-pins {
--		mux {
--			function = "wifi";
--			groups = "wf_dbdc";
--		};
--		conf {
--			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
--			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
--			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
--			       "WF0_TOP_CLK", "WF0_TOP_DATA";
--			drive-strength = <4>;
--		};
--	};
--};
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -25,10 +25,6 @@
- 	};
- };
- 
--&uart0 {
--	status = "okay";
--};
--
- &eth {
- 	status = "okay";
- 
-@@ -99,13 +95,6 @@
- 	};
- };
- 
--&wifi {
--	status = "okay";
--	pinctrl-names = "default", "dbdc";
--	pinctrl-0 = <&wf_2g_5g_pins>;
--	pinctrl-1 = <&wf_dbdc_pins>;
--};
--
- &pio {
- 	wf_2g_5g_pins: wf-2g-5g-pins {
- 		mux {
-@@ -138,3 +127,14 @@
- 		};
- 	};
- };
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&wifi {
-+	status = "okay";
-+	pinctrl-names = "default", "dbdc";
-+	pinctrl-0 = <&wf_2g_5g_pins>;
-+	pinctrl-1 = <&wf_dbdc_pins>;
-+};
diff --git a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch
deleted file mode 100644
index fec048e68e..0000000000
--- a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:50:27 +0100
-Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
-
-This patch adds crypto engine support for MT7986.
-
-Signed-off-by: Vic Wu <vic.wu@mediatek.com>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  4 ++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  4 ++++
- 3 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -25,6 +25,10 @@
- 	};
- };
- 
-+&crypto {
-+	status = "okay";
-+};
-+
- &eth {
- 	status = "okay";
- 
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -224,6 +224,21 @@
- 			status = "disabled";
- 		};
- 
-+		crypto: crypto@10320000 {
-+			compatible = "inside-secure,safexcel-eip97";
-+			reg = <0 0x10320000 0 0x40000>;
-+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "ring0", "ring1", "ring2", "ring3";
-+			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-+			clock-names = "infra_eip97_ck";
-+			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-+			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@11002000 {
- 			compatible = "mediatek,mt7986-uart",
- 				     "mediatek,mt6577-uart";
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -25,6 +25,10 @@
- 	};
- };
- 
-+&crypto {
-+	status = "okay";
-+};
-+
- &eth {
- 	status = "okay";
- 
diff --git a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch b/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch
deleted file mode 100644
index 132940915b..0000000000
--- a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 6 Nov 2022 09:50:29 +0100
-Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
-
-Add i2c Node to mt7986 devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -280,6 +280,20 @@
- 			status = "disabled";
- 		};
- 
-+		i2c0: i2c@11008000 {
-+			compatible = "mediatek,mt7986-i2c";
-+			reg = <0 0x11008000 0 0x90>,
-+			      <0 0x10217080 0 0x80>;
-+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-div = <5>;
-+			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-+				 <&infracfg CLK_INFRA_AP_DMA_CK>;
-+			clock-names = "main", "dma";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
- 		ethsys: syscon@15000000 {
- 			 #address-cells = <1>;
- 			 #size-cells = <1>;
diff --git a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch b/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch
deleted file mode 100644
index 8201b47df6..0000000000
--- a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
-From: Matthias Brugger <mbrugger@suse.com>
-Date: Mon, 14 Nov 2022 13:16:53 +0100
-Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
-
-Missing SoC compatible in the board file causes dt bindings check.
-
-Signed-off-by: Matthias Brugger <mbrugger@suse.com>
-Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 1 +
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
- arch/arm64/boot/dts/mediatek/mt7986b.dtsi    | 3 +++
- 4 files changed, 6 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -9,7 +9,7 @@
- 
- / {
- 	model = "MediaTek MT7986a RFB";
--	compatible = "mediatek,mt7986a-rfb";
-+	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
- 
- 	aliases {
- 		serial0 = &uart0;
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -10,6 +10,7 @@
- #include <dt-bindings/reset/mt7986-resets.h>
- 
- / {
-+	compatible = "mediatek,mt7986a";
- 	interrupt-parent = <&gic>;
- 	#address-cells = <2>;
- 	#size-cells = <2>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -9,7 +9,7 @@
- 
- / {
- 	model = "MediaTek MT7986b RFB";
--	compatible = "mediatek,mt7986b-rfb";
-+	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
- 
- 	aliases {
- 		serial0 = &uart0;
---- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
-@@ -5,6 +5,9 @@
-  */
- 
- #include "mt7986a.dtsi"
-+/ {
-+	compatible = "mediatek,mt7986b";
-+};
- 
- &pio {
- 	compatible = "mediatek,mt7986b-pinctrl";
diff --git a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch
deleted file mode 100644
index c45f183dc7..0000000000
--- a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 18 Nov 2022 20:01:21 +0100
-Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
-
-This patch adds spi support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 28 ++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
- 3 files changed, 98 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -59,6 +59,20 @@
- };
- 
- &pio {
-+	spi_flash_pins: spi-flash-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spic_pins: spic-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi1_2";
-+		};
-+	};
-+
- 	uart1_pins: uart1-pins {
- 		mux {
- 			function = "uart";
-@@ -105,6 +119,27 @@
- 	};
- };
- 
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi_flash_pins>;
-+	cs-gpios = <0>, <0>;
-+	status = "okay";
-+	spi_nand: spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+	};
-+};
-+
-+&spi1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spic_pins>;
-+	cs-gpios = <0>, <0>;
-+	status = "okay";
-+};
-+
- &switch {
- 	ports {
- 		#address-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -295,6 +295,34 @@
- 			status = "disabled";
- 		};
- 
-+		spi0: spi@1100a000 {
-+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0 0x1100a000 0 0x100>;
-+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-+				 <&topckgen CLK_TOP_SPI_SEL>,
-+				 <&infracfg CLK_INFRA_SPI0_CK>,
-+				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-+			status = "disabled";
-+		};
-+
-+		spi1: spi@1100b000 {
-+			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0 0x1100b000 0 0x100>;
-+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-+				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
-+				 <&infracfg CLK_INFRA_SPI1_CK>,
-+				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-+			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-+			status = "disabled";
-+		};
-+
- 		ethsys: syscon@15000000 {
- 			 #address-cells = <1>;
- 			 #size-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -100,6 +100,20 @@
- };
- 
- &pio {
-+	spi_flash_pins: spi-flash-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spic_pins: spic-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi1_2";
-+		};
-+	};
-+
- 	wf_2g_5g_pins: wf-2g-5g-pins {
- 		mux {
- 			function = "wifi";
-@@ -132,6 +146,27 @@
- 	};
- };
- 
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi_flash_pins>;
-+	cs-gpios = <0>, <0>;
-+	status = "okay";
-+	spi_nand: spi_nand@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+	};
-+};
-+
-+&spi1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spic_pins>;
-+	cs-gpios = <0>, <0>;
-+	status = "okay";
-+};
-+
- &uart0 {
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch
deleted file mode 100644
index 603f33b150..0000000000
--- a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:42 +0100
-Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
-
-This patch adds USB support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
-Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  8 +++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 55 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  8 +++
- 3 files changed, 71 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -140,6 +140,10 @@
- 	status = "okay";
- };
- 
-+&ssusb {
-+	status = "okay";
-+};
-+
- &switch {
- 	ports {
- 		#address-cells = <1>;
-@@ -201,6 +205,10 @@
- 	status = "okay";
- };
- 
-+&usb_phy {
-+	status = "okay";
-+};
-+
- &wifi {
- 	status = "okay";
- 	pinctrl-names = "default", "dbdc";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -323,6 +323,61 @@
- 			status = "disabled";
- 		};
- 
-+		ssusb: usb@11200000 {
-+			compatible = "mediatek,mt7986-xhci",
-+				     "mediatek,mtk-xhci";
-+			reg = <0 0x11200000 0 0x2e00>,
-+			      <0 0x11203e00 0 0x0100>;
-+			reg-names = "mac", "ippc";
-+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-+				 <&infracfg CLK_INFRA_IUSB_CK>,
-+				 <&infracfg CLK_INFRA_IUSB_133_CK>,
-+				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
-+				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-+			clock-names = "sys_ck",
-+				      "ref_ck",
-+				      "mcu_ck",
-+				      "dma_ck",
-+				      "xhci_ck";
-+			phys = <&u2port0 PHY_TYPE_USB2>,
-+			       <&u3port0 PHY_TYPE_USB3>,
-+			       <&u2port1 PHY_TYPE_USB2>;
-+			status = "disabled";
-+		};
-+
-+		usb_phy: t-phy@11e10000 {
-+			compatible = "mediatek,mt7986-tphy",
-+				     "mediatek,generic-tphy-v2";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			ranges = <0 0 0x11e10000 0x1700>;
-+			status = "disabled";
-+
-+			u2port0: usb-phy@0 {
-+				reg = <0x0 0x700>;
-+				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-+					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-+				clock-names = "ref", "da_ref";
-+				#phy-cells = <1>;
-+			};
-+
-+			u3port0: usb-phy@700 {
-+				reg = <0x700 0x900>;
-+				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-+				clock-names = "ref";
-+				#phy-cells = <1>;
-+			};
-+
-+			u2port1: usb-phy@1000 {
-+				reg = <0x1000 0x700>;
-+				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-+					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-+				clock-names = "ref", "da_ref";
-+				#phy-cells = <1>;
-+			};
-+		};
-+
- 		ethsys: syscon@15000000 {
- 			 #address-cells = <1>;
- 			 #size-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -167,10 +167,18 @@
- 	status = "okay";
- };
- 
-+&ssusb {
-+	status = "okay";
-+};
-+
- &uart0 {
- 	status = "okay";
- };
- 
-+&usb_phy {
-+	status = "okay";
-+};
-+
- &wifi {
- 	status = "okay";
- 	pinctrl-names = "default", "dbdc";
diff --git a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch
deleted file mode 100644
index 40e71cd429..0000000000
--- a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch
+++ /dev/null
@@ -1,160 +0,0 @@
-From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:43 +0100
-Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
-
-This patch adds mmc support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++
- 2 files changed, 111 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -5,6 +5,8 @@
-  */
- 
- /dts-v1/;
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
- #include "mt7986a.dtsi"
- 
- / {
-@@ -23,6 +25,24 @@
- 		device_type = "memory";
- 		reg = <0 0x40000000 0 0x40000000>;
- 	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-1.8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "fixed-3.3V";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
- };
- 
- &crypto {
-@@ -58,7 +78,83 @@
- 	};
- };
- 
-+&mmc0 {
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	pinctrl-1 = <&mmc0_pins_uhs>;
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	cap-mmc-highspeed;
-+	mmc-hs200-1_8v;
-+	mmc-hs400-1_8v;
-+	hs400-ds-delay = <0x14014>;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+	non-removable;
-+	no-sd;
-+	no-sdio;
-+	status = "okay";
-+};
-+
- &pio {
-+	mmc0_pins_default: mmc0-pins {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+	};
-+
-+	mmc0_pins_uhs: mmc0-uhs-pins {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+	};
-+
- 	spi_flash_pins: spi-flash-pins {
- 		mux {
- 			function = "spi";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -346,6 +346,21 @@
- 			status = "disabled";
- 		};
- 
-+		mmc0: mmc@11230000 {
-+			compatible = "mediatek,mt7986-mmc";
-+			reg = <0 0x11230000 0 0x1000>,
-+			      <0 0x11c20000 0 0x1000>;
-+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-+				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-+				 <&infracfg CLK_INFRA_MSDC_CK>,
-+				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
-+				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
-+			clock-names = "source", "hclk", "source_cg", "bus_clk",
-+				      "sys_cg";
-+			status = "disabled";
-+		};
-+
- 		usb_phy: t-phy@11e10000 {
- 			compatible = "mediatek,mt7986-tphy",
- 				     "mediatek,generic-tphy-v2";
diff --git a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch
deleted file mode 100644
index ab039c335a..0000000000
--- a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:44 +0100
-Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
-
-This patch adds PCIe support for MT7986.
-
-Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 52 ++++++++++++++++++++
- 2 files changed, 68 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -93,6 +93,15 @@
- 	non-removable;
- 	no-sd;
- 	no-sdio;
-+};
-+
-+&pcie {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie_pins>;
-+	status = "okay";
-+};
-+
-+&pcie_phy {
- 	status = "okay";
- };
- 
-@@ -155,6 +164,13 @@
- 		};
- 	};
- 
-+	pcie_pins: pcie-pins {
-+		mux {
-+			function = "pcie";
-+			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-+		};
-+	};
-+
- 	spi_flash_pins: spi-flash-pins {
- 		mux {
- 			function = "spi";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -8,6 +8,7 @@
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt7986-clk.h>
- #include <dt-bindings/reset/mt7986-resets.h>
-+#include <dt-bindings/phy/phy.h>
- 
- / {
- 	compatible = "mediatek,mt7986a";
-@@ -361,6 +362,57 @@
- 			status = "disabled";
- 		};
- 
-+		pcie: pcie@11280000 {
-+			compatible = "mediatek,mt7986-pcie",
-+				     "mediatek,mt8192-pcie";
-+			device_type = "pci";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			reg = <0x00 0x11280000 0x00 0x4000>;
-+			reg-names = "pcie-mac";
-+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-+			bus-range = <0x00 0xff>;
-+			ranges = <0x82000000 0x00 0x20000000 0x00
-+				  0x20000000 0x00 0x10000000>;
-+			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-+				 <&infracfg CLK_INFRA_IPCIE_CK>,
-+				 <&infracfg CLK_INFRA_IPCIER_CK>,
-+				 <&infracfg CLK_INFRA_IPCIEB_CK>;
-+			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-+			status = "disabled";
-+
-+			phys = <&pcie_port PHY_TYPE_PCIE>;
-+			phy-names = "pcie-phy";
-+
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 0x7>;
-+			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-+					<0 0 0 2 &pcie_intc 1>,
-+					<0 0 0 3 &pcie_intc 2>,
-+					<0 0 0 4 &pcie_intc 3>;
-+			pcie_intc: interrupt-controller {
-+				#address-cells = <0>;
-+				#interrupt-cells = <1>;
-+				interrupt-controller;
-+			};
-+		};
-+
-+		pcie_phy: t-phy@11c00000 {
-+			compatible = "mediatek,mt7986-tphy",
-+				     "mediatek,generic-tphy-v2";
-+			#address-cells = <2>;
-+			#size-cells = <2>;
-+			ranges;
-+			status = "disabled";
-+
-+			pcie_port: pcie-phy@11c00000 {
-+				reg = <0 0x11c00000 0 0x20000>;
-+				clocks = <&clk40m>;
-+				clock-names = "ref";
-+				#phy-cells = <1>;
-+			};
-+		};
-+
- 		usb_phy: t-phy@11e10000 {
- 			compatible = "mediatek,mt7986-tphy",
- 				     "mediatek,generic-tphy-v2";
diff --git a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch
deleted file mode 100644
index 38f159c74e..0000000000
--- a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch
+++ /dev/null
@@ -1,689 +0,0 @@
-From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 6 Jan 2023 16:28:45 +0100
-Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
-
-Add support for Bananapi R3 SBC.
-
-- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
-- SPI-NAND/NOR support (switched CS by sw5/C)
-- all rj45 ports and both SFP working (eth1/lan4)
-- all USB-Ports + SIM-Slot tested
-- i2c and all uarts tested
-- wifi tested (with eeprom calibration data)
-
-The device can boot from all 4 storage options. Both, SPI and MMC, can
-be switched using hardware switches on the board, see
-https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/Makefile         |   5 +
- .../mt7986a-bananapi-bpi-r3-emmc.dtso         |  29 ++
- .../mt7986a-bananapi-bpi-r3-nand.dtso         |  55 +++
- .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso |  68 +++
- .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso  |  23 +
- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 450 ++++++++++++++++++
- 6 files changed, 630 insertions(+)
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-
---- a/arch/arm64/boot/dts/mediatek/Makefile
-+++ b/arch/arm64/boot/dts/mediatek/Makefile
-@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-@@ -0,0 +1,29 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Author: Sam.Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/soc/mmc@11230000";
-+		__overlay__ {
-+			bus-width = <8>;
-+			max-frequency = <200000000>;
-+			cap-mmc-highspeed;
-+			mmc-hs200-1_8v;
-+			mmc-hs400-1_8v;
-+			hs400-ds-delay = <0x14014>;
-+			non-removable;
-+			no-sd;
-+			no-sdio;
-+			status = "okay";
-+		};
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -0,0 +1,55 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+/*
-+ * Authors: Daniel Golle <daniel@makrotopia.org>
-+ *          Frank Wunderlich <frank-w@public-files.de>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/soc/spi@1100a000";
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			spi_nand: spi_nand@0 {
-+				compatible = "spi-nand";
-+				reg = <0>;
-+				spi-max-frequency = <10000000>;
-+				spi-tx-bus-width = <4>;
-+				spi-rx-bus-width = <4>;
-+
-+				partitions {
-+					compatible = "fixed-partitions";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					partition@0 {
-+						label = "bl2";
-+						reg = <0x0 0x80000>;
-+						read-only;
-+					};
-+
-+					partition@80000 {
-+						label = "reserved";
-+						reg = <0x80000 0x300000>;
-+					};
-+
-+					partition@380000 {
-+						label = "fip";
-+						reg = <0x380000 0x200000>;
-+						read-only;
-+					};
-+
-+					partition@580000 {
-+						label = "ubi";
-+						reg = <0x580000 0x7a80000>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -0,0 +1,68 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+/*
-+ * Authors: Daniel Golle <daniel@makrotopia.org>
-+ *          Frank Wunderlich <frank-w@public-files.de>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/soc/spi@1100a000";
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			flash@0 {
-+				compatible = "jedec,spi-nor";
-+				reg = <0>;
-+				spi-max-frequency = <10000000>;
-+
-+				partitions {
-+					compatible = "fixed-partitions";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					partition@0 {
-+						label = "bl2";
-+						reg = <0x0 0x20000>;
-+						read-only;
-+					};
-+
-+					partition@20000 {
-+						label = "reserved";
-+						reg = <0x20000 0x20000>;
-+					};
-+
-+					partition@40000 {
-+						label = "u-boot-env";
-+						reg = <0x40000 0x40000>;
-+					};
-+
-+					partition@80000 {
-+						label = "reserved2";
-+						reg = <0x80000 0x80000>;
-+					};
-+
-+					partition@100000 {
-+						label = "fip";
-+						reg = <0x100000 0x80000>;
-+						read-only;
-+					};
-+
-+					partition@180000 {
-+						label = "recovery";
-+						reg = <0x180000 0xa80000>;
-+					};
-+
-+					partition@c00000 {
-+						label = "fit";
-+						reg = <0xc00000 0x1400000>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-@@ -0,0 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Author: Sam.Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/soc/mmc@11230000";
-+		__overlay__ {
-+			bus-width = <4>;
-+			max-frequency = <52000000>;
-+			cap-sd-highspeed;
-+			status = "okay";
-+		};
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -0,0 +1,450 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Authors: Sam.Shih <sam.shih@mediatek.com>
-+ *          Frank Wunderlich <frank-w@public-files.de>
-+ *          Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
-+#include "mt7986a.dtsi"
-+
-+/ {
-+	model = "Bananapi BPI-R3";
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	aliases {
-+		serial0 = &uart0;
-+		ethernet0 = &gmac0;
-+		ethernet1 = &gmac1;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	dcin: regulator-12vd {
-+		compatible = "regulator-fixed";
-+		regulator-name = "12vd";
-+		regulator-min-microvolt = <12000000>;
-+		regulator-max-microvolt = <12000000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+	};
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+
-+		reset-key {
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
-+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-+		};
-+
-+		wps-key {
-+			label = "wps";
-+			linux,code = <KEY_WPS_BUTTON>;
-+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	/* i2c of the left SFP cage (wan) */
-+	i2c_sfp1: i2c-gpio-0 {
-+		compatible = "i2c-gpio";
-+		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+		i2c-gpio,delay-us = <2>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+
-+	/* i2c of the right SFP cage (lan) */
-+	i2c_sfp2: i2c-gpio-1 {
-+		compatible = "i2c-gpio";
-+		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+		i2c-gpio,delay-us = <2>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		green_led: led-0 {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_POWER;
-+			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-+			default-state = "on";
-+		};
-+
-+		blue_led: led-1 {
-+			color = <LED_COLOR_ID_BLUE>;
-+			function = LED_FUNCTION_STATUS;
-+			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-+			default-state = "off";
-+		};
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "1.8vd";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+		vin-supply = <&dcin>;
-+	};
-+
-+	reg_3p3v: regulator-3p3v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "3.3vd";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-boot-on;
-+		regulator-always-on;
-+		vin-supply = <&dcin>;
-+	};
-+
-+	/* left SFP cage (wan) */
-+	sfp1: sfp-1 {
-+		compatible = "sff,sfp";
-+		i2c-bus = <&i2c_sfp1>;
-+		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-+		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-+		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-+		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-+	};
-+
-+	/* right SFP cage (lan) */
-+	sfp2: sfp-2 {
-+		compatible = "sff,sfp";
-+		i2c-bus = <&i2c_sfp2>;
-+		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-+		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-+		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-+		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-+	};
-+};
-+
-+&crypto {
-+	status = "okay";
-+};
-+
-+&eth {
-+	status = "okay";
-+
-+	gmac0: mac@0 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <0>;
-+		phy-mode = "2500base-x";
-+
-+		fixed-link {
-+			speed = <2500>;
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+
-+	gmac1: mac@1 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <1>;
-+		phy-mode = "2500base-x";
-+		sfp = <&sfp1>;
-+		managed = "in-band-status";
-+	};
-+
-+	mdio: mdio-bus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+};
-+
-+&mdio {
-+	switch: switch@1f {
-+		compatible = "mediatek,mt7531";
-+		reg = <31>;
-+		interrupt-controller;
-+		#interrupt-cells = <1>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-+		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-+	};
-+};
-+
-+&mmc0 {
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	pinctrl-1 = <&mmc0_pins_uhs>;
-+	vmmc-supply = <&reg_3p3v>;
-+	vqmmc-supply = <&reg_1p8v>;
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c_pins>;
-+	status = "okay";
-+};
-+
-+&pcie {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie_pins>;
-+	status = "okay";
-+};
-+
-+&pcie_phy {
-+	status = "okay";
-+};
-+
-+&pio {
-+	i2c_pins: i2c-pins {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c";
-+		};
-+	};
-+
-+	mmc0_pins_default: mmc0-pins {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+	};
-+
-+	mmc0_pins_uhs: mmc0-uhs-pins {
-+		mux {
-+			function = "emmc";
-+			groups = "emmc_51";
-+		};
-+		conf-cmd-dat {
-+			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+			input-enable;
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+		conf-clk {
-+			pins = "EMMC_CK";
-+			drive-strength = <6>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-ds {
-+			pins = "EMMC_DSL";
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+		};
-+		conf-rst {
-+			pins = "EMMC_RSTB";
-+			drive-strength = <4>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+		};
-+	};
-+
-+	pcie_pins: pcie-pins {
-+		mux {
-+			function = "pcie";
-+			groups = "pcie_clk", "pcie_pereset";
-+		};
-+	};
-+
-+	spi_flash_pins: spi-flash-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi0", "spi0_wp_hold";
-+		};
-+	};
-+
-+	spic_pins: spic-pins {
-+		mux {
-+			function = "spi";
-+			groups = "spi1_0";
-+		};
-+	};
-+
-+	uart1_pins: uart1-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart1_rx_tx";
-+		};
-+	};
-+
-+	uart2_pins: uart2-pins {
-+		mux {
-+			function = "uart";
-+			groups = "uart2_0_rx_tx";
-+		};
-+	};
-+
-+	wf_2g_5g_pins: wf-2g-5g-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_2g", "wf_5g";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+
-+	wf_dbdc_pins: wf-dbdc-pins {
-+		mux {
-+			function = "wifi";
-+			groups = "wf_dbdc";
-+		};
-+		conf {
-+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
-+			drive-strength = <4>;
-+		};
-+	};
-+
-+	wf_led_pins: wf-led-pins {
-+		mux {
-+			function = "led";
-+			groups = "wifi_led";
-+		};
-+	};
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi_flash_pins>;
-+	status = "okay";
-+};
-+
-+&spi1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spic_pins>;
-+	status = "okay";
-+};
-+
-+&ssusb {
-+	status = "okay";
-+};
-+
-+&switch {
-+	ports {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		port@0 {
-+			reg = <0>;
-+			label = "wan";
-+		};
-+
-+		port@1 {
-+			reg = <1>;
-+			label = "lan0";
-+		};
-+
-+		port@2 {
-+			reg = <2>;
-+			label = "lan1";
-+		};
-+
-+		port@3 {
-+			reg = <3>;
-+			label = "lan2";
-+		};
-+
-+		port@4 {
-+			reg = <4>;
-+			label = "lan3";
-+		};
-+
-+		port5: port@5 {
-+			reg = <5>;
-+			label = "lan4";
-+			phy-mode = "2500base-x";
-+			sfp = <&sfp2>;
-+			managed = "in-band-status";
-+		};
-+
-+		port@6 {
-+			reg = <6>;
-+			label = "cpu";
-+			ethernet = <&gmac0>;
-+			phy-mode = "2500base-x";
-+
-+			fixed-link {
-+				speed = <2500>;
-+				full-duplex;
-+				pause;
-+			};
-+		};
-+	};
-+};
-+
-+&trng {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart2_pins>;
-+	status = "okay";
-+};
-+
-+&usb_phy {
-+	status = "okay";
-+};
-+
-+&watchdog {
-+	status = "okay";
-+};
-+
-+&wifi {
-+	status = "okay";
-+	pinctrl-names = "default", "dbdc";
-+	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-+	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+};
-+
diff --git a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch b/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch
deleted file mode 100644
index 79038334c4..0000000000
--- a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch
+++ /dev/null
@@ -1,323 +0,0 @@
-From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 17 May 2023 12:11:08 +0200
-Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
-
-The chassis-type string identifies the form-factor of the system:
-add this property to all device trees of devices for which the form
-factor is known.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt2712-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt6755-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt6779-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt6795-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt6797-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts                  | 1 +
- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts         | 1 +
- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts                     | 1 +
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts         | 1 +
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts                     | 1 +
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts                     | 1 +
- arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts                  | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts            | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts                 | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-evb.dts                      | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts     | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts       | 1 +
- .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts     | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts       | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts             | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts       | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts      | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts      | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts         | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts       | 1 +
- arch/arm64/boot/dts/mediatek/mt8186-evb.dts                      | 1 +
- 28 files changed, 28 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
-@@ -11,6 +11,7 @@
- 
- / {
- 	model = "MediaTek MT2712 evaluation board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek MT6755 EVB";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
-@@ -10,6 +10,7 @@
- 
- / {
- 	model = "MediaTek MT6779 EVB";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek MT6795 Evaluation Board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek MT6797 Evaluation Board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
-@@ -12,6 +12,7 @@
- 
- / {
- 	model = "Mediatek X20 Development Board";
-+	chassis-type = "embedded";
- 	compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -15,6 +15,7 @@
- 
- / {
- 	model = "Bananapi BPI-R64";
-+	chassis-type = "embedded";
- 	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -15,6 +15,7 @@
- 
- / {
- 	model = "MediaTek MT7622 RFB1 board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -16,6 +16,7 @@
- 
- / {
- 	model = "Bananapi BPI-R3";
-+	chassis-type = "embedded";
- 	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -11,6 +11,7 @@
- 
- / {
- 	model = "MediaTek MT7986a RFB";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek MT7986b RFB";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
-@@ -11,6 +11,7 @@
- 
- / {
- 	model = "Pumpkin MT8167";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
- 
- 	memory@40000000 {
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
-@@ -8,6 +8,7 @@
- 
- / {
- 	model = "Google Hanawl";
-+	chassis-type = "laptop";
- 	compatible = "google,hana-rev7", "mediatek,mt8173";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
-@@ -8,6 +8,7 @@
- 
- / {
- 	model = "Google Hana";
-+	chassis-type = "laptop";
- 	compatible = "google,hana-rev6", "google,hana-rev5",
- 		     "google,hana-rev4", "google,hana-rev3",
- 		     "google,hana", "mediatek,mt8173";
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
-@@ -8,6 +8,7 @@
- 
- / {
- 	model = "Google Elm";
-+	chassis-type = "laptop";
- 	compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
- 		     "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
- 		     "google,elm", "mediatek,mt8173";
---- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
-@@ -10,6 +10,7 @@
- 
- / {
- 	model = "MediaTek MT8173 evaluation board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
-@@ -11,6 +11,7 @@
- 
- / {
- 	model = "MediaTek MT8183 evaluation board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
- 
- 	aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "Google burnet board";
-+	chassis-type = "convertible";
- 	compatible = "google,burnet", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "Google damu board";
-+	chassis-type = "convertible";
- 	compatible = "google,damu", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "Google juniper sku16 board";
-+	chassis-type = "convertible";
- 	compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek kakadu board sku22";
-+	chassis-type = "tablet";
- 	compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
- 		     "google,kakadu", "mediatek,mt8183";
- };
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
-@@ -9,6 +9,7 @@
- 
- / {
- 	model = "MediaTek kakadu board";
-+	chassis-type = "tablet";
- 	compatible = "google,kakadu-rev3", "google,kakadu-rev2",
- 			"google,kakadu", "mediatek,mt8183";
- };
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
-@@ -12,6 +12,7 @@
- 
- / {
- 	model = "MediaTek kodama sku16 board";
-+	chassis-type = "tablet";
- 	compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
-@@ -12,6 +12,7 @@
- 
- / {
- 	model = "MediaTek kodama sku272 board";
-+	chassis-type = "tablet";
- 	compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
-@@ -12,6 +12,7 @@
- 
- / {
- 	model = "MediaTek kodama sku288 board";
-+	chassis-type = "tablet";
- 	compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
-@@ -14,6 +14,7 @@
- 
- / {
- 	model = "MediaTek krane sku0 board";
-+	chassis-type = "tablet";
- 	compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
-@@ -14,6 +14,7 @@
- 
- / {
- 	model = "MediaTek krane sku176 board";
-+	chassis-type = "tablet";
- 	compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
- };
- 
---- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
-@@ -7,6 +7,7 @@
- 
- / {
- 	model = "MediaTek MT8186 evaluation board";
-+	chassis-type = "embedded";
- 	compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
- 
- 	aliases {
diff --git a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch b/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch
deleted file mode 100644
index 915da7984e..0000000000
--- a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 21 Apr 2023 15:20:44 +0200
-Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
-
-This adds pwm node to mt7986.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -241,6 +241,20 @@
- 			status = "disabled";
- 		};
- 
-+		pwm: pwm@10048000 {
-+			compatible = "mediatek,mt7986-pwm";
-+			reg = <0 0x10048000 0 0x1000>;
-+			#clock-cells = <1>;
-+			#pwm-cells = <2>;
-+			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&topckgen CLK_TOP_PWM_SEL>,
-+				 <&infracfg CLK_INFRA_PWM_STA>,
-+				 <&infracfg CLK_INFRA_PWM1_CK>,
-+				 <&infracfg CLK_INFRA_PWM2_CK>;
-+			clock-names = "top", "main", "pwm1", "pwm2";
-+			status = "disabled";
-+		};
-+
- 		uart0: serial@11002000 {
- 			compatible = "mediatek,mt7986-uart",
- 				     "mediatek,mt6577-uart";
diff --git a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch b/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch
deleted file mode 100644
index ce908e3d31..0000000000
--- a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 21 Apr 2023 15:20:45 +0200
-Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
-
-Add pwm node and pinctrl to BananaPi R3 devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts   | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -275,6 +275,13 @@
- 		};
- 	};
- 
-+	pwm_pins: pwm-pins {
-+		mux {
-+			function = "pwm";
-+			groups = "pwm0", "pwm1_0";
-+		};
-+	};
-+
- 	spi_flash_pins: spi-flash-pins {
- 		mux {
- 			function = "spi";
-@@ -345,6 +352,12 @@
- 	};
- };
- 
-+&pwm {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm_pins>;
-+	status = "okay";
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spi_flash_pins>;
diff --git a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch b/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch
deleted file mode 100644
index c7b38484f4..0000000000
--- a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 5 Feb 2023 18:48:33 +0100
-Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
-
-Leds for Wifi are low-active, so add property to devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -460,5 +460,9 @@
- 	pinctrl-names = "default", "dbdc";
- 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
- 	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+	led {
-+		led-active-low;
-+	};
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch b/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch
deleted file mode 100644
index 0b84f1463a..0000000000
--- a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 28 May 2023 13:33:42 +0200
-Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
- bl2
-
-To store uncompressed bl2 more space is required than partition is
-actually defined.
-
-There is currently no known usage of this reserved partition.
-Openwrt uses same partition layout.
-
-We added same change to u-boot with commit d7bb1099 [1].
-
-[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
-
-Cc: stable@vger.kernel.org
-Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso     | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -27,15 +27,10 @@
- 
- 					partition@0 {
- 						label = "bl2";
--						reg = <0x0 0x20000>;
-+						reg = <0x0 0x40000>;
- 						read-only;
- 					};
- 
--					partition@20000 {
--						label = "reserved";
--						reg = <0x20000 0x20000>;
--					};
--
- 					partition@40000 {
- 						label = "u-boot-env";
- 						reg = <0x40000 0x40000>;
diff --git a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch b/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch
deleted file mode 100644
index f1cb0eaf02..0000000000
--- a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:33 +0200
-Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
-
-Add thermal related nodes to mt7986 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
- 1 file changed, 35 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -338,6 +338,15 @@
- 			status = "disabled";
- 		};
- 
-+		auxadc: adc@1100d000 {
-+			compatible = "mediatek,mt7986-auxadc";
-+			reg = <0 0x1100d000 0 0x1000>;
-+			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-+			clock-names = "main";
-+			#io-channel-cells = <1>;
-+			status = "disabled";
-+		};
-+
- 		ssusb: usb@11200000 {
- 			compatible = "mediatek,mt7986-xhci",
- 				     "mediatek,mtk-xhci";
-@@ -376,6 +385,21 @@
- 			status = "disabled";
- 		};
- 
-+		thermal: thermal@1100c800 {
-+			#thermal-sensor-cells = <1>;
-+			compatible = "mediatek,mt7986-thermal";
-+			reg = <0 0x1100c800 0 0x800>;
-+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&infracfg CLK_INFRA_THERM_CK>,
-+				 <&infracfg CLK_INFRA_ADC_26M_CK>,
-+				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
-+			clock-names = "therm", "auxadc", "adc_32k";
-+			mediatek,auxadc = <&auxadc>;
-+			mediatek,apmixedsys = <&apmixedsys>;
-+			nvmem-cells = <&thermal_calibration>;
-+			nvmem-cell-names = "calibration-data";
-+		};
-+
- 		pcie: pcie@11280000 {
- 			compatible = "mediatek,mt7986-pcie",
- 				     "mediatek,mt8192-pcie";
-@@ -427,6 +451,17 @@
- 			};
- 		};
- 
-+		efuse: efuse@11d00000 {
-+			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-+			reg = <0 0x11d00000 0 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			thermal_calibration: calib@274 {
-+				reg = <0x274 0xc>;
-+			};
-+		};
-+
- 		usb_phy: t-phy@11e10000 {
- 			compatible = "mediatek,mt7986-tphy",
- 				     "mediatek,generic-tphy-v2";
-@@ -568,5 +603,4 @@
- 			memory-region = <&wmcpu_emi>;
- 		};
- 	};
--
- };
diff --git a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch b/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch
deleted file mode 100644
index ad21fb8c3c..0000000000
--- a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:34 +0200
-Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
-
-Add thermal-zones to mt7986 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -603,4 +603,32 @@
- 			memory-region = <&wmcpu_emi>;
- 		};
- 	};
-+
-+	thermal-zones {
-+		cpu_thermal: cpu-thermal {
-+			polling-delay-passive = <1000>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&thermal 0>;
-+
-+			trips {
-+				cpu_trip_active_high: active-high {
-+					temperature = <115000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+
-+				cpu_trip_active_low: active-low {
-+					temperature = <85000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+
-+				cpu_trip_passive: passive {
-+					temperature = <40000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+			};
-+		};
-+	};
- };
diff --git a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch b/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch
deleted file mode 100644
index ca7d872a1b..0000000000
--- a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:35 +0200
-Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
- BPI-R3 dts
-
-Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 31 +++++++++++++++++++
- 1 file changed, 31 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -38,6 +38,15 @@
- 		regulator-always-on;
- 	};
- 
-+	fan: pwm-fan {
-+		compatible = "pwm-fan";
-+		#cooling-cells = <2>;
-+		/* cooling level (0, 1, 2) - pwm inverted */
-+		cooling-levels = <255 96 0>;
-+		pwms = <&pwm 0 10000 0>;
-+		status = "okay";
-+	};
-+
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 
-@@ -133,6 +142,28 @@
- 	};
- };
- 
-+&cpu_thermal {
-+	cooling-maps {
-+		cpu-active-high {
-+			/* active: set fan to cooling level 2 */
-+			cooling-device = <&fan 2 2>;
-+			trip = <&cpu_trip_active_high>;
-+		};
-+
-+		cpu-active-low {
-+			/* active: set fan to cooling level 1 */
-+			cooling-device = <&fan 1 1>;
-+			trip = <&cpu_trip_active_low>;
-+		};
-+
-+		cpu-passive {
-+			/* passive: set fan to cooling level 0 */
-+			cooling-device = <&fan 0 0>;
-+			trip = <&cpu_trip_passive>;
-+		};
-+	};
-+};
-+
- &crypto {
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch b/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch
deleted file mode 100644
index 9cc6cad0af..0000000000
--- a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 6 Jun 2023 16:43:20 +0100
-Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
- Bananapi R3
-
-The bootrom burned into the MT7986 SoC will try multiple locations on
-the SPI-NAND flash to load bl2 in case the bl2 image located at the the
-previously attempted offset is corrupt.
-
-Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
-allowing for up to four redundant copies of bl2 (typically sized a
-bit less than 0x40000).
-
-Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso     | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -29,13 +29,13 @@
- 
- 					partition@0 {
- 						label = "bl2";
--						reg = <0x0 0x80000>;
-+						reg = <0x0 0x100000>;
- 						read-only;
- 					};
- 
--					partition@80000 {
-+					partition@100000 {
- 						label = "reserved";
--						reg = <0x80000 0x300000>;
-+						reg = <0x100000 0x280000>;
- 					};
- 
- 					partition@380000 {
diff --git a/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
deleted file mode 100644
index 8cba3b2059..0000000000
--- a/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:33 +0200
-Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on
- BPI-R3
-
-All SFP power supplies are connected to the system VDD33 which is 3v3/8A.
-Set 3A per SFP slot to allow SFPs work which need more power than the
-default 1W.
-
-Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -126,6 +126,7 @@
- 		compatible = "sff,sfp";
- 		i2c-bus = <&i2c_sfp1>;
- 		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-+		maximum-power-milliwatt = <3000>;
- 		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
- 		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
- 		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-@@ -137,6 +138,7 @@
- 		i2c-bus = <&i2c_sfp2>;
- 		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
- 		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-+		maximum-power-milliwatt = <3000>;
- 		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
- 		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
- 	};
diff --git a/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
deleted file mode 100644
index 318ca43e13..0000000000
--- a/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:34 +0200
-Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips
-
-Add Critical and hot trips for emergency system shutdown and limiting
-system load.
-
-Change passive trip to active to make sure fan is activated on the
-lowest trip.
-
-Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -611,22 +611,34 @@
- 			thermal-sensors = <&thermal 0>;
- 
- 			trips {
-+				cpu_trip_crit: crit {
-+					temperature = <125000>;
-+					hysteresis = <2000>;
-+					type = "critical";
-+				};
-+
-+				cpu_trip_hot: hot {
-+					temperature = <120000>;
-+					hysteresis = <2000>;
-+					type = "hot";
-+				};
-+
- 				cpu_trip_active_high: active-high {
- 					temperature = <115000>;
- 					hysteresis = <2000>;
- 					type = "active";
- 				};
- 
--				cpu_trip_active_low: active-low {
-+				cpu_trip_active_med: active-med {
- 					temperature = <85000>;
- 					hysteresis = <2000>;
- 					type = "active";
- 				};
- 
--				cpu_trip_passive: passive {
--					temperature = <40000>;
-+				cpu_trip_active_low: active-low {
-+					temperature = <60000>;
- 					hysteresis = <2000>;
--					type = "passive";
-+					type = "active";
- 				};
- 			};
- 		};
diff --git a/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
deleted file mode 100644
index 7166ab6a14..0000000000
--- a/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:35 +0200
-Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3
-
-Apply new naming after mt7986 thermal trips were changed.
-
-Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts      | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -152,16 +152,16 @@
- 			trip = <&cpu_trip_active_high>;
- 		};
- 
--		cpu-active-low {
-+		cpu-active-med {
- 			/* active: set fan to cooling level 1 */
- 			cooling-device = <&fan 1 1>;
--			trip = <&cpu_trip_active_low>;
-+			trip = <&cpu_trip_active_med>;
- 		};
- 
--		cpu-passive {
--			/* passive: set fan to cooling level 0 */
-+		cpu-active-low {
-+			/* active: set fan to cooling level 0 */
- 			cooling-device = <&fan 0 0>;
--			trip = <&cpu_trip_passive>;
-+			trip = <&cpu_trip_active_low>;
- 		};
- 	};
- };
diff --git a/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
deleted file mode 100644
index bb87c20a91..0000000000
--- a/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -103,6 +103,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -11,6 +11,9 @@
- #include <linux/vmalloc.h>
- #include <linux/raid/detect.h>
- #include <linux/property.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
- 
- #include "check.h"
- 
-@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -439,6 +445,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -51,6 +51,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	} else {
- 		snprintf(gd->disk_name, sizeof(gd->disk_name),
- 			 "%s%d", tr->name, new->devnum);
--		gd->flags |= GENHD_FL_NO_PART;
-+
-+		if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
-+			gd->flags |= GENHD_FL_NO_PART;
- 	}
- 
- 	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in
- 		ret = -ENODEV;
- 		goto out_cleanup_disk;
- 	}
--	gd->flags |= GENHD_FL_NO_PART;
-+	if (!IS_ENABLED(CONFIG_FIT_PARTITION))
-+		gd->flags |= GENHD_FL_NO_PART;
-+
- 	gd->private_data = dev;
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch
deleted file mode 100644
index 1eeed82c1b..0000000000
--- a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch
+++ /dev/null
@@ -1,107 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -1,7 +1,6 @@
- /*
-- * Copyright (c) 2017 MediaTek Inc.
-- * Author: Ming Huang <ming.huang@mediatek.com>
-- *	   Sean Wang <sean.wang@mediatek.com>
-+ * Copyright (c) 2018 MediaTek Inc.
-+ * Author: Ryder Lee <ryder.lee@mediatek.com>
-  *
-  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
-  */
-@@ -24,7 +23,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
-@@ -45,18 +44,18 @@
- 		key-factory {
- 			label = "factory";
- 			linux,code = <BTN_0>;
--			gpios = <&pio 0 0>;
-+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
- 		};
- 
- 		key-wps {
- 			label = "wps";
- 			linux,code = <KEY_WPS_BUTTON>;
--			gpios = <&pio 102 0>;
-+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- 		};
- 	};
- 
- 	memory@40000000 {
--		reg = <0 0x40000000 0 0x20000000>;
-+		reg = <0 0x40000000 0 0x40000000>;
- 		device_type = "memory";
- 	};
- 
-@@ -133,22 +132,22 @@
- 
- 				port@0 {
- 					reg = <0>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@4 {
-@@ -241,7 +240,22 @@
- 	status = "okay";
- };
- 
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_pins>;
-+	status = "okay";
-+};
-+
- &pio {
-+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
-+	 */
-+	asm_sel {
-+		gpio-hog;
-+		gpios = <90 GPIO_ACTIVE_HIGH>;
-+		output-high;
-+	};
-+
- 	/* eMMC is shared pin with parallel NAND */
- 	emmc_pins_default: emmc-pins-default {
- 		mux {
-@@ -518,11 +532,11 @@
- };
- 
- &sata {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "okay";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch
deleted file mode 100644
index b1770371b0..0000000000
--- a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch
+++ /dev/null
@@ -1,60 +0,0 @@
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -18,6 +18,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
- 	};
- 
- 	gpio-keys {
-@@ -70,6 +71,10 @@
- 		compatible = "mediatek,eth-mac";
- 		reg = <0>;
- 		phy-mode = "2500base-x";
-+
-+		nvmem-cells = <&macaddr_factory_2a>;
-+		nvmem-cell-names = "mac-address";
-+
- 		fixed-link {
- 			speed = <2500>;
- 			full-duplex;
-@@ -82,6 +87,9 @@
- 		reg = <1>;
- 		phy-mode = "gmii";
- 		phy-handle = <&phy0>;
-+
-+		nvmem-cells = <&macaddr_factory_24>;
-+		nvmem-cell-names = "mac-address";
- 	};
- 
- 	mdio: mdio-bus {
-@@ -133,8 +141,9 @@
- 			};
- 
- 			partition@b0000 {
--				label = "kernel";
-+				label = "firmware";
- 				reg = <0xb0000 0xb50000>;
-+				compatible = "denx,fit";
- 			};
- 		};
- 	};
-@@ -273,3 +282,17 @@
- 	pinctrl-0 = <&watchdog_pins>;
- 	status = "okay";
- };
-+
-+&factory {
-+	compatible = "nvmem-cells";
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+
-+	macaddr_factory_24: macaddr@24 {
-+		reg = <0x24 0x6>;
-+	};
-+
-+	macaddr_factory_2a: macaddr@2a {
-+		reg = <0x2a 0x6>;
-+	};
-+};
diff --git a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch
deleted file mode 100644
index 04df7b927b..0000000000
--- a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Fri, 29 Apr 2022 10:40:56 +0800
-Subject: [PATCH] arm: mediatek: select arch timer for mt7623
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
----
- arch/arm/mach-mediatek/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -26,6 +26,7 @@ config MACH_MT6592
- config MACH_MT7623
- 	bool "MediaTek MT7623 SoCs support"
- 	default ARCH_MEDIATEK
-+	select HAVE_ARM_ARCH_TIMER
- 
- config MACH_MT7629
- 	bool "MediaTek MT7629 SoCs support"
diff --git a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch
deleted file mode 100644
index 0d9c91f44d..0000000000
--- a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -578,6 +578,7 @@
- 		compatible = "mediatek,mt7622-nor",
- 			     "mediatek,mt8173-nor";
- 		reg = <0 0x11014000 0 0xe0>;
-+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
- 		clocks = <&pericfg CLK_PERI_FLASH_PD>,
- 			 <&topckgen CLK_TOP_FLASH_SEL>;
- 		clock-names = "spi", "sf";
diff --git a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch
deleted file mode 100644
index 93da722e72..0000000000
--- a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch
+++ /dev/null
@@ -1,16 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -134,6 +134,13 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch b/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch
deleted file mode 100644
index ac8594b396..0000000000
--- a/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -109,10 +109,6 @@
- 	status = "disabled";
- };
- 
--&btif {
--	status = "okay";
--};
--
- &cir {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&irrx_pins>;
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -90,10 +90,6 @@
- 	status = "disabled";
- };
- 
--&btif {
--	status = "okay";
--};
--
- &cir {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&irrx_pins>;
diff --git a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch
deleted file mode 100644
index 8dc53d2985..0000000000
--- a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,6 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
-+		bootargs = "console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch
deleted file mode 100644
index f77f10cb95..0000000000
--- a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -24,7 +24,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- 	};
- 
- 	cpus {
diff --git a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch
deleted file mode 100644
index 2cc0efdade..0000000000
--- a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch
+++ /dev/null
@@ -1,37 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -20,6 +20,7 @@
- 
- 	aliases {
- 		serial0 = &uart0;
-+		ethernet0 = &gmac0;
- 	};
- 
- 	chosen {
-@@ -161,22 +162,22 @@
- 
- 				port@1 {
- 					reg = <1>;
--					label = "lan0";
-+					label = "lan1";
- 				};
- 
- 				port@2 {
- 					reg = <2>;
--					label = "lan1";
-+					label = "lan2";
- 				};
- 
- 				port@3 {
- 					reg = <3>;
--					label = "lan2";
-+					label = "lan3";
- 				};
- 
- 				port@4 {
- 					reg = <4>;
--					label = "lan3";
-+					label = "lan4";
- 				};
- 
- 				port@6 {
diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
deleted file mode 100644
index 1cca6f3534..0000000000
--- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch
+++ /dev/null
@@ -1,49 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -21,6 +21,12 @@
- 	aliases {
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
-+		mmc0 = &mmc0;
-+		mmc1 = &mmc1;
- 	};
- 
- 	chosen {
-@@ -44,8 +50,8 @@
- 		compatible = "gpio-keys";
- 
- 		factory-key {
--			label = "factory";
--			linux,code = <BTN_0>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
- 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- 		};
- 
-@@ -59,17 +65,17 @@
- 	leds {
- 		compatible = "gpio-leds";
- 
--		led-0 {
-+		led_system_green: led-0 {
- 			label = "bpi-r64:pio:green";
- 			color = <LED_COLOR_ID_GREEN>;
- 			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
- 
--		led-1 {
--			label = "bpi-r64:pio:red";
--			color = <LED_COLOR_ID_RED>;
--			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+		led_system_blue: led-1 {
-+			label = "bpi-r64:pio:blue";
-+			color = <LED_COLOR_ID_BLUE>;
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
- 			default-state = "off";
- 		};
- 	};
diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
deleted file mode 100644
index 119de1c457..0000000000
--- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -557,12 +557,16 @@
- 	status = "okay";
- };
- 
-+&rtc {
-+	status = "disabled";
-+};
-+
- &sata {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &sata_phy {
--	status = "disable";
-+	status = "disabled";
- };
- 
- &spi0 {
diff --git a/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch b/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch
deleted file mode 100644
index 6eac51f825..0000000000
--- a/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:15:53 +0100
-Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64
-
-The SPI-NOR node in the device tree of the BananaPi R64 has most likely
-been copied from the reference board's device tree even though the R64
-comes with an SPI-NAND chip rather than SPI-NOR.
-
-Setup the Serial NAND Flash Interface (SNFI) controller, enable
-hardware BCH error detection and correction engine and add the SPI-NAND
-chip including basic partitions,
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 38 ++++++++++++++++---
- 1 file changed, 33 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -254,14 +254,42 @@
- 	status = "disabled";
- };
- 
--&nor_flash {
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi_nor_pins>;
--	status = "disabled";
-+&bch {
-+	status = "okay";
-+};
- 
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
- 	flash@0 {
--		compatible = "jedec,spi-nor";
-+		compatible = "spi-nand";
- 		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "bl2";
-+				reg = <0x0 0x80000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "fip";
-+				reg = <0x80000 0x200000>;
-+				read-only;
-+			};
-+
-+			ubi: partition@280000 {
-+				label = "ubi";
-+				reg = <0x280000 0x7d80000>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch
deleted file mode 100644
index ff5521c44e..0000000000
--- a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
- static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
- {
- 	struct spinand_device *spinand = nand_to_spinand(nand);
--	u8 marker[2] = { };
-+	u8 marker[1] = { };
- 	struct nand_page_io_req req = {
- 		.pos = *pos,
- 		.ooblen = sizeof(marker),
-@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
- 
- 	spinand_select_target(spinand, pos->target);
- 	spinand_read_page(spinand, &req);
--	if (marker[0] != 0xff || marker[1] != 0xff)
-+	if (marker[0] != 0xff)
- 		return true;
- 
- 	return false;
diff --git a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch
deleted file mode 100644
index 82654e683c..0000000000
--- a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
-From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
-Date: Thu, 6 Jun 2019 16:29:04 +0800
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
-
-Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
- 3 files changed, 79 insertions(+)
-
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -272,6 +272,27 @@
- 			status = "disabled";
- 		};
- 
-+		snfi: spi@1100d000 {
-+			compatible = "mediatek,mt7629-snand";
-+			reg = <0x1100d000 0x1000>;
-+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+			clock-names = "nfi_clk", "pad_clk";
-+			nand-ecc-engine = <&bch>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		bch: ecc@1100e000 {
-+			compatible = "mediatek,mt7622-ecc";
-+			reg = <0x1100e000 0x1000>;
-+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
-+			clocks = <&pericfg CLK_PERI_NFIECC_PD>;
-+			clock-names = "nfiecc_clk";
-+			status = "disabled";
-+		};
-+
- 		spi: spi@1100a000 {
- 			compatible = "mediatek,mt7629-spi",
- 				     "mediatek,mt7622-spi";
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -255,6 +255,50 @@
- 	};
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Bootloader";
-+				reg = <0x00000 0x0100000>;
-+				read-only;
-+			};
-+
-+			partition@100000 {
-+				label = "Config";
-+				reg = <0x100000 0x0040000>;
-+			};
-+
-+			partition@140000 {
-+				label = "factory";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "firmware";
-+				reg = <0x1c0000 0x1000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spi_pins>;
diff --git a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch
deleted file mode 100644
index 1a0e3237c8..0000000000
--- a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -535,6 +535,65 @@
- 	status = "disabled";
- };
- 
-+&bch {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&serial_nand_pins>;
-+	status = "okay";
-+	flash@0 {
-+		compatible = "spi-nand";
-+		reg = <0>;
-+		spi-tx-bus-width = <4>;
-+		spi-rx-bus-width = <4>;
-+		nand-ecc-engine = <&snfi>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "Preloader";
-+				reg = <0x00000 0x0080000>;
-+				read-only;
-+			};
-+
-+			partition@80000 {
-+				label = "ATF";
-+				reg = <0x80000 0x0040000>;
-+			};
-+
-+			partition@c0000 {
-+				label = "Bootloader";
-+				reg = <0xc0000 0x0080000>;
-+			};
-+
-+			partition@140000 {
-+				label = "Config";
-+				reg = <0x140000 0x0080000>;
-+			};
-+
-+			partition@1c0000 {
-+				label = "Factory";
-+				reg = <0x1c0000 0x0100000>;
-+			};
-+
-+			partition@200000 {
-+				label = "firmware";
-+				reg = <0x2c0000 0x2000000>;
-+			};
-+
-+			partition@2200000 {
-+				label = "User_data";
-+				reg = <0x22c0000 0x4000000>;
-+			};
-+		};
-+	};
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spic0_pins>;
diff --git a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
deleted file mode 100644
index 208046ad16..0000000000
--- a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -576,7 +576,7 @@
- 				reg = <0x140000 0x0080000>;
- 			};
- 
--			partition@1c0000 {
-+			factory: partition@1c0000 {
- 				label = "Factory";
- 				reg = <0x1c0000 0x0100000>;
- 			};
-@@ -637,5 +637,6 @@
- &wmac {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&wmac_pins>;
-+	mediatek,mtd-eeprom = <&factory 0x0000>;
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch
deleted file mode 100644
index 0860a22c37..0000000000
--- a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,24 +0,0 @@
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -984,17 +984,15 @@
- 	};
- 
- 	crypto: crypto@1b240000 {
--		compatible = "mediatek,eip97-crypto";
-+		compatible = "inside-secure,safexcel-eip97";
- 		reg = <0 0x1b240000 0 0x20000>;
- 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
- 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
--			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-+			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
- 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
--		clock-names = "cryp";
--		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
--		status = "disabled";
-+		status = "okay";
- 	};
- 
- 	bdpsys: syscon@1c000000 {
diff --git a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch
deleted file mode 100644
index 091cffc3c0..0000000000
--- a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,7 +19,7 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
--		bootargs = "console=ttyS2,115200n8 console=tty1";
-+		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
- 	};
- 
- 	connector {
diff --git a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch
deleted file mode 100644
index d1bafc1526..0000000000
--- a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,8 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		mmc0 = &mmc0;
-+		mmc1 = &mmc1;
- 	};
- 
- 	chosen {
diff --git a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch
deleted file mode 100644
index f6745add5b..0000000000
--- a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -17,6 +17,10 @@
- 		serial2 = &uart2;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
-+		led-boot = &led_system_green;
-+		led-failsafe = &led_system_blue;
-+		led-running = &led_system_green;
-+		led-upgrade = &led_system_blue;
- 	};
- 
- 	chosen {
-@@ -112,13 +116,13 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&led_pins_a>;
- 
--		blue {
-+		led_system_blue: blue {
- 			label = "bpi-r2:pio:blue";
- 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
- 		};
- 
--		green {
-+		led_system_green: green {
- 			label = "bpi-r2:pio:green";
- 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
- 			default-state = "off";
diff --git a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch
deleted file mode 100644
index b1dd75a414..0000000000
--- a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,7 @@
- 
- 	aliases {
- 		serial2 = &uart2;
-+		ethernet0 = &gmac0;
- 		mmc0 = &mmc0;
- 		mmc1 = &mmc1;
- 		led-boot = &led_system_green;
diff --git a/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
deleted file mode 100644
index f617211c9a..0000000000
--- a/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
+++ /dev/null
@@ -1,55 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -26,7 +26,9 @@
- 
- 	chosen {
- 		stdout-path = "serial2:115200n8";
--		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+		bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+		rootdisk-emmc = <&emmc_rootdisk>;
-+		rootdisk-sd = <&sd_rootdisk>;
- 	};
- 
- 	connector {
-@@ -315,6 +317,20 @@
- 	vmmc-supply = <&reg_3p3v>;
- 	vqmmc-supply = <&reg_1p8v>;
- 	non-removable;
-+
-+	card@0 {
-+		compatible = "mmc-card";
-+		reg = <0>;
-+
-+		block {
-+			compatible = "block-device";
-+			partitions {
-+				emmc_rootdisk: block-partition-fit {
-+					partno = <3>;
-+				};
-+			};
-+		};
-+	};
- };
- 
- &mmc1 {
-@@ -328,6 +344,20 @@
- 	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
- 	vmmc-supply = <&reg_3p3v>;
- 	vqmmc-supply = <&reg_3p3v>;
-+
-+	card@0 {
-+		compatible = "mmc-card";
-+		reg = <0>;
-+
-+		block {
-+			compatible = "block-device";
-+			partitions {
-+				sd_rootdisk: block-partition-fit {
-+					partno = <3>;
-+				};
-+			};
-+		};
-+	};
- };
- 
- &mt6323_leds {
diff --git a/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch b/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch
deleted file mode 100644
index d396d38f20..0000000000
--- a/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:16:29 +0100
-Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on
- BPI-R64
-
-Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support")
-the mt7530 driver can act as an interrupt controller. Wire up irq line
-of the MT7531 switch on the BananaPi BPi-R64 board, so the status of
-the PHYs of the five 1000Base-T ports doesn't need to be polled any
-more.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -155,6 +155,10 @@
- 		switch@0 {
- 			compatible = "mediatek,mt7531";
- 			reg = <0>;
-+			interrupt-controller;
-+			#interrupt-cells = <1>;
-+			interrupt-parent = <&pio>;
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- 			reset-gpios = <&pio 54 0>;
- 
- 			ports {
diff --git a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
deleted file mode 100644
index 1e04d23a0e..0000000000
--- a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From patchwork Tue Apr 26 19:51:36 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 12827872
-Return-Path: 
- <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
-X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
-	aws-us-west-2-korg-lkml-1.web.codeaurora.org
-Received: from bombadil.infradead.org (bombadil.infradead.org
- [198.137.202.133])
-	(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
-	(No client certificate requested)
-	by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF
-	for <linux-arm-kernel@archiver.kernel.org>;
- Tue, 26 Apr 2022 19:53:05 +0000 (UTC)
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
-	d=lists.infradead.org; s=bombadil.20210309; h=Sender:
-	Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
-	List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To:
-	From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
-	Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
-	List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb
-	x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg
-	WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9
-	QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh
-	o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k
-	AZHmXoQxq1mrsm2FxfnQ==;
-Received: from localhost ([::1] helo=bombadil.infradead.org)
-	by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
-	id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000
-Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71])
- by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
- id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000
-Received: from local
- by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256)
- (Exim 4.94.2) (envelope-from <daniel@makrotopia.org>)
- id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
-Date: Tue, 26 Apr 2022 20:51:36 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Matthias Brugger <matthias.bgg@gmail.com>
-Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
-Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
-X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C 
-X-CRM114-Status: GOOD (  12.45  )
-X-BeenThere: linux-arm-kernel@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-arm-kernel.lists.infradead.org>
-List-Unsubscribe: 
- <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
-List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
-List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
-List-Subscribe: 
- <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
-Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
-Errors-To: 
- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-With the current range specified for the CPU interface there is an
-error message at boot:
-
-GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
-
-Setting irqchip.gicv2_force_probe=1 in bootargs results in:
-
-GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
-GIC: Adjusting CPU interface base to 0x000000001032f000
-GIC: Using split EOI/Deactivate mode
-
-Using the adjusted CPU interface base and 8K size results in only the
-final line remaining and fully working system as well as /proc/interrupts
-showing additional IPI3,4,5,6:
-
-IPI3:         0          0       CPU stop (for crash dump) interrupts
-IPI4:         0          0       Timer broadcast interrupts
-IPI5:         0          0       IRQ work interrupts
-IPI6:         0          0       CPU wake-up interrupts
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -346,7 +346,7 @@
- 		#interrupt-cells = <3>;
- 		interrupt-parent = <&gic>;
- 		reg = <0 0x10310000 0 0x1000>,
--		      <0 0x10320000 0 0x1000>,
-+		      <0 0x1032f000 0 0x2000>,
- 		      <0 0x10340000 0 0x2000>,
- 		      <0 0x10360000 0 0x2000>;
- 	};
diff --git a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch
deleted file mode 100644
index 1cfb53d620..0000000000
--- a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
-From: Bruno Umuarama <anonimou_eu@hotmail.com>
-Date: Thu, 13 Oct 2022 21:18:21 +0000
-Subject: [PATCH] mediatek: mt7623: fix thermal zone
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Raising the temperatures for passive and active trips. @VA1DER
-proposed at issue 9396 to remove passive trip. This commit relates to
-his suggestion.
-
-Without this patch. the CPU will be throttled all the way down to 98MHz
-if the temperature rises even a degree above the trip point, and it was
-further discovered that if the internal temperature of the device is
-above the first trip point temperature when it boots then it will start
-in a throttled state and even
-$ echo disabled > /sys/class/thermal/thermal_zone0/mode
-will have no effect.
-
-The patch increases the passive trip point and active cooling map. The
-throttling temperature will then be at 77°C and 82°C, which is still a
-low enough temperature for ARM devices to not be in the real danger
-zone, and gives some operational headroom.
-
-Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
----
- arch/arm/boot/dts/mt7623.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -160,13 +160,13 @@
- 
- 				trips {
- 					cpu_passive: cpu-passive {
--						temperature = <57000>;
-+						temperature = <77000>;
- 						hysteresis = <2000>;
- 						type = "passive";
- 					};
- 
- 					cpu_active: cpu-active {
--						temperature = <67000>;
-+						temperature = <82000>;
- 						hysteresis = <2000>;
- 						type = "active";
- 					};
diff --git a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch
deleted file mode 100644
index 161c1e7516..0000000000
--- a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -68,6 +68,14 @@
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+
-+		/* 64 KiB reserved for ramoops/pstore */
-+		ramoops@42ff0000 {
-+			compatible = "ramoops";
-+			reg = <0 0x42ff0000 0 0x10000>;
-+			record-size = <0x1000>;
-+		};
-+
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- 		secmon_reserved: secmon@43000000 {
- 			reg = <0 0x43000000 0 0x30000>;
diff --git a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
deleted file mode 100644
index 336920bafe..0000000000
--- a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch
+++ /dev/null
@@ -1,196 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -23,6 +23,10 @@
- 		serial0 = &uart0;
- 		ethernet0 = &gmac0;
- 		ethernet1 = &gmac1;
-+		led-boot = &green_led;
-+		led-failsafe = &green_led;
-+		led-running = &green_led;
-+		led-upgrade = &blue_led;
- 	};
- 
- 	chosen {
-@@ -419,27 +423,27 @@
- 
- 		port@1 {
- 			reg = <1>;
--			label = "lan0";
-+			label = "lan1";
- 		};
- 
- 		port@2 {
- 			reg = <2>;
--			label = "lan1";
-+			label = "lan2";
- 		};
- 
- 		port@3 {
- 			reg = <3>;
--			label = "lan2";
-+			label = "lan3";
- 		};
- 
- 		port@4 {
- 			reg = <4>;
--			label = "lan3";
-+			label = "lan4";
- 		};
- 
- 		port5: port@5 {
- 			reg = <5>;
--			label = "lan4";
-+			label = "sfp2";
- 			phy-mode = "2500base-x";
- 			sfp = <&sfp2>;
- 			managed = "in-band-status";
-@@ -490,9 +494,137 @@
- 
- &wifi {
- 	status = "okay";
--	pinctrl-names = "default", "dbdc";
-+	pinctrl-names = "default";
- 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
--	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+	mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
-+				0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
-+				0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
-+				0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
-+				0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
-+				0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
-+				0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
-+				0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
-+				0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
-+				0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
-+				0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
-+				0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
-+				0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
-+				0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
-+				0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
-+				0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
-+				0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
-+				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+				0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
-+				0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
-+				0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
-+				0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
-+				0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
-+				0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
-+				0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
-+				0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
-+				0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
-+				0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
-+				0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
-+				0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
-+				0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
-+				0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+				0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
-+				0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
-+				0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
-+				0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
-+				0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
-+				0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
-+				0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
-+				0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
-+				0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
-+				0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
- 
- 	led {
- 		led-active-low;
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -55,6 +55,7 @@
- 					partition@c00000 {
- 						label = "fit";
- 						reg = <0xc00000 0x1400000>;
-+						compatible = "denx,fit";
- 					};
- 				};
- 			};
diff --git a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
deleted file mode 100644
index 38510c0fc7..0000000000
--- a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch
+++ /dev/null
@@ -1,131 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-@@ -23,7 +23,27 @@
- 			no-sd;
- 			no-sdio;
- 			status = "okay";
-+
-+			card@0 {
-+				compatible = "mmc-card";
-+				reg = <0>;
-+
-+				block {
-+					compatible = "block-device";
-+					partitions {
-+						emmc_rootdisk: block-partition-production {
-+							partname = "production";
-+						};
-+					};
-+				};
-+			};
- 		};
- 	};
--};
- 
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			rootdisk-emmc = <&emmc_rootdisk>;
-+		};
-+	};
-+};
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -29,27 +29,30 @@
- 
- 					partition@0 {
- 						label = "bl2";
--						reg = <0x0 0x100000>;
-+						reg = <0x0 0x200000>;
- 						read-only;
- 					};
- 
--					partition@100000 {
--						label = "reserved";
--						reg = <0x100000 0x280000>;
--					};
--
--					partition@380000 {
--						label = "fip";
--						reg = <0x380000 0x200000>;
--						read-only;
--					};
--
--					partition@580000 {
-+					partition@200000 {
- 						label = "ubi";
--						reg = <0x580000 0x7a80000>;
-+						reg = <0x200000 0x7e00000>;
-+						compatible = "linux,ubi";
-+
-+						volumes {
-+							nand_rootdisk: ubi-volume-fit {
-+								volname = "fit";
-+							};
-+						};
- 					};
- 				};
- 			};
- 		};
- 	};
-+
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			rootdisk-spim-nand = <&nand_rootdisk>;
-+		};
-+	};
- };
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -52,7 +52,7 @@
- 						reg = <0x180000 0xa80000>;
- 					};
- 
--					partition@c00000 {
-+					nor_rootdisk: partition@c00000 {
- 						label = "fit";
- 						reg = <0xc00000 0x1400000>;
- 						compatible = "denx,fit";
-@@ -61,4 +61,11 @@
- 			};
- 		};
- 	};
-+
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			rootdisk-nor = <&nor_rootdisk>;
-+		};
-+	};
- };
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-@@ -17,6 +17,27 @@
- 			max-frequency = <52000000>;
- 			cap-sd-highspeed;
- 			status = "okay";
-+
-+			card@0 {
-+				compatible = "mmc-card";
-+				reg = <0>;
-+
-+				block {
-+					compatible = "block-device";
-+					partitions {
-+						sd_rootdisk: block-partition-production {
-+							partname = "production";
-+						};
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			rootdisk-sd = <&sd_rootdisk>;
- 		};
- 	};
- };
diff --git a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
deleted file mode 100644
index 6347533aa8..0000000000
--- a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
-From: Kristian Evensen <kristian.evensen@gmail.com>
-Date: Mon, 30 Apr 2018 14:38:01 +0200
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
-
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -17,6 +17,8 @@
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- #include "phy-mtk-io.h"
- 
-@@ -264,6 +266,9 @@
- 
- #define TPHY_CLKS_CNT	2
- 
-+#define HIF_SYSCFG1			0x14
-+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
-+
- enum mtk_phy_version {
- 	MTK_PHY_V1 = 1,
- 	MTK_PHY_V2,
-@@ -331,6 +336,7 @@ struct mtk_tphy {
- 	void __iomem *sif_base;	/* only shared sif */
- 	const struct mtk_phy_pdata *pdata;
- 	struct mtk_phy_instance **phys;
-+	struct regmap *hif;
- 	int nphys;
- 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
- 	int src_coef; /* coefficient for slew rate calibrate */
-@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
- 	if (tphy->pdata->version != MTK_PHY_V1)
- 		return;
- 
-+	if (tphy->hif)
-+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
-+				   HIF_SYSCFG1_PHY2_MASK, 0);
-+
- 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
- 			    P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
- 			    FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
-@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
- 					 &tphy->src_coef);
- 	}
- 
-+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
-+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
-+							    "mediatek,phy-switch");
-+		if (IS_ERR(tphy->hif)) {
-+			dev_err(&pdev->dev,
-+				"missing \"mediatek,phy-switch\" phandle\n");
-+			return PTR_ERR(tphy->hif);
-+		}
-+	}
-+
- 	port = 0;
- 	for_each_child_of_node(np, child_np) {
- 		struct mtk_phy_instance *instance;
diff --git a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch b/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch
deleted file mode 100644
index 3e16a533e1..0000000000
--- a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sat, 8 Oct 2022 18:48:06 +0200
-Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
- separately
-
-Some mt7986 boards use uart rts/cts pins as gpio,
-This patch allows to change rts/cts to gpio mode, but keep
-rx/tx as UART function.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
- 1 file changed, 25 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
- static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
- static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
- 
--static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
-+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
- 
--static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
-+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-+
-+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-+
-+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
- 
- static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
- static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
- static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
- static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
- 
-+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-+
-+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-+
- static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
- static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
- 
-@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
- 	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
- 	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
- 	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-+	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-+	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
- 	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
- 	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
- 	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
- 	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
- 	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
- 	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
--	PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
--	PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
-+	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-+	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-+	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-+	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
- 	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
- 	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
- 	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
- static const char *mt7986_spi_groups[] = {
- 	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
- static const char *mt7986_uart_groups[] = {
--	"uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
-+	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-+	"uart1_2_rx_tx", "uart1_2_cts_rts",
-+	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
- 	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
- };
- static const char *mt7986_wdt_groups[] = { "watchdog", };
diff --git a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch b/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch
deleted file mode 100644
index 47ded1aeb5..0000000000
--- a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:13 +0100
-Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
- MT7986 SoC
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-add SoC specify 'pull_type' attribute for bias configuration.
-
-This patch add pull_type attribute to pinctrl-mt7986.c, and make
-bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
- 	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
- };
- 
-+static const unsigned int mt7986_pull_type[] = {
-+	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-+	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-+	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-+	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-+	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-+	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-+	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-+	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-+	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-+	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-+	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-+	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-+	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-+	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-+	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-+	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-+	MTK_PULL_PU_PD_TYPE,/*100*/
-+};
-+
- static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
- 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
- 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
- 	.ies_present = false,
- 	.base_names = mt7986_pinctrl_register_base_names,
- 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+	.pull_type = mt7986_pull_type,
- 	.bias_set_combo = mtk_pinconf_bias_set_combo,
- 	.bias_get_combo = mtk_pinconf_bias_get_combo,
- 	.drive_set = mtk_pinconf_drive_set_rev1,
-@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
- 	.ies_present = false,
- 	.base_names = mt7986_pinctrl_register_base_names,
- 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+	.pull_type = mt7986_pull_type,
- 	.bias_set_combo = mtk_pinconf_bias_set_combo,
- 	.bias_get_combo = mtk_pinconf_bias_get_combo,
- 	.drive_set = mtk_pinconf_drive_set_rev1,
diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch
deleted file mode 100644
index 46dfa24b7b..0000000000
--- a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch
+++ /dev/null
@@ -1,1094 +0,0 @@
-From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 00:34:56 +0000
-Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
-
-Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
-which can also be found the SDK.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/Kconfig          |    5 +
- drivers/pinctrl/mediatek/Makefile         |    1 +
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
- 3 files changed, 1054 insertions(+)
- create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -127,6 +127,11 @@ config PINCTRL_MT7622
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7981
-+	bool "Mediatek MT7981 pin control"
-+	depends on OF
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- 	bool "Mediatek MT7986 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
---- /dev/null
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -0,0 +1,1048 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * The MT7981 driver based on Linux generic pinctrl binding.
-+ *
-+ * Copyright (C) 2020 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include "pinctrl-moore.h"
-+
-+#define MT7981_PIN(_number, _name)				\
-+	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-+
-+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-+		       _x_bits, 32, 0)
-+
-+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
-+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
-+		      _x_bits, 32, 1)
-+
-+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-+	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-+	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-+	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-+	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-+	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-+	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-+	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-+	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-+	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-+	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-+	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-+	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-+	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-+	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-+	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-+	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-+	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-+	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-+	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-+	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-+	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-+	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-+	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-+	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-+	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-+	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-+	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-+	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-+	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-+	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-+	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-+	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-+	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-+	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-+	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-+	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-+	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-+	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-+	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-+	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-+	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-+	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-+	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-+	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-+	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-+	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-+	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-+	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-+	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-+	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-+	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-+	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-+	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-+	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-+	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-+	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-+
-+	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-+	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-+	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-+	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-+	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-+	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-+	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-+	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-+	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-+	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-+	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-+	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-+	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-+
-+	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-+	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-+	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-+	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-+	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-+
-+	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-+
-+	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-+
-+	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-+	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-+	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-+	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-+	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-+
-+	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-+	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-+	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-+	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-+	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-+	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-+	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-+	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-+	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-+	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-+	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-+	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-+	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-+	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-+	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-+	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-+	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-+	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-+	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-+	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-+	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-+	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-+	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-+	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-+	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-+	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-+	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-+	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-+	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-+	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-+	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-+	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-+	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-+	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-+	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-+	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-+
-+	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-+	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-+	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-+	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-+
-+	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-+	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-+	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-+	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-+	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-+
-+	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-+	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-+	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-+	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-+	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-+	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-+
-+	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-+
-+	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-+	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-+
-+	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-+	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-+	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-+	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-+};
-+
-+static const unsigned int mt7981_pull_type[] = {
-+	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-+	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-+	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-+	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-+	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-+	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-+	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-+	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-+	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-+	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-+	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-+	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-+	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-+	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-+	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-+	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-+	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-+	MTK_PULL_PU_PD_TYPE,/*100*/
-+};
-+
-+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-+};
-+
-+static const struct mtk_pin_desc mt7981_pins[] = {
-+	MT7981_PIN(0, "GPIO_WPS"),
-+	MT7981_PIN(1, "GPIO_RESET"),
-+	MT7981_PIN(2, "SYS_WATCHDOG"),
-+	MT7981_PIN(3, "PCIE_PERESET_N"),
-+	MT7981_PIN(4, "JTAG_JTDO"),
-+	MT7981_PIN(5, "JTAG_JTDI"),
-+	MT7981_PIN(6, "JTAG_JTMS"),
-+	MT7981_PIN(7, "JTAG_JTCLK"),
-+	MT7981_PIN(8, "JTAG_JTRST_N"),
-+	MT7981_PIN(9, "WO_JTAG_JTDO"),
-+	MT7981_PIN(10, "WO_JTAG_JTDI"),
-+	MT7981_PIN(11, "WO_JTAG_JTMS"),
-+	MT7981_PIN(12, "WO_JTAG_JTCLK"),
-+	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-+	MT7981_PIN(14, "USB_VBUS"),
-+	MT7981_PIN(15, "PWM0"),
-+	MT7981_PIN(16, "SPI0_CLK"),
-+	MT7981_PIN(17, "SPI0_MOSI"),
-+	MT7981_PIN(18, "SPI0_MISO"),
-+	MT7981_PIN(19, "SPI0_CS"),
-+	MT7981_PIN(20, "SPI0_HOLD"),
-+	MT7981_PIN(21, "SPI0_WP"),
-+	MT7981_PIN(22, "SPI1_CLK"),
-+	MT7981_PIN(23, "SPI1_MOSI"),
-+	MT7981_PIN(24, "SPI1_MISO"),
-+	MT7981_PIN(25, "SPI1_CS"),
-+	MT7981_PIN(26, "SPI2_CLK"),
-+	MT7981_PIN(27, "SPI2_MOSI"),
-+	MT7981_PIN(28, "SPI2_MISO"),
-+	MT7981_PIN(29, "SPI2_CS"),
-+	MT7981_PIN(30, "SPI2_HOLD"),
-+	MT7981_PIN(31, "SPI2_WP"),
-+	MT7981_PIN(32, "UART0_RXD"),
-+	MT7981_PIN(33, "UART0_TXD"),
-+	MT7981_PIN(34, "PCIE_CLK_REQ"),
-+	MT7981_PIN(35, "PCIE_WAKE_N"),
-+	MT7981_PIN(36, "SMI_MDC"),
-+	MT7981_PIN(37, "SMI_MDIO"),
-+	MT7981_PIN(38, "GBE_INT"),
-+	MT7981_PIN(39, "GBE_RESET"),
-+	MT7981_PIN(40, "WF_DIG_RESETB"),
-+	MT7981_PIN(41, "WF_CBA_RESETB"),
-+	MT7981_PIN(42, "WF_XO_REQ"),
-+	MT7981_PIN(43, "WF_TOP_CLK"),
-+	MT7981_PIN(44, "WF_TOP_DATA"),
-+	MT7981_PIN(45, "WF_HB1"),
-+	MT7981_PIN(46, "WF_HB2"),
-+	MT7981_PIN(47, "WF_HB3"),
-+	MT7981_PIN(48, "WF_HB4"),
-+	MT7981_PIN(49, "WF_HB0"),
-+	MT7981_PIN(50, "WF_HB0_B"),
-+	MT7981_PIN(51, "WF_HB5"),
-+	MT7981_PIN(52, "WF_HB6"),
-+	MT7981_PIN(53, "WF_HB7"),
-+	MT7981_PIN(54, "WF_HB8"),
-+	MT7981_PIN(55, "WF_HB9"),
-+	MT7981_PIN(56, "WF_HB10"),
-+};
-+
-+/* List all groups consisting of these pins dedicated to the enablement of
-+ * certain hardware block and the corresponding mode for all of the pins.
-+ * The hardware probably has multiple combinations of these pinouts.
-+ */
-+
-+/* WA_AICE */
-+static int mt7981_wa_aice1_pins[] = { 0, 1, };
-+static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-+
-+static int mt7981_wa_aice2_pins[] = { 0, 1, };
-+static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-+
-+static int mt7981_wa_aice3_pins[] = { 28, 29, };
-+static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-+
-+static int mt7981_wm_aice1_pins[] = { 9, 10, };
-+static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-+
-+static int mt7981_wm_aice2_pins[] = { 30, 31, };
-+static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-+
-+/* WM_UART */
-+static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-+static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-+
-+static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-+static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-+
-+static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-+static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-+
-+/* DFD */
-+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-+
-+/* SYS_WATCHDOG */
-+static int mt7981_watchdog_pins[] = { 2, };
-+static int mt7981_watchdog_funcs[] = { 1, };
-+
-+static int mt7981_watchdog1_pins[] = { 13, };
-+static int mt7981_watchdog1_funcs[] = { 5, };
-+
-+/* PCIE_PERESET_N */
-+static int mt7981_pcie_pereset_pins[] = { 3, };
-+static int mt7981_pcie_pereset_funcs[] = { 1, };
-+
-+/* JTAG */
-+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-+
-+/* WM_JTAG */
-+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-+
-+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+
-+/* WO0_JTAG */
-+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-+
-+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+
-+/* UART2 */
-+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-+
-+/* GBE_LED0 */
-+static int mt7981_gbe_led0_pins[] = { 8, };
-+static int mt7981_gbe_led0_funcs[] = { 3, };
-+
-+/* PTA_EXT */
-+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-+
-+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-+
-+/* PWM2 */
-+static int mt7981_pwm2_pins[] = { 7, };
-+static int mt7981_pwm2_funcs[] = { 4, };
-+
-+/* NET_WO0_UART_TXD */
-+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-+
-+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-+
-+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-+
-+/* SPI1 */
-+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-+
-+/* I2C */
-+static int mt7981_i2c0_0_pins[] = { 6, 7, };
-+static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-+
-+static int mt7981_i2c0_1_pins[] = { 30, 31, };
-+static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-+
-+static int mt7981_i2c0_2_pins[] = { 36, 37, };
-+static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-+
-+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-+
-+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-+
-+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-+
-+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-+
-+/* DFD_NTRST */
-+static int mt7981_dfd_ntrst_pins[] = { 8, };
-+static int mt7981_dfd_ntrst_funcs[] = { 6, };
-+
-+/* PWM0 */
-+static int mt7981_pwm0_0_pins[] = { 13, };
-+static int mt7981_pwm0_0_funcs[] = { 2, };
-+
-+static int mt7981_pwm0_1_pins[] = { 15, };
-+static int mt7981_pwm0_1_funcs[] = { 1, };
-+
-+/* PWM1 */
-+static int mt7981_pwm1_0_pins[] = { 14, };
-+static int mt7981_pwm1_0_funcs[] = { 2, };
-+
-+static int mt7981_pwm1_1_pins[] = { 15, };
-+static int mt7981_pwm1_1_funcs[] = { 3, };
-+
-+/* GBE_LED1 */
-+static int mt7981_gbe_led1_pins[] = { 13, };
-+static int mt7981_gbe_led1_funcs[] = { 3, };
-+
-+/* PCM */
-+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-+
-+/* UDI */
-+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-+
-+/* DRV_VBUS */
-+static int mt7981_drv_vbus_pins[] = { 14, };
-+static int mt7981_drv_vbus_funcs[] = { 1, };
-+
-+/* EMMC */
-+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+
-+/* SNFI */
-+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+
-+/* SPI0 */
-+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI0 */
-+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-+
-+/* SPI1 */
-+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI2 */
-+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI2 */
-+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-+
-+/* UART1 */
-+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-+
-+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-+
-+/* UART2 */
-+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+
-+/* UART0 */
-+static int mt7981_uart0_pins[] = { 32, 33, };
-+static int mt7981_uart0_funcs[] = { 1, 1, };
-+
-+/* PCIE_CLK_REQ */
-+static int mt7981_pcie_clk_pins[] = { 34, };
-+static int mt7981_pcie_clk_funcs[] = { 2, };
-+
-+/* PCIE_WAKE_N */
-+static int mt7981_pcie_wake_pins[] = { 35, };
-+static int mt7981_pcie_wake_funcs[] = { 2, };
-+
-+/* MDC_MDIO */
-+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-+
-+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-+
-+/* WF0_MODE1 */
-+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-+
-+/* WF0_MODE3 */
-+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+
-+/* WF2G_LED */
-+static int mt7981_wf2g_led0_pins[] = { 30, };
-+static int mt7981_wf2g_led0_funcs[] = { 2, };
-+
-+static int mt7981_wf2g_led1_pins[] = { 34, };
-+static int mt7981_wf2g_led1_funcs[] = { 1, };
-+
-+/* WF5G_LED */
-+static int mt7981_wf5g_led0_pins[] = { 31, };
-+static int mt7981_wf5g_led0_funcs[] = { 2, };
-+
-+static int mt7981_wf5g_led1_pins[] = { 35, };
-+static int mt7981_wf5g_led1_funcs[] = { 1, };
-+
-+/* MT7531_INT */
-+static int mt7981_mt7531_int_pins[] = { 38, };
-+static int mt7981_mt7531_int_funcs[] = { 1, };
-+
-+/* ANT_SEL */
-+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-+
-+static const struct group_desc mt7981_groups[] = {
-+	/* @GPIO(0,1): WA_AICE(2) */
-+	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-+	/* @GPIO(0,1): WA_AICE(3) */
-+	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-+	/* @GPIO(0,1): WM_UART(5) */
-+	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-+	/* @GPIO(0,1,4,5): DFD(6) */
-+	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-+	/* @GPIO(2): SYS_WATCHDOG(1) */
-+	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-+	/* @GPIO(3): PCIE_PERESET_N(1) */
-+	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-+	/* @GPIO(4,8) JTAG(1) */
-+	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-+	/* @GPIO(4,8) WM_JTAG(2) */
-+	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-+	/* @GPIO(9,13) WO0_JTAG(1) */
-+	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-+	/* @GPIO(4,7) WM_JTAG(3) */
-+	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-+	/* @GPIO(8) GBE_LED0(3) */
-+	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-+	/* @GPIO(4,6) PTA_EXT(4) */
-+	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-+	/* @GPIO(7) PWM2(4) */
-+	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-+	/* @GPIO(8) NET_WO0_UART_TXD(4) */
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-+	/* @GPIO(4,7) SPI1(5) */
-+	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-+	/* @GPIO(6,7) I2C(5) */
-+	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-+	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
-+	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-+	/* @GPIO(9,10): WM_AICE(2) */
-+	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-+	/* @GPIO(13): PWM0(2) */
-+	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-+	/* @GPIO(15): PWM0(1) */
-+	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-+	/* @GPIO(14): PWM1(2) */
-+	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-+	/* @GPIO(15): PWM1(3) */
-+	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-+	/* @GPIO(14) NET_WO0_UART_TXD(3) */
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-+	/* @GPIO(15) NET_WO0_UART_TXD(4) */
-+	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-+	/* @GPIO(13) GBE_LED0(3) */
-+	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-+	/* @GPIO(9,13) PCM(4) */
-+	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-+	/* @GPIO(13): SYS_WATCHDOG1(5) */
-+	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-+	/* @GPIO(9,13) UDI(4) */
-+	PINCTRL_PIN_GROUP("udi", mt7981_udi),
-+	/* @GPIO(14) DRV_VBUS(1) */
-+	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-+	/* @GPIO(15,25): EMMC(2) */
-+	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-+	/* @GPIO(16,21): SNFI(3) */
-+	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-+	/* @GPIO(16,19): SPI0(1) */
-+	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-+	/* @GPIO(20,21): SPI0(1) */
-+	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-+	/* @GPIO(22,25) SPI1(1) */
-+	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-+	/* @GPIO(26,29): SPI2(1) */
-+	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-+	/* @GPIO(30,31): SPI0(1) */
-+	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-+	/* @GPIO(16,19): UART1(4) */
-+	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-+	/* @GPIO(26,29): UART1(2) */
-+	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-+	/* @GPIO(22,25): UART1(3) */
-+	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-+	/* @GPIO(22,24) PTA_EXT(4) */
-+	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-+	/* @GPIO(20,21): WM_UART(4) */
-+	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-+	/* @GPIO(30,31): WM_UART(3) */
-+	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-+	/* @GPIO(20,24) WM_JTAG(5) */
-+	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-+	/* @GPIO(25,29) WO0_JTAG(5) */
-+	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-+	/* @GPIO(28,29): WA_AICE(3) */
-+	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-+	/* @GPIO(30,31): WM_AICE(5) */
-+	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-+	/* @GPIO(30,31): I2C(4) */
-+	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-+	/* @GPIO(30,31): I2C(6) */
-+	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-+	/* @GPIO(32,33): I2C(1) */
-+	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-+	/* @GPIO(32,33): I2C(2) */
-+	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-+	/* @GPIO(32,33): I2C(3) */
-+	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-+	/* @GPIO(32,33): I2C(5) */
-+	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-+	/* @GPIO(34): PCIE_CLK_REQ(2) */
-+	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-+	/* @GPIO(35): PCIE_WAKE_N(2) */
-+	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-+	/* @GPIO(36,37): I2C(2) */
-+	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-+	/* @GPIO(36,37): MDC_MDIO(1) */
-+	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-+	/* @GPIO(36,37): MDC_MDIO(3) */
-+	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-+	/* @GPIO(69,85): WF0_MODE1(1) */
-+	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-+	/* @GPIO(74,80): WF0_MODE3(3) */
-+	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-+	/* @GPIO(30): WF2G_LED(2) */
-+	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-+	/* @GPIO(34): WF2G_LED(1) */
-+	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-+	/* @GPIO(31): WF5G_LED(2) */
-+	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-+	/* @GPIO(35): WF5G_LED(1) */
-+	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-+	/* @GPIO(38): MT7531_INT(1) */
-+	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-+	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-+	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-+};
-+
-+/* Joint those groups owning the same capability in user point of view which
-+ * allows that people tend to use through the device tree.
-+ */
-+static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-+	"wa_aice3", "wm_aice1_2", };
-+static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-+	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-+	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-+static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-+static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-+static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-+static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-+	"wo0_jtag_1", "wm_jtag_1", };
-+static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-+	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
-+static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-+static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-+	"pwm1_0", "pwm1_1", };
-+static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-+	"spi2_wp_hold", };
-+static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-+	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-+static const char *mt7981_pcm_groups[] = { "pcm", };
-+static const char *mt7981_udi_groups[] = { "udi", };
-+static const char *mt7981_usb_groups[] = { "drv_vbus", };
-+static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-+static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-+	"wf0_mode1", "wf0_mode3", "mt7531_int", };
-+static const char *mt7981_ant_groups[] = { "ant_sel", };
-+
-+static const struct function_desc mt7981_functions[] = {
-+	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-+	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-+	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-+	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-+	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-+	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-+	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-+	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-+	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-+	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-+	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-+	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-+	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-+	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-+	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-+	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-+	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-+};
-+
-+static const struct mtk_eint_hw mt7981_eint_hw = {
-+	.port_mask = 7,
-+	.ports     = 7,
-+	.ap_num    = ARRAY_SIZE(mt7981_pins),
-+	.db_cnt    = 16,
-+};
-+
-+static const char * const mt7981_pinctrl_register_base_names[] = {
-+	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-+	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-+};
-+
-+static struct mtk_pin_soc mt7981_data = {
-+	.reg_cal = mt7981_reg_cals,
-+	.pins = mt7981_pins,
-+	.npins = ARRAY_SIZE(mt7981_pins),
-+	.grps = mt7981_groups,
-+	.ngrps = ARRAY_SIZE(mt7981_groups),
-+	.funcs = mt7981_functions,
-+	.nfuncs = ARRAY_SIZE(mt7981_functions),
-+	.eint_hw = &mt7981_eint_hw,
-+	.gpio_m = 0,
-+	.ies_present = false,
-+	.base_names = mt7981_pinctrl_register_base_names,
-+	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-+	.pull_type = mt7981_pull_type,
-+	.bias_set_combo = mtk_pinconf_bias_set_combo,
-+	.bias_get_combo = mtk_pinconf_bias_get_combo,
-+	.drive_set = mtk_pinconf_drive_set_rev1,
-+	.drive_get = mtk_pinconf_drive_get_rev1,
-+	.adv_pull_get = mtk_pinconf_adv_pull_get,
-+	.adv_pull_set = mtk_pinconf_adv_pull_set,
-+};
-+
-+static const struct of_device_id mt7981_pinctrl_of_match[] = {
-+	{ .compatible = "mediatek,mt7981-pinctrl", },
-+	{}
-+};
-+
-+static int mt7981_pinctrl_probe(struct platform_device *pdev)
-+{
-+	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-+}
-+
-+static struct platform_driver mt7981_pinctrl_driver = {
-+	.driver = {
-+		.name = "mt7981-pinctrl",
-+		.of_match_table = mt7981_pinctrl_of_match,
-+	},
-+	.probe = mt7981_pinctrl_probe,
-+};
-+
-+static int __init mt7981_pinctrl_init(void)
-+{
-+	return platform_driver_register(&mt7981_pinctrl_driver);
-+}
-+arch_initcall(mt7981_pinctrl_init);
diff --git a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch b/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch
deleted file mode 100644
index 995e0dc7ed..0000000000
--- a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 18 Feb 2023 09:51:06 +0300
-Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are options missing from PINCTRL_MT7981 whilst being on every other
-pin controller. Add them.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Acked-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -130,6 +130,8 @@ config PINCTRL_MT7622
- config PINCTRL_MT7981
- 	bool "Mediatek MT7981 pin control"
- 	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
- config PINCTRL_MT7986
diff --git a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch b/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch
deleted file mode 100644
index db2561695b..0000000000
--- a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 18 Aug 2023 04:02:35 +0100
-Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981
-
-MediaTek has released pull_type data for MT7981 in their SDK.
-Use it and set functions to configure pin bias.
-
-Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++----------------
- 1 file changed, 13 insertions(+), 31 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty
- 	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
- 	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
- 	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
--	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
--	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
--	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
--	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
--	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
--	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
--	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
--	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
--	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
--	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
--	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
--	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
--	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
--	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
--	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
--	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
--	MTK_PULL_PU_PD_TYPE,/*100*/
-+	MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
-+	MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
-+	MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
-+	MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
-+	MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
-+	MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
-+	MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
-+	MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
-+	MTK_PULL_PU_PD_TYPE,/*56*/
- };
- 
- static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data =
- 	.ies_present = false,
- 	.base_names = mt7981_pinctrl_register_base_names,
- 	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-+	.bias_disable_set = mtk_pinconf_bias_disable_set,
-+	.bias_disable_get = mtk_pinconf_bias_disable_get,
-+	.bias_set = mtk_pinconf_bias_set,
-+	.bias_get = mtk_pinconf_bias_get,
- 	.pull_type = mt7981_pull_type,
- 	.bias_set_combo = mtk_pinconf_bias_set_combo,
- 	.bias_get_combo = mtk_pinconf_bias_get_combo,
diff --git a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch b/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch
deleted file mode 100644
index d2f055836b..0000000000
--- a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:06:14 +0100
-Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
-
-Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
- 1 file changed, 13 insertions(+), 3 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
- static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
- static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
- 
-+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
-+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
-+
- /* GBE_LED0 */
- static int mt7981_gbe_led0_pins[] = { 8, };
- static int mt7981_gbe_led0_funcs[] = { 3, };
-@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
- static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
- static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
- 
-+static int mt7981_uart1_2_pins[] = { 9, 10, };
-+static int mt7981_uart1_2_funcs[] = { 2, 2, };
-+
- /* UART2 */
- static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
- static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
- 	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
- 	/* @GPIO(4,7) WM_JTAG(3) */
- 	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-+	/* @GPIO(4,5) WM_JTAG(4) */
-+	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
- 	/* @GPIO(8) GBE_LED0(3) */
- 	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
- 	/* @GPIO(4,6) PTA_EXT(4) */
-@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
- 	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
- 	/* @GPIO(26,29): UART1(2) */
- 	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-+	/* @GPIO(9,10): UART1(2) */
-+	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
- 	/* @GPIO(22,25): UART1(3) */
- 	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
- 	/* @GPIO(22,24) PTA_EXT(4) */
-@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
-  */
- static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
- 	"wa_aice3", "wm_aice1_2", };
--static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
--	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
--	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
-+	"net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
-+	"uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
- static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
- static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
- static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
diff --git a/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch
deleted file mode 100644
index 7992a02677..0000000000
--- a/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 18 Aug 2023 04:03:26 +0100
-Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on
- MT7986
-
-Assign bias_disable_get/set and bias_get/set functions to allow
-configuring pin bias on MT7986.
-
-Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data =
- 	.ies_present = false,
- 	.base_names = mt7986_pinctrl_register_base_names,
- 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+	.bias_disable_set = mtk_pinconf_bias_disable_set,
-+	.bias_disable_get = mtk_pinconf_bias_disable_get,
-+	.bias_set = mtk_pinconf_bias_set,
-+	.bias_get = mtk_pinconf_bias_get,
- 	.pull_type = mt7986_pull_type,
- 	.bias_set_combo = mtk_pinconf_bias_set_combo,
- 	.bias_get_combo = mtk_pinconf_bias_get_combo,
-@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data =
- 	.ies_present = false,
- 	.base_names = mt7986_pinctrl_register_base_names,
- 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+	.bias_disable_set = mtk_pinconf_bias_disable_set,
-+	.bias_disable_get = mtk_pinconf_bias_disable_get,
-+	.bias_set = mtk_pinconf_bias_set,
-+	.bias_get = mtk_pinconf_bias_get,
- 	.pull_type = mt7986_pull_type,
- 	.bias_set_combo = mtk_pinconf_bias_set_combo,
- 	.bias_get_combo = mtk_pinconf_bias_get_combo,
diff --git a/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch b/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch
deleted file mode 100644
index af5715e1f5..0000000000
--- a/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch
+++ /dev/null
@@ -1,536 +0,0 @@
-From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:33 +0100
-Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
- mtk_clk_register_gates()
-
-Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
-introduces a helper function for the sole purpose of propagating a
-struct device pointer to the clk API when registering the mtk-gate
-clocks to take advantage of Runtime PM when/where needed and where
-a power domain is defined in devicetree.
-
-Function mtk_clk_register_gates() then becomes a wrapper around the
-new mtk_clk_register_gates_with_dev() function that will simply pass
-NULL as struct device: this is essential when registering drivers
-with CLK_OF_DECLARE instead of as a platform device, as there will
-be no struct device to pass... but we can as well simply have only
-one function that always takes such pointer as a param and pass NULL
-when unavoidable.
-
-This commit removes the mtk_clk_register_gates() wrapper and renames
-mtk_clk_register_gates_with_dev() to the former and all of the calls
-to either of the two functions were fixed in all drivers in order to
-reflect this change; also, to improve consistency with other kernel
-functions, the pointer to struct device was moved as the first param.
-
-Since a lot of MediaTek clock drivers are actually registering as a
-platform device, but were still registering the mtk-gate clocks
-without passing any struct device to the clock framework, they've
-been changed to pass a valid one now, as to make all those platforms
-able to use runtime power management where available.
-
-While at it, some much needed indentation changes were also done.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: dropped parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-gate.c            | 23 +++++++---------------
- drivers/clk/mediatek/clk-gate.h            |  7 +------
- drivers/clk/mediatek/clk-mt2701-aud.c      |  4 ++--
- drivers/clk/mediatek/clk-mt2701-eth.c      |  4 ++--
- drivers/clk/mediatek/clk-mt2701-g3d.c      |  2 +-
- drivers/clk/mediatek/clk-mt2701-hif.c      |  4 ++--
- drivers/clk/mediatek/clk-mt2701-mm.c       |  4 ++--
- drivers/clk/mediatek/clk-mt2701.c          | 12 +++++------
- drivers/clk/mediatek/clk-mt2712-mm.c       |  4 ++--
- drivers/clk/mediatek/clk-mt2712.c          | 12 +++++------
- drivers/clk/mediatek/clk-mt7622-aud.c      |  4 ++--
- drivers/clk/mediatek/clk-mt7622-eth.c      |  8 ++++----
- drivers/clk/mediatek/clk-mt7622-hif.c      |  8 ++++----
- drivers/clk/mediatek/clk-mt7622.c          | 14 ++++++-------
- drivers/clk/mediatek/clk-mt7629-eth.c      |  7 ++++---
- drivers/clk/mediatek/clk-mt7629-hif.c      |  8 ++++----
- drivers/clk/mediatek/clk-mt7629.c          | 10 +++++-----
- drivers/clk/mediatek/clk-mt7986-eth.c      | 10 +++++-----
- drivers/clk/mediatek/clk-mt7986-infracfg.c |  4 ++--
- 19 files changed, 68 insertions(+), 81 deletions(-)
-
---- a/drivers/clk/mediatek/clk-gate.c
-+++ b/drivers/clk/mediatek/clk-gate.c
-@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
- };
- EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
- 
--static struct clk_hw *mtk_clk_register_gate(const char *name,
-+static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
- 					 const char *parent_name,
- 					 struct regmap *regmap, int set_ofs,
- 					 int clr_ofs, int sta_ofs, u8 bit,
- 					 const struct clk_ops *ops,
--					 unsigned long flags, struct device *dev)
-+					 unsigned long flags)
- {
- 	struct mtk_clk_gate *cg;
- 	int ret;
-@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
- 	kfree(cg);
- }
- 
--int mtk_clk_register_gates_with_dev(struct device_node *node,
--				    const struct mtk_gate *clks, int num,
--				    struct clk_hw_onecell_data *clk_data,
--				    struct device *dev)
-+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
-+			   const struct mtk_gate *clks, int num,
-+			   struct clk_hw_onecell_data *clk_data)
- {
- 	int i;
- 	struct clk_hw *hw;
-@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
- 			continue;
- 		}
- 
--		hw = mtk_clk_register_gate(gate->name, gate->parent_name,
-+		hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
- 					    regmap,
- 					    gate->regs->set_ofs,
- 					    gate->regs->clr_ofs,
- 					    gate->regs->sta_ofs,
- 					    gate->shift, gate->ops,
--					    gate->flags, dev);
-+					    gate->flags);
- 
- 		if (IS_ERR(hw)) {
- 			pr_err("Failed to register clk %s: %pe\n", gate->name,
-@@ -261,14 +260,6 @@ err:
- 
- 	return PTR_ERR(hw);
- }
--EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
--
--int mtk_clk_register_gates(struct device_node *node,
--			   const struct mtk_gate *clks, int num,
--			   struct clk_hw_onecell_data *clk_data)
--{
--	return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
--}
- EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
- 
- void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
---- a/drivers/clk/mediatek/clk-gate.h
-+++ b/drivers/clk/mediatek/clk-gate.h
-@@ -50,15 +50,10 @@ struct mtk_gate {
- #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops)		\
- 	GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
- 
--int mtk_clk_register_gates(struct device_node *node,
-+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
- 			   const struct mtk_gate *clks, int num,
- 			   struct clk_hw_onecell_data *clk_data);
- 
--int mtk_clk_register_gates_with_dev(struct device_node *node,
--				    const struct mtk_gate *clks, int num,
--				    struct clk_hw_onecell_data *clk_data,
--				    struct device *dev);
--
- void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
- 			      struct clk_hw_onecell_data *clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt2701-aud.c
-+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
-@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
- 
- 	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
- 
--	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-+			       ARRAY_SIZE(audio_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r) {
---- a/drivers/clk/mediatek/clk-mt2701-eth.c
-+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
-@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
- 
- 	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
- 
--	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
--						clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+			       ARRAY_SIZE(eth_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt2701-g3d.c
-+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
-@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
- 
- 	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
- 
--	mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
-+	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
- 			       clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mt2701-hif.c
-+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
-@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
- 
- 	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
- 
--	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
--						clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
-+			       ARRAY_SIZE(hif_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r) {
---- a/drivers/clk/mediatek/clk-mt2701-mm.c
-+++ b/drivers/clk/mediatek/clk-mt2701-mm.c
-@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
- 
- 	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
- 
--	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
--						clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
-+			       ARRAY_SIZE(mm_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- 				base, &mt2701_clk_lock, clk_data);
- 
--	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
--						clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+			       ARRAY_SIZE(top_clks), clk_data);
- 
- 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- }
-@@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat
- 		}
- 	}
- 
--	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
--						infra_clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+			       ARRAY_SIZE(infra_clks), infra_clk_data);
- 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- 						infra_clk_data);
- 
-@@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
--						clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+			       ARRAY_SIZE(peri_clks), clk_data);
- 
- 	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
- 			&mt2701_clk_lock, clk_data);
---- a/drivers/clk/mediatek/clk-mt2712-mm.c
-+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
-@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
- 
- 	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
- 
--	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
--			clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
-+			       ARRAY_SIZE(mm_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
- 			&mt2712_clk_lock, top_clk_data);
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
- 			&mt2712_clk_lock, top_clk_data);
--	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
--			top_clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+			       ARRAY_SIZE(top_clks), top_clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
- 
-@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
- 
- 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- 
--	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
--			clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+			       ARRAY_SIZE(infra_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
-@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
- 
- 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- 
--	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
--			clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+			       ARRAY_SIZE(peri_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt7622-aud.c
-+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
-@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
- 
- 	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
- 
--	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-+			       ARRAY_SIZE(audio_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r) {
---- a/drivers/clk/mediatek/clk-mt7622-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
-@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
- 
- 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
- 
--	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+			       ARRAY_SIZE(eth_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
- 
- 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
- 
--	mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
-+			       ARRAY_SIZE(sgmii_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt7622-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
-@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
- 
- 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
- 
--	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-+			       ARRAY_SIZE(ssusb_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
- 
- 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
- 
--	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-+			       ARRAY_SIZE(pcie_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- 				  base, &mt7622_clk_lock, clk_data);
- 
--	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+			       ARRAY_SIZE(top_clks), clk_data);
- 
- 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- }
-@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
- 
- 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
- 
--	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+			       ARRAY_SIZE(infra_clks), clk_data);
- 
- 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- 				  clk_data);
-@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
- 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
- 			      clk_data);
- 
--	mtk_clk_register_gates(node, apmixed_clks,
-+	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- 			       ARRAY_SIZE(apmixed_clks), clk_data);
- 
- 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
- 
- 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
- 
--	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+			       ARRAY_SIZE(peri_clks), clk_data);
- 
- 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
- 				    &mt7622_clk_lock, clk_data);
---- a/drivers/clk/mediatek/clk-mt7629-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
-@@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+			       CLK_ETH_NR_CLK, clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
-+			       CLK_SGMII_NR_CLK, clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt7629-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
-@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
- 
- 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
- 
--	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-+			       ARRAY_SIZE(ssusb_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
- 
- 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
- 
--	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-+			       ARRAY_SIZE(pcie_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+			       ARRAY_SIZE(infra_clks), clk_data);
- 
- 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- 				  clk_data);
-@@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+			       ARRAY_SIZE(peri_clks), clk_data);
- 
- 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
- 				    &mt7629_clk_lock, clk_data);
-@@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl
- 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
- 			      clk_data);
- 
--	mtk_clk_register_gates(node, apmixed_clks,
-+	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- 			       ARRAY_SIZE(apmixed_clks), clk_data);
- 
- 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
---- a/drivers/clk/mediatek/clk-mt7986-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
-@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
- 
- 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
- 
--	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
--			       clk_data);
-+	mtk_clk_register_gates(NULL, node, sgmii0_clks,
-+			       ARRAY_SIZE(sgmii0_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
- 
- 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
- 
--	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
--			       clk_data);
-+	mtk_clk_register_gates(NULL, node, sgmii1_clks,
-+			       ARRAY_SIZE(sgmii1_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
-@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
- 
- 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
- 
--	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-+	mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
-@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
- 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- 	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
- 			       &mt7986_clk_lock, clk_data);
--	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
--			       clk_data);
-+	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+			       ARRAY_SIZE(infra_clks), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r) {
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
--					    clk_data, &pdev->dev);
-+	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
-+				   clk_data);
- 	if (r)
- 		goto free_data;
- 
diff --git a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch b/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch
deleted file mode 100644
index 223155c59b..0000000000
--- a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:34 +0100
-Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
- possible
-
-Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
-propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
-Even though runtime pm is unlikely to be used with CPU muxes, this
-helps with code consistency and possibly opens to commonization of
-some mtk_clk_register_(x) functions.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-cpumux.c          | 8 ++++----
- drivers/clk/mediatek/clk-cpumux.h          | 2 +-
- drivers/clk/mediatek/clk-mt2701.c          | 2 +-
- drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
- drivers/clk/mediatek/clk-mt7622.c          | 4 ++--
- drivers/clk/mediatek/clk-mt7629.c          | 4 ++--
- drivers/clk/mediatek/clk-mt8173.c          | 4 ++--
- 7 files changed, 14 insertions(+), 13 deletions(-)
-
---- a/drivers/clk/mediatek/clk-cpumux.c
-+++ b/drivers/clk/mediatek/clk-cpumux.c
-@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
- };
- 
- static struct clk_hw *
--mtk_clk_register_cpumux(const struct mtk_composite *mux,
-+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
- 			struct regmap *regmap)
- {
- 	struct mtk_clk_cpumux *cpumux;
-@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
- 	cpumux->regmap = regmap;
- 	cpumux->hw.init = &init;
- 
--	ret = clk_hw_register(NULL, &cpumux->hw);
-+	ret = clk_hw_register(dev, &cpumux->hw);
- 	if (ret) {
- 		kfree(cpumux);
- 		return ERR_PTR(ret);
-@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
- 	kfree(cpumux);
- }
- 
--int mtk_clk_register_cpumuxes(struct device_node *node,
-+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
- 			      const struct mtk_composite *clks, int num,
- 			      struct clk_hw_onecell_data *clk_data)
- {
-@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
- 			continue;
- 		}
- 
--		hw = mtk_clk_register_cpumux(mux, regmap);
-+		hw = mtk_clk_register_cpumux(dev, mux, regmap);
- 		if (IS_ERR(hw)) {
- 			pr_err("Failed to register clk %s: %pe\n", mux->name,
- 			       hw);
---- a/drivers/clk/mediatek/clk-cpumux.h
-+++ b/drivers/clk/mediatek/clk-cpumux.h
-@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
- struct device_node;
- struct mtk_composite;
- 
--int mtk_clk_register_cpumuxes(struct device_node *node,
-+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
- 			      const struct mtk_composite *clks, int num,
- 			      struct clk_hw_onecell_data *clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -761,7 +761,7 @@ static void __init mtk_infrasys_init_ear
- 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- 						infra_clk_data);
- 
--	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
-+	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
- 				  infra_clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
---- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
-@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
- 	if (ret)
- 		goto free_clk_data;
- 
--	ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
-+	ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
-+					ARRAY_SIZE(cpu_muxes), clk_data);
- 	if (ret)
- 		goto unregister_gates;
- 
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
- 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- 			       ARRAY_SIZE(infra_clks), clk_data);
- 
--	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
--				  clk_data);
-+	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
-+				  ARRAY_SIZE(infra_muxes), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- 				   clk_data);
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -588,8 +588,8 @@ static int mtk_infrasys_init(struct plat
- 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- 			       ARRAY_SIZE(infra_clks), clk_data);
- 
--	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
--				  clk_data);
-+	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
-+				  ARRAY_SIZE(infra_muxes), clk_data);
- 
- 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- 				      clk_data);
---- a/drivers/clk/mediatek/clk-mt8173.c
-+++ b/drivers/clk/mediatek/clk-mt8173.c
-@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
- 						clk_data);
- 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- 
--	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
--				  clk_data);
-+	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
-+				  ARRAY_SIZE(cpu_muxes), clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
diff --git a/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch b/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch
deleted file mode 100644
index eca1b614cd..0000000000
--- a/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:35 +0100
-Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
- composites
-
-Like done for cpumux clocks, propagate struct device for composite
-clocks registered through clk-mtk helpers to be able to get runtime
-pm support for MTK clocks.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: remove parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
- drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
- drivers/clk/mediatek/clk-mt7622.c |  8 +++++---
- drivers/clk/mediatek/clk-mt7629.c |  8 +++++---
- drivers/clk/mediatek/clk-mtk.c    | 11 ++++++-----
- drivers/clk/mediatek/clk-mtk.h    |  3 ++-
- 6 files changed, 32 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -679,8 +679,9 @@ static int mtk_topckgen_init(struct plat
- 	mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
- 								clk_data);
- 
--	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
--				base, &mt2701_clk_lock, clk_data);
-+	mtk_clk_register_composites(&pdev->dev, top_muxes,
-+				    ARRAY_SIZE(top_muxes), base,
-+				    &mt2701_clk_lock, clk_data);
- 
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- 				base, &mt2701_clk_lock, clk_data);
-@@ -905,8 +906,9 @@ static int mtk_pericfg_init(struct platf
- 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- 			       ARRAY_SIZE(peri_clks), clk_data);
- 
--	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
--			&mt2701_clk_lock, clk_data);
-+	mtk_clk_register_composites(&pdev->dev, peri_muxs,
-+				    ARRAY_SIZE(peri_muxs), base,
-+				    &mt2701_clk_lock, clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
- 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
- 			top_clk_data);
- 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
--	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
--			&mt2712_clk_lock, top_clk_data);
-+	mtk_clk_register_composites(&pdev->dev, top_muxes,
-+				    ARRAY_SIZE(top_muxes), base,
-+				    &mt2712_clk_lock, top_clk_data);
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
- 			&mt2712_clk_lock, top_clk_data);
- 	mtk_clk_register_gates(&pdev->dev, node, top_clks,
-@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
- 
- 	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
- 
--	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
--			&mt2712_clk_lock, clk_data);
-+	r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
-+					ARRAY_SIZE(mcu_muxes), base,
-+					&mt2712_clk_lock, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev, "Could not register composites: %d\n", r);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
- 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
- 				 clk_data);
- 
--	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
--				    base, &mt7622_clk_lock, clk_data);
-+	mtk_clk_register_composites(&pdev->dev, top_muxes,
-+				    ARRAY_SIZE(top_muxes), base,
-+				    &mt7622_clk_lock, clk_data);
- 
- 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- 				  base, &mt7622_clk_lock, clk_data);
-@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
- 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- 			       ARRAY_SIZE(peri_clks), clk_data);
- 
--	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
-+	mtk_clk_register_composites(&pdev->dev, peri_muxes,
-+				    ARRAY_SIZE(peri_muxes), base,
- 				    &mt7622_clk_lock, clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -566,8 +566,9 @@ static int mtk_topckgen_init(struct plat
- 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
- 				 clk_data);
- 
--	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
--				    base, &mt7629_clk_lock, clk_data);
-+	mtk_clk_register_composites(&pdev->dev, top_muxes,
-+				    ARRAY_SIZE(top_muxes), base,
-+				    &mt7629_clk_lock, clk_data);
- 
- 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
- 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
-@@ -613,7 +614,8 @@ static int mtk_pericfg_init(struct platf
- 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- 			       ARRAY_SIZE(peri_clks), clk_data);
- 
--	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
-+	mtk_clk_register_composites(&pdev->dev, peri_muxes,
-+				    ARRAY_SIZE(peri_muxes), base,
- 				    &mt7629_clk_lock, clk_data);
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
- }
- EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
- 
--static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
--		void __iomem *base, spinlock_t *lock)
-+static struct clk_hw *mtk_clk_register_composite(struct device *dev,
-+		const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
- {
- 	struct clk_hw *hw;
- 	struct clk_mux *mux = NULL;
-@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
- 		div_ops = &clk_divider_ops;
- 	}
- 
--	hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
-+	hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
- 		mux_hw, mux_ops,
- 		div_hw, div_ops,
- 		gate_hw, gate_ops,
-@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
- 	kfree(mux);
- }
- 
--int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
-+int mtk_clk_register_composites(struct device *dev,
-+				const struct mtk_composite *mcs, int num,
- 				void __iomem *base, spinlock_t *lock,
- 				struct clk_hw_onecell_data *clk_data)
- {
-@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
- 			continue;
- 		}
- 
--		hw = mtk_clk_register_composite(mc, base, lock);
-+		hw = mtk_clk_register_composite(dev, mc, base, lock);
- 
- 		if (IS_ERR(hw)) {
- 			pr_err("Failed to register clk %s: %pe\n", mc->name,
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -149,7 +149,8 @@ struct mtk_composite {
- 		.flags = 0,						\
- 	}
- 
--int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
-+int mtk_clk_register_composites(struct device *dev,
-+				const struct mtk_composite *mcs, int num,
- 				void __iomem *base, spinlock_t *lock,
- 				struct clk_hw_onecell_data *clk_data);
- void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
diff --git a/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch b/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch
deleted file mode 100644
index a50422da58..0000000000
--- a/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:36 +0100
-Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
- mtk-mux
-
-Like done for other clocks, propagate struct device for mtk mux clocks
-registered through clk-mux helpers to enable runtime pm support.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt7986-infracfg.c |  3 ++-
- drivers/clk/mediatek/clk-mt7986-topckgen.c |  3 ++-
- drivers/clk/mediatek/clk-mux.c             | 14 ++++++++------
- drivers/clk/mediatek/clk-mux.h             |  3 ++-
- 4 files changed, 14 insertions(+), 9 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
-@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
- 		return -ENOMEM;
- 
- 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
--	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-+	mtk_clk_register_muxes(&pdev->dev, infra_muxes,
-+			       ARRAY_SIZE(infra_muxes), node,
- 			       &mt7986_clk_lock, clk_data);
- 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- 			       ARRAY_SIZE(infra_clks), clk_data);
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
- 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- 				    clk_data);
- 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
--	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-+	mtk_clk_register_muxes(&pdev->dev, top_muxes,
-+			       ARRAY_SIZE(top_muxes), node,
- 			       &mt7986_clk_lock, clk_data);
- 
- 	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
---- a/drivers/clk/mediatek/clk-mux.c
-+++ b/drivers/clk/mediatek/clk-mux.c
-@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
- };
- EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
- 
--static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
--				 struct regmap *regmap,
--				 spinlock_t *lock)
-+static struct clk_hw *mtk_clk_register_mux(struct device *dev,
-+					   const struct mtk_mux *mux,
-+					   struct regmap *regmap,
-+					   spinlock_t *lock)
- {
- 	struct mtk_clk_mux *clk_mux;
- 	struct clk_init_data init = {};
-@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
- 	clk_mux->lock = lock;
- 	clk_mux->hw.init = &init;
- 
--	ret = clk_hw_register(NULL, &clk_mux->hw);
-+	ret = clk_hw_register(dev, &clk_mux->hw);
- 	if (ret) {
- 		kfree(clk_mux);
- 		return ERR_PTR(ret);
-@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
- 	kfree(mux);
- }
- 
--int mtk_clk_register_muxes(const struct mtk_mux *muxes,
-+int mtk_clk_register_muxes(struct device *dev,
-+			   const struct mtk_mux *muxes,
- 			   int num, struct device_node *node,
- 			   spinlock_t *lock,
- 			   struct clk_hw_onecell_data *clk_data)
-@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
- 			continue;
- 		}
- 
--		hw = mtk_clk_register_mux(mux, regmap, lock);
-+		hw = mtk_clk_register_mux(dev, mux, regmap, lock);
- 
- 		if (IS_ERR(hw)) {
- 			pr_err("Failed to register clk %s: %pe\n", mux->name,
---- a/drivers/clk/mediatek/clk-mux.h
-+++ b/drivers/clk/mediatek/clk-mux.h
-@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
- 			0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,		\
- 			mtk_mux_clr_set_upd_ops)
- 
--int mtk_clk_register_muxes(const struct mtk_mux *muxes,
-+int mtk_clk_register_muxes(struct device *dev,
-+			   const struct mtk_mux *muxes,
- 			   int num, struct device_node *node,
- 			   spinlock_t *lock,
- 			   struct clk_hw_onecell_data *clk_data);
diff --git a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch
deleted file mode 100644
index de2e6976c3..0000000000
--- a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:37 +0100
-Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
-
-In order to migrate some (few) old clock drivers to the common
-mtk_clk_simple_probe() function, add dummy clock ops to be able
-to insert a dummy clock with ID 0 at the beginning of the list.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
- 2 files changed, 35 insertions(+)
-
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -18,6 +18,22 @@
- #include "clk-mtk.h"
- #include "clk-gate.h"
- 
-+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
-+EXPORT_SYMBOL_GPL(cg_regs_dummy);
-+
-+static int mtk_clk_dummy_enable(struct clk_hw *hw)
-+{
-+	return 0;
-+}
-+
-+static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
-+
-+const struct clk_ops mtk_clk_dummy_ops = {
-+	.enable		= mtk_clk_dummy_enable,
-+	.disable	= mtk_clk_dummy_disable,
-+};
-+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
-+
- static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
- 			      unsigned int clk_num)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -22,6 +22,25 @@
- 
- struct platform_device;
- 
-+/*
-+ * We need the clock IDs to start from zero but to maintain devicetree
-+ * backwards compatibility we can't change bindings to start from zero.
-+ * Only a few platforms are affected, so we solve issues given by the
-+ * commonized MTK clocks probe function(s) by adding a dummy clock at
-+ * the beginning where needed.
-+ */
-+#define CLK_DUMMY		0
-+
-+extern const struct clk_ops mtk_clk_dummy_ops;
-+extern const struct mtk_gate_regs cg_regs_dummy;
-+
-+#define GATE_DUMMY(_id, _name) {				\
-+		.id = _id,					\
-+		.name = _name,					\
-+		.regs = &cg_regs_dummy,				\
-+		.ops = &mtk_clk_dummy_ops,			\
-+	}
-+
- struct mtk_fixed_clk {
- 	int id;
- 	const char *name;
diff --git a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch b/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch
deleted file mode 100644
index becfcd0ed8..0000000000
--- a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch
+++ /dev/null
@@ -1,790 +0,0 @@
-From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:41 +0100
-Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
- possible
-
-mtk_clk_simple_probe() is a function that registers mtk gate clocks
-and, if reset data is present, a reset controller and across all of
-the MTK clock drivers, such a function is duplicated many times:
-switch to the common mtk_clk_simple_probe() function for all of the
-clock drivers that are registering as platform drivers.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
- drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
- drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
- drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
- drivers/clk/mediatek/clk-mt2712.c     | 83 ++++++++++----------------
- drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
- drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
- drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
- drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
- 9 files changed, 144 insertions(+), 406 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt2701-aud.c
-+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
-@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
- };
- 
- static const struct mtk_gate audio_clks[] = {
-+	GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
- 	/* AUDIO0 */
- 	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
- 	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
-@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
- 	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
- };
- 
-+static const struct mtk_clk_desc audio_desc = {
-+	.clks = audio_clks,
-+	.num_clks = ARRAY_SIZE(audio_clks),
-+};
-+
- static const struct of_device_id of_match_clk_mt2701_aud[] = {
--	{ .compatible = "mediatek,mt2701-audsys", },
--	{}
-+	{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
-+	{ /* sentinel */ }
- };
- 
- static int clk_mt2701_aud_probe(struct platform_device *pdev)
- {
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
- 	int r;
- 
--	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
--
--	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
--			       ARRAY_SIZE(audio_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+	r = mtk_clk_simple_probe(pdev);
- 	if (r) {
- 		dev_err(&pdev->dev,
- 			"could not register clock provider: %s: %d\n",
- 			pdev->name, r);
- 
--		goto err_clk_provider;
-+		return r;
- 	}
- 
- 	r = devm_of_platform_populate(&pdev->dev);
-@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
- 	return 0;
- 
- err_plat_populate:
--	of_clk_del_provider(node);
--err_clk_provider:
-+	mtk_clk_simple_remove(pdev);
- 	return r;
- }
- 
-+static int clk_mt2701_aud_remove(struct platform_device *pdev)
-+{
-+	of_platform_depopulate(&pdev->dev);
-+	return mtk_clk_simple_remove(pdev);
-+}
-+
- static struct platform_driver clk_mt2701_aud_drv = {
- 	.probe = clk_mt2701_aud_probe,
-+	.remove = clk_mt2701_aud_remove,
- 	.driver = {
- 		.name = "clk-mt2701-aud",
- 		.of_match_table = of_match_clk_mt2701_aud,
---- a/drivers/clk/mediatek/clk-mt2701-eth.c
-+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
-@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
- 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
- 
- static const struct mtk_gate eth_clks[] = {
-+	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
- 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
- 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
- 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
-@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static const struct of_device_id of_match_clk_mt2701_eth[] = {
--	{ .compatible = "mediatek,mt2701-ethsys", },
--	{}
-+static const struct mtk_clk_desc eth_desc = {
-+	.clks = eth_clks,
-+	.num_clks = ARRAY_SIZE(eth_clks),
-+	.rst_desc = &clk_rst_desc,
- };
- 
--static int clk_mt2701_eth_probe(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	int r;
--	struct device_node *node = pdev->dev.of_node;
--
--	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
--
--	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
--			       ARRAY_SIZE(eth_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return r;
--}
-+static const struct of_device_id of_match_clk_mt2701_eth[] = {
-+	{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
-+	{ /* sentinel */ }
-+};
- 
- static struct platform_driver clk_mt2701_eth_drv = {
--	.probe = clk_mt2701_eth_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt2701-eth",
- 		.of_match_table = of_match_clk_mt2701_eth,
---- a/drivers/clk/mediatek/clk-mt2701-g3d.c
-+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
-@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
- };
- 
- static const struct mtk_gate g3d_clks[] = {
-+	GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
- 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
- };
- 
-@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
--
--	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
--			       clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return r;
--}
-+static const struct mtk_clk_desc g3d_desc = {
-+	.clks = g3d_clks,
-+	.num_clks = ARRAY_SIZE(g3d_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
- static const struct of_device_id of_match_clk_mt2701_g3d[] = {
--	{
--		.compatible = "mediatek,mt2701-g3dsys",
--		.data = clk_mt2701_g3dsys_init,
--	}, {
--		/* sentinel */
--	}
-+	{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
-+	{ /* sentinel */ }
- };
- 
--static int clk_mt2701_g3d_probe(struct platform_device *pdev)
--{
--	int (*clk_init)(struct platform_device *);
--	int r;
--
--	clk_init = of_device_get_match_data(&pdev->dev);
--	if (!clk_init)
--		return -EINVAL;
--
--	r = clk_init(pdev);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	return r;
--}
--
- static struct platform_driver clk_mt2701_g3d_drv = {
--	.probe = clk_mt2701_g3d_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt2701-g3d",
- 		.of_match_table = of_match_clk_mt2701_g3d,
---- a/drivers/clk/mediatek/clk-mt2701-hif.c
-+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
-@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
- 	GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
- 
- static const struct mtk_gate hif_clks[] = {
-+	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
- 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
- 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
- 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
-@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static const struct of_device_id of_match_clk_mt2701_hif[] = {
--	{ .compatible = "mediatek,mt2701-hifsys", },
--	{}
-+static const struct mtk_clk_desc hif_desc = {
-+	.clks = hif_clks,
-+	.num_clks = ARRAY_SIZE(hif_clks),
-+	.rst_desc = &clk_rst_desc,
- };
- 
--static int clk_mt2701_hif_probe(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	int r;
--	struct device_node *node = pdev->dev.of_node;
--
--	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
--
--	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
--			       ARRAY_SIZE(hif_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r) {
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--		return r;
--	}
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return 0;
--}
-+static const struct of_device_id of_match_clk_mt2701_hif[] = {
-+	{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
-+	{ /* sentinel */ }
-+};
- 
- static struct platform_driver clk_mt2701_hif_drv = {
--	.probe = clk_mt2701_hif_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt2701-hif",
- 		.of_match_table = of_match_clk_mt2701_hif,
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
- 	return r;
- }
- 
--static int clk_mt2712_infra_probe(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	int r;
--	struct device_node *node = pdev->dev.of_node;
--
--	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
--			       ARRAY_SIZE(infra_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
--	if (r != 0)
--		pr_err("%s(): could not register clock provider: %d\n",
--			__func__, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
--
--	return r;
--}
--
--static int clk_mt2712_peri_probe(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	int r;
--	struct device_node *node = pdev->dev.of_node;
--
--	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
--			       ARRAY_SIZE(peri_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
--	if (r != 0)
--		pr_err("%s(): could not register clock provider: %d\n",
--			__func__, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
--
--	return r;
--}
--
- static int clk_mt2712_mcu_probe(struct platform_device *pdev)
- {
- 	struct clk_hw_onecell_data *clk_data;
-@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
- 		.compatible = "mediatek,mt2712-topckgen",
- 		.data = clk_mt2712_top_probe,
- 	}, {
--		.compatible = "mediatek,mt2712-infracfg",
--		.data = clk_mt2712_infra_probe,
--	}, {
--		.compatible = "mediatek,mt2712-pericfg",
--		.data = clk_mt2712_peri_probe,
--	}, {
- 		.compatible = "mediatek,mt2712-mcucfg",
- 		.data = clk_mt2712_mcu_probe,
- 	}, {
-@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
- 	return r;
- }
- 
-+static const struct mtk_clk_desc infra_desc = {
-+	.clks = infra_clks,
-+	.num_clks = ARRAY_SIZE(infra_clks),
-+	.rst_desc = &clk_rst_desc[0],
-+};
-+
-+static const struct mtk_clk_desc peri_desc = {
-+	.clks = peri_clks,
-+	.num_clks = ARRAY_SIZE(peri_clks),
-+	.rst_desc = &clk_rst_desc[1],
-+};
-+
-+static const struct of_device_id of_match_clk_mt2712_simple[] = {
-+	{ .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
-+	{ .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
-+	{ /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt2712_simple_drv = {
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+	.driver = {
-+		.name = "clk-mt2712-simple",
-+		.of_match_table = of_match_clk_mt2712_simple,
-+	},
-+};
-+
- static struct platform_driver clk_mt2712_drv = {
- 	.probe = clk_mt2712_probe,
- 	.driver = {
-@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
- 
- static int __init clk_mt2712_init(void)
- {
--	return platform_driver_register(&clk_mt2712_drv);
-+	int ret = platform_driver_register(&clk_mt2712_drv);
-+
-+	if (ret)
-+		return ret;
-+	return platform_driver_register(&clk_mt2712_simple_drv);
- }
- 
- arch_initcall(clk_mt2712_init);
---- a/drivers/clk/mediatek/clk-mt7622-aud.c
-+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
-@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
- 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
- };
- 
--static int clk_mt7622_audiosys_init(struct platform_device *pdev)
-+static const struct mtk_clk_desc audio_desc = {
-+	.clks = audio_clks,
-+	.num_clks = ARRAY_SIZE(audio_clks),
-+};
-+
-+static int clk_mt7622_aud_probe(struct platform_device *pdev)
- {
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
- 	int r;
- 
--	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
--			       ARRAY_SIZE(audio_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+	r = mtk_clk_simple_probe(pdev);
- 	if (r) {
- 		dev_err(&pdev->dev,
- 			"could not register clock provider: %s: %d\n",
- 			pdev->name, r);
- 
--		goto err_clk_provider;
-+		return r;
- 	}
- 
- 	r = devm_of_platform_populate(&pdev->dev);
-@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
- 	return 0;
- 
- err_plat_populate:
--	of_clk_del_provider(node);
--err_clk_provider:
-+	mtk_clk_simple_remove(pdev);
- 	return r;
- }
- 
--static const struct of_device_id of_match_clk_mt7622_aud[] = {
--	{
--		.compatible = "mediatek,mt7622-audsys",
--		.data = clk_mt7622_audiosys_init,
--	}, {
--		/* sentinel */
--	}
--};
--
--static int clk_mt7622_aud_probe(struct platform_device *pdev)
-+static int clk_mt7622_aud_remove(struct platform_device *pdev)
- {
--	int (*clk_init)(struct platform_device *);
--	int r;
--
--	clk_init = of_device_get_match_data(&pdev->dev);
--	if (!clk_init)
--		return -EINVAL;
--
--	r = clk_init(pdev);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	return r;
-+	of_platform_depopulate(&pdev->dev);
-+	return mtk_clk_simple_remove(pdev);
- }
- 
-+static const struct of_device_id of_match_clk_mt7622_aud[] = {
-+	{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
-+	{ /* sentinel */ }
-+};
-+
- static struct platform_driver clk_mt7622_aud_drv = {
- 	.probe = clk_mt7622_aud_probe,
-+	.remove = clk_mt7622_aud_remove,
- 	.driver = {
- 		.name = "clk-mt7622-aud",
- 		.of_match_table = of_match_clk_mt7622_aud,
---- a/drivers/clk/mediatek/clk-mt7622-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
-@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static int clk_mt7622_ethsys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
--			       ARRAY_SIZE(eth_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return r;
--}
--
--static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
--			       ARRAY_SIZE(sgmii_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
-+static const struct mtk_clk_desc eth_desc = {
-+	.clks = eth_clks,
-+	.num_clks = ARRAY_SIZE(eth_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
--	return r;
--}
-+static const struct mtk_clk_desc sgmii_desc = {
-+	.clks = sgmii_clks,
-+	.num_clks = ARRAY_SIZE(sgmii_clks),
-+};
- 
- static const struct of_device_id of_match_clk_mt7622_eth[] = {
--	{
--		.compatible = "mediatek,mt7622-ethsys",
--		.data = clk_mt7622_ethsys_init,
--	}, {
--		.compatible = "mediatek,mt7622-sgmiisys",
--		.data = clk_mt7622_sgmiisys_init,
--	}, {
--		/* sentinel */
--	}
-+	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
-+	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
-+	{ /* sentinel */ }
- };
- 
--static int clk_mt7622_eth_probe(struct platform_device *pdev)
--{
--	int (*clk_init)(struct platform_device *);
--	int r;
--
--	clk_init = of_device_get_match_data(&pdev->dev);
--	if (!clk_init)
--		return -EINVAL;
--
--	r = clk_init(pdev);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	return r;
--}
--
- static struct platform_driver clk_mt7622_eth_drv = {
--	.probe = clk_mt7622_eth_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt7622-eth",
- 		.of_match_table = of_match_clk_mt7622_eth,
---- a/drivers/clk/mediatek/clk-mt7622-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
-@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
--			       ARRAY_SIZE(ssusb_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return r;
--}
--
--static int clk_mt7622_pciesys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
--			       ARRAY_SIZE(pcie_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-+static const struct mtk_clk_desc ssusb_desc = {
-+	.clks = ssusb_clks,
-+	.num_clks = ARRAY_SIZE(ssusb_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
--	return r;
--}
-+static const struct mtk_clk_desc pcie_desc = {
-+	.clks = pcie_clks,
-+	.num_clks = ARRAY_SIZE(pcie_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
- static const struct of_device_id of_match_clk_mt7622_hif[] = {
--	{
--		.compatible = "mediatek,mt7622-pciesys",
--		.data = clk_mt7622_pciesys_init,
--	}, {
--		.compatible = "mediatek,mt7622-ssusbsys",
--		.data = clk_mt7622_ssusbsys_init,
--	}, {
--		/* sentinel */
--	}
-+	{ .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
-+	{ .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
-+	{ /* sentinel */ }
- };
- 
--static int clk_mt7622_hif_probe(struct platform_device *pdev)
--{
--	int (*clk_init)(struct platform_device *);
--	int r;
--
--	clk_init = of_device_get_match_data(&pdev->dev);
--	if (!clk_init)
--		return -EINVAL;
--
--	r = clk_init(pdev);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	return r;
--}
--
- static struct platform_driver clk_mt7622_hif_drv = {
--	.probe = clk_mt7622_hif_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt7622-hif",
- 		.of_match_table = of_match_clk_mt7622_hif,
---- a/drivers/clk/mediatek/clk-mt7629-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
-@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
- 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
- 
--static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
--			       ARRAY_SIZE(ssusb_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
--	return r;
--}
--
--static int clk_mt7629_pciesys_init(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--
--	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
--
--	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
--			       ARRAY_SIZE(pcie_clks), clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-+static const struct mtk_clk_desc ssusb_desc = {
-+	.clks = ssusb_clks,
-+	.num_clks = ARRAY_SIZE(ssusb_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
--	return r;
--}
-+static const struct mtk_clk_desc pcie_desc = {
-+	.clks = pcie_clks,
-+	.num_clks = ARRAY_SIZE(pcie_clks),
-+	.rst_desc = &clk_rst_desc,
-+};
- 
- static const struct of_device_id of_match_clk_mt7629_hif[] = {
--	{
--		.compatible = "mediatek,mt7629-pciesys",
--		.data = clk_mt7629_pciesys_init,
--	}, {
--		.compatible = "mediatek,mt7629-ssusbsys",
--		.data = clk_mt7629_ssusbsys_init,
--	}, {
--		/* sentinel */
--	}
-+	{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
-+	{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
-+	{ /* sentinel */ }
- };
- 
--static int clk_mt7629_hif_probe(struct platform_device *pdev)
--{
--	int (*clk_init)(struct platform_device *);
--	int r;
--
--	clk_init = of_device_get_match_data(&pdev->dev);
--	if (!clk_init)
--		return -EINVAL;
--
--	r = clk_init(pdev);
--	if (r)
--		dev_err(&pdev->dev,
--			"could not register clock provider: %s: %d\n",
--			pdev->name, r);
--
--	return r;
--}
--
- static struct platform_driver clk_mt7629_hif_drv = {
--	.probe = clk_mt7629_hif_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt7629-hif",
- 		.of_match_table = of_match_clk_mt7629_hif,
diff --git a/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch b/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch
deleted file mode 100644
index ad02df10b6..0000000000
--- a/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:42 +0100
-Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
-
-As a preparation to increase probe functions commonization across
-various MediaTek SoC clock controller drivers, extend function
-mtk_clk_simple_probe() to be able to register not only gates, but
-also fixed clocks, factors, muxes and composites.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
- drivers/clk/mediatek/clk-mtk.h |  10 ++++
- 2 files changed, 103 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -11,12 +11,14 @@
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
- 
- #include "clk-mtk.h"
- #include "clk-gate.h"
-+#include "clk-mux.h"
- 
- const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
- EXPORT_SYMBOL_GPL(cg_regs_dummy);
-@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
- 	const struct mtk_clk_desc *mcd;
- 	struct clk_hw_onecell_data *clk_data;
- 	struct device_node *node = pdev->dev.of_node;
--	int r;
-+	void __iomem *base;
-+	int num_clks, r;
- 
- 	mcd = of_device_get_match_data(&pdev->dev);
- 	if (!mcd)
- 		return -EINVAL;
- 
--	clk_data = mtk_alloc_clk_data(mcd->num_clks);
-+	/* Composite clocks needs us to pass iomem pointer */
-+	if (mcd->composite_clks) {
-+		if (!mcd->shared_io)
-+			base = devm_platform_ioremap_resource(pdev, 0);
-+		else
-+			base = of_iomap(node, 0);
-+
-+		if (IS_ERR_OR_NULL(base))
-+			return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
-+	}
-+
-+	/* Calculate how many clk_hw_onecell_data entries to allocate */
-+	num_clks = mcd->num_clks + mcd->num_composite_clks;
-+	num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
-+	num_clks += mcd->num_mux_clks;
-+
-+	clk_data = mtk_alloc_clk_data(num_clks);
- 	if (!clk_data)
- 		return -ENOMEM;
- 
--	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
--				   clk_data);
--	if (r)
--		goto free_data;
-+	if (mcd->fixed_clks) {
-+		r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
-+						mcd->num_fixed_clks, clk_data);
-+		if (r)
-+			goto free_data;
-+	}
-+
-+	if (mcd->factor_clks) {
-+		r = mtk_clk_register_factors(mcd->factor_clks,
-+					     mcd->num_factor_clks, clk_data);
-+		if (r)
-+			goto unregister_fixed_clks;
-+	}
-+
-+	if (mcd->mux_clks) {
-+		r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
-+					   mcd->num_mux_clks, node,
-+					   mcd->clk_lock, clk_data);
-+		if (r)
-+			goto unregister_factors;
-+	};
-+
-+	if (mcd->composite_clks) {
-+		/* We don't check composite_lock because it's optional */
-+		r = mtk_clk_register_composites(&pdev->dev,
-+						mcd->composite_clks,
-+						mcd->num_composite_clks,
-+						base, mcd->clk_lock, clk_data);
-+		if (r)
-+			goto unregister_muxes;
-+	}
-+
-+	if (mcd->clks) {
-+		r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
-+					   mcd->num_clks, clk_data);
-+		if (r)
-+			goto unregister_composites;
-+	}
- 
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r)
-@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
- 	return r;
- 
- unregister_clks:
--	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+	if (mcd->clks)
-+		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+unregister_composites:
-+	if (mcd->composite_clks)
-+		mtk_clk_unregister_composites(mcd->composite_clks,
-+					      mcd->num_composite_clks, clk_data);
-+unregister_muxes:
-+	if (mcd->mux_clks)
-+		mtk_clk_unregister_muxes(mcd->mux_clks,
-+					 mcd->num_mux_clks, clk_data);
-+unregister_factors:
-+	if (mcd->factor_clks)
-+		mtk_clk_unregister_factors(mcd->factor_clks,
-+					   mcd->num_factor_clks, clk_data);
-+unregister_fixed_clks:
-+	if (mcd->fixed_clks)
-+		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
-+					      mcd->num_fixed_clks, clk_data);
- free_data:
- 	mtk_free_clk_data(clk_data);
-+	if (mcd->shared_io && base)
-+		iounmap(base);
- 	return r;
- }
- EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
-@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
- 	struct device_node *node = pdev->dev.of_node;
- 
- 	of_clk_del_provider(node);
--	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+	if (mcd->clks)
-+		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+	if (mcd->composite_clks)
-+		mtk_clk_unregister_composites(mcd->composite_clks,
-+					      mcd->num_composite_clks, clk_data);
-+	if (mcd->mux_clks)
-+		mtk_clk_unregister_muxes(mcd->mux_clks,
-+					 mcd->num_mux_clks, clk_data);
-+	if (mcd->factor_clks)
-+		mtk_clk_unregister_factors(mcd->factor_clks,
-+					   mcd->num_factor_clks, clk_data);
-+	if (mcd->fixed_clks)
-+		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
-+					      mcd->num_fixed_clks, clk_data);
- 	mtk_free_clk_data(clk_data);
- 
- 	return 0;
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
- struct mtk_clk_desc {
- 	const struct mtk_gate *clks;
- 	size_t num_clks;
-+	const struct mtk_composite *composite_clks;
-+	size_t num_composite_clks;
-+	const struct mtk_fixed_clk *fixed_clks;
-+	size_t num_fixed_clks;
-+	const struct mtk_fixed_factor *factor_clks;
-+	size_t num_factor_clks;
-+	const struct mtk_mux *mux_clks;
-+	size_t num_mux_clks;
- 	const struct mtk_clk_rst_desc *rst_desc;
-+	spinlock_t *clk_lock;
-+	bool shared_io;
- };
- 
- int mtk_clk_simple_probe(struct platform_device *pdev);
diff --git a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch b/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch
deleted file mode 100644
index bf9a172926..0000000000
--- a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:52 +0100
-Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
- clocks enabled
-
-Instead of calling clk_prepare_enable() on a bunch of clocks at probe
-time, set the CLK_IS_CRITICAL flag to the same as these are required
-to be always on, and this is the right way of achieving that.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
- 1 file changed, 24 insertions(+), 22 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
- 			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
- 			     0x1C0, 10),
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
--			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-+				   f_26m_adc_parents, 0x020, 0x024, 0x028,
-+				   24, 1, 31, 0x1C0, 11,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- 	/* CLK_CFG_3 */
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
--			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
--			     0x1C0, 12),
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
--			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
--			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-+				   dramc_md32_parents, 0x030, 0x034, 0x038,
-+				   0, 1, 7, 0x1C0, 12,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-+				   sysaxi_parents, 0x030, 0x034, 0x038,
-+				   8, 2, 15, 0x1C0, 13,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-+				   sysapb_parents, 0x030, 0x034, 0x038,
-+				   16, 2, 23, 0x1C0, 14,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
- 			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
- 			     31, 0x1C0, 15),
-@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 			     0x1C0, 21),
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
--			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
--			     0x1C0, 22),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-+				   sgm_reg_parents, 0x050, 0x054, 0x058,
-+				   16, 1, 23, 0x1C0, 22,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
- 			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
- 	/* CLK_CFG_6 */
-@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
- 			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
- 			     0x1C0, 27),
- 	/* CLK_CFG_7 */
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
--			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
--			     0x1C0, 28),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-+				   f_26m_adc_parents, 0x070, 0x074, 0x078,
-+				   0, 1, 7, 0x1C0, 28,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
- 			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
- 			       ARRAY_SIZE(top_muxes), node,
- 			       &mt7986_clk_lock, clk_data);
- 
--	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
--	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
--	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
--	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
--	clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
--	clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
--
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 
- 	if (r) {
diff --git a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch b/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch
deleted file mode 100644
index d77b859f00..0000000000
--- a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:53 +0100
-Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
- mtk_clk_simple_probe()
-
-There are no more non-common calls in clk_mt7986_topckgen_probe():
-migrate this driver to mtk_clk_simple_probe().
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
- 1 file changed, 13 insertions(+), 42 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
- 			     0x1C4, 5),
- };
- 
--static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
--{
--	struct clk_hw_onecell_data *clk_data;
--	struct device_node *node = pdev->dev.of_node;
--	int r;
--	void __iomem *base;
--	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
--		 ARRAY_SIZE(top_muxes);
--
--	base = of_iomap(node, 0);
--	if (!base) {
--		pr_err("%s(): ioremap failed\n", __func__);
--		return -ENOMEM;
--	}
--
--	clk_data = mtk_alloc_clk_data(nr);
--	if (!clk_data)
--		return -ENOMEM;
--
--	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
--				    clk_data);
--	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
--	mtk_clk_register_muxes(&pdev->dev, top_muxes,
--			       ARRAY_SIZE(top_muxes), node,
--			       &mt7986_clk_lock, clk_data);
--
--	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
--	if (r) {
--		pr_err("%s(): could not register clock provider: %d\n",
--		       __func__, r);
--		goto free_topckgen_data;
--	}
--	return r;
--
--free_topckgen_data:
--	mtk_free_clk_data(clk_data);
--	return r;
--}
-+static const struct mtk_clk_desc topck_desc = {
-+	.fixed_clks = top_fixed_clks,
-+	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-+	.factor_clks = top_divs,
-+	.num_factor_clks = ARRAY_SIZE(top_divs),
-+	.mux_clks = top_muxes,
-+	.num_mux_clks = ARRAY_SIZE(top_muxes),
-+	.clk_lock = &mt7986_clk_lock,
-+};
- 
- static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
--	{ .compatible = "mediatek,mt7986-topckgen", },
--	{}
-+	{ .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
-+	{ /* sentinel */ }
- };
- 
- static struct platform_driver clk_mt7986_topckgen_drv = {
--	.probe = clk_mt7986_topckgen_probe,
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
- 	.driver = {
- 		.name = "clk-mt7986-topckgen",
- 		.of_match_table = of_match_clk_mt7986_topckgen,
diff --git a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch b/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch
deleted file mode 100644
index a47dd4b053..0000000000
--- a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Mon, 6 Mar 2023 15:05:21 +0100
-Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
- critical clock
-
-Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
-flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
-+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
-@@ -42,7 +42,7 @@
- 		 "clkxtal")
- 
- static const struct mtk_pll_data plls[] = {
--	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
-+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
- 	    0x0200, 4, 0, 0x0204, 0),
- 	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
- 	    0x0210, 4, 0, 0x0214, 0),
-@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
- 
- 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
- 
--	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
--
- 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- 	if (r) {
- 		pr_err("%s(): could not register clock provider: %d\n",
diff --git a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch b/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch
deleted file mode 100644
index ae76940e1d..0000000000
--- a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch
+++ /dev/null
@@ -1,237 +0,0 @@
-From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:34:05 +0000
-Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
-
-Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
-infracfg, and ethernet subsystem clocks.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../dt-bindings/clock/mediatek,mt7981-clk.h   | 215 ++++++++++++++++++
- 1 file changed, 215 insertions(+)
- create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
-@@ -0,0 +1,215 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7981_H
-+#define _DT_BINDINGS_CLK_MT7981_H
-+
-+/* TOPCKGEN */
-+#define CLK_TOP_CB_CKSQ_40M		0
-+#define CLK_TOP_CB_M_416M		1
-+#define CLK_TOP_CB_M_D2			2
-+#define CLK_TOP_CB_M_D3			3
-+#define CLK_TOP_M_D3_D2			4
-+#define CLK_TOP_CB_M_D4			5
-+#define CLK_TOP_CB_M_D8			6
-+#define CLK_TOP_M_D8_D2			7
-+#define CLK_TOP_CB_MM_720M		8
-+#define CLK_TOP_CB_MM_D2		9
-+#define CLK_TOP_CB_MM_D3		10
-+#define CLK_TOP_CB_MM_D3_D5		11
-+#define CLK_TOP_CB_MM_D4		12
-+#define CLK_TOP_CB_MM_D6		13
-+#define CLK_TOP_MM_D6_D2		14
-+#define CLK_TOP_CB_MM_D8		15
-+#define CLK_TOP_CB_APLL2_196M		16
-+#define CLK_TOP_APLL2_D2		17
-+#define CLK_TOP_APLL2_D4		18
-+#define CLK_TOP_NET1_2500M		19
-+#define CLK_TOP_CB_NET1_D4		20
-+#define CLK_TOP_CB_NET1_D5		21
-+#define CLK_TOP_NET1_D5_D2		22
-+#define CLK_TOP_NET1_D5_D4		23
-+#define CLK_TOP_CB_NET1_D8		24
-+#define CLK_TOP_NET1_D8_D2		25
-+#define CLK_TOP_NET1_D8_D4		26
-+#define CLK_TOP_CB_NET2_800M		27
-+#define CLK_TOP_CB_NET2_D2		28
-+#define CLK_TOP_CB_NET2_D4		29
-+#define CLK_TOP_NET2_D4_D2		30
-+#define CLK_TOP_NET2_D4_D4		31
-+#define CLK_TOP_CB_NET2_D6		32
-+#define CLK_TOP_CB_WEDMCU_208M		33
-+#define CLK_TOP_CB_SGM_325M		34
-+#define CLK_TOP_CKSQ_40M_D2		35
-+#define CLK_TOP_CB_RTC_32K		36
-+#define CLK_TOP_CB_RTC_32P7K		37
-+#define CLK_TOP_USB_TX250M		38
-+#define CLK_TOP_FAUD			39
-+#define CLK_TOP_NFI1X			40
-+#define CLK_TOP_USB_EQ_RX250M		41
-+#define CLK_TOP_USB_CDR_CK		42
-+#define CLK_TOP_USB_LN0_CK		43
-+#define CLK_TOP_SPINFI_BCK		44
-+#define CLK_TOP_SPI			45
-+#define CLK_TOP_SPIM_MST		46
-+#define CLK_TOP_UART_BCK		47
-+#define CLK_TOP_PWM_BCK			48
-+#define CLK_TOP_I2C_BCK			49
-+#define CLK_TOP_PEXTP_TL		50
-+#define CLK_TOP_EMMC_208M		51
-+#define CLK_TOP_EMMC_400M		52
-+#define CLK_TOP_DRAMC_REF		53
-+#define CLK_TOP_DRAMC_MD32		54
-+#define CLK_TOP_SYSAXI			55
-+#define CLK_TOP_SYSAPB			56
-+#define CLK_TOP_ARM_DB_MAIN		57
-+#define CLK_TOP_AP2CNN_HOST		58
-+#define CLK_TOP_NETSYS			59
-+#define CLK_TOP_NETSYS_500M		60
-+#define CLK_TOP_NETSYS_WED_MCU		61
-+#define CLK_TOP_NETSYS_2X		62
-+#define CLK_TOP_SGM_325M		63
-+#define CLK_TOP_SGM_REG			64
-+#define CLK_TOP_F26M			65
-+#define CLK_TOP_EIP97B			66
-+#define CLK_TOP_USB3_PHY		67
-+#define CLK_TOP_AUD			68
-+#define CLK_TOP_A1SYS			69
-+#define CLK_TOP_AUD_L			70
-+#define CLK_TOP_A_TUNER			71
-+#define CLK_TOP_U2U3_REF		72
-+#define CLK_TOP_U2U3_SYS		73
-+#define CLK_TOP_U2U3_XHCI		74
-+#define CLK_TOP_USB_FRMCNT		75
-+#define CLK_TOP_NFI1X_SEL		76
-+#define CLK_TOP_SPINFI_SEL		77
-+#define CLK_TOP_SPI_SEL			78
-+#define CLK_TOP_SPIM_MST_SEL		79
-+#define CLK_TOP_UART_SEL		80
-+#define CLK_TOP_PWM_SEL			81
-+#define CLK_TOP_I2C_SEL			82
-+#define CLK_TOP_PEXTP_TL_SEL		83
-+#define CLK_TOP_EMMC_208M_SEL		84
-+#define CLK_TOP_EMMC_400M_SEL		85
-+#define CLK_TOP_F26M_SEL		86
-+#define CLK_TOP_DRAMC_SEL		87
-+#define CLK_TOP_DRAMC_MD32_SEL		88
-+#define CLK_TOP_SYSAXI_SEL		89
-+#define CLK_TOP_SYSAPB_SEL		90
-+#define CLK_TOP_ARM_DB_MAIN_SEL		91
-+#define CLK_TOP_AP2CNN_HOST_SEL		92
-+#define CLK_TOP_NETSYS_SEL		93
-+#define CLK_TOP_NETSYS_500M_SEL		94
-+#define CLK_TOP_NETSYS_MCU_SEL		95
-+#define CLK_TOP_NETSYS_2X_SEL		96
-+#define CLK_TOP_SGM_325M_SEL		97
-+#define CLK_TOP_SGM_REG_SEL		98
-+#define CLK_TOP_EIP97B_SEL		99
-+#define CLK_TOP_USB3_PHY_SEL		100
-+#define CLK_TOP_AUD_SEL			101
-+#define CLK_TOP_A1SYS_SEL		102
-+#define CLK_TOP_AUD_L_SEL		103
-+#define CLK_TOP_A_TUNER_SEL		104
-+#define CLK_TOP_U2U3_SEL		105
-+#define CLK_TOP_U2U3_SYS_SEL		106
-+#define CLK_TOP_U2U3_XHCI_SEL		107
-+#define CLK_TOP_USB_FRMCNT_SEL		108
-+#define CLK_TOP_AUD_I2S_M		109
-+
-+/* INFRACFG */
-+#define CLK_INFRA_66M_MCK		0
-+#define CLK_INFRA_UART0_SEL		1
-+#define CLK_INFRA_UART1_SEL		2
-+#define CLK_INFRA_UART2_SEL		3
-+#define CLK_INFRA_SPI0_SEL		4
-+#define CLK_INFRA_SPI1_SEL		5
-+#define CLK_INFRA_SPI2_SEL		6
-+#define CLK_INFRA_PWM1_SEL		7
-+#define CLK_INFRA_PWM2_SEL		8
-+#define CLK_INFRA_PWM3_SEL		9
-+#define CLK_INFRA_PWM_BSEL		10
-+#define CLK_INFRA_PCIE_SEL		11
-+#define CLK_INFRA_GPT_STA		12
-+#define CLK_INFRA_PWM_HCK		13
-+#define CLK_INFRA_PWM_STA		14
-+#define CLK_INFRA_PWM1_CK		15
-+#define CLK_INFRA_PWM2_CK		16
-+#define CLK_INFRA_PWM3_CK		17
-+#define CLK_INFRA_CQ_DMA_CK		18
-+#define CLK_INFRA_AUD_BUS_CK		19
-+#define CLK_INFRA_AUD_26M_CK		20
-+#define CLK_INFRA_AUD_L_CK		21
-+#define CLK_INFRA_AUD_AUD_CK		22
-+#define CLK_INFRA_AUD_EG2_CK		23
-+#define CLK_INFRA_DRAMC_26M_CK		24
-+#define CLK_INFRA_DBG_CK		25
-+#define CLK_INFRA_AP_DMA_CK		26
-+#define CLK_INFRA_SEJ_CK		27
-+#define CLK_INFRA_SEJ_13M_CK		28
-+#define CLK_INFRA_THERM_CK		29
-+#define CLK_INFRA_I2C0_CK		30
-+#define CLK_INFRA_UART0_CK		31
-+#define CLK_INFRA_UART1_CK		32
-+#define CLK_INFRA_UART2_CK		33
-+#define CLK_INFRA_SPI2_CK		34
-+#define CLK_INFRA_SPI2_HCK_CK		35
-+#define CLK_INFRA_NFI1_CK		36
-+#define CLK_INFRA_SPINFI1_CK		37
-+#define CLK_INFRA_NFI_HCK_CK		38
-+#define CLK_INFRA_SPI0_CK		39
-+#define CLK_INFRA_SPI1_CK		40
-+#define CLK_INFRA_SPI0_HCK_CK		41
-+#define CLK_INFRA_SPI1_HCK_CK		42
-+#define CLK_INFRA_FRTC_CK		43
-+#define CLK_INFRA_MSDC_CK		44
-+#define CLK_INFRA_MSDC_HCK_CK		45
-+#define CLK_INFRA_MSDC_133M_CK		46
-+#define CLK_INFRA_MSDC_66M_CK		47
-+#define CLK_INFRA_ADC_26M_CK		48
-+#define CLK_INFRA_ADC_FRC_CK		49
-+#define CLK_INFRA_FBIST2FPC_CK		50
-+#define CLK_INFRA_I2C_MCK_CK		51
-+#define CLK_INFRA_I2C_PCK_CK		52
-+#define CLK_INFRA_IUSB_133_CK		53
-+#define CLK_INFRA_IUSB_66M_CK		54
-+#define CLK_INFRA_IUSB_SYS_CK		55
-+#define CLK_INFRA_IUSB_CK		56
-+#define CLK_INFRA_IPCIE_CK		57
-+#define CLK_INFRA_IPCIE_PIPE_CK		58
-+#define CLK_INFRA_IPCIER_CK		59
-+#define CLK_INFRA_IPCIEB_CK		60
-+
-+/* APMIXEDSYS */
-+#define CLK_APMIXED_ARMPLL		0
-+#define CLK_APMIXED_NET2PLL		1
-+#define CLK_APMIXED_MMPLL		2
-+#define CLK_APMIXED_SGMPLL		3
-+#define CLK_APMIXED_WEDMCUPLL		4
-+#define CLK_APMIXED_NET1PLL		5
-+#define CLK_APMIXED_MPLL		6
-+#define CLK_APMIXED_APLL2		7
-+
-+/* SGMIISYS_0 */
-+#define CLK_SGM0_TX_EN			0
-+#define CLK_SGM0_RX_EN			1
-+#define CLK_SGM0_CK0_EN			2
-+#define CLK_SGM0_CDR_CK0_EN		3
-+
-+/* SGMIISYS_1 */
-+#define CLK_SGM1_TX_EN			0
-+#define CLK_SGM1_RX_EN			1
-+#define CLK_SGM1_CK1_EN			2
-+#define CLK_SGM1_CDR_CK1_EN		3
-+
-+/* ETHSYS */
-+#define CLK_ETH_FE_EN			0
-+#define CLK_ETH_GP2_EN			1
-+#define CLK_ETH_GP1_EN			2
-+#define CLK_ETH_WOCPU0_EN		3
-+
-+#endif /* _DT_BINDINGS_CLK_MT7981_H */
diff --git a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch b/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch
deleted file mode 100644
index f9dd94a78a..0000000000
--- a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch
+++ /dev/null
@@ -1,932 +0,0 @@
-From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:34:24 +0000
-Subject: [PATCH] clk: mediatek: add MT7981 clock support
-
-Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
-ethernet subsystem clocks.
-
-The drivers are based on clk-mt7981.c which can be found in MediaTek's
-SDK sources. To be fit for upstream inclusion the driver has been split
-into clock domains and the infracfg part has been significantly
-de-bloated by removing all the 1:1 factors (aliases).
-
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[sboyd@kernel.org: Add module license]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/Kconfig               |  17 +
- drivers/clk/mediatek/Makefile              |   4 +
- drivers/clk/mediatek/clk-mt7981-apmixed.c  | 102 +++++
- drivers/clk/mediatek/clk-mt7981-eth.c      | 118 ++++++
- drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
- drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
- 6 files changed, 870 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
- 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
- 	  to PCI-E and USB.
- 
-+config COMMON_CLK_MT7981
-+	bool "Clock driver for MediaTek MT7981"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7981 basic clocks and clocks
-+	  required for various peripherals found on this SoC.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+	tristate "Clock driver for MediaTek MT7981 ETHSYS"
-+	depends on COMMON_CLK_MT7981
-+	default COMMON_CLK_MT7981
-+	help
-+	  This driver adds support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- 	bool "Clock driver for MediaTek MT7986"
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
-@@ -0,0 +1,102 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-gate.h"
-+#include "clk-mtk.h"
-+#include "clk-mux.h"
-+#include "clk-pll.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+#define MT7981_PLL_FMAX (2500UL * MHZ)
-+#define CON0_MT7981_RST_BAR BIT(27)
-+
-+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-+		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
-+		 _div_table, _parent_name)                                     \
-+	{                                                                      \
-+		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
-+		.en_mask = _en_mask, .flags = _flags,                          \
-+		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
-+		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-+		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
-+		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
-+		.parent_name = _parent_name,                                   \
-+	}
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
-+	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
-+	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
-+		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
-+		 "clkxtal")
-+
-+static const struct mtk_pll_data plls[] = {
-+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-+	    32, 0x0200, 4, 0, 0x0204, 0),
-+	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-+	    0x0210, 4, 0, 0x0214, 0),
-+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-+	    0x0220, 4, 0, 0x0224, 0),
-+	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-+	    0x0230, 4, 0, 0x0234, 0),
-+	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-+	    0x0240, 4, 0, 0x0244, 0),
-+	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-+	    0x0250, 4, 0, 0x0254, 0),
-+	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-+	    0x0260, 4, 0, 0x0264, 0),
-+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-+	    0x0278, 4, 0, 0x027C, 0),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-+	{ .compatible = "mediatek,mt7981-apmixedsys", },
-+	{ /* sentinel */ }
-+};
-+
-+static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-+{
-+	struct clk_hw_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-+	if (!clk_data)
-+		return -ENOMEM;
-+
-+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-+
-+	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+	if (r) {
-+		pr_err("%s(): could not register clock provider: %d\n",
-+		       __func__, r);
-+		goto free_apmixed_data;
-+	}
-+	return r;
-+
-+free_apmixed_data:
-+	mtk_free_clk_data(clk_data);
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7981_apmixed_drv = {
-+	.probe = clk_mt7981_apmixed_probe,
-+	.driver = {
-+		.name = "clk-mt7981-apmixed",
-+		.of_match_table = of_match_clk_mt7981_apmixed,
-+	},
-+};
-+builtin_platform_driver(clk_mt7981_apmixed_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-eth.c
-@@ -0,0 +1,118 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+
-+static const struct mtk_gate_regs sgmii0_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &sgmii0_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate sgmii0_clks[] __initconst = {
-+	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-+	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-+	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-+	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-+};
-+
-+static const struct mtk_gate_regs sgmii1_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &sgmii1_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate sgmii1_clks[] __initconst = {
-+	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-+	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-+	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-+	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-+};
-+
-+static const struct mtk_gate_regs eth_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETH(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &eth_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate eth_clks[] __initconst = {
-+	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-+	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-+	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-+	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-+};
-+
-+static const struct mtk_clk_desc eth_desc = {
-+	.clks = eth_clks,
-+	.num_clks = ARRAY_SIZE(eth_clks),
-+};
-+
-+static const struct mtk_clk_desc sgmii0_desc = {
-+	.clks = sgmii0_clks,
-+	.num_clks = ARRAY_SIZE(sgmii0_clks),
-+};
-+
-+static const struct mtk_clk_desc sgmii1_desc = {
-+	.clks = sgmii1_clks,
-+	.num_clks = ARRAY_SIZE(sgmii1_clks),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_eth[] = {
-+	{ .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
-+	{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
-+	{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
-+	{ /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_eth_drv = {
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+	.driver = {
-+		.name = "clk-mt7981-eth",
-+		.of_match_table = of_match_clk_mt7981_eth,
-+	},
-+};
-+module_platform_driver(clk_mt7981_eth_drv);
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
-@@ -0,0 +1,207 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+static DEFINE_SPINLOCK(mt7981_clk_lock);
-+
-+static const struct mtk_fixed_factor infra_divs[] = {
-+	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-+};
-+
-+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-+								"uart_sel" };
-+
-+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-+							      "spi_sel" };
-+
-+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-+							      "spim_mst_sel" };
-+
-+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-+
-+static const char *const infra_pwm_bsel_parents[] __initconst = {
-+	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-+};
-+
-+static const char *const infra_pcie_parents[] __initconst = {
-+	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-+};
-+
-+static const struct mtk_mux infra_muxes[] = {
-+	/* MODULE_CLK_SEL_0 */
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-+			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-+			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-+			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-+			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-+			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-+			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-+			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-+			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-+			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-+			     -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-+			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-+			     2, -1, -1, -1),
-+	/* MODULE_CLK_SEL_1 */
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-+			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-+			     -1, -1, -1),
-+};
-+
-+static const struct mtk_gate_regs infra0_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra1_cg_regs = {
-+	.set_ofs = 0x50,
-+	.clr_ofs = 0x54,
-+	.sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra2_cg_regs = {
-+	.set_ofs = 0x60,
-+	.clr_ofs = 0x64,
-+	.sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .name = _name, .parent_name = _parent,              \
-+		.regs = &infra0_cg_regs, .shift = _shift,                      \
-+		.ops = &mtk_clk_gate_ops_setclr,                               \
-+	}
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .name = _name, .parent_name = _parent,              \
-+		.regs = &infra1_cg_regs, .shift = _shift,                      \
-+		.ops = &mtk_clk_gate_ops_setclr,                               \
-+	}
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
-+	{                                                                      \
-+		.id = _id, .name = _name, .parent_name = _parent,              \
-+		.regs = &infra2_cg_regs, .shift = _shift,                      \
-+		.ops = &mtk_clk_gate_ops_setclr,                               \
-+	}
-+
-+static const struct mtk_gate infra_clks[] = {
-+	/* INFRA0 */
-+	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-+	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-+	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-+	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-+	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-+	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-+
-+	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-+	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-+	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-+	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-+	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-+	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-+		    14),
-+	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-+	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-+	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-+	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-+	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-+	/* INFRA1 */
-+	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-+	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-+	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-+	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-+	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-+	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-+	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-+	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-+	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-+	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-+	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-+	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-+	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-+		    13),
-+	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-+		    14),
-+	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-+	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-+	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-+	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-+	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-+	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-+	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-+	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-+	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-+	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-+	/* INFRA2 */
-+	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-+	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-+	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-+	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-+	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-+	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-+		    13),
-+	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-+	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-+};
-+
-+static const struct mtk_clk_desc infracfg_desc = {
-+	.factor_clks = infra_divs,
-+	.num_factor_clks = ARRAY_SIZE(infra_divs),
-+	.mux_clks = infra_muxes,
-+	.num_mux_clks = ARRAY_SIZE(infra_muxes),
-+	.clks = infra_clks,
-+	.num_clks = ARRAY_SIZE(infra_clks),
-+	.clk_lock = &mt7981_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-+	{ .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
-+	{ /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_infracfg_drv = {
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+	.driver = {
-+		.name = "clk-mt7981-infracfg",
-+		.of_match_table = of_match_clk_mt7981_infracfg,
-+	},
-+};
-+builtin_platform_driver(clk_mt7981_infracfg_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
-@@ -0,0 +1,422 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ */
-+
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+static DEFINE_SPINLOCK(mt7981_clk_lock);
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-+	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-+	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-+	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-+	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-+	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-+	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-+	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-+	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-+	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-+	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-+	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-+	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-+	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-+	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-+	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-+	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-+	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-+	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-+	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-+	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-+	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-+	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-+	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-+	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-+	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-+	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-+	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-+	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-+	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-+	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-+	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-+	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-+	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-+	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-+	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-+	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-+	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-+	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-+	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-+	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-+	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-+	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-+	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-+	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-+	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-+	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-+	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-+	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-+	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-+	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-+	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-+	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-+	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-+	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-+	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-+	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-+	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-+	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-+	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-+	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-+	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-+	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-+	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-+	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-+	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-+	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-+	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-+	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-+	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-+	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-+	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-+	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-+	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-+	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-+};
-+
-+static const char * const nfi1x_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_mm_d4",
-+	"net1_d8_d2",
-+	"cb_net2_d6",
-+	"cb_m_d4",
-+	"cb_mm_d8",
-+	"net1_d8_d4",
-+	"cb_m_d8"
-+};
-+
-+static const char * const spinfi_parents[] __initconst = {
-+	"cksq_40m_d2",
-+	"cb_cksq_40m",
-+	"net1_d5_d4",
-+	"cb_m_d4",
-+	"cb_mm_d8",
-+	"net1_d8_d4",
-+	"mm_d6_d2",
-+	"cb_m_d8"
-+};
-+
-+static const char * const spi_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_m_d2",
-+	"cb_mm_d4",
-+	"net1_d8_d2",
-+	"cb_net2_d6",
-+	"net1_d5_d4",
-+	"cb_m_d4",
-+	"net1_d8_d4"
-+};
-+
-+static const char * const uart_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_m_d8",
-+	"m_d8_d2"
-+};
-+
-+static const char * const pwm_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d8_d2",
-+	"net1_d5_d4",
-+	"cb_m_d4",
-+	"m_d8_d2",
-+	"cb_rtc_32k"
-+};
-+
-+static const char * const i2c_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d5_d4",
-+	"cb_m_d4",
-+	"net1_d8_d4"
-+};
-+
-+static const char * const pextp_tl_ck_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d5_d4",
-+	"cb_m_d4",
-+	"cb_rtc_32k"
-+};
-+
-+static const char * const emmc_208m_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_m_d2",
-+	"cb_net2_d4",
-+	"cb_apll2_196m",
-+	"cb_mm_d4",
-+	"net1_d8_d2",
-+	"cb_mm_d6"
-+};
-+
-+static const char * const emmc_400m_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net2_d2",
-+	"cb_mm_d2",
-+	"cb_net2_d2"
-+};
-+
-+static const char * const csw_f26m_parents[] __initconst = {
-+	"cksq_40m_d2",
-+	"m_d8_d2"
-+};
-+
-+static const char * const dramc_md32_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_m_d2",
-+	"cb_wedmcu_208m"
-+};
-+
-+static const char * const sysaxi_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d8_d2"
-+};
-+
-+static const char * const sysapb_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"m_d3_d2"
-+};
-+
-+static const char * const arm_db_main_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net2_d6"
-+};
-+
-+static const char * const ap2cnn_host_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d8_d4"
-+};
-+
-+static const char * const netsys_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_mm_d2"
-+};
-+
-+static const char * const netsys_500m_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net1_d5"
-+};
-+
-+static const char * const netsys_mcu_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_mm_720m",
-+	"cb_net1_d4",
-+	"cb_net1_d5",
-+	"cb_m_416m"
-+};
-+
-+static const char * const netsys_2x_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net2_800m",
-+	"cb_mm_720m"
-+};
-+
-+static const char * const sgm_325m_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_sgm_325m"
-+};
-+
-+static const char * const sgm_reg_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net2_d4"
-+};
-+
-+static const char * const eip97b_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_net1_d5",
-+	"cb_m_416m",
-+	"cb_mm_d2",
-+	"net1_d5_d2"
-+};
-+
-+static const char * const aud_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_apll2_196m"
-+};
-+
-+static const char * const a1sys_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"apll2_d4"
-+};
-+
-+static const char * const aud_l_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_apll2_196m",
-+	"m_d8_d2"
-+};
-+
-+static const char * const a_tuner_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"apll2_d4",
-+	"m_d8_d2"
-+};
-+
-+static const char * const u2u3_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"m_d8_d2"
-+};
-+
-+static const char * const u2u3_sys_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"net1_d5_d4"
-+};
-+
-+static const char * const usb_frmcnt_parents[] __initconst = {
-+	"cb_cksq_40m",
-+	"cb_mm_d3_d5"
-+};
-+
-+static const struct mtk_mux top_muxes[] = {
-+	/* CLK_CFG_0 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-+			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-+			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-+			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-+			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-+	/* CLK_CFG_1 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-+			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-+			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-+			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-+			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-+			     0x1C0, 7),
-+	/* CLK_CFG_2 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-+			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-+			     0x1C0, 8),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-+			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-+			     0x1C0, 9),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-+				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-+				   0x1C0, 10,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-+				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-+				   31, 0x1C0, 11,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	/* CLK_CFG_3 */
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-+				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-+				   7, 0x1C0, 12,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-+				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-+				   0x1C0, 13,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-+				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-+				   23, 0x1C0, 14,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-+			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-+			     0x1C0, 15),
-+	/* CLK_CFG_4 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-+			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-+			     0x1C0, 16),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-+			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-+			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-+			     0x1C0, 18),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-+			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-+			     0x1C0, 19),
-+	/* CLK_CFG_5 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-+			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-+			     0x1C0, 20),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-+			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-+			     0x1C0, 21),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-+			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-+			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-+	/* CLK_CFG_6 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-+			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-+			     7, 0x1C0, 24),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-+			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-+			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-+			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-+	/* CLK_CFG_7 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-+			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-+			     0x1C0, 28),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-+			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-+			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-+			     0x1C0, 30),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-+			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-+			     0x1C4, 0),
-+	/* CLK_CFG_8 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-+			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-+			     0x1C4, 1),
-+};
-+
-+static struct mtk_composite top_aud_divs[] = {
-+	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-+		0x0420, 0, 0x0420, 8, 8),
-+};
-+
-+static const struct mtk_clk_desc topck_desc = {
-+	.factor_clks = top_divs,
-+	.num_factor_clks = ARRAY_SIZE(top_divs),
-+	.mux_clks = top_muxes,
-+	.num_mux_clks = ARRAY_SIZE(top_muxes),
-+	.composite_clks = top_aud_divs,
-+	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
-+	.clk_lock = &mt7981_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-+	{ .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
-+	{ /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_topckgen_drv = {
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+	.driver = {
-+		.name = "clk-mt7981-topckgen",
-+		.of_match_table = of_match_clk_mt7981_topckgen,
-+	},
-+};
-+builtin_platform_driver(clk_mt7981_topckgen_drv);
diff --git a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
deleted file mode 100644
index 8820d57f01..0000000000
--- a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 18 Feb 2024 01:59:59 +0000
-Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
-
-Without the SGM_REG_SEL clock enabled the system freezes if trying to
-access registers used by MT7981 clock drivers itself.
-Mark SGM_REG_SEL as critical to make sure it is always enabled to
-prevent freezes on boot depending on probe order.
-
-Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
-@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 			     0x1C0, 21),
--	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
--			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-+				   0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
-+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
- 			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
- 	/* CLK_CFG_6 */
diff --git a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
deleted file mode 100644
index a365f0860b..0000000000
--- a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -141,6 +141,13 @@ config PINCTRL_MT7986
- 	default ARM64 && ARCH_MEDIATEK
- 	select PINCTRL_MTK_MOORE
- 
-+config PINCTRL_MT7988
-+	bool "Mediatek MT7988 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	default ARCH_MEDIATEK
-+	select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- 	bool "Mediatek MT8167 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988)	+= pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
diff --git a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
deleted file mode 100644
index ad4ecdf83f..0000000000
--- a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:33:46 +0000
-Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981
-
-Add compatible string for MT7981 to existing bindings at
- - mediatek,apmixedsys.yaml
- - mediatek,topckgen.yaml
- - mediatek,ethsys.txt
- - mediatek,infracfg.yaml
- - mediatek,sgmiisys.txt
-
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt        | 1 +
- .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml     | 1 +
- .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt      | 2 ++
- .../devicetree/bindings/clock/mediatek,apmixedsys.yaml          | 1 +
- Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml  | 1 +
- 5 files changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-@@ -10,6 +10,7 @@ Required Properties:
- 	- "mediatek,mt7622-ethsys", "syscon"
- 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- 	- "mediatek,mt7629-ethsys", "syscon"
-+	- "mediatek,mt7981-ethsys", "syscon"
- 	- "mediatek,mt7986-ethsys", "syscon"
- - #clock-cells: Must be 1
- - #reset-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-@@ -28,6 +28,7 @@ properties:
-               - mediatek,mt6797-infracfg
-               - mediatek,mt7622-infracfg
-               - mediatek,mt7629-infracfg
-+              - mediatek,mt7981-infracfg
-               - mediatek,mt7986-infracfg
-               - mediatek,mt8135-infracfg
-               - mediatek,mt8167-infracfg
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-@@ -8,6 +8,8 @@ Required Properties:
- - compatible: Should be:
- 	- "mediatek,mt7622-sgmiisys", "syscon"
- 	- "mediatek,mt7629-sgmiisys", "syscon"
-+	- "mediatek,mt7981-sgmiisys_0", "syscon"
-+	- "mediatek,mt7981-sgmiisys_1", "syscon"
- 	- "mediatek,mt7986-sgmiisys_0", "syscon"
- 	- "mediatek,mt7986-sgmiisys_1", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-@@ -20,6 +20,7 @@ properties:
-       - enum:
-           - mediatek,mt6797-apmixedsys
-           - mediatek,mt7622-apmixedsys
-+          - mediatek,mt7981-apmixedsys
-           - mediatek,mt7986-apmixedsys
-           - mediatek,mt8135-apmixedsys
-           - mediatek,mt8173-apmixedsys
---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-@@ -35,6 +35,7 @@ properties:
-               - mediatek,mt6779-topckgen
-               - mediatek,mt6795-topckgen
-               - mediatek,mt7629-topckgen
-+              - mediatek,mt7981-topckgen
-               - mediatek,mt7986-topckgen
-               - mediatek,mt8167-topckgen
-               - mediatek,mt8183-topckgen
diff --git a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
deleted file mode 100644
index 48d3d4e90c..0000000000
--- a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 19 Mar 2023 12:56:52 +0000
-Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
- schema
-
-Convert mediatek,sgmiiisys bindings to DT schema format.
-Add maintainer Matthias Brugger, no maintainers were listed in the
-original documentation.
-As this node is also referenced by the Ethernet controller and used
-as SGMII PCS add this fact to the description.
-Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
-more appropriate given that the great majority of registers are related
-to SGMII PCS functionality and only one register represents clock bits.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- .../arm/mediatek/mediatek,sgmiisys.txt        | 27 ----------
- .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 49 +++++++++++++++++++
- 2 files changed, 49 insertions(+), 27 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
- create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-+++ /dev/null
-@@ -1,27 +0,0 @@
--MediaTek SGMIISYS controller
--============================
--
--The MediaTek SGMIISYS controller provides various clocks to the system.
--
--Required Properties:
--
--- compatible: Should be:
--	- "mediatek,mt7622-sgmiisys", "syscon"
--	- "mediatek,mt7629-sgmiisys", "syscon"
--	- "mediatek,mt7981-sgmiisys_0", "syscon"
--	- "mediatek,mt7981-sgmiisys_1", "syscon"
--	- "mediatek,mt7986-sgmiisys_0", "syscon"
--	- "mediatek,mt7986-sgmiisys_1", "syscon"
--- #clock-cells: Must be 1
--
--The SGMIISYS controller uses the common clk binding from
--Documentation/devicetree/bindings/clock/clock-bindings.txt
--The available clocks are defined in dt-bindings/clock/mt*-clk.h.
--
--Example:
--
--sgmiisys: sgmiisys@1b128000 {
--	compatible = "mediatek,mt7622-sgmiisys", "syscon";
--	reg = <0 0x1b128000 0 0x1000>;
--	#clock-cells = <1>;
--};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -0,0 +1,49 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek SGMIISYS Controller
-+
-+maintainers:
-+  - Matthias Brugger <matthias.bgg@gmail.com>
-+
-+description:
-+  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
-+  to the ethernet subsystem to which it is attached.
-+
-+properties:
-+  compatible:
-+    items:
-+      - enum:
-+          - mediatek,mt7622-sgmiisys
-+          - mediatek,mt7629-sgmiisys
-+          - mediatek,mt7986-sgmiisys_0
-+          - mediatek,mt7986-sgmiisys_1
-+      - const: syscon
-+
-+  reg:
-+    maxItems: 1
-+
-+  '#clock-cells':
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - '#clock-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    soc {
-+      #address-cells = <2>;
-+      #size-cells = <2>;
-+      sgmiisys: syscon@1b128000 {
-+        compatible = "mediatek,mt7622-sgmiisys", "syscon";
-+        reg = <0 0x1b128000 0 0x1000>;
-+        #clock-cells = <1>;
-+      };
-+    };
diff --git a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
deleted file mode 100644
index 62a64b9dd0..0000000000
--- a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 19 Mar 2023 12:57:04 +0000
-Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC
-
-Add mediatek,pnswap boolean property needed on many boards using the
-MediaTek MT7981 SoC.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml      | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -19,6 +19,8 @@ properties:
-       - enum:
-           - mediatek,mt7622-sgmiisys
-           - mediatek,mt7629-sgmiisys
-+          - mediatek,mt7981-sgmiisys_0
-+          - mediatek,mt7981-sgmiisys_1
-           - mediatek,mt7986-sgmiisys_0
-           - mediatek,mt7986-sgmiisys_1
-       - const: syscon
-@@ -29,6 +31,10 @@ properties:
-   '#clock-cells':
-     const: 1
- 
-+  mediatek,pnswap:
-+    description: Invert polarity of the SGMII data lanes
-+    type: boolean
-+
- required:
-   - compatible
-   - reg
diff --git a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
deleted file mode 100644
index 946db82235..0000000000
--- a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Sun, 19 Nov 2023 22:24:16 +0100
-Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
- to DT schema
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-DT schema helps validating DTS files. Binding was moved to clock/ as
-this hardware is a clock provider. Example required a small fix for
-"reg" value (1 address cell + 1 size cell).
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
- .../bindings/clock/mediatek,ethsys.yaml       | 54 +++++++++++++++++++
- 2 files changed, 54 insertions(+), 29 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-+++ /dev/null
-@@ -1,29 +0,0 @@
--Mediatek ethsys controller
--============================
--
--The Mediatek ethsys controller provides various clocks to the system.
--
--Required Properties:
--
--- compatible: Should be:
--	- "mediatek,mt2701-ethsys", "syscon"
--	- "mediatek,mt7622-ethsys", "syscon"
--	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
--	- "mediatek,mt7629-ethsys", "syscon"
--	- "mediatek,mt7981-ethsys", "syscon"
--	- "mediatek,mt7986-ethsys", "syscon"
--- #clock-cells: Must be 1
--- #reset-cells: Must be 1
--
--The ethsys controller uses the common clk binding from
--Documentation/devicetree/bindings/clock/clock-bindings.txt
--The available clocks are defined in dt-bindings/clock/mt*-clk.h.
--
--Example:
--
--ethsys: clock-controller@1b000000 {
--	compatible = "mediatek,mt2701-ethsys", "syscon";
--	reg = <0 0x1b000000 0 0x1000>;
--	#clock-cells = <1>;
--	#reset-cells = <1>;
--};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-@@ -0,0 +1,54 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Mediatek ethsys controller
-+
-+description:
-+  The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+maintainers:
-+  - James Liao <jamesjj.liao@mediatek.com>
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - items:
-+          - enum:
-+              - mediatek,mt2701-ethsys
-+              - mediatek,mt7622-ethsys
-+              - mediatek,mt7629-ethsys
-+              - mediatek,mt7981-ethsys
-+              - mediatek,mt7986-ethsys
-+          - const: syscon
-+      - items:
-+          - const: mediatek,mt7623-ethsys
-+          - const: mediatek,mt2701-ethsys
-+          - const: syscon
-+
-+  reg:
-+    maxItems: 1
-+
-+  "#clock-cells":
-+    const: 1
-+
-+  "#reset-cells":
-+    const: 1
-+
-+required:
-+  - reg
-+  - "#clock-cells"
-+  - "#reset-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    clock-controller@1b000000 {
-+        compatible = "mediatek,mt2701-ethsys", "syscon";
-+        reg = <0x1b000000 0x1000>;
-+        #clock-cells = <1>;
-+        #reset-cells = <1>;
-+    };
diff --git a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
deleted file mode 100644
index 47f05e93c6..0000000000
--- a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 17 Dec 2023 21:49:45 +0000
-Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
- IDs
-
-Add reset ID for ethwarp subsystem allowing to reset the built-in
-Ethernet switch of the MediaTek MT7988 SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
- create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
-+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
-+
-+/* ETHWARP resets */
-+#define MT7988_ETHWARP_RST_SWITCH		0
-+
-+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
diff --git a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
deleted file mode 100644
index cf5cae6341..0000000000
--- a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch
+++ /dev/null
@@ -1,302 +0,0 @@
-From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:49:33 +0000
-Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
-
-Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
-ethernet and xfipll subsystem clocks.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../dt-bindings/clock/mediatek,mt7988-clk.h   | 280 ++++++++++++++++++
- 1 file changed, 280 insertions(+)
- create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
-@@ -0,0 +1,280 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7988_H
-+#define _DT_BINDINGS_CLK_MT7988_H
-+
-+/* APMIXEDSYS */
-+
-+#define CLK_APMIXED_NETSYSPLL			0
-+#define CLK_APMIXED_MPLL			1
-+#define CLK_APMIXED_MMPLL			2
-+#define CLK_APMIXED_APLL2			3
-+#define CLK_APMIXED_NET1PLL			4
-+#define CLK_APMIXED_NET2PLL			5
-+#define CLK_APMIXED_WEDMCUPLL			6
-+#define CLK_APMIXED_SGMPLL			7
-+#define CLK_APMIXED_ARM_B			8
-+#define CLK_APMIXED_CCIPLL2_B			9
-+#define CLK_APMIXED_USXGMIIPLL			10
-+#define CLK_APMIXED_MSDCPLL			11
-+
-+/* TOPCKGEN */
-+
-+#define CLK_TOP_XTAL				0
-+#define CLK_TOP_XTAL_D2				1
-+#define CLK_TOP_RTC_32K				2
-+#define CLK_TOP_RTC_32P7K			3
-+#define CLK_TOP_MPLL_D2				4
-+#define CLK_TOP_MPLL_D3_D2			5
-+#define CLK_TOP_MPLL_D4				6
-+#define CLK_TOP_MPLL_D8				7
-+#define CLK_TOP_MPLL_D8_D2			8
-+#define CLK_TOP_MMPLL_D2			9
-+#define CLK_TOP_MMPLL_D3_D5			10
-+#define CLK_TOP_MMPLL_D4			11
-+#define CLK_TOP_MMPLL_D6_D2			12
-+#define CLK_TOP_MMPLL_D8			13
-+#define CLK_TOP_APLL2_D4			14
-+#define CLK_TOP_NET1PLL_D4			15
-+#define CLK_TOP_NET1PLL_D5			16
-+#define CLK_TOP_NET1PLL_D5_D2			17
-+#define CLK_TOP_NET1PLL_D5_D4			18
-+#define CLK_TOP_NET1PLL_D8			19
-+#define CLK_TOP_NET1PLL_D8_D2			20
-+#define CLK_TOP_NET1PLL_D8_D4			21
-+#define CLK_TOP_NET1PLL_D8_D8			22
-+#define CLK_TOP_NET1PLL_D8_D16			23
-+#define CLK_TOP_NET2PLL_D2			24
-+#define CLK_TOP_NET2PLL_D4			25
-+#define CLK_TOP_NET2PLL_D4_D4			26
-+#define CLK_TOP_NET2PLL_D4_D8			27
-+#define CLK_TOP_NET2PLL_D6			28
-+#define CLK_TOP_NET2PLL_D8			29
-+#define CLK_TOP_NETSYS_SEL			30
-+#define CLK_TOP_NETSYS_500M_SEL			31
-+#define CLK_TOP_NETSYS_2X_SEL			32
-+#define CLK_TOP_NETSYS_GSW_SEL			33
-+#define CLK_TOP_ETH_GMII_SEL			34
-+#define CLK_TOP_NETSYS_MCU_SEL			35
-+#define CLK_TOP_NETSYS_PAO_2X_SEL		36
-+#define CLK_TOP_EIP197_SEL			37
-+#define CLK_TOP_AXI_INFRA_SEL			38
-+#define CLK_TOP_UART_SEL			39
-+#define CLK_TOP_EMMC_250M_SEL			40
-+#define CLK_TOP_EMMC_400M_SEL			41
-+#define CLK_TOP_SPI_SEL				42
-+#define CLK_TOP_SPIM_MST_SEL			43
-+#define CLK_TOP_NFI1X_SEL			44
-+#define CLK_TOP_SPINFI_SEL			45
-+#define CLK_TOP_PWM_SEL				46
-+#define CLK_TOP_I2C_SEL				47
-+#define CLK_TOP_PCIE_MBIST_250M_SEL		48
-+#define CLK_TOP_PEXTP_TL_SEL			49
-+#define CLK_TOP_PEXTP_TL_P1_SEL			50
-+#define CLK_TOP_PEXTP_TL_P2_SEL			51
-+#define CLK_TOP_PEXTP_TL_P3_SEL			52
-+#define CLK_TOP_USB_SYS_SEL			53
-+#define CLK_TOP_USB_SYS_P1_SEL			54
-+#define CLK_TOP_USB_XHCI_SEL			55
-+#define CLK_TOP_USB_XHCI_P1_SEL			56
-+#define CLK_TOP_USB_FRMCNT_SEL			57
-+#define CLK_TOP_USB_FRMCNT_P1_SEL		58
-+#define CLK_TOP_AUD_SEL				59
-+#define CLK_TOP_A1SYS_SEL			60
-+#define CLK_TOP_AUD_L_SEL			61
-+#define CLK_TOP_A_TUNER_SEL			62
-+#define CLK_TOP_SSPXTP_SEL			63
-+#define CLK_TOP_USB_PHY_SEL			64
-+#define CLK_TOP_USXGMII_SBUS_0_SEL		65
-+#define CLK_TOP_USXGMII_SBUS_1_SEL		66
-+#define CLK_TOP_SGM_0_SEL			67
-+#define CLK_TOP_SGM_SBUS_0_SEL			68
-+#define CLK_TOP_SGM_1_SEL			69
-+#define CLK_TOP_SGM_SBUS_1_SEL			70
-+#define CLK_TOP_XFI_PHY_0_XTAL_SEL		71
-+#define CLK_TOP_XFI_PHY_1_XTAL_SEL		72
-+#define CLK_TOP_SYSAXI_SEL			73
-+#define CLK_TOP_SYSAPB_SEL			74
-+#define CLK_TOP_ETH_REFCK_50M_SEL		75
-+#define CLK_TOP_ETH_SYS_200M_SEL		76
-+#define CLK_TOP_ETH_SYS_SEL			77
-+#define CLK_TOP_ETH_XGMII_SEL			78
-+#define CLK_TOP_BUS_TOPS_SEL			79
-+#define CLK_TOP_NPU_TOPS_SEL			80
-+#define CLK_TOP_DRAMC_SEL			81
-+#define CLK_TOP_DRAMC_MD32_SEL			82
-+#define CLK_TOP_INFRA_F26M_SEL			83
-+#define CLK_TOP_PEXTP_P0_SEL			84
-+#define CLK_TOP_PEXTP_P1_SEL			85
-+#define CLK_TOP_PEXTP_P2_SEL			86
-+#define CLK_TOP_PEXTP_P3_SEL			87
-+#define CLK_TOP_DA_XTP_GLB_P0_SEL		88
-+#define CLK_TOP_DA_XTP_GLB_P1_SEL		89
-+#define CLK_TOP_DA_XTP_GLB_P2_SEL		90
-+#define CLK_TOP_DA_XTP_GLB_P3_SEL		91
-+#define CLK_TOP_CKM_SEL				92
-+#define CLK_TOP_DA_SEL				93
-+#define CLK_TOP_PEXTP_SEL			94
-+#define CLK_TOP_TOPS_P2_26M_SEL			95
-+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL		96
-+#define CLK_TOP_NETSYS_SYNC_250M_SEL		97
-+#define CLK_TOP_MACSEC_SEL			98
-+#define CLK_TOP_NETSYS_TOPS_400M_SEL		99
-+#define CLK_TOP_NETSYS_PPEFB_250M_SEL		100
-+#define CLK_TOP_NETSYS_WARP_SEL			101
-+#define CLK_TOP_ETH_MII_SEL			102
-+#define CLK_TOP_NPU_SEL				103
-+#define CLK_TOP_AUD_I2S_M			104
-+
-+/* MCUSYS */
-+
-+#define CLK_MCU_BUS_DIV_SEL			0
-+#define CLK_MCU_ARM_DIV_SEL			1
-+
-+/* INFRACFG_AO */
-+
-+#define CLK_INFRA_MUX_UART0_SEL			0
-+#define CLK_INFRA_MUX_UART1_SEL			1
-+#define CLK_INFRA_MUX_UART2_SEL			2
-+#define CLK_INFRA_MUX_SPI0_SEL			3
-+#define CLK_INFRA_MUX_SPI1_SEL			4
-+#define CLK_INFRA_MUX_SPI2_SEL			5
-+#define CLK_INFRA_PWM_SEL			6
-+#define CLK_INFRA_PWM_CK1_SEL			7
-+#define CLK_INFRA_PWM_CK2_SEL			8
-+#define CLK_INFRA_PWM_CK3_SEL			9
-+#define CLK_INFRA_PWM_CK4_SEL			10
-+#define CLK_INFRA_PWM_CK5_SEL			11
-+#define CLK_INFRA_PWM_CK6_SEL			12
-+#define CLK_INFRA_PWM_CK7_SEL			13
-+#define CLK_INFRA_PWM_CK8_SEL			14
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL	15
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL	16
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL	17
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL	18
-+
-+/* INFRACFG */
-+
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P0		19
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P1		20
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P2		21
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P3		22
-+#define CLK_INFRA_66M_GPT_BCK			23
-+#define CLK_INFRA_66M_PWM_HCK			24
-+#define CLK_INFRA_66M_PWM_BCK			25
-+#define CLK_INFRA_66M_PWM_CK1			26
-+#define CLK_INFRA_66M_PWM_CK2			27
-+#define CLK_INFRA_66M_PWM_CK3			28
-+#define CLK_INFRA_66M_PWM_CK4			29
-+#define CLK_INFRA_66M_PWM_CK5			30
-+#define CLK_INFRA_66M_PWM_CK6			31
-+#define CLK_INFRA_66M_PWM_CK7			32
-+#define CLK_INFRA_66M_PWM_CK8			33
-+#define CLK_INFRA_133M_CQDMA_BCK		34
-+#define CLK_INFRA_66M_AUD_SLV_BCK		35
-+#define CLK_INFRA_AUD_26M			36
-+#define CLK_INFRA_AUD_L				37
-+#define CLK_INFRA_AUD_AUD			38
-+#define CLK_INFRA_AUD_EG2			39
-+#define CLK_INFRA_DRAMC_F26M			40
-+#define CLK_INFRA_133M_DBG_ACKM			41
-+#define CLK_INFRA_66M_AP_DMA_BCK		42
-+#define CLK_INFRA_66M_SEJ_BCK			43
-+#define CLK_INFRA_PRE_CK_SEJ_F13M		44
-+#define CLK_INFRA_26M_THERM_SYSTEM		45
-+#define CLK_INFRA_I2C_BCK			46
-+#define CLK_INFRA_52M_UART0_CK			47
-+#define CLK_INFRA_52M_UART1_CK			48
-+#define CLK_INFRA_52M_UART2_CK			49
-+#define CLK_INFRA_NFI				50
-+#define CLK_INFRA_SPINFI			51
-+#define CLK_INFRA_66M_NFI_HCK			52
-+#define CLK_INFRA_104M_SPI0			53
-+#define CLK_INFRA_104M_SPI1			54
-+#define CLK_INFRA_104M_SPI2_BCK			55
-+#define CLK_INFRA_66M_SPI0_HCK			56
-+#define CLK_INFRA_66M_SPI1_HCK			57
-+#define CLK_INFRA_66M_SPI2_HCK			58
-+#define CLK_INFRA_66M_FLASHIF_AXI		59
-+#define CLK_INFRA_RTC				60
-+#define CLK_INFRA_26M_ADC_BCK			61
-+#define CLK_INFRA_RC_ADC			62
-+#define CLK_INFRA_MSDC400			63
-+#define CLK_INFRA_MSDC2_HCK			64
-+#define CLK_INFRA_133M_MSDC_0_HCK		65
-+#define CLK_INFRA_66M_MSDC_0_HCK		66
-+#define CLK_INFRA_133M_CPUM_BCK			67
-+#define CLK_INFRA_BIST2FPC			68
-+#define CLK_INFRA_I2C_X16W_MCK_CK_P1		69
-+#define CLK_INFRA_I2C_X16W_PCK_CK_P1		70
-+#define CLK_INFRA_133M_USB_HCK			71
-+#define CLK_INFRA_133M_USB_HCK_CK_P1		72
-+#define CLK_INFRA_66M_USB_HCK			73
-+#define CLK_INFRA_66M_USB_HCK_CK_P1		74
-+#define CLK_INFRA_USB_SYS			75
-+#define CLK_INFRA_USB_SYS_CK_P1			76
-+#define CLK_INFRA_USB_REF			77
-+#define CLK_INFRA_USB_CK_P1			78
-+#define CLK_INFRA_USB_FRMCNT			79
-+#define CLK_INFRA_USB_FRMCNT_CK_P1		80
-+#define CLK_INFRA_USB_PIPE			81
-+#define CLK_INFRA_USB_PIPE_CK_P1		82
-+#define CLK_INFRA_USB_UTMI			83
-+#define CLK_INFRA_USB_UTMI_CK_P1		84
-+#define CLK_INFRA_USB_XHCI			85
-+#define CLK_INFRA_USB_XHCI_CK_P1		86
-+#define CLK_INFRA_PCIE_GFMUX_TL_P0		87
-+#define CLK_INFRA_PCIE_GFMUX_TL_P1		88
-+#define CLK_INFRA_PCIE_GFMUX_TL_P2		89
-+#define CLK_INFRA_PCIE_GFMUX_TL_P3		90
-+#define CLK_INFRA_PCIE_PIPE_P0			91
-+#define CLK_INFRA_PCIE_PIPE_P1			92
-+#define CLK_INFRA_PCIE_PIPE_P2			93
-+#define CLK_INFRA_PCIE_PIPE_P3			94
-+#define CLK_INFRA_133M_PCIE_CK_P0		95
-+#define CLK_INFRA_133M_PCIE_CK_P1		96
-+#define CLK_INFRA_133M_PCIE_CK_P2		97
-+#define CLK_INFRA_133M_PCIE_CK_P3		98
-+
-+/* ETHDMA */
-+
-+#define CLK_ETHDMA_XGP1_EN			0
-+#define CLK_ETHDMA_XGP2_EN			1
-+#define CLK_ETHDMA_XGP3_EN			2
-+#define CLK_ETHDMA_FE_EN			3
-+#define CLK_ETHDMA_GP2_EN			4
-+#define CLK_ETHDMA_GP1_EN			5
-+#define CLK_ETHDMA_GP3_EN			6
-+#define CLK_ETHDMA_ESW_EN			7
-+#define CLK_ETHDMA_CRYPT0_EN			8
-+#define CLK_ETHDMA_NR_CLK			9
-+
-+/* SGMIISYS_0 */
-+
-+#define CLK_SGM0_TX_EN				0
-+#define CLK_SGM0_RX_EN				1
-+#define CLK_SGMII0_NR_CLK			2
-+
-+/* SGMIISYS_1 */
-+
-+#define CLK_SGM1_TX_EN				0
-+#define CLK_SGM1_RX_EN				1
-+#define CLK_SGMII1_NR_CLK			2
-+
-+/* ETHWARP */
-+
-+#define CLK_ETHWARP_WOCPU2_EN			0
-+#define CLK_ETHWARP_WOCPU1_EN			1
-+#define CLK_ETHWARP_WOCPU0_EN			2
-+#define CLK_ETHWARP_NR_CLK			3
-+
-+/* XFIPLL */
-+#define CLK_XFIPLL_PLL				0
-+#define CLK_XFIPLL_PLL_EN			1
-+
-+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
deleted file mode 100644
index 79088b461b..0000000000
--- a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch
+++ /dev/null
@@ -1,260 +0,0 @@
-From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 17 Dec 2023 21:49:55 +0000
-Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
- MT7988
-
-Add various clock controllers found in the MT7988 SoC to existing
-bindings (if applicable) and add files for the new ethwarp, mcusys
-and xfi-pll clock controllers not previously present in any SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../arm/mediatek/mediatek,infracfg.yaml       |  1 +
- .../bindings/clock/mediatek,apmixedsys.yaml   |  1 +
- .../bindings/clock/mediatek,ethsys.yaml       |  1 +
- .../clock/mediatek,mt7988-ethwarp.yaml        | 52 +++++++++++++++
- .../clock/mediatek,mt7988-xfi-pll.yaml        | 48 ++++++++++++++
- .../bindings/clock/mediatek,topckgen.yaml     |  2 +
- .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 65 ++++++++++++++++---
- 7 files changed, 161 insertions(+), 9 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-@@ -30,6 +30,7 @@ properties:
-               - mediatek,mt7629-infracfg
-               - mediatek,mt7981-infracfg
-               - mediatek,mt7986-infracfg
-+              - mediatek,mt7988-infracfg
-               - mediatek,mt8135-infracfg
-               - mediatek,mt8167-infracfg
-               - mediatek,mt8173-infracfg
---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-@@ -22,6 +22,7 @@ properties:
-           - mediatek,mt7622-apmixedsys
-           - mediatek,mt7981-apmixedsys
-           - mediatek,mt7986-apmixedsys
-+          - mediatek,mt7988-apmixedsys
-           - mediatek,mt8135-apmixedsys
-           - mediatek,mt8173-apmixedsys
-           - mediatek,mt8516-apmixedsys
---- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-@@ -22,6 +22,7 @@ properties:
-               - mediatek,mt7629-ethsys
-               - mediatek,mt7981-ethsys
-               - mediatek,mt7986-ethsys
-+              - mediatek,mt7988-ethsys
-           - const: syscon
-       - items:
-           - const: mediatek,mt7623-ethsys
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
-@@ -0,0 +1,52 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7988 ethwarp Controller
-+
-+maintainers:
-+  - Daniel Golle <daniel@makrotopia.org>
-+
-+description:
-+  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
-+  Ethernet related subsystems found the MT7988 SoC.
-+  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
-+
-+properties:
-+  compatible:
-+    items:
-+      - const: mediatek,mt7988-ethwarp
-+
-+  reg:
-+    maxItems: 1
-+
-+  '#clock-cells':
-+    const: 1
-+
-+  '#reset-cells':
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - '#clock-cells'
-+  - '#reset-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/reset/ti-syscon.h>
-+    soc {
-+        #address-cells = <2>;
-+        #size-cells = <2>;
-+
-+        clock-controller@15031000 {
-+            compatible = "mediatek,mt7988-ethwarp";
-+            reg = <0 0x15031000 0 0x1000>;
-+            #clock-cells = <1>;
-+            #reset-cells = <1>;
-+        };
-+    };
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
-@@ -0,0 +1,48 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7988 XFI PLL Clock Controller
-+
-+maintainers:
-+  - Daniel Golle <daniel@makrotopia.org>
-+
-+description:
-+  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
-+  Ethernet SerDes PHY from the 40MHz top_xtal clock.
-+
-+properties:
-+  compatible:
-+    const: mediatek,mt7988-xfi-pll
-+
-+  reg:
-+    maxItems: 1
-+
-+  resets:
-+    maxItems: 1
-+
-+  '#clock-cells':
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - resets
-+  - '#clock-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    soc {
-+        #address-cells = <2>;
-+        #size-cells = <2>;
-+        clock-controller@11f40000 {
-+            compatible = "mediatek,mt7988-xfi-pll";
-+            reg = <0 0x11f40000 0 0x1000>;
-+            resets = <&watchdog 16>;
-+            #clock-cells = <1>;
-+        };
-+    };
---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-@@ -37,6 +37,8 @@ properties:
-               - mediatek,mt7629-topckgen
-               - mediatek,mt7981-topckgen
-               - mediatek,mt7986-topckgen
-+              - mediatek,mt7988-mcusys
-+              - mediatek,mt7988-topckgen
-               - mediatek,mt8167-topckgen
-               - mediatek,mt8183-topckgen
-           - const: syscon
---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -15,15 +15,22 @@ description:
- 
- properties:
-   compatible:
--    items:
--      - enum:
--          - mediatek,mt7622-sgmiisys
--          - mediatek,mt7629-sgmiisys
--          - mediatek,mt7981-sgmiisys_0
--          - mediatek,mt7981-sgmiisys_1
--          - mediatek,mt7986-sgmiisys_0
--          - mediatek,mt7986-sgmiisys_1
--      - const: syscon
-+    oneOf:
-+      - items:
-+          - enum:
-+              - mediatek,mt7622-sgmiisys
-+              - mediatek,mt7629-sgmiisys
-+              - mediatek,mt7981-sgmiisys_0
-+              - mediatek,mt7981-sgmiisys_1
-+              - mediatek,mt7986-sgmiisys_0
-+              - mediatek,mt7986-sgmiisys_1
-+          - const: syscon
-+      - items:
-+          - enum:
-+              - mediatek,mt7988-sgmiisys0
-+              - mediatek,mt7988-sgmiisys1
-+          - const: simple-mfd
-+          - const: syscon
- 
-   reg:
-     maxItems: 1
-@@ -35,11 +42,51 @@ properties:
-     description: Invert polarity of the SGMII data lanes
-     type: boolean
- 
-+  pcs:
-+    type: object
-+    description: MediaTek LynxI HSGMII PCS
-+    properties:
-+      compatible:
-+        const: mediatek,mt7988-sgmii
-+
-+      clocks:
-+        maxItems: 3
-+
-+      clock-names:
-+        items:
-+          - const: sgmii_sel
-+          - const: sgmii_tx
-+          - const: sgmii_rx
-+
-+    required:
-+      - compatible
-+      - clocks
-+      - clock-names
-+
-+    additionalProperties: false
-+
- required:
-   - compatible
-   - reg
-   - '#clock-cells'
- 
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - mediatek,mt7988-sgmiisys0
-+              - mediatek,mt7988-sgmiisys1
-+
-+    then:
-+      required:
-+        - pcs
-+
-+    else:
-+      properties:
-+        pcs: false
-+
- additionalProperties: false
- 
- examples:
diff --git a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
deleted file mode 100644
index ca37fc793a..0000000000
--- a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:50:07 +0000
-Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
-
-Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
-of the previously hardcoded PCW_CHG_MASK macro if set.
-This will needed for clocks on the MT7988 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-pll.c | 5 +++--
- drivers/clk/mediatek/clk-pll.h | 1 +
- 2 files changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -23,7 +23,7 @@
- #define CON0_BASE_EN		BIT(0)
- #define CON0_PWR_ON		BIT(0)
- #define CON0_ISO_EN		BIT(1)
--#define PCW_CHG_MASK		BIT(31)
-+#define PCW_CHG_BIT		31
- 
- #define AUDPLL_TUNER_EN		BIT(31)
- 
-@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
- 			pll->data->pcw_shift);
- 	val |= pcw << pll->data->pcw_shift;
- 	writel(val, pll->pcw_addr);
--	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+	chg = readl(pll->pcw_chg_addr) |
-+	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
- 	writel(chg, pll->pcw_chg_addr);
- 	if (pll->tuner_addr)
- 		writel(val + 1, pll->tuner_addr);
---- a/drivers/clk/mediatek/clk-pll.h
-+++ b/drivers/clk/mediatek/clk-pll.h
-@@ -46,6 +46,7 @@ struct mtk_pll_data {
- 	const char *parent_name;
- 	u32 en_reg;
- 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
-+	u8 pcw_chg_bit;
- };
- 
- int mtk_clk_register_plls(struct device_node *node,
diff --git a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
deleted file mode 100644
index 61664b934c..0000000000
--- a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch
+++ /dev/null
@@ -1,1026 +0,0 @@
-From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:50:15 +0000
-Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
-
-Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
-typical MediaTek designs.
-
-Also add driver for XFIPLL clock generating the 156.25MHz clock for
-the XFI SerDes. It needs an undocumented software workaround and has
-an unknown internal design.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
-[sboyd@kernel.org: Add module license to infracfg file]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/Kconfig               |   9 +
- drivers/clk/mediatek/Makefile              |   5 +
- drivers/clk/mediatek/clk-mt7988-apmixed.c  | 114 ++++++++
- drivers/clk/mediatek/clk-mt7988-eth.c      | 150 ++++++++++
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
- drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
- drivers/clk/mediatek/clk-mt7988-xfipll.c   |  82 ++++++
- 7 files changed, 960 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
- 	  This driver adds support for clocks for Ethernet and SGMII
- 	  required on MediaTek MT7986 SoC.
- 
-+config COMMON_CLK_MT7988
-+	tristate "Clock driver for MediaTek MT7988"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	help
-+	  This driver supports MediaTek MT7988 basic clocks and clocks
-+	  required for various periperals found on this SoC.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
-@@ -0,0 +1,114 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include "clk-pll.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+#define MT7988_PLL_FMAX (2500UL * MHZ)
-+#define MT7988_PCW_CHG_BIT 2
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg,	\
-+	    _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift,		\
-+	    _pcw_chg_reg)									\
-+	{											\
-+		.id = _id,									\
-+		.name = _name,									\
-+		.reg = _reg,									\
-+		.pwr_reg = _pwr_reg,								\
-+		.en_mask = _en_mask,								\
-+		.flags = _flags,								\
-+		.rst_bar_mask = BIT(_rst_bar_mask),						\
-+		.fmax = MT7988_PLL_FMAX,							\
-+		.pcwbits = _pcwbits,								\
-+		.pd_reg = _pd_reg,								\
-+		.pd_shift = _pd_shift,								\
-+		.tuner_reg = _tuner_reg,							\
-+		.tuner_en_reg = _tuner_en_reg,							\
-+		.tuner_en_bit = _tuner_en_bit,							\
-+		.pcw_reg = _pcw_reg,								\
-+		.pcw_shift = _pcw_shift,							\
-+		.pcw_chg_reg = _pcw_chg_reg,							\
-+		.pcw_chg_bit = MT7988_PCW_CHG_BIT,						\
-+		.parent_name = "clkxtal",							\
-+	}
-+
-+static const struct mtk_pll_data plls[] = {
-+	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
-+	    0, 0, 0x0108, 0, 0x0104),
-+	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
-+	    0, 0, 0, 0x0118, 0, 0x0114),
-+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
-+	    0, 0, 0, 0x0128, 0, 0x0124),
-+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
-+	    0x0700, 1, 0x0138, 0, 0x0134),
-+	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
-+	    0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-+	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
-+	    32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
-+	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
-+	    0, 0, 0x0168, 0, 0x0164),
-+	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
-+	    0x0178, 0, 0x0174),
-+	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
-+	    0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
-+	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
-+	    0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-+	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
-+	    0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
-+	    0, 0x0318, 0, 0x0314),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-+	{ .compatible = "mediatek,mt7988-apmixedsys" },
-+	{ /* sentinel */ }
-+};
-+
-+static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-+{
-+	struct clk_hw_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-+	if (!clk_data)
-+		return -ENOMEM;
-+
-+	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-+	if (r)
-+		goto free_apmixed_data;
-+
-+	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+	if (r)
-+		goto unregister_plls;
-+
-+	return r;
-+
-+unregister_plls:
-+	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-+free_apmixed_data:
-+	mtk_free_clk_data(clk_data);
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7988_apmixed_drv = {
-+	.probe = clk_mt7988_apmixed_probe,
-+	.driver = {
-+		.name = "clk-mt7988-apmixed",
-+		.of_match_table = of_match_clk_mt7988_apmixed,
-+	},
-+};
-+builtin_platform_driver(clk_mt7988_apmixed_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-eth.c
-@@ -0,0 +1,150 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "reset.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-+
-+static const struct mtk_gate_regs ethdma_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETHDMA(_id, _name, _parent, _shift)		\
-+	{							\
-+		.id = _id,					\
-+		.name = _name,					\
-+		.parent_name = _parent,				\
-+		.regs = &ethdma_cg_regs,			\
-+		.shift = _shift,				\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
-+	}
-+
-+static const struct mtk_gate ethdma_clks[] = {
-+	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-+	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-+	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-+	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-+	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-+	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-+	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-+	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-+	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
-+};
-+
-+static const struct mtk_clk_desc ethdma_desc = {
-+	.clks = ethdma_clks,
-+	.num_clks = ARRAY_SIZE(ethdma_clks),
-+};
-+
-+static const struct mtk_gate_regs sgmii_cg_regs = {
-+	.set_ofs = 0xe4,
-+	.clr_ofs = 0xe4,
-+	.sta_ofs = 0xe4,
-+};
-+
-+#define GATE_SGMII(_id, _name, _parent, _shift)			\
-+	{							\
-+		.id = _id,					\
-+		.name = _name,					\
-+		.parent_name = _parent,				\
-+		.regs = &sgmii_cg_regs,				\
-+		.shift = _shift,				\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
-+	}
-+
-+static const struct mtk_gate sgmii0_clks[] = {
-+	GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-+	GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-+};
-+
-+static const struct mtk_clk_desc sgmii0_desc = {
-+	.clks = sgmii0_clks,
-+	.num_clks = ARRAY_SIZE(sgmii0_clks),
-+};
-+
-+static const struct mtk_gate sgmii1_clks[] = {
-+	GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-+	GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-+};
-+
-+static const struct mtk_clk_desc sgmii1_desc = {
-+	.clks = sgmii1_clks,
-+	.num_clks = ARRAY_SIZE(sgmii1_clks),
-+};
-+
-+static const struct mtk_gate_regs ethwarp_cg_regs = {
-+	.set_ofs = 0x14,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x14,
-+};
-+
-+#define GATE_ETHWARP(_id, _name, _parent, _shift)		\
-+	{							\
-+		.id = _id,					\
-+		.name = _name,					\
-+		.parent_name = _parent,				\
-+		.regs = &ethwarp_cg_regs,			\
-+		.shift = _shift,				\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
-+	}
-+
-+static const struct mtk_gate ethwarp_clks[] = {
-+	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
-+	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
-+	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
-+};
-+
-+static u16 ethwarp_rst_ofs[] = { 0x8 };
-+
-+static u16 ethwarp_idx_map[] = {
-+	[MT7988_ETHWARP_RST_SWITCH] = 9,
-+};
-+
-+static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
-+	.version = MTK_RST_SIMPLE,
-+	.rst_bank_ofs = ethwarp_rst_ofs,
-+	.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
-+	.rst_idx_map = ethwarp_idx_map,
-+	.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
-+};
-+
-+static const struct mtk_clk_desc ethwarp_desc = {
-+	.clks = ethwarp_clks,
-+	.num_clks = ARRAY_SIZE(ethwarp_clks),
-+	.rst_desc = &ethwarp_rst_desc,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_eth[] = {
-+	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
-+	{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
-+	{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
-+	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
-+
-+static struct platform_driver clk_mt7988_eth_drv = {
-+	.driver = {
-+		.name = "clk-mt7988-eth",
-+		.of_match_table = of_match_clk_mt7988_eth,
-+	},
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_eth_drv);
-+
-+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -0,0 +1,275 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+static DEFINE_SPINLOCK(mt7988_clk_lock);
-+
-+static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
-+								   "uart_sel" };
-+
-+static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
-+								   "uart_sel" };
-+
-+static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
-+								   "uart_sel" };
-+
-+static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
-+
-+static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
-+
-+static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
-+								 "csw_infra_f26m_sel", "sysaxi_sel",
-+								 "pwm_sel" };
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
-+};
-+
-+static const struct mtk_mux infra_muxes[] = {
-+	/* MODULE_CLK_SEL_0 */
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-+			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-+			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-+			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
-+			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
-+			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
-+			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
-+			     0x0010, 0x0014, 14, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
-+			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
-+	/* MODULE_CLK_SEL_1 */
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
-+			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
-+			     -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
-+			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
-+			     -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
-+			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
-+			     -1, -1),
-+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
-+			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
-+			     -1, -1),
-+};
-+
-+static const struct mtk_gate_regs infra0_cg_regs = {
-+	.set_ofs = 0x10,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs infra1_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra2_cg_regs = {
-+	.set_ofs = 0x50,
-+	.clr_ofs = 0x54,
-+	.sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra3_cg_regs = {
-+	.set_ofs = 0x60,
-+	.clr_ofs = 0x64,
-+	.sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
-+	GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+		       _flags)
-+
-+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
-+	GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+		       _flags)
-+
-+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
-+	GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+		       _flags)
-+
-+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
-+	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+		       _flags)
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+static const struct mtk_gate infra_clks[] = {
-+	/* INFRA0 */
-+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
-+		    "csw_infra_f26m_sel", 7),
-+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
-+		    "csw_infra_f26m_sel", 8),
-+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
-+		    "csw_infra_f26m_sel", 9),
-+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
-+		    "csw_infra_f26m_sel", 10),
-+	/* INFRA1 */
-+	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
-+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
-+	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
-+	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
-+	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
-+	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-+	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-+	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-+	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
-+			  CLK_IS_CRITICAL),
-+	/* JTAG */
-+	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
-+			  CLK_IS_CRITICAL),
-+	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
-+	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
-+	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
-+	/* INFRA2 */
-+	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
-+		    0),
-+	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-+	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
-+	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
-+	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
-+	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-+	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-+	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
-+			  CLK_IS_CRITICAL),
-+	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
-+			  CLK_IS_CRITICAL),
-+	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
-+	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
-+	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
-+			  CLK_IS_CRITICAL),
-+	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
-+	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
-+	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
-+	GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
-+	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
-+	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
-+	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
-+	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
-+	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
-+	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
-+	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
-+	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-+	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-+	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-+	/* INFRA3 */
-+	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
-+	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
-+	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
-+	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
-+	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-+	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
-+	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-+	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
-+			  CLK_IS_CRITICAL),
-+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
-+			  9, CLK_IS_CRITICAL),
-+	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-+	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
-+	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-+	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
-+	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-+	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
-+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-+		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
-+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-+		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
-+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-+		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
-+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-+		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
-+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
-+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
-+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
-+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
-+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
-+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
-+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
-+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
-+};
-+
-+static const struct mtk_clk_desc infra_desc = {
-+	.clks = infra_clks,
-+	.num_clks = ARRAY_SIZE(infra_clks),
-+	.mux_clks = infra_muxes,
-+	.num_mux_clks = ARRAY_SIZE(infra_muxes),
-+	.clk_lock = &mt7988_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-+	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
-+
-+static struct platform_driver clk_mt7988_infracfg_drv = {
-+	.driver = {
-+		.name = "clk-mt7988-infracfg",
-+		.of_match_table = of_match_clk_mt7988_infracfg,
-+	},
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_infracfg_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
-@@ -0,0 +1,325 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+static DEFINE_SPINLOCK(mt7988_clk_lock);
-+
-+static const struct mtk_fixed_clk top_fixed_clks[] = {
-+	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-+};
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-+	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-+	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-+	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-+	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-+	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-+	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-+	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-+	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-+	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-+	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-+	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-+	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-+	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-+	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-+	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-+	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-+	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-+	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-+	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-+	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-+	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-+	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-+	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-+	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-+	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-+	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-+	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-+};
-+
-+static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
-+static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
-+static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
-+static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
-+static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-+static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",    "mmpll",
-+						  "net1pll_d4", "net1pll_d5", "mpll" };
-+static const char *const eip197_parents[] = { "top_xtal", "netsyspll",	"net2pll",
-+					      "mmpll",	  "net1pll_d4", "net1pll_d5" };
-+static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-+static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
-+static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
-+static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",	 "mmpll_d2",
-+						 "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };
-+static const char *const spi_parents[] = { "top_xtal",	    "mpll_d2",	    "mmpll_d4",
-+					   "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",
-+					   "mpll_d4",	    "net1pll_d8_d4" };
-+static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
-+					     "mpll_d4",	 "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
-+static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
-+					      "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",
-+					      "mmpll_d6_d2", "mpll_d8" };
-+static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
-+					   "mpll_d4",  "mpll_d8_d2",	"top_rtc_32k" };
-+static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
-+					   "net1pll_d8_d4" };
-+static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
-+static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
-+						   "mpll_d8_d2", "top_rtc_32k" };
-+static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-+static const char *const aud_parents[] = { "top_xtal", "apll2" };
-+static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-+static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
-+static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-+static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
-+static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-+static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-+static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
-+static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-+static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
-+static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
-+static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-+static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
-+static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
-+static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
-+static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
-+static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
-+static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
-+
-+static const struct mtk_mux top_muxes[] = {
-+	/* CLK_CFG_0 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
-+			     0, 2, 7, 0x1c0, 0),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
-+			     0x004, 0x008, 8, 2, 15, 0x1C0, 1),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
-+			     0x004, 0x008, 16, 2, 23, 0x1C0, 2),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
-+			     0x004, 0x008, 24, 2, 31, 0x1C0, 3),
-+	/* CLK_CFG_1 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
-+			     0x018, 0, 1, 7, 0x1C0, 4),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
-+			     0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
-+			     0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
-+			     24, 3, 31, 0x1c0, 7),
-+	/* CLK_CFG_2 */
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
-+				   0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
-+			     15, 0x1c0, 9),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
-+			     0x024, 0x028, 16, 2, 23, 0x1C0, 10),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
-+			     0x024, 0x028, 24, 3, 31, 0x1C0, 11),
-+	/* CLK_CFG_3 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
-+			     0x1c0, 12),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
-+			     8, 3, 15, 0x1c0, 13),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
-+			     3, 23, 0x1c0, 14),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
-+			     24, 3, 31, 0x1c0, 15),
-+	/* CLK_CFG_4 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
-+			     0x1c0, 16),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
-+			     0x1c0, 17),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
-+			     pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
-+			     0x044, 0x048, 24, 3, 31, 0x1C0, 19),
-+	/* CLK_CFG_5 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
-+			     0x054, 0x058, 0, 3, 7, 0x1C0, 20),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
-+			     0x054, 0x058, 8, 3, 15, 0x1C0, 21),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
-+			     0x054, 0x058, 16, 3, 23, 0x1C0, 22),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
-+			     0x058, 24, 1, 31, 0x1C0, 23),
-+	/* CLK_CFG_6 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
-+			     0x064, 0x068, 0, 1, 7, 0x1C0, 24),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
-+			     0x068, 8, 1, 15, 0x1C0, 25),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
-+			     0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
-+			     0x064, 0x068, 24, 1, 31, 0x1C0, 27),
-+	/* CLK_CFG_7 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
-+			     0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
-+			     0x1c0, 29),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
-+			     1, 23, 0x1c0, 30),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
-+			     2, 31, 0x1c4, 0),
-+	/* CLK_CFG_8 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
-+			     0, 1, 7, 0x1c4, 1),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
-+			     8, 1, 15, 0x1c4, 2),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
-+			     0x088, 16, 1, 23, 0x1c4, 3),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-+			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
-+	/* CLK_CFG_9 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-+			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
-+			     1, 15, 0x1c4, 6),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
-+				   0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
-+			     1, 31, 0x1c4, 8),
-+	/* CLK_CFG_10 */
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
-+				   0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
-+			     0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
-+			     0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
-+	/* CLK_CFG_11 */
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
-+				   0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
-+				   0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
-+			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
-+			     0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
-+			     0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
-+	/* CLK_CFG_12 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
-+			     0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
-+			     0x0c8, 8, 2, 15, 0x1C4, 18),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
-+			     0x0c8, 16, 1, 23, 0x1C4, 19),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
-+				   0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
-+	/* CLK_CFG_13 */
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
-+				   0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-+				   0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
-+			     0x0d8, 16, 1, 23, 0x1C4, 23),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
-+			     0x0d8, 24, 1, 31, 0x1C4, 24),
-+	/* CLK_CFG_14 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
-+			     0x0e8, 0, 1, 7, 0x1C4, 25),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
-+			     0x0e8, 8, 1, 15, 0x1C4, 26),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
-+			     0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
-+			     0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
-+	/* CLK_CFG_15 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
-+			     0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
-+			     0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
-+			     23, 0x1c8, 0),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
-+			     31, 0x1C8, 1),
-+	/* CLK_CFG_16 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
-+			     0, 1, 7, 0x1c8, 2),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
-+			     0x104, 0x108, 8, 1, 15, 0x1C8, 3),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
-+			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
-+			     pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-+	/* CLK_CFG_17 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
-+			     0, 2, 7, 0x1c8, 6),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
-+			     netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
-+			     pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
-+			     0x114, 0x118, 24, 2, 31, 0x1C8, 9),
-+	/* CLK_CFG_18 */
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
-+			     0x128, 0, 1, 7, 0x1c8, 10),
-+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
-+			     8, 2, 15, 0x1c8, 11),
-+};
-+
-+static const struct mtk_composite top_aud_divs[] = {
-+	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
-+};
-+
-+static const struct mtk_clk_desc topck_desc = {
-+	.fixed_clks = top_fixed_clks,
-+	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-+	.factor_clks = top_divs,
-+	.num_factor_clks = ARRAY_SIZE(top_divs),
-+	.mux_clks = top_muxes,
-+	.num_mux_clks = ARRAY_SIZE(top_muxes),
-+	.composite_clks = top_aud_divs,
-+	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
-+	.clk_lock = &mt7988_clk_lock,
-+};
-+
-+static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
-+
-+static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
-+
-+static struct mtk_composite mcu_muxes[] = {
-+	/* bus_pll_divider_cfg */
-+	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
-+		       CLK_IS_CRITICAL),
-+	/* mp2_pll_divider_cfg */
-+	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
-+		       CLK_IS_CRITICAL),
-+};
-+
-+static const struct mtk_clk_desc mcusys_desc = {
-+	.composite_clks = mcu_muxes,
-+	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-+	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
-+	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
-+
-+static struct platform_driver clk_mt7988_topckgen_drv = {
-+	.probe = mtk_clk_simple_probe,
-+	.remove = mtk_clk_simple_remove,
-+	.driver = {
-+		.name = "clk-mt7988-topckgen",
-+		.of_match_table = of_match_clk_mt7988_topckgen,
-+	},
-+};
-+module_platform_driver(clk_mt7988_topckgen_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
-@@ -0,0 +1,82 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8		0x108
-+#define RG_XFI_PLL_ANA_SWWA		0x02283248
-+
-+static const struct mtk_gate_regs xfipll_cg_regs = {
-+	.set_ofs = 0x8,
-+	.clr_ofs = 0x8,
-+	.sta_ofs = 0x8,
-+};
-+
-+#define GATE_XFIPLL(_id, _name, _parent, _shift)		\
-+	{							\
-+		.id = _id,					\
-+		.name = _name,					\
-+		.parent_name = _parent,				\
-+		.regs = &xfipll_cg_regs,			\
-+		.shift = _shift,				\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
-+	}
-+
-+static const struct mtk_fixed_factor xfipll_divs[] = {
-+	FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
-+};
-+
-+static const struct mtk_gate xfipll_clks[] = {
-+	GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
-+};
-+
-+static const struct mtk_clk_desc xfipll_desc = {
-+	.clks = xfipll_clks,
-+	.num_clks = ARRAY_SIZE(xfipll_clks),
-+	.factor_clks = xfipll_divs,
-+	.num_factor_clks = ARRAY_SIZE(xfipll_divs),
-+};
-+
-+static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
-+{
-+	struct device_node *node = pdev->dev.of_node;
-+	void __iomem *base = of_iomap(node, 0);
-+
-+	if (!base)
-+		return -ENOMEM;
-+
-+	/* Apply software workaround for USXGMII PLL TCL issue */
-+	writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
-+	iounmap(base);
-+
-+	return mtk_clk_simple_probe(pdev);
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
-+	{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
-+
-+static struct platform_driver clk_mt7988_xfipll_drv = {
-+	.driver = {
-+		.name = "clk-mt7988-xfipll",
-+		.of_match_table = of_match_clk_mt7988_xfipll,
-+	},
-+	.probe = clk_mt7988_xfipll_probe,
-+	.remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_xfipll_drv);
-+
-+MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
deleted file mode 100644
index cecf095e92..0000000000
--- a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Wed, 17 Jan 2024 19:41:11 +0100
-Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
-
-Infracfg can also operate as reset controller, add support for it.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -14,6 +14,10 @@
- #include "clk-gate.h"
- #include "clk-mux.h"
- #include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-+
-+#define	MT7988_INFRA_RST0_SET_OFFSET	0x70
-+#define	MT7988_INFRA_RST1_SET_OFFSET	0x80
- 
- static DEFINE_SPINLOCK(mt7988_clk_lock);
- 
-@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
- 	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
- };
- 
-+static u16 infra_rst_ofs[] = {
-+	MT7988_INFRA_RST0_SET_OFFSET,
-+	MT7988_INFRA_RST1_SET_OFFSET,
-+};
-+
-+static u16 infra_idx_map[] = {
-+	[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
-+	[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
-+};
-+
-+static struct mtk_clk_rst_desc infra_rst_desc = {
-+	.version = MTK_RST_SET_CLR,
-+	.rst_bank_ofs = infra_rst_ofs,
-+	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
-+	.rst_idx_map = infra_idx_map,
-+	.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
-+};
-+
- static const struct mtk_clk_desc infra_desc = {
- 	.clks = infra_clks,
- 	.num_clks = ARRAY_SIZE(infra_clks),
- 	.mux_clks = infra_muxes,
- 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
- 	.clk_lock = &mt7988_clk_lock,
-+	.rst_desc = &infra_rst_desc,
- };
- 
- static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
diff --git a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
deleted file mode 100644
index d353074e84..0000000000
--- a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Wed, 17 Jan 2024 19:41:10 +0100
-Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
-
-Add reset constants for using as index in driver and dts.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
-+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
-@@ -10,4 +10,10 @@
- /* ETHWARP resets */
- #define MT7988_ETHWARP_RST_SWITCH		0
- 
-+/* INFRA resets */
-+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST	0
-+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST	1
-+
-+
- #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
-+
diff --git a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
deleted file mode 100644
index cb49ce1d25..0000000000
--- a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch
+++ /dev/null
@@ -1,125 +0,0 @@
-From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 20 Nov 2023 18:22:31 +0000
-Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
-
-Add support for watchdog and reset generator unit of the MediaTek
-MT7988 SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -56,9 +56,13 @@
- #define WDT_SWSYSRST		0x18U
- #define WDT_SWSYS_RST_KEY	0x88000000
- 
-+#define WDT_SWSYSRST_EN		0xfc
-+
- #define DRV_NAME		"mtk-wdt"
- #define DRV_VERSION		"1.0"
- 
-+#define MT7988_TOPRGU_SW_RST_NUM	24
-+
- static bool nowayout = WATCHDOG_NOWAYOUT;
- static unsigned int timeout;
- 
-@@ -68,10 +72,12 @@ struct mtk_wdt_dev {
- 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
- 	struct reset_controller_dev rcdev;
- 	bool disable_wdt_extrst;
-+	bool has_swsysrst_en;
- };
- 
- struct mtk_wdt_data {
- 	int toprgu_sw_rst_num;
-+	bool has_swsysrst_en;
- };
- 
- static const struct mtk_wdt_data mt2712_data = {
-@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_
- 	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
- };
- 
-+static const struct mtk_wdt_data mt7988_data = {
-+	.toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
-+	.has_swsysrst_en = true,
-+};
-+
- static const struct mtk_wdt_data mt8183_data = {
- 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
- };
-@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_
- 	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
- };
- 
-+/**
-+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
-+ * @data: Pointer to instance of driver data.
-+ * @id: Bit number identifying the reset to be enabled or disabled.
-+ * @enable: If true, enable software control for that bit, disable otherwise.
-+ *
-+ * Context: The caller must hold lock of struct mtk_wdt_dev.
-+ */
-+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
-+					unsigned long id, bool enable)
-+{
-+	u32 tmp;
-+
-+	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
-+	if (enable)
-+		tmp |= BIT(id);
-+	else
-+		tmp &= ~BIT(id);
-+
-+	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
-+}
-+
- static int toprgu_reset_update(struct reset_controller_dev *rcdev,
- 			       unsigned long id, bool assert)
- {
-@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re
- 
- 	spin_lock_irqsave(&data->lock, flags);
- 
-+	if (assert && data->has_swsysrst_en)
-+		toprgu_reset_sw_en_unlocked(data, id, true);
-+
- 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
- 	if (assert)
- 		tmp |= BIT(id);
-@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re
- 	tmp |= WDT_SWSYS_RST_KEY;
- 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
- 
-+	if (!assert && data->has_swsysrst_en)
-+		toprgu_reset_sw_en_unlocked(data, id, false);
-+
- 	spin_unlock_irqrestore(&data->lock, flags);
- 
- 	return 0;
-@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform
- 						       wdt_data->toprgu_sw_rst_num);
- 		if (err)
- 			return err;
-+
-+		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
- 	}
- 
- 	mtk_wdt->disable_wdt_extrst =
-@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt
- 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
- 	{ .compatible = "mediatek,mt6589-wdt" },
- 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
-+	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
- 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
- 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
- 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
diff --git a/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch b/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch
deleted file mode 100644
index c4760b9eff..0000000000
--- a/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 11 Mar 2024 17:14:19 +0000
-Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
-
-Due to what seems to be an undocumented oddity in MediaTek's MT7988
-SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
-CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
-
-This currently leads to PCIe port 2 not working in Linux.
-
-Reflect the apparent relationship in the clk driver to make sure PCIe
-port 2 of the MT7988 SoC works.
-
-Suggested-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
- 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
- 		    "csw_infra_f26m_sel", 8),
- 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
--		    "csw_infra_f26m_sel", 9),
-+		    "infra_pcie_peri_ck_26m_ck_p3", 9),
- 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
- 		    "csw_infra_f26m_sel", 10),
- 	/* INFRA1 */
diff --git a/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch b/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch
deleted file mode 100644
index 1e53777d65..0000000000
--- a/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From patchwork Wed Jan 17 12:42:33 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
-X-Patchwork-Id: 13521682
-Return-Path:
- <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
-From: Jean Thomas <jean.thomas@wifirst.fr>
-To: sean.wang@kernel.org,
-	linus.walleij@linaro.org,
-	matthias.bgg@gmail.com,
-	angelogioacchino.delregno@collabora.com,
-	linux-mediatek@lists.infradead.org,
-	linux-gpio@vger.kernel.org,
-	linux-kernel@vger.kernel.org,
-	linux-arm-kernel@lists.infradead.org
-Cc: Jean Thomas <jean.thomas@wifirst.fr>
-Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group
-Date: Wed, 17 Jan 2024 13:42:33 +0100
-Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr>
-MIME-Version: 1.0
-List-Id: <linux-mediatek.lists.infradead.org>
-
-Add uart1_3 (pins 26, 27) group to the pinctrl driver for the
-MediaTek MT7981 SoC.
-
-Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2,
- static int mt7981_uart1_2_pins[] = { 9, 10, };
- static int mt7981_uart1_2_funcs[] = { 2, 2, };
- 
-+static int mt7981_uart1_3_pins[] = { 26, 27, };
-+static int mt7981_uart1_3_funcs[] = { 2, 2, };
-+
- /* UART2 */
- static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
- static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr
- 	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
- 	/* @GPIO(9,10): UART1(2) */
- 	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
-+	/* @GPIO(26,27): UART1(2) */
-+	PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
- 	/* @GPIO(22,25): UART1(3) */
- 	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
- 	/* @GPIO(22,24) PTA_EXT(4) */
-@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr
- static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
- 	"wa_aice3", "wm_aice1_2", };
- static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
--	"net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
-+	"net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0",
- 	"uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
- static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
- static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
diff --git a/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch b/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch
deleted file mode 100644
index df4d82c9d9..0000000000
--- a/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From patchwork Wed Jan 17 14:55:47 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
-X-Patchwork-Id: 13521855
-Return-Path:
- <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
-From: Jean Thomas <jean.thomas@wifirst.fr>
-To: sean.wang@kernel.org,
-	linus.walleij@linaro.org,
-	matthias.bgg@gmail.com,
-	angelogioacchino.delregno@collabora.com,
-	linux-mediatek@lists.infradead.org,
-	linux-gpio@vger.kernel.org,
-	linux-kernel@vger.kernel.org,
-	linux-arm-kernel@lists.infradead.org
-Cc: Jean Thomas <jean.thomas@wifirst.fr>,
-	Daniel Golle <daniel@makrotopia.org>
-Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups
-Date: Wed, 17 Jan 2024 15:55:47 +0100
-Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr>
-List-Id: <linux-mediatek.lists.infradead.org>
-
-Add new emmc groups in the pinctrl driver for the
-MediaTek MT7981 SoC:
-* emmc reset, with pin 15.
-* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25.
-* emmc 8-bit bus-width, with pins 16 to 25.
-
-The existing emmc_45 group is kept for legacy reasons, even
-if this is the union of emmc_reset and emmc_8 groups.
-
-Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++-
- 1 file changed, 16 insertions(+), 1 deletion(-)
-
---
-2.39.2
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14
- static int mt7981_drv_vbus_funcs[] = { 1, };
- 
- /* EMMC */
-+static int mt7981_emmc_reset_pins[] = { 15, };
-+static int mt7981_emmc_reset_funcs[] = { 2, };
-+
-+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
-+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+
-+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+
- static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
- static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
- 
-@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr
- 	PINCTRL_PIN_GROUP("udi", mt7981_udi),
- 	/* @GPIO(14) DRV_VBUS(1) */
- 	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-+	/* @GPIO(15): EMMC_RSTB(2) */
-+	PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
-+	/* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
-+	PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
-+	/* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
-+	PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
- 	/* @GPIO(15,25): EMMC(2) */
- 	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
- 	/* @GPIO(16,21): SNFI(3) */
-@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] =
- static const char *mt7981_pcm_groups[] = { "pcm", };
- static const char *mt7981_udi_groups[] = { "udi", };
- static const char *mt7981_usb_groups[] = { "drv_vbus", };
--static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", };
- static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
- 	"wf0_mode1", "wf0_mode3", "mt7531_int", };
- static const char *mt7981_ant_groups[] = { "ant_sel", };
diff --git a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch
deleted file mode 100644
index 5e3afd856f..0000000000
--- a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 25 Oct 2022 15:29:53 +0200
-Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC
-
-Adding mt7986 own characteristics and of_device_id to have support
-of MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m
- 	.support_64g = false,
- };
- 
-+static const struct mtk_mmc_compatible mt7986_compat = {
-+	.clk_div_bits = 12,
-+	.recheck_sdio_irq = true,
-+	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE0,
-+	.async_fifo = true,
-+	.data_tune = true,
-+	.busy_check = true,
-+	.stop_clk_fix = true,
-+	.enhance_rx = true,
-+	.support_64g = true,
-+};
-+
- static const struct mtk_mmc_compatible mt8135_compat = {
- 	.clk_div_bits = 8,
- 	.recheck_sdio_irq = true,
-@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of
- 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
- 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
- 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
-+	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
- 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
- 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
- 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
diff --git a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch
deleted file mode 100644
index db2802bd0f..0000000000
--- a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001
-From: Mengqi Zhang <mengqi.zhang@mediatek.com>
-Date: Sun, 6 Nov 2022 11:39:24 +0800
-Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control
-
-Add crypto clock control and ungate it before CQHCI init.
-
-Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -452,6 +452,7 @@ struct msdc_host {
- 	struct clk *bus_clk;	/* bus clock which used to access register */
- 	struct clk *src_clk_cg; /* msdc source clock control gate */
- 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
-+	struct clk *crypto_clk; /* msdc crypto clock control gate */
- 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
- 	u32 mclk;		/* mmc subsystem clock frequency */
- 	u32 src_clk_freq;	/* source clock frequency */
-@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct
- static void msdc_gate_clock(struct msdc_host *host)
- {
- 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
-+	clk_disable_unprepare(host->crypto_clk);
- 	clk_disable_unprepare(host->src_clk_cg);
- 	clk_disable_unprepare(host->src_clk);
- 	clk_disable_unprepare(host->bus_clk);
-@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc
- 	clk_prepare_enable(host->bus_clk);
- 	clk_prepare_enable(host->src_clk);
- 	clk_prepare_enable(host->src_clk_cg);
-+	clk_prepare_enable(host->crypto_clk);
- 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
- 	if (ret) {
- 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
-@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor
- 		goto host_free;
- 	}
- 
-+	/* only eMMC has crypto property */
-+	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
-+		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
-+		if (IS_ERR(host->crypto_clk))
-+			host->crypto_clk = NULL;
-+		else
-+			mmc->caps2 |= MMC_CAP2_CRYPTO;
-+	}
-+
- 	host->irq = platform_get_irq(pdev, 0);
- 	if (host->irq < 0) {
- 		ret = host->irq;
diff --git a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch
deleted file mode 100644
index 921d249f8c..0000000000
--- a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001
-From: Yu Zhe <yuzhe@nfschina.com>
-Date: Thu, 10 Nov 2022 15:28:19 +0800
-Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment
-
-spelling mistake fix : "alreay" -> "already"
-		       "checksume" -> "checksum"
-
-Signed-off-by: Yu Zhe <yuzhe@nfschina.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct
- 		else
- 			bd[j].bd_info &= ~BDMA_DESC_EOL;
- 
--		/* checksume need to clear first */
-+		/* checksum need to clear first */
- 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
- 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
- 	}
-@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho
- 		     !host->hs400_tuning))
- 			/*
- 			 * should not clear fifo/interrupt as the tune data
--			 * may have alreay come when cmd19/cmd21 gets response
-+			 * may have already come when cmd19/cmd21 gets response
- 			 * CRC error.
- 			 */
- 			msdc_reset_hw(host);
diff --git a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch
deleted file mode 100644
index 8e2151e16b..0000000000
--- a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001
-From: ChanWoo Lee <cw9316.lee@samsung.com>
-Date: Thu, 24 Nov 2022 17:00:31 +0900
-Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning()
-
-Replace code with the already defined function. No functional changes.
-
-Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com>
-Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
-Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho
- 
- 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
- 		if (events & MSDC_INT_CMDTMO ||
--		    (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
--		     cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
--		     !host->hs400_tuning))
-+		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
- 			/*
- 			 * should not clear fifo/interrupt as the tune data
- 			 * may have already come when cmd19/cmd21 gets response
-@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho
- {
- 	if ((cmd->error &&
- 	    !(cmd->error == -EILSEQ &&
--	      (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
--	       cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
--	       host->hs400_tuning))) ||
-+	      (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
- 	    (mrq->sbc && mrq->sbc->error))
- 		msdc_request_done(host, mrq);
- 	else if (cmd == mrq->sbc)
diff --git a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch
deleted file mode 100644
index 55a308e46c..0000000000
--- a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch
+++ /dev/null
@@ -1,34 +0,0 @@
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -19,6 +19,7 @@
- #include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-+#include <linux/mtd/mtk_bmt.h>
- 
- static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
- {
-@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_attach(mtd);
- 	ret = mtd_device_register(mtd, NULL, 0);
- 	if (ret)
- 		goto err_spinand_cleanup;
-@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
- 	return 0;
- 
- err_spinand_cleanup:
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return ret;
-@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
- 	if (ret)
- 		return ret;
- 
-+	mtk_bmt_detach(mtd);
- 	spinand_cleanup(spinand);
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch
deleted file mode 100644
index a6f98fdf83..0000000000
--- a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -549,6 +549,7 @@
- 		spi-tx-bus-width = <4>;
- 		spi-rx-bus-width = <4>;
- 		nand-ecc-engine = <&snfi>;
-+		mediatek,bmt-v2;
- 
- 		partitions {
- 			compatible = "fixed-partitions";
diff --git a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
deleted file mode 100644
index ec66363dc9..0000000000
--- a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
-From: Davide Fioravanti <pantanastyle@gmail.com>
-Date: Fri, 8 Jan 2021 15:35:24 +0100
-Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
-
-Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
-
-Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
----
- drivers/mtd/nand/spi/Makefile  |  2 +-
- drivers/mtd/nand/spi/core.c    |  1 +
- drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
- include/linux/mtd/spinand.h    |  1 +
- 4 files changed, 79 insertions(+), 1 deletion(-)
- create mode 100644 drivers/mtd/nand/spi/fidelix.c
-
---- a/drivers/mtd/nand/spi/Makefile
-+++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,3 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
--spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
-+spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops
- static const struct spinand_manufacturer *spinand_manufacturers[] = {
- 	&ato_spinand_manufacturer,
- 	&esmt_c8_spinand_manufacturer,
-+	&fidelix_spinand_manufacturer,
- 	&etron_spinand_manufacturer,
- 	&gigadevice_spinand_manufacturer,
- 	&macronix_spinand_manufacturer,
---- /dev/null
-+++ b/drivers/mtd/nand/spi/fidelix.c
-@@ -0,0 +1,76 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#include <linux/mtd/spinand.h>
-+
-+#define SPINAND_MFR_FIDELIX		0xE5
-+#define FIDELIX_ECCSR_MASK		0x0F
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants,
-+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(write_cache_variants,
-+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 8;
-+	region->length = 8;
-+
-+	return 0;
-+}
-+
-+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section > 3)
-+		return -ERANGE;
-+
-+	region->offset = (16 * section) + 2;
-+	region->length = 6;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
-+	.ecc = fm35x1ga_ooblayout_ecc,
-+	.free = fm35x1ga_ooblayout_free,
-+};
-+
-+static const struct spinand_info fidelix_spinand_table[] = {
-+	SPINAND_INFO("FM35X1GA",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(4, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     SPINAND_HAS_QE_BIT,
-+		     SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
-+};
-+
-+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
-+};
-+
-+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
-+	.id = SPINAND_MFR_FIDELIX,
-+	.name = "Fidelix",
-+	.chips = fidelix_spinand_table,
-+	.nchips = ARRAY_SIZE(fidelix_spinand_table),
-+	.ops = &fidelix_spinand_manuf_ops,
-+};
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -263,6 +263,7 @@ struct spinand_manufacturer {
- extern const struct spinand_manufacturer ato_spinand_manufacturer;
- extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
- extern const struct spinand_manufacturer etron_spinand_manufacturer;
-+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
- extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
- extern const struct spinand_manufacturer macronix_spinand_manufacturer;
- extern const struct spinand_manufacturer micron_spinand_manufacturer;
diff --git a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
deleted file mode 100644
index 96bc7cebd0..0000000000
--- a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From patchwork Fri Apr 19 16:59:07 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 13636668
-Return-Path: 
- <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
-Date: Fri, 19 Apr 2024 17:59:07 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: "Rafael J. Wysocki" <rafael@kernel.org>,
-	Viresh Kumar <viresh.kumar@linaro.org>,
-	Matthias Brugger <matthias.bgg@gmail.com>,
-	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-	linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
-	linux-arm-kernel@lists.infradead.org,
-	linux-mediatek@lists.infradead.org
-Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
-Message-ID: 
- <acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
-Content-Disposition: inline
-List-Id: <linux-mediatek.lists.infradead.org>
-
-From: Sam Shih <sam.shih@mediatek.com>
-
-This add cpufreq support for mediatek MT7988A SoC.
-
-The platform data of MT7988A is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform
- 	.ccifreq_supported = false,
- };
- 
-+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
-+	.min_volt_shift = 100000,
-+	.max_volt_shift = 200000,
-+	.proc_max_volt = 900000,
-+	.sram_min_volt = 0,
-+	.sram_max_volt = 1150000,
-+	.ccifreq_supported = true,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- 	.min_volt_shift = 100000,
- 	.max_volt_shift = 200000,
-@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu
- 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- 	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
-+	{ .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
- 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
diff --git a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
deleted file mode 100644
index 1fcb1e64c7..0000000000
--- a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch
+++ /dev/null
@@ -1,99 +0,0 @@
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -601,6 +601,30 @@ out:
- 	return err;
- }
- 
-+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
-+				const struct mtk_pin_desc *desc,
-+				u32 pullup, u32 arg)
-+{
-+    int err, pd;
-+
-+	if (arg == MTK_DISABLE)
-+		pd = 0;
-+	else if ((arg == MTK_ENABLE) && pullup)
-+		pd = 0;
-+	else if ((arg == MTK_ENABLE) && !pullup)
-+		pd = 1;
-+	else {
-+		err = -EINVAL;
-+		goto out;
-+	}
-+
-+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-+
-+out:
-+	return err;
-+
-+}
-+
- static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
- 				const struct mtk_pin_desc *desc,
- 				u32 pullup, u32 arg)
-@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
- 			return err;
- 	}
- 
-+	if (try_all_type & MTK_PULL_PD_TYPE) {
-+		err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
-+		if (!err)
-+			return err;
-+    }
-+
- 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- 		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
- 		if (!err)
-@@ -875,6 +905,29 @@ out:
- 	return err;
- }
- 
-+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
-+				const struct mtk_pin_desc *desc,
-+				u32 *pullup, u32 *enable)
-+{
-+	int err, pd;
-+
-+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+	if (err)
-+		goto out;
-+
-+	if (pd == 0) {
-+		*pullup = 0;
-+		*enable = MTK_DISABLE;
-+	} else if (pd == 1) {
-+		*pullup = 0;
-+		*enable = MTK_ENABLE;
-+	} else
-+		err = -EINVAL;
-+
-+out:
-+	return err;
-+}
-+
- static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
- 				const struct mtk_pin_desc *desc,
- 				u32 *pullup, u32 *enable)
-@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
- 		if (!err)
- 			return err;
- 	}
-+
-+	if (try_all_type & MTK_PULL_PD_TYPE) {
-+		err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
-+		if (!err)
-+			return err;
-+	}
- 
- 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- 		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-@@ -24,6 +24,7 @@
-  * turned on/off itself. But it can't be selected pull up/down
-  */
- #define MTK_PULL_RSEL_TYPE		BIT(3)
-+#define MTK_PULL_PD_TYPE        BIT(4)
- /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
-  * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
-  */
diff --git a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch
deleted file mode 100644
index 25ca9485e4..0000000000
--- a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.c
-+++ b/drivers/crypto/inside-secure/safexcel.c
-@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
- 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
- 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
- 	}
-+	/*
-+	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
-+	 */
-+	else {
-+		val = 0;
-+		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
-+		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
-+	}
- 
- 	/* Configure wr/rd cache values */
- 	writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -315,6 +315,7 @@
- #define EIP197_MST_CTRL_RD_CACHE(n)		(((n) & 0xf) << 0)
- #define EIP197_MST_CTRL_WD_CACHE(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
-+#define EIP97_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
- #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
- #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)
diff --git a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch
deleted file mode 100644
index 186c66f687..0000000000
--- a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -737,6 +737,9 @@ enum safexcel_eip_version {
- /* Priority we use for advertising our algorithms */
- #define SAFEXCEL_CRA_PRIORITY		300
- 
-+/* System cache line size */
-+#define SYSTEM_CACHELINE_SIZE		64
-+
- /* SM3 digest result for zero length message */
- #define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
- 				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
---- a/drivers/crypto/inside-secure/safexcel_hash.c
-+++ b/drivers/crypto/inside-secure/safexcel_hash.c
-@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
- 	u8 block_sz;    /* block size, only set once */
- 	u8 digest_sz;   /* output digest size, only set once */
- 	__le32 state[SHA3_512_BLOCK_SIZE /
--		     sizeof(__le32)] __aligned(sizeof(__le32));
-+		     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
- 
--	u64 len;
-+	u64 len __aligned(SYSTEM_CACHELINE_SIZE);
- 	u64 processed;
- 
- 	u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
diff --git a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch
deleted file mode 100644
index 615a1a1d71..0000000000
--- a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001
-From: "Mingming.Su" <Mingming.Su@mediatek.com>
-Date: Sat, 8 Oct 2022 18:45:53 +0200
-Subject: [PATCH] hwrng: mtk - add mt7986 support
-
-1. Add trng compatible name for MT7986
-2. Fix mtk_rng_wait_ready() function
-
-Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
----
- drivers/char/hw_random/mtk-rng.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/char/hw_random/mtk-rng.c
-+++ b/drivers/char/hw_random/mtk-rng.c
-@@ -22,7 +22,7 @@
- #define RNG_AUTOSUSPEND_TIMEOUT		100
- 
- #define USEC_POLL			2
--#define TIMEOUT_POLL			20
-+#define TIMEOUT_POLL			60
- 
- #define RNG_CTRL			0x00
- #define RNG_EN				BIT(0)
-@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
- 		readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
- 					  ready & RNG_READY, USEC_POLL,
- 					  TIMEOUT_POLL);
--	return !!ready;
-+	return !!(ready & RNG_READY);
- }
- 
- static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
- #endif	/* CONFIG_PM */
- 
- static const struct of_device_id mtk_rng_match[] = {
-+	{ .compatible = "mediatek,mt7986-rng" },
- 	{ .compatible = "mediatek,mt7623-rng" },
- 	{},
- };
diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch
deleted file mode 100644
index fa232b5d4e..0000000000
--- a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/tty/serial/8250/8250.h
-+++ b/drivers/tty/serial/8250/8250.h
-@@ -86,6 +86,7 @@ struct serial8250_config {
- 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
- 					 */
- #define UART_CAP_NOTEMT	BIT(18)	/* UART without interrupt on TEMT available */
-+#define UART_CAP_NMOD	BIT(19)	/* UART doesn't do termios */
- 
- #define UART_BUG_QUOT	BIT(0)	/* UART has buggy quot LSB */
- #define UART_BUG_TXEN	BIT(1)	/* UART has buggy TX IIR status */
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -287,7 +287,7 @@ static const struct serial8250_config ua
- 		.tx_loadsz	= 16,
- 		.fcr		= UART_FCR_ENABLE_FIFO |
- 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
--		.flags		= UART_CAP_FIFO,
-+		.flags		= UART_CAP_FIFO | UART_CAP_NMOD,
- 	},
- 	[PORT_NPCM] = {
- 		.name		= "Nuvoton 16550",
-@@ -2767,6 +2767,11 @@ serial8250_do_set_termios(struct uart_po
- 	unsigned long flags;
- 	unsigned int baud, quot, frac = 0;
- 
-+	if (up->capabilities & UART_CAP_NMOD) {
-+		termios->c_cflag = 0;
-+		return;
-+	}
-+
- 	if (up->capabilities & UART_CAP_MINI) {
- 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
- 		if ((termios->c_cflag & CSIZE) == CS5 ||
diff --git a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
deleted file mode 100644
index 95fc7f4668..0000000000
--- a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:29:51 +0800
-Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
- data
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c                 | 29 +++++++++---------------
- include/linux/platform_data/spi-mt65xx.h | 17 --------------
- 2 files changed, 11 insertions(+), 35 deletions(-)
- delete mode 100644 include/linux/platform_data/spi-mt65xx.h
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -14,7 +14,6 @@
- #include <linux/of.h>
- #include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
--#include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-@@ -171,6 +170,8 @@ struct mtk_spi {
- 	struct device *dev;
- 	dma_addr_t tx_dma;
- 	dma_addr_t rx_dma;
-+	u32 sample_sel;
-+	u32 get_tick_dly;
- };
- 
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
- 	.no_need_unprepare = true,
- };
- 
--/*
-- * A piece of default chip info unless the platform
-- * supplies it.
-- */
--static const struct mtk_chip_config mtk_default_chip_info = {
--	.sample_sel = 0,
--	.tick_delay = 0,
--};
--
- static const struct of_device_id mtk_spi_of_match[] = {
- 	{ .compatible = "mediatek,spi-ipm",
- 		.data = (void *)&mtk_ipm_compat,
-@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
- {
- 	u16 cpha, cpol;
- 	u32 reg_val;
--	struct mtk_chip_config *chip_config = spi->controller_data;
- 	struct mtk_spi *mdata = spi_master_get_devdata(master);
- 
- 	cpha = spi->mode & SPI_CPHA ? 1 : 0;
-@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
- 		else
- 			reg_val &= ~SPI_CMD_CS_POL;
- 
--		if (chip_config->sample_sel)
-+		if (mdata->sample_sel)
- 			reg_val |= SPI_CMD_SAMPLE_SEL;
- 		else
- 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
-@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
- 		if (mdata->dev_comp->ipm_design) {
- 			reg_val = readl(mdata->base + SPI_CMD_REG);
- 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CMD_REG);
- 		} else {
- 			reg_val = readl(mdata->base + SPI_CFG1_REG);
- 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
--			reg_val |= ((chip_config->tick_delay & 0x7)
-+			reg_val |= ((mdata->get_tick_dly & 0x7)
- 				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
- 			writel(reg_val, mdata->base + SPI_CFG1_REG);
- 		}
- 	} else {
- 		reg_val = readl(mdata->base + SPI_CFG1_REG);
- 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
--		reg_val |= ((chip_config->tick_delay & 0x3)
-+		reg_val |= ((mdata->get_tick_dly & 0x3)
- 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
- 		writel(reg_val, mdata->base + SPI_CFG1_REG);
- 	}
-@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
- {
- 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
- 
--	if (!spi->controller_data)
--		spi->controller_data = (void *)&mtk_default_chip_info;
--
- 	if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
- 		/* CS de-asserted, gpiolib will handle inversion */
- 		gpiod_direction_output(spi->cs_gpiod, 0);
-@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
- 	mdata = spi_master_get_devdata(master);
- 	mdata->dev_comp = device_get_match_data(dev);
- 
-+	/* Set device configs to default first. Calibrate it later. */
-+	mdata->sample_sel = 0;
-+	mdata->get_tick_dly = 2;
-+
- 	if (mdata->dev_comp->enhance_timing)
- 		master->mode_bits |= SPI_CS_HIGH;
- 
---- a/include/linux/platform_data/spi-mt65xx.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--/*
-- *  MTK SPI bus driver definitions
-- *
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Leilk Liu <leilk.liu@mediatek.com>
-- */
--
--#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
--#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
--
--/* Board specific platform_data */
--struct mtk_chip_config {
--	u32 sample_sel;
--	u32 tick_delay;
--};
--#endif
diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch
deleted file mode 100644
index b2c9df4386..0000000000
--- a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:35:52 +0800
-Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi.c       | 137 ++++++++++++++++++++++++++++++++++++++++
- include/linux/spi/spi.h |  42 ++++++++++++
- 2 files changed, 179 insertions(+)
-
---- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -1385,6 +1385,70 @@ static int spi_transfer_wait(struct spi_
- 	return 0;
- }
- 
-+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
-+{
-+	int datalen = ctlr->cal_rule->datalen;
-+	int addrlen = ctlr->cal_rule->addrlen;
-+	u8 *buf;
-+	int ret;
-+	int i;
-+	struct list_head *cal_head, *listptr;
-+	struct spi_cal_target *target;
-+
-+	/* Calculate calibration result */
-+	int hit_val, total_hit, origin;
-+	bool hit;
-+
-+	/* Make sure we can start calibration */
-+	if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
-+		return 0;
-+
-+	buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
-+	if(!buf)
-+		return -ENOMEM;
-+
-+	ret = ctlr->append_caldata(ctlr);
-+	if (ret)
-+		goto cal_end;
-+
-+	cal_head = ctlr->cal_target;
-+	list_for_each(listptr, cal_head) {
-+		target = list_entry(listptr, struct spi_cal_target, list);
-+
-+		hit = false;
-+		hit_val = 0;
-+		total_hit = 0;
-+		origin = *target->cal_item;
-+
-+		for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
-+			*target->cal_item = i;
-+			ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
-+			if(ret)
-+				break;
-+			dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
-+			if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
-+				hit = true;
-+				hit_val += i;
-+				total_hit++;
-+				dev_dbg(&spi->dev, "golden data matches data read!\n");
-+			}
-+		}
-+		if(hit) {
-+			*target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
-+			dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
-+		} else {
-+			*target->cal_item = origin;
-+			dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
-+		}
-+	}
-+
-+cal_end:
-+	kfree(buf);
-+	return ret? ret: 0;
-+}
-+EXPORT_SYMBOL_GPL(spi_do_calibration);
-+
- static void _spi_transfer_delay_ns(u32 ns)
- {
- 	if (!ns)
-@@ -2223,6 +2287,75 @@ void spi_flush_queue(struct spi_controll
- /*-------------------------------------------------------------------------*/
- 
- #if defined(CONFIG_OF)
-+static inline void alloc_cal_data(struct list_head **cal_target,
-+	struct spi_cal_rule **cal_rule, bool enable)
-+{
-+	if(enable) {
-+		*cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
-+		INIT_LIST_HEAD(*cal_target);
-+		*cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
-+	} else {
-+		kfree(*cal_target);
-+		kfree(*cal_rule);
-+	}
-+}
-+
-+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
-+			   struct device_node *nc)
-+{
-+	u32 value;
-+	int rc;
-+	const char *cal_mode;
-+
-+	rc = of_property_read_bool(nc, "spi-cal-enable");
-+	if (rc)
-+		alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
-+	else
-+		return 0;
-+
-+	rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
-+	if(!rc) {
-+		if(strcmp("read-data", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
-+		} else if(strcmp("read-pp", cal_mode) == 0) {
-+			ctlr->cal_rule->mode = SPI_CAL_READ_PP;
-+			return 0;
-+		} else if(strcmp("read-sfdp", cal_mode) == 0){
-+			ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
-+			return 0;
-+		}
-+	} else
-+		goto err;
-+
-+	ctlr->cal_rule->datalen = 0;
-+	rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->datalen = value;
-+
-+		ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
-+		rc = of_property_read_u8_array(nc, "spi-cal-data",
-+				ctlr->cal_rule->match_data, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->match_data);
-+	}
-+
-+	rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
-+	if(!rc && value > 0) {
-+		ctlr->cal_rule->addrlen = value;
-+
-+		ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
-+		rc = of_property_read_u32_array(nc, "spi-cal-addr",
-+				ctlr->cal_rule->addr, value);
-+		if(rc)
-+			kfree(ctlr->cal_rule->addr);
-+	}
-+	return 0;
-+
-+err:
-+	alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
-+	return 0;
-+}
-+
- static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
- 			   struct device_node *nc)
- {
-@@ -2341,6 +2474,10 @@ of_register_spi_device(struct spi_contro
- 	if (rc)
- 		goto err_out;
- 
-+	rc = of_spi_parse_cal_dt(ctlr, spi, nc);
-+	if (rc)
-+		goto err_out;
-+
- 	/* Store a pointer to the node in the device structure */
- 	of_node_get(nc);
- 	spi->dev.of_node = nc;
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -318,6 +318,40 @@ struct spi_driver {
- 	struct device_driver	driver;
- };
- 
-+enum {
-+	SPI_CAL_READ_DATA = 0,
-+	SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
-+	SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
-+};
-+
-+struct nand_addr {
-+	unsigned int lun;
-+	unsigned int plane;
-+	unsigned int eraseblock;
-+	unsigned int page;
-+	unsigned int dataoffs;
-+};
-+
-+/**
-+ * Read calibration rule from device dts node.
-+ * Once calibration result matches the rule, we regard is as success.
-+ */
-+struct spi_cal_rule {
-+	int datalen;
-+	u8 *match_data;
-+	int addrlen;
-+	u32 *addr;
-+	int mode;
-+};
-+
-+struct spi_cal_target {
-+	u32 *cal_item;
-+	int cal_min; /* min of cal_item */
-+	int cal_max; /* max of cal_item */
-+	int step; /* Increase/decrease cal_item */
-+	struct list_head list;
-+};
-+
- static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
- {
- 	return drv ? container_of(drv, struct spi_driver, driver) : NULL;
-@@ -703,6 +737,11 @@ struct spi_controller {
- 	void			*dummy_rx;
- 	void			*dummy_tx;
- 
-+	/* For calibration */
-+	int (*append_caldata)(struct spi_controller *ctlr);
-+	struct list_head *cal_target;
-+	struct spi_cal_rule *cal_rule;
-+
- 	int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
- 
- 	/*
-@@ -1510,6 +1549,9 @@ spi_register_board_info(struct spi_board
- 	{ return 0; }
- #endif
- 
-+extern int spi_do_calibration(struct spi_controller *ctlr,
-+	struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
-+
- /* If you're hotplugging an adapter with devices (parport, usb, etc)
-  * use spi_new_device() to describe each device.  You can also call
-  * spi_unregister_device() to start making that device vanish, but
diff --git a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch
deleted file mode 100644
index e87d63db69..0000000000
--- a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:37:55 +0800
-Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mem.c       | 8 ++++++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
- }
- EXPORT_SYMBOL_GPL(spi_mem_exec_op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+	int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
-+	void *priv)
-+{
-+	return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
-+}
-+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
-+
- /**
-  * spi_mem_get_name() - Return the SPI mem device name to be used by the
-  *			upper layer if necessary
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
- int spi_mem_exec_op(struct spi_mem *mem,
- 		    const struct spi_mem_op *op);
- 
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+			int (*cal_read)(void *, u32 *, int, u8 *, int),
-+			void *priv);
-+
- const char *spi_mem_get_name(struct spi_mem *mem);
- 
- struct spi_mem_dirmap_desc *
diff --git a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
deleted file mode 100644
index dbdb1947aa..0000000000
--- a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:03 +0800
-Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
- paramter
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int
- 	return IRQ_HANDLED;
- }
- 
-+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
-+{
-+	struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
-+	struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
-+
-+	cal_target->cal_item = &mdata->get_tick_dly;
-+	cal_target->cal_min = 0;
-+	cal_target->cal_max = 7;
-+	cal_target->step = 1;
-+
-+	list_add(&cal_target->list, ctlr->cal_target);
-+
-+	return 0;
-+}
-+
- static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
- 				      struct spi_mem_op *op)
- {
-@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform
- 	master->setup = mtk_spi_setup;
- 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
- 	master->use_gpio_descriptors = true;
-+	master->append_caldata = mtk_spi_append_caldata;
- 
- 	mdata = spi_master_get_devdata(master);
- 	mdata->dev_comp = device_get_match_data(dev);
diff --git a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
deleted file mode 100644
index 3991d8925a..0000000000
--- a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:56 +0800
-Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
- spinand
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st
- 	return -ENOTSUPP;
- }
- 
-+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
-+	struct spinand_device *spinand = (struct spinand_device *)priv;
-+	struct device *dev = &spinand->spimem->spi->dev;
-+	struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
-+	struct nand_pos pos;
-+	struct nand_page_io_req req;
-+	u8 status;
-+	int ret;
-+
-+	if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
-+		dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
-+		return -EINVAL;
-+	}
-+
-+	ret = spinand_reset_op(spinand);
-+	if (ret)
-+		return ret;
-+
-+	/* We should store our golden data in first target because
-+	 * we can't switch target at this moment.
-+	 */
-+	pos = (struct nand_pos){
-+		.target = 0,
-+		.lun = *addr,
-+		.plane = *(addr+1),
-+		.eraseblock = *(addr+2),
-+		.page = *(addr+3),
-+	};
-+
-+	req = (struct nand_page_io_req){
-+		.pos = pos,
-+		.dataoffs = *(addr+4),
-+		.datalen = readlen,
-+		.databuf.in = buf,
-+		.mode = MTD_OPS_AUTO_OOB,
-+	};
-+
-+	ret = spinand_load_page_op(spinand, &req);
-+	if (ret)
-+		return ret;
-+
-+	ret = spinand_wait(spinand, &status);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = spi_mem_exec_op(spinand->spimem, &op);
-+
-+	return 0;
-+}
-+
- static int spinand_id_detect(struct spinand_device *spinand)
- {
- 	u8 *id = spinand->id.data;
-@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d
- 	if (!spinand->scratchbuf)
- 		return -ENOMEM;
- 
-+	ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
-+	if (ret)
-+		dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
-+
- 	ret = spinand_detect(spinand);
- 	if (ret)
- 		goto err_free_bufs;
diff --git a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
deleted file mode 100644
index ac8a55e187..0000000000
--- a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:40:59 +0800
-Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
- spi-nor
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c |  5 ++++-
- drivers/mtd/spi-nor/core.c  | 15 +++++++++++++++
- 2 files changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad
- 	if (ret)
- 		return ret;
- 
--	ret = spinand_wait(spinand, &status);
-+	ret = spinand_wait(spinand,
-+			   SPINAND_READ_INITIAL_DELAY_US,
-+			   SPINAND_READ_POLL_DELAY_US,
-+			   &status);
- 	if (ret < 0)
- 		return ret;
- 
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -2922,6 +2922,18 @@ static const struct flash_info *spi_nor_
- 	return NULL;
- }
- 
-+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
-+{
-+	struct spi_nor *nor = (struct spi_nor *)priv;
-+
-+	nor->reg_proto = SNOR_PROTO_1_1_1;
-+	nor->read_proto = SNOR_PROTO_1_1_1;
-+	nor->read_opcode = SPINOR_OP_READ;
-+	nor->read_dummy = 0;
-+
-+	return nor->controller_ops->read(nor, *addr, readlen, buf);
-+}
-+
- static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
- 						       const char *name)
- {
-@@ -3025,6 +3037,9 @@ int spi_nor_scan(struct spi_nor *nor, co
- 	if (!nor->bouncebuf)
- 		return -ENOMEM;
- 
-+	if(nor->spimem)
-+		spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
-+
- 	info = spi_nor_get_flash_info(nor, name);
- 	if (IS_ERR(info))
- 		return PTR_ERR(info);
diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
deleted file mode 100644
index 487990ab77..0000000000
--- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -384,6 +384,12 @@ config ROCKCHIP_PHY
- 	help
- 	  Currently supports the integrated Ethernet PHY.
- 
-+config RTL8367S_GSW
-+	tristate "rtl8367 Gigabit Switch support for mt7622"
-+	depends on NET_VENDOR_MEDIATEK
-+	help
-+	  This driver supports rtl8367s in mt7622
-+
- config SMSC_PHY
- 	tristate "SMSC PHYs"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
-+obj-$(CONFIG_RTL8367S_GSW)	+= rtk/
- obj-$(CONFIG_SMSC_PHY)		+= smsc.o
- obj-$(CONFIG_STE10XP)		+= ste10Xp.o
- obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
deleted file mode 100644
index 983fde707f..0000000000
--- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From: qizhong cheng <qizhong.cheng@mediatek.com>
-Date: Mon, 27 Dec 2021 21:31:10 +0800
-Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
- stabilize
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-be delayed 100ms (TPVPERL) for the power and clock to become stable.
-
-Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
-Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Pali Rohár <pali@kernel.org>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
- 	 */
- 	msleep(100);
- 
-+	/*
-+	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-+	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-+	 * be delayed 100ms (TPVPERL) for the power and clock to become stable.
-+	 */
-+	msleep(100);
-+
- 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
- 	val = readl(port->base + PCIE_RST_CTRL);
- 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
diff --git a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
deleted file mode 100644
index bf479ab53b..0000000000
--- a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot0: pcie@0,0 {
-+			reg = <0x0000 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
- 			#address-cells = <0>;
- 			#interrupt-cells = <1>;
- 		};
-+
-+		slot1: pcie@1,0 {
-+			reg = <0x0800 0 0 0 0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+		};
- 	};
- 
- 	sata: sata@1a200000 {
diff --git a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch
deleted file mode 100644
index 2a49b2275c..0000000000
--- a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:33:27 +0200
-Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
-
-Clearing the status needs to happen after running the handler, otherwise
-we will get an extra spurious interrupt after the cause has been cleared
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
- 	if (status & INTX_MASK) {
- 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- 			/* Clear the INTx */
--			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 			generic_handle_domain_irq(port->irq_domain,
- 						  bit - INTX_SHIFT);
-+			writel(1 << bit, port->base + PCIE_INT_STATUS);
- 		}
- 	}
- 
diff --git a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
deleted file mode 100644
index 32b4237d82..0000000000
--- a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct
- 	msleep(100);
- 
- 	/* De-assert reset signals */
--	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
-+	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
-+	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+
-+	msleep(100);
-+
-+	/* De-assert PERST# signals */
-+	val &= ~(PCIE_PE_RSTB);
- 	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
- 
- 	/* Check if the link is up or not */
diff --git a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
deleted file mode 100644
index a597f70caa..0000000000
--- a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch
+++ /dev/null
@@ -1,167 +0,0 @@
-From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 2 Jun 2023 13:06:26 +0800
-Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
-
-Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
-released under GPL.
-
-Get syscon and use it to set the PHY type.
-Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
- 1 file changed, 80 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/mediatek/phy-mtk-xsphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
-@@ -11,10 +11,12 @@
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/iopoll.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of_address.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-+#include <linux/regmap.h>
- 
- #include "phy-mtk-io.h"
- 
-@@ -81,12 +83,22 @@
- #define XSP_SR_COEF_DIVISOR	1000
- #define XSP_FM_DET_CYCLE_CNT	1024
- 
-+/* PHY switch between pcie/usb3/sgmii */
-+#define USB_PHY_SWITCH_CTRL	0x0
-+#define RG_PHY_SW_TYPE		GENMASK(3, 0)
-+#define RG_PHY_SW_PCIE		0x0
-+#define RG_PHY_SW_USB3		0x1
-+#define RG_PHY_SW_SGMII		0x2
-+
- struct xsphy_instance {
- 	struct phy *phy;
- 	void __iomem *port_base;
- 	struct clk *ref_clk;	/* reference clock of anolog phy */
- 	u32 index;
- 	u32 type;
-+	struct regmap *type_sw;
-+	u32 type_sw_reg;
-+	u32 type_sw_index;
- 	/* only for HQA test */
- 	int efuse_intr;
- 	int efuse_tx_imp;
-@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
- 			inst->efuse_intr, inst->efuse_tx_imp,
- 			inst->efuse_rx_imp);
- 		break;
-+	case PHY_TYPE_PCIE:
-+	case PHY_TYPE_SGMII:
-+		/* nothing to do */
-+		break;
- 	default:
- 		dev_err(xsphy->dev, "incompatible phy type\n");
- 		return;
-@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
- 				     RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
- }
- 
-+/* type switch for usb3/pcie/sgmii */
-+static int phy_type_syscon_get(struct xsphy_instance *instance,
-+			       struct device_node *dn)
-+{
-+	struct of_phandle_args args;
-+	int ret;
-+
-+	/* type switch function is optional */
-+	if (!of_property_read_bool(dn, "mediatek,syscon-type"))
-+		return 0;
-+
-+	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
-+					       2, 0, &args);
-+	if (ret)
-+		return ret;
-+
-+	instance->type_sw_reg = args.args[0];
-+	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
-+	instance->type_sw = syscon_node_to_regmap(args.np);
-+	of_node_put(args.np);
-+	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
-+		 instance->type_sw_reg, instance->type_sw_index);
-+
-+	return PTR_ERR_OR_ZERO(instance->type_sw);
-+}
-+
-+static int phy_type_set(struct xsphy_instance *instance)
-+{
-+	int type;
-+	u32 offset;
-+
-+	if (!instance->type_sw)
-+		return 0;
-+
-+	switch (instance->type) {
-+	case PHY_TYPE_USB3:
-+		type = RG_PHY_SW_USB3;
-+		break;
-+	case PHY_TYPE_PCIE:
-+		type = RG_PHY_SW_PCIE;
-+		break;
-+	case PHY_TYPE_SGMII:
-+		type = RG_PHY_SW_SGMII;
-+		break;
-+	case PHY_TYPE_USB2:
-+	default:
-+		return 0;
-+	}
-+
-+	offset = instance->type_sw_index * BITS_PER_BYTE;
-+	regmap_update_bits(instance->type_sw, instance->type_sw_reg,
-+			   RG_PHY_SW_TYPE << offset, type << offset);
-+
-+	return 0;
-+}
-+
- static int mtk_phy_init(struct phy *phy)
- {
- 	struct xsphy_instance *inst = phy_get_drvdata(phy);
-@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
- 	case PHY_TYPE_USB3:
- 		u3_phy_props_set(xsphy, inst);
- 		break;
-+	case PHY_TYPE_PCIE:
-+	case PHY_TYPE_SGMII:
-+		/* nothing to do, only used to set type */
-+		break;
- 	default:
- 		dev_err(xsphy->dev, "incompatible phy type\n");
- 		clk_disable_unprepare(inst->ref_clk);
-@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
- 
- 	inst->type = args->args[0];
- 	if (!(inst->type == PHY_TYPE_USB2 ||
--	      inst->type == PHY_TYPE_USB3)) {
-+	      inst->type == PHY_TYPE_USB3 ||
-+	      inst->type == PHY_TYPE_PCIE ||
-+	      inst->type == PHY_TYPE_SGMII)) {
- 		dev_err(dev, "unsupported phy type: %d\n", inst->type);
- 		return ERR_PTR(-EINVAL);
- 	}
- 
- 	phy_parse_property(xsphy, inst);
-+	phy_type_set(inst);
- 
- 	return inst->phy;
- }
-@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
- 			retval = PTR_ERR(inst->ref_clk);
- 			goto put_child;
- 		}
-+
-+		retval = phy_type_syscon_get(inst, child_np);
-+		if (retval)
-+			goto put_child;
- 	}
- 
- 	provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
deleted file mode 100644
index 76ee2fc89a..0000000000
--- a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:42:42 +0200
-Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
-
-It improves performance by eliminating the need for a cache flush for DMA on
-attached devices
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
- 		bus-range = <0x00 0xff>;
- 		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
- 		status = "disabled";
-+		dma-coherent;
-+		mediatek,hifsys = <&hifsys>;
-+		mediatek,cci-control = <&cci_control2>;
- 
- 		#interrupt-cells = <1>;
- 		interrupt-map-mask = <0 0 0 7>;
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -20,6 +20,7 @@
- #include <linux/of_address.h>
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
-+#include <linux/of_address.h>
- #include <linux/pci.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-@@ -139,6 +140,11 @@
- #define PCIE_LINK_STATUS_V2	0x804
- #define PCIE_PORT_LINKUP_V2	BIT(10)
- 
-+/* DMA channel mapping */
-+#define HIFSYS_DMA_AG_MAP	0x008
-+#define HIFSYS_DMA_AG_MAP_PCIE0	BIT(0)
-+#define HIFSYS_DMA_AG_MAP_PCIE1	BIT(1)
-+
- struct mtk_pcie_port;
- 
- /**
-@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
- 	struct mtk_pcie_port *port, *tmp;
- 	int err, slot;
- 
-+	if (of_dma_is_coherent(node)) {
-+		struct regmap *con;
-+		u32 mask;
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,cci-control");
-+		/* enable CPU/bus coherency */
-+		if (!IS_ERR(con))
-+			regmap_write(con, 0, 3);
-+
-+		con = syscon_regmap_lookup_by_phandle(node,
-+						      "mediatek,hifsys");
-+		if (IS_ERR(con)) {
-+			dev_err(dev, "missing hifsys node\n");
-+			return PTR_ERR(con);
-+		}
-+
-+		mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
-+		regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
-+	}
-+
- 	slot = of_get_pci_domain_nr(dev->of_node);
- 	if (slot < 0) {
- 		for_each_available_child_of_node(node, child) {
diff --git a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch
deleted file mode 100644
index f9a5fdbd0d..0000000000
--- a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Jip de Beer <gpk6x3591g0l@opayq.com>
-Date: Sun, 9 Jan 2022 13:14:04 +0100
-Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
-
-The lowest frequency should be 300MHz, since that is the label
-assigned to the OPP in the mt7622.dtsi device tree, while there is one
-missing zero in the actual value.
-
-To be clear, the lowest frequency should be 300MHz instead of 30MHz.
-
-As mentioned @dangowrt on the OpenWrt forum there is no benefit in
-leaving 30MHz as the lowest frequency.
-
-Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
-Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
----
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -24,7 +24,7 @@
- 		compatible = "operating-points-v2";
- 		opp-shared;
- 		opp-300000000 {
--			opp-hz = /bits/ 64 <30000000>;
-+			opp-hz = /bits/ 64 <300000000>;
- 			opp-microvolt = <950000>;
- 		};
- 
diff --git a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch
deleted file mode 100644
index 52069496ca..0000000000
--- a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -23,11 +23,17 @@
- 	cpu_opp_table: opp-table {
- 		compatible = "operating-points-v2";
- 		opp-shared;
--		opp-300000000 {
--			opp-hz = /bits/ 64 <300000000>;
--			opp-microvolt = <950000>;
--		};
--
-+		/* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
-+		 * voltage condition that can cause a hang when rebooting the RT3200/E8450.
-+		 *
-+		 * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
-+		 *
-+		 * opp-300000000 {
-+		 *	opp-hz = /bits/ 64 <300000000>;
-+		 *	opp-microvolt = <950000>;
-+		 * };
-+		 *
-+		 */
- 		opp-437500000 {
- 			opp-hz = /bits/ 64 <437500000>;
- 			opp-microvolt = <1000000>;
diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
deleted file mode 100644
index 4022b2a842..0000000000
--- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ /dev/null
@@ -1,1204 +0,0 @@
-From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 11 Jun 2023 00:48:10 +0100
-Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
-
-Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
-PHYs which require calibration data from the SoC's efuse.
-Despite the similar design the driver doesn't share any code with the
-existing mediatek-ge.c.
-Add support for such PHYs by introducing a new driver with basic
-support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS                       |    9 +
- drivers/net/phy/Kconfig           |   12 +
- drivers/net/phy/Makefile          |    1 +
- drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
- drivers/net/phy/mediatek-ge.c     |    3 +-
- 5 files changed, 1140 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/phy/mediatek-ge-soc.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -12945,6 +12945,15 @@ F:	drivers/net/pcs/pcs-mtk-usxgmii.c
- F:	include/linux/pcs/pcs-mtk-lynxi.h
- F:	include/linux/pcs/pcs-mtk-usxgmii.h
- 
-+MEDIATEK ETHERNET PHY DRIVERS
-+M:	Daniel Golle <daniel@makrotopia.org>
-+M:	Qingfang Deng <dqfext@gmail.com>
-+M:	SkyLake Huang <SkyLake.Huang@mediatek.com>
-+L:	netdev@vger.kernel.org
-+S:	Maintained
-+F:	drivers/net/phy/mediatek-ge-soc.c
-+F:	drivers/net/phy/mediatek-ge.c
-+
- MEDIATEK I2C CONTROLLER DRIVER
- M:	Qii Wang <qii.wang@mediatek.com>
- L:	linux-i2c@vger.kernel.org
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY
- 	help
- 	  Supports the MediaTek Gigabit Ethernet PHYs.
- 
-+config MEDIATEK_GE_SOC_PHY
-+	tristate "MediaTek SoC Ethernet PHYs"
-+	depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
-+	select NVMEM_MTK_EFUSE
-+	help
-+	  Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
-+
-+	  Include support for built-in Ethernet PHYs which are present in
-+	  the MT7981 and MT7988 SoCs. These PHYs need calibration data
-+	  present in the SoCs efuse and will dynamically calibrate VCM
-+	  (common-mode voltage) during startup.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	depends on PTP_1588_CLOCK_OPTIONAL
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
-+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA)	+= spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY)	+= micrel.o
---- /dev/null
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -0,0 +1,1116 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+#include <linux/bitfield.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/phy.h>
-+
-+#define MTK_GPHY_ID_MT7981			0x03a29461
-+#define MTK_GPHY_ID_MT7988			0x03a29481
-+
-+#define MTK_EXT_PAGE_ACCESS			0x1f
-+#define MTK_PHY_PAGE_STANDARD			0x0000
-+#define MTK_PHY_PAGE_EXTENDED_3			0x0003
-+
-+#define MTK_PHY_LPI_REG_14			0x14
-+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK	GENMASK(8, 0)
-+
-+#define MTK_PHY_LPI_REG_1c			0x1c
-+#define MTK_PHY_SMI_DET_ON_THRESH_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_PAGE_EXTENDED_2A30		0x2a30
-+#define MTK_PHY_PAGE_EXTENDED_52B5		0x52b5
-+
-+#define ANALOG_INTERNAL_OPERATION_MAX_US	20
-+#define TXRESERVE_MIN				0
-+#define TXRESERVE_MAX				7
-+
-+#define MTK_PHY_ANARG_RG			0x10
-+#define   MTK_PHY_TCLKOFFSET_MASK		GENMASK(12, 8)
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define MTK_PHY_TXVLD_DA_RG			0x12
-+#define   MTK_PHY_DA_TX_I2MPB_A_GBE_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2		0x16
-+#define   MTK_PHY_DA_TX_I2MPB_A_HBT_MASK	GENMASK(15, 10)
-+#define   MTK_PHY_DA_TX_I2MPB_A_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1		0x17
-+#define   MTK_PHY_DA_TX_I2MPB_B_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2		0x18
-+#define   MTK_PHY_DA_TX_I2MPB_B_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_B_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1		0x19
-+#define   MTK_PHY_DA_TX_I2MPB_C_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2		0x20
-+#define   MTK_PHY_DA_TX_I2MPB_C_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_C_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1		0x21
-+#define   MTK_PHY_DA_TX_I2MPB_D_GBE_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TBT_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2		0x22
-+#define   MTK_PHY_DA_TX_I2MPB_D_HBT_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_DA_TX_I2MPB_D_TST_MASK	GENMASK(5, 0)
-+
-+#define MTK_PHY_RXADC_CTRL_RG7			0xc6
-+#define   MTK_PHY_DA_AD_BUF_BIAS_LP_MASK	GENMASK(9, 8)
-+
-+#define MTK_PHY_RXADC_CTRL_RG9			0xc8
-+#define   MTK_PHY_DA_RX_PSBN_TBT_MASK		GENMASK(14, 12)
-+#define   MTK_PHY_DA_RX_PSBN_HBT_MASK		GENMASK(10, 8)
-+#define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
-+#define   MTK_PHY_DA_RX_PSBN_LP_MASK		GENMASK(2, 0)
-+
-+#define MTK_PHY_LDO_OUTPUT_V			0xd7
-+
-+#define MTK_PHY_RG_ANA_CAL_RG0			0xdb
-+#define   MTK_PHY_RG_CAL_CKINV			BIT(12)
-+#define   MTK_PHY_RG_ANA_CALEN			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_A			BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG1			0xdc
-+#define   MTK_PHY_RG_ZCALEN_B			BIT(12)
-+#define   MTK_PHY_RG_ZCALEN_C			BIT(8)
-+#define   MTK_PHY_RG_ZCALEN_D			BIT(4)
-+#define   MTK_PHY_RG_TXVOS_CALEN		BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG5			0xe0
-+#define   MTK_PHY_RG_REXT_TRIM_MASK		GENMASK(13, 8)
-+
-+#define MTK_PHY_RG_TX_FILTER			0xfe
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120	0x120
-+#define   MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK	GENMASK(12, 8)
-+#define   MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122	0x122
-+#define   MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK	GENMASK(7, 0)
-+
-+#define MTK_PHY_RG_TESTMUX_ADC_CTRL		0x144
-+#define   MTK_PHY_RG_TXEN_DIG_MASK		GENMASK(5, 5)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B		0x172
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_A_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D		0x173
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_C_MASK	GENMASK(13, 8)
-+#define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_AD_CAL_COMP			0x17a
-+#define   MTK_PHY_AD_CAL_COMP_OUT_SHIFT		(8)
-+
-+#define MTK_PHY_RG_AD_CAL_CLK			0x17b
-+#define   MTK_PHY_DA_CAL_CLK			BIT(0)
-+
-+#define MTK_PHY_RG_AD_CALIN			0x17c
-+#define   MTK_PHY_DA_CALIN_FLAG			BIT(0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_A		0x17d
-+#define   MTK_PHY_DASN_DAC_IN0_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_B		0x17e
-+#define   MTK_PHY_DASN_DAC_IN0_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_C		0x17f
-+#define   MTK_PHY_DASN_DAC_IN0_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_D		0x180
-+#define   MTK_PHY_DASN_DAC_IN0_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_A		0x181
-+#define   MTK_PHY_DASN_DAC_IN1_A_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_B		0x182
-+#define   MTK_PHY_DASN_DAC_IN1_B_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_C		0x183
-+#define   MTK_PHY_DASN_DAC_IN1_C_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_D		0x184
-+#define   MTK_PHY_DASN_DAC_IN1_D_MASK		GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG19b			0x19b
-+#define   MTK_PHY_BYPASS_DSP_LPI_READY		BIT(8)
-+
-+#define MTK_PHY_RG_LP_IIR2_K1_L			0x22a
-+#define MTK_PHY_RG_LP_IIR2_K1_U			0x22b
-+#define MTK_PHY_RG_LP_IIR2_K2_L			0x22c
-+#define MTK_PHY_RG_LP_IIR2_K2_U			0x22d
-+#define MTK_PHY_RG_LP_IIR2_K3_L			0x22e
-+#define MTK_PHY_RG_LP_IIR2_K3_U			0x22f
-+#define MTK_PHY_RG_LP_IIR2_K4_L			0x230
-+#define MTK_PHY_RG_LP_IIR2_K4_U			0x231
-+#define MTK_PHY_RG_LP_IIR2_K5_L			0x232
-+#define MTK_PHY_RG_LP_IIR2_K5_U			0x233
-+
-+#define MTK_PHY_RG_DEV1E_REG234			0x234
-+#define   MTK_PHY_TR_OPEN_LOOP_EN_MASK		GENMASK(0, 0)
-+#define   MTK_PHY_LPF_X_AVERAGE_MASK		GENMASK(7, 4)
-+#define   MTK_PHY_TR_LP_IIR_EEE_EN		BIT(12)
-+
-+#define MTK_PHY_RG_LPF_CNT_VAL			0x235
-+
-+#define MTK_PHY_RG_DEV1E_REG238			0x238
-+#define   MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_SLV_SEND_TX_EN		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG239			0x239
-+#define   MTK_PHY_LPI_SEND_LOC_TIMER_MASK	GENMASK(8, 0)
-+#define   MTK_PHY_LPI_TXPCS_LOC_RCV		BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG27C			0x27c
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST1_MASK	GENMASK(12, 8)
-+#define MTK_PHY_RG_DEV1E_REG27D			0x27d
-+#define   MTK_PHY_VGASTATE_FFE_THR_ST2_MASK	GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG2C7			0x2c7
-+#define   MTK_PHY_MAX_GAIN_MASK			GENMASK(4, 0)
-+#define   MTK_PHY_MIN_GAIN_MASK			GENMASK(12, 8)
-+
-+#define MTK_PHY_RG_DEV1E_REG2D1			0x2d1
-+#define   MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK	GENMASK(7, 0)
-+#define   MTK_PHY_LPI_SKIP_SD_SLV_TR		BIT(8)
-+#define   MTK_PHY_LPI_TR_READY			BIT(9)
-+#define   MTK_PHY_LPI_VCO_EEE_STG0_EN		BIT(10)
-+
-+#define MTK_PHY_RG_DEV1E_REG323			0x323
-+#define   MTK_PHY_EEE_WAKE_MAS_INT_DC		BIT(0)
-+#define   MTK_PHY_EEE_WAKE_SLV_INT_DC		BIT(4)
-+
-+#define MTK_PHY_RG_DEV1E_REG324			0x324
-+#define   MTK_PHY_SMI_DETCNT_MAX_MASK		GENMASK(5, 0)
-+#define   MTK_PHY_SMI_DET_MAX_EN		BIT(8)
-+
-+#define MTK_PHY_RG_DEV1E_REG326			0x326
-+#define   MTK_PHY_LPI_MODE_SD_ON		BIT(0)
-+#define   MTK_PHY_RESET_RANDUPD_CNT		BIT(1)
-+#define   MTK_PHY_TREC_UPDATE_ENAB_CLR		BIT(2)
-+#define   MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF	BIT(4)
-+#define   MTK_PHY_TR_READY_SKIP_AFE_WAKEUP	BIT(5)
-+
-+#define MTK_PHY_LDO_PUMP_EN_PAIRAB		0x502
-+#define MTK_PHY_LDO_PUMP_EN_PAIRCD		0x503
-+
-+#define MTK_PHY_DA_TX_R50_PAIR_A		0x53d
-+#define MTK_PHY_DA_TX_R50_PAIR_B		0x53e
-+#define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
-+#define MTK_PHY_DA_TX_R50_PAIR_D		0x540
-+
-+#define MTK_PHY_RG_BG_RASEL			0x115
-+#define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
-+
-+/* These macro privides efuse parsing for internal phy. */
-+#define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_C(x)			(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_D(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_A(x)		(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_AMP_OFFSET_B(x)		(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_D(x)		(((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_A(x)			(((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_B(x)			(((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_R50_C(x)			(((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
-+
-+#define EFS_RG_BG_RASEL(x)			(((x) >> 4) & GENMASK(2, 0))
-+#define EFS_RG_REXT_TRIM(x)			(((x) >> 7) & GENMASK(5, 0))
-+
-+enum {
-+	NO_PAIR,
-+	PAIR_A,
-+	PAIR_B,
-+	PAIR_C,
-+	PAIR_D,
-+};
-+
-+enum {
-+	GPHY_PORT0,
-+	GPHY_PORT1,
-+	GPHY_PORT2,
-+	GPHY_PORT3,
-+};
-+
-+enum calibration_mode {
-+	EFUSE_K,
-+	SW_K
-+};
-+
-+enum CAL_ITEM {
-+	REXT,
-+	TX_OFFSET,
-+	TX_AMP,
-+	TX_R50,
-+	TX_VCM
-+};
-+
-+enum CAL_MODE {
-+	EFUSE_M,
-+	SW_M
-+};
-+
-+static int mtk_socphy_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-+}
-+
-+static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-+}
-+
-+/* One calibration cycle consists of:
-+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
-+ *   until AD_CAL_COMP is ready to output calibration result.
-+ * 2.Wait until DA_CAL_CLK is available.
-+ * 3.Fetch AD_CAL_COMP_OUT.
-+ */
-+static int cal_cycle(struct phy_device *phydev, int devad,
-+		     u32 regnum, u16 mask, u16 cal_val)
-+{
-+	int reg_val;
-+	int ret;
-+
-+	phy_modify_mmd(phydev, devad, regnum,
-+		       mask, cal_val);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			 MTK_PHY_DA_CALIN_FLAG);
-+
-+	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+					MTK_PHY_RG_AD_CAL_CLK, reg_val,
-+					reg_val & MTK_PHY_DA_CAL_CLK, 500,
-+					ANALOG_INTERNAL_OPERATION_MAX_US, false);
-+	if (ret) {
-+		phydev_err(phydev, "Calibration cycle timeout\n");
-+		return ret;
-+	}
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+			   MTK_PHY_DA_CALIN_FLAG);
-+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
-+			   MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
-+	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-+
-+	return ret;
-+}
-+
-+static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
-+		       MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
-+		       MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-+
-+	return 0;
-+}
-+
-+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 rext_cal_val[2];
-+
-+	rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
-+	rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
-+	rext_fill_result(phydev, rext_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+		       MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-+
-+	return 0;
-+}
-+
-+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_offset_cal_val[4];
-+
-+	tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
-+	tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
-+	tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
-+	tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-+
-+	tx_offset_fill_result(phydev, tx_offset_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+	int i;
-+	int bias[16] = {};
-+	const int vals_9461[16] = { 7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7,
-+				    7, 1, 4, 7 };
-+	const int vals_9481[16] = { 10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10,
-+				    10, 6, 6, 10 };
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		/* We add some calibration to efuse values
-+		 * due to board level influence.
-+		 * GBE: +7, TBT: +1, HBT: +4, TST: +7
-+		 */
-+		memcpy(bias, (const void *)vals_9461, sizeof(bias));
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		memcpy(bias, (const void *)vals_9481, sizeof(bias));
-+		break;
-+	}
-+
-+	/* Prevent overflow */
-+	for (i = 0; i < 12; i++) {
-+		if (buf[i >> 2] + bias[i] > 63) {
-+			buf[i >> 2] = 63;
-+			bias[i] = 0;
-+		}
-+	}
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+		       MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+		       MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+		       MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+		       MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+		       MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+		       MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+		       MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+		       MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-+
-+	return 0;
-+}
-+
-+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+	u16 tx_amp_cal_val[4];
-+
-+	tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
-+	tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
-+	tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
-+	tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
-+	tx_amp_fill_result(phydev, tx_amp_cal_val);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
-+			      u8 txg_calen_x)
-+{
-+	int bias = 0;
-+	u16 reg, val;
-+
-+	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-+		bias = -2;
-+
-+	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_A;
-+		break;
-+	case PAIR_B:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_B;
-+		break;
-+	case PAIR_C:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_C;
-+		break;
-+	case PAIR_D:
-+		reg = MTK_PHY_DA_TX_R50_PAIR_D;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-+
-+	return 0;
-+}
-+
-+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
-+			    u8 txg_calen_x)
-+{
-+	u16 tx_r50_cal_val;
-+
-+	switch (txg_calen_x) {
-+	case PAIR_A:
-+		tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
-+		break;
-+	case PAIR_B:
-+		tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
-+		break;
-+	case PAIR_C:
-+		tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
-+		break;
-+	case PAIR_D:
-+		tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-+
-+	return 0;
-+}
-+
-+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-+{
-+	u8 lower_idx, upper_idx, txreserve_val;
-+	u8 lower_ret, upper_ret;
-+	int ret;
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			 MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_CAL_CKINV);
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			 MTK_PHY_RG_TXVOS_CALEN);
-+
-+	switch (rg_txreserve_x) {
-+	case PAIR_A:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_A,
-+				   MTK_PHY_DASN_DAC_IN0_A_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_A,
-+				   MTK_PHY_DASN_DAC_IN1_A_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG0,
-+				 MTK_PHY_RG_ZCALEN_A);
-+		break;
-+	case PAIR_B:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_B,
-+				   MTK_PHY_DASN_DAC_IN0_B_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_B,
-+				   MTK_PHY_DASN_DAC_IN1_B_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_B);
-+		break;
-+	case PAIR_C:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_C,
-+				   MTK_PHY_DASN_DAC_IN0_C_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_C,
-+				   MTK_PHY_DASN_DAC_IN1_C_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_C);
-+		break;
-+	case PAIR_D:
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN0_D,
-+				   MTK_PHY_DASN_DAC_IN0_D_MASK);
-+		phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				   MTK_PHY_RG_DASN_DAC_IN1_D,
-+				   MTK_PHY_DASN_DAC_IN1_D_MASK);
-+		phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+				 MTK_PHY_RG_ANA_CAL_RG1,
-+				 MTK_PHY_RG_ZCALEN_D);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		goto restore;
-+	}
-+
-+	lower_idx = TXRESERVE_MIN;
-+	upper_idx = TXRESERVE_MAX;
-+
-+	phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
-+	while ((upper_idx - lower_idx) > 1) {
-+		txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
-+		ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+				MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				txreserve_val << 12 | txreserve_val << 8 |
-+				txreserve_val << 4 | txreserve_val);
-+		if (ret == 1) {
-+			upper_idx = txreserve_val;
-+			upper_ret = ret;
-+		} else if (ret == 0) {
-+			lower_idx = txreserve_val;
-+			lower_ret = ret;
-+		} else {
-+			goto restore;
-+		}
-+	}
-+
-+	if (lower_idx == TXRESERVE_MIN) {
-+		lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      lower_idx << 12 | lower_idx << 8 |
-+				      lower_idx << 4 | lower_idx);
-+		ret = lower_ret;
-+	} else if (upper_idx == TXRESERVE_MAX) {
-+		upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+				      MTK_PHY_RXADC_CTRL_RG9,
-+				      MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+				      MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+				      MTK_PHY_DA_RX_PSBN_LP_MASK,
-+				      upper_idx << 12 | upper_idx << 8 |
-+				      upper_idx << 4 | upper_idx);
-+		ret = upper_ret;
-+	}
-+	if (ret < 0)
-+		goto restore;
-+
-+	/* We calibrate TX-VCM in different logic. Check upper index and then
-+	 * lower index. If this calibration is valid, apply lower index's result.
-+	 */
-+	ret = upper_ret - lower_ret;
-+	if (ret == 1) {
-+		ret = 0;
-+		/* Make sure we use upper_idx in our calibration system */
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  upper_idx << 12 | upper_idx << 8 |
-+			  upper_idx << 4 | upper_idx);
-+		phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
-+	} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
-+		   lower_ret == 1) {
-+		ret = 0;
-+		cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+			  MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+			  MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+			  MTK_PHY_DA_RX_PSBN_LP_MASK,
-+			  lower_idx << 12 | lower_idx << 8 |
-+			  lower_idx << 4 | lower_idx);
-+		phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
-+			    lower_idx);
-+	} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
-+		   lower_ret == 0) {
-+		ret = 0;
-+		phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
-+			    upper_idx);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+restore:
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ANA_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_TXVOS_CALEN);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+			   MTK_PHY_RG_ZCALEN_A);
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+			   MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
-+			   MTK_PHY_RG_ZCALEN_D);
-+
-+	return ret;
-+}
-+
-+static void mt798x_phy_common_finetune(struct phy_device *phydev)
-+{
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* EnabRandUpdTrig = 1 */
-+	__phy_write(phydev, 0x11, 0x2f00);
-+	__phy_write(phydev, 0x12, 0xe);
-+	__phy_write(phydev, 0x10, 0x8fb0);
-+
-+	/* NormMseLoThresh = 85 */
-+	__phy_write(phydev, 0x11, 0x55a0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x83aa);
-+
-+	/* TrFreeze = 0 */
-+	__phy_write(phydev, 0x11, 0x0);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9686);
-+
-+	/* SSTrKp1000Slv = 5 */
-+	__phy_write(phydev, 0x11, 0xbaef);
-+	__phy_write(phydev, 0x12, 0x2e);
-+	__phy_write(phydev, 0x10, 0x968c);
-+
-+	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-+	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-+	 */
-+	__phy_write(phydev, 0x11, 0xd10a);
-+	__phy_write(phydev, 0x12, 0x34);
-+	__phy_write(phydev, 0x10, 0x8f82);
-+
-+	/* VcoSlicerThreshBitsHigh */
-+	__phy_write(phydev, 0x11, 0x5555);
-+	__phy_write(phydev, 0x12, 0x55);
-+	__phy_write(phydev, 0x10, 0x8ec0);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-+
-+	/* rg_tr_lpf_cnt_val = 512 */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-+
-+	/* IIR2 related */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-+
-+	/* FFE peaking */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
-+		       MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-+
-+	/* Disable LDO pump */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-+	/* Adjust LDO output voltage */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[8] = { 0x01ce, 0x01c1,
-+		       0x020f, 0x0202,
-+		       0x03d0, 0x03c0,
-+		       0x0013, 0x0005 };
-+	int i, k;
-+
-+	/* 100M eye finetune:
-+	 * Keep middle level of TX MLT3 shapper as default.
-+	 * Only change TX MLT3 overshoot level here.
-+	 */
-+	for (k = 0, i = 1; i < 12; i++) {
-+		if (i % 3 == 0)
-+			continue;
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+	}
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+	__phy_write(phydev, 0x11, 0xc71);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 6 */
-+	__phy_write(phydev, 0x11, 0x600);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate = 1 */
-+	__phy_write(phydev, 0x11, 0x4c2a);
-+	__phy_write(phydev, 0x12, 0x3e);
-+	__phy_write(phydev, 0x10, 0x8fa4);
-+
-+	/* FfeUpdGainForce = 4 */
-+	__phy_write(phydev, 0x11, 0x240);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9680);
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7988_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-+			0x020d, 0x0206, 0x0384, 0x03d0,
-+			0x03c6, 0x030a, 0x0011, 0x0005 };
-+	int i;
-+
-+	/* Set default MLT3 shaper first */
-+	for (i = 0; i < 12; i++)
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-+
-+	/* TCT finetune */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-+
-+	/* Disable TX power saving */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-+	__phy_write(phydev, 0x11, 0x671);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
-+	/* ResetSyncOffset = 5 */
-+	__phy_write(phydev, 0x11, 0x500);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate is 1 at default on mt7988 */
-+
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-+	/* TxClkOffset = 2 */
-+	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-+		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt798x_phy_eee(struct phy_device *phydev)
-+{
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
-+		       MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
-+		       MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
-+		       FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+				  0xff));
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_TESTMUX_ADC_CTRL,
-+			   MTK_PHY_RG_TXEN_DIG_MASK);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-+
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+			   MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
-+		       MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
-+		       MTK_PHY_LPI_SLV_SEND_TX_EN,
-+		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-+		       MTK_PHY_LPI_TXPCS_LOC_RCV,
-+		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-+		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-+		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-+		       FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
-+		       MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+		       FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+				  0x33) |
-+		       MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
-+		       MTK_PHY_LPI_VCO_EEE_STG0_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
-+			 MTK_PHY_EEE_WAKE_MAS_INT_DC |
-+			 MTK_PHY_EEE_WAKE_SLV_INT_DC);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
-+		       MTK_PHY_SMI_DETCNT_MAX_MASK,
-+		       FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
-+		       MTK_PHY_SMI_DET_MAX_EN);
-+
-+	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
-+			 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
-+			 MTK_PHY_TREC_UPDATE_ENAB_CLR |
-+			 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
-+			 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* Regsigdet_sel_1000 = 0 */
-+	__phy_write(phydev, 0x11, 0xb);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9690);
-+
-+	/* REG_EEE_st2TrKf1000 = 3 */
-+	__phy_write(phydev, 0x11, 0x114f);
-+	__phy_write(phydev, 0x12, 0x2);
-+	__phy_write(phydev, 0x10, 0x969a);
-+
-+	/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
-+	__phy_write(phydev, 0x11, 0x3028);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x969e);
-+
-+	/* RegEEE_slv_wake_int_timer_tar = 8 */
-+	__phy_write(phydev, 0x11, 0x5010);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a0);
-+
-+	/* RegEEE_trfreeze_timer2 = 586 */
-+	__phy_write(phydev, 0x11, 0x24a);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96a8);
-+
-+	/* RegEEE100Stg1_tar = 16 */
-+	__phy_write(phydev, 0x11, 0x3210);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96b8);
-+
-+	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+	__phy_write(phydev, 0x11, 0x1463);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x96ca);
-+
-+	/* DfeTailEnableVgaThresh1000 = 27 */
-+	__phy_write(phydev, 0x11, 0x36);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8f80);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
-+		     FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-+
-+	__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
-+		     FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+		       MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+		       MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+		       FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-+}
-+
-+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		  u8 start_pair, u8 end_pair)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_OFFSET & TX_AMP have no SW calibration. */
-+		switch (cal_item) {
-+		case TX_VCM:
-+			ret = tx_vcm_cal_sw(phydev, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+	return 0;
-+}
-+
-+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     u8 start_pair, u8 end_pair, u32 *buf)
-+{
-+	u8 pair_n;
-+	int ret;
-+
-+	for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+		/* TX_VCM has no efuse calibration. */
-+		switch (cal_item) {
-+		case REXT:
-+			ret = rext_cal_efuse(phydev, buf);
-+			break;
-+		case TX_OFFSET:
-+			ret = tx_offset_cal_efuse(phydev, buf);
-+			break;
-+		case TX_AMP:
-+			ret = tx_amp_cal_efuse(phydev, buf);
-+			break;
-+		case TX_R50:
-+			ret = tx_r50_cal_efuse(phydev, buf, pair_n);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+		     enum CAL_MODE cal_mode, u8 start_pair,
-+		     u8 end_pair, u32 *buf)
-+{
-+	int ret;
-+
-+	switch (cal_mode) {
-+	case EFUSE_M:
-+		ret = cal_efuse(phydev, cal_item, start_pair,
-+				end_pair, buf);
-+		break;
-+	case SW_M:
-+		ret = cal_sw(phydev, cal_item, start_pair, end_pair);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (ret) {
-+		phydev_err(phydev, "cal %d failed\n", cal_item);
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mt798x_phy_calibration(struct phy_device *phydev)
-+{
-+	int ret = 0;
-+	u32 *buf;
-+	size_t len;
-+	struct nvmem_cell *cell;
-+
-+	cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
-+	if (IS_ERR(cell)) {
-+		if (PTR_ERR(cell) == -EPROBE_DEFER)
-+			return PTR_ERR(cell);
-+		return 0;
-+	}
-+
-+	buf = (u32 *)nvmem_cell_read(cell, &len);
-+	if (IS_ERR(buf))
-+		return PTR_ERR(buf);
-+	nvmem_cell_put(cell);
-+
-+	if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
-+		phydev_err(phydev, "invalid efuse data\n");
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
-+	if (ret)
-+		goto out;
-+	ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
-+	if (ret)
-+		goto out;
-+
-+out:
-+	kfree(buf);
-+	return ret;
-+}
-+
-+static int mt798x_phy_config_init(struct phy_device *phydev)
-+{
-+	switch (phydev->drv->phy_id) {
-+	case MTK_GPHY_ID_MT7981:
-+		mt7981_phy_finetune(phydev);
-+		break;
-+	case MTK_GPHY_ID_MT7988:
-+		mt7988_phy_finetune(phydev);
-+		break;
-+	}
-+
-+	mt798x_phy_common_finetune(phydev);
-+	mt798x_phy_eee(phydev);
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
-+static struct phy_driver mtk_socphy_driver[] = {
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-+		.name		= "MediaTek MT7981 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+	{
-+		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-+		.name		= "MediaTek MT7988 PHY",
-+		.config_init	= mt798x_phy_config_init,
-+		.config_intr	= genphy_no_config_intr,
-+		.handle_interrupt = genphy_handle_interrupt_no_ack,
-+		.probe		= mt798x_phy_calibration,
-+		.suspend	= genphy_suspend,
-+		.resume		= genphy_resume,
-+		.read_page	= mtk_socphy_read_page,
-+		.write_page	= mtk_socphy_write_page,
-+	},
-+};
-+
-+module_phy_driver(mtk_socphy_driver);
-+
-+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
-+	{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
-+	{ }
-+};
-+
-+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
---- a/drivers/net/phy/mediatek-ge.c
-+++ b/drivers/net/phy/mediatek-ge.c
-@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
- module_phy_driver(mtk_gephy_driver);
- 
- static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
--	{ PHY_ID_MATCH_VENDOR(0x03a29400) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29441) },
-+	{ PHY_ID_MATCH_EXACT(0x03a29412) },
- 	{ }
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch b/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch
deleted file mode 100644
index 286ce96a7d..0000000000
--- a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch
+++ /dev/null
@@ -1,524 +0,0 @@
-From c66937b0f8dbb4c6c043663c702b1053fb47fab2 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 14 Aug 2023 02:58:14 +0100
-Subject: [PATCH] net: phy: mediatek-ge-soc: support PHY LEDs
-
-Implement netdev trigger and primitive bliking offloading as well as
-simple set_brigthness function for both PHY LEDs of the in-SoC PHYs
-found in MT7981 and MT7988.
-
-For MT7988, read boottrap register and apply LED polarities accordingly
-to get uniform behavior from all LEDs on MT7988.
-This requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
-which should point to the syscon holding the boottrap register.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Link: https://lore.kernel.org/r/dc324d48c00cd7350f3a506eaa785324cae97372.1691977904.git.daniel@makrotopia.org
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 435 +++++++++++++++++++++++++++++-
- 1 file changed, 426 insertions(+), 9 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -1,11 +1,14 @@
- // SPDX-License-Identifier: GPL-2.0+
- #include <linux/bitfield.h>
-+#include <linux/bitmap.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/pinctrl/consumer.h>
- #include <linux/phy.h>
-+#include <linux/regmap.h>
- 
- #define MTK_GPHY_ID_MT7981			0x03a29461
- #define MTK_GPHY_ID_MT7988			0x03a29481
-@@ -208,9 +211,42 @@
- #define MTK_PHY_DA_TX_R50_PAIR_C		0x53f
- #define MTK_PHY_DA_TX_R50_PAIR_D		0x540
- 
-+/* Registers on MDIO_MMD_VEND2 */
-+#define MTK_PHY_LED0_ON_CTRL			0x24
-+#define MTK_PHY_LED1_ON_CTRL			0x26
-+#define   MTK_PHY_LED_ON_MASK			GENMASK(6, 0)
-+#define   MTK_PHY_LED_ON_LINK1000		BIT(0)
-+#define   MTK_PHY_LED_ON_LINK100		BIT(1)
-+#define   MTK_PHY_LED_ON_LINK10			BIT(2)
-+#define   MTK_PHY_LED_ON_LINKDOWN		BIT(3)
-+#define   MTK_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
-+#define   MTK_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
-+#define   MTK_PHY_LED_ON_FORCE_ON		BIT(6)
-+#define   MTK_PHY_LED_ON_POLARITY		BIT(14)
-+#define   MTK_PHY_LED_ON_ENABLE			BIT(15)
-+
-+#define MTK_PHY_LED0_BLINK_CTRL			0x25
-+#define MTK_PHY_LED1_BLINK_CTRL			0x27
-+#define   MTK_PHY_LED_BLINK_1000TX		BIT(0)
-+#define   MTK_PHY_LED_BLINK_1000RX		BIT(1)
-+#define   MTK_PHY_LED_BLINK_100TX		BIT(2)
-+#define   MTK_PHY_LED_BLINK_100RX		BIT(3)
-+#define   MTK_PHY_LED_BLINK_10TX		BIT(4)
-+#define   MTK_PHY_LED_BLINK_10RX		BIT(5)
-+#define   MTK_PHY_LED_BLINK_COLLISION		BIT(6)
-+#define   MTK_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
-+#define   MTK_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
-+#define   MTK_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
-+
-+#define MTK_PHY_LED1_DEFAULT_POLARITIES		BIT(1)
-+
- #define MTK_PHY_RG_BG_RASEL			0x115
- #define   MTK_PHY_RG_BG_RASEL_MASK		GENMASK(2, 0)
- 
-+/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
-+#define RG_GPIO_MISC_TPBANK0			0x6f0
-+#define   RG_GPIO_MISC_TPBANK0_BOOTMODE		GENMASK(11, 8)
-+
- /* These macro privides efuse parsing for internal phy. */
- #define EFS_DA_TX_I2MPB_A(x)			(((x) >> 0) & GENMASK(5, 0))
- #define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
-@@ -238,13 +274,6 @@ enum {
- 	PAIR_D,
- };
- 
--enum {
--	GPHY_PORT0,
--	GPHY_PORT1,
--	GPHY_PORT2,
--	GPHY_PORT3,
--};
--
- enum calibration_mode {
- 	EFUSE_K,
- 	SW_K
-@@ -263,6 +292,19 @@ enum CAL_MODE {
- 	SW_M
- };
- 
-+#define MTK_PHY_LED_STATE_FORCE_ON	0
-+#define MTK_PHY_LED_STATE_FORCE_BLINK	1
-+#define MTK_PHY_LED_STATE_NETDEV	2
-+
-+struct mtk_socphy_priv {
-+	unsigned long		led_state;
-+};
-+
-+struct mtk_socphy_shared {
-+	u32			boottrap;
-+	struct mtk_socphy_priv	priv[4];
-+};
-+
- static int mtk_socphy_read_page(struct phy_device *phydev)
- {
- 	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-@@ -1073,6 +1115,371 @@ static int mt798x_phy_config_init(struct
- 	return mt798x_phy_calibration(phydev);
- }
- 
-+static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
-+				    bool on)
-+{
-+	unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
-+	struct mtk_socphy_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (on)
-+		changed = !test_and_set_bit(bit_on, &priv->led_state);
-+	else
-+		changed = !!test_and_clear_bit(bit_on, &priv->led_state);
-+
-+	changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
-+					(index ? 16 : 0), &priv->led_state);
-+	if (changed)
-+		return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+				      MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
-+				      MTK_PHY_LED_ON_MASK,
-+				      on ? MTK_PHY_LED_ON_FORCE_ON : 0);
-+	else
-+		return 0;
-+}
-+
-+static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+				       bool blinking)
-+{
-+	unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
-+	struct mtk_socphy_priv *priv = phydev->priv;
-+	bool changed;
-+
-+	if (blinking)
-+		changed = !test_and_set_bit(bit_blink, &priv->led_state);
-+	else
-+		changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
-+
-+	changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
-+			      (index ? 16 : 0), &priv->led_state);
-+	if (changed)
-+		return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
-+				     MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
-+				     blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
-+	else
-+		return 0;
-+}
-+
-+static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
-+				    unsigned long *delay_on,
-+				    unsigned long *delay_off)
-+{
-+	bool blinking = false;
-+	int err = 0;
-+
-+	if (index > 1)
-+		return -EINVAL;
-+
-+	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+		blinking = true;
-+		*delay_on = 50;
-+		*delay_off = 50;
-+	}
-+
-+	err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
-+	if (err)
-+		return err;
-+
-+	return mt798x_phy_hw_led_on_set(phydev, index, false);
-+}
-+
-+static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
-+					 u8 index, enum led_brightness value)
-+{
-+	int err;
-+
-+	err = mt798x_phy_hw_led_blink_set(phydev, index, false);
-+	if (err)
-+		return err;
-+
-+	return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
-+}
-+
-+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+						 BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
-+						 BIT(TRIGGER_NETDEV_LINK)        |
-+						 BIT(TRIGGER_NETDEV_LINK_10)     |
-+						 BIT(TRIGGER_NETDEV_LINK_100)    |
-+						 BIT(TRIGGER_NETDEV_LINK_1000)   |
-+						 BIT(TRIGGER_NETDEV_RX)          |
-+						 BIT(TRIGGER_NETDEV_TX));
-+
-+static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+					  unsigned long rules)
-+{
-+	if (index > 1)
-+		return -EINVAL;
-+
-+	/* All combinations of the supported triggers are allowed */
-+	if (rules & ~supported_triggers)
-+		return -EOPNOTSUPP;
-+
-+	return 0;
-+};
-+
-+static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
-+					 unsigned long *rules)
-+{
-+	unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
-+	unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
-+	unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
-+	struct mtk_socphy_priv *priv = phydev->priv;
-+	int on, blink;
-+
-+	if (index > 1)
-+		return -EINVAL;
-+
-+	on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
-+			  index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
-+
-+	if (on < 0)
-+		return -EIO;
-+
-+	blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
-+			     index ? MTK_PHY_LED1_BLINK_CTRL :
-+				     MTK_PHY_LED0_BLINK_CTRL);
-+	if (blink < 0)
-+		return -EIO;
-+
-+	if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 |
-+		   MTK_PHY_LED_ON_LINK10)) ||
-+	    (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX |
-+		      MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX |
-+		      MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)))
-+		set_bit(bit_netdev, &priv->led_state);
-+	else
-+		clear_bit(bit_netdev, &priv->led_state);
-+
-+	if (on & MTK_PHY_LED_ON_FORCE_ON)
-+		set_bit(bit_on, &priv->led_state);
-+	else
-+		clear_bit(bit_on, &priv->led_state);
-+
-+	if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
-+		set_bit(bit_blink, &priv->led_state);
-+	else
-+		clear_bit(bit_blink, &priv->led_state);
-+
-+	if (!rules)
-+		return 0;
-+
-+	if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10))
-+		*rules |= BIT(TRIGGER_NETDEV_LINK);
-+
-+	if (on & MTK_PHY_LED_ON_LINK10)
-+		*rules |= BIT(TRIGGER_NETDEV_LINK_10);
-+
-+	if (on & MTK_PHY_LED_ON_LINK100)
-+		*rules |= BIT(TRIGGER_NETDEV_LINK_100);
-+
-+	if (on & MTK_PHY_LED_ON_LINK1000)
-+		*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
-+
-+	if (on & MTK_PHY_LED_ON_FDX)
-+		*rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
-+
-+	if (on & MTK_PHY_LED_ON_HDX)
-+		*rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
-+
-+	if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX))
-+		*rules |= BIT(TRIGGER_NETDEV_RX);
-+
-+	if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))
-+		*rules |= BIT(TRIGGER_NETDEV_TX);
-+
-+	return 0;
-+};
-+
-+static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
-+					 unsigned long rules)
-+{
-+	unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
-+	struct mtk_socphy_priv *priv = phydev->priv;
-+	u16 on = 0, blink = 0;
-+	int ret;
-+
-+	if (index > 1)
-+		return -EINVAL;
-+
-+	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+		on |= MTK_PHY_LED_ON_FDX;
-+
-+	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+		on |= MTK_PHY_LED_ON_HDX;
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
-+		on |= MTK_PHY_LED_ON_LINK10;
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
-+		on |= MTK_PHY_LED_ON_LINK100;
-+
-+	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
-+		on |= MTK_PHY_LED_ON_LINK1000;
-+
-+	if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+		blink |= MTK_PHY_LED_BLINK_10RX  |
-+			 MTK_PHY_LED_BLINK_100RX |
-+			 MTK_PHY_LED_BLINK_1000RX;
-+	}
-+
-+	if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+		blink |= MTK_PHY_LED_BLINK_10TX  |
-+			 MTK_PHY_LED_BLINK_100TX |
-+			 MTK_PHY_LED_BLINK_1000TX;
-+	}
-+
-+	if (blink || on)
-+		set_bit(bit_netdev, &priv->led_state);
-+	else
-+		clear_bit(bit_netdev, &priv->led_state);
-+
-+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+				MTK_PHY_LED1_ON_CTRL :
-+				MTK_PHY_LED0_ON_CTRL,
-+			     MTK_PHY_LED_ON_FDX     |
-+			     MTK_PHY_LED_ON_HDX     |
-+			     MTK_PHY_LED_ON_LINK10  |
-+			     MTK_PHY_LED_ON_LINK100 |
-+			     MTK_PHY_LED_ON_LINK1000,
-+			     on);
-+
-+	if (ret)
-+		return ret;
-+
-+	return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
-+				MTK_PHY_LED1_BLINK_CTRL :
-+				MTK_PHY_LED0_BLINK_CTRL, blink);
-+};
-+
-+static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
-+{
-+	struct mtk_socphy_shared *priv = phydev->shared->priv;
-+	u32 polarities;
-+
-+	if (led_num == 0)
-+		polarities = ~(priv->boottrap);
-+	else
-+		polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
-+
-+	if (polarities & BIT(phydev->mdio.addr))
-+		return true;
-+
-+	return false;
-+}
-+
-+static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
-+{
-+	struct pinctrl *pinctrl;
-+	int index;
-+
-+	/* Setup LED polarity according to bootstrap use of LED pins */
-+	for (index = 0; index < 2; ++index)
-+		phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+				MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
-+			       MTK_PHY_LED_ON_POLARITY,
-+			       mt7988_phy_led_get_polarity(phydev, index) ?
-+				MTK_PHY_LED_ON_POLARITY : 0);
-+
-+	/* Only now setup pinctrl to avoid bogus blinking */
-+	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
-+	if (IS_ERR(pinctrl))
-+		dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
-+
-+	return 0;
-+}
-+
-+static int mt7988_phy_probe_shared(struct phy_device *phydev)
-+{
-+	struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
-+	struct mtk_socphy_shared *shared = phydev->shared->priv;
-+	struct regmap *regmap;
-+	u32 reg;
-+	int ret;
-+
-+	/* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
-+	 * LED_C and LED_D respectively. At the same time those pins are used to
-+	 * bootstrap configuration of the reference clock source (LED_A),
-+	 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
-+	 * In practise this is done using a LED and a resistor pulling the pin
-+	 * either to GND or to VIO.
-+	 * The detected value at boot time is accessible at run-time using the
-+	 * TPBANK0 register located in the gpio base of the pinctrl, in order
-+	 * to read it here it needs to be referenced by a phandle called
-+	 * 'mediatek,pio' in the MDIO bus hosting the PHY.
-+	 * The 4 bits in TPBANK0 are kept as package shared data and are used to
-+	 * set LED polarity for each of the LED0.
-+	 */
-+	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
-+	if (IS_ERR(regmap))
-+		return PTR_ERR(regmap);
-+
-+	ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
-+	if (ret)
-+		return ret;
-+
-+	shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
-+
-+	return 0;
-+}
-+
-+static void mt798x_phy_leds_state_init(struct phy_device *phydev)
-+{
-+	int i;
-+
-+	for (i = 0; i < 2; ++i)
-+		mt798x_phy_led_hw_control_get(phydev, i, NULL);
-+}
-+
-+static int mt7988_phy_probe(struct phy_device *phydev)
-+{
-+	struct mtk_socphy_shared *shared;
-+	struct mtk_socphy_priv *priv;
-+	int err;
-+
-+	if (phydev->mdio.addr > 3)
-+		return -EINVAL;
-+
-+	err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
-+				    sizeof(struct mtk_socphy_shared));
-+	if (err)
-+		return err;
-+
-+	if (phy_package_probe_once(phydev)) {
-+		err = mt7988_phy_probe_shared(phydev);
-+		if (err)
-+			return err;
-+	}
-+
-+	shared = phydev->shared->priv;
-+	priv = &shared->priv[phydev->mdio.addr];
-+
-+	phydev->priv = priv;
-+
-+	mt798x_phy_leds_state_init(phydev);
-+
-+	err = mt7988_phy_fix_leds_polarities(phydev);
-+	if (err)
-+		return err;
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
-+static int mt7981_phy_probe(struct phy_device *phydev)
-+{
-+	struct mtk_socphy_priv *priv;
-+
-+	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
-+			    GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	phydev->priv = priv;
-+
-+	mt798x_phy_leds_state_init(phydev);
-+
-+	return mt798x_phy_calibration(phydev);
-+}
-+
- static struct phy_driver mtk_socphy_driver[] = {
- 	{
- 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-@@ -1080,11 +1487,16 @@ static struct phy_driver mtk_socphy_driv
- 		.config_init	= mt798x_phy_config_init,
- 		.config_intr	= genphy_no_config_intr,
- 		.handle_interrupt = genphy_handle_interrupt_no_ack,
--		.probe		= mt798x_phy_calibration,
-+		.probe		= mt7981_phy_probe,
- 		.suspend	= genphy_suspend,
- 		.resume		= genphy_resume,
- 		.read_page	= mtk_socphy_read_page,
- 		.write_page	= mtk_socphy_write_page,
-+		.led_blink_set	= mt798x_phy_led_blink_set,
-+		.led_brightness_set = mt798x_phy_led_brightness_set,
-+		.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
-+		.led_hw_control_set = mt798x_phy_led_hw_control_set,
-+		.led_hw_control_get = mt798x_phy_led_hw_control_get,
- 	},
- 	{
- 		PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-@@ -1092,11 +1504,16 @@ static struct phy_driver mtk_socphy_driv
- 		.config_init	= mt798x_phy_config_init,
- 		.config_intr	= genphy_no_config_intr,
- 		.handle_interrupt = genphy_handle_interrupt_no_ack,
--		.probe		= mt798x_phy_calibration,
-+		.probe		= mt7988_phy_probe,
- 		.suspend	= genphy_suspend,
- 		.resume		= genphy_resume,
- 		.read_page	= mtk_socphy_read_page,
- 		.write_page	= mtk_socphy_write_page,
-+		.led_blink_set	= mt798x_phy_led_blink_set,
-+		.led_brightness_set = mt798x_phy_led_brightness_set,
-+		.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
-+		.led_hw_control_set = mt798x_phy_led_hw_control_set,
-+		.led_hw_control_get = mt798x_phy_led_hw_control_get,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
deleted file mode 100644
index 76d8b0ef00..0000000000
--- a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 6 Apr 2023 23:36:50 +0100
-Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
-
-MAC drivers using phylink expect SGMII in-band-status to be switched off
-when attached to a PHY. Make sure this is the case also for mxl-gpy which
-keeps SGMII in-band-status in case of SGMII interface mode is used.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
- 1 file changed, 16 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/mxl-gpy.c
-+++ b/drivers/net/phy/mxl-gpy.c
-@@ -371,8 +371,11 @@ static bool gpy_2500basex_chk(struct phy
- 
- 	phydev->speed = SPEED_2500;
- 	phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
--		       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
-+	if (!phydev->phylink)
-+		phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+			       VSPEC1_SGMII_CTRL_ANEN, 0);
-+
- 	return true;
- }
- 
-@@ -396,6 +399,14 @@ static int gpy_config_aneg(struct phy_de
- 	u32 adv;
- 	int ret;
- 
-+	/* Disable SGMII auto-negotiation if using phylink */
-+	if (phydev->phylink) {
-+		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+				     VSPEC1_SGMII_CTRL_ANEN, 0);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
- 	if (phydev->autoneg == AUTONEG_DISABLE) {
- 		/* Configure half duplex with genphy_setup_forced,
- 		 * because genphy_c45_pma_setup_forced does not support.
-@@ -486,6 +497,8 @@ static void gpy_update_interface(struct
- 	switch (phydev->speed) {
- 	case SPEED_2500:
- 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+		if (phydev->phylink)
-+			break;
- 		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
- 				     VSPEC1_SGMII_CTRL_ANEN, 0);
- 		if (ret < 0)
-@@ -497,7 +510,7 @@ static void gpy_update_interface(struct
- 	case SPEED_100:
- 	case SPEED_10:
- 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
--		if (gpy_sgmii_aneg_en(phydev))
-+		if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
- 			break;
- 		/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
- 		 * if ANEG is disabled (in 2500-BaseX mode).
diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
deleted file mode 100644
index b4c07a4b1f..0000000000
--- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 28 Feb 2023 17:53:37 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig          |   7 ++
- drivers/net/phy/Makefile         |   1 +
- drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
- 3 files changed, 226 insertions(+)
- create mode 100644 drivers/net/phy/mediatek-2p5ge.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY
- 	  present in the SoCs efuse and will dynamically calibrate VCM
- 	  (common-mode voltage) during startup.
- 
-+config MEDIATEK_2P5G_PHY
-+	tristate "MediaTek 2.5G Ethernet PHY"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	default NET_MEDIATEK_SOC
-+	help
-+	  Supports the MediaTek 2.5G Ethernet PHY.
-+
- config MICREL_PHY
- 	tristate "Micrel PHYs"
- 	depends on PTP_1588_CLOCK_OPTIONAL
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_10G_PHY)	+= marvell
- obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY)	+= marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY)	+= mxl-gpy.o
-+obj-$(CONFIG_MEDIATEK_2P5G_PHY)	+= mediatek-2p5ge.o
- obj-$(CONFIG_MEDIATEK_GE_PHY)	+= mediatek-ge.o
- obj-$(CONFIG_MEDIATEK_GE_SOC_PHY)	+= mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY)	+= meson-gxl.o
diff --git a/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
deleted file mode 100644
index 5daa62b6b7..0000000000
--- a/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
+++ /dev/null
@@ -1,270 +0,0 @@
-From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
-Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 24 Jan 2024 02:27:04 +0000
-Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
-To: Daniel Golle <daniel@makrotopia.org>,
-    Qingfang Deng <dqfext@gmail.com>,
-    SkyLake Huang <SkyLake.Huang@mediatek.com>,
-    Andrew Lunn <andrew@lunn.ch>,
-    Heiner Kallweit <hkallweit1@gmail.com>,
-    Russell King <linux@armlinux.org.uk>,
-    David S. Miller <davem@davemloft.net>,
-    Eric Dumazet <edumazet@google.com>,
-    Jakub Kicinski <kuba@kernel.org>,
-    Paolo Abeni <pabeni@redhat.com>,
-    Matthias Brugger <matthias.bgg@gmail.com>,
-    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-    netdev@vger.kernel.org,
-    linux-kernel@vger.kernel.org,
-    linux-arm-kernel@lists.infradead.org,
-    linux-mediatek@lists.infradead.org
-
-Sync initialization and calibration routines with MediaTek's reference
-driver. Improves compliance and resolves link stability issues with
-CH340 IoT devices connected to MT798x built-in PHYs.
-
-Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
- 1 file changed, 81 insertions(+), 66 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy
- 	u16 reg, val;
- 
- 	if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
--		bias = -2;
-+		bias = -1;
- 
- 	val = clamp_val(bias + tx_r50_cal_val, 0, 63);
- 
-@@ -707,6 +707,11 @@ restore:
- static void mt798x_phy_common_finetune(struct phy_device *phydev)
- {
- 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+	__phy_write(phydev, 0x11, 0xc71);
-+	__phy_write(phydev, 0x12, 0xc);
-+	__phy_write(phydev, 0x10, 0x8fae);
-+
- 	/* EnabRandUpdTrig = 1 */
- 	__phy_write(phydev, 0x11, 0x2f00);
- 	__phy_write(phydev, 0x12, 0xe);
-@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x83aa);
- 
--	/* TrFreeze = 0 */
-+	/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
-+	__phy_write(phydev, 0x11, 0x240);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x9680);
-+
-+	/* TrFreeze = 0 (mt7988 default) */
- 	__phy_write(phydev, 0x11, 0x0);
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x9686);
- 
-+	/* SSTrKp100 = 5 */
-+	/* SSTrKf100 = 6 */
-+	/* SSTrKp1000Mas = 5 */
-+	/* SSTrKf1000Mas = 6 */
- 	/* SSTrKp1000Slv = 5 */
-+	/* SSTrKf1000Slv = 6 */
- 	__phy_write(phydev, 0x11, 0xbaef);
- 	__phy_write(phydev, 0x12, 0x2e);
- 	__phy_write(phydev, 0x10, 0x968c);
-+	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+	u16 val[8] = { 0x01ce, 0x01c1,
-+		       0x020f, 0x0202,
-+		       0x03d0, 0x03c0,
-+		       0x0013, 0x0005 };
-+	int i, k;
-+
-+	/* 100M eye finetune:
-+	 * Keep middle level of TX MLT3 shapper as default.
-+	 * Only change TX MLT3 overshoot level here.
-+	 */
-+	for (k = 0, i = 1; i < 12; i++) {
-+		if (i % 3 == 0)
-+			continue;
-+		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+	}
-+
-+	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+	/* ResetSyncOffset = 6 */
-+	__phy_write(phydev, 0x11, 0x600);
-+	__phy_write(phydev, 0x12, 0x0);
-+	__phy_write(phydev, 0x10, 0x8fc0);
-+
-+	/* VgaDecRate = 1 */
-+	__phy_write(phydev, 0x11, 0x4c2a);
-+	__phy_write(phydev, 0x12, 0x3e);
-+	__phy_write(phydev, 0x10, 0x8fa4);
- 
- 	/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- 	 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s
- 	__phy_write(phydev, 0x10, 0x8ec0);
- 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- 
--	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
- 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- 		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- 		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s
- 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
- }
- 
--static void mt7981_phy_finetune(struct phy_device *phydev)
--{
--	u16 val[8] = { 0x01ce, 0x01c1,
--		       0x020f, 0x0202,
--		       0x03d0, 0x03c0,
--		       0x0013, 0x0005 };
--	int i, k;
--
--	/* 100M eye finetune:
--	 * Keep middle level of TX MLT3 shapper as default.
--	 * Only change TX MLT3 overshoot level here.
--	 */
--	for (k = 0, i = 1; i < 12; i++) {
--		if (i % 3 == 0)
--			continue;
--		phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
--	}
--
--	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
--	__phy_write(phydev, 0x11, 0xc71);
--	__phy_write(phydev, 0x12, 0xc);
--	__phy_write(phydev, 0x10, 0x8fae);
--
--	/* ResetSyncOffset = 6 */
--	__phy_write(phydev, 0x11, 0x600);
--	__phy_write(phydev, 0x12, 0x0);
--	__phy_write(phydev, 0x10, 0x8fc0);
--
--	/* VgaDecRate = 1 */
--	__phy_write(phydev, 0x11, 0x4c2a);
--	__phy_write(phydev, 0x12, 0x3e);
--	__phy_write(phydev, 0x10, 0x8fa4);
--
--	/* FfeUpdGainForce = 4 */
--	__phy_write(phydev, 0x11, 0x240);
--	__phy_write(phydev, 0x12, 0x0);
--	__phy_write(phydev, 0x10, 0x9680);
--
--	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
--}
--
- static void mt7988_phy_finetune(struct phy_device *phydev)
- {
- 	u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p
- 	/* TCT finetune */
- 	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- 
--	/* Disable TX power saving */
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
--		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
--
- 	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--
--	/* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
--	__phy_write(phydev, 0x11, 0x671);
--	__phy_write(phydev, 0x12, 0xc);
--	__phy_write(phydev, 0x10, 0x8fae);
--
- 	/* ResetSyncOffset = 5 */
- 	__phy_write(phydev, 0x11, 0x500);
- 	__phy_write(phydev, 0x12, 0x0);
-@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p
- 
- 	/* VgaDecRate is 1 at default on mt7988 */
- 
--	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+	/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
-+	 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
-+	 */
-+	__phy_write(phydev, 0x11, 0xb90a);
-+	__phy_write(phydev, 0x12, 0x6f);
-+	__phy_write(phydev, 0x10, 0x8f82);
-+
-+	/* RemAckCntLimitCtrl = 1 */
-+	__phy_write(phydev, 0x11, 0xfbba);
-+	__phy_write(phydev, 0x12, 0xc3);
-+	__phy_write(phydev, 0x10, 0x87f8);
- 
--	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
--	/* TxClkOffset = 2 */
--	__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
--		     FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
- 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+	/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+		       MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+		       BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
-+
-+	/* rg_tr_lpf_cnt_val = 1023 */
-+	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
- }
- 
- static void mt798x_phy_eee(struct phy_device *phydev)
-@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de
- 		       MTK_PHY_LPI_SLV_SEND_TX_EN,
- 		       FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- 
--	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
--		       MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
--		       MTK_PHY_LPI_TXPCS_LOC_RCV,
--		       FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+	/* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
-+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+			   MTK_PHY_LPI_TXPCS_LOC_RCV);
- 
-+	/* This also fixes some IoT issues, such as CH340 */
- 	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
- 		       MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
- 		       FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x9690);
- 
--	/* REG_EEE_st2TrKf1000 = 3 */
-+	/* REG_EEE_st2TrKf1000 = 2 */
- 	__phy_write(phydev, 0x11, 0x114f);
- 	__phy_write(phydev, 0x12, 0x2);
- 	__phy_write(phydev, 0x10, 0x969a);
-@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x96b8);
- 
--	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+	/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
- 	__phy_write(phydev, 0x11, 0x1463);
- 	__phy_write(phydev, 0x12, 0x0);
- 	__phy_write(phydev, 0x10, 0x96ca);
-@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d
- 	if (err)
- 		return err;
- 
-+	/* Disable TX power saving at probing to:
-+	 * 1. Meet common mode compliance test criteria
-+	 * 2. Make sure that TX-VCM calibration works fine
-+	 */
-+	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+		       MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
- 	return mt798x_phy_calibration(phydev);
- }
- 
diff --git a/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch b/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch
deleted file mode 100644
index 51f2a197e9..0000000000
--- a/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Sat, 23 Mar 2024 20:21:14 +0100
-Subject: [PATCH] net: phy: add Airoha EN8801SC PHY
-
-Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a
-modified version of MTK SDK driver.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/phy/Kconfig  | 5 +++++
- drivers/net/phy/Makefile | 1 +
- 2 files changed, 6 insertions(+)
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -143,6 +143,11 @@ endif # RTL8366_SMI
- 
- comment "MII PHY device drivers"
- 
-+config AIROHA_EN8801SC_PHY
-+	tristate "Airoha EN8801SC Gigabit PHY"
-+	help
-+	  Currently supports the Airoha EN8801SC PHY.
-+
- config AIR_EN8811H_PHY
- 	tristate "Airoha EN8811H 2.5 Gigabit PHY"
- 	help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -47,6 +47,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
- 
- obj-$(CONFIG_ADIN_PHY)		+= adin.o
- obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
-+obj-$(CONFIG_AIROHA_EN8801SC_PHY)   += en8801sc.o
- obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
diff --git a/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch
deleted file mode 100644
index 0c73d520b4..0000000000
--- a/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch
+++ /dev/null
@@ -1,23 +0,0 @@
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data
- 	.has_ck_26m_sel = true,
- };
- 
-+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
-+	.num_pwms = 2,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+};
-+
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
-@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
diff --git a/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch
deleted file mode 100644
index 72feecadb1..0000000000
--- a/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From 967da67a745fb73fd0fc7aa61fd197b76fceb273 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 21 Apr 2023 00:23:21 +0100
-Subject: [PATCH] pwm: mediatek: Add support for MT7981
-
-The PWM unit on MT7981 uses different register offsets than previous
-MediaTek PWM units. Add support for these new offsets and add support
-for PWM on MT7981 which has 3 PWM channels, one of them is typically
-used for a temperature controlled fan.
-While at it, also reorder pwm_mediatek_of_data entries to restore
-alphabetic order.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
----
- drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++--------
- 1 file changed, 31 insertions(+), 8 deletions(-)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
- 	unsigned int num_pwms;
- 	bool pwm45_fixup;
- 	bool has_ck_26m_sel;
-+	const unsigned int *reg_offset;
- };
- 
- /**
-@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
- 	const struct pwm_mediatek_of_data *soc;
- };
- 
--static const unsigned int pwm_mediatek_reg_offset[] = {
-+static const unsigned int mtk_pwm_reg_offset_v1[] = {
- 	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
- };
- 
-+static const unsigned int mtk_pwm_reg_offset_v2[] = {
-+	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
-+};
-+
- static inline struct pwm_mediatek_chip *
- to_pwm_mediatek_chip(struct pwm_chip *chip)
- {
-@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
- 				       unsigned int num, unsigned int offset,
- 				       u32 value)
- {
--	writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
-+	writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
- }
- 
- static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
-@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data
- 	.num_pwms = 8,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt6795_pwm_data = {
- 	.num_pwms = 7,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7622_pwm_data = {
- 	.num_pwms = 6,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7623_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7628_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = true,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt7629_pwm_data = {
- 	.num_pwms = 1,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
--static const struct pwm_mediatek_of_data mt8183_pwm_data = {
--	.num_pwms = 4,
-+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
-+	.num_pwms = 3,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v2,
- };
- 
--static const struct pwm_mediatek_of_data mt8365_pwm_data = {
--	.num_pwms = 3,
-+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
-+	.num_pwms = 2,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
--static const struct pwm_mediatek_of_data mt7986_pwm_data = {
--	.num_pwms = 2,
-+static const struct pwm_mediatek_of_data mt8183_pwm_data = {
-+	.num_pwms = 4,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
-+};
-+
-+static const struct pwm_mediatek_of_data mt8365_pwm_data = {
-+	.num_pwms = 3,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- 	.num_pwms = 5,
- 	.pwm45_fixup = false,
- 	.has_ck_26m_sel = true,
-+	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
- static const struct of_device_id pwm_mediatek_of_match[] = {
-@@ -348,6 +370,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- 	{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
diff --git a/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch
deleted file mode 100644
index 00543a1bb1..0000000000
--- a/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 14 Feb 2024 15:04:54 +0100
-Subject: [PATCH] pwm: mediatek: add support for MT7988
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
-interfaces.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
-Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
----
- drivers/pwm/pwm-mediatek.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -342,6 +342,13 @@ static const struct pwm_mediatek_of_data
- 	.reg_offset = mtk_pwm_reg_offset_v1,
- };
- 
-+static const struct pwm_mediatek_of_data mt7988_pwm_data = {
-+	.num_pwms = 8,
-+	.pwm45_fixup = false,
-+	.has_ck_26m_sel = false,
-+	.reg_offset = mtk_pwm_reg_offset_v2,
-+};
-+
- static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- 	.num_pwms = 4,
- 	.pwm45_fixup = false,
-@@ -372,6 +379,7 @@ static const struct of_device_id pwm_med
- 	{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
- 	{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
- 	{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
-+	{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
- 	{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- 	{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
- 	{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
diff --git a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
deleted file mode 100644
index f130fdbc56..0000000000
--- a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:12 +0100
-Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias
- functions
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
-and mtk_pinconf_bias_get_combo, and make the functions able to support
-almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
-
-This patch enables pinctrl_moore to support these functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++----
- 1 file changed, 42 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -8,6 +8,7 @@
-  *
-  */
- 
-+#include <dt-bindings/pinctrl/mt65xx.h>
- #include <linux/gpio/driver.h>
- #include "pinctrl-moore.h"
- 
-@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr
- {
- 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
- 	u32 param = pinconf_to_config_param(*config);
--	int val, val2, err, reg, ret = 1;
-+	int val, val2, err, pullup, reg, ret = 1;
- 	const struct mtk_pin_desc *desc;
- 
- 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr
- 
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
--		if (hw->soc->bias_disable_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_disable_get) {
- 			err = hw->soc->bias_disable_get(hw, desc, &ret);
- 			if (err)
- 				return err;
-@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_UP:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (!pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 1, &ret);
- 			if (err)
- 				return err;
-@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr
- 		}
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_DOWN:
--		if (hw->soc->bias_get) {
-+		if (hw->soc->bias_get_combo) {
-+			err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+			if (err)
-+				return err;
-+			if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+				return -EINVAL;
-+			if (pullup)
-+				return -EINVAL;
-+		} else if (hw->soc->bias_get) {
- 			err = hw->soc->bias_get(hw, desc, 0, &ret);
- 			if (err)
- 				return err;
-@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr
- 
- 		switch (param) {
- 		case PIN_CONFIG_BIAS_DISABLE:
--			if (hw->soc->bias_disable_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_disable_set) {
- 				err = hw->soc->bias_disable_set(hw, desc);
- 				if (err)
- 					return err;
-@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_UP:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 1, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 1);
- 				if (err)
- 					return err;
-@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr
- 			}
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_DOWN:
--			if (hw->soc->bias_set) {
-+			if (hw->soc->bias_set_combo) {
-+				err = hw->soc->bias_set_combo(hw, desc, 0, arg);
-+				if (err)
-+					return err;
-+			} else if (hw->soc->bias_set) {
- 				err = hw->soc->bias_set(hw, desc, 0);
- 				if (err)
- 					return err;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
deleted file mode 100644
index 694b73a2b1..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001
-From: Randy Dunlap <rdunlap@infradead.org>
-Date: Thu, 12 Jan 2023 22:44:49 -0800
-Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function
- name
-
-Use the correct function name in a kernel-doc comment to prevent
-a warning:
-
-drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead
-
-Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
-Cc: "Rafael J. Wysocki" <rafael@kernel.org>
-Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
-Cc: Amit Kucheria <amitk@kernel.org>
-Cc: Zhang Rui <rui.zhang@intel.com>
-Cc: Matthias Brugger <matthias.bgg@gmail.com>
-Cc: linux-pm@vger.kernel.org
-Cc: linux-arm-kernel@lists.infradead.org
-Cc: linux-mediatek@lists.infradead.org
-Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8
- };
- 
- /**
-- * raw_to_mcelsius - convert a raw ADC value to mcelsius
-+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-  * @sensno:	sensor number
-  * @raw:	raw ADC value
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
deleted file mode 100644
index aaed9d7e90..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Wed, 18 Jan 2023 16:37:47 +0800
-Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat
- 	int ret, i, ctrl_id;
- 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
- 	struct mtk_thermal *mt;
--	struct resource *res;
- 	u64 auxadc_phys_base, apmixed_phys_base;
- 	struct thermal_zone_device *tzdev;
- 	void __iomem *apmixed_base, *auxadc_base;
-@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat
- 	if (IS_ERR(mt->clk_auxadc))
- 		return PTR_ERR(mt->clk_auxadc);
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
-+	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- 	if (IS_ERR(mt->thermal_base))
- 		return PTR_ERR(mt->thermal_base);
- 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
deleted file mode 100644
index 215b0fd7de..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 15:40:39 +0000
-Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for
- raw_to_mcelsius
-
-Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
-raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
-pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
-probe function.
-
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -292,6 +292,8 @@ struct mtk_thermal {
- 
- 	const struct mtk_thermal_data *conf;
- 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
- };
- 
- /* MT8183 thermal sensor data */
-@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
- 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
- 		raw = readl(mt->thermal_base + conf->msr[i]);
- 
--		if (mt->conf->version == MTK_THERMAL_V1) {
--			temp = raw_to_mcelsius_v1(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		} else {
--			temp = raw_to_mcelsius_v2(
--				mt, conf->bank_data[bank->id].sensors[i], raw);
--		}
-+		temp = mt->raw_to_mcelsius(
-+			mt, conf->bank_data[bank->id].sensors[i], raw);
-+
- 
- 		/*
- 		 * The first read of a sensor often contains very high bogus
-@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
-+	if (mt->conf->version == MTK_THERMAL_V1)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
- 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
deleted file mode 100644
index ef2006775a..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 15:40:58 +0000
-Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981
-
-Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
-Brings code to assign values from efuse as well as new function to
-convert raw temperature to millidegree celsius, as found in MediaTek's
-SDK sources (but cleaned up and de-duplicated)
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++--
- 1 file changed, 124 insertions(+), 4 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -150,6 +150,20 @@
- #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
- #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
- 
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
-+
- enum {
- 	VTS1,
- 	VTS2,
-@@ -163,6 +177,7 @@ enum {
- enum mtk_thermal_version {
- 	MTK_THERMAL_V1 = 1,
- 	MTK_THERMAL_V2,
-+	MTK_THERMAL_V3,
- };
- 
- /* MT2701 thermal sensors */
-@@ -245,6 +260,27 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor  */
- #define MT8183_CALIBRATION	153
- 
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS		1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES		1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE	1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1			0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7986_CALIBRATION		165
-+
- struct mtk_thermal;
- 
- struct thermal_bank_cfg {
-@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
- static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
- static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
- 
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
- /*
-  * The MT8173 thermal controller has four banks. Each bank can read up to
-  * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
- 	.version = MTK_THERMAL_V1,
- };
- 
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7986_NUM_ZONES,
-+	.num_sensors = MT7986_NUM_SENSORS,
-+	.vts_index = mt7986_vts_index,
-+	.cali_val = MT7986_CALIBRATION,
-+	.num_controller = MT7986_NUM_CONTROLLER,
-+	.controller_offset = mt7986_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7986_bank_data,
-+		},
-+	},
-+	.msr = mt7986_msr,
-+	.adcpnp = mt7986_adcpnp,
-+	.sensor_mux_values = mt7986_mux_values,
-+	.version = MTK_THERMAL_V3,
-+};
-+
- /**
-  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
- 	return (format_2 - tmp) * 100;
- }
- 
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	tmp = 100000 * 15 / 16 * 10000;
-+	tmp /= 4096 - 512 + mt->adc_ge;
-+	tmp /= 1490;
-+	tmp *= raw - mt->vts[sensno] - 2900;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
- /**
-  * mtk_thermal_get_bank - get bank
-  * @bank:	The bank
-@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
- 	return 0;
- }
- 
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V3(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+		mt->o_slope = 0;
-+
-+	return 0;
-+}
-+
- static int mtk_thermal_get_calibration_data(struct device *dev,
- 					    struct mtk_thermal *mt)
- {
-@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
- 
- 	/* Start with default values */
- 	mt->adc_ge = 512;
-+	mt->adc_oe = 512;
- 	for (i = 0; i < mt->conf->num_sensors; i++)
- 		mt->vts[i] = 260;
- 	mt->degc_cali = 40;
-@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
- 		goto out;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V1)
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
- 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
--	else
-+		break;
-+	case MTK_THERMAL_V2:
- 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+		break;
-+	case MTK_THERMAL_V3:
-+		ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
- 
- 	if (ret) {
- 		dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
- 		.data = (void *)&mt7622_thermal_data,
- 	},
- 	{
-+		.compatible = "mediatek,mt7986-thermal",
-+		.data = (void *)&mt7986_thermal_data,
-+	},
-+	{
- 		.compatible = "mediatek,mt8183-thermal",
- 		.data = (void *)&mt8183_thermal_data,
- 	}, {
-@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_auxadc;
- 	}
- 
--	if (mt->conf->version == MTK_THERMAL_V2) {
-+	if (mt->conf->version != MTK_THERMAL_V1) {
- 		mtk_thermal_turn_on_buffer(apmixed_base);
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 	}
- 
- 	if (mt->conf->version == MTK_THERMAL_V1)
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
--	else
-+	else if (mt->conf->version == MTK_THERMAL_V2)
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
- 
- 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- 		for (i = 0; i < mt->conf->num_banks; i++)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
deleted file mode 100644
index e102a338cd..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch
+++ /dev/null
@@ -1,2602 +0,0 @@
-From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:23 +0100
-Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek
- folder
-
-Add MediaTek proprietary folder to upstream more thermal zone and cooler
-drivers, relocate the original thermal controller driver to it, and rename it
-as "auxadc_thermal.c" to show its purpose more clearly.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/Kconfig                       | 14 ++++---------
- drivers/thermal/Makefile                      |  2 +-
- drivers/thermal/mediatek/Kconfig              | 21 +++++++++++++++++++
- drivers/thermal/mediatek/Makefile             |  1 +
- .../auxadc_thermal.c}                         |  2 +-
- 5 files changed, 28 insertions(+), 12 deletions(-)
- create mode 100644 drivers/thermal/mediatek/Kconfig
- create mode 100644 drivers/thermal/mediatek/Makefile
- rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%)
-
---- a/drivers/thermal/Kconfig
-+++ b/drivers/thermal/Kconfig
-@@ -412,16 +412,10 @@ config DA9062_THERMAL
- 	  zone.
- 	  Compatible with the DA9062 and DA9061 PMICs.
- 
--config MTK_THERMAL
--	tristate "Temperature sensor driver for mediatek SoCs"
--	depends on ARCH_MEDIATEK || COMPILE_TEST
--	depends on HAS_IOMEM
--	depends on NVMEM || NVMEM=n
--	depends on RESET_CONTROLLER
--	default y
--	help
--	  Enable this option if you want to have support for thermal management
--	  controller present in Mediatek SoCs
-+menu "Mediatek thermal drivers"
-+depends on ARCH_MEDIATEK || COMPILE_TEST
-+source "drivers/thermal/mediatek/Kconfig"
-+endmenu
- 
- config AMLOGIC_THERMAL
- 	tristate "Amlogic Thermal Support"
---- a/drivers/thermal/Makefile
-+++ b/drivers/thermal/Makefile
-@@ -55,7 +55,7 @@ obj-y				+= st/
- obj-y				+= qcom/
- obj-y				+= tegra/
- obj-$(CONFIG_HISI_THERMAL)     += hisi_thermal.o
--obj-$(CONFIG_MTK_THERMAL)	+= mtk_thermal.o
-+obj-y				+= mediatek/
- obj-$(CONFIG_GENERIC_ADC_THERMAL)	+= thermal-generic-adc.o
- obj-$(CONFIG_UNIPHIER_THERMAL)	+= uniphier_thermal.o
- obj-$(CONFIG_AMLOGIC_THERMAL)     += amlogic_thermal.o
---- /dev/null
-+++ b/drivers/thermal/mediatek/Kconfig
-@@ -0,0 +1,21 @@
-+config MTK_THERMAL
-+	tristate "MediaTek thermal drivers"
-+	depends on THERMAL_OF
-+	help
-+	  This is the option for MediaTek thermal software solutions.
-+	  Please enable corresponding options to get temperature
-+	  information from thermal sensors or turn on throttle
-+	  mechaisms for thermal mitigation.
-+
-+if MTK_THERMAL
-+
-+config MTK_SOC_THERMAL
-+	tristate "AUXADC temperature sensor driver for MediaTek SoCs"
-+	depends on HAS_IOMEM
-+	help
-+	  Enable this option if you want to get SoC temperature
-+	  information for MediaTek platforms.
-+	  This driver configures thermal controllers to collect
-+	  temperature via AUXADC interface.
-+
-+endif
---- /dev/null
-+++ b/drivers/thermal/mediatek/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
---- a/drivers/thermal/mtk_thermal.c
-+++ /dev/null
-@@ -1,1254 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0-only
--/*
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Hanyi Wu <hanyi.wu@mediatek.com>
-- *         Sascha Hauer <s.hauer@pengutronix.de>
-- *         Dawei Chien <dawei.chien@mediatek.com>
-- *         Louis Yu <louis.yu@mediatek.com>
-- */
--
--#include <linux/clk.h>
--#include <linux/delay.h>
--#include <linux/interrupt.h>
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/nvmem-consumer.h>
--#include <linux/of.h>
--#include <linux/of_address.h>
--#include <linux/of_device.h>
--#include <linux/platform_device.h>
--#include <linux/slab.h>
--#include <linux/io.h>
--#include <linux/thermal.h>
--#include <linux/reset.h>
--#include <linux/types.h>
--
--#include "thermal_hwmon.h"
--
--/* AUXADC Registers */
--#define AUXADC_CON1_SET_V	0x008
--#define AUXADC_CON1_CLR_V	0x00c
--#define AUXADC_CON2_V		0x010
--#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
--
--#define APMIXED_SYS_TS_CON1	0x604
--
--/* Thermal Controller Registers */
--#define TEMP_MONCTL0		0x000
--#define TEMP_MONCTL1		0x004
--#define TEMP_MONCTL2		0x008
--#define TEMP_MONIDET0		0x014
--#define TEMP_MONIDET1		0x018
--#define TEMP_MSRCTL0		0x038
--#define TEMP_MSRCTL1		0x03c
--#define TEMP_AHBPOLL		0x040
--#define TEMP_AHBTO		0x044
--#define TEMP_ADCPNP0		0x048
--#define TEMP_ADCPNP1		0x04c
--#define TEMP_ADCPNP2		0x050
--#define TEMP_ADCPNP3		0x0b4
--
--#define TEMP_ADCMUX		0x054
--#define TEMP_ADCEN		0x060
--#define TEMP_PNPMUXADDR		0x064
--#define TEMP_ADCMUXADDR		0x068
--#define TEMP_ADCENADDR		0x074
--#define TEMP_ADCVALIDADDR	0x078
--#define TEMP_ADCVOLTADDR	0x07c
--#define TEMP_RDCTRL		0x080
--#define TEMP_ADCVALIDMASK	0x084
--#define TEMP_ADCVOLTAGESHIFT	0x088
--#define TEMP_ADCWRITECTRL	0x08c
--#define TEMP_MSR0		0x090
--#define TEMP_MSR1		0x094
--#define TEMP_MSR2		0x098
--#define TEMP_MSR3		0x0B8
--
--#define TEMP_SPARE0		0x0f0
--
--#define TEMP_ADCPNP0_1          0x148
--#define TEMP_ADCPNP1_1          0x14c
--#define TEMP_ADCPNP2_1          0x150
--#define TEMP_MSR0_1             0x190
--#define TEMP_MSR1_1             0x194
--#define TEMP_MSR2_1             0x198
--#define TEMP_ADCPNP3_1          0x1b4
--#define TEMP_MSR3_1             0x1B8
--
--#define PTPCORESEL		0x400
--
--#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
--
--#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
--#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
--
--#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
--
--#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
--#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
--
--#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
--#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
--
--/* MT8173 thermal sensors */
--#define MT8173_TS1	0
--#define MT8173_TS2	1
--#define MT8173_TS3	2
--#define MT8173_TS4	3
--#define MT8173_TSABB	4
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT8173_TEMP_AUXADC_CHANNEL	11
--
--/* The total number of temperature sensors in the MT8173 */
--#define MT8173_NUM_SENSORS		5
--
--/* The number of banks in the MT8173 */
--#define MT8173_NUM_ZONES		4
--
--/* The number of sensing points per bank */
--#define MT8173_NUM_SENSORS_PER_ZONE	4
--
--/* The number of controller in the MT8173 */
--#define MT8173_NUM_CONTROLLER		1
--
--/* The calibration coefficient of sensor  */
--#define MT8173_CALIBRATION	165
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-- * MT8183 has 6 sensors and needs 6 VTS calibration data.
-- * MT8173 has 5 sensors and needs 5 VTS calibration data.
-- * MT2701 has 3 sensors and needs 3 VTS calibration data.
-- * MT2712 has 4 sensors and needs 4 VTS calibration data.
-- */
--#define CALIB_BUF0_VALID_V1		BIT(0)
--#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
--#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
--#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
--#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
--#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
--#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
--#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
--#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
--#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros could be used for MT7622.
-- */
--#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
--#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
--#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
--#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
--#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
--#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
--#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
--#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros can be used for MT7981 and MT7986.
-- */
--#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
--#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
--#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
--#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
--#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
--#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
--#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
--#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
--
--enum {
--	VTS1,
--	VTS2,
--	VTS3,
--	VTS4,
--	VTS5,
--	VTSABB,
--	MAX_NUM_VTS,
--};
--
--enum mtk_thermal_version {
--	MTK_THERMAL_V1 = 1,
--	MTK_THERMAL_V2,
--	MTK_THERMAL_V3,
--};
--
--/* MT2701 thermal sensors */
--#define MT2701_TS1	0
--#define MT2701_TS2	1
--#define MT2701_TSABB	2
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT2701_TEMP_AUXADC_CHANNEL	11
--
--/* The total number of temperature sensors in the MT2701 */
--#define MT2701_NUM_SENSORS	3
--
--/* The number of sensing points per bank */
--#define MT2701_NUM_SENSORS_PER_ZONE	3
--
--/* The number of controller in the MT2701 */
--#define MT2701_NUM_CONTROLLER		1
--
--/* The calibration coefficient of sensor  */
--#define MT2701_CALIBRATION	165
--
--/* MT2712 thermal sensors */
--#define MT2712_TS1	0
--#define MT2712_TS2	1
--#define MT2712_TS3	2
--#define MT2712_TS4	3
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT2712_TEMP_AUXADC_CHANNEL	11
--
--/* The total number of temperature sensors in the MT2712 */
--#define MT2712_NUM_SENSORS	4
--
--/* The number of sensing points per bank */
--#define MT2712_NUM_SENSORS_PER_ZONE	4
--
--/* The number of controller in the MT2712 */
--#define MT2712_NUM_CONTROLLER		1
--
--/* The calibration coefficient of sensor  */
--#define MT2712_CALIBRATION	165
--
--#define MT7622_TEMP_AUXADC_CHANNEL	11
--#define MT7622_NUM_SENSORS		1
--#define MT7622_NUM_ZONES		1
--#define MT7622_NUM_SENSORS_PER_ZONE	1
--#define MT7622_TS1	0
--#define MT7622_NUM_CONTROLLER		1
--
--/* The maximum number of banks */
--#define MAX_NUM_ZONES		8
--
--/* The calibration coefficient of sensor  */
--#define MT7622_CALIBRATION	165
--
--/* MT8183 thermal sensors */
--#define MT8183_TS1	0
--#define MT8183_TS2	1
--#define MT8183_TS3	2
--#define MT8183_TS4	3
--#define MT8183_TS5	4
--#define MT8183_TSABB	5
--
--/* AUXADC channel  is used for the temperature sensors */
--#define MT8183_TEMP_AUXADC_CHANNEL	11
--
--/* The total number of temperature sensors in the MT8183 */
--#define MT8183_NUM_SENSORS	6
--
--/* The number of banks in the MT8183 */
--#define MT8183_NUM_ZONES               1
--
--/* The number of sensing points per bank */
--#define MT8183_NUM_SENSORS_PER_ZONE	 6
--
--/* The number of controller in the MT8183 */
--#define MT8183_NUM_CONTROLLER		2
--
--/* The calibration coefficient of sensor  */
--#define MT8183_CALIBRATION	153
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT7986_TEMP_AUXADC_CHANNEL	11
--
--/* The total number of temperature sensors in the MT7986 */
--#define MT7986_NUM_SENSORS		1
--
--/* The number of banks in the MT7986 */
--#define MT7986_NUM_ZONES		1
--
--/* The number of sensing points per bank */
--#define MT7986_NUM_SENSORS_PER_ZONE	1
--
--/* MT7986 thermal sensors */
--#define MT7986_TS1			0
--
--/* The number of controller in the MT7986 */
--#define MT7986_NUM_CONTROLLER		1
--
--/* The calibration coefficient of sensor  */
--#define MT7986_CALIBRATION		165
--
--struct mtk_thermal;
--
--struct thermal_bank_cfg {
--	unsigned int num_sensors;
--	const int *sensors;
--};
--
--struct mtk_thermal_bank {
--	struct mtk_thermal *mt;
--	int id;
--};
--
--struct mtk_thermal_data {
--	s32 num_banks;
--	s32 num_sensors;
--	s32 auxadc_channel;
--	const int *vts_index;
--	const int *sensor_mux_values;
--	const int *msr;
--	const int *adcpnp;
--	const int cali_val;
--	const int num_controller;
--	const int *controller_offset;
--	bool need_switch_bank;
--	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
--	enum mtk_thermal_version version;
--};
--
--struct mtk_thermal {
--	struct device *dev;
--	void __iomem *thermal_base;
--
--	struct clk *clk_peri_therm;
--	struct clk *clk_auxadc;
--	/* lock: for getting and putting banks */
--	struct mutex lock;
--
--	/* Calibration values */
--	s32 adc_ge;
--	s32 adc_oe;
--	s32 degc_cali;
--	s32 o_slope;
--	s32 o_slope_sign;
--	s32 vts[MAX_NUM_VTS];
--
--	const struct mtk_thermal_data *conf;
--	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
--
--	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
--};
--
--/* MT8183 thermal sensor data */
--static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
--	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
--};
--
--static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
--	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
--};
--
--static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
--	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
--	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
--};
--
--static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
--static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
--
--static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
--	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
--};
--
--/* MT8173 thermal sensor data */
--static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
--	{ MT8173_TS2, MT8173_TS3 },
--	{ MT8173_TS2, MT8173_TS4 },
--	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
--	{ MT8173_TS2 },
--};
--
--static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
--	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
--};
--
--static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
--	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
--};
--
--static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
--static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
--	VTS1, VTS2, VTS3, VTS4, VTSABB
--};
--
--/* MT2701 thermal sensor data */
--static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
--	MT2701_TS1, MT2701_TS2, MT2701_TSABB
--};
--
--static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
--	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
--};
--
--static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
--	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
--};
--
--static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
--static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
--	VTS1, VTS2, VTS3
--};
--
--/* MT2712 thermal sensor data */
--static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
--	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
--};
--
--static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
--	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
--};
--
--static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
--	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
--};
--
--static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
--static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
--	VTS1, VTS2, VTS3, VTS4
--};
--
--/* MT7622 thermal sensor data */
--static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
--static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
--static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
--static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
--static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
--static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
--
--/* MT7986 thermal sensor data */
--static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
--static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
--static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
--static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
--static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
--static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
--
--/*
-- * The MT8173 thermal controller has four banks. Each bank can read up to
-- * four temperature sensors simultaneously. The MT8173 has a total of 5
-- * temperature sensors. We use each bank to measure a certain area of the
-- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
-- * areas, hence is used in different banks.
-- *
-- * The thermal core only gets the maximum temperature of all banks, so
-- * the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data, and this indeed needs the temperatures of the individual banks
-- * for making better decisions.
-- */
--static const struct mtk_thermal_data mt8173_thermal_data = {
--	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
--	.num_banks = MT8173_NUM_ZONES,
--	.num_sensors = MT8173_NUM_SENSORS,
--	.vts_index = mt8173_vts_index,
--	.cali_val = MT8173_CALIBRATION,
--	.num_controller = MT8173_NUM_CONTROLLER,
--	.controller_offset = mt8173_tc_offset,
--	.need_switch_bank = true,
--	.bank_data = {
--		{
--			.num_sensors = 2,
--			.sensors = mt8173_bank_data[0],
--		}, {
--			.num_sensors = 2,
--			.sensors = mt8173_bank_data[1],
--		}, {
--			.num_sensors = 3,
--			.sensors = mt8173_bank_data[2],
--		}, {
--			.num_sensors = 1,
--			.sensors = mt8173_bank_data[3],
--		},
--	},
--	.msr = mt8173_msr,
--	.adcpnp = mt8173_adcpnp,
--	.sensor_mux_values = mt8173_mux_values,
--	.version = MTK_THERMAL_V1,
--};
--
--/*
-- * The MT2701 thermal controller has one bank, which can read up to
-- * three temperature sensors simultaneously. The MT2701 has a total of 3
-- * temperature sensors.
-- *
-- * The thermal core only gets the maximum temperature of this one bank,
-- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data.
-- */
--static const struct mtk_thermal_data mt2701_thermal_data = {
--	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
--	.num_banks = 1,
--	.num_sensors = MT2701_NUM_SENSORS,
--	.vts_index = mt2701_vts_index,
--	.cali_val = MT2701_CALIBRATION,
--	.num_controller = MT2701_NUM_CONTROLLER,
--	.controller_offset = mt2701_tc_offset,
--	.need_switch_bank = true,
--	.bank_data = {
--		{
--			.num_sensors = 3,
--			.sensors = mt2701_bank_data,
--		},
--	},
--	.msr = mt2701_msr,
--	.adcpnp = mt2701_adcpnp,
--	.sensor_mux_values = mt2701_mux_values,
--	.version = MTK_THERMAL_V1,
--};
--
--/*
-- * The MT2712 thermal controller has one bank, which can read up to
-- * four temperature sensors simultaneously. The MT2712 has a total of 4
-- * temperature sensors.
-- *
-- * The thermal core only gets the maximum temperature of this one bank,
-- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data.
-- */
--static const struct mtk_thermal_data mt2712_thermal_data = {
--	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
--	.num_banks = 1,
--	.num_sensors = MT2712_NUM_SENSORS,
--	.vts_index = mt2712_vts_index,
--	.cali_val = MT2712_CALIBRATION,
--	.num_controller = MT2712_NUM_CONTROLLER,
--	.controller_offset = mt2712_tc_offset,
--	.need_switch_bank = true,
--	.bank_data = {
--		{
--			.num_sensors = 4,
--			.sensors = mt2712_bank_data,
--		},
--	},
--	.msr = mt2712_msr,
--	.adcpnp = mt2712_adcpnp,
--	.sensor_mux_values = mt2712_mux_values,
--	.version = MTK_THERMAL_V1,
--};
--
--/*
-- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
-- * access.
-- */
--static const struct mtk_thermal_data mt7622_thermal_data = {
--	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
--	.num_banks = MT7622_NUM_ZONES,
--	.num_sensors = MT7622_NUM_SENSORS,
--	.vts_index = mt7622_vts_index,
--	.cali_val = MT7622_CALIBRATION,
--	.num_controller = MT7622_NUM_CONTROLLER,
--	.controller_offset = mt7622_tc_offset,
--	.need_switch_bank = true,
--	.bank_data = {
--		{
--			.num_sensors = 1,
--			.sensors = mt7622_bank_data,
--		},
--	},
--	.msr = mt7622_msr,
--	.adcpnp = mt7622_adcpnp,
--	.sensor_mux_values = mt7622_mux_values,
--	.version = MTK_THERMAL_V2,
--};
--
--/*
-- * The MT8183 thermal controller has one bank for the current SW framework.
-- * The MT8183 has a total of 6 temperature sensors.
-- * There are two thermal controller to control the six sensor.
-- * The first one bind 2 sensor, and the other bind 4 sensors.
-- * The thermal core only gets the maximum temperature of all sensor, so
-- * the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data, and this indeed needs the temperatures of the individual banks
-- * for making better decisions.
-- */
--static const struct mtk_thermal_data mt8183_thermal_data = {
--	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
--	.num_banks = MT8183_NUM_ZONES,
--	.num_sensors = MT8183_NUM_SENSORS,
--	.vts_index = mt8183_vts_index,
--	.cali_val = MT8183_CALIBRATION,
--	.num_controller = MT8183_NUM_CONTROLLER,
--	.controller_offset = mt8183_tc_offset,
--	.need_switch_bank = false,
--	.bank_data = {
--		{
--			.num_sensors = 6,
--			.sensors = mt8183_bank_data,
--		},
--	},
--
--	.msr = mt8183_msr,
--	.adcpnp = mt8183_adcpnp,
--	.sensor_mux_values = mt8183_mux_values,
--	.version = MTK_THERMAL_V1,
--};
--
--/*
-- * MT7986 uses AUXADC Channel 11 for raw data access.
-- */
--static const struct mtk_thermal_data mt7986_thermal_data = {
--	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
--	.num_banks = MT7986_NUM_ZONES,
--	.num_sensors = MT7986_NUM_SENSORS,
--	.vts_index = mt7986_vts_index,
--	.cali_val = MT7986_CALIBRATION,
--	.num_controller = MT7986_NUM_CONTROLLER,
--	.controller_offset = mt7986_tc_offset,
--	.need_switch_bank = true,
--	.bank_data = {
--		{
--			.num_sensors = 1,
--			.sensors = mt7986_bank_data,
--		},
--	},
--	.msr = mt7986_msr,
--	.adcpnp = mt7986_adcpnp,
--	.sensor_mux_values = mt7986_mux_values,
--	.version = MTK_THERMAL_V3,
--};
--
--/**
-- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-- * @mt:	The thermal controller
-- * @sensno:	sensor number
-- * @raw:	raw ADC value
-- *
-- * This converts the raw ADC value to mcelsius using the SoC specific
-- * calibration constants
-- */
--static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
--{
--	s32 tmp;
--
--	raw &= 0xfff;
--
--	tmp = 203450520 << 3;
--	tmp /= mt->conf->cali_val + mt->o_slope;
--	tmp /= 10000 + mt->adc_ge;
--	tmp *= raw - mt->vts[sensno] - 3350;
--	tmp >>= 3;
--
--	return mt->degc_cali * 500 - tmp;
--}
--
--static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
--{
--	s32 format_1;
--	s32 format_2;
--	s32 g_oe;
--	s32 g_gain;
--	s32 g_x_roomt;
--	s32 tmp;
--
--	if (raw == 0)
--		return 0;
--
--	raw &= 0xfff;
--	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
--	g_oe = mt->adc_oe - 512;
--	format_1 = mt->vts[VTS2] + 3105 - g_oe;
--	format_2 = (mt->degc_cali * 10) >> 1;
--	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
--
--	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
--	tmp = tmp * 10 * 100 / 11;
--
--	if (mt->o_slope_sign == 0)
--		tmp = tmp / (165 - mt->o_slope);
--	else
--		tmp = tmp / (165 + mt->o_slope);
--
--	return (format_2 - tmp) * 100;
--}
--
--static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
--{
--	s32 tmp;
--
--	if (raw == 0)
--		return 0;
--
--	raw &= 0xfff;
--	tmp = 100000 * 15 / 16 * 10000;
--	tmp /= 4096 - 512 + mt->adc_ge;
--	tmp /= 1490;
--	tmp *= raw - mt->vts[sensno] - 2900;
--
--	return mt->degc_cali * 500 - tmp;
--}
--
--/**
-- * mtk_thermal_get_bank - get bank
-- * @bank:	The bank
-- *
-- * The bank registers are banked, we have to select a bank in the
-- * PTPCORESEL register to access it.
-- */
--static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
--{
--	struct mtk_thermal *mt = bank->mt;
--	u32 val;
--
--	if (mt->conf->need_switch_bank) {
--		mutex_lock(&mt->lock);
--
--		val = readl(mt->thermal_base + PTPCORESEL);
--		val &= ~0xf;
--		val |= bank->id;
--		writel(val, mt->thermal_base + PTPCORESEL);
--	}
--}
--
--/**
-- * mtk_thermal_put_bank - release bank
-- * @bank:	The bank
-- *
-- * release a bank previously taken with mtk_thermal_get_bank,
-- */
--static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
--{
--	struct mtk_thermal *mt = bank->mt;
--
--	if (mt->conf->need_switch_bank)
--		mutex_unlock(&mt->lock);
--}
--
--/**
-- * mtk_thermal_bank_temperature - get the temperature of a bank
-- * @bank:	The bank
-- *
-- * The temperature of a bank is considered the maximum temperature of
-- * the sensors associated to the bank.
-- */
--static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
--{
--	struct mtk_thermal *mt = bank->mt;
--	const struct mtk_thermal_data *conf = mt->conf;
--	int i, temp = INT_MIN, max = INT_MIN;
--	u32 raw;
--
--	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
--		raw = readl(mt->thermal_base + conf->msr[i]);
--
--		temp = mt->raw_to_mcelsius(
--			mt, conf->bank_data[bank->id].sensors[i], raw);
--
--
--		/*
--		 * The first read of a sensor often contains very high bogus
--		 * temperature value. Filter these out so that the system does
--		 * not immediately shut down.
--		 */
--		if (temp > 200000)
--			temp = 0;
--
--		if (temp > max)
--			max = temp;
--	}
--
--	return max;
--}
--
--static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
--{
--	struct mtk_thermal *mt = tz->devdata;
--	int i;
--	int tempmax = INT_MIN;
--
--	for (i = 0; i < mt->conf->num_banks; i++) {
--		struct mtk_thermal_bank *bank = &mt->banks[i];
--
--		mtk_thermal_get_bank(bank);
--
--		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
--
--		mtk_thermal_put_bank(bank);
--	}
--
--	*temperature = tempmax;
--
--	return 0;
--}
--
--static const struct thermal_zone_device_ops mtk_thermal_ops = {
--	.get_temp = mtk_read_temp,
--};
--
--static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
--				  u32 apmixed_phys_base, u32 auxadc_phys_base,
--				  int ctrl_id)
--{
--	struct mtk_thermal_bank *bank = &mt->banks[num];
--	const struct mtk_thermal_data *conf = mt->conf;
--	int i;
--
--	int offset = mt->conf->controller_offset[ctrl_id];
--	void __iomem *controller_base = mt->thermal_base + offset;
--
--	bank->id = num;
--	bank->mt = mt;
--
--	mtk_thermal_get_bank(bank);
--
--	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
--	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
--
--	/*
--	 * filt interval is 1 * 46.540us = 46.54us,
--	 * sen interval is 429 * 46.540us = 19.96ms
--	 */
--	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
--			TEMP_MONCTL2_SENSOR_INTERVAL(429),
--			controller_base + TEMP_MONCTL2);
--
--	/* poll is set to 10u */
--	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
--	       controller_base + TEMP_AHBPOLL);
--
--	/* temperature sampling control, 1 sample */
--	writel(0x0, controller_base + TEMP_MSRCTL0);
--
--	/* exceed this polling time, IRQ would be inserted */
--	writel(0xffffffff, controller_base + TEMP_AHBTO);
--
--	/* number of interrupts per event, 1 is enough */
--	writel(0x0, controller_base + TEMP_MONIDET0);
--	writel(0x0, controller_base + TEMP_MONIDET1);
--
--	/*
--	 * The MT8173 thermal controller does not have its own ADC. Instead it
--	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
--	 * controller has to be programmed with the physical addresses of the
--	 * AUXADC registers and with the various bit positions in the AUXADC.
--	 * Also the thermal controller controls a mux in the APMIXEDSYS register
--	 * space.
--	 */
--
--	/*
--	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
--	 * automatically by hw
--	 */
--	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
--
--	/* AHB address for auxadc mux selection */
--	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
--	       controller_base + TEMP_ADCMUXADDR);
--
--	if (mt->conf->version == MTK_THERMAL_V1) {
--		/* AHB address for pnp sensor mux selection */
--		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
--		       controller_base + TEMP_PNPMUXADDR);
--	}
--
--	/* AHB value for auxadc enable */
--	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
--
--	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
--	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
--	       controller_base + TEMP_ADCENADDR);
--
--	/* AHB address for auxadc valid bit */
--	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
--	       controller_base + TEMP_ADCVALIDADDR);
--
--	/* AHB address for auxadc voltage output */
--	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
--	       controller_base + TEMP_ADCVOLTADDR);
--
--	/* read valid & voltage are at the same register */
--	writel(0x0, controller_base + TEMP_RDCTRL);
--
--	/* indicate where the valid bit is */
--	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
--	       controller_base + TEMP_ADCVALIDMASK);
--
--	/* no shift */
--	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
--
--	/* enable auxadc mux write transaction */
--	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
--		controller_base + TEMP_ADCWRITECTRL);
--
--	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
--		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
--		       mt->thermal_base + conf->adcpnp[i]);
--
--	writel((1 << conf->bank_data[num].num_sensors) - 1,
--	       controller_base + TEMP_MONCTL0);
--
--	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
--	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
--	       controller_base + TEMP_ADCWRITECTRL);
--
--	mtk_thermal_put_bank(bank);
--}
--
--static u64 of_get_phys_base(struct device_node *np)
--{
--	u64 size64;
--	const __be32 *regaddr_p;
--
--	regaddr_p = of_get_address(np, 0, &size64, NULL);
--	if (!regaddr_p)
--		return OF_BAD_ADDR;
--
--	return of_translate_address(np, regaddr_p);
--}
--
--static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
--{
--	int i;
--
--	if (!(buf[0] & CALIB_BUF0_VALID_V1))
--		return -EINVAL;
--
--	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
--
--	for (i = 0; i < mt->conf->num_sensors; i++) {
--		switch (mt->conf->vts_index[i]) {
--		case VTS1:
--			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
--			break;
--		case VTS2:
--			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
--			break;
--		case VTS3:
--			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
--			break;
--		case VTS4:
--			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
--			break;
--		case VTS5:
--			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
--			break;
--		case VTSABB:
--			mt->vts[VTSABB] =
--				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
--			break;
--		default:
--			break;
--		}
--	}
--
--	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
--	if (CALIB_BUF1_ID_V1(buf[1]) &
--	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
--		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
--	else
--		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
--
--	return 0;
--}
--
--static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
--{
--	if (!CALIB_BUF1_VALID_V2(buf[1]))
--		return -EINVAL;
--
--	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
--	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
--	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
--	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
--	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
--	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
--	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
--	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
--
--	return 0;
--}
--
--static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
--{
--	if (!CALIB_BUF1_VALID_V3(buf[1]))
--		return -EINVAL;
--
--	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
--	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
--	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
--	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
--	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
--	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
--	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
--
--	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
--		mt->o_slope = 0;
--
--	return 0;
--}
--
--static int mtk_thermal_get_calibration_data(struct device *dev,
--					    struct mtk_thermal *mt)
--{
--	struct nvmem_cell *cell;
--	u32 *buf;
--	size_t len;
--	int i, ret = 0;
--
--	/* Start with default values */
--	mt->adc_ge = 512;
--	mt->adc_oe = 512;
--	for (i = 0; i < mt->conf->num_sensors; i++)
--		mt->vts[i] = 260;
--	mt->degc_cali = 40;
--	mt->o_slope = 0;
--
--	cell = nvmem_cell_get(dev, "calibration-data");
--	if (IS_ERR(cell)) {
--		if (PTR_ERR(cell) == -EPROBE_DEFER)
--			return PTR_ERR(cell);
--		return 0;
--	}
--
--	buf = (u32 *)nvmem_cell_read(cell, &len);
--
--	nvmem_cell_put(cell);
--
--	if (IS_ERR(buf))
--		return PTR_ERR(buf);
--
--	if (len < 3 * sizeof(u32)) {
--		dev_warn(dev, "invalid calibration data\n");
--		ret = -EINVAL;
--		goto out;
--	}
--
--	switch (mt->conf->version) {
--	case MTK_THERMAL_V1:
--		ret = mtk_thermal_extract_efuse_v1(mt, buf);
--		break;
--	case MTK_THERMAL_V2:
--		ret = mtk_thermal_extract_efuse_v2(mt, buf);
--		break;
--	case MTK_THERMAL_V3:
--		ret = mtk_thermal_extract_efuse_v3(mt, buf);
--		break;
--	default:
--		ret = -EINVAL;
--		break;
--	}
--
--	if (ret) {
--		dev_info(dev, "Device not calibrated, using default calibration values\n");
--		ret = 0;
--	}
--
--out:
--	kfree(buf);
--
--	return ret;
--}
--
--static const struct of_device_id mtk_thermal_of_match[] = {
--	{
--		.compatible = "mediatek,mt8173-thermal",
--		.data = (void *)&mt8173_thermal_data,
--	},
--	{
--		.compatible = "mediatek,mt2701-thermal",
--		.data = (void *)&mt2701_thermal_data,
--	},
--	{
--		.compatible = "mediatek,mt2712-thermal",
--		.data = (void *)&mt2712_thermal_data,
--	},
--	{
--		.compatible = "mediatek,mt7622-thermal",
--		.data = (void *)&mt7622_thermal_data,
--	},
--	{
--		.compatible = "mediatek,mt7986-thermal",
--		.data = (void *)&mt7986_thermal_data,
--	},
--	{
--		.compatible = "mediatek,mt8183-thermal",
--		.data = (void *)&mt8183_thermal_data,
--	}, {
--	},
--};
--MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
--
--static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
--{
--	int tmp;
--
--	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
--	tmp &= ~(0x37);
--	tmp |= 0x1;
--	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
--	udelay(200);
--}
--
--static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
--					    void __iomem *auxadc_base)
--{
--	int tmp;
--
--	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
--	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
--	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
--	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
--}
--
--static int mtk_thermal_probe(struct platform_device *pdev)
--{
--	int ret, i, ctrl_id;
--	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
--	struct mtk_thermal *mt;
--	u64 auxadc_phys_base, apmixed_phys_base;
--	struct thermal_zone_device *tzdev;
--	void __iomem *apmixed_base, *auxadc_base;
--
--	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
--	if (!mt)
--		return -ENOMEM;
--
--	mt->conf = of_device_get_match_data(&pdev->dev);
--
--	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
--	if (IS_ERR(mt->clk_peri_therm))
--		return PTR_ERR(mt->clk_peri_therm);
--
--	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
--	if (IS_ERR(mt->clk_auxadc))
--		return PTR_ERR(mt->clk_auxadc);
--
--	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
--	if (IS_ERR(mt->thermal_base))
--		return PTR_ERR(mt->thermal_base);
--
--	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
--	if (ret)
--		return ret;
--
--	mutex_init(&mt->lock);
--
--	mt->dev = &pdev->dev;
--
--	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
--	if (!auxadc) {
--		dev_err(&pdev->dev, "missing auxadc node\n");
--		return -ENODEV;
--	}
--
--	auxadc_base = of_iomap(auxadc, 0);
--	auxadc_phys_base = of_get_phys_base(auxadc);
--
--	of_node_put(auxadc);
--
--	if (auxadc_phys_base == OF_BAD_ADDR) {
--		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
--		return -EINVAL;
--	}
--
--	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
--	if (!apmixedsys) {
--		dev_err(&pdev->dev, "missing apmixedsys node\n");
--		return -ENODEV;
--	}
--
--	apmixed_base = of_iomap(apmixedsys, 0);
--	apmixed_phys_base = of_get_phys_base(apmixedsys);
--
--	of_node_put(apmixedsys);
--
--	if (apmixed_phys_base == OF_BAD_ADDR) {
--		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
--		return -EINVAL;
--	}
--
--	ret = device_reset_optional(&pdev->dev);
--	if (ret)
--		return ret;
--
--	ret = clk_prepare_enable(mt->clk_auxadc);
--	if (ret) {
--		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
--		return ret;
--	}
--
--	ret = clk_prepare_enable(mt->clk_peri_therm);
--	if (ret) {
--		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
--		goto err_disable_clk_auxadc;
--	}
--
--	if (mt->conf->version != MTK_THERMAL_V1) {
--		mtk_thermal_turn_on_buffer(apmixed_base);
--		mtk_thermal_release_periodic_ts(mt, auxadc_base);
--	}
--
--	if (mt->conf->version == MTK_THERMAL_V1)
--		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
--	else if (mt->conf->version == MTK_THERMAL_V2)
--		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
--	else
--		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
--
--	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
--		for (i = 0; i < mt->conf->num_banks; i++)
--			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
--					      auxadc_phys_base, ctrl_id);
--
--	platform_set_drvdata(pdev, mt);
--
--	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
--					      &mtk_thermal_ops);
--	if (IS_ERR(tzdev)) {
--		ret = PTR_ERR(tzdev);
--		goto err_disable_clk_peri_therm;
--	}
--
--	ret = devm_thermal_add_hwmon_sysfs(tzdev);
--	if (ret)
--		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
--
--	return 0;
--
--err_disable_clk_peri_therm:
--	clk_disable_unprepare(mt->clk_peri_therm);
--err_disable_clk_auxadc:
--	clk_disable_unprepare(mt->clk_auxadc);
--
--	return ret;
--}
--
--static int mtk_thermal_remove(struct platform_device *pdev)
--{
--	struct mtk_thermal *mt = platform_get_drvdata(pdev);
--
--	clk_disable_unprepare(mt->clk_peri_therm);
--	clk_disable_unprepare(mt->clk_auxadc);
--
--	return 0;
--}
--
--static struct platform_driver mtk_thermal_driver = {
--	.probe = mtk_thermal_probe,
--	.remove = mtk_thermal_remove,
--	.driver = {
--		.name = "mtk-thermal",
--		.of_match_table = mtk_thermal_of_match,
--	},
--};
--
--module_platform_driver(mtk_thermal_driver);
--
--MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
--MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
--MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
--MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
--MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
--MODULE_DESCRIPTION("Mediatek thermal driver");
--MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -0,0 +1,1254 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2015 MediaTek Inc.
-+ * Author: Hanyi Wu <hanyi.wu@mediatek.com>
-+ *         Sascha Hauer <s.hauer@pengutronix.de>
-+ *         Dawei Chien <dawei.chien@mediatek.com>
-+ *         Louis Yu <louis.yu@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/thermal.h>
-+#include <linux/reset.h>
-+#include <linux/types.h>
-+
-+#include "../thermal_hwmon.h"
-+
-+/* AUXADC Registers */
-+#define AUXADC_CON1_SET_V	0x008
-+#define AUXADC_CON1_CLR_V	0x00c
-+#define AUXADC_CON2_V		0x010
-+#define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
-+
-+#define APMIXED_SYS_TS_CON1	0x604
-+
-+/* Thermal Controller Registers */
-+#define TEMP_MONCTL0		0x000
-+#define TEMP_MONCTL1		0x004
-+#define TEMP_MONCTL2		0x008
-+#define TEMP_MONIDET0		0x014
-+#define TEMP_MONIDET1		0x018
-+#define TEMP_MSRCTL0		0x038
-+#define TEMP_MSRCTL1		0x03c
-+#define TEMP_AHBPOLL		0x040
-+#define TEMP_AHBTO		0x044
-+#define TEMP_ADCPNP0		0x048
-+#define TEMP_ADCPNP1		0x04c
-+#define TEMP_ADCPNP2		0x050
-+#define TEMP_ADCPNP3		0x0b4
-+
-+#define TEMP_ADCMUX		0x054
-+#define TEMP_ADCEN		0x060
-+#define TEMP_PNPMUXADDR		0x064
-+#define TEMP_ADCMUXADDR		0x068
-+#define TEMP_ADCENADDR		0x074
-+#define TEMP_ADCVALIDADDR	0x078
-+#define TEMP_ADCVOLTADDR	0x07c
-+#define TEMP_RDCTRL		0x080
-+#define TEMP_ADCVALIDMASK	0x084
-+#define TEMP_ADCVOLTAGESHIFT	0x088
-+#define TEMP_ADCWRITECTRL	0x08c
-+#define TEMP_MSR0		0x090
-+#define TEMP_MSR1		0x094
-+#define TEMP_MSR2		0x098
-+#define TEMP_MSR3		0x0B8
-+
-+#define TEMP_SPARE0		0x0f0
-+
-+#define TEMP_ADCPNP0_1          0x148
-+#define TEMP_ADCPNP1_1          0x14c
-+#define TEMP_ADCPNP2_1          0x150
-+#define TEMP_MSR0_1             0x190
-+#define TEMP_MSR1_1             0x194
-+#define TEMP_MSR2_1             0x198
-+#define TEMP_ADCPNP3_1          0x1b4
-+#define TEMP_MSR3_1             0x1B8
-+
-+#define PTPCORESEL		0x400
-+
-+#define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
-+
-+#define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
-+#define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
-+
-+#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
-+
-+#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
-+#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
-+
-+#define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
-+#define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
-+
-+/* MT8173 thermal sensors */
-+#define MT8173_TS1	0
-+#define MT8173_TS2	1
-+#define MT8173_TS3	2
-+#define MT8173_TS4	3
-+#define MT8173_TSABB	4
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT8173_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT8173 */
-+#define MT8173_NUM_SENSORS		5
-+
-+/* The number of banks in the MT8173 */
-+#define MT8173_NUM_ZONES		4
-+
-+/* The number of sensing points per bank */
-+#define MT8173_NUM_SENSORS_PER_ZONE	4
-+
-+/* The number of controller in the MT8173 */
-+#define MT8173_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT8173_CALIBRATION	165
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-+ * MT8183 has 6 sensors and needs 6 VTS calibration data.
-+ * MT8173 has 5 sensors and needs 5 VTS calibration data.
-+ * MT2701 has 3 sensors and needs 3 VTS calibration data.
-+ * MT2712 has 4 sensors and needs 4 VTS calibration data.
-+ */
-+#define CALIB_BUF0_VALID_V1		BIT(0)
-+#define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
-+#define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
-+#define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
-+#define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
-+#define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
-+#define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
-+#define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros could be used for MT7622.
-+ */
-+#define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
-+#define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
-+#define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
-+
-+enum {
-+	VTS1,
-+	VTS2,
-+	VTS3,
-+	VTS4,
-+	VTS5,
-+	VTSABB,
-+	MAX_NUM_VTS,
-+};
-+
-+enum mtk_thermal_version {
-+	MTK_THERMAL_V1 = 1,
-+	MTK_THERMAL_V2,
-+	MTK_THERMAL_V3,
-+};
-+
-+/* MT2701 thermal sensors */
-+#define MT2701_TS1	0
-+#define MT2701_TS2	1
-+#define MT2701_TSABB	2
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT2701_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT2701 */
-+#define MT2701_NUM_SENSORS	3
-+
-+/* The number of sensing points per bank */
-+#define MT2701_NUM_SENSORS_PER_ZONE	3
-+
-+/* The number of controller in the MT2701 */
-+#define MT2701_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT2701_CALIBRATION	165
-+
-+/* MT2712 thermal sensors */
-+#define MT2712_TS1	0
-+#define MT2712_TS2	1
-+#define MT2712_TS3	2
-+#define MT2712_TS4	3
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT2712_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT2712 */
-+#define MT2712_NUM_SENSORS	4
-+
-+/* The number of sensing points per bank */
-+#define MT2712_NUM_SENSORS_PER_ZONE	4
-+
-+/* The number of controller in the MT2712 */
-+#define MT2712_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT2712_CALIBRATION	165
-+
-+#define MT7622_TEMP_AUXADC_CHANNEL	11
-+#define MT7622_NUM_SENSORS		1
-+#define MT7622_NUM_ZONES		1
-+#define MT7622_NUM_SENSORS_PER_ZONE	1
-+#define MT7622_TS1	0
-+#define MT7622_NUM_CONTROLLER		1
-+
-+/* The maximum number of banks */
-+#define MAX_NUM_ZONES		8
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7622_CALIBRATION	165
-+
-+/* MT8183 thermal sensors */
-+#define MT8183_TS1	0
-+#define MT8183_TS2	1
-+#define MT8183_TS3	2
-+#define MT8183_TS4	3
-+#define MT8183_TS5	4
-+#define MT8183_TSABB	5
-+
-+/* AUXADC channel  is used for the temperature sensors */
-+#define MT8183_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT8183 */
-+#define MT8183_NUM_SENSORS	6
-+
-+/* The number of banks in the MT8183 */
-+#define MT8183_NUM_ZONES               1
-+
-+/* The number of sensing points per bank */
-+#define MT8183_NUM_SENSORS_PER_ZONE	 6
-+
-+/* The number of controller in the MT8183 */
-+#define MT8183_NUM_CONTROLLER		2
-+
-+/* The calibration coefficient of sensor  */
-+#define MT8183_CALIBRATION	153
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL	11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS		1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES		1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE	1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1			0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER		1
-+
-+/* The calibration coefficient of sensor  */
-+#define MT7986_CALIBRATION		165
-+
-+struct mtk_thermal;
-+
-+struct thermal_bank_cfg {
-+	unsigned int num_sensors;
-+	const int *sensors;
-+};
-+
-+struct mtk_thermal_bank {
-+	struct mtk_thermal *mt;
-+	int id;
-+};
-+
-+struct mtk_thermal_data {
-+	s32 num_banks;
-+	s32 num_sensors;
-+	s32 auxadc_channel;
-+	const int *vts_index;
-+	const int *sensor_mux_values;
-+	const int *msr;
-+	const int *adcpnp;
-+	const int cali_val;
-+	const int num_controller;
-+	const int *controller_offset;
-+	bool need_switch_bank;
-+	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
-+	enum mtk_thermal_version version;
-+};
-+
-+struct mtk_thermal {
-+	struct device *dev;
-+	void __iomem *thermal_base;
-+
-+	struct clk *clk_peri_therm;
-+	struct clk *clk_auxadc;
-+	/* lock: for getting and putting banks */
-+	struct mutex lock;
-+
-+	/* Calibration values */
-+	s32 adc_ge;
-+	s32 adc_oe;
-+	s32 degc_cali;
-+	s32 o_slope;
-+	s32 o_slope_sign;
-+	s32 vts[MAX_NUM_VTS];
-+
-+	const struct mtk_thermal_data *conf;
-+	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
-+};
-+
-+/* MT8183 thermal sensor data */
-+static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
-+	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
-+};
-+
-+static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
-+};
-+
-+static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
-+	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
-+};
-+
-+static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
-+static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
-+
-+static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
-+	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
-+};
-+
-+/* MT8173 thermal sensor data */
-+static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
-+	{ MT8173_TS2, MT8173_TS3 },
-+	{ MT8173_TS2, MT8173_TS4 },
-+	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
-+	{ MT8173_TS2 },
-+};
-+
-+static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
-+};
-+
-+static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
-+};
-+
-+static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
-+static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
-+	VTS1, VTS2, VTS3, VTS4, VTSABB
-+};
-+
-+/* MT2701 thermal sensor data */
-+static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
-+	MT2701_TS1, MT2701_TS2, MT2701_TSABB
-+};
-+
-+static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
-+};
-+
-+static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
-+};
-+
-+static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
-+static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
-+	VTS1, VTS2, VTS3
-+};
-+
-+/* MT2712 thermal sensor data */
-+static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
-+	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
-+};
-+
-+static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
-+};
-+
-+static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
-+};
-+
-+static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
-+static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
-+	VTS1, VTS2, VTS3, VTS4
-+};
-+
-+/* MT7622 thermal sensor data */
-+static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
-+static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
-+static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
-+static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
-+
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
-+/*
-+ * The MT8173 thermal controller has four banks. Each bank can read up to
-+ * four temperature sensors simultaneously. The MT8173 has a total of 5
-+ * temperature sensors. We use each bank to measure a certain area of the
-+ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
-+ * areas, hence is used in different banks.
-+ *
-+ * The thermal core only gets the maximum temperature of all banks, so
-+ * the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data, and this indeed needs the temperatures of the individual banks
-+ * for making better decisions.
-+ */
-+static const struct mtk_thermal_data mt8173_thermal_data = {
-+	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT8173_NUM_ZONES,
-+	.num_sensors = MT8173_NUM_SENSORS,
-+	.vts_index = mt8173_vts_index,
-+	.cali_val = MT8173_CALIBRATION,
-+	.num_controller = MT8173_NUM_CONTROLLER,
-+	.controller_offset = mt8173_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 2,
-+			.sensors = mt8173_bank_data[0],
-+		}, {
-+			.num_sensors = 2,
-+			.sensors = mt8173_bank_data[1],
-+		}, {
-+			.num_sensors = 3,
-+			.sensors = mt8173_bank_data[2],
-+		}, {
-+			.num_sensors = 1,
-+			.sensors = mt8173_bank_data[3],
-+		},
-+	},
-+	.msr = mt8173_msr,
-+	.adcpnp = mt8173_adcpnp,
-+	.sensor_mux_values = mt8173_mux_values,
-+	.version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * The MT2701 thermal controller has one bank, which can read up to
-+ * three temperature sensors simultaneously. The MT2701 has a total of 3
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt2701_thermal_data = {
-+	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
-+	.num_banks = 1,
-+	.num_sensors = MT2701_NUM_SENSORS,
-+	.vts_index = mt2701_vts_index,
-+	.cali_val = MT2701_CALIBRATION,
-+	.num_controller = MT2701_NUM_CONTROLLER,
-+	.controller_offset = mt2701_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 3,
-+			.sensors = mt2701_bank_data,
-+		},
-+	},
-+	.msr = mt2701_msr,
-+	.adcpnp = mt2701_adcpnp,
-+	.sensor_mux_values = mt2701_mux_values,
-+	.version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * The MT2712 thermal controller has one bank, which can read up to
-+ * four temperature sensors simultaneously. The MT2712 has a total of 4
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt2712_thermal_data = {
-+	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
-+	.num_banks = 1,
-+	.num_sensors = MT2712_NUM_SENSORS,
-+	.vts_index = mt2712_vts_index,
-+	.cali_val = MT2712_CALIBRATION,
-+	.num_controller = MT2712_NUM_CONTROLLER,
-+	.controller_offset = mt2712_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 4,
-+			.sensors = mt2712_bank_data,
-+		},
-+	},
-+	.msr = mt2712_msr,
-+	.adcpnp = mt2712_adcpnp,
-+	.sensor_mux_values = mt2712_mux_values,
-+	.version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
-+ * access.
-+ */
-+static const struct mtk_thermal_data mt7622_thermal_data = {
-+	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7622_NUM_ZONES,
-+	.num_sensors = MT7622_NUM_SENSORS,
-+	.vts_index = mt7622_vts_index,
-+	.cali_val = MT7622_CALIBRATION,
-+	.num_controller = MT7622_NUM_CONTROLLER,
-+	.controller_offset = mt7622_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7622_bank_data,
-+		},
-+	},
-+	.msr = mt7622_msr,
-+	.adcpnp = mt7622_adcpnp,
-+	.sensor_mux_values = mt7622_mux_values,
-+	.version = MTK_THERMAL_V2,
-+};
-+
-+/*
-+ * The MT8183 thermal controller has one bank for the current SW framework.
-+ * The MT8183 has a total of 6 temperature sensors.
-+ * There are two thermal controller to control the six sensor.
-+ * The first one bind 2 sensor, and the other bind 4 sensors.
-+ * The thermal core only gets the maximum temperature of all sensor, so
-+ * the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data, and this indeed needs the temperatures of the individual banks
-+ * for making better decisions.
-+ */
-+static const struct mtk_thermal_data mt8183_thermal_data = {
-+	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT8183_NUM_ZONES,
-+	.num_sensors = MT8183_NUM_SENSORS,
-+	.vts_index = mt8183_vts_index,
-+	.cali_val = MT8183_CALIBRATION,
-+	.num_controller = MT8183_NUM_CONTROLLER,
-+	.controller_offset = mt8183_tc_offset,
-+	.need_switch_bank = false,
-+	.bank_data = {
-+		{
-+			.num_sensors = 6,
-+			.sensors = mt8183_bank_data,
-+		},
-+	},
-+
-+	.msr = mt8183_msr,
-+	.adcpnp = mt8183_adcpnp,
-+	.sensor_mux_values = mt8183_mux_values,
-+	.version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT7986_NUM_ZONES,
-+	.num_sensors = MT7986_NUM_SENSORS,
-+	.vts_index = mt7986_vts_index,
-+	.cali_val = MT7986_CALIBRATION,
-+	.num_controller = MT7986_NUM_CONTROLLER,
-+	.controller_offset = mt7986_tc_offset,
-+	.need_switch_bank = true,
-+	.bank_data = {
-+		{
-+			.num_sensors = 1,
-+			.sensors = mt7986_bank_data,
-+		},
-+	},
-+	.msr = mt7986_msr,
-+	.adcpnp = mt7986_adcpnp,
-+	.sensor_mux_values = mt7986_mux_values,
-+	.version = MTK_THERMAL_V3,
-+};
-+
-+/**
-+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-+ * @mt:	The thermal controller
-+ * @sensno:	sensor number
-+ * @raw:	raw ADC value
-+ *
-+ * This converts the raw ADC value to mcelsius using the SoC specific
-+ * calibration constants
-+ */
-+static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	raw &= 0xfff;
-+
-+	tmp = 203450520 << 3;
-+	tmp /= mt->conf->cali_val + mt->o_slope;
-+	tmp /= 10000 + mt->adc_ge;
-+	tmp *= raw - mt->vts[sensno] - 3350;
-+	tmp >>= 3;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
-+static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 format_1;
-+	s32 format_2;
-+	s32 g_oe;
-+	s32 g_gain;
-+	s32 g_x_roomt;
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
-+	g_oe = mt->adc_oe - 512;
-+	format_1 = mt->vts[VTS2] + 3105 - g_oe;
-+	format_2 = (mt->degc_cali * 10) >> 1;
-+	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
-+
-+	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
-+	tmp = tmp * 10 * 100 / 11;
-+
-+	if (mt->o_slope_sign == 0)
-+		tmp = tmp / (165 - mt->o_slope);
-+	else
-+		tmp = tmp / (165 + mt->o_slope);
-+
-+	return (format_2 - tmp) * 100;
-+}
-+
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+	s32 tmp;
-+
-+	if (raw == 0)
-+		return 0;
-+
-+	raw &= 0xfff;
-+	tmp = 100000 * 15 / 16 * 10000;
-+	tmp /= 4096 - 512 + mt->adc_ge;
-+	tmp /= 1490;
-+	tmp *= raw - mt->vts[sensno] - 2900;
-+
-+	return mt->degc_cali * 500 - tmp;
-+}
-+
-+/**
-+ * mtk_thermal_get_bank - get bank
-+ * @bank:	The bank
-+ *
-+ * The bank registers are banked, we have to select a bank in the
-+ * PTPCORESEL register to access it.
-+ */
-+static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
-+{
-+	struct mtk_thermal *mt = bank->mt;
-+	u32 val;
-+
-+	if (mt->conf->need_switch_bank) {
-+		mutex_lock(&mt->lock);
-+
-+		val = readl(mt->thermal_base + PTPCORESEL);
-+		val &= ~0xf;
-+		val |= bank->id;
-+		writel(val, mt->thermal_base + PTPCORESEL);
-+	}
-+}
-+
-+/**
-+ * mtk_thermal_put_bank - release bank
-+ * @bank:	The bank
-+ *
-+ * release a bank previously taken with mtk_thermal_get_bank,
-+ */
-+static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
-+{
-+	struct mtk_thermal *mt = bank->mt;
-+
-+	if (mt->conf->need_switch_bank)
-+		mutex_unlock(&mt->lock);
-+}
-+
-+/**
-+ * mtk_thermal_bank_temperature - get the temperature of a bank
-+ * @bank:	The bank
-+ *
-+ * The temperature of a bank is considered the maximum temperature of
-+ * the sensors associated to the bank.
-+ */
-+static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
-+{
-+	struct mtk_thermal *mt = bank->mt;
-+	const struct mtk_thermal_data *conf = mt->conf;
-+	int i, temp = INT_MIN, max = INT_MIN;
-+	u32 raw;
-+
-+	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
-+		raw = readl(mt->thermal_base + conf->msr[i]);
-+
-+		temp = mt->raw_to_mcelsius(
-+			mt, conf->bank_data[bank->id].sensors[i], raw);
-+
-+
-+		/*
-+		 * The first read of a sensor often contains very high bogus
-+		 * temperature value. Filter these out so that the system does
-+		 * not immediately shut down.
-+		 */
-+		if (temp > 200000)
-+			temp = 0;
-+
-+		if (temp > max)
-+			max = temp;
-+	}
-+
-+	return max;
-+}
-+
-+static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
-+{
-+	struct mtk_thermal *mt = tz->devdata;
-+	int i;
-+	int tempmax = INT_MIN;
-+
-+	for (i = 0; i < mt->conf->num_banks; i++) {
-+		struct mtk_thermal_bank *bank = &mt->banks[i];
-+
-+		mtk_thermal_get_bank(bank);
-+
-+		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
-+
-+		mtk_thermal_put_bank(bank);
-+	}
-+
-+	*temperature = tempmax;
-+
-+	return 0;
-+}
-+
-+static const struct thermal_zone_device_ops mtk_thermal_ops = {
-+	.get_temp = mtk_read_temp,
-+};
-+
-+static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
-+				  u32 apmixed_phys_base, u32 auxadc_phys_base,
-+				  int ctrl_id)
-+{
-+	struct mtk_thermal_bank *bank = &mt->banks[num];
-+	const struct mtk_thermal_data *conf = mt->conf;
-+	int i;
-+
-+	int offset = mt->conf->controller_offset[ctrl_id];
-+	void __iomem *controller_base = mt->thermal_base + offset;
-+
-+	bank->id = num;
-+	bank->mt = mt;
-+
-+	mtk_thermal_get_bank(bank);
-+
-+	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
-+	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
-+
-+	/*
-+	 * filt interval is 1 * 46.540us = 46.54us,
-+	 * sen interval is 429 * 46.540us = 19.96ms
-+	 */
-+	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
-+			TEMP_MONCTL2_SENSOR_INTERVAL(429),
-+			controller_base + TEMP_MONCTL2);
-+
-+	/* poll is set to 10u */
-+	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
-+	       controller_base + TEMP_AHBPOLL);
-+
-+	/* temperature sampling control, 1 sample */
-+	writel(0x0, controller_base + TEMP_MSRCTL0);
-+
-+	/* exceed this polling time, IRQ would be inserted */
-+	writel(0xffffffff, controller_base + TEMP_AHBTO);
-+
-+	/* number of interrupts per event, 1 is enough */
-+	writel(0x0, controller_base + TEMP_MONIDET0);
-+	writel(0x0, controller_base + TEMP_MONIDET1);
-+
-+	/*
-+	 * The MT8173 thermal controller does not have its own ADC. Instead it
-+	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
-+	 * controller has to be programmed with the physical addresses of the
-+	 * AUXADC registers and with the various bit positions in the AUXADC.
-+	 * Also the thermal controller controls a mux in the APMIXEDSYS register
-+	 * space.
-+	 */
-+
-+	/*
-+	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
-+	 * automatically by hw
-+	 */
-+	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
-+
-+	/* AHB address for auxadc mux selection */
-+	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
-+	       controller_base + TEMP_ADCMUXADDR);
-+
-+	if (mt->conf->version == MTK_THERMAL_V1) {
-+		/* AHB address for pnp sensor mux selection */
-+		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
-+		       controller_base + TEMP_PNPMUXADDR);
-+	}
-+
-+	/* AHB value for auxadc enable */
-+	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
-+
-+	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
-+	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
-+	       controller_base + TEMP_ADCENADDR);
-+
-+	/* AHB address for auxadc valid bit */
-+	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-+	       controller_base + TEMP_ADCVALIDADDR);
-+
-+	/* AHB address for auxadc voltage output */
-+	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-+	       controller_base + TEMP_ADCVOLTADDR);
-+
-+	/* read valid & voltage are at the same register */
-+	writel(0x0, controller_base + TEMP_RDCTRL);
-+
-+	/* indicate where the valid bit is */
-+	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
-+	       controller_base + TEMP_ADCVALIDMASK);
-+
-+	/* no shift */
-+	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
-+
-+	/* enable auxadc mux write transaction */
-+	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-+		controller_base + TEMP_ADCWRITECTRL);
-+
-+	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
-+		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
-+		       mt->thermal_base + conf->adcpnp[i]);
-+
-+	writel((1 << conf->bank_data[num].num_sensors) - 1,
-+	       controller_base + TEMP_MONCTL0);
-+
-+	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
-+	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-+	       controller_base + TEMP_ADCWRITECTRL);
-+
-+	mtk_thermal_put_bank(bank);
-+}
-+
-+static u64 of_get_phys_base(struct device_node *np)
-+{
-+	u64 size64;
-+	const __be32 *regaddr_p;
-+
-+	regaddr_p = of_get_address(np, 0, &size64, NULL);
-+	if (!regaddr_p)
-+		return OF_BAD_ADDR;
-+
-+	return of_translate_address(np, regaddr_p);
-+}
-+
-+static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
-+{
-+	int i;
-+
-+	if (!(buf[0] & CALIB_BUF0_VALID_V1))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
-+
-+	for (i = 0; i < mt->conf->num_sensors; i++) {
-+		switch (mt->conf->vts_index[i]) {
-+		case VTS1:
-+			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
-+			break;
-+		case VTS2:
-+			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
-+			break;
-+		case VTS3:
-+			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
-+			break;
-+		case VTS4:
-+			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
-+			break;
-+		case VTS5:
-+			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
-+			break;
-+		case VTSABB:
-+			mt->vts[VTSABB] =
-+				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
-+	if (CALIB_BUF1_ID_V1(buf[1]) &
-+	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
-+		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
-+	else
-+		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
-+
-+	return 0;
-+}
-+
-+static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V2(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
-+
-+	return 0;
-+}
-+
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+	if (!CALIB_BUF1_VALID_V3(buf[1]))
-+		return -EINVAL;
-+
-+	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+		mt->o_slope = 0;
-+
-+	return 0;
-+}
-+
-+static int mtk_thermal_get_calibration_data(struct device *dev,
-+					    struct mtk_thermal *mt)
-+{
-+	struct nvmem_cell *cell;
-+	u32 *buf;
-+	size_t len;
-+	int i, ret = 0;
-+
-+	/* Start with default values */
-+	mt->adc_ge = 512;
-+	mt->adc_oe = 512;
-+	for (i = 0; i < mt->conf->num_sensors; i++)
-+		mt->vts[i] = 260;
-+	mt->degc_cali = 40;
-+	mt->o_slope = 0;
-+
-+	cell = nvmem_cell_get(dev, "calibration-data");
-+	if (IS_ERR(cell)) {
-+		if (PTR_ERR(cell) == -EPROBE_DEFER)
-+			return PTR_ERR(cell);
-+		return 0;
-+	}
-+
-+	buf = (u32 *)nvmem_cell_read(cell, &len);
-+
-+	nvmem_cell_put(cell);
-+
-+	if (IS_ERR(buf))
-+		return PTR_ERR(buf);
-+
-+	if (len < 3 * sizeof(u32)) {
-+		dev_warn(dev, "invalid calibration data\n");
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	switch (mt->conf->version) {
-+	case MTK_THERMAL_V1:
-+		ret = mtk_thermal_extract_efuse_v1(mt, buf);
-+		break;
-+	case MTK_THERMAL_V2:
-+		ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+		break;
-+	case MTK_THERMAL_V3:
-+		ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+	if (ret) {
-+		dev_info(dev, "Device not calibrated, using default calibration values\n");
-+		ret = 0;
-+	}
-+
-+out:
-+	kfree(buf);
-+
-+	return ret;
-+}
-+
-+static const struct of_device_id mtk_thermal_of_match[] = {
-+	{
-+		.compatible = "mediatek,mt8173-thermal",
-+		.data = (void *)&mt8173_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt2701-thermal",
-+		.data = (void *)&mt2701_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt2712-thermal",
-+		.data = (void *)&mt2712_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt7622-thermal",
-+		.data = (void *)&mt7622_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt7986-thermal",
-+		.data = (void *)&mt7986_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt8183-thermal",
-+		.data = (void *)&mt8183_thermal_data,
-+	}, {
-+	},
-+};
-+MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
-+
-+static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
-+{
-+	int tmp;
-+
-+	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
-+	tmp &= ~(0x37);
-+	tmp |= 0x1;
-+	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
-+	udelay(200);
-+}
-+
-+static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
-+					    void __iomem *auxadc_base)
-+{
-+	int tmp;
-+
-+	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
-+	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
-+	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
-+	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
-+}
-+
-+static int mtk_thermal_probe(struct platform_device *pdev)
-+{
-+	int ret, i, ctrl_id;
-+	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
-+	struct mtk_thermal *mt;
-+	u64 auxadc_phys_base, apmixed_phys_base;
-+	struct thermal_zone_device *tzdev;
-+	void __iomem *apmixed_base, *auxadc_base;
-+
-+	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
-+	if (!mt)
-+		return -ENOMEM;
-+
-+	mt->conf = of_device_get_match_data(&pdev->dev);
-+
-+	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
-+	if (IS_ERR(mt->clk_peri_therm))
-+		return PTR_ERR(mt->clk_peri_therm);
-+
-+	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
-+	if (IS_ERR(mt->clk_auxadc))
-+		return PTR_ERR(mt->clk_auxadc);
-+
-+	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+	if (IS_ERR(mt->thermal_base))
-+		return PTR_ERR(mt->thermal_base);
-+
-+	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
-+	if (ret)
-+		return ret;
-+
-+	mutex_init(&mt->lock);
-+
-+	mt->dev = &pdev->dev;
-+
-+	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
-+	if (!auxadc) {
-+		dev_err(&pdev->dev, "missing auxadc node\n");
-+		return -ENODEV;
-+	}
-+
-+	auxadc_base = of_iomap(auxadc, 0);
-+	auxadc_phys_base = of_get_phys_base(auxadc);
-+
-+	of_node_put(auxadc);
-+
-+	if (auxadc_phys_base == OF_BAD_ADDR) {
-+		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-+		return -EINVAL;
-+	}
-+
-+	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
-+	if (!apmixedsys) {
-+		dev_err(&pdev->dev, "missing apmixedsys node\n");
-+		return -ENODEV;
-+	}
-+
-+	apmixed_base = of_iomap(apmixedsys, 0);
-+	apmixed_phys_base = of_get_phys_base(apmixedsys);
-+
-+	of_node_put(apmixedsys);
-+
-+	if (apmixed_phys_base == OF_BAD_ADDR) {
-+		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-+		return -EINVAL;
-+	}
-+
-+	ret = device_reset_optional(&pdev->dev);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(mt->clk_auxadc);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = clk_prepare_enable(mt->clk_peri_therm);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
-+		goto err_disable_clk_auxadc;
-+	}
-+
-+	if (mt->conf->version != MTK_THERMAL_V1) {
-+		mtk_thermal_turn_on_buffer(apmixed_base);
-+		mtk_thermal_release_periodic_ts(mt, auxadc_base);
-+	}
-+
-+	if (mt->conf->version == MTK_THERMAL_V1)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+	else if (mt->conf->version == MTK_THERMAL_V2)
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+	else
-+		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+
-+	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
-+		for (i = 0; i < mt->conf->num_banks; i++)
-+			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
-+					      auxadc_phys_base, ctrl_id);
-+
-+	platform_set_drvdata(pdev, mt);
-+
-+	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
-+					      &mtk_thermal_ops);
-+	if (IS_ERR(tzdev)) {
-+		ret = PTR_ERR(tzdev);
-+		goto err_disable_clk_peri_therm;
-+	}
-+
-+	ret = devm_thermal_add_hwmon_sysfs(tzdev);
-+	if (ret)
-+		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
-+
-+	return 0;
-+
-+err_disable_clk_peri_therm:
-+	clk_disable_unprepare(mt->clk_peri_therm);
-+err_disable_clk_auxadc:
-+	clk_disable_unprepare(mt->clk_auxadc);
-+
-+	return ret;
-+}
-+
-+static int mtk_thermal_remove(struct platform_device *pdev)
-+{
-+	struct mtk_thermal *mt = platform_get_drvdata(pdev);
-+
-+	clk_disable_unprepare(mt->clk_peri_therm);
-+	clk_disable_unprepare(mt->clk_auxadc);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_thermal_driver = {
-+	.probe = mtk_thermal_probe,
-+	.remove = mtk_thermal_remove,
-+	.driver = {
-+		.name = "mtk-thermal",
-+		.of_match_table = mtk_thermal_of_match,
-+	},
-+};
-+
-+module_platform_driver(mtk_thermal_driver);
-+
-+MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
-+MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
-+MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
-+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
-+MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
-+MODULE_DESCRIPTION("Mediatek thermal driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
deleted file mode 100644
index 2ae3734e40..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch
+++ /dev/null
@@ -1,1298 +0,0 @@
-From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:26 +0100
-Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal
- Sensor driver
-
-The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi
-controllers contained in a thermal domain.
-
-A thermal domains can be the MCU or the AP.
-
-Each thermal domains contain up to seven controllers, each thermal
-controller handle up to four thermal sensors.
-
-The LVTS has two Finite State Machines (FSM), one to handle the
-functionin temperatures range like hot or cold temperature and another
-one to handle monitoring trip point. The FSM notifies via interrupts
-when a trip point is crossed.
-
-The interrupt is managed at the thermal controller level, so when an
-interrupt occurs, the driver has to find out which sensor triggered
-such an interrupt.
-
-The sampling of the thermal can be filtered or immediate. For the
-former, the LVTS measures several points and applies a low pass
-filter.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
-On MT8195 Tomato Chromebook:
-
-Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/Kconfig        |   16 +
- drivers/thermal/mediatek/Makefile       |    1 +
- drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++
- 3 files changed, 1241 insertions(+)
- create mode 100644 drivers/thermal/mediatek/lvts_thermal.c
-
---- a/drivers/thermal/mediatek/Kconfig
-+++ b/drivers/thermal/mediatek/Kconfig
-@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL
- 	  This driver configures thermal controllers to collect
- 	  temperature via AUXADC interface.
- 
-+config MTK_LVTS_THERMAL
-+        tristate "LVTS Thermal Driver for MediaTek SoCs"
-+        depends on HAS_IOMEM
-+        help
-+          Enable this option if you want to get SoC temperature
-+          information for supported MediaTek platforms.
-+          This driver configures LVTS (Low Voltage Thermal Sensor)
-+          thermal controllers to collect temperatures via ASIF
-+          (Analog Serial Interface).
-+
-+config MTK_LVTS_THERMAL_DEBUGFS
-+       bool "LVTS thermal debugfs"
-+       depends on MTK_LVTS_THERMAL && DEBUG_FS
-+       help
-+         Enable this option to debug the internals of the device driver.
-+
- endif
---- a/drivers/thermal/mediatek/Makefile
-+++ b/drivers/thermal/mediatek/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_MTK_SOC_THERMAL)	+= auxadc_thermal.o
-+obj-$(CONFIG_MTK_LVTS_THERMAL)	+= lvts_thermal.o
---- /dev/null
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -0,0 +1,1224 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Balsam CHIHI <bchihi@baylibre.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/debugfs.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/thermal.h>
-+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
-+
-+#define LVTS_MONCTL0(__base)	(__base + 0x0000)
-+#define LVTS_MONCTL1(__base)	(__base + 0x0004)
-+#define LVTS_MONCTL2(__base)	(__base + 0x0008)
-+#define LVTS_MONINT(__base)		(__base + 0x000C)
-+#define LVTS_MONINTSTS(__base)	(__base + 0x0010)
-+#define LVTS_MONIDET0(__base)	(__base + 0x0014)
-+#define LVTS_MONIDET1(__base)	(__base + 0x0018)
-+#define LVTS_MONIDET2(__base)	(__base + 0x001C)
-+#define LVTS_MONIDET3(__base)	(__base + 0x0020)
-+#define LVTS_H2NTHRE(__base)	(__base + 0x0024)
-+#define LVTS_HTHRE(__base)		(__base + 0x0028)
-+#define LVTS_OFFSETH(__base)	(__base + 0x0030)
-+#define LVTS_OFFSETL(__base)	(__base + 0x0034)
-+#define LVTS_MSRCTL0(__base)	(__base + 0x0038)
-+#define LVTS_MSRCTL1(__base)	(__base + 0x003C)
-+#define LVTS_TSSEL(__base)		(__base + 0x0040)
-+#define LVTS_CALSCALE(__base)	(__base + 0x0048)
-+#define LVTS_ID(__base)			(__base + 0x004C)
-+#define LVTS_CONFIG(__base)		(__base + 0x0050)
-+#define LVTS_EDATA00(__base)	(__base + 0x0054)
-+#define LVTS_EDATA01(__base)	(__base + 0x0058)
-+#define LVTS_EDATA02(__base)	(__base + 0x005C)
-+#define LVTS_EDATA03(__base)	(__base + 0x0060)
-+#define LVTS_MSR0(__base)		(__base + 0x0090)
-+#define LVTS_MSR1(__base)		(__base + 0x0094)
-+#define LVTS_MSR2(__base)		(__base + 0x0098)
-+#define LVTS_MSR3(__base)		(__base + 0x009C)
-+#define LVTS_IMMD0(__base)		(__base + 0x00A0)
-+#define LVTS_IMMD1(__base)		(__base + 0x00A4)
-+#define LVTS_IMMD2(__base)		(__base + 0x00A8)
-+#define LVTS_IMMD3(__base)		(__base + 0x00AC)
-+#define LVTS_PROTCTL(__base)	(__base + 0x00C0)
-+#define LVTS_PROTTA(__base)		(__base + 0x00C4)
-+#define LVTS_PROTTB(__base)		(__base + 0x00C8)
-+#define LVTS_PROTTC(__base)		(__base + 0x00CC)
-+#define LVTS_CLKEN(__base)		(__base + 0x00E4)
-+
-+#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
-+#define LVTS_GROUP_INTERVAL			1
-+#define LVTS_FILTER_INTERVAL		1
-+#define LVTS_SENSOR_INTERVAL		1
-+#define LVTS_HW_FILTER				0x2
-+#define LVTS_TSSEL_CONF				0x13121110
-+#define LVTS_CALSCALE_CONF			0x300
-+#define LVTS_MONINT_CONF			0x9FBF7BDE
-+
-+#define LVTS_INT_SENSOR0			0x0009001F
-+#define LVTS_INT_SENSOR1			0X000881F0
-+#define LVTS_INT_SENSOR2			0x00247C00
-+#define LVTS_INT_SENSOR3			0x1FC00000
-+
-+#define LVTS_SENSOR_MAX				4
-+#define LVTS_GOLDEN_TEMP_MAX		62
-+#define LVTS_GOLDEN_TEMP_DEFAULT	50
-+#define LVTS_COEFF_A				-250460
-+#define LVTS_COEFF_B				250460
-+
-+#define LVTS_MSR_IMMEDIATE_MODE		0
-+#define LVTS_MSR_FILTERED_MODE		1
-+
-+#define LVTS_HW_SHUTDOWN_MT8195		105000
-+
-+static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
-+static int coeff_b = LVTS_COEFF_B;
-+
-+struct lvts_sensor_data {
-+	int dt_id;
-+};
-+
-+struct lvts_ctrl_data {
-+	struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
-+	int cal_offset[LVTS_SENSOR_MAX];
-+	int hw_tshut_temp;
-+	int num_lvts_sensor;
-+	int offset;
-+	int mode;
-+};
-+
-+struct lvts_data {
-+	const struct lvts_ctrl_data *lvts_ctrl;
-+	int num_lvts_ctrl;
-+};
-+
-+struct lvts_sensor {
-+	struct thermal_zone_device *tz;
-+	void __iomem *msr;
-+	void __iomem *base;
-+	int id;
-+	int dt_id;
-+};
-+
-+struct lvts_ctrl {
-+	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
-+	u32 calibration[LVTS_SENSOR_MAX];
-+	u32 hw_tshut_raw_temp;
-+	int num_lvts_sensor;
-+	int mode;
-+	void __iomem *base;
-+};
-+
-+struct lvts_domain {
-+	struct lvts_ctrl *lvts_ctrl;
-+	struct reset_control *reset;
-+	struct clk *clk;
-+	int num_lvts_ctrl;
-+	void __iomem *base;
-+	size_t calib_len;
-+	u8 *calib;
-+#ifdef CONFIG_DEBUG_FS
-+	struct dentry *dom_dentry;
-+#endif
-+};
-+
-+#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
-+
-+#define LVTS_DEBUG_FS_REGS(__reg)		\
-+{						\
-+	.name = __stringify(__reg),		\
-+	.offset = __reg(0),			\
-+}
-+
-+static const struct debugfs_reg32 lvts_regs[] = {
-+	LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONINT),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
-+	LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
-+	LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
-+	LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
-+	LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
-+	LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
-+	LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
-+	LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
-+	LVTS_DEBUG_FS_REGS(LVTS_ID),
-+	LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
-+	LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
-+	LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
-+	LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
-+	LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSR0),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSR1),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSR2),
-+	LVTS_DEBUG_FS_REGS(LVTS_MSR3),
-+	LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
-+	LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
-+	LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
-+	LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
-+	LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
-+	LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
-+	LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
-+	LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
-+	LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
-+};
-+
-+static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
-+{
-+	struct debugfs_regset32 *regset;
-+	struct lvts_ctrl *lvts_ctrl;
-+	struct dentry *dentry;
-+	char name[64];
-+	int i;
-+
-+	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
-+	if (!lvts_td->dom_dentry)
-+		return 0;
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+		lvts_ctrl = &lvts_td->lvts_ctrl[i];
-+
-+		sprintf(name, "controller%d", i);
-+		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
-+		if (!dentry)
-+			continue;
-+
-+		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
-+		if (!regset)
-+			continue;
-+
-+		regset->base = lvts_ctrl->base;
-+		regset->regs = lvts_regs;
-+		regset->nregs = ARRAY_SIZE(lvts_regs);
-+
-+		debugfs_create_regset32("registers", 0400, dentry, regset);
-+	}
-+
-+	return 0;
-+}
-+
-+static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
-+{
-+	debugfs_remove_recursive(lvts_td->dom_dentry);
-+}
-+
-+#else
-+
-+static inline int lvts_debugfs_init(struct device *dev,
-+				    struct lvts_domain *lvts_td)
-+{
-+	return 0;
-+}
-+
-+static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
-+
-+#endif
-+
-+static int lvts_raw_to_temp(u32 raw_temp)
-+{
-+	int temperature;
-+
-+	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
-+	temperature += coeff_b;
-+
-+	return temperature;
-+}
-+
-+static u32 lvts_temp_to_raw(int temperature)
-+{
-+	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
-+
-+	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
-+
-+	return raw_temp;
-+}
-+
-+static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
-+{
-+	struct lvts_sensor *lvts_sensor = tz->devdata;
-+	void __iomem *msr = lvts_sensor->msr;
-+	u32 value;
-+
-+	/*
-+	 * Measurement registers:
-+	 *
-+	 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
-+	 *
-+	 * Bits:
-+	 *
-+	 * 32-17: Unused
-+	 * 16	: Valid temperature
-+	 * 15-0	: Raw temperature
-+	 */
-+	value = readl(msr);
-+
-+	/*
-+	 * As the thermal zone temperature will read before the
-+	 * hardware sensor is fully initialized, we have to check the
-+	 * validity of the temperature returned when reading the
-+	 * measurement register. The thermal controller will set the
-+	 * valid bit temperature only when it is totally initialized.
-+	 *
-+	 * Otherwise, we may end up with garbage values out of the
-+	 * functionning temperature and directly jump to a system
-+	 * shutdown.
-+	 */
-+	if (!(value & BIT(16)))
-+		return -EAGAIN;
-+
-+	*temp = lvts_raw_to_temp(value & 0xFFFF);
-+
-+	return 0;
-+}
-+
-+static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
-+{
-+	struct lvts_sensor *lvts_sensor = tz->devdata;
-+	void __iomem *base = lvts_sensor->base;
-+	u32 raw_low = lvts_temp_to_raw(low);
-+	u32 raw_high = lvts_temp_to_raw(high);
-+
-+	/*
-+	 * Hot to normal temperature threshold
-+	 *
-+	 * LVTS_H2NTHRE
-+	 *
-+	 * Bits:
-+	 *
-+	 * 14-0 : Raw temperature for threshold
-+	 */
-+	if (low != -INT_MAX) {
-+		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
-+		writel(raw_low, LVTS_H2NTHRE(base));
-+	}
-+
-+	/*
-+	 * Hot temperature threshold
-+	 *
-+	 * LVTS_HTHRE
-+	 *
-+	 * Bits:
-+	 *
-+	 * 14-0 : Raw temperature for threshold
-+	 */
-+	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
-+	writel(raw_high, LVTS_HTHRE(base));
-+
-+	return 0;
-+}
-+
-+static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
-+{
-+	irqreturn_t iret = IRQ_NONE;
-+	u32 value;
-+	u32 masks[] = {
-+		LVTS_INT_SENSOR0,
-+		LVTS_INT_SENSOR1,
-+		LVTS_INT_SENSOR2,
-+		LVTS_INT_SENSOR3
-+	};
-+	int i;
-+
-+	/*
-+	 * Interrupt monitoring status
-+	 *
-+	 * LVTS_MONINTST
-+	 *
-+	 * Bits:
-+	 *
-+	 * 31 : Interrupt for stage 3
-+	 * 30 : Interrupt for stage 2
-+	 * 29 : Interrupt for state 1
-+	 * 28 : Interrupt using filter on sensor 3
-+	 *
-+	 * 27 : Interrupt using immediate on sensor 3
-+	 * 26 : Interrupt normal to hot on sensor 3
-+	 * 25 : Interrupt high offset on sensor 3
-+	 * 24 : Interrupt low offset on sensor 3
-+	 *
-+	 * 23 : Interrupt hot threshold on sensor 3
-+	 * 22 : Interrupt cold threshold on sensor 3
-+	 * 21 : Interrupt using filter on sensor 2
-+	 * 20 : Interrupt using filter on sensor 1
-+	 *
-+	 * 19 : Interrupt using filter on sensor 0
-+	 * 18 : Interrupt using immediate on sensor 2
-+	 * 17 : Interrupt using immediate on sensor 1
-+	 * 16 : Interrupt using immediate on sensor 0
-+	 *
-+	 * 15 : Interrupt device access timeout interrupt
-+	 * 14 : Interrupt normal to hot on sensor 2
-+	 * 13 : Interrupt high offset interrupt on sensor 2
-+	 * 12 : Interrupt low offset interrupt on sensor 2
-+	 *
-+	 * 11 : Interrupt hot threshold on sensor 2
-+	 * 10 : Interrupt cold threshold on sensor 2
-+	 *  9 : Interrupt normal to hot on sensor 1
-+	 *  8 : Interrupt high offset interrupt on sensor 1
-+	 *
-+	 *  7 : Interrupt low offset interrupt on sensor 1
-+	 *  6 : Interrupt hot threshold on sensor 1
-+	 *  5 : Interrupt cold threshold on sensor 1
-+	 *  4 : Interrupt normal to hot on sensor 0
-+	 *
-+	 *  3 : Interrupt high offset interrupt on sensor 0
-+	 *  2 : Interrupt low offset interrupt on sensor 0
-+	 *  1 : Interrupt hot threshold on sensor 0
-+	 *  0 : Interrupt cold threshold on sensor 0
-+	 *
-+	 * We are interested in the sensor(s) responsible of the
-+	 * interrupt event. We update the thermal framework with the
-+	 * thermal zone associated with the sensor. The framework will
-+	 * take care of the rest whatever the kind of interrupt, we
-+	 * are only interested in which sensor raised the interrupt.
-+	 *
-+	 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
-+	 *                  => 0x1FC00000
-+	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
-+	 *                  => 0x00247C00
-+	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
-+	 *                  => 0X000881F0
-+	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
-+	 *                  => 0x0009001F
-+	 */
-+	value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
-+
-+	/*
-+	 * Let's figure out which sensors raised the interrupt
-+	 *
-+	 * NOTE: the masks array must be ordered with the index
-+	 * corresponding to the sensor id eg. index=0, mask for
-+	 * sensor0.
-+	 */
-+	for (i = 0; i < ARRAY_SIZE(masks); i++) {
-+
-+		if (!(value & masks[i]))
-+			continue;
-+
-+		thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
-+					   THERMAL_TRIP_VIOLATED);
-+		iret = IRQ_HANDLED;
-+	}
-+
-+	/*
-+	 * Write back to clear the interrupt status (W1C)
-+	 */
-+	writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
-+
-+	return iret;
-+}
-+
-+/*
-+ * Temperature interrupt handler. Even if the driver supports more
-+ * interrupt modes, we use the interrupt when the temperature crosses
-+ * the hot threshold the way up and the way down (modulo the
-+ * hysteresis).
-+ *
-+ * Each thermal domain has a couple of interrupts, one for hardware
-+ * reset and another one for all the thermal events happening on the
-+ * different sensors.
-+ *
-+ * The interrupt is configured for thermal events when crossing the
-+ * hot temperature limit. At each interrupt, we check in every
-+ * controller if there is an interrupt pending.
-+ */
-+static irqreturn_t lvts_irq_handler(int irq, void *data)
-+{
-+	struct lvts_domain *lvts_td = data;
-+	irqreturn_t aux, iret = IRQ_NONE;
-+	int i;
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
-+		if (aux != IRQ_HANDLED)
-+			continue;
-+
-+		iret = IRQ_HANDLED;
-+	}
-+
-+	return iret;
-+}
-+
-+static struct thermal_zone_device_ops lvts_ops = {
-+	.get_temp = lvts_get_temp,
-+	.set_trips = lvts_set_trips,
-+};
-+
-+static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
-+					const struct lvts_ctrl_data *lvts_ctrl_data)
-+{
-+	struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
-+	void __iomem *msr_regs[] = {
-+		LVTS_MSR0(lvts_ctrl->base),
-+		LVTS_MSR1(lvts_ctrl->base),
-+		LVTS_MSR2(lvts_ctrl->base),
-+		LVTS_MSR3(lvts_ctrl->base)
-+	};
-+
-+	void __iomem *imm_regs[] = {
-+		LVTS_IMMD0(lvts_ctrl->base),
-+		LVTS_IMMD1(lvts_ctrl->base),
-+		LVTS_IMMD2(lvts_ctrl->base),
-+		LVTS_IMMD3(lvts_ctrl->base)
-+	};
-+
-+	int i;
-+
-+	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
-+
-+		int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
-+
-+		/*
-+		 * At this point, we don't know which id matches which
-+		 * sensor. Let's set arbitrally the id from the index.
-+		 */
-+		lvts_sensor[i].id = i;
-+
-+		/*
-+		 * The thermal zone registration will set the trip
-+		 * point interrupt in the thermal controller
-+		 * register. But this one will be reset in the
-+		 * initialization after. So we need to post pone the
-+		 * thermal zone creation after the controller is
-+		 * setup. For this reason, we store the device tree
-+		 * node id from the data in the sensor structure
-+		 */
-+		lvts_sensor[i].dt_id = dt_id;
-+
-+		/*
-+		 * We assign the base address of the thermal
-+		 * controller as a back pointer. So it will be
-+		 * accessible from the different thermal framework ops
-+		 * as we pass the lvts_sensor pointer as thermal zone
-+		 * private data.
-+		 */
-+		lvts_sensor[i].base = lvts_ctrl->base;
-+
-+		/*
-+		 * Each sensor has its own register address to read from.
-+		 */
-+		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
-+			imm_regs[i] : msr_regs[i];
-+	};
-+
-+	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
-+
-+	return 0;
-+}
-+
-+/*
-+ * The efuse blob values follows the sensor enumeration per thermal
-+ * controller. The decoding of the stream is as follow:
-+ *
-+ *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
-+ *                        ------------------------------------------
-+ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
-+ *                        ------------------------------------------
-+ *
-+ *                        <--sensor1--><-0-> <----big1 ???---> <-sen
-+ *                        ------------------------------------------
-+ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-+ *                        ------------------------------------------
-+ *
-+ *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
-+ *                        ------------------------------------------
-+ *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-+ *                        ------------------------------------------
-+ *
-+ * And so on ...
-+ *
-+ * The data description gives the offset of the calibration data in
-+ * this bytes stream for each sensor.
-+ *
-+ * Each thermal controller can handle up to 4 sensors max, we don't
-+ * care if there are less as the array of calibration is sized to 4
-+ * anyway. The unused sensor slot will be zeroed.
-+ */
-+static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
-+					const struct lvts_ctrl_data *lvts_ctrl_data,
-+					u8 *efuse_calibration)
-+{
-+	int i;
-+
-+	for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
-+		memcpy(&lvts_ctrl->calibration[i],
-+		       efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
-+
-+	return 0;
-+}
-+
-+/*
-+ * The efuse bytes stream can be split into different chunk of
-+ * nvmems. This function reads and concatenate those into a single
-+ * buffer so it can be read sequentially when initializing the
-+ * calibration data.
-+ */
-+static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
-+					const struct lvts_data *lvts_data)
-+{
-+	struct device_node *np = dev_of_node(dev);
-+	struct nvmem_cell *cell;
-+	struct property *prop;
-+	const char *cell_name;
-+
-+	of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
-+		size_t len;
-+		u8 *efuse;
-+
-+		cell = of_nvmem_cell_get(np, cell_name);
-+		if (IS_ERR(cell)) {
-+			dev_err(dev, "Failed to get cell '%s'\n", cell_name);
-+			return PTR_ERR(cell);
-+		}
-+
-+		efuse = nvmem_cell_read(cell, &len);
-+
-+		nvmem_cell_put(cell);
-+
-+		if (IS_ERR(efuse)) {
-+			dev_err(dev, "Failed to read cell '%s'\n", cell_name);
-+			return PTR_ERR(efuse);
-+		}
-+
-+		lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
-+					       lvts_td->calib_len + len, GFP_KERNEL);
-+		if (!lvts_td->calib)
-+			return -ENOMEM;
-+
-+		memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
-+
-+		lvts_td->calib_len += len;
-+
-+		kfree(efuse);
-+	}
-+
-+	return 0;
-+}
-+
-+static int lvts_golden_temp_init(struct device *dev, u32 *value)
-+{
-+	u32 gt;
-+
-+	gt = (*value) >> 24;
-+
-+	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
-+		golden_temp = gt;
-+
-+	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
-+
-+	return 0;
-+}
-+
-+static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
-+					const struct lvts_data *lvts_data)
-+{
-+	size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
-+	struct lvts_ctrl *lvts_ctrl;
-+	int i, ret;
-+
-+	/*
-+	 * Create the calibration bytes stream from efuse data
-+	 */
-+	ret = lvts_calibration_read(dev, lvts_td, lvts_data);
-+	if (ret)
-+		return ret;
-+
-+	/*
-+	 * The golden temp information is contained in the first chunk
-+	 * of efuse data.
-+	 */
-+	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
-+	if (ret)
-+		return ret;
-+
-+	lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
-+	if (!lvts_ctrl)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
-+
-+		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
-+
-+		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
-+				       &lvts_data->lvts_ctrl[i]);
-+		if (ret)
-+			return ret;
-+
-+		ret = lvts_calibration_init(dev, &lvts_ctrl[i],
-+					    &lvts_data->lvts_ctrl[i],
-+					    lvts_td->calib);
-+		if (ret)
-+			return ret;
-+
-+		/*
-+		 * The mode the ctrl will use to read the temperature
-+		 * (filtered or immediate)
-+		 */
-+		lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
-+
-+		/*
-+		 * The temperature to raw temperature must be done
-+		 * after initializing the calibration.
-+		 */
-+		lvts_ctrl[i].hw_tshut_raw_temp =
-+			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+	}
-+
-+	/*
-+	 * We no longer need the efuse bytes stream, let's free it
-+	 */
-+	devm_kfree(dev, lvts_td->calib);
-+
-+	lvts_td->lvts_ctrl = lvts_ctrl;
-+	lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
-+
-+	return 0;
-+}
-+
-+/*
-+ * At this point the configuration register is the only place in the
-+ * driver where we write multiple values. Per hardware constraint,
-+ * each write in the configuration register must be separated by a
-+ * delay of 2 us.
-+ */
-+static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
-+{
-+	int i;
-+
-+	/*
-+	 * Configuration register
-+	 */
-+	for (i = 0; i < nr_cmds; i++) {
-+		writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
-+		usleep_range(2, 4);
-+	}
-+}
-+
-+static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
-+{
-+	/*
-+	 * LVTS_PROTCTL : Thermal Protection Sensor Selection
-+	 *
-+	 * Bits:
-+	 *
-+	 * 19-18 : Sensor to base the protection on
-+	 * 17-16 : Strategy:
-+	 *         00 : Average of 4 sensors
-+	 *         01 : Max of 4 sensors
-+	 *         10 : Selected sensor with bits 19-18
-+	 *         11 : Reserved
-+	 */
-+	writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
-+
-+	/*
-+	 * LVTS_PROTTA : Stage 1 temperature threshold
-+	 * LVTS_PROTTB : Stage 2 temperature threshold
-+	 * LVTS_PROTTC : Stage 3 temperature threshold
-+	 *
-+	 * Bits:
-+	 *
-+	 * 14-0: Raw temperature threshold
-+	 *
-+	 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
-+	 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
-+	 */
-+	writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
-+
-+	/*
-+	 * LVTS_MONINT : Interrupt configuration register
-+	 *
-+	 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
-+	 * register, except we set the bits to enable the interrupt.
-+	 */
-+	writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
-+
-+	return 0;
-+}
-+
-+static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
-+{
-+	int ret;
-+
-+	ret = reset_control_assert(reset);
-+	if (ret)
-+		return ret;
-+
-+	return reset_control_deassert(reset);
-+}
-+
-+/*
-+ * Enable or disable the clocks of a specified thermal controller
-+ */
-+static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
-+{
-+	/*
-+	 * LVTS_CLKEN : Internal LVTS clock
-+	 *
-+	 * Bits:
-+	 *
-+	 * 0 : enable / disable clock
-+	 */
-+	writel(enable, LVTS_CLKEN(lvts_ctrl->base));
-+
-+	return 0;
-+}
-+
-+static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+	u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
-+
-+	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
-+
-+	/*
-+	 * LVTS_ID : Get ID and status of the thermal controller
-+	 *
-+	 * Bits:
-+	 *
-+	 * 0-5	: thermal controller id
-+	 *   7	: thermal controller connection is valid
-+	 */
-+	id = readl(LVTS_ID(lvts_ctrl->base));
-+	if (!(id & BIT(7)))
-+		return -EIO;
-+
-+	return 0;
-+}
-+
-+static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+	/*
-+	 * Write device mask: 0xC1030000
-+	 */
-+	u32 cmds[] = {
-+		0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
-+		0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
-+		0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
-+		0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
-+	};
-+
-+	lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
-+
-+	return 0;
-+}
-+
-+static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+	int i;
-+	void __iomem *lvts_edata[] = {
-+		LVTS_EDATA00(lvts_ctrl->base),
-+		LVTS_EDATA01(lvts_ctrl->base),
-+		LVTS_EDATA02(lvts_ctrl->base),
-+		LVTS_EDATA03(lvts_ctrl->base)
-+	};
-+
-+	/*
-+	 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
-+	 *
-+	 * Bits:
-+	 *
-+	 * 20-0 : Efuse value for normalization data
-+	 */
-+	for (i = 0; i < LVTS_SENSOR_MAX; i++)
-+		writel(lvts_ctrl->calibration[i], lvts_edata[i]);
-+
-+	return 0;
-+}
-+
-+static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+	u32 value;
-+
-+	/*
-+	 * LVTS_TSSEL : Sensing point index numbering
-+	 *
-+	 * Bits:
-+	 *
-+	 * 31-24: ADC Sense 3
-+	 * 23-16: ADC Sense 2
-+	 * 15-8	: ADC Sense 1
-+	 * 7-0	: ADC Sense 0
-+	 */
-+	value = LVTS_TSSEL_CONF;
-+	writel(value, LVTS_TSSEL(lvts_ctrl->base));
-+
-+	/*
-+	 * LVTS_CALSCALE : ADC voltage round
-+	 */
-+	value = 0x300;
-+	value = LVTS_CALSCALE_CONF;
-+
-+	/*
-+	 * LVTS_MSRCTL0 : Sensor filtering strategy
-+	 *
-+	 * Filters:
-+	 *
-+	 * 000 : One sample
-+	 * 001 : Avg 2 samples
-+	 * 010 : 4 samples, drop min and max, avg 2 samples
-+	 * 011 : 6 samples, drop min and max, avg 4 samples
-+	 * 100 : 10 samples, drop min and max, avg 8 samples
-+	 * 101 : 18 samples, drop min and max, avg 16 samples
-+	 *
-+	 * Bits:
-+	 *
-+	 * 0-2  : Sensor0 filter
-+	 * 3-5  : Sensor1 filter
-+	 * 6-8  : Sensor2 filter
-+	 * 9-11 : Sensor3 filter
-+	 */
-+	value = LVTS_HW_FILTER << 9 |  LVTS_HW_FILTER << 6 |
-+			LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
-+	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
-+
-+	/*
-+	 * LVTS_MSRCTL1 : Measurement control
-+	 *
-+	 * Bits:
-+	 *
-+	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
-+	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
-+	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
-+	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
-+	 *
-+	 * That configuration will ignore the filtering and the delays
-+	 * introduced below in MONCTL1 and MONCTL2
-+	 */
-+	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
-+		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
-+		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
-+	}
-+
-+	/*
-+	 * LVTS_MONCTL1 : Period unit and group interval configuration
-+	 *
-+	 * The clock source of LVTS thermal controller is 26MHz.
-+	 *
-+	 * The period unit is a time base for all the interval delays
-+	 * specified in the registers. By default we use 12. The time
-+	 * conversion is done by multiplying by 256 and 1/26.10^6
-+	 *
-+	 * An interval delay multiplied by the period unit gives the
-+	 * duration in seconds.
-+	 *
-+	 * - Filter interval delay is a delay between two samples of
-+	 * the same sensor.
-+	 *
-+	 * - Sensor interval delay is a delay between two samples of
-+	 * different sensors.
-+	 *
-+	 * - Group interval delay is a delay between different rounds.
-+	 *
-+	 * For example:
-+	 *     If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
-+	 *     and two sensors, TS1 and TS2, are in a LVTS thermal controller
-+	 *     and then
-+	 *     Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
-+	 *     Filter interval delay = 1 * Period unit = 118.149us
-+	 *     Sensor interval delay = 2 * Period unit = 236.298us
-+	 *     Group interval delay = 1 * Period unit = 118.149us
-+	 *
-+	 *     TS1    TS1 ... TS1    TS2    TS2 ... TS2    TS1...
-+	 *        <--> Filter interval delay
-+	 *                       <--> Sensor interval delay
-+	 *                                             <--> Group interval delay
-+	 * Bits:
-+	 *      29 - 20 : Group interval
-+	 *      16 - 13 : Send a single interrupt when crossing the hot threshold (1)
-+	 *                or an interrupt everytime the hot threshold is crossed (0)
-+	 *       9 - 0  : Period unit
-+	 *
-+	 */
-+	value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
-+	writel(value, LVTS_MONCTL1(lvts_ctrl->base));
-+
-+	/*
-+	 * LVTS_MONCTL2 : Filtering and sensor interval
-+	 *
-+	 * Bits:
-+	 *
-+	 *      25-16 : Interval unit in PERIOD_UNIT between sample on
-+	 *              the same sensor, filter interval
-+	 *       9-0  : Interval unit in PERIOD_UNIT between each sensor
-+	 *
-+	 */
-+	value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
-+	writel(value, LVTS_MONCTL2(lvts_ctrl->base));
-+
-+	return lvts_irq_init(lvts_ctrl);
-+}
-+
-+static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+	struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
-+	struct thermal_zone_device *tz;
-+	u32 sensor_map = 0;
-+	int i;
-+
-+	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
-+
-+		int dt_id = lvts_sensors[i].dt_id;
-+
-+		tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
-+						   &lvts_ops);
-+		if (IS_ERR(tz)) {
-+			/*
-+			 * This thermal zone is not described in the
-+			 * device tree. It is not an error from the
-+			 * thermal OF code POV, we just continue.
-+			 */
-+			if (PTR_ERR(tz) == -ENODEV)
-+				continue;
-+
-+			return PTR_ERR(tz);
-+		}
-+
-+		/*
-+		 * The thermal zone pointer will be needed in the
-+		 * interrupt handler, we store it in the sensor
-+		 * structure. The thermal domain structure will be
-+		 * passed to the interrupt handler private data as the
-+		 * interrupt is shared for all the controller
-+		 * belonging to the thermal domain.
-+		 */
-+		lvts_sensors[i].tz = tz;
-+
-+		/*
-+		 * This sensor was correctly associated with a thermal
-+		 * zone, let's set the corresponding bit in the sensor
-+		 * map, so we can enable the temperature monitoring in
-+		 * the hardware thermal controller.
-+		 */
-+		sensor_map |= BIT(i);
-+	}
-+
-+	/*
-+	 * Bits:
-+	 *      9: Single point access flow
-+	 *    0-3: Enable sensing point 0-3
-+	 *
-+	 * The initialization of the thermal zones give us
-+	 * which sensor point to enable. If any thermal zone
-+	 * was not described in the device tree, it won't be
-+	 * enabled here in the sensor map.
-+	 */
-+	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+
-+	return 0;
-+}
-+
-+static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
-+					const struct lvts_data *lvts_data)
-+{
-+	struct lvts_ctrl *lvts_ctrl;
-+	int i, ret;
-+
-+	ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
-+	if (ret)
-+		return ret;
-+
-+	ret = lvts_domain_reset(dev, lvts_td->reset);
-+	if (ret) {
-+		dev_dbg(dev, "Failed to reset domain");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+		lvts_ctrl = &lvts_td->lvts_ctrl[i];
-+
-+		/*
-+		 * Initialization steps:
-+		 *
-+		 * - Enable the clock
-+		 * - Connect to the LVTS
-+		 * - Initialize the LVTS
-+		 * - Prepare the calibration data
-+		 * - Select monitored sensors
-+		 * [ Configure sampling ]
-+		 * [ Configure the interrupt ]
-+		 * - Start measurement
-+		 */
-+		ret = lvts_ctrl_set_enable(lvts_ctrl, true);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to enable LVTS clock");
-+			return ret;
-+		}
-+
-+		ret = lvts_ctrl_connect(dev, lvts_ctrl);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to connect to LVTS controller");
-+			return ret;
-+		}
-+
-+		ret = lvts_ctrl_initialize(dev, lvts_ctrl);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to initialize controller");
-+			return ret;
-+		}
-+
-+		ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to calibrate controller");
-+			return ret;
-+		}
-+
-+		ret = lvts_ctrl_configure(dev, lvts_ctrl);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to configure controller");
-+			return ret;
-+		}
-+
-+		ret = lvts_ctrl_start(dev, lvts_ctrl);
-+		if (ret) {
-+			dev_dbg(dev, "Failed to start controller");
-+			return ret;
-+		}
-+	}
-+
-+	return lvts_debugfs_init(dev, lvts_td);
-+}
-+
-+static int lvts_probe(struct platform_device *pdev)
-+{
-+	const struct lvts_data *lvts_data;
-+	struct lvts_domain *lvts_td;
-+	struct device *dev = &pdev->dev;
-+	struct resource *res;
-+	int irq, ret;
-+
-+	lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
-+	if (!lvts_td)
-+		return -ENOMEM;
-+
-+	lvts_data = of_device_get_match_data(dev);
-+
-+	lvts_td->clk = devm_clk_get_enabled(dev, NULL);
-+	if (IS_ERR(lvts_td->clk))
-+		return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
-+
-+	res = platform_get_mem_or_io(pdev, 0);
-+	if (!res)
-+		return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
-+
-+	lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-+	if (IS_ERR(lvts_td->base))
-+		return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
-+
-+	lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
-+	if (IS_ERR(lvts_td->reset))
-+		return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0)
-+		return dev_err_probe(dev, irq, "No irq resource\n");
-+
-+	ret = lvts_domain_init(dev, lvts_td, lvts_data);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
-+
-+	/*
-+	 * At this point the LVTS is initialized and enabled. We can
-+	 * safely enable the interrupt.
-+	 */
-+	ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
-+					IRQF_ONESHOT, dev_name(dev), lvts_td);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to request interrupt\n");
-+
-+	platform_set_drvdata(pdev, lvts_td);
-+
-+	return 0;
-+}
-+
-+static int lvts_remove(struct platform_device *pdev)
-+{
-+	struct lvts_domain *lvts_td;
-+	int i;
-+
-+	lvts_td = platform_get_drvdata(pdev);
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
-+
-+	lvts_debugfs_exit(lvts_td);
-+
-+	return 0;
-+}
-+
-+static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
-+	{
-+		.cal_offset = { 0x04, 0x07 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_MCU_BIG_CPU0 },
-+			{ .dt_id = MT8195_MCU_BIG_CPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x0,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	},
-+	{
-+		.cal_offset = { 0x0d, 0x10 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_MCU_BIG_CPU2 },
-+			{ .dt_id = MT8195_MCU_BIG_CPU3 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x100,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	},
-+	{
-+		.cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_MCU_LITTLE_CPU0 },
-+			{ .dt_id = MT8195_MCU_LITTLE_CPU1 },
-+			{ .dt_id = MT8195_MCU_LITTLE_CPU2 },
-+			{ .dt_id = MT8195_MCU_LITTLE_CPU3 }
-+		},
-+		.num_lvts_sensor = 4,
-+		.offset = 0x200,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	}
-+};
-+
-+static const struct lvts_data mt8195_lvts_mcu_data = {
-+	.lvts_ctrl	= mt8195_lvts_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
-+};
-+
-+static const struct of_device_id lvts_of_match[] = {
-+	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, lvts_of_match);
-+
-+static struct platform_driver lvts_driver = {
-+	.probe = lvts_probe,
-+	.remove = lvts_remove,
-+	.driver = {
-+		.name = "mtk-lvts-thermal",
-+		.of_match_table = lvts_of_match,
-+	},
-+};
-+module_platform_driver(lvts_driver);
-+
-+MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
-+MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
deleted file mode 100644
index b6a5f64090..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
+++ /dev/null
@@ -1,186 +0,0 @@
-From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:24 +0100
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers
-
-Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- .../thermal/mediatek,lvts-thermal.yaml        | 142 ++++++++++++++++++
- .../thermal/mediatek,lvts-thermal.h           |  19 +++
- 2 files changed, 161 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
- create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
-@@ -0,0 +1,142 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
-+
-+maintainers:
-+  - Balsam CHIHI <bchihi@baylibre.com>
-+
-+description: |
-+  LVTS is a thermal management architecture composed of three subsystems,
-+  a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
-+  a Converter - Low Voltage Thermal Sensor converter (LVTS), and
-+  a Digital controller (LVTS_CTRL).
-+
-+properties:
-+  compatible:
-+    enum:
-+      - mediatek,mt8192-lvts-ap
-+      - mediatek,mt8192-lvts-mcu
-+      - mediatek,mt8195-lvts-ap
-+      - mediatek,mt8195-lvts-mcu
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    maxItems: 1
-+
-+  resets:
-+    maxItems: 1
-+    description: LVTS reset for clearing temporary data on AP/MCU.
-+
-+  nvmem-cells:
-+    minItems: 1
-+    items:
-+      - description: Calibration eFuse data 1 for LVTS
-+      - description: Calibration eFuse data 2 for LVTS
-+
-+  nvmem-cell-names:
-+    minItems: 1
-+    items:
-+      - const: lvts-calib-data-1
-+      - const: lvts-calib-data-2
-+
-+  "#thermal-sensor-cells":
-+    const: 1
-+
-+allOf:
-+  - $ref: thermal-sensor.yaml#
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - mediatek,mt8192-lvts-ap
-+              - mediatek,mt8192-lvts-mcu
-+    then:
-+      properties:
-+        nvmem-cells:
-+          maxItems: 1
-+
-+        nvmem-cell-names:
-+          maxItems: 1
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - mediatek,mt8195-lvts-ap
-+              - mediatek,mt8195-lvts-mcu
-+    then:
-+      properties:
-+        nvmem-cells:
-+          minItems: 2
-+
-+        nvmem-cell-names:
-+          minItems: 2
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - resets
-+  - nvmem-cells
-+  - nvmem-cell-names
-+  - "#thermal-sensor-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/clock/mt8195-clk.h>
-+    #include <dt-bindings/reset/mt8195-resets.h>
-+    #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
-+
-+    soc {
-+      #address-cells = <2>;
-+      #size-cells = <2>;
-+
-+      lvts_mcu: thermal-sensor@11278000 {
-+        compatible = "mediatek,mt8195-lvts-mcu";
-+        reg = <0 0x11278000 0 0x1000>;
-+        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
-+        clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
-+        resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
-+        nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
-+        nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
-+        #thermal-sensor-cells = <1>;
-+      };
-+    };
-+
-+    thermal_zones: thermal-zones {
-+      cpu0-thermal {
-+        polling-delay = <1000>;
-+        polling-delay-passive = <250>;
-+        thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
-+
-+        trips {
-+          cpu0_alert: trip-alert {
-+            temperature = <85000>;
-+            hysteresis = <2000>;
-+            type = "passive";
-+          };
-+
-+          cpu0_crit: trip-crit {
-+            temperature = <100000>;
-+            hysteresis = <2000>;
-+            type = "critical";
-+          };
-+        };
-+      };
-+    };
---- /dev/null
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -0,0 +1,19 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Balsam CHIHI <bchihi@baylibre.com>
-+ */
-+
-+#ifndef __MEDIATEK_LVTS_DT_H
-+#define __MEDIATEK_LVTS_DT_H
-+
-+#define MT8195_MCU_BIG_CPU0     0
-+#define MT8195_MCU_BIG_CPU1     1
-+#define MT8195_MCU_BIG_CPU2     2
-+#define MT8195_MCU_BIG_CPU3     3
-+#define MT8195_MCU_LITTLE_CPU0  4
-+#define MT8195_MCU_LITTLE_CPU1  5
-+#define MT8195_MCU_LITTLE_CPU2  6
-+#define MT8195_MCU_LITTLE_CPU3  7
-+
-+#endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
deleted file mode 100644
index efb0d8b64f..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 7 Mar 2023 16:45:21 +0100
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal
- controllers for mt8195
-
-Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com
----
- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -16,4 +16,14 @@
- #define MT8195_MCU_LITTLE_CPU2  6
- #define MT8195_MCU_LITTLE_CPU3  7
- 
-+#define MT8195_AP_VPU0  8
-+#define MT8195_AP_VPU1  9
-+#define MT8195_AP_GPU0  10
-+#define MT8195_AP_GPU1  11
-+#define MT8195_AP_VDEC  12
-+#define MT8195_AP_IMG   13
-+#define MT8195_AP_INFRA 14
-+#define MT8195_AP_CAM0  15
-+#define MT8195_AP_CAM1  16
-+
- #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
deleted file mode 100644
index c68969321e..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:29 +0100
-Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor
-
-The thermal zone device structure is exposed to the different drivers
-and obviously they access the internals while that should be
-restricted to the core thermal code.
-
-In order to self-encapsulate the thermal core code, we need to prevent
-the drivers accessing directly the thermal zone structure and provide
-accessor functions to deal with.
-
-Provide an accessor to the 'devdata' structure and make use of it in
-the different drivers.
-
-No functional changes intended.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-Acked-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/thermal_core.c | 6 ++++++
- include/linux/thermal.h        | 7 +++++++
- 2 files changed, 13 insertions(+)
-
---- a/drivers/thermal/thermal_core.c
-+++ b/drivers/thermal/thermal_core.c
-@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone
- }
- EXPORT_SYMBOL_GPL(thermal_zone_device_register);
- 
-+void *thermal_zone_device_priv(struct thermal_zone_device *tzd)
-+{
-+	return tzd->devdata;
-+}
-+EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
-+
- /**
-  * thermal_zone_device_unregister - removes the registered thermal zone device
-  * @tz: the thermal zone device to remove
---- a/include/linux/thermal.h
-+++ b/include/linux/thermal.h
-@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips(
- 					void *, struct thermal_zone_device_ops *,
- 					struct thermal_zone_params *, int, int);
- 
-+void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
-+
- int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
- 				     struct thermal_cooling_device *,
- 				     unsigned long, unsigned long,
-@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse
- 		struct thermal_zone_device *tz)
- { return -ENODEV; }
- 
-+static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz)
-+{
-+	return NULL;
-+}
-+
- static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
- { return -ENODEV; }
- 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
deleted file mode 100644
index 66d3c9e302..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:38 +0100
-Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type'
- accessor
-
-The thermal zone device structure is exposed via the exported
-thermal.h header. This structure should stay private the thermal core
-code. In order to encapsulate the structure, let's add an accessor to
-get the 'type' of the thermal zone.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/thermal_core.c | 6 ++++++
- include/linux/thermal.h        | 6 ++++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/thermal/thermal_core.c
-+++ b/drivers/thermal/thermal_core.c
-@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th
- }
- EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
- 
-+const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
-+{
-+	return tzd->type;
-+}
-+EXPORT_SYMBOL_GPL(thermal_zone_device_type);
-+
- /**
-  * thermal_zone_device_unregister - removes the registered thermal zone device
-  * @tz: the thermal zone device to remove
---- a/include/linux/thermal.h
-+++ b/include/linux/thermal.h
-@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips(
- 					struct thermal_zone_params *, int, int);
- 
- void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
-+const char *thermal_zone_device_type(struct thermal_zone_device *tzd);
- 
- int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
- 				     struct thermal_cooling_device *,
-@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_
- {
- 	return NULL;
- }
-+
-+static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
-+{
-+	return NULL;
-+}
- 
- static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
- { return -ENODEV; }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
deleted file mode 100644
index 57bc910d3e..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:30 +0100
-Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor
- in thermal located drivers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The thermal zone device structure is exposed to the different drivers
-and obviously they access the internals while that should be
-restricted to the core thermal code.
-
-In order to self-encapsulate the thermal core code, we need to prevent
-the drivers accessing directly the thermal zone structure and provide
-accessor functions to deal with.
-
-Use the devdata accessor introduced in the previous patch.
-
-No functional changes intended.
-
-[skipped drivers not relevant for mediatek target]
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> #R-Car
-Acked-by: Mark Brown <broonie@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc and lvts
-Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek lvts
-Reviewed-by: Adam Ward <DLG-Adam.Ward.opensource@dm.renesas.com> #da9062
-Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>  #spread
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
-Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com> #Broadcom
-Reviewed-by: Dhruva Gole <d-gole@ti.com> # K3 bandgap
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
-Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> #uniphier
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/auxadc_thermal.c           |  2 +-
- drivers/thermal/mediatek/lvts_thermal.c             |  4 ++--
- 43 files changed, 71 insertions(+), 73 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature(
- 
- static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
- {
--	struct mtk_thermal *mt = tz->devdata;
-+	struct mtk_thermal *mt = thermal_zone_device_priv(tz);
- 	int i;
- 	int tempmax = INT_MIN;
- 
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat
- 
- static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
- {
--	struct lvts_sensor *lvts_sensor = tz->devdata;
-+	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- 	void __iomem *msr = lvts_sensor->msr;
- 	u32 value;
- 
-@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_
- 
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
--	struct lvts_sensor *lvts_sensor = tz->devdata;
-+	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- 	void __iomem *base = lvts_sensor->base;
- 	u32 raw_low = lvts_temp_to_raw(low);
- 	u32 raw_high = lvts_temp_to_raw(high);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
deleted file mode 100644
index 647b3b0eca..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch
+++ /dev/null
@@ -1,201 +0,0 @@
-From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:36 +0100
-Subject: [PATCH 08/42] thermal/hwmon: Use the right device for
- devm_thermal_add_hwmon_sysfs()
-
-The devres variant of thermal_add_hwmon_sysfs() only takes the thermal
-zone structure pointer as parameter.
-
-Actually, it uses the tz->device to add it in the devres list.
-
-It is preferable to use the device registering the thermal zone
-instead of the thermal zone device itself. That prevents the driver
-accessing the thermal zone structure internals and it is from my POV
-more correct regarding how devm_ is used.
-
-[skipped imx thermal which did not apply cleanly and irrelevant on
-mediatek target]
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> #amlogic_thermal
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/amlogic_thermal.c                  | 2 +-
- drivers/thermal/imx_sc_thermal.c                   | 2 +-
- drivers/thermal/k3_bandgap.c                       | 2 +-
- drivers/thermal/mediatek/auxadc_thermal.c          | 2 +-
- drivers/thermal/qcom/qcom-spmi-adc-tm5.c           | 2 +-
- drivers/thermal/qcom/qcom-spmi-temp-alarm.c        | 2 +-
- drivers/thermal/qcom/tsens.c                       | 2 +-
- drivers/thermal/qoriq_thermal.c                    | 2 +-
- drivers/thermal/sun8i_thermal.c                    | 2 +-
- drivers/thermal/tegra/tegra30-tsensor.c            | 2 +-
- drivers/thermal/thermal_hwmon.c                    | 4 ++--
- drivers/thermal/thermal_hwmon.h                    | 4 ++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 13 files changed, 15 insertions(+), 15 deletions(-)
-
---- a/drivers/thermal/amlogic_thermal.c
-+++ b/drivers/thermal/amlogic_thermal.c
-@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct
- 		return ret;
- 	}
- 
--	if (devm_thermal_add_hwmon_sysfs(pdata->tzd))
-+	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd))
- 		dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n");
- 
- 	ret = amlogic_thermal_initialize(pdata);
---- a/drivers/thermal/imx_sc_thermal.c
-+++ b/drivers/thermal/imx_sc_thermal.c
-@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p
- 			return ret;
- 		}
- 
--		if (devm_thermal_add_hwmon_sysfs(sensor->tzd))
-+		if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd))
- 			dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
- 	}
- 
---- a/drivers/thermal/k3_bandgap.c
-+++ b/drivers/thermal/k3_bandgap.c
-@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf
- 			goto err_alloc;
- 		}
- 
--		if (devm_thermal_add_hwmon_sysfs(data[id].tzd))
-+		if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd))
- 			dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
- 	}
- 
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_peri_therm;
- 	}
- 
--	ret = devm_thermal_add_hwmon_sysfs(tzdev);
-+	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
- 	if (ret)
- 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
- 
---- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
-+++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
-@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a
- 			return PTR_ERR(tzd);
- 		}
- 		adc_tm->channels[i].tzd = tzd;
--		if (devm_thermal_add_hwmon_sysfs(tzd))
-+		if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd))
- 			dev_warn(adc_tm->dev,
- 				 "Failed to add hwmon sysfs attributes\n");
- 	}
---- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
-+++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
-@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform
- 		return ret;
- 	}
- 
--	if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
-+	if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev))
- 		dev_warn(&pdev->dev,
- 			 "Failed to add hwmon sysfs attributes\n");
- 
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p
- 		if (priv->ops->enable)
- 			priv->ops->enable(priv, i);
- 
--		if (devm_thermal_add_hwmon_sysfs(tzd))
-+		if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd))
- 			dev_warn(priv->dev,
- 				 "Failed to add hwmon sysfs attributes\n");
- 	}
---- a/drivers/thermal/qoriq_thermal.c
-+++ b/drivers/thermal/qoriq_thermal.c
-@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s
- 			return ret;
- 		}
- 
--		if (devm_thermal_add_hwmon_sysfs(tzd))
-+		if (devm_thermal_add_hwmon_sysfs(dev, tzd))
- 			dev_warn(dev,
- 				 "Failed to add hwmon sysfs attributes\n");
- 
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths
- 		if (IS_ERR(tmdev->sensor[i].tzd))
- 			return PTR_ERR(tmdev->sensor[i].tzd);
- 
--		if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
-+		if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd))
- 			dev_warn(tmdev->dev,
- 				 "Failed to add hwmon sysfs attributes\n");
- 	}
---- a/drivers/thermal/tegra/tegra30-tsensor.c
-+++ b/drivers/thermal/tegra/tegra30-tsensor.c
-@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe
- 		return 0;
- 	}
- 
--	if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
-+	if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd))
- 		dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
- 
- 	return 0;
---- a/drivers/thermal/thermal_hwmon.c
-+++ b/drivers/thermal/thermal_hwmon.c
-@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s
- 	thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res);
- }
- 
--int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
-+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
- {
- 	struct thermal_zone_device **ptr;
- 	int ret;
-@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct
- 	}
- 
- 	*ptr = tz;
--	devres_add(&tz->device, ptr);
-+	devres_add(dev, ptr);
- 
- 	return ret;
- }
---- a/drivers/thermal/thermal_hwmon.h
-+++ b/drivers/thermal/thermal_hwmon.h
-@@ -17,7 +17,7 @@
- 
- #ifdef CONFIG_THERMAL_HWMON
- int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
--int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
-+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz);
- void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz);
- #else
- static inline int
-@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z
- }
- 
- static inline int
--devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
-+devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
- {
- 	return 0;
- }
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b
- 	ti_bandgap_set_sensor_data(bgp, id, data);
- 	ti_bandgap_write_update_interval(bgp, data->sensor_id, interval);
- 
--	if (devm_thermal_add_hwmon_sysfs(data->ti_thermal))
-+	if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal))
- 		dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n");
- 
- 	return 0;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
deleted file mode 100644
index 9dedc2cb68..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:37 +0100
-Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone
- structure field
-
-Some drivers are directly using the thermal zone's 'device' structure
-field.
-
-Use the driver device pointer instead of the thermal zone device when
-it is available.
-
-Remove the traces when they are duplicate with the traces in the core
-code.
-
-[again skipped imx_thermal.c]
-
-Cc: Jean Delvare <jdelvare@suse.com>
-Cc: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek LVTS
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/lvts_thermal.c            | 4 ++--
- drivers/thermal/thermal_hwmon.c                    | 4 ++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 3 files changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal
- 	 * 14-0 : Raw temperature for threshold
- 	 */
- 	if (low != -INT_MAX) {
--		dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
-+		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
- 		writel(raw_low, LVTS_H2NTHRE(base));
- 	}
- 
-@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal
- 	 *
- 	 * 14-0 : Raw temperature for threshold
- 	 */
--	dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
-+	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
- 	writel(raw_high, LVTS_HTHRE(base));
- 
- 	return 0;
---- a/drivers/thermal/thermal_hwmon.c
-+++ b/drivers/thermal/thermal_hwmon.c
-@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t
- 	hwmon = thermal_hwmon_lookup_by_type(tz);
- 	if (unlikely(!hwmon)) {
- 		/* Should never happen... */
--		dev_dbg(&tz->device, "hwmon device lookup failed!\n");
-+		dev_dbg(hwmon->device, "hwmon device lookup failed!\n");
- 		return;
- 	}
- 
- 	temp = thermal_hwmon_lookup_temp(hwmon, tz);
- 	if (unlikely(!temp)) {
- 		/* Should never happen... */
--		dev_dbg(&tz->device, "temperature input lookup failed!\n");
-+		dev_dbg(hwmon->device, "temperature input lookup failed!\n");
- 		return;
- 	}
- 
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_
- 
- 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
- 
--	dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n",
-+	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
- 		data->ti_thermal->type);
- }
- 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
deleted file mode 100644
index 8cec9aba97..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:41 +0100
-Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor
-
-Replace the accesses to 'tz->type' by its accessor version in order to
-self-encapsulate the thermal_zone_device structure.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Ido Schimmel <idosch@nvidia.com> #mlxsw
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +-
- drivers/thermal/mediatek/lvts_thermal.c            | 6 ++++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 3 files changed, 6 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
-+++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
-@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct
- 
- 	if (crit_temp > emerg_temp) {
- 		dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n",
--			 tz->tzdev->type, crit_temp, emerg_temp);
-+			 thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp);
- 		return 0;
- 	}
- 
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal
- 	 * 14-0 : Raw temperature for threshold
- 	 */
- 	if (low != -INT_MAX) {
--		pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
-+		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
-+			 thermal_zone_device_type(tz), low);
- 		writel(raw_low, LVTS_H2NTHRE(base));
- 	}
- 
-@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal
- 	 *
- 	 * 14-0 : Raw temperature for threshold
- 	 */
--	pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
-+	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
-+		 thermal_zone_device_type(tz), high);
- 	writel(raw_high, LVTS_HTHRE(base));
- 
- 	return 0;
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_
- 	thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
- 
- 	dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
--		data->ti_thermal->type);
-+		thermal_zone_device_type(data->ti_thermal));
- }
- 
- /**
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
deleted file mode 100644
index 68f41fdd16..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001
-From: Markus Schneider-Pargmann <msp@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:43 +0100
-Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement
- tweaks
-
-Add logic in order to be able to turn on the control buffer on MT8365.
-This change now allows to have control buffer support for MTK_THERMAL_V1,
-and it allows to define the register offset, and mask used to enable it.
-
-Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Signed-off-by: Fabien Parent <fparent@baylibre.com>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++--------
- 1 file changed, 19 insertions(+), 9 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -307,6 +307,9 @@ struct mtk_thermal_data {
- 	bool need_switch_bank;
- 	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
- 	enum mtk_thermal_version version;
-+	u32 apmixed_buffer_ctl_reg;
-+	u32 apmixed_buffer_ctl_mask;
-+	u32 apmixed_buffer_ctl_set;
- };
- 
- struct mtk_thermal {
-@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7
- 	.adcpnp = mt7622_adcpnp,
- 	.sensor_mux_values = mt7622_mux_values,
- 	.version = MTK_THERMAL_V2,
-+	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
-+	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
-+	.apmixed_buffer_ctl_set = BIT(0),
- };
- 
- /*
-@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the
- };
- MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
- 
--static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
-+static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
-+				       void __iomem *apmixed_base)
- {
--	int tmp;
-+	u32 tmp;
-+
-+	if (!mt->conf->apmixed_buffer_ctl_reg)
-+		return;
- 
--	tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
--	tmp &= ~(0x37);
--	tmp |= 0x1;
--	writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
-+	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
-+	tmp &= mt->conf->apmixed_buffer_ctl_mask;
-+	tmp |= mt->conf->apmixed_buffer_ctl_set;
-+	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
- 	udelay(200);
- }
- 
-@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat
- 		goto err_disable_clk_auxadc;
- 	}
- 
--	if (mt->conf->version != MTK_THERMAL_V1) {
--		mtk_thermal_turn_on_buffer(apmixed_base);
-+	mtk_thermal_turn_on_buffer(mt, apmixed_base);
-+
-+	if (mt->conf->version != MTK_THERMAL_V2)
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
--	}
- 
- 	if (mt->conf->version == MTK_THERMAL_V1)
- 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
deleted file mode 100644
index 285c6f6a7b..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001
-From: Fabien Parent <fparent@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:44 +0100
-Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC
-
-MT8365 is similar to the other SoCs supported by the driver. It has only
-one bank and 3 actual sensors that can be multiplexed. There is another
-one sensor that does not have usable data.
-
-Signed-off-by: Fabien Parent <fparent@baylibre.com>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++
- 1 file changed, 68 insertions(+)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -31,6 +31,7 @@
- #define AUXADC_CON2_V		0x010
- #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
- 
-+#define APMIXED_SYS_TS_CON0	0x600
- #define APMIXED_SYS_TS_CON1	0x604
- 
- /* Thermal Controller Registers */
-@@ -281,6 +282,17 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor  */
- #define MT7986_CALIBRATION		165
- 
-+/* MT8365 */
-+#define MT8365_TEMP_AUXADC_CHANNEL 11
-+#define MT8365_CALIBRATION 164
-+#define MT8365_NUM_CONTROLLER 1
-+#define MT8365_NUM_BANKS 1
-+#define MT8365_NUM_SENSORS 3
-+#define MT8365_NUM_SENSORS_PER_ZONE 3
-+#define MT8365_TS1 0
-+#define MT8365_TS2 1
-+#define MT8365_TS3 2
-+
- struct mtk_thermal;
- 
- struct thermal_bank_cfg {
-@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798
- static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
- static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
- 
-+/* MT8365 thermal sensor data */
-+static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
-+	MT8365_TS1, MT8365_TS2, MT8365_TS3
-+};
-+
-+static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
-+};
-+
-+static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
-+	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
-+};
-+
-+static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
-+static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
-+
-+static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
-+
- /*
-  * The MT8173 thermal controller has four banks. Each bank can read up to
-  * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2
- };
- 
- /*
-+ * The MT8365 thermal controller has one bank, which can read up to
-+ * four temperature sensors simultaneously. The MT8365 has a total of 3
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt8365_thermal_data = {
-+	.auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
-+	.num_banks = MT8365_NUM_BANKS,
-+	.num_sensors = MT8365_NUM_SENSORS,
-+	.vts_index = mt8365_vts_index,
-+	.cali_val = MT8365_CALIBRATION,
-+	.num_controller = MT8365_NUM_CONTROLLER,
-+	.controller_offset = mt8365_tc_offset,
-+	.need_switch_bank = false,
-+	.bank_data = {
-+		{
-+			.num_sensors = MT8365_NUM_SENSORS,
-+			.sensors = mt8365_bank_data
-+		},
-+	},
-+	.msr = mt8365_msr,
-+	.adcpnp = mt8365_adcpnp,
-+	.sensor_mux_values = mt8365_mux_values,
-+	.version = MTK_THERMAL_V1,
-+	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
-+	.apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
-+	.apmixed_buffer_ctl_set = 0,
-+};
-+
-+/*
-  * The MT2712 thermal controller has one bank, which can read up to
-  * four temperature sensors simultaneously. The MT2712 has a total of 4
-  * temperature sensors.
-@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the
- 	{
- 		.compatible = "mediatek,mt8183-thermal",
- 		.data = (void *)&mt8183_thermal_data,
-+	},
-+	{
-+		.compatible = "mediatek,mt8365-thermal",
-+		.data = (void *)&mt8365_thermal_data,
- 	}, {
- 	},
- };
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
deleted file mode 100644
index 5c99aa80c1..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001
-From: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:46 +0100
-Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks
- initialization
-
-Thermal sensor reads performed immediately after thermal bank
-initialization returns bogus values. This is currently tackled by returning
-0 if the temperature is bogus (exceeding 200000).
-
-Instead, add a delay between the bank init and the thermal zone device
-register to properly fix this.
-
-Signed-off-by: Michael Kao <michael.kao@mediatek.com>
-Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 11 +++--------
- 1 file changed, 3 insertions(+), 8 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature(
- 			mt, conf->bank_data[bank->id].sensors[i], raw);
- 
- 
--		/*
--		 * The first read of a sensor often contains very high bogus
--		 * temperature value. Filter these out so that the system does
--		 * not immediately shut down.
--		 */
--		if (temp > 200000)
--			temp = 0;
--
- 		if (temp > max)
- 			max = temp;
- 	}
-@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat
- 
- 	platform_set_drvdata(pdev, mt);
- 
-+	/* Delay for thermal banks to be ready */
-+	msleep(30);
-+
- 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- 					      &mtk_thermal_ops);
- 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
deleted file mode 100644
index 734f5c1e77..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wenst@chromium.org>
-Date: Tue, 28 Mar 2023 11:10:17 +0800
-Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1
- interrupt status bitmask
-
-The binary representation for sensor 1 interrupt status was incorrectly
-assembled, when compared to the full table given in the same comment
-section. The conversion into hex was also incorrect, leading to
-incorrect interrupt status bitmask for sensor 1. This would cause the
-driver to incorrectly identify changes for sensor 1, when in fact it
-was sensor 0, or a sensor access time out.
-
-Fix the binary and hex representations in the comments, and the actual
-bitmask macro.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org
----
- drivers/thermal/mediatek/lvts_thermal.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -66,7 +66,7 @@
- #define LVTS_MONINT_CONF			0x9FBF7BDE
- 
- #define LVTS_INT_SENSOR0			0x0009001F
--#define LVTS_INT_SENSOR1			0X000881F0
-+#define LVTS_INT_SENSOR1			0x001203E0
- #define LVTS_INT_SENSOR2			0x00247C00
- #define LVTS_INT_SENSOR3			0x1FC00000
- 
-@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler
- 	 *                  => 0x1FC00000
- 	 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
- 	 *                  => 0x00247C00
--	 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
--	 *                  => 0X000881F0
-+	 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
-+	 *                  => 0X001203E0
- 	 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
- 	 *                  => 0x0009001F
- 	 */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
deleted file mode 100644
index d09c2055a3..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 7 Mar 2023 16:45:22 +0100
-Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
- for mt8195
-
-Add MT8195 AP Domain support to LVTS Driver.
-
-Take the opportunity to update the comments to show calibration data
-information related to the new domain.
-
-[dlezcano]: Massaged a bit the changelog
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
- 1 file changed, 74 insertions(+), 20 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
-  * The efuse blob values follows the sensor enumeration per thermal
-  * controller. The decoding of the stream is as follow:
-  *
-- *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
-- *                        ------------------------------------------
-- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
-- *                        ------------------------------------------
-+ * stream index map for MCU Domain :
-  *
-- *                        <--sensor1--><-0-> <----big1 ???---> <-sen
-- *                        ------------------------------------------
-- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-- *                        ------------------------------------------
-+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-+ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
-  *
-- *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
-- *                        ------------------------------------------
-- *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-- *                        ------------------------------------------
-+ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
-+ *  0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
-  *
-- * And so on ...
-+ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
-+ *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
-+ *
-+ * stream index map for AP Domain :
-+ *
-+ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-+ *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
-+ *
-+ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
-+ *  0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
-+ *
-+ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
-+ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
-+ *
-+ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
-+ *  0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
-  *
-  * The data description gives the offset of the calibration data in
-  * this bytes stream for each sensor.
-- *
-- * Each thermal controller can handle up to 4 sensors max, we don't
-- * care if there are less as the array of calibration is sized to 4
-- * anyway. The unused sensor slot will be zeroed.
-  */
- static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
- 					const struct lvts_ctrl_data *lvts_ctrl_data,
-@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
- 	return 0;
- }
- 
--static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
-+static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- 	{
- 		.cal_offset = { 0x04, 0x07 },
- 		.lvts_sensor = {
-@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
- 	}
- };
- 
-+static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
-+		{
-+		.cal_offset = { 0x25, 0x28 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_AP_VPU0 },
-+			{ .dt_id = MT8195_AP_VPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x0,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	},
-+	{
-+		.cal_offset = { 0x2e, 0x31 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_AP_GPU0 },
-+			{ .dt_id = MT8195_AP_GPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x100,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	},
-+	{
-+		.cal_offset = { 0x37, 0x3a, 0x3d },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_AP_VDEC },
-+			{ .dt_id = MT8195_AP_IMG },
-+			{ .dt_id = MT8195_AP_INFRA },
-+		},
-+		.num_lvts_sensor = 3,
-+		.offset = 0x200,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	},
-+	{
-+		.cal_offset = { 0x43, 0x46 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8195_AP_CAM0 },
-+			{ .dt_id = MT8195_AP_CAM1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x300,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+	}
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
--	.lvts_ctrl	= mt8195_lvts_data_ctrl,
--	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_data_ctrl),
-+	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-+};
-+
-+static const struct lvts_data mt8195_lvts_ap_data = {
-+	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
- };
- 
- static const struct of_device_id lvts_of_match[] = {
- 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
-+	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, lvts_of_match);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
deleted file mode 100644
index a48ea3742b..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 19 Apr 2023 08:11:45 +0200
-Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after
- thermal banks initialization"
-
-Some more testing revealed that this commit introduces a regression on some
-MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due
-to the delay being apparently variable and machine specific.
-
-Another solution would be to delay for a bit more (~70ms) but this is not
-feasible for two reasons: first of all, we're adding an even bigger delay
-in a probe function; second, some machines need less, some may need even
-more, making the msleep at probe solution highly suboptimal.
-
-This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b.
-
-Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization")
-Reported-by: "kernelci.org bot" <bot@kernelci.org>
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++---
- 1 file changed, 8 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature(
- 			mt, conf->bank_data[bank->id].sensors[i], raw);
- 
- 
-+		/*
-+		 * The first read of a sensor often contains very high bogus
-+		 * temperature value. Filter these out so that the system does
-+		 * not immediately shut down.
-+		 */
-+		if (temp > 200000)
-+			temp = 0;
-+
- 		if (temp > max)
- 			max = temp;
- 	}
-@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat
- 
- 	platform_set_drvdata(pdev, mt);
- 
--	/* Delay for thermal banks to be ready */
--	msleep(30);
--
- 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- 					      &mtk_thermal_ops);
- 	if (IS_ERR(tzdev)) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
deleted file mode 100644
index aae87af5d1..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 19 Apr 2023 08:11:46 +0200
-Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints
- to validate read
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The AUXADC thermal v1 allows reading temperature range between -20°C to
-150°C and any value out of this range is invalid.
-
-Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper
-mtk_thermal_temp_is_valid() to check if new readings are in range: if
-not, we tell to the API that the reading is invalid by returning
-THERMAL_TEMP_INVALID.
-
-It was chosen to introduce the helper function because, even though this
-temperature range is realistically ok for all, it comes from a downstream
-kernel driver for version 1, but here we also support v2 and v3 which may
-may have wider constraints.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------
- 1 file changed, 18 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -116,6 +116,10 @@
- /* The calibration coefficient of sensor  */
- #define MT8173_CALIBRATION	165
- 
-+/* Valid temperatures range */
-+#define MT8173_TEMP_MIN		-20000
-+#define MT8173_TEMP_MAX		150000
-+
- /*
-  * Layout of the fuses providing the calibration data
-  * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7
- 	.version = MTK_THERMAL_V3,
- };
- 
-+static bool mtk_thermal_temp_is_valid(int temp)
-+{
-+	return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
-+}
-+
- /**
-  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-  * @mt:	The thermal controller
-@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature(
- 		temp = mt->raw_to_mcelsius(
- 			mt, conf->bank_data[bank->id].sensors[i], raw);
- 
--
- 		/*
--		 * The first read of a sensor often contains very high bogus
--		 * temperature value. Filter these out so that the system does
--		 * not immediately shut down.
-+		 * Depending on the filt/sen intervals and ADC polling time,
-+		 * we may need up to 60 milliseconds after initialization: this
-+		 * will result in the first reading containing an out of range
-+		 * temperature value.
-+		 * Validate the reading to both address the aforementioned issue
-+		 * and to eventually avoid bogus readings during runtime in the
-+		 * event that the AUXADC gets unstable due to high EMI, etc.
- 		 */
--		if (temp > 200000)
--			temp = 0;
-+		if (!mtk_thermal_temp_is_valid(temp))
-+			temp = THERMAL_TEMP_INVALID;
- 
- 		if (temp > max)
- 			max = temp;
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
deleted file mode 100644
index 782684aacc..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001
-From: Kang Chen <void0red@hust.edu.cn>
-Date: Wed, 19 Apr 2023 10:07:48 +0800
-Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid
- resource leak in mtk_thermal_probe
-
-Smatch reports:
-1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released.
-2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released.
-
-The original code forgets to release iomap resource when handling errors,
-fix it by switch to devm_of_iomap.
-
-Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system")
-Signed-off-by: Kang Chen <void0red@hust.edu.cn>
-Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn
----
- drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat
- 		return -ENODEV;
- 	}
- 
--	auxadc_base = of_iomap(auxadc, 0);
-+	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
-+	if (IS_ERR(auxadc_base)) {
-+		of_node_put(auxadc);
-+		return PTR_ERR(auxadc_base);
-+	}
-+
- 	auxadc_phys_base = of_get_phys_base(auxadc);
- 
- 	of_node_put(auxadc);
-@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat
- 		return -ENODEV;
- 	}
- 
--	apmixed_base = of_iomap(apmixedsys, 0);
-+	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
-+	if (IS_ERR(apmixed_base)) {
-+		of_node_put(apmixedsys);
-+		return PTR_ERR(apmixed_base);
-+	}
-+
- 	apmixed_phys_base = of_get_phys_base(apmixedsys);
- 
- 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
deleted file mode 100644
index d7896dbd60..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001
-From: Kang Chen <void0red@hust.edu.cn>
-Date: Wed, 19 Apr 2023 10:07:49 +0800
-Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to
- devm_clk_get_enabled in mtk_thermal_probe
-
-Use devm_clk_get_enabled to do automatic resource management.
-Meanwhile, remove error handling labels in the probe function and
-the whole remove function.
-
-Signed-off-by: Kang Chen <void0red@hust.edu.cn>
-Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn
----
- drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------
- 1 file changed, 9 insertions(+), 35 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat
- 
- 	mt->conf = of_device_get_match_data(&pdev->dev);
- 
--	mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
--	if (IS_ERR(mt->clk_peri_therm))
--		return PTR_ERR(mt->clk_peri_therm);
--
--	mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
--	if (IS_ERR(mt->clk_auxadc))
--		return PTR_ERR(mt->clk_auxadc);
--
- 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- 	if (IS_ERR(mt->thermal_base))
- 		return PTR_ERR(mt->thermal_base);
-@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat
- 	if (ret)
- 		return ret;
- 
--	ret = clk_prepare_enable(mt->clk_auxadc);
--	if (ret) {
-+	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
-+	if (IS_ERR(mt->clk_auxadc)) {
-+		ret = PTR_ERR(mt->clk_auxadc);
- 		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
- 		return ret;
- 	}
- 
--	ret = clk_prepare_enable(mt->clk_peri_therm);
--	if (ret) {
-+	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
-+	if (IS_ERR(mt->clk_peri_therm)) {
-+		ret = PTR_ERR(mt->clk_peri_therm);
- 		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
--		goto err_disable_clk_auxadc;
-+		return ret;
- 	}
- 
- 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
-@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat
- 
- 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- 					      &mtk_thermal_ops);
--	if (IS_ERR(tzdev)) {
--		ret = PTR_ERR(tzdev);
--		goto err_disable_clk_peri_therm;
--	}
-+	if (IS_ERR(tzdev))
-+		return PTR_ERR(tzdev);
- 
- 	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
- 	if (ret)
- 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
- 
- 	return 0;
--
--err_disable_clk_peri_therm:
--	clk_disable_unprepare(mt->clk_peri_therm);
--err_disable_clk_auxadc:
--	clk_disable_unprepare(mt->clk_auxadc);
--
--	return ret;
--}
--
--static int mtk_thermal_remove(struct platform_device *pdev)
--{
--	struct mtk_thermal *mt = platform_get_drvdata(pdev);
--
--	clk_disable_unprepare(mt->clk_peri_therm);
--	clk_disable_unprepare(mt->clk_auxadc);
--
--	return 0;
- }
- 
- static struct platform_driver mtk_thermal_driver = {
- 	.probe = mtk_thermal_probe,
--	.remove = mtk_thermal_remove,
- 	.driver = {
- 		.name = "mtk-thermal",
- 		.of_match_table = mtk_thermal_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
deleted file mode 100644
index fd18a5365c..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001
-From: Rob Herring <robh@kernel.org>
-Date: Sun, 19 Mar 2023 11:32:31 -0500
-Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource()
-
-Replace of_get_address() and of_translate_address() calls with single
-call to of_address_to_resource().
-
-Signed-off-by: Rob Herring <robh@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org
----
- drivers/thermal/mediatek/auxadc_thermal.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct
- 
- static u64 of_get_phys_base(struct device_node *np)
- {
--	u64 size64;
--	const __be32 *regaddr_p;
-+	struct resource res;
- 
--	regaddr_p = of_get_address(np, 0, &size64, NULL);
--	if (!regaddr_p)
-+	if (of_address_to_resource(np, 0, &res))
- 		return OF_BAD_ADDR;
- 
--	return of_translate_address(np, regaddr_p);
-+	return res.start;
- }
- 
- static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
deleted file mode 100644
index c3ff17d517..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
-Date: Thu, 25 May 2023 14:18:11 +0200
-Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to
- avoid resource leak in mtk_thermal_probe"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26.
-
-That change was causing a regression in the generic-adc-thermal-probed
-bootrr test as reported in the kernelci-results list [1].
-A proper rework will take longer, so revert it for now.
-
-[1] https://groups.io/g/kernelci-results/message/42660
-
-Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe")
-Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
-Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------
- 1 file changed, 2 insertions(+), 12 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat
- 		return -ENODEV;
- 	}
- 
--	auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
--	if (IS_ERR(auxadc_base)) {
--		of_node_put(auxadc);
--		return PTR_ERR(auxadc_base);
--	}
--
-+	auxadc_base = of_iomap(auxadc, 0);
- 	auxadc_phys_base = of_get_phys_base(auxadc);
- 
- 	of_node_put(auxadc);
-@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat
- 		return -ENODEV;
- 	}
- 
--	apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
--	if (IS_ERR(apmixed_base)) {
--		of_node_put(apmixedsys);
--		return PTR_ERR(apmixed_base);
--	}
--
-+	apmixed_base = of_iomap(apmixedsys, 0);
- 	apmixed_phys_base = of_get_phys_base(apmixedsys);
- 
- 	of_node_put(apmixedsys);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
deleted file mode 100644
index c4456529c1..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wenst@chromium.org>
-Date: Tue, 13 Jun 2023 17:13:16 +0800
-Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal
- zones as hwmon sensors
-
-Register thermal zones as hwmon sensors to let userspace read
-temperatures using standard hwmon interface.
-
-Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org
----
- drivers/thermal/mediatek/lvts_thermal.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -19,6 +19,8 @@
- #include <linux/thermal.h>
- #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
- 
-+#include "../thermal_hwmon.h"
-+
- #define LVTS_MONCTL0(__base)	(__base + 0x0000)
- #define LVTS_MONCTL1(__base)	(__base + 0x0004)
- #define LVTS_MONCTL2(__base)	(__base + 0x0008)
-@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device
- 			return PTR_ERR(tz);
- 		}
- 
-+		if (devm_thermal_add_hwmon_sysfs(dev, tz))
-+			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
-+
- 		/*
- 		 * The thermal zone pointer will be needed in the
- 		 * interrupt handler, we store it in the sensor
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
deleted file mode 100644
index 22e7a954ed..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001
-From: Yangtao Li <frank.li@vivo.com>
-Date: Tue, 20 Jun 2023 17:07:31 +0800
-Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant
- msg in lvts_ctrl_start()
-
-The upper-layer devm_thermal_add_hwmon_sysfs() function can directly
-print error information.
-
-Signed-off-by: Yangtao Li <frank.li@vivo.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device
- 			return PTR_ERR(tz);
- 		}
- 
--		if (devm_thermal_add_hwmon_sysfs(dev, tz))
--			dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
-+		devm_thermal_add_hwmon_sysfs(dev, tz);
- 
- 		/*
- 		 * The thermal zone pointer will be needed in the
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
deleted file mode 100644
index bc67727423..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:32 -0400
-Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on
- all controllers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There is a single IRQ handler for each LVTS thermal domain, and it is
-supposed to check each of its underlying controllers for the origin of
-the interrupt and clear its status. However due to a typo, only the
-first controller was ever being handled, which resulted in the interrupt
-never being cleared when it happened on the other controllers. Add the
-missing index so interrupts are handled for all controllers.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int
- 
- 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
- 
--		aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
-+		aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
- 		if (aux != IRQ_HANDLED)
- 			continue;
- 
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
deleted file mode 100644
index 51d119c05b..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:33 -0400
-Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in
- immediate mode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Each controller can be configured to operate on immediate or filtered
-mode. On filtered mode, the sensors are enabled by setting the
-corresponding bits in MONCTL0, while on immediate mode, by setting
-MSRCTL1.
-
-Previously, the code would set MSRCTL1 for all four sensors when
-configured to immediate mode, but given that the controller might not
-have all four sensors connected, this would cause interrupts to trigger
-for non-existent sensors. Fix this by handling the MSRCTL1 register
-analogously to the MONCTL0: only enable the sensors that were declared.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++-----------
- 1 file changed, 33 insertions(+), 24 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de
- 	writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
- 
- 	/*
--	 * LVTS_MSRCTL1 : Measurement control
--	 *
--	 * Bits:
--	 *
--	 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
--	 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
--	 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
--	 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
--	 *
--	 * That configuration will ignore the filtering and the delays
--	 * introduced below in MONCTL1 and MONCTL2
--	 */
--	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
--		value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
--		writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
--	}
--
--	/*
- 	 * LVTS_MONCTL1 : Period unit and group interval configuration
- 	 *
- 	 * The clock source of LVTS thermal controller is 26MHz.
-@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device
- 	struct thermal_zone_device *tz;
- 	u32 sensor_map = 0;
- 	int i;
-+	/*
-+	 * Bitmaps to enable each sensor on immediate and filtered modes, as
-+	 * described in MSRCTL1 and MONCTL0 registers below, respectively.
-+	 */
-+	u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
-+	u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
-+
-+	u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
-+			     sensor_imm_bitmap : sensor_filt_bitmap;
- 
- 	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
- 
-@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device
- 		 * map, so we can enable the temperature monitoring in
- 		 * the hardware thermal controller.
- 		 */
--		sensor_map |= BIT(i);
-+		sensor_map |= sensor_bitmap[i];
- 	}
- 
- 	/*
--	 * Bits:
--	 *      9: Single point access flow
--	 *    0-3: Enable sensing point 0-3
--	 *
- 	 * The initialization of the thermal zones give us
- 	 * which sensor point to enable. If any thermal zone
- 	 * was not described in the device tree, it won't be
- 	 * enabled here in the sensor map.
- 	 */
--	writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+	if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
-+		/*
-+		 * LVTS_MSRCTL1 : Measurement control
-+		 *
-+		 * Bits:
-+		 *
-+		 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
-+		 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
-+		 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
-+		 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
-+		 *
-+		 * That configuration will ignore the filtering and the delays
-+		 * introduced in MONCTL1 and MONCTL2
-+		 */
-+		writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
-+	} else {
-+		/*
-+		 * Bits:
-+		 *      9: Single point access flow
-+		 *    0-3: Enable sensing point 0-3
-+		 */
-+		writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+	}
- 
- 	return 0;
- }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
deleted file mode 100644
index bfbadee350..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:34 -0400
-Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset
- threshold for IRQ
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are two kinds of temperature monitoring interrupts available:
-* High Offset, Low Offset
-* Hot, Hot to normal, Cold
-
-The code currently uses the hot/h2n/cold interrupts, however in a way
-that doesn't work: the cold threshold is left uninitialized, which
-prevents the other thresholds from ever triggering, and the h2n
-interrupt is used as the lower threshold, which prevents the hot
-interrupt from triggering again after the thresholds are updated by the
-thermal framework, since a hot interrupt can only trigger again after
-the hot to normal interrupt has been triggered.
-
-But better yet than addressing those issues, is to use the high/low
-offset interrupts instead. This way only two thresholds need to be
-managed, which have a simpler state machine, making them a better match
-to the thermal framework's high and low thresholds.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal
- 	u32 raw_high = lvts_temp_to_raw(high);
- 
- 	/*
--	 * Hot to normal temperature threshold
-+	 * Low offset temperature threshold
- 	 *
--	 * LVTS_H2NTHRE
-+	 * LVTS_OFFSETL
- 	 *
- 	 * Bits:
- 	 *
-@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal
- 	if (low != -INT_MAX) {
- 		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
- 			 thermal_zone_device_type(tz), low);
--		writel(raw_low, LVTS_H2NTHRE(base));
-+		writel(raw_low, LVTS_OFFSETL(base));
- 	}
- 
- 	/*
--	 * Hot temperature threshold
-+	 * High offset temperature threshold
- 	 *
--	 * LVTS_HTHRE
-+	 * LVTS_OFFSETH
- 	 *
- 	 * Bits:
- 	 *
-@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal
- 	 */
- 	pr_debug("%s: Setting high limit temperature interrupt: %d\n",
- 		 thermal_zone_device_type(tz), high);
--	writel(raw_high, LVTS_HTHRE(base));
-+	writel(raw_high, LVTS_OFFSETH(base));
- 
- 	return 0;
- }
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
deleted file mode 100644
index 1c35d0ad19..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:35 -0400
-Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable
- undesired interrupts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Out of the many interrupts supported by the hardware, the only ones of
-interest to the driver currently are:
-* The temperature went over the high offset threshold, for any of the
-  sensors
-* The temperature went below the low offset threshold, for any of the
-  sensors
-* The temperature went over the stage3 threshold
-
-These are the only thresholds configured by the driver through the
-OFFSETH, OFFSETL, and PROTTC registers, respectively.
-
-The current interrupt mask in LVTS_MONINT_CONF, enables many more
-interrupts, including data ready on sensors for both filtered and
-immediate mode. These are not only not handled by the driver, but they
-are also triggered too often, causing unneeded overhead. Disable these
-unnecessary interrupts.
-
-The meaning of each bit can be seen in the comment describing
-LVTS_MONINTST in the IRQ handler.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -65,7 +65,7 @@
- #define LVTS_HW_FILTER				0x2
- #define LVTS_TSSEL_CONF				0x13121110
- #define LVTS_CALSCALE_CONF			0x300
--#define LVTS_MONINT_CONF			0x9FBF7BDE
-+#define LVTS_MONINT_CONF			0x8300318C
- 
- #define LVTS_INT_SENSOR0			0x0009001F
- #define LVTS_INT_SENSOR1			0x001203E0
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
deleted file mode 100644
index 60942fdb89..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:36 -0400
-Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave
- threshold zeroed
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The thermal framework might leave the low threshold unset if there
-aren't any lower trip points. This leaves the register zeroed, which
-translates to a very high temperature for the low threshold. The
-interrupt for this threshold is then immediately triggered, and the
-state machine gets stuck, preventing any other temperature monitoring
-interrupts to ever trigger.
-
-(The same happens by not setting the Cold or Hot to Normal thresholds
-when using those)
-
-Set the unused threshold to a valid low value. This value was chosen so
-that for any valid golden temperature read from the efuse, when the
-value is converted to raw and back again to milliCelsius, the result
-doesn't underflow.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -83,6 +83,8 @@
- 
- #define LVTS_HW_SHUTDOWN_MT8195		105000
- 
-+#define LVTS_MINIMUM_THRESHOLD		20000
-+
- static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
- static int coeff_b = LVTS_COEFF_B;
- 
-@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal
- {
- 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- 	void __iomem *base = lvts_sensor->base;
--	u32 raw_low = lvts_temp_to_raw(low);
-+	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
- 	u32 raw_high = lvts_temp_to_raw(high);
- 
- 	/*
-@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal
- 	 *
- 	 * 14-0 : Raw temperature for threshold
- 	 */
--	if (low != -INT_MAX) {
--		pr_debug("%s: Setting low limit temperature interrupt: %d\n",
--			 thermal_zone_device_type(tz), low);
--		writel(raw_low, LVTS_OFFSETL(base));
--	}
-+	pr_debug("%s: Setting low limit temperature interrupt: %d\n",
-+		 thermal_zone_device_type(tz), low);
-+	writel(raw_low, LVTS_OFFSETL(base));
- 
- 	/*
- 	 * High offset temperature threshold
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
deleted file mode 100644
index e99aa0cdfd..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch
+++ /dev/null
@@ -1,156 +0,0 @@
-From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:37 -0400
-Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold
- between sensors
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Each LVTS thermal controller can have up to four sensors, each capable
-of triggering its own interrupt when its measured temperature crosses
-the configured threshold. The threshold for each sensor is handled
-separately by the thermal framework, since each one is registered with
-its own thermal zone and trips. However, the temperature thresholds are
-configured on the controller, and therefore are shared between all
-sensors on that controller.
-
-When the temperature measured by the sensors is different enough to
-cause the thermal framework to configure different thresholds for each
-one, interrupts start triggering on sensors outside the last threshold
-configured.
-
-To address the issue, track the thresholds required by each sensor and
-only actually set the highest one in the hardware, and disable
-interrupts for all sensors outside the current configured range.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++
- 1 file changed, 69 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -67,6 +67,11 @@
- #define LVTS_CALSCALE_CONF			0x300
- #define LVTS_MONINT_CONF			0x8300318C
- 
-+#define LVTS_MONINT_OFFSET_SENSOR0		0xC
-+#define LVTS_MONINT_OFFSET_SENSOR1		0x180
-+#define LVTS_MONINT_OFFSET_SENSOR2		0x3000
-+#define LVTS_MONINT_OFFSET_SENSOR3		0x3000000
-+
- #define LVTS_INT_SENSOR0			0x0009001F
- #define LVTS_INT_SENSOR1			0x001203E0
- #define LVTS_INT_SENSOR2			0x00247C00
-@@ -112,6 +117,8 @@ struct lvts_sensor {
- 	void __iomem *base;
- 	int id;
- 	int dt_id;
-+	int low_thresh;
-+	int high_thresh;
- };
- 
- struct lvts_ctrl {
-@@ -121,6 +128,8 @@ struct lvts_ctrl {
- 	int num_lvts_sensor;
- 	int mode;
- 	void __iomem *base;
-+	int low_thresh;
-+	int high_thresh;
- };
- 
- struct lvts_domain {
-@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_
- 	return 0;
- }
- 
-+static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
-+{
-+	u32 masks[] = {
-+		LVTS_MONINT_OFFSET_SENSOR0,
-+		LVTS_MONINT_OFFSET_SENSOR1,
-+		LVTS_MONINT_OFFSET_SENSOR2,
-+		LVTS_MONINT_OFFSET_SENSOR3,
-+	};
-+	u32 value = 0;
-+	int i;
-+
-+	value = readl(LVTS_MONINT(lvts_ctrl->base));
-+
-+	for (i = 0; i < ARRAY_SIZE(masks); i++) {
-+		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
-+		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
-+			value |= masks[i];
-+		else
-+			value &= ~masks[i];
-+	}
-+
-+	writel(value, LVTS_MONINT(lvts_ctrl->base));
-+}
-+
-+static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
-+{
-+	int i;
-+
-+	if (high > lvts_ctrl->high_thresh)
-+		return true;
-+
-+	for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
-+		if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
-+		    && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
-+			return false;
-+
-+	return true;
-+}
-+
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
-+	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
- 	void __iomem *base = lvts_sensor->base;
- 	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
- 	u32 raw_high = lvts_temp_to_raw(high);
-+	bool should_update_thresh;
-+
-+	lvts_sensor->low_thresh = low;
-+	lvts_sensor->high_thresh = high;
-+
-+	should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
-+	if (should_update_thresh) {
-+		lvts_ctrl->high_thresh = high;
-+		lvts_ctrl->low_thresh = low;
-+	}
-+	lvts_update_irq_mask(lvts_ctrl);
-+
-+	if (!should_update_thresh)
-+		return 0;
- 
- 	/*
- 	 * Low offset temperature threshold
-@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic
- 		 */
- 		lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
- 			imm_regs[i] : msr_regs[i];
-+
-+		lvts_sensor[i].low_thresh = INT_MIN;
-+		lvts_sensor[i].high_thresh = INT_MIN;
- 	};
- 
- 	lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
-@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device
- 		 */
- 		lvts_ctrl[i].hw_tshut_raw_temp =
- 			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+
-+		lvts_ctrl[i].low_thresh = INT_MIN;
-+		lvts_ctrl[i].high_thresh = INT_MIN;
- 	}
- 
- 	/*
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
deleted file mode 100644
index 9ce3eeb74b..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001
-From: Minjie Du <duminjie@vivo.com>
-Date: Thu, 13 Jul 2023 12:24:12 +0800
-Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in
- lvts_debugfs_init()
-
-The documentation says "If an error occurs, ERR_PTR(-ERROR) will be
-returned" but the current code checks against a NULL pointer returned.
-
-Fix this by checking if IS_ERR().
-
-Signed-off-by: Minjie Du <duminjie@vivo.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi
- 	int i;
- 
- 	lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
--	if (!lvts_td->dom_dentry)
-+	if (IS_ERR(lvts_td->dom_dentry))
- 		return 0;
- 
- 	for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
deleted file mode 100644
index 4841054917..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001
-From: Chen Jiahao <chenjiahao16@huawei.com>
-Date: Wed, 2 Aug 2023 17:45:27 +0800
-Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant
- dev_err_probe()
-
-Referring to platform_get_irq()'s definition, the return value has
-already been checked if ret < 0, and printed via dev_err_probe().
-Calling dev_err_probe() one more time outside platform_get_irq()
-is obviously redundant.
-
-Removing dev_err_probe() outside platform_get_irq() to clean up
-above problem.
-
-Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de
- 
- 	irq = platform_get_irq(pdev, 0);
- 	if (irq < 0)
--		return dev_err_probe(dev, irq, "No irq resource\n");
-+		return irq;
- 
- 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
- 	if (ret)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
deleted file mode 100644
index c88bf984fa..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch
+++ /dev/null
@@ -1,95 +0,0 @@
-From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 13 Jul 2023 11:42:37 -0400
-Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings
- valid in filtered mode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Currently, when a controller is configured to use filtered mode, thermal
-readings are valid only about 30% of the time.
-
-Upon testing, it was noticed that lowering any of the interval settings
-resulted in an improved rate of valid data. The same was observed when
-decreasing the number of samples for each sensor (which also results in
-quicker measurements).
-
-Retrying the read with a timeout longer than the time it takes to
-resample (about 344us with these settings and 4 sensors) also improves
-the rate.
-
-Lower all timing settings to the minimum, configure the filtering to
-single sample, and poll the measurement register for at least one period
-to improve the data validity on filtered mode.  With these changes in
-place, out of 100000 reads, a single one failed, ie 99.999% of the data
-was valid.
-
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++-------
- 1 file changed, 12 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -58,11 +58,11 @@
- #define LVTS_PROTTC(__base)		(__base + 0x00CC)
- #define LVTS_CLKEN(__base)		(__base + 0x00E4)
- 
--#define LVTS_PERIOD_UNIT			((118 * 1000) / (256 * 38))
--#define LVTS_GROUP_INTERVAL			1
--#define LVTS_FILTER_INTERVAL		1
--#define LVTS_SENSOR_INTERVAL		1
--#define LVTS_HW_FILTER				0x2
-+#define LVTS_PERIOD_UNIT			0
-+#define LVTS_GROUP_INTERVAL			0
-+#define LVTS_FILTER_INTERVAL		0
-+#define LVTS_SENSOR_INTERVAL		0
-+#define LVTS_HW_FILTER				0x0
- #define LVTS_TSSEL_CONF				0x13121110
- #define LVTS_CALSCALE_CONF			0x300
- #define LVTS_MONINT_CONF			0x8300318C
-@@ -86,6 +86,9 @@
- #define LVTS_MSR_IMMEDIATE_MODE		0
- #define LVTS_MSR_FILTERED_MODE		1
- 
-+#define LVTS_MSR_READ_TIMEOUT_US	400
-+#define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
-+
- #define LVTS_HW_SHUTDOWN_MT8195		105000
- 
- #define LVTS_MINIMUM_THRESHOLD		20000
-@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_
- 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- 	void __iomem *msr = lvts_sensor->msr;
- 	u32 value;
-+	int rc;
- 
- 	/*
- 	 * Measurement registers:
-@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_
- 	 * 16	: Valid temperature
- 	 * 15-0	: Raw temperature
- 	 */
--	value = readl(msr);
-+	rc = readl_poll_timeout(msr, value, value & BIT(16),
-+				LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
- 
- 	/*
- 	 * As the thermal zone temperature will read before the
-@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_
- 	 * functionning temperature and directly jump to a system
- 	 * shutdown.
- 	 */
--	if (!(value & BIT(16)))
-+	if (rc)
- 		return -EAGAIN;
- 
- 	*temp = lvts_raw_to_temp(value & 0xFFFF);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch b/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
deleted file mode 100644
index 994461cdb1..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001
-From: Andrei Coardos <aboutphysycs@gmail.com>
-Date: Fri, 11 Aug 2023 22:28:47 +0300
-Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call
- to platform_set_drvdata()
-
-This function call was found to be unnecessary as there is no equivalent
-platform_get_drvdata() call to access the private data of the driver. Also,
-the private data is defined in this driver, so there is no risk of it being
-accessed outside of this driver file.
-
-Signed-off-by: Andrei Coardos <aboutphysycs@gmail.com>
-Reviewed-by: Alexandru Ardelean <alex@shruggie.ro>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat
- 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
- 					      auxadc_phys_base, ctrl_id);
- 
--	platform_set_drvdata(pdev, mt);
--
- 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- 					      &mtk_thermal_ops);
- 	if (IS_ERR(tzdev))
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
deleted file mode 100644
index b3bfa37458..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
-Date: Wed, 27 Sep 2023 21:37:23 +0200
-Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
- returning void
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The .remove() callback for a platform driver returns an int which makes
-many driver authors wrongly assume it's possible to do error handling by
-returning an error code. However the value returned is ignored (apart
-from emitting a warning) and this typically results in resource leaks.
-
-To improve here there is a quest to make the remove callback return
-void. In the first step of this quest all drivers are converted to
-.remove_new(), which already returns void. Eventually after all drivers
-are converted, .remove_new() will be renamed to .remove().
-
-Trivially convert this driver from always returning zero in the remove
-callback to the void returning variant.
-
-Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
-Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de
- 	return 0;
- }
- 
--static int lvts_remove(struct platform_device *pdev)
-+static void lvts_remove(struct platform_device *pdev)
- {
- 	struct lvts_domain *lvts_td;
- 	int i;
-@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d
- 		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
- 
- 	lvts_debugfs_exit(lvts_td);
--
--	return 0;
- }
- 
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
-@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
- 
- static struct platform_driver lvts_driver = {
- 	.probe = lvts_probe,
--	.remove = lvts_remove,
-+	.remove_new = lvts_remove,
- 	.driver = {
- 		.name = "mtk-lvts-thermal",
- 		.of_match_table = lvts_of_match,
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
deleted file mode 100644
index 16a32f564b..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:19 +0200
-Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
- configurable
-
-The upcoming mt7988 has different temperature coefficients so we
-cannot use constants in the functions lvts_golden_temp_init,
-lvts_golden_temp_init and lvts_raw_to_temp anymore.
-
-Add a field in the lvts_ctrl pointing to the lvts_data which now
-contains the soc-specific temperature coefficents.
-
-To make the code better readable, rename static int coeff_b to
-golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
----
- drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
- 1 file changed, 34 insertions(+), 17 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -80,8 +80,8 @@
- #define LVTS_SENSOR_MAX				4
- #define LVTS_GOLDEN_TEMP_MAX		62
- #define LVTS_GOLDEN_TEMP_DEFAULT	50
--#define LVTS_COEFF_A				-250460
--#define LVTS_COEFF_B				250460
-+#define LVTS_COEFF_A_MT8195			-250460
-+#define LVTS_COEFF_B_MT8195			250460
- 
- #define LVTS_MSR_IMMEDIATE_MODE		0
- #define LVTS_MSR_FILTERED_MODE		1
-@@ -94,7 +94,7 @@
- #define LVTS_MINIMUM_THRESHOLD		20000
- 
- static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
--static int coeff_b = LVTS_COEFF_B;
-+static int golden_temp_offset;
- 
- struct lvts_sensor_data {
- 	int dt_id;
-@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
- struct lvts_data {
- 	const struct lvts_ctrl_data *lvts_ctrl;
- 	int num_lvts_ctrl;
-+	int temp_factor;
-+	int temp_offset;
- };
- 
- struct lvts_sensor {
-@@ -126,6 +128,7 @@ struct lvts_sensor {
- 
- struct lvts_ctrl {
- 	struct lvts_sensor sensors[LVTS_SENSOR_MAX];
-+	const struct lvts_data *lvts_data;
- 	u32 calibration[LVTS_SENSOR_MAX];
- 	u32 hw_tshut_raw_temp;
- 	int num_lvts_sensor;
-@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
- 
- #endif
- 
--static int lvts_raw_to_temp(u32 raw_temp)
-+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
- {
- 	int temperature;
- 
--	temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
--	temperature += coeff_b;
-+	temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
-+	temperature += golden_temp_offset;
- 
- 	return temperature;
- }
- 
--static u32 lvts_temp_to_raw(int temperature)
-+static u32 lvts_temp_to_raw(int temperature, int temp_factor)
- {
--	u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
-+	u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
- 
--	raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
-+	raw_temp = div_s64(raw_temp, -temp_factor);
- 
- 	return raw_temp;
- }
-@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
- static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
- {
- 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
-+	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
-+						   sensors[lvts_sensor->id]);
-+	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
- 	void __iomem *msr = lvts_sensor->msr;
- 	u32 value;
- 	int rc;
-@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
- 	if (rc)
- 		return -EAGAIN;
- 
--	*temp = lvts_raw_to_temp(value & 0xFFFF);
-+	*temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
- 
- 	return 0;
- }
-@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- 	struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
--	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
-+	struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
-+						   sensors[lvts_sensor->id]);
-+	const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
- 	void __iomem *base = lvts_sensor->base;
--	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
--	u32 raw_high = lvts_temp_to_raw(high);
-+	u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
-+				       lvts_data->temp_factor);
-+	u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
- 	bool should_update_thresh;
- 
- 	lvts_sensor->low_thresh = low;
-@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct
- 	return 0;
- }
- 
--static int lvts_golden_temp_init(struct device *dev, u32 *value)
-+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
- {
- 	u32 gt;
- 
-@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct
- 	if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
- 		golden_temp = gt;
- 
--	coeff_b = golden_temp * 500 + LVTS_COEFF_B;
-+	golden_temp_offset = golden_temp * 500 + temp_offset;
- 
- 	return 0;
- }
-@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device
- 	 * The golden temp information is contained in the first chunk
- 	 * of efuse data.
- 	 */
--	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
-+	ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
- 	if (ret)
- 		return ret;
- 
-@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device
- 	for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
- 
- 		lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
-+		lvts_ctrl[i].lvts_data = lvts_data;
- 
- 		ret = lvts_sensor_init(dev, &lvts_ctrl[i],
- 				       &lvts_data->lvts_ctrl[i]);
-@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device
- 		 * after initializing the calibration.
- 		 */
- 		lvts_ctrl[i].hw_tshut_raw_temp =
--			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+			lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
-+					 lvts_data->temp_factor);
- 
- 		lvts_ctrl[i].low_thresh = INT_MIN;
- 		lvts_ctrl[i].high_thresh = INT_MIN;
-@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de
- 	if (irq < 0)
- 		return irq;
- 
-+	golden_temp_offset = lvts_data->temp_offset;
-+
- 	ret = lvts_domain_init(dev, lvts_td, lvts_data);
- 	if (ret)
- 		return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
-@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819
- static const struct lvts_data mt8195_lvts_mcu_data = {
- 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
- 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-+	.temp_factor	= LVTS_COEFF_A_MT8195,
-+	.temp_offset	= LVTS_COEFF_B_MT8195,
- };
- 
- static const struct lvts_data mt8195_lvts_ap_data = {
- 	.lvts_ctrl	= mt8195_lvts_ap_data_ctrl,
- 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
-+	.temp_factor	= LVTS_COEFF_A_MT8195,
-+	.temp_offset	= LVTS_COEFF_B_MT8195,
- };
- 
- static const struct of_device_id lvts_of_match[] = {
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
deleted file mode 100644
index 1c2146f43f..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:18 +0200
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for
- mt7988
-
-Add sensor constants for MT7988.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Conor Dooley <conor.dooley@microchip.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
----
- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -7,6 +7,15 @@
- #ifndef __MEDIATEK_LVTS_DT_H
- #define __MEDIATEK_LVTS_DT_H
- 
-+#define MT7988_CPU_0		0
-+#define MT7988_CPU_1		1
-+#define MT7988_ETH2P5G_0	2
-+#define MT7988_ETH2P5G_1	3
-+#define MT7988_TOPS_0		4
-+#define MT7988_TOPS_1		5
-+#define MT7988_ETHWARP_0	6
-+#define MT7988_ETHWARP_1	7
-+
- #define MT8195_MCU_BIG_CPU0     0
- #define MT8195_MCU_BIG_CPU1     1
- #define MT8195_MCU_BIG_CPU2     2
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
deleted file mode 100644
index 97c803a820..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch
+++ /dev/null
@@ -1,91 +0,0 @@
-From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:20 +0200
-Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
- support
-
-Add Support for Mediatek Filogic 880/MT7988 LVTS.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
----
- drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -82,6 +82,8 @@
- #define LVTS_GOLDEN_TEMP_DEFAULT	50
- #define LVTS_COEFF_A_MT8195			-250460
- #define LVTS_COEFF_B_MT8195			250460
-+#define LVTS_COEFF_A_MT7988			-204650
-+#define LVTS_COEFF_B_MT7988			204650
- 
- #define LVTS_MSR_IMMEDIATE_MODE		0
- #define LVTS_MSR_FILTERED_MODE		1
-@@ -89,6 +91,7 @@
- #define LVTS_MSR_READ_TIMEOUT_US	400
- #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
- 
-+#define LVTS_HW_SHUTDOWN_MT7988		105000
- #define LVTS_HW_SHUTDOWN_MT8195		105000
- 
- #define LVTS_MINIMUM_THRESHOLD		20000
-@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
- 	lvts_debugfs_exit(lvts_td);
- }
- 
-+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
-+	{
-+		.cal_offset = { 0x00, 0x04, 0x08, 0x0c },
-+		.lvts_sensor = {
-+			{ .dt_id = MT7988_CPU_0 },
-+			{ .dt_id = MT7988_CPU_1 },
-+			{ .dt_id = MT7988_ETH2P5G_0 },
-+			{ .dt_id = MT7988_ETH2P5G_1 }
-+		},
-+		.num_lvts_sensor = 4,
-+		.offset = 0x0,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
-+	},
-+	{
-+		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT7988_TOPS_0},
-+			{ .dt_id = MT7988_TOPS_1},
-+			{ .dt_id = MT7988_ETHWARP_0},
-+			{ .dt_id = MT7988_ETHWARP_1}
-+		},
-+		.num_lvts_sensor = 4,
-+		.offset = 0x100,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
-+	}
-+};
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- 	{
- 		.cal_offset = { 0x04, 0x07 },
-@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
- 	}
- };
- 
-+static const struct lvts_data mt7988_lvts_ap_data = {
-+	.lvts_ctrl	= mt7988_lvts_ap_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
-+	.temp_factor	= LVTS_COEFF_A_MT7988,
-+	.temp_offset	= LVTS_COEFF_B_MT7988,
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
- 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
- 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
- };
- 
- static const struct of_device_id lvts_of_match[] = {
-+	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
- 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
- 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
deleted file mode 100644
index 5b212a2a37..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
-From: Minjie Du <duminjie@vivo.com>
-Date: Thu, 21 Sep 2023 17:10:50 +0800
-Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
- in lvts_debugfs_init()
-
-debugfs_create_dir() function returns an error value embedded in
-the pointer (PTR_ERR). Evaluate the return value using IS_ERR
-rather than checking for NULL.
-
-Signed-off-by: Minjie Du <duminjie@vivo.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
- 
- 		sprintf(name, "controller%d", i);
- 		dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
--		if (!dentry)
-+		if (IS_ERR(dentry))
- 			continue;
- 
- 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
deleted file mode 100644
index 88f383c4ae..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001
-From: Markus Schneider-Pargmann <msp@baylibre.com>
-Date: Mon, 18 Sep 2023 12:07:06 +0200
-Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2
-
-Fix the probe function to call mtk_thermal_release_periodic_ts for
-everything != MTK_THERMAL_V1. This was accidentally changed from V1
-to V2 in the original patch.
-
-Reported-by: Frank Wunderlich <frank-w@public-files.de>
-Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/
-Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/
-Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
-Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat
- 
- 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
- 
--	if (mt->conf->version != MTK_THERMAL_V2)
-+	if (mt->conf->version != MTK_THERMAL_V1)
- 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 
- 	if (mt->conf->version == MTK_THERMAL_V1)
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
deleted file mode 100644
index 7b4b124b56..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:42 +0200
-Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
- resume
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add suspend and resume support to LVTS driver.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-[bero@baylibre.com: suspend/resume in noirq phase]
-Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798
- 	}
- };
- 
-+static int lvts_suspend(struct device *dev)
-+{
-+	struct lvts_domain *lvts_td;
-+	int i;
-+
-+	lvts_td = dev_get_drvdata(dev);
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
-+
-+	clk_disable_unprepare(lvts_td->clk);
-+
-+	return 0;
-+}
-+
-+static int lvts_resume(struct device *dev)
-+{
-+	struct lvts_domain *lvts_td;
-+	int i, ret;
-+
-+	lvts_td = dev_get_drvdata(dev);
-+
-+	ret = clk_prepare_enable(lvts_td->clk);
-+	if (ret)
-+		return ret;
-+
-+	for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+		lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
-+
-+	return 0;
-+}
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- 	{
- 		.cal_offset = { 0x04, 0x07 },
-@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of
- };
- MODULE_DEVICE_TABLE(of, lvts_of_match);
- 
-+static const struct dev_pm_ops lvts_pm_ops = {
-+	NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
-+};
-+
- static struct platform_driver lvts_driver = {
- 	.probe = lvts_probe,
- 	.remove_new = lvts_remove,
- 	.driver = {
- 		.name = "mtk-lvts-thermal",
- 		.of_match_table = lvts_of_match,
-+		.pm = &lvts_pm_ops,
- 	},
- };
- module_platform_driver(lvts_driver);
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
deleted file mode 100644
index c278168610..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:41 +0200
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller
- definition for mt8192
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add LVTS thermal controller definition for MT8192.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
----
- .../thermal/mediatek,lvts-thermal.h           | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -35,4 +35,23 @@
- #define MT8195_AP_CAM0  15
- #define MT8195_AP_CAM1  16
- 
-+#define MT8192_MCU_BIG_CPU0     0
-+#define MT8192_MCU_BIG_CPU1     1
-+#define MT8192_MCU_BIG_CPU2     2
-+#define MT8192_MCU_BIG_CPU3     3
-+#define MT8192_MCU_LITTLE_CPU0  4
-+#define MT8192_MCU_LITTLE_CPU1  5
-+#define MT8192_MCU_LITTLE_CPU2  6
-+#define MT8192_MCU_LITTLE_CPU3  7
-+
-+#define MT8192_AP_VPU0  8
-+#define MT8192_AP_VPU1  9
-+#define MT8192_AP_GPU0  10
-+#define MT8192_AP_GPU1  11
-+#define MT8192_AP_INFRA 12
-+#define MT8192_AP_CAM   13
-+#define MT8192_AP_MD0   14
-+#define MT8192_AP_MD1   15
-+#define MT8192_AP_MD2   16
-+
- #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
deleted file mode 100644
index 6d68a6cd57..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:43 +0200
-Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
- support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add LVTS Driver support for MT8192.
-
-Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-[bero@baylibre.com: cosmetic changes, rebase]
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
- 1 file changed, 95 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -92,6 +92,7 @@
- #define LVTS_MSR_READ_WAIT_US		(LVTS_MSR_READ_TIMEOUT_US / 2)
- 
- #define LVTS_HW_SHUTDOWN_MT7988		105000
-+#define LVTS_HW_SHUTDOWN_MT8192		105000
- #define LVTS_HW_SHUTDOWN_MT8195		105000
- 
- #define LVTS_MINIMUM_THRESHOLD		20000
-@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de
- 	return 0;
- }
- 
-+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
-+	{
-+		.cal_offset = { 0x04, 0x08 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_MCU_BIG_CPU0 },
-+			{ .dt_id = MT8192_MCU_BIG_CPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x0,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+		.mode = LVTS_MSR_FILTERED_MODE,
-+	},
-+	{
-+		.cal_offset = { 0x0c, 0x10 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_MCU_BIG_CPU2 },
-+			{ .dt_id = MT8192_MCU_BIG_CPU3 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x100,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+		.mode = LVTS_MSR_FILTERED_MODE,
-+	},
-+	{
-+		.cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_MCU_LITTLE_CPU0 },
-+			{ .dt_id = MT8192_MCU_LITTLE_CPU1 },
-+			{ .dt_id = MT8192_MCU_LITTLE_CPU2 },
-+			{ .dt_id = MT8192_MCU_LITTLE_CPU3 }
-+		},
-+		.num_lvts_sensor = 4,
-+		.offset = 0x200,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+		.mode = LVTS_MSR_FILTERED_MODE,
-+	}
-+};
-+
-+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
-+		{
-+		.cal_offset = { 0x24, 0x28 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_AP_VPU0 },
-+			{ .dt_id = MT8192_AP_VPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x0,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+	},
-+	{
-+		.cal_offset = { 0x2c, 0x30 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_AP_GPU0 },
-+			{ .dt_id = MT8192_AP_GPU1 }
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x100,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+	},
-+	{
-+		.cal_offset = { 0x34, 0x38 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_AP_INFRA },
-+			{ .dt_id = MT8192_AP_CAM },
-+		},
-+		.num_lvts_sensor = 2,
-+		.offset = 0x200,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+	},
-+	{
-+		.cal_offset = { 0x3c, 0x40, 0x44 },
-+		.lvts_sensor = {
-+			{ .dt_id = MT8192_AP_MD0 },
-+			{ .dt_id = MT8192_AP_MD1 },
-+			{ .dt_id = MT8192_AP_MD2 }
-+		},
-+		.num_lvts_sensor = 3,
-+		.offset = 0x300,
-+		.hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+	}
-+};
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- 	{
- 		.cal_offset = { 0x04, 0x07 },
-@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt
- 	.temp_offset	= LVTS_COEFF_B_MT7988,
- };
- 
-+static const struct lvts_data mt8192_lvts_mcu_data = {
-+	.lvts_ctrl	= mt8192_lvts_mcu_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
-+};
-+
-+static const struct lvts_data mt8192_lvts_ap_data = {
-+	.lvts_ctrl	= mt8192_lvts_ap_data_ctrl,
-+	.num_lvts_ctrl	= ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
- 	.lvts_ctrl	= mt8195_lvts_mcu_data_ctrl,
- 	.num_lvts_ctrl	= ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt
- 
- static const struct of_device_id lvts_of_match[] = {
- 	{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
-+	{ .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
-+	{ .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
- 	{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
- 	{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- 	{},
diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
deleted file mode 100644
index c20c0b5f2e..0000000000
--- a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:45 +0200
-Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
- calibration data documentation
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Update LVTS calibration data documentation for mt8192 and mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
- 1 file changed, 29 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
-  * The efuse blob values follows the sensor enumeration per thermal
-  * controller. The decoding of the stream is as follow:
-  *
-- * stream index map for MCU Domain :
-+ * MT8192 :
-+ * Stream index map for MCU Domain mt8192 :
-+ *
-+ * <-----mcu-tc#0-----> <-----sensor#0----->        <-----sensor#1----->
-+ *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
-+ *
-+ * <-----sensor#2----->        <-----sensor#3----->
-+ *  0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
-+ *
-+ * <-----sensor#4----->        <-----sensor#5----->        <-----sensor#6----->        <-----sensor#7----->
-+ *  0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
-+ *
-+ * Stream index map for AP Domain mt8192 :
-+ *
-+ * <-----sensor#0----->        <-----sensor#1----->
-+ *  0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
-+ *
-+ * <-----sensor#2----->        <-----sensor#3----->
-+ *  0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
-+ *
-+ * <-----sensor#4----->        <-----sensor#5----->
-+ *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
-+ *
-+ * <-----sensor#6----->        <-----sensor#7----->        <-----sensor#8----->
-+ *  0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
-+ *
-+ * MT8195 :
-+ * Stream index map for MCU Domain mt8195 :
-  *
-  * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-  *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
-@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
-  * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
-  *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
-  *
-- * stream index map for AP Domain :
-+ * Stream index map for AP Domain mt8195 :
-  *
-  * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-  *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
diff --git a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
deleted file mode 100644
index fc173646e0..0000000000
--- a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From patchwork Thu Sep  7 11:20:18 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
-X-Patchwork-Id: 13376356
-From: Frank Wunderlich <linux@fw-web.de>
-To: linux-mediatek@lists.infradead.org
-Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on
- MT7896
-Date: Thu,  7 Sep 2023 13:20:18 +0200
-Message-Id: <20230907112018.52811-1-linux@fw-web.de>
-X-Mailer: git-send-email 2.34.1
-MIME-Version: 1.0
-X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e
-X-BeenThere: linux-mediatek@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-mediatek.lists.infradead.org>
-Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
- "Rafael J. Wysocki" <rafael@kernel.org>, linux-pm@vger.kernel.org,
- Amit Kucheria <amitk@kernel.org>, Daniel Golle <daniel@makrotopia.org>,
- stable@vger.kernel.org, linux-kernel@vger.kernel.org,
- Matthias Brugger <matthias.bgg@gmail.com>, Zhang Rui <rui.zhang@intel.com>,
- linux-arm-kernel@lists.infradead.org,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
-
-From: Frank Wunderlich <frank-w@public-files.de>
-
-Reading thermal sensor on mt7986 devices returns invalid temperature:
-
-bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp
- -274000
-
-Fix this by adding missing members in mtk_thermal_data struct which were
-used in mtk_thermal_turn_on_buffer after commit 33140e668b10.
-
-Cc: stable@vger.kernel.org
-Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7
- 	.adcpnp = mt7986_adcpnp,
- 	.sensor_mux_values = mt7986_mux_values,
- 	.version = MTK_THERMAL_V3,
-+	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
-+	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
-+	.apmixed_buffer_ctl_set = BIT(0),
- };
- 
- static bool mtk_thermal_temp_is_valid(int temp)
diff --git a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch
deleted file mode 100644
index 4c398c59f9..0000000000
--- a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 9 Oct 2022 12:16:31 +0200
-Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support
-
-Add i2c support for MT7986 SoC.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7986_compat = {
-+	.quirks = &mt7622_i2c_quirks,
-+	.regs = mt_i2c_regs_v1,
-+	.pmic_i2c = 0,
-+	.dcm = 1,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 0,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 0,
-+	.max_dma_support = 32,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- 	.regs = mt_i2c_regs_v1,
- 	.pmic_i2c = 0,
-@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- 	{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
diff --git a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
deleted file mode 100644
index 18c66cdac5..0000000000
--- a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Thu, 19 Jan 2023 17:19:58 +0800
-Subject: [PATCH 13/16] i2c: mt65xx: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform
- {
- 	int ret = 0;
- 	struct mtk_i2c *i2c;
--	struct resource *res;
- 	int i, irq, speed_clk;
- 
- 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- 	if (!i2c)
- 		return -ENOMEM;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- 	if (IS_ERR(i2c->base))
- 		return PTR_ERR(i2c->base);
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
--	i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
-+	i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- 	if (IS_ERR(i2c->pdmabase))
- 		return PTR_ERR(i2c->pdmabase);
- 
diff --git a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
deleted file mode 100644
index d000d53522..0000000000
--- a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sat, 11 Mar 2023 12:16:54 +0100
-Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The driver can match only via the DT table so the table should be always
-used and the of_match_ptr does not have any sense (this also allows ACPI
-matching via PRP0001, even though it might not be relevant here).
-
-  drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=]
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Guenter Roeck <groeck@chromium.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr
- 	.driver = {
- 		.name = I2C_DRV_NAME,
- 		.pm = &mtk_i2c_pm,
--		.of_match_table = of_match_ptr(mtk_i2c_of_match),
-+		.of_match_table = mtk_i2c_of_match,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
deleted file mode 100644
index e0973741e2..0000000000
--- a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 10 Apr 2023 17:19:38 +0100
-Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC
-
-Add support for the I2C units found in the MediaTek MT7981 and MT7988
-SoCs. Just like other recent MediaTek I2C units that also uses v3
-register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being
-0x94 instead of 0x4).
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m
- 	.max_dma_support = 33,
- };
- 
-+static const struct mtk_i2c_compatible mt7981_compat = {
-+	.regs = mt_i2c_regs_v3,
-+	.pmic_i2c = 0,
-+	.dcm = 0,
-+	.auto_restart = 1,
-+	.aux_len_reg = 1,
-+	.timing_adjust = 1,
-+	.dma_sync = 1,
-+	.ltiming_adjust = 1,
-+	.max_dma_support = 33
-+};
-+
- static const struct mtk_i2c_compatible mt7986_compat = {
- 	.quirks = &mt7622_i2c_quirks,
- 	.regs = mt_i2c_regs_v1,
-@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c
- 	{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- 	{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- 	{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+	{ .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
- 	{ .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- 	{ .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- 	{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
diff --git a/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch
deleted file mode 100644
index 69cc155d8d..0000000000
--- a/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:56:51 +0100
-Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
-
-Using the I2C host controller on the MT7981 SoC requires 4 clocks to
-be enabled. One of them, the pmic clk, is only enabled in case
-'mediatek,have-pmic' is also set which has other consequences which
-are not desired in this case.
-
-Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
-is not present and the bus is not used to connect to a pmic, but may
-still require to enable the pmic clock.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform
- 	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
- 		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
- 
-+	i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
-+	if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		dev_err(&pdev->dev, "cannot get pmic clock\n");
-+		return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+	}
-+
- 	if (i2c->have_pmic) {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
--		if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+		if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
- 			dev_err(&pdev->dev, "cannot get pmic clock\n");
--			return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+			return -ENODEV;
- 		}
- 		speed_clk = I2C_MT65XX_CLK_PMIC;
- 	} else {
--		i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
- 		speed_clk = I2C_MT65XX_CLK_MAIN;
- 	}
- 
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch b/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
deleted file mode 100644
index 9607eec821..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch
+++ /dev/null
@@ -1,269 +0,0 @@
-From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:33 +0800
-Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
-
-Add header files for register definition and structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-afe-common.h |  49 +++++
- sound/soc/mediatek/mt7986/mt7986-reg.h        | 196 ++++++++++++++++++
- 2 files changed, 245 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
-@@ -0,0 +1,49 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-afe-common.h  --  MediaTek 7986 audio driver definitions
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT_7986_AFE_COMMON_H_
-+#define _MT_7986_AFE_COMMON_H_
-+
-+#include <sound/soc.h>
-+#include <linux/clk.h>
-+#include <linux/list.h>
-+#include <linux/regmap.h>
-+#include "../common/mtk-base-afe.h"
-+
-+enum {
-+	MT7986_MEMIF_DL1,
-+	MT7986_MEMIF_VUL12,
-+	MT7986_MEMIF_NUM,
-+	MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
-+	MT7986_DAI_NUM,
-+};
-+
-+enum {
-+	MT7986_IRQ_0,
-+	MT7986_IRQ_1,
-+	MT7986_IRQ_2,
-+	MT7986_IRQ_NUM,
-+};
-+
-+struct mt7986_afe_private {
-+	struct clk_bulk_data *clks;
-+	int num_clks;
-+
-+	int pm_runtime_bypass_reg_ctl;
-+
-+	/* dai */
-+	void *dai_priv[MT7986_DAI_NUM];
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev,
-+				       unsigned int rate);
-+
-+/* dai register */
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
-+#endif
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
-@@ -0,0 +1,196 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-reg.h  --  MediaTek 7986 audio driver reg definition
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT7986_REG_H_
-+#define _MT7986_REG_H_
-+
-+#define AUDIO_TOP_CON2                  0x0008
-+#define AUDIO_TOP_CON4                  0x0010
-+#define AUDIO_ENGEN_CON0                0x0014
-+#define AFE_IRQ_MCU_EN                  0x0100
-+#define AFE_IRQ_MCU_STATUS              0x0120
-+#define AFE_IRQ_MCU_CLR                 0x0128
-+#define AFE_IRQ0_MCU_CFG0               0x0140
-+#define AFE_IRQ0_MCU_CFG1               0x0144
-+#define AFE_IRQ1_MCU_CFG0               0x0148
-+#define AFE_IRQ1_MCU_CFG1               0x014c
-+#define AFE_IRQ2_MCU_CFG0               0x0150
-+#define AFE_IRQ2_MCU_CFG1               0x0154
-+#define ETDM_IN5_CON0                   0x13f0
-+#define ETDM_IN5_CON1                   0x13f4
-+#define ETDM_IN5_CON2                   0x13f8
-+#define ETDM_IN5_CON3                   0x13fc
-+#define ETDM_IN5_CON4                   0x1400
-+#define ETDM_OUT5_CON0                  0x1570
-+#define ETDM_OUT5_CON4                  0x1580
-+#define ETDM_OUT5_CON5                  0x1584
-+#define ETDM_4_7_COWORK_CON0            0x15e0
-+#define ETDM_4_7_COWORK_CON1            0x15e4
-+#define AFE_CONN018_1                   0x1b44
-+#define AFE_CONN018_4                   0x1b50
-+#define AFE_CONN019_1                   0x1b64
-+#define AFE_CONN019_4                   0x1b70
-+#define AFE_CONN124_1                   0x2884
-+#define AFE_CONN124_4                   0x2890
-+#define AFE_CONN125_1                   0x28a4
-+#define AFE_CONN125_4                   0x28b0
-+#define AFE_CONN_RS_0                   0x3920
-+#define AFE_CONN_RS_3                   0x392c
-+#define AFE_CONN_16BIT_0                0x3960
-+#define AFE_CONN_16BIT_3                0x396c
-+#define AFE_CONN_24BIT_0                0x3980
-+#define AFE_CONN_24BIT_3                0x398c
-+#define AFE_MEMIF_CON0                  0x3d98
-+#define AFE_MEMIF_RD_MON                0x3da0
-+#define AFE_MEMIF_WR_MON                0x3da4
-+#define AFE_DL0_BASE_MSB                0x3e40
-+#define AFE_DL0_BASE                    0x3e44
-+#define AFE_DL0_CUR_MSB                 0x3e48
-+#define AFE_DL0_CUR                     0x3e4c
-+#define AFE_DL0_END_MSB                 0x3e50
-+#define AFE_DL0_END                     0x3e54
-+#define AFE_DL0_RCH_MON                 0x3e58
-+#define AFE_DL0_LCH_MON                 0x3e5c
-+#define AFE_DL0_CON0                    0x3e60
-+#define AFE_VUL0_BASE_MSB               0x4220
-+#define AFE_VUL0_BASE                   0x4224
-+#define AFE_VUL0_CUR_MSB                0x4228
-+#define AFE_VUL0_CUR                    0x422c
-+#define AFE_VUL0_END_MSB                0x4230
-+#define AFE_VUL0_END                    0x4234
-+#define AFE_VUL0_CON0                   0x4238
-+
-+#define AFE_MAX_REGISTER AFE_VUL0_CON0
-+#define AFE_IRQ_STATUS_BITS             0x7
-+#define AFE_IRQ_CNT_SHIFT               0
-+#define AFE_IRQ_CNT_MASK	        0xffffff
-+
-+/* AUDIO_TOP_CON2 */
-+#define CLK_OUT5_PDN                    BIT(14)
-+#define CLK_OUT5_PDN_MASK               BIT(14)
-+#define CLK_IN5_PDN                     BIT(7)
-+#define CLK_IN5_PDN_MASK                BIT(7)
-+
-+/* AUDIO_TOP_CON4 */
-+#define PDN_APLL_TUNER2                 BIT(12)
-+#define PDN_APLL_TUNER2_MASK            BIT(12)
-+
-+/* AUDIO_ENGEN_CON0 */
-+#define AUD_APLL2_EN                    BIT(3)
-+#define AUD_APLL2_EN_MASK               BIT(3)
-+#define AUD_26M_EN                      BIT(0)
-+#define AUD_26M_EN_MASK                 BIT(0)
-+
-+/* AFE_DL0_CON0 */
-+#define DL0_ON_SFT                      28
-+#define DL0_ON_MASK                     0x1
-+#define DL0_ON_MASK_SFT                 BIT(28)
-+#define DL0_MINLEN_SFT                  20
-+#define DL0_MINLEN_MASK                 0xf
-+#define DL0_MINLEN_MASK_SFT             (0xf << 20)
-+#define DL0_MODE_SFT                    8
-+#define DL0_MODE_MASK                   0x1f
-+#define DL0_MODE_MASK_SFT               (0x1f << 8)
-+#define DL0_PBUF_SIZE_SFT               5
-+#define DL0_PBUF_SIZE_MASK              0x3
-+#define DL0_PBUF_SIZE_MASK_SFT          (0x3 << 5)
-+#define DL0_MONO_SFT                    4
-+#define DL0_MONO_MASK                   0x1
-+#define DL0_MONO_MASK_SFT               BIT(4)
-+#define DL0_HALIGN_SFT                  2
-+#define DL0_HALIGN_MASK                 0x1
-+#define DL0_HALIGN_MASK_SFT             BIT(2)
-+#define DL0_HD_MODE_SFT                 0
-+#define DL0_HD_MODE_MASK                0x3
-+#define DL0_HD_MODE_MASK_SFT            (0x3 << 0)
-+
-+/* AFE_VUL0_CON0 */
-+#define VUL0_ON_SFT                     28
-+#define VUL0_ON_MASK                    0x1
-+#define VUL0_ON_MASK_SFT                BIT(28)
-+#define VUL0_MODE_SFT                   8
-+#define VUL0_MODE_MASK                  0x1f
-+#define VUL0_MODE_MASK_SFT              (0x1f << 8)
-+#define VUL0_MONO_SFT                   4
-+#define VUL0_MONO_MASK                  0x1
-+#define VUL0_MONO_MASK_SFT              BIT(4)
-+#define VUL0_HALIGN_SFT                 2
-+#define VUL0_HALIGN_MASK                0x1
-+#define VUL0_HALIGN_MASK_SFT            BIT(2)
-+#define VUL0_HD_MODE_SFT                0
-+#define VUL0_HD_MODE_MASK               0x3
-+#define VUL0_HD_MODE_MASK_SFT           (0x3 << 0)
-+
-+/* AFE_IRQ_MCU_CON */
-+#define IRQ_MCU_MODE_SFT                4
-+#define IRQ_MCU_MODE_MASK               0x1f
-+#define IRQ_MCU_MODE_MASK_SFT           (0x1f << 4)
-+#define IRQ_MCU_ON_SFT                  0
-+#define IRQ_MCU_ON_MASK                 0x1
-+#define IRQ_MCU_ON_MASK_SFT             BIT(0)
-+#define IRQ0_MCU_CLR_SFT                0
-+#define IRQ0_MCU_CLR_MASK               0x1
-+#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
-+#define IRQ1_MCU_CLR_SFT                1
-+#define IRQ1_MCU_CLR_MASK               0x1
-+#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
-+#define IRQ2_MCU_CLR_SFT                2
-+#define IRQ2_MCU_CLR_MASK               0x1
-+#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
-+
-+/* ETDM_IN5_CON2 */
-+#define IN_CLK_SRC(x)                   ((x) << 10)
-+#define IN_CLK_SRC_SFT                  10
-+#define IN_CLK_SRC_MASK                 GENMASK(12, 10)
-+
-+/* ETDM_IN5_CON3 */
-+#define IN_SEL_FS(x)                    ((x) << 26)
-+#define IN_SEL_FS_SFT                   26
-+#define IN_SEL_FS_MASK                  GENMASK(30, 26)
-+
-+/* ETDM_IN5_CON4 */
-+#define IN_RELATCH(x)                   ((x) << 20)
-+#define IN_RELATCH_SFT                  20
-+#define IN_RELATCH_MASK                 GENMASK(24, 20)
-+#define IN_CLK_INV                      BIT(18)
-+#define IN_CLK_INV_MASK                 BIT(18)
-+
-+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
-+#define RELATCH_SRC_MASK                GENMASK(30, 28)
-+#define ETDM_CH_NUM_MASK                GENMASK(27, 23)
-+#define ETDM_WRD_LEN_MASK               GENMASK(20, 16)
-+#define ETDM_BIT_LEN_MASK               GENMASK(15, 11)
-+#define ETDM_FMT_MASK                   GENMASK(8, 6)
-+#define ETDM_SYNC                       BIT(1)
-+#define ETDM_SYNC_MASK                  BIT(1)
-+#define ETDM_EN                         BIT(0)
-+#define ETDM_EN_MASK                    BIT(0)
-+
-+/* ETDM_OUT5_CON4 */
-+#define OUT_RELATCH(x)                  ((x) << 24)
-+#define OUT_RELATCH_SFT                 24
-+#define OUT_RELATCH_MASK                GENMASK(28, 24)
-+#define OUT_CLK_SRC(x)                  ((x) << 6)
-+#define OUT_CLK_SRC_SFT                 6
-+#define OUT_CLK_SRC_MASK                GENMASK(8, 6)
-+#define OUT_SEL_FS(x)                   (x)
-+#define OUT_SEL_FS_SFT                  0
-+#define OUT_SEL_FS_MASK                 GENMASK(4, 0)
-+
-+/* ETDM_OUT5_CON5 */
-+#define ETDM_CLK_DIV                    BIT(12)
-+#define ETDM_CLK_DIV_MASK               BIT(12)
-+#define OUT_CLK_INV                     BIT(9)
-+#define OUT_CLK_INV_MASK                BIT(9)
-+
-+/* ETDM_4_7_COWORK_CON0 */
-+#define OUT_SEL(x)                      ((x) << 12)
-+#define OUT_SEL_SFT                     12
-+#define OUT_SEL_MASK                    GENMASK(15, 12)
-+#endif
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch b/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
deleted file mode 100644
index f22add580f..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch
+++ /dev/null
@@ -1,430 +0,0 @@
-From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:34 +0800
-Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver
-
-Add mt7986 etdm dai driver support.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++
- 1 file changed, 411 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -0,0 +1,411 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC Audio DAI eTDM Control
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/bitops.h>
-+#include <linux/regmap.h>
-+#include <sound/pcm_params.h>
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+
-+#define HOPPING_CLK  0
-+#define APLL_CLK     1
-+#define MTK_DAI_ETDM_FORMAT_I2S   0
-+#define MTK_DAI_ETDM_FORMAT_DSPA  4
-+#define MTK_DAI_ETDM_FORMAT_DSPB  5
-+
-+enum {
-+	MTK_ETDM_RATE_8K = 0,
-+	MTK_ETDM_RATE_12K = 1,
-+	MTK_ETDM_RATE_16K = 2,
-+	MTK_ETDM_RATE_24K = 3,
-+	MTK_ETDM_RATE_32K = 4,
-+	MTK_ETDM_RATE_48K = 5,
-+	MTK_ETDM_RATE_96K = 7,
-+	MTK_ETDM_RATE_192K = 9,
-+	MTK_ETDM_RATE_11K = 16,
-+	MTK_ETDM_RATE_22K = 17,
-+	MTK_ETDM_RATE_44K = 18,
-+	MTK_ETDM_RATE_88K = 19,
-+	MTK_ETDM_RATE_176K = 20,
-+};
-+
-+struct mtk_dai_etdm_priv {
-+	bool bck_inv;
-+	bool lrck_inv;
-+	bool slave_mode;
-+	unsigned int format;
-+};
-+
-+static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_ETDM_RATE_8K;
-+	case 11025:
-+		return MTK_ETDM_RATE_11K;
-+	case 12000:
-+		return MTK_ETDM_RATE_12K;
-+	case 16000:
-+		return MTK_ETDM_RATE_16K;
-+	case 22050:
-+		return MTK_ETDM_RATE_22K;
-+	case 24000:
-+		return MTK_ETDM_RATE_24K;
-+	case 32000:
-+		return MTK_ETDM_RATE_32K;
-+	case 44100:
-+		return MTK_ETDM_RATE_44K;
-+	case 48000:
-+		return MTK_ETDM_RATE_48K;
-+	case 88200:
-+		return MTK_ETDM_RATE_88K;
-+	case 96000:
-+		return MTK_ETDM_RATE_96K;
-+	case 176400:
-+		return MTK_ETDM_RATE_176K;
-+	case 192000:
-+		return MTK_ETDM_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_ETDM_RATE_48K);
-+		return MTK_ETDM_RATE_48K;
-+	}
-+}
-+
-+static int get_etdm_wlen(unsigned int bitwidth)
-+{
-+	return bitwidth <= 16 ? 16 : 32;
-+}
-+
-+/* dai component */
-+/* interconnection */
-+
-+static const struct snd_kcontrol_new o124_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o125_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
-+
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
-+	SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
-+	{"I150", NULL, "ETDM Capture"},
-+	{"I151", NULL, "ETDM Capture"},
-+	{"ETDM Playback", NULL, "O124"},
-+	{"ETDM Playback", NULL, "O125"},
-+	{"O124", "I032_Switch", "I032"},
-+	{"O125", "I033_Switch", "I033"},
-+};
-+
-+/* dai ops */
-+static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
-+
-+	return 0;
-+}
-+
-+static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
-+			   CLK_OUT5_PDN);
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
-+			   CLK_IN5_PDN);
-+
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+}
-+
-+static unsigned int get_etdm_ch_fixup(unsigned int channels)
-+{
-+	if (channels > 16)
-+		return 24;
-+	else if (channels > 8)
-+		return 16;
-+	else if (channels > 4)
-+		return 8;
-+	else if (channels > 2)
-+		return 4;
-+	else
-+		return 2;
-+}
-+
-+static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
-+			       struct snd_pcm_hw_params *params,
-+			       struct snd_soc_dai *dai,
-+			       int stream)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
-+	unsigned int rate = params_rate(params);
-+	unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
-+	unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
-+	unsigned int channels = params_channels(params);
-+	unsigned int bit_width = params_width(params);
-+	unsigned int wlen = get_etdm_wlen(bit_width);
-+	unsigned int val = 0;
-+	unsigned int mask = 0;
-+
-+	dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
-+		 __func__, stream, rate, bit_width);
-+
-+	/* CON0 */
-+	mask |= ETDM_BIT_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
-+	mask |= ETDM_WRD_LEN_MASK;
-+	val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
-+	mask |= ETDM_FMT_MASK;
-+	val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
-+	mask |= ETDM_CH_NUM_MASK;
-+	val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
-+	mask |= RELATCH_SRC_MASK;
-+	val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
-+
-+	switch (stream) {
-+	case SNDRV_PCM_STREAM_PLAYBACK:
-+		/* set ETDM_OUT5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
-+
-+		/* set ETDM_OUT5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+				   OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_OUT5_CON5 */
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
-+				   ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
-+		break;
-+	case SNDRV_PCM_STREAM_CAPTURE:
-+		/* set ETDM_IN5_CON0 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
-+				   ETDM_SYNC_MASK, ETDM_SYNC);
-+
-+		/* set ETDM_IN5_CON2 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
-+				   IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
-+
-+		/* set ETDM_IN5_CON3 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
-+				   IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
-+
-+		/* set ETDM_IN5_CON4 */
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
-+				   IN_RELATCH_MASK, IN_RELATCH(afe_rate));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
-+				  struct snd_pcm_hw_params *params,
-+				  struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
-+				struct snd_soc_dai *dai)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   ETDM_EN);
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+		regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+				   0);
-+		regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+				   0);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	struct mtk_dai_etdm_priv *etdm_data;
-+	void *priv_data;
-+
-+	switch (dai->id) {
-+	case MT7986_DAI_ETDM:
-+		break;
-+	default:
-+		dev_warn(afe->dev, "%s(), id %d not support\n",
-+			 __func__, dai->id);
-+		return -EINVAL;
-+	}
-+
-+	priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
-+				 GFP_KERNEL);
-+	if (!priv_data)
-+		return -ENOMEM;
-+
-+	afe_priv->dai_priv[dai->id] = priv_data;
-+	etdm_data = afe_priv->dai_priv[dai->id];
-+
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_A:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_B:
-+		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_NB_NF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_NB_IF:
-+		etdm_data->bck_inv = false;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	case SND_SOC_DAIFMT_IB_NF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = false;
-+		break;
-+	case SND_SOC_DAIFMT_IB_IF:
-+		etdm_data->bck_inv = true;
-+		etdm_data->lrck_inv = true;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		etdm_data->slave_mode = true;
-+		break;
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+		etdm_data->slave_mode = false;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
-+	.startup = mtk_dai_etdm_startup,
-+	.shutdown = mtk_dai_etdm_shutdown,
-+	.hw_params = mtk_dai_etdm_hw_params,
-+	.trigger = mtk_dai_etdm_trigger,
-+	.set_fmt = mtk_dai_etdm_set_fmt,
-+};
-+
-+/* dai driver */
-+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+			SNDRV_PCM_RATE_88200 |\
-+			SNDRV_PCM_RATE_96000 |\
-+			SNDRV_PCM_RATE_176400 |\
-+			SNDRV_PCM_RATE_192000)
-+
-+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			  SNDRV_PCM_FMTBIT_S24_LE |\
-+			  SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
-+	{
-+		.name = "ETDM",
-+		.id = MT7986_DAI_ETDM,
-+		.capture = {
-+			.stream_name = "ETDM Capture",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.playback = {
-+			.stream_name = "ETDM Playback",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_ETDM_RATES,
-+			.formats = MTK_ETDM_FORMATS,
-+		},
-+		.ops = &mtk_dai_etdm_ops,
-+		.symmetric_rate = 1,
-+		.symmetric_sample_bits = 1,
-+	},
-+};
-+
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mtk_dai_etdm_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
-+
-+	dai->dapm_widgets = mtk_dai_etdm_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
-+	dai->dapm_routes = mtk_dai_etdm_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
-+
-+	return 0;
-+}
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch b/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
deleted file mode 100644
index b899b963d2..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch
+++ /dev/null
@@ -1,685 +0,0 @@
-From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:35 +0800
-Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver
-
-Add mt7986 platform driver.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                 |  10 +
- sound/soc/mediatek/Makefile                |   1 +
- sound/soc/mediatek/mt7986/Makefile         |   8 +
- sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++
- 4 files changed, 641 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/Makefile
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986
-+	tristate "ASoC support for Mediatek MT7986 chip"
-+	depends on ARCH_MEDIATEK
-+	select SND_SOC_MEDIATEK
-+	help
-+	  This adds ASoC platform driver support for MediaTek MT7986 chip
-+	  that can be used with other codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/Makefile
-+++ b/sound/soc/mediatek/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
- obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
- obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
-+obj-$(CONFIG_SND_SOC_MT7986) += mt7986/
- obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
- obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
- obj-$(CONFIG_SND_SOC_MT8186) += mt8186/
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+# platform driver
-+snd-soc-mt7986-afe-objs := \
-+	mt7986-afe-pcm.o \
-+	mt7986-dai-etdm.o
-+
-+obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-@@ -0,0 +1,622 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC AFE platform driver for MT7986
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/pm_runtime.h>
-+
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+#include "../common/mtk-afe-platform-driver.h"
-+#include "../common/mtk-afe-fe-dai.h"
-+
-+enum {
-+	MTK_AFE_RATE_8K = 0,
-+	MTK_AFE_RATE_11K = 1,
-+	MTK_AFE_RATE_12K = 2,
-+	MTK_AFE_RATE_16K = 4,
-+	MTK_AFE_RATE_22K = 5,
-+	MTK_AFE_RATE_24K = 6,
-+	MTK_AFE_RATE_32K = 8,
-+	MTK_AFE_RATE_44K = 9,
-+	MTK_AFE_RATE_48K = 10,
-+	MTK_AFE_RATE_88K = 13,
-+	MTK_AFE_RATE_96K = 14,
-+	MTK_AFE_RATE_176K = 17,
-+	MTK_AFE_RATE_192K = 18,
-+};
-+
-+enum {
-+	CLK_INFRA_AUD_BUS_CK = 0,
-+	CLK_INFRA_AUD_26M_CK,
-+	CLK_INFRA_AUD_L_CK,
-+	CLK_INFRA_AUD_AUD_CK,
-+	CLK_INFRA_AUD_EG2_CK,
-+	CLK_NUM
-+};
-+
-+static const char *aud_clks[CLK_NUM] = {
-+	[CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
-+	[CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
-+	[CLK_INFRA_AUD_L_CK] = "aud_l_ck",
-+	[CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
-+	[CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
-+{
-+	switch (rate) {
-+	case 8000:
-+		return MTK_AFE_RATE_8K;
-+	case 11025:
-+		return MTK_AFE_RATE_11K;
-+	case 12000:
-+		return MTK_AFE_RATE_12K;
-+	case 16000:
-+		return MTK_AFE_RATE_16K;
-+	case 22050:
-+		return MTK_AFE_RATE_22K;
-+	case 24000:
-+		return MTK_AFE_RATE_24K;
-+	case 32000:
-+		return MTK_AFE_RATE_32K;
-+	case 44100:
-+		return MTK_AFE_RATE_44K;
-+	case 48000:
-+		return MTK_AFE_RATE_48K;
-+	case 88200:
-+		return MTK_AFE_RATE_88K;
-+	case 96000:
-+		return MTK_AFE_RATE_96K;
-+	case 176400:
-+		return MTK_AFE_RATE_176K;
-+	case 192000:
-+		return MTK_AFE_RATE_192K;
-+	default:
-+		dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+			 __func__, rate, MTK_AFE_RATE_48K);
-+		return MTK_AFE_RATE_48K;
-+	}
-+}
-+
-+static const struct snd_pcm_hardware mt7986_afe_hardware = {
-+	.info = SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_MMAP_VALID,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+		   SNDRV_PCM_FMTBIT_S24_LE |
-+		   SNDRV_PCM_FMTBIT_S32_LE,
-+	.period_bytes_min = 256,
-+	.period_bytes_max = 4 * 48 * 1024,
-+	.periods_min = 2,
-+	.periods_max = 256,
-+	.buffer_bytes_max = 8 * 48 * 1024,
-+	.fifo_size = 0,
-+};
-+
-+static int mt7986_memif_fs(struct snd_pcm_substream *substream,
-+			   unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+static int mt7986_irq_fs(struct snd_pcm_substream *substream,
-+			 unsigned int rate)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+	return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+		       SNDRV_PCM_RATE_88200 |\
-+		       SNDRV_PCM_RATE_96000 |\
-+		       SNDRV_PCM_RATE_176400 |\
-+		       SNDRV_PCM_RATE_192000)
-+
-+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+			 SNDRV_PCM_FMTBIT_S24_LE |\
-+			 SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
-+	/* FE DAIs: memory intefaces to CPU */
-+	{
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.playback = {
-+			.stream_name = "DL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+	{
-+		.name = "UL1",
-+		.id = MT7986_MEMIF_VUL12,
-+		.capture = {
-+			.stream_name = "UL1",
-+			.channels_min = 1,
-+			.channels_max = 2,
-+			.rates = MTK_PCM_RATES,
-+			.formats = MTK_PCM_FORMATS,
-+		},
-+		.ops = &mtk_afe_fe_ops,
-+	},
-+};
-+
-+static const struct snd_kcontrol_new o018_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o019_mix[] = {
-+	SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
-+	/* DL */
-+	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
-+	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
-+
-+	/* UL */
-+	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
-+			   o018_mix, ARRAY_SIZE(o018_mix)),
-+	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
-+			   o019_mix, ARRAY_SIZE(o019_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
-+	{"I032", NULL, "DL1"},
-+	{"I033", NULL, "DL1"},
-+	{"UL1", NULL, "O018"},
-+	{"UL1", NULL, "O019"},
-+	{"O018", "I150_Switch", "I150"},
-+	{"O019", "I151_Switch", "I151"},
-+};
-+
-+static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
-+	.name = "mt7986-afe-pcm-dai",
-+};
-+
-+static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
-+	[MT7986_MEMIF_DL1] = {
-+		.name = "DL1",
-+		.id = MT7986_MEMIF_DL1,
-+		.reg_ofs_base = AFE_DL0_BASE,
-+		.reg_ofs_cur = AFE_DL0_CUR,
-+		.reg_ofs_end = AFE_DL0_END,
-+		.reg_ofs_base_msb = AFE_DL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_DL0_END_MSB,
-+		.fs_reg = AFE_DL0_CON0,
-+		.fs_shift =  DL0_MODE_SFT,
-+		.fs_maskbit =  DL0_MODE_MASK,
-+		.mono_reg = AFE_DL0_CON0,
-+		.mono_shift = DL0_MONO_SFT,
-+		.enable_reg = AFE_DL0_CON0,
-+		.enable_shift = DL0_ON_SFT,
-+		.hd_reg = AFE_DL0_CON0,
-+		.hd_shift = DL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_DL0_CON0,
-+		.hd_align_mshift = DL0_HALIGN_SFT,
-+		.pbuf_reg = AFE_DL0_CON0,
-+		.pbuf_shift = DL0_PBUF_SIZE_SFT,
-+		.minlen_reg = AFE_DL0_CON0,
-+		.minlen_shift = DL0_MINLEN_SFT,
-+	},
-+	[MT7986_MEMIF_VUL12] = {
-+		.name = "VUL12",
-+		.id = MT7986_MEMIF_VUL12,
-+		.reg_ofs_base = AFE_VUL0_BASE,
-+		.reg_ofs_cur = AFE_VUL0_CUR,
-+		.reg_ofs_end = AFE_VUL0_END,
-+		.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
-+		.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
-+		.reg_ofs_end_msb = AFE_VUL0_END_MSB,
-+		.fs_reg = AFE_VUL0_CON0,
-+		.fs_shift = VUL0_MODE_SFT,
-+		.fs_maskbit = VUL0_MODE_MASK,
-+		.mono_reg = AFE_VUL0_CON0,
-+		.mono_shift = VUL0_MONO_SFT,
-+		.enable_reg = AFE_VUL0_CON0,
-+		.enable_shift = VUL0_ON_SFT,
-+		.hd_reg = AFE_VUL0_CON0,
-+		.hd_shift = VUL0_HD_MODE_SFT,
-+		.hd_align_reg = AFE_VUL0_CON0,
-+		.hd_align_mshift = VUL0_HALIGN_SFT,
-+	},
-+};
-+
-+static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
-+	[MT7986_IRQ_0] = {
-+		.id = MT7986_IRQ_0,
-+		.irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ0_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ0_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_1] = {
-+		.id = MT7986_IRQ_1,
-+		.irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ1_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ1_MCU_CLR_SFT,
-+	},
-+	[MT7986_IRQ_2] = {
-+		.id = MT7986_IRQ_2,
-+		.irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
-+		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+		.irq_fs_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_fs_shift = IRQ_MCU_MODE_SFT,
-+		.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+		.irq_en_reg = AFE_IRQ2_MCU_CFG0,
-+		.irq_en_shift = IRQ_MCU_ON_SFT,
-+		.irq_clr_reg = AFE_IRQ_MCU_CLR,
-+		.irq_clr_shift = IRQ2_MCU_CLR_SFT,
-+	},
-+};
-+
-+static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+	/*
-+	 * Those auto-gen regs are read-only, so put it as volatile because
-+	 * volatile registers cannot be cached, which means that they cannot
-+	 * be set when power is off
-+	 */
-+
-+	switch (reg) {
-+	case AFE_DL0_CUR_MSB:
-+	case AFE_DL0_CUR:
-+	case AFE_DL0_RCH_MON:
-+	case AFE_DL0_LCH_MON:
-+	case AFE_VUL0_CUR_MSB:
-+	case AFE_VUL0_CUR:
-+	case AFE_IRQ_MCU_STATUS:
-+	case AFE_MEMIF_RD_MON:
-+	case AFE_MEMIF_WR_MON:
-+		return true;
-+	default:
-+		return false;
-+	};
-+}
-+
-+static const struct regmap_config mt7986_afe_regmap_config = {
-+	.reg_bits = 32,
-+	.reg_stride = 4,
-+	.val_bits = 32,
-+	.volatile_reg = mt7986_is_volatile_reg,
-+	.max_register = AFE_MAX_REGISTER,
-+	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
-+};
-+
-+static int mt7986_init_clock(struct mtk_base_afe *afe)
-+{
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret, i;
-+
-+	afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
-+				sizeof(*afe_priv->clks), GFP_KERNEL);
-+	if (!afe_priv->clks)
-+		return -ENOMEM;
-+	afe_priv->num_clks = CLK_NUM;
-+
-+	for (i = 0; i < afe_priv->num_clks; i++)
-+		afe_priv->clks[i].id = aud_clks[i];
-+
-+	ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
-+
-+	return 0;
-+}
-+
-+static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
-+{
-+	struct mtk_base_afe *afe = dev;
-+	struct mtk_base_afe_irq *irq;
-+	u32 mcu_en, status, status_mcu;
-+	int i, ret;
-+	irqreturn_t irq_ret = IRQ_HANDLED;
-+
-+	/* get irq that is sent to MCU */
-+	regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
-+
-+	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
-+	/* only care IRQ which is sent to MCU */
-+	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
-+
-+	if (ret || status_mcu == 0) {
-+		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
-+			__func__, ret, status, mcu_en);
-+
-+		irq_ret = IRQ_NONE;
-+		goto err_irq;
-+	}
-+
-+	for (i = 0; i < MT7986_MEMIF_NUM; i++) {
-+		struct mtk_base_afe_memif *memif = &afe->memif[i];
-+
-+		if (!memif->substream)
-+			continue;
-+
-+		if (memif->irq_usage < 0)
-+			continue;
-+
-+		irq = &afe->irqs[memif->irq_usage];
-+
-+		if (status_mcu & (1 << irq->irq_data->irq_en_shift))
-+			snd_pcm_period_elapsed(memif->substream);
-+	}
-+
-+err_irq:
-+	/* clear irq */
-+	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
-+
-+	return irq_ret;
-+}
-+
-+static int mt7986_afe_runtime_suspend(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		goto skip_regmap;
-+
-+	/* disable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
-+
-+	/* make sure all irq status are cleared, twice intended */
-+	regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
-+
-+skip_regmap:
-+	clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_runtime_resume(struct device *dev)
-+{
-+	struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+	struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+	if (ret)
-+		return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+		return 0;
-+
-+	/* enable clk*/
-+	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
-+			   AUD_APLL2_EN);
-+	regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
-+			   AUD_26M_EN);
-+
-+	return 0;
-+}
-+
-+static int mt7986_afe_component_probe(struct snd_soc_component *component)
-+{
-+	return mtk_afe_add_sub_dai_control(component);
-+}
-+
-+static const struct snd_soc_component_driver mt7986_afe_component = {
-+	.name = AFE_PCM_NAME,
-+	.probe = mt7986_afe_component_probe,
-+	.pointer	= mtk_afe_pcm_pointer,
-+	.pcm_construct	= mtk_afe_pcm_new,
-+};
-+
-+static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
-+{
-+	struct mtk_base_afe_dai *dai;
-+
-+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+	if (!dai)
-+		return -ENOMEM;
-+
-+	list_add(&dai->list, &afe->sub_dais);
-+
-+	dai->dai_drivers = mt7986_memif_dai_driver;
-+	dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
-+
-+	dai->dapm_widgets = mt7986_memif_widgets;
-+	dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
-+	dai->dapm_routes = mt7986_memif_routes;
-+	dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
-+
-+	return 0;
-+}
-+
-+typedef int (*dai_register_cb)(struct mtk_base_afe *);
-+static const dai_register_cb dai_register_cbs[] = {
-+	mt7986_dai_etdm_register,
-+	mt7986_dai_memif_register,
-+};
-+
-+static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
-+{
-+	struct mtk_base_afe *afe;
-+	struct mt7986_afe_private *afe_priv;
-+	struct device *dev;
-+	int i, irq_id, ret;
-+
-+	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
-+	if (!afe)
-+		return -ENOMEM;
-+	platform_set_drvdata(pdev, afe);
-+
-+	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
-+					  GFP_KERNEL);
-+	if (!afe->platform_priv)
-+		return -ENOMEM;
-+
-+	afe_priv = afe->platform_priv;
-+	afe->dev = &pdev->dev;
-+	dev = afe->dev;
-+
-+	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(afe->base_addr))
-+		return PTR_ERR(afe->base_addr);
-+
-+	/* initial audio related clock */
-+	ret = mt7986_init_clock(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
-+
-+	ret = devm_pm_runtime_enable(dev);
-+	if (ret)
-+		return ret;
-+
-+	/* enable clock for regcache get default value from hw */
-+	afe_priv->pm_runtime_bypass_reg_ctl = true;
-+	pm_runtime_get_sync(&pdev->dev);
-+
-+	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
-+		      &mt7986_afe_regmap_config);
-+
-+	pm_runtime_put_sync(&pdev->dev);
-+	if (IS_ERR(afe->regmap))
-+		return PTR_ERR(afe->regmap);
-+
-+	afe_priv->pm_runtime_bypass_reg_ctl = false;
-+
-+	/* init memif */
-+	afe->memif_size = MT7986_MEMIF_NUM;
-+	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
-+				  GFP_KERNEL);
-+	if (!afe->memif)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->memif_size; i++) {
-+		afe->memif[i].data = &memif_data[i];
-+		afe->memif[i].irq_usage = -1;
-+	}
-+
-+	mutex_init(&afe->irq_alloc_lock);
-+
-+	/* irq initialize */
-+	afe->irqs_size = MT7986_IRQ_NUM;
-+	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
-+				 GFP_KERNEL);
-+	if (!afe->irqs)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < afe->irqs_size; i++)
-+		afe->irqs[i].irq_data = &irq_data[i];
-+
-+	/* request irq */
-+	irq_id = platform_get_irq(pdev, 0);
-+	if (irq_id < 0) {
-+		ret = irq_id;
-+		return dev_err_probe(dev, ret, "No irq found\n");
-+	}
-+	ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
-+			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
-+
-+	/* init sub_dais */
-+	INIT_LIST_HEAD(&afe->sub_dais);
-+
-+	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
-+		ret = dai_register_cbs[i](afe);
-+		if (ret)
-+			return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
-+	}
-+
-+	/* init dai_driver and component_driver */
-+	ret = mtk_afe_combine_sub_dai(afe);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
-+
-+	afe->mtk_afe_hardware = &mt7986_afe_hardware;
-+	afe->memif_fs = mt7986_memif_fs;
-+	afe->irq_fs = mt7986_irq_fs;
-+
-+	afe->runtime_resume = mt7986_afe_runtime_resume;
-+	afe->runtime_suspend = mt7986_afe_runtime_suspend;
-+
-+	/* register component */
-+	ret = devm_snd_soc_register_component(&pdev->dev,
-+					      &mt7986_afe_component,
-+					      NULL, 0);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register AFE component\n");
-+
-+	ret = devm_snd_soc_register_component(afe->dev,
-+					      &mt7986_afe_pcm_dai_component,
-+					      afe->dai_drivers,
-+					      afe->num_dai_drivers);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
-+
-+	return 0;
-+}
-+
-+static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
-+{
-+	pm_runtime_disable(&pdev->dev);
-+	if (!pm_runtime_status_suspended(&pdev->dev))
-+		mt7986_afe_runtime_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
-+	{ .compatible = "mediatek,mt7986-afe" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
-+
-+static const struct dev_pm_ops mt7986_afe_pm_ops = {
-+	SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
-+			   mt7986_afe_runtime_resume, NULL)
-+};
-+
-+static struct platform_driver mt7986_afe_pcm_driver = {
-+	.driver = {
-+		   .name = "mt7986-audio",
-+		   .of_match_table = mt7986_afe_pcm_dt_match,
-+		   .pm = &mt7986_afe_pm_ops,
-+	},
-+	.probe = mt7986_afe_pcm_dev_probe,
-+	.remove_new = mt7986_afe_pcm_dev_remove,
-+};
-+module_platform_driver(mt7986_afe_pcm_driver);
-+
-+MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch b/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
deleted file mode 100644
index dd354c04e3..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch
+++ /dev/null
@@ -1,243 +0,0 @@
-From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:36 +0800
-Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960
-
-Add support for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig                |  10 ++
- sound/soc/mediatek/mt7986/Makefile        |   1 +
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++
- 3 files changed, 207 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -64,6 +64,16 @@ config SND_SOC_MT7986
- 	  Select Y if you have such device.
- 	  If unsure select "N".
- 
-+config SND_SOC_MT7986_WM8960
-+	tristate "ASoc Audio driver for MT7986 with WM8960 codec"
-+	depends on SND_SOC_MT7986 && I2C
-+	select SND_SOC_WM8960
-+	help
-+	  This adds support for ASoC machine driver for MediaTek MT7986
-+	  boards with the WM8960 codecs.
-+	  Select Y if you have such device.
-+	  If unsure select "N".
-+
- config SND_SOC_MT8173
- 	tristate "ASoC support for Mediatek MT8173 chip"
- 	depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/mt7986/Makefile
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \
- 	mt7986-dai-etdm.o
- 
- obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
-+obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -0,0 +1,196 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mt7986-wm8960.c  --  MT7986-WM8960 ALSA SoC machine driver
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ *          Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/module.h>
-+#include <sound/soc.h>
-+
-+#include "mt7986-afe-common.h"
-+
-+struct mt7986_wm8960_priv {
-+	struct device_node *platform_node;
-+	struct device_node *codec_node;
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphone", NULL),
-+	SND_SOC_DAPM_MIC("AMIC", NULL),
-+};
-+
-+static const struct snd_kcontrol_new mt7986_wm8960_controls[] = {
-+	SOC_DAPM_PIN_SWITCH("Headphone"),
-+	SOC_DAPM_PIN_SWITCH("AMIC"),
-+};
-+
-+SND_SOC_DAILINK_DEFS(playback,
-+	DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(capture,
-+	DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
-+	DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(codec,
-+	DAILINK_COMP_ARRAY(COMP_CPU("ETDM")),
-+	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
-+	DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = {
-+	/* FE */
-+	{
-+		.name = "wm8960-playback",
-+		.stream_name = "wm8960-playback",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_playback = 1,
-+		SND_SOC_DAILINK_REG(playback),
-+	},
-+	{
-+		.name = "wm8960-capture",
-+		.stream_name = "wm8960-capture",
-+		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+			    SND_SOC_DPCM_TRIGGER_POST},
-+		.dynamic = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(capture),
-+	},
-+	/* BE */
-+	{
-+		.name = "wm8960-codec",
-+		.no_pcm = 1,
-+		.dai_fmt = SND_SOC_DAIFMT_I2S |
-+			SND_SOC_DAIFMT_NB_NF |
-+			SND_SOC_DAIFMT_CBS_CFS |
-+			SND_SOC_DAIFMT_GATED,
-+		.dpcm_playback = 1,
-+		.dpcm_capture = 1,
-+		SND_SOC_DAILINK_REG(codec),
-+	},
-+};
-+
-+static struct snd_soc_card mt7986_wm8960_card = {
-+	.name = "mt7986-wm8960",
-+	.owner = THIS_MODULE,
-+	.dai_link = mt7986_wm8960_dai_links,
-+	.num_links = ARRAY_SIZE(mt7986_wm8960_dai_links),
-+	.controls = mt7986_wm8960_controls,
-+	.num_controls = ARRAY_SIZE(mt7986_wm8960_controls),
-+	.dapm_widgets = mt7986_wm8960_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets),
-+};
-+
-+static int mt7986_wm8960_machine_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &mt7986_wm8960_card;
-+	struct snd_soc_dai_link *dai_link;
-+	struct device_node *platform, *codec;
-+	struct mt7986_wm8960_priv *priv;
-+	int ret, i;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
-+
-+	if (platform) {
-+		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		of_node_put(platform);
-+
-+		if (!priv->platform_node) {
-+			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->platforms->name)
-+			continue;
-+		dai_link->platforms->of_node = priv->platform_node;
-+	}
-+
-+	card->dev = &pdev->dev;
-+
-+	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
-+
-+	if (codec) {
-+		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		of_node_put(codec);
-+
-+		if (!priv->codec_node) {
-+			of_node_put(priv->platform_node);
-+			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		of_node_put(priv->platform_node);
-+		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	for_each_card_prelinks(card, i, dai_link) {
-+		if (dai_link->codecs->name)
-+			continue;
-+		dai_link->codecs->of_node = priv->codec_node;
-+	}
-+
-+	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret);
-+		goto err_of_node_put;
-+	}
-+
-+	ret = devm_snd_soc_register_card(&pdev->dev, card);
-+	if (ret) {
-+		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		goto err_of_node_put;
-+	}
-+
-+err_of_node_put:
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+	return ret;
-+}
-+
-+static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+	of_node_put(priv->codec_node);
-+	of_node_put(priv->platform_node);
-+}
-+
-+static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
-+	{.compatible = "mediatek,mt7986-wm8960-sound"},
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match);
-+
-+static struct platform_driver mt7986_wm8960_machine = {
-+	.driver = {
-+		.name = "mt7986-wm8960",
-+		.of_match_table = mt7986_wm8960_machine_dt_match,
-+	},
-+	.probe = mt7986_wm8960_machine_probe,
-+	.remove_new = mt7986_wm8960_machine_remove,
-+};
-+
-+module_platform_driver(mt7986_wm8960_machine);
-+
-+/* Module information */
-+MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("mt7986 wm8960 soc card");
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch b/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
deleted file mode 100644
index 8cf0b5464a..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:37 +0800
-Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add
- mt7986-wm8960 document
-
-Add document for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../sound/mediatek,mt7986-wm8960.yaml         | 67 +++++++++++++++++++
- 1 file changed, 67 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-@@ -0,0 +1,67 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7986 sound card with WM8960 codec
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+allOf:
-+  - $ref: sound-card-common.yaml#
-+
-+properties:
-+  compatible:
-+    const: mediatek,mt7986-wm8960-sound
-+
-+  platform:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of MT7986 platform.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+  codec:
-+    type: object
-+    additionalProperties: false
-+    properties:
-+      sound-dai:
-+        description: The phandle of wm8960 codec.
-+        maxItems: 1
-+    required:
-+      - sound-dai
-+
-+unevaluatedProperties: false
-+
-+required:
-+  - compatible
-+  - audio-routing
-+  - platform
-+  - codec
-+
-+examples:
-+  - |
-+    sound {
-+        compatible = "mediatek,mt7986-wm8960-sound";
-+        model = "mt7986-wm8960";
-+        audio-routing =
-+            "Headphone", "HP_L",
-+            "Headphone", "HP_R",
-+            "LINPUT1", "AMIC",
-+            "RINPUT1", "AMIC";
-+
-+        platform {
-+            sound-dai = <&afe>;
-+        };
-+
-+        codec {
-+            sound-dai = <&wm8960>;
-+        };
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch b/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
deleted file mode 100644
index 236d6a217c..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:38 +0800
-Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe
- document
-
-Add mt7986 audio afe document.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../bindings/sound/mediatek,mt7986-afe.yaml   | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-@@ -0,0 +1,160 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek AFE PCM controller for MT7986
-+
-+maintainers:
-+  - Maso Huang <maso.huang@mediatek.com>
-+
-+properties:
-+  compatible:
-+    oneOf:
-+      - const: mediatek,mt7986-afe
-+      - items:
-+          - enum:
-+              - mediatek,mt7981-afe
-+              - mediatek,mt7988-afe
-+          - const: mediatek,mt7986-afe
-+
-+  reg:
-+    maxItems: 1
-+
-+  interrupts:
-+    maxItems: 1
-+
-+  clocks:
-+    minItems: 5
-+    items:
-+      - description: audio bus clock
-+      - description: audio 26M clock
-+      - description: audio intbus clock
-+      - description: audio hopping clock
-+      - description: audio pll clock
-+      - description: mux for pcm_mck
-+      - description: audio i2s/pcm mck
-+
-+  clock-names:
-+    minItems: 5
-+    items:
-+      - const: bus_ck
-+      - const: 26m_ck
-+      - const: l_ck
-+      - const: aud_ck
-+      - const: eg2_ck
-+      - const: sel
-+      - const: i2s_m
-+
-+required:
-+  - compatible
-+  - reg
-+  - interrupts
-+  - clocks
-+  - clock-names
-+
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7986-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7981-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: mediatek,mt7988-afe
-+    then:
-+      properties:
-+        clocks:
-+          items:
-+            - description: audio bus clock
-+            - description: audio 26M clock
-+            - description: audio intbus clock
-+            - description: audio hopping clock
-+            - description: audio pll clock
-+            - description: mux for pcm_mck
-+            - description: audio i2s/pcm mck
-+        clock-names:
-+          items:
-+            - const: bus_ck
-+            - const: 26m_ck
-+            - const: l_ck
-+            - const: aud_ck
-+            - const: eg2_ck
-+            - const: sel
-+            - const: i2s_m
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
-+    #include <dt-bindings/interrupt-controller/irq.h>
-+    #include <dt-bindings/clock/mt7986-clk.h>
-+
-+    afe@11210000 {
-+        compatible = "mediatek,mt7986-afe";
-+        reg = <0x11210000 0x9000>;
-+        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
-+                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
-+        clock-names = "bus_ck",
-+                      "26m_ck",
-+                      "l_ck",
-+                      "aud_ck",
-+                      "eg2_ck";
-+        assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+                          <&topckgen CLK_TOP_AUD_L_SEL>,
-+                          <&topckgen CLK_TOP_A_TUNER_SEL>;
-+        assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+                                 <&apmixedsys CLK_APMIXED_APLL2>,
-+                                 <&topckgen CLK_TOP_APLL2_D4>;
-+    };
-+
-+...
diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
deleted file mode 100644
index 413db8233f..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:17 +0800
-Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
- mt7986_wm8960
-
-Drop the remove callback of mt7986_wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
- 1 file changed, 10 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -163,15 +163,6 @@ err_of_node_put:
- 	return ret;
- }
- 
--static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
--{
--	struct snd_soc_card *card = platform_get_drvdata(pdev);
--	struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
--
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
--}
--
- static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
- 	{.compatible = "mediatek,mt7986-wm8960-sound"},
- 	{ /* sentinel */ }
-@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
- 		.of_match_table = mt7986_wm8960_machine_dt_match,
- 	},
- 	.probe = mt7986_wm8960_machine_probe,
--	.remove_new = mt7986_wm8960_machine_remove,
- };
- 
- module_platform_driver(mt7986_wm8960_machine);
diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
deleted file mode 100644
index 5c596fc49c..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:18 +0800
-Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
- structure
-
-Remove the mt7986_wm8960_priv structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
- 1 file changed, 12 insertions(+), 21 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -12,11 +12,6 @@
- 
- #include "mt7986-afe-common.h"
- 
--struct mt7986_wm8960_priv {
--	struct device_node *platform_node;
--	struct device_node *codec_node;
--};
--
- static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
- 	SND_SOC_DAPM_HP("Headphone", NULL),
- 	SND_SOC_DAPM_MIC("AMIC", NULL),
-@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
- 	struct snd_soc_card *card = &mt7986_wm8960_card;
- 	struct snd_soc_dai_link *dai_link;
- 	struct device_node *platform, *codec;
--	struct mt7986_wm8960_priv *priv;
-+	struct device_node *platform_dai_node, *codec_dai_node;
- 	int ret, i;
- 
--	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
-+	card->dev = &pdev->dev;
- 
- 	platform = of_get_child_by_name(pdev->dev.of_node, "platform");
- 
- 	if (platform) {
--		priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+		platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
- 		of_node_put(platform);
- 
--		if (!priv->platform_node) {
-+		if (!platform_dai_node) {
- 			dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
- 			return -EINVAL;
- 		}
-@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->platforms->name)
- 			continue;
--		dai_link->platforms->of_node = priv->platform_node;
-+		dai_link->platforms->of_node = platform_dai_node;
- 	}
- 
--	card->dev = &pdev->dev;
--
- 	codec = of_get_child_by_name(pdev->dev.of_node, "codec");
- 
- 	if (codec) {
--		priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+		codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
- 		of_node_put(codec);
- 
--		if (!priv->codec_node) {
--			of_node_put(priv->platform_node);
-+		if (!codec_dai_node) {
-+			of_node_put(platform_dai_node);
- 			dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
- 			return -EINVAL;
- 		}
- 	} else {
--		of_node_put(priv->platform_node);
-+		of_node_put(platform_dai_node);
- 		dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
- 		return -EINVAL;
- 	}
-@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
- 	for_each_card_prelinks(card, i, dai_link) {
- 		if (dai_link->codecs->name)
- 			continue;
--		dai_link->codecs->of_node = priv->codec_node;
-+		dai_link->codecs->of_node = codec_dai_node;
- 	}
- 
- 	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
- 	}
- 
- err_of_node_put:
--	of_node_put(priv->codec_node);
--	of_node_put(priv->platform_node);
-+	of_node_put(platform_dai_node);
-+	of_node_put(codec_dai_node);
- 	return ret;
- }
- 
diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
deleted file mode 100644
index d4128deabc..0000000000
--- a/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:19 +0800
-Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
-
-mt7986 only supports 8/12/16/24/32/48/96/192 kHz
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
- 1 file changed, 19 insertions(+), 4 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
- 				  struct snd_pcm_hw_params *params,
- 				  struct snd_soc_dai *dai)
- {
-+	unsigned int rate = params_rate(params);
- 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
- 
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
--	mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
--
--	return 0;
-+	switch (rate) {
-+	case 8000:
-+	case 12000:
-+	case 16000:
-+	case 24000:
-+	case 32000:
-+	case 48000:
-+	case 96000:
-+	case 192000:
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+		mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+		return 0;
-+	default:
-+		dev_err(afe->dev,
-+			"Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
-+			rate);
-+		return -EINVAL;
-+	}
- }
- 
- static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
diff --git a/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
deleted file mode 100644
index a40c249257..0000000000
--- a/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 10 Dec 2023 22:41:39 +0000
-Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
- -EPROBE_DEFER
-
-If probe is defered no error should be printed. Mute it.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
- 
- 	ret = devm_snd_soc_register_card(&pdev->dev, card);
- 	if (ret) {
--		dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+
- 		goto err_of_node_put;
- 	}
- 
diff --git a/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch
deleted file mode 100644
index e40dca2a7d..0000000000
--- a/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add afe
-
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi     | 23 +++++++++++
- 1 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -249,6 +249,28 @@
- 			status = "disabled";
- 		};
- 
-+		afe: audio-controller@11210000 {
-+			compatible = "mediatek,mt7986-afe";
-+			reg = <0 0x11210000 0 0x9000>;
-+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-+				 <&infracfg CLK_INFRA_AUD_26M_CK>,
-+				 <&infracfg CLK_INFRA_AUD_L_CK>,
-+				 <&infracfg CLK_INFRA_AUD_AUD_CK>,
-+				 <&infracfg CLK_INFRA_AUD_EG2_CK>;
-+			clock-names = "aud_bus_ck",
-+				      "aud_26m_ck",
-+				      "aud_l_ck",
-+				      "aud_aud_ck",
-+				      "aud_eg2_ck";
-+			assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+					  <&topckgen CLK_TOP_AUD_L_SEL>,
-+					  <&topckgen CLK_TOP_A_TUNER_SEL>;
-+			assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+						 <&apmixedsys CLK_APMIXED_APLL2>,
-+						 <&topckgen CLK_TOP_APLL2_D4>;
-+		};
-+
- 		pwm: pwm@10048000 {
- 			compatible = "mediatek,mt7986-pwm";
- 			reg = <0 0x10048000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch
deleted file mode 100644
index 15e30dec56..0000000000
--- a/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
-
----
- .../dts/mediatek/mt7986a-rfb-spim-nand.dts    | 39 +++++++++++++++++++
- 1 files changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-@@ -4,6 +4,35 @@
- 
- / {
- 	compatible = "mediatek,mt7986a-rfb-snand";
-+
-+	sound_wm8960 {
-+		compatible = "mediatek,mt7986-wm8960-sound";
-+		audio-routing = "Headphone", "HP_L",
-+				"Headphone", "HP_R",
-+				"LINPUT1", "AMIC",
-+				"RINPUT1", "AMIC";
-+
-+		status = "okay";
-+
-+		platform {
-+			sound-dai = <&afe>;
-+		};
-+
-+		codec {
-+			sound-dai = <&wm8960>;
-+		};
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c_pins>;
-+	status = "okay";
-+
-+	wm8960: wm8960@1a {
-+		compatible = "wlf,wm8960";
-+		reg = <0x1a>;
-+	};
- };
- 
- &spi0 {
-@@ -50,3 +79,13 @@
- &wifi {
- 	mediatek,mtd-eeprom = <&factory 0>;
- };
-+
-+&pio {
-+	i2c_pins: i2c-pins-3-4 {
-+		mux {
-+			function = "i2c";
-+			groups = "i2c";
-+		};
-+	};
-+};
-+
diff --git a/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
deleted file mode 100644
index bddcd4bb0c..0000000000
--- a/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch
+++ /dev/null
@@ -1,75 +0,0 @@
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso
-@@ -0,0 +1,62 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ * Author: Maso Huang <Maso.Huang@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			sound_wm8960 {
-+				compatible = "mediatek,mt7986-wm8960-sound";
-+				audio-routing = "Headphone", "HP_L",
-+					"Headphone", "HP_R",
-+					"LINPUT1", "AMIC",
-+					"RINPUT1", "AMIC";
-+
-+				status = "okay";
-+
-+				platform {
-+					sound-dai = <&afe>;
-+				};
-+
-+				codec {
-+					sound-dai = <&wm8960>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&i2c_pins>;
-+			clock-frequency = <400000>;
-+			status = "okay";
-+
-+			wm8960: wm8960@1a {
-+				compatible = "wlf,wm8960";
-+				reg = <0x1a>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&pio>;
-+		__overlay__ {
-+			i2c_pins: i2c-pins-3-4 {
-+				mux {
-+					function = "i2c";
-+					groups = "i2c";
-+				};
-+			};
-+		};
-+	};
-+};
---- a/arch/arm64/boot/dts/mediatek/Makefile
-+++ b/arch/arm64/boot/dts/mediatek/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
deleted file mode 100644
index 87a937be05..0000000000
--- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ /dev/null
@@ -1,65 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -313,7 +313,7 @@
- 	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
- 	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
- 	 */
--	asm_sel {
-+	asmsel: asm_sel {
- 		gpio-hog;
- 		gpios = <90 GPIO_ACTIVE_HIGH>;
- 		output-high;
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&sata>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sata_phy>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+	fragment@0 {
-+		target = <&asmsel>;
-+		__overlay__ {
-+			gpios = <90 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+};
diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
deleted file mode 100644
index bfca4b6389..0000000000
--- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
+++ /dev/null
@@ -1,54 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config CMDLINE
- 	string "Default kernel command string"
- 	default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
- 	if (p != NULL && l > 0)
- 		strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
- 
-+    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+     * device tree option of chosen/bootargs-override. This is
-+     * helpful on boards where u-boot sets bootargs, and is unable
-+     * to be modified.
-+     */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+	if (p != NULL && l > 0)
-+		strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
- 	/*
- 	 * CONFIG_CMDLINE is meant to be a default in case nothing else
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -2240,6 +2240,14 @@ config CMDLINE_FORCE
- 
- endchoice
- 
-+config CMDLINE_OVERRIDE
-+	bool "Use alternative cmdline from device tree"
-+	help
-+	  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+	  be used, this is not a good option for kernels that are shared across
-+	  devices. This setting enables using "chosen/cmdline-override" as the
-+	  cmdline if it exists in the device tree.
-+
- config EFI_STUB
- 	bool
- 
diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
deleted file mode 100644
index d1f6a96720..0000000000
--- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -640,5 +640,28 @@
- };
- 
- &wmac {
-+	mediatek,eeprom-data = <0x22760500	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x44000020	0x0		0x10002000
-+				0x4400		0x4000000	0x0		0x0
-+				0x200000b3	0x40b6c3c3	0x26000000	0x41c42600
-+				0x41c4		0x26000000	0xc0c52600	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0xc6c6
-+				0xc3c3c2c1	0xc300c3	0x818181	0x83c1c182
-+				0x83838382	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x84002e00	0x90000087	0x8a000000	0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0xb000009	0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x0
-+				0x0		0x0		0x0		0x7707>;
-+
- 	status = "okay";
- };
diff --git a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
deleted file mode 100644
index 014342aad5..0000000000
--- a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch
+++ /dev/null
@@ -1,103 +0,0 @@
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -32,6 +32,9 @@
- 	chosen {
- 		stdout-path = "serial0:115200n8";
- 		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
-+		rootdisk-emmc = <&emmc_rootfs>;
-+		rootdisk-sd = <&sd_rootfs>;
-+		rootdisk-snfi = <&ubi_rootfs>;
- 	};
- 
- 	cpus {
-@@ -234,6 +237,26 @@
- 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- 	non-removable;
-+
-+	card@0 {
-+		compatible = "mmc-card";
-+		reg = <0>;
-+
-+		block {
-+			compatible = "block-device";
-+			partitions {
-+				block-partition-env {
-+					partname = "ubootenv";
-+					nvmem-layout {
-+						compatible = "u-boot,env-layout";
-+					};
-+				};
-+				emmc_rootfs: block-partition-production {
-+					partname = "production";
-+				};
-+			};
-+		};
-+	};
- };
- 
- &mmc1 {
-@@ -250,6 +273,26 @@
- 	vqmmc-supply = <&reg_3p3v>;
- 	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- 	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-+
-+	card@0 {
-+		compatible = "mmc-card";
-+		reg = <0>;
-+
-+		block {
-+			compatible = "block-device";
-+			partitions {
-+				block-partition-env {
-+					partname = "ubootenv";
-+					nvmem-layout {
-+						compatible = "u-boot,env-layout";
-+					};
-+				};
-+				sd_rootfs: block-partition-production {
-+					partname = "production";
-+				};
-+			};
-+		};
-+	};
- };
- 
- &nandc {
-@@ -284,14 +327,29 @@
- 			};
- 
- 			partition@80000 {
--				label = "fip";
--				reg = <0x80000 0x200000>;
--				read-only;
--			};
--
--			ubi: partition@280000 {
- 				label = "ubi";
--				reg = <0x280000 0x7d80000>;
-+				reg = <0x80000 0x7f80000>;
-+				compatible = "linux,ubi";
-+
-+				volumes {
-+					ubi-volume-ubootenv {
-+						volname = "ubootenv";
-+						nvmem-layout {
-+							compatible = "u-boot,env-redundant-bool-layout";
-+						};
-+					};
-+
-+					ubi-volume-ubootenv2 {
-+						volname = "ubootenv2";
-+						nvmem-layout {
-+							compatible = "u-boot,env-redundant-bool-layout";
-+						};
-+					};
-+
-+					ubi_rootfs: ubi-volume-fit {
-+						volname = "fit";
-+					};
-+				};
- 			};
- 		};
- 	};
diff --git a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch
deleted file mode 100644
index 3d05bf7679..0000000000
--- a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -1227,8 +1227,15 @@ static int mtk_spi_probe(struct platform
- 	if (ret < 0)
- 		return dev_err_probe(dev, ret, "failed to enable hclk\n");
- 
-+	ret = clk_prepare_enable(mdata->sel_clk);
-+	if (ret < 0) {
-+		clk_disable_unprepare(mdata->spi_hclk);
-+		return dev_err_probe(dev, ret, "failed to enable sel_clk\n");
-+	}
-+
- 	ret = clk_prepare_enable(mdata->spi_clk);
- 	if (ret < 0) {
-+		clk_disable_unprepare(mdata->sel_clk);
- 		clk_disable_unprepare(mdata->spi_hclk);
- 		return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
- 	}
diff --git a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
deleted file mode 100644
index 30be53518a..0000000000
--- a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
-Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 16:40:31 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
- mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
-
-This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
-dedicated dts nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
- }
- 
- static int
--mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
--			  struct mtk_wed_wo_memory_region *region)
-+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index,
-+				   struct mtk_wed_wo_memory_region *region)
- {
- 	struct reserved_mem *rmem;
- 	struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
--		ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
-+		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
- 	}
diff --git a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
deleted file mode 100644
index da61f1c050..0000000000
--- a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
-Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 16:32:41 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
- 1 file changed, 11 insertions(+), 10 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -121,12 +121,6 @@
- 			reg = <0 0x151f8000 0 0x2000>;
- 			no-map;
- 		};
--
--		wo_boot: wo-boot@15194000 {
--			reg = <0 0x15194000 0 0x1000>;
--			no-map;
--		};
--
- 	};
- 
- 	timer {
-@@ -541,10 +535,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wed1: wed@15011000 {
-@@ -554,10 +549,11 @@
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- 			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>, <&wo_boot>;
-+					<&wo_data>;
- 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data", "wo-boot";
-+					      "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
- 		wo_ccif0: syscon@151a5000 {
-@@ -574,6 +570,11 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_cpuboot: syscon@15194000 {
-+			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-+			reg = <0 0x15194000 0 0x1000>;
-+		};
-+
- 		eth: ethernet@15100000 {
- 			compatible = "mediatek,mt7986-eth";
- 			reg = <0 0x15100000 0 0x80000>;
diff --git a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
deleted file mode 100644
index b4bea2087b..0000000000
--- a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
-Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
-In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 18:13:04 +0100
-Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
- dedicated dts node
-
-Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
-in a deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where cpuboot was
-defined as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_wed_wo.h  |  3 +-
- 2 files changed, 30 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
- 
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
- {
--	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	u32 val;
-+
-+	if (!wo->boot_regmap)
-+		return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+
-+	if (regmap_read(wo->boot_regmap, reg, &val))
-+		val = ~0;
-+
-+	return val;
- }
- 
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
- {
--	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+	if (wo->boot_regmap)
-+		regmap_write(wo->boot_regmap, reg, val);
-+	else
-+		writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
- }
- 
- static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
-+							  "mediatek,wo-cpuboot");
-+
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
- 		int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 		if (index < 0)
- 			continue;
- 
-+		if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap))
-+			continue;
-+
- 		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- 		if (ret)
- 			return ret;
---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
- struct mtk_wed_wo {
- 	struct mtk_wed_hw *hw;
- 
-+	struct regmap *boot_regmap;
- 	struct mtk_wed_wo_queue q_tx;
- 	struct mtk_wed_wo_queue q_rx;
- 
diff --git a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
deleted file mode 100644
index b4ba5b0d2d..0000000000
--- a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
-Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 18:51:47 +0100
-Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
- node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where ilm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
- 1 file changed, 49 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
- }
- 
- static int
-+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo)
-+{
-+	struct mtk_wed_wo_memory_region *ilm_region;
-+	struct resource res;
-+	struct device_node *np;
-+	int ret;
-+
-+	np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
-+	if (!np)
-+		return 0;
-+
-+	ret = of_address_to_resource(np, 0, &res);
-+	of_node_put(np);
-+
-+	if (ret < 0)
-+		return ret;
-+
-+	ilm_region = &mem_region[MTK_WED_WO_REGION_ILM];
-+	ilm_region->phy_addr = res.start;
-+	ilm_region->size = resource_size(&res);
-+	ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
-+					resource_size(&res));
-+
-+	if (!IS_ERR(ilm_region->addr))
-+		return 0;
-+
-+	ret = PTR_ERR(ilm_region->addr);
-+	ilm_region->addr = NULL;
-+
-+	return ret;
-+}
-+
-+static int
- mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
- {
- 	const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- 	u32 val, boot_cr;
- 	int ret, i;
- 
-+	mtk_wed_mcu_load_ilm(wo);
- 	wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
- 							  "mediatek,wo-cpuboot");
- 
- 	/* load firmware region metadata */
- 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
--		int index = of_property_match_string(wo->hw->node,
--						     "memory-region-names",
--						     mem_region[i].name);
-+		int index;
-+
-+		if (mem_region[i].addr)
-+			continue;
-+
-+		index = of_property_match_string(wo->hw->node,
-+						 "memory-region-names",
-+						 mem_region[i].name);
- 		if (index < 0)
- 			continue;
- 
diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
deleted file mode 100644
index c92fcd43ce..0000000000
--- a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
-Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
-In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:45:16 +0100
-Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
- node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where dlm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 	struct device_node *np;
- 	int index;
- 
-+	np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
-+	if (np) {
-+		struct resource res;
-+		int ret;
-+
-+		ret = of_address_to_resource(np, 0, &res);
-+		of_node_put(np);
-+
-+		if (ret < 0)
-+			return ret;
-+
-+		dev->rro.miod_phys = res.start;
-+		goto out;
-+	}
-+
-+	/* For backward compatibility, we need to check if DLM
-+	 * node is defined through reserved memory property.
-+	 */
- 	index = of_property_match_string(dev->hw->node, "memory-region-names",
- 					 "wo-dlm");
- 	if (index < 0)
-@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- 		return -ENODEV;
- 
- 	dev->rro.miod_phys = rmem->base;
-+out:
- 	dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
- 
- 	return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
diff --git a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
deleted file mode 100644
index 2f1becd1b8..0000000000
--- a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
-Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:10:56 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
- 1 file changed, 16 insertions(+), 18 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -97,16 +97,6 @@
- 			no-map;
- 		};
- 
--		wo_ilm0: wo-ilm@151e0000 {
--			reg = <0 0x151e0000 0 0x8000>;
--			no-map;
--		};
--
--		wo_ilm1: wo-ilm@151f0000 {
--			reg = <0 0x151f0000 0 0x8000>;
--			no-map;
--		};
--
- 		wo_data: wo-data@4fd80000 {
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
-@@ -534,11 +524,10 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
-+			mediatek,wo-ilm = <&wo_ilm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -548,11 +537,10 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
--					<&wo_data>;
--			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
--					      "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
-+			mediatek,wo-ilm = <&wo_ilm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -570,6 +558,16 @@
- 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		wo_ilm0: syscon@151e0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151e0000 0 0x8000>;
-+		};
-+
-+		wo_ilm1: syscon@151f0000 {
-+			compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+			reg = <0 0x151f0000 0 0x8000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
deleted file mode 100644
index 5b52a4934e..0000000000
--- a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
-Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:53:30 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
- 1 file changed, 16 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -101,16 +101,6 @@
- 			reg = <0 0x4fd80000 0 0x240000>;
- 			no-map;
- 		};
--
--		wo_dlm0: wo-dlm@151e8000 {
--			reg = <0 0x151e8000 0 0x2000>;
--			no-map;
--		};
--
--		wo_dlm1: wo-dlm@151f8000 {
--			reg = <0 0x151f8000 0 0x2000>;
--			no-map;
--		};
- 	};
- 
- 	timer {
-@@ -524,10 +514,11 @@
- 			reg = <0 0x15010000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi0>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif0>;
- 			mediatek,wo-ilm = <&wo_ilm0>;
-+			mediatek,wo-dlm = <&wo_dlm0>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -537,10 +528,11 @@
- 			reg = <0 0x15011000 0 0x1000>;
- 			interrupt-parent = <&gic>;
- 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
--			memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
--			memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+			memory-region = <&wo_emi1>, <&wo_data>;
-+			memory-region-names = "wo-emi", "wo-data";
- 			mediatek,wo-ccif = <&wo_ccif1>;
- 			mediatek,wo-ilm = <&wo_ilm1>;
-+			mediatek,wo-dlm = <&wo_dlm1>;
- 			mediatek,wo-cpuboot = <&wo_cpuboot>;
- 		};
- 
-@@ -568,6 +560,16 @@
- 			reg = <0 0x151f0000 0 0x8000>;
- 		};
- 
-+		wo_dlm0: syscon@151e8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151e8000 0 0x2000>;
-+		};
-+
-+		wo_dlm1: syscon@151f8000 {
-+			compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+			reg = <0 0x151f8000 0 0x2000>;
-+		};
-+
- 		wo_cpuboot: syscon@15194000 {
- 			compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- 			reg = <0 0x15194000 0 0x1000>;
diff --git a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch
deleted file mode 100644
index 8b86c50429..0000000000
--- a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch
+++ /dev/null
@@ -1,34 +0,0 @@
----
- drivers/leds/Kconfig  |   10 ++++++++++
- drivers/leds/Makefile |    1 +
- 2 files changed, 11 insertions(+)
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig"
- comment "RGB LED drivers"
- source "drivers/leds/rgb/Kconfig"
- 
-+config LEDS_SMARTRG_LED
-+	tristate "LED support for Adtran SmartRG"
-+	depends on LEDS_CLASS && I2C && OF
-+	help
-+	  This option enables support for the Adtran SmartRG platform
-+	  system LED driver.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called leds-smartrg-system.
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
- 
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX)		+= leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SMARTRG_LED)		+= leds-smartrg-system.o
- obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o
diff --git a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
deleted file mode 100644
index 71cb3006ab..0000000000
--- a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ /dev/null
@@ -1,599 +0,0 @@
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et
- 		eth->scratch_ring = eth->sram_base;
- 	else
- 		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
--						       cnt * soc->txrx.txd_size,
-+						       cnt * soc->tx.desc_size,
- 						       &eth->phy_scratch_ring,
- 						       GFP_KERNEL);
- 	if (unlikely(!eth->scratch_ring))
-@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et
- 	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- 		return -ENOMEM;
- 
--	phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
- 
- 	for (i = 0; i < cnt; i++) {
- 		struct mtk_tx_dma_v2 *txd;
- 
--		txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+		txd = eth->scratch_ring + i * soc->tx.desc_size;
- 		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- 		if (i < cnt - 1)
- 			txd->txd2 = eth->phy_scratch_ring +
--				    (i + 1) * soc->txrx.txd_size;
-+				    (i + 1) * soc->tx.desc_size;
- 
- 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- 		txd->txd4 = 0;
-@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	if (itxd == ring->last_free)
- 		return -ENOMEM;
- 
--	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 	memset(itx_buf, 0, sizeof(*itx_buf));
- 
- 	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- 			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- 			txd_info.size = min_t(unsigned int, frag_size,
--					      soc->txrx.dma_max_len);
-+					      soc->tx.dma_max_len);
- 			txd_info.qid = queue;
- 			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- 					!(frag_size - txd_info.size);
-@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 			mtk_tx_set_dma_desc(dev, txd, &txd_info);
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			if (new_desc)
- 				memset(tx_buf, 0, sizeof(*tx_buf));
- 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	} else {
- 		int next_idx;
- 
--		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- 					 ring->dma_size);
- 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- 	}
-@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- err_dma:
- 	do {
--		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 
- 		/* unmap dma */
- 		mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et
- 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- 			frag = &skb_shinfo(skb)->frags[i];
- 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
--					       eth->soc->txrx.dma_max_len);
-+					       eth->soc->tx.dma_max_len);
- 		}
- 	} else {
- 		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
- 
- 		ring = &eth->rx_ring[i];
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		if (rxd->rxd2 & RX_DMA_DONE) {
- 			ring->calc_idx_update = true;
- 			return ring;
-@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m
- 	}
- 	htxd = txd;
- 
--	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- 	memset(tx_buf, 0, sizeof(*tx_buf));
- 	htx_buf = tx_buf;
- 
-@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m
- 				goto unmap;
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			memset(tx_buf, 0, sizeof(*tx_buf));
- 			n_desc++;
- 		}
-@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m
- 	} else {
- 		int idx;
- 
--		idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+		idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- 			MT7628_TX_CTX_IDX0);
- 	}
-@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m
- 
- unmap:
- 	while (htxd != txd) {
--		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- 		mtk_tx_unmap(eth, tx_buf, NULL, false);
- 
- 		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc
- 			goto rx_done;
- 
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		data = ring->data[idx];
- 
- 		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc
- 			rxdcsum = &trxd.rxd4;
- 		}
- 
--		if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+		if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- 			skb->ip_summed = CHECKSUM_UNNECESSARY;
- 		else
- 			skb_checksum_none_assert(skb);
-@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- 			break;
- 
- 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
--					    eth->soc->txrx.txd_size);
-+					    eth->soc->tx.desc_size);
- 		if (!tx_buf->data)
- 			break;
- 
-@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- 		}
- 		mtk_tx_unmap(eth, tx_buf, &bq, true);
- 
--		desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+		desc = ring->dma + cpu * eth->soc->tx.desc_size;
- 		ring->last_free = desc;
- 		atomic_inc(&ring->free_count);
- 
-@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc
- 	do {
- 		int rx_done;
- 
--		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+		mtk_w32(eth, eth->soc->rx.irq_done_mask,
- 			reg_map->pdma.irq_status);
- 		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- 		rx_done_total += rx_done;
-@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc
- 			return budget;
- 
- 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
--		 eth->soc->txrx.rx_irq_done_mask);
-+		 eth->soc->rx.irq_done_mask);
- 
- 	if (napi_complete_done(napi, rx_done_total))
--		mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- 
- 	return rx_done_total;
- }
-@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- 	const struct mtk_soc_data *soc = eth->soc;
- 	struct mtk_tx_ring *ring = &eth->tx_ring;
--	int i, sz = soc->txrx.txd_size;
-+	int i, sz = soc->tx.desc_size;
- 	struct mtk_tx_dma_v2 *txd;
- 	int ring_size;
- 	u32 ofs, val;
-@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth
- 	}
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
- 
- 	if (ring->dma_pdma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma_pdma, ring->phys_pdma);
- 		ring->dma_pdma = NULL;
- 	}
-@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- 	    rx_flag != MTK_RX_FLAGS_NORMAL) {
- 		ring->dma = dma_alloc_coherent(eth->dma_dev,
--					       rx_dma_size * eth->soc->txrx.rxd_size,
--					       &ring->phys, GFP_KERNEL);
-+				rx_dma_size * eth->soc->rx.desc_size,
-+				&ring->phys, GFP_KERNEL);
- 	} else {
- 		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
- 
- 		ring->dma = tx_ring->dma + tx_ring_size *
--			    eth->soc->txrx.txd_size * (ring_no + 1);
-+			    eth->soc->tx.desc_size * (ring_no + 1);
- 		ring->phys = tx_ring->phys + tx_ring_size *
--			     eth->soc->txrx.txd_size * (ring_no + 1);
-+			     eth->soc->tx.desc_size * (ring_no + 1);
- 	}
- 
- 	if (!ring->dma)
-@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 		dma_addr_t dma_addr;
- 		void *data;
- 
--		rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + i * eth->soc->rx.desc_size;
- 		if (ring->page_pool) {
- 			data = mtk_page_pool_get_buff(ring->page_pool,
- 						      &dma_addr, GFP_KERNEL);
-@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth
- 			if (!ring->data[i])
- 				continue;
- 
--			rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+			rxd = ring->dma + i * eth->soc->rx.desc_size;
- 			if (!rxd->rxd1)
- 				continue;
- 
-@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
- 
- 	if (!in_sram && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * eth->soc->txrx.rxd_size,
-+				  ring->dma_size * eth->soc->rx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
-@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth
- 			netdev_reset_queue(eth->netdev[i]);
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- 		dma_free_coherent(eth->dma_dev,
--				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- 				  eth->scratch_ring, eth->phy_scratch_ring);
- 		eth->scratch_ring = NULL;
- 		eth->phy_scratch_ring = 0;
-@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int
- 
- 	eth->rx_events++;
- 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
--		mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 		__napi_schedule(&eth->rx_napi);
- 	}
- 
-@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir
- 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- 
- 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
--	    eth->soc->txrx.rx_irq_done_mask) {
-+	    eth->soc->rx.irq_done_mask) {
- 		if (mtk_r32(eth, reg_map->pdma.irq_status) &
--		    eth->soc->txrx.rx_irq_done_mask)
-+		    eth->soc->rx.irq_done_mask)
- 			mtk_handle_irq_rx(irq, _eth);
- 	}
- 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n
- 	struct mtk_eth *eth = mac->hw;
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	mtk_handle_irq_rx(eth->irq[2], dev);
- 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
- 
-@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d
- 		napi_enable(&eth->tx_napi);
- 		napi_enable(&eth->rx_napi);
- 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--		mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- 		refcount_set(&eth->dma_refcnt, 1);
- 	}
- 	else
-@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d
- 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	napi_disable(&eth->tx_napi);
- 	napi_disable(&eth->rx_napi);
- 
-@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e
- 
- 	/* FE int grouping */
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
- 
- 	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_
- 	.required_clks = MT7623_CLKS_BITMAP,
- 	.required_pctl = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_
- 	.offload_version = 1,
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_
- 	.hash_offset = 2,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- 	.disable_pll_modes = true,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_
- 	.required_pctl = false,
- 	.has_accounting = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_
- 	.required_clks = MT7628_CLKS_BITMAP,
- 	.required_pctl = false,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -327,8 +327,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU	BIT(31)
- #define TX_DMA_LS0		BIT(30)
--#define TX_DMA_PLEN0(x)		(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x)		(((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x)		((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC		BIT(14)
- #define TX_DMA_PQID		GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -348,8 +348,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE		BIT(31)
- #define RX_DMA_LSO		BIT(30)
--#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG		BIT(15)
- #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
-  * @foe_entry_size		Foe table entry size.
-  * @has_accounting		Bool indicating support for accounting of
-  *				offloaded flows.
-- * @txd_size			Tx DMA descriptor size.
-- * @rxd_size			Rx DMA descriptor size.
-- * @rx_irq_done_mask		Rx irq done register mask.
-- * @rx_dma_l4_valid		Rx DMA valid register mask.
-+ * @desc_size			Tx/Rx DMA descriptor size.
-+ * @irq_done_mask		Rx irq done register mask.
-+ * @dma_l4_valid		Rx DMA valid register mask.
-  * @dma_max_len			Max DMA tx/rx buffer length.
-  * @dma_len_offset		Tx/Rx DMA length field offset.
-  */
-@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
- 	bool		has_accounting;
- 	bool		disable_pll_modes;
- 	struct {
--		u32	txd_size;
--		u32	rxd_size;
--		u32	rx_irq_done_mask;
--		u32	rx_dma_l4_valid;
-+		u32	desc_size;
- 		u32	dma_max_len;
- 		u32	dma_len_offset;
--	} txrx;
-+	} tx;
-+	struct {
-+		u32	desc_size;
-+		u32	irq_done_mask;
-+		u32	dma_l4_valid;
-+		u32	dma_max_len;
-+		u32	dma_len_offset;
-+	} rx;
- };
- 
- #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
diff --git a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
deleted file mode 100644
index 8b7d5c0a1c..0000000000
--- a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
- 	.tx_irq_mask		= 0x461c,
- 	.tx_irq_status		= 0x4618,
- 	.pdma = {
--		.rx_ptr		= 0x6100,
--		.rx_cnt_cfg	= 0x6104,
--		.pcrx_ptr	= 0x6108,
--		.glo_cfg	= 0x6204,
--		.rst_idx	= 0x6208,
--		.delay_irq	= 0x620c,
--		.irq_status	= 0x6220,
--		.irq_mask	= 0x6228,
--		.adma_rx_dbg0	= 0x6238,
--		.int_grp	= 0x6250,
-+		.rx_ptr		= 0x4100,
-+		.rx_cnt_cfg	= 0x4104,
-+		.pcrx_ptr	= 0x4108,
-+		.glo_cfg	= 0x4204,
-+		.rst_idx	= 0x4208,
-+		.delay_irq	= 0x420c,
-+		.irq_status	= 0x4220,
-+		.irq_mask	= 0x4228,
-+		.adma_rx_dbg0	= 0x4238,
-+		.int_grp	= 0x4250,
- 	},
- 	.qdma = {
- 		.qtx_cfg	= 0x4400,
-@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- 	}
-@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
- 			break;
- 
- 		/* find out which mac the packet come from. values start at 1 */
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
- 
- 			switch (val) {
-@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
- 		skb->dev = netdev;
- 		bytes += skb->len;
- 
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- 			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 
- 		rxd->rxd3 = 0;
- 		rxd->rxd4 = 0;
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			rxd->rxd5 = 0;
- 			rxd->rxd6 = 0;
- 			rxd->rxd7 = 0;
-@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 	else
- 		mtk_hw_reset(eth);
- 
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		/* Set FE to PDMAv2 if necessary */
- 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
- 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
-@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
deleted file mode 100644
index 11b52d07ab..0000000000
--- a/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+	mtk_wed_dma_disable(dev);
- 	mtk_wed_set_ext_int(dev, false);
- 
- 	wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- 	wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
--	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- 
- 	if (!mtk_wed_get_rx_capa(dev))
- 		return;
-@@ -1090,7 +1090,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- 	mtk_wed_stop(dev);
--	mtk_wed_dma_disable(dev);
- 
- 	wed_clr(dev, MTK_WED_CTRL,
- 		MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
--	if (!dev->running)
--		return;
--
- 	mtk_wed_set_ext_int(dev, !!mask);
- 	wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
diff --git a/target/linux/mediatek/patches-6.6/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.6/104-mt7622-add-snor-irq.patch
index 0d9c91f44d..d15d989e97 100644
--- a/target/linux/mediatek/patches-6.6/104-mt7622-add-snor-irq.patch
+++ b/target/linux/mediatek/patches-6.6/104-mt7622-add-snor-irq.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -578,6 +578,7 @@
+@@ -575,6 +575,7 @@
  		compatible = "mediatek,mt7622-nor",
  			     "mediatek,mt8173-nor";
  		reg = <0 0x11014000 0 0xe0>;
diff --git a/target/linux/mediatek/patches-6.6/107-mt7622_fix_dts_mt7531_reg.patch b/target/linux/mediatek/patches-6.6/107-mt7622_fix_dts_mt7531_reg.patch
new file mode 100644
index 0000000000..75a9c55f92
--- /dev/null
+++ b/target/linux/mediatek/patches-6.6/107-mt7622_fix_dts_mt7531_reg.patch
@@ -0,0 +1,28 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -145,9 +145,9 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		switch@0 {
++		switch@1f {
+ 			compatible = "mediatek,mt7531";
+-			reg = <0>;
++			reg = <31>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <1>;
+ 			interrupt-parent = <&pio>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -117,9 +117,9 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		switch@0 {
++		switch@1f {
+ 			compatible = "mediatek,mt7531";
+-			reg = <0>;
++			reg = <31>;
+ 			reset-gpios = <&pio 54 0>;
+ 
+ 			ports {
diff --git a/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
index f1a182b044..fac14b4d82 100644
--- a/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
+++ b/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch
@@ -5,7 +5,7 @@
  	chosen {
  		stdout-path = "serial2:115200n8";
 -		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+		bootargs = "root=/dev/fit0 earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++		bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
 +		rootdisk-emmc = <&emmc_rootdisk>;
 +		rootdisk-sd = <&sd_rootdisk>;
  	};
diff --git a/target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
index bd0c785fde..bf6823147e 100644
--- a/target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
+++ b/target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch
@@ -95,7 +95,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -347,7 +347,7 @@
+@@ -345,7 +345,7 @@
  		#interrupt-cells = <3>;
  		interrupt-parent = <&gic>;
  		reg = <0 0x10310000 0 0x1000>,
diff --git a/target/linux/mediatek/patches-6.6/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.6/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
index 7188c254ba..22408b9273 100644
--- a/target/linux/mediatek/patches-6.6/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
+++ b/target/linux/mediatek/patches-6.6/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch
@@ -57,8 +57,8 @@ Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
 +		SPINAND_PROG_LOAD(true, 0, NULL, 0));
 +
 +static SPINAND_OP_VARIANTS(update_cache_variants,
-+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
++		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++		SPINAND_PROG_LOAD(true, 0, NULL, 0));
 +
 +static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
 +				  struct mtd_oob_region *region)
diff --git a/target/linux/mediatek/patches-6.6/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.6/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
index bf479ab53b..d58082aa6f 100644
--- a/target/linux/mediatek/patches-6.6/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
+++ b/target/linux/mediatek/patches-6.6/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
+@@ -844,6 +844,12 @@
  			#address-cells = <0>;
  			#interrupt-cells = <1>;
  		};
@@ -13,7 +13,7 @@
  	};
  
  	pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
+@@ -882,6 +888,12 @@
  			#address-cells = <0>;
  			#interrupt-cells = <1>;
  		};
diff --git a/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
index 76ee2fc89a..917a458d30 100644
--- a/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
+++ b/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
+@@ -832,6 +832,9 @@
  		bus-range = <0x00 0xff>;
  		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
  		status = "disabled";
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  		#interrupt-cells = <1>;
  		interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
+@@ -876,6 +879,9 @@
  		bus-range = <0x00 0xff>;
  		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
  		status = "disabled";
@@ -30,6 +30,15 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  		#interrupt-cells = <1>;
  		interrupt-map-mask = <0 0 0 7>;
+@@ -937,7 +943,7 @@
+ 	};
+ 
+ 	hifsys: clock-controller@1af00000 {
+-		compatible = "mediatek,mt7622-hifsys";
++		compatible = "mediatek,mt7622-hifsys", "syscon";
+ 		reg = <0 0x1af00000 0 0x70>;
+ 		#clock-cells = <1>;
+ 	};
 --- a/drivers/pci/controller/pcie-mediatek.c
 +++ b/drivers/pci/controller/pcie-mediatek.c
 @@ -20,6 +20,7 @@
diff --git a/target/linux/mediatek/patches-6.6/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-6.6/862-arm64-dts-mt7986-add-afe.patch
index b31710fe69..29de7851d3 100644
--- a/target/linux/mediatek/patches-6.6/862-arm64-dts-mt7986-add-afe.patch
+++ b/target/linux/mediatek/patches-6.6/862-arm64-dts-mt7986-add-afe.patch
@@ -9,8 +9,8 @@ Subject: [PATCH] arm64: dts: mt7986: add afe
 
 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -248,6 +248,28 @@
- 			status = "disabled";
+@@ -202,6 +202,28 @@
+ 			#interrupt-cells = <2>;
  		};
  
 +		afe: audio-controller@11210000 {
diff --git a/target/linux/mediatek/patches-6.6/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.6/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
index 30be53518a..465f0eaf27 100644
--- a/target/linux/mediatek/patches-6.6/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
+++ b/target/linux/mediatek/patches-6.6/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch
@@ -26,7 +26,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  {
  	struct reserved_mem *rmem;
  	struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
  		if (index < 0)
  			continue;
  
diff --git a/target/linux/mediatek/patches-6.6/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.6/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
index e1f121eba1..73714fbd6f 100644
--- a/target/linux/mediatek/patches-6.6/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
+++ b/target/linux/mediatek/patches-6.6/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch
@@ -23,8 +23,8 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 -
  	};
  
- 	timer {
-@@ -543,10 +537,11 @@
+ 	soc {
+@@ -532,10 +526,11 @@
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
@@ -38,7 +38,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		};
  
  		wed1: wed@15011000 {
-@@ -556,10 +551,11 @@
+@@ -545,10 +540,11 @@
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
@@ -51,8 +51,8 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 +			mediatek,wo-cpuboot = <&wo_cpuboot>;
  		};
  
- 		wo_ccif0: syscon@151a5000 {
-@@ -576,6 +572,11 @@
+ 		eth: ethernet@15100000 {
+@@ -606,6 +602,11 @@
  			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
  		};
  
@@ -61,6 +61,6 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 +			reg = <0 0x15194000 0 0x1000>;
 +		};
 +
- 		eth: ethernet@15100000 {
- 			compatible = "mediatek,mt7986-eth";
- 			reg = <0 0x15100000 0 0x80000>;
+ 		wifi: wifi@18000000 {
+ 			compatible = "mediatek,mt7986-wmac";
+ 			reg = <0 0x18000000 0 0x1000000>,
diff --git a/target/linux/mediatek/patches-6.6/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.6/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
index b4bea2087b..43014c5d12 100644
--- a/target/linux/mediatek/patches-6.6/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
+++ b/target/linux/mediatek/patches-6.6/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch
@@ -23,9 +23,12 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
+@@ -32,14 +32,25 @@ static struct mtk_wed_wo_memory_region m
+ 	},
+ };
  
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+-static u32 wo_r32(u32 reg)
++static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
  {
 -	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
 +	u32 val;
@@ -39,7 +42,8 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 +	return val;
  }
  
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+-static void wo_w32(u32 reg, u32 val)
++static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
  {
 -	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
 +	if (wo->boot_regmap)
@@ -49,7 +53,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  }
  
  static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
  	u32 val, boot_cr;
  	int ret, i;
  
@@ -59,7 +63,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	/* load firmware region metadata */
  	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
  		int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
  		if (index < 0)
  			continue;
  
@@ -69,6 +73,24 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
  		if (ret)
  			return ret;
+@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 		boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
+ 	else
+ 		boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+-	wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
++	wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ 	/* wo firmware reset */
+-	wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
++	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+ 
+-	val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
+ 	      MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+-	wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
++	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ 	release_firmware(fw);
+ 
 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
 @@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
diff --git a/target/linux/mediatek/patches-6.6/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.6/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
index b4ba5b0d2d..641c2597f7 100644
--- a/target/linux/mediatek/patches-6.6/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
+++ b/target/linux/mediatek/patches-6.6/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch
@@ -20,7 +20,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
+@@ -320,6 +320,39 @@ next:
  }
  
  static int
@@ -60,7 +60,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
  {
  	const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
  	u32 val, boot_cr;
  	int ret, i;
  
diff --git a/target/linux/mediatek/patches-6.6/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.6/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
index 0701743ffb..abb6591b7d 100644
--- a/target/linux/mediatek/patches-6.6/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
+++ b/target/linux/mediatek/patches-6.6/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch
@@ -22,7 +22,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1321,6 +1321,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
  	struct device_node *np;
  	int index;
  
@@ -47,7 +47,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	index = of_property_match_string(dev->hw->node, "memory-region-names",
  					 "wo-dlm");
  	if (index < 0)
-@@ -1337,6 +1355,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
  		return -ENODEV;
  
  	dev->rro.miod_phys = rmem->base;
diff --git a/target/linux/mediatek/patches-6.6/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.6/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
index 08c76cf44b..e2dce9ffa3 100644
--- a/target/linux/mediatek/patches-6.6/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
+++ b/target/linux/mediatek/patches-6.6/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch
@@ -34,7 +34,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  		wo_data: wo-data@4fd80000 {
  			reg = <0 0x4fd80000 0 0x240000>;
  			no-map;
-@@ -536,11 +526,10 @@
+@@ -525,11 +515,10 @@
  			reg = <0 0x15010000 0 0x1000>;
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
@@ -49,7 +49,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mediatek,wo-cpuboot = <&wo_cpuboot>;
  		};
  
-@@ -550,11 +539,10 @@
+@@ -539,11 +528,10 @@
  			reg = <0 0x15011000 0 0x1000>;
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
@@ -64,7 +64,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mediatek,wo-cpuboot = <&wo_cpuboot>;
  		};
  
-@@ -572,6 +560,16 @@
+@@ -602,6 +590,16 @@
  			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
  		};
  
diff --git a/target/linux/mediatek/patches-6.6/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.6/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
index a44d006c53..a972f235f2 100644
--- a/target/linux/mediatek/patches-6.6/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
+++ b/target/linux/mediatek/patches-6.6/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch
@@ -33,8 +33,8 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 -		};
  	};
  
- 	timer {
-@@ -526,10 +516,11 @@
+ 	soc {
+@@ -515,10 +505,11 @@
  			reg = <0 0x15010000 0 0x1000>;
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
@@ -48,7 +48,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mediatek,wo-cpuboot = <&wo_cpuboot>;
  		};
  
-@@ -539,10 +530,11 @@
+@@ -528,10 +519,11 @@
  			reg = <0 0x15011000 0 0x1000>;
  			interrupt-parent = <&gic>;
  			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
@@ -62,7 +62,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  			mediatek,wo-cpuboot = <&wo_cpuboot>;
  		};
  
-@@ -570,6 +562,16 @@
+@@ -600,6 +592,16 @@
  			reg = <0 0x151f0000 0 0x8000>;
  		};
  
diff --git a/target/linux/mediatek/patches-6.6/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-6.6/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
deleted file mode 100644
index d4517af447..0000000000
--- a/target/linux/mediatek/patches-6.6/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
+++ /dev/null
@@ -1,599 +0,0 @@
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1281,7 +1281,7 @@ static int mtk_init_fq_dma(struct mtk_et
- 		eth->scratch_ring = eth->sram_base;
- 	else
- 		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
--						       cnt * soc->txrx.txd_size,
-+						       cnt * soc->tx.desc_size,
- 						       &eth->phy_scratch_ring,
- 						       GFP_KERNEL);
- 	if (unlikely(!eth->scratch_ring))
-@@ -1297,16 +1297,16 @@ static int mtk_init_fq_dma(struct mtk_et
- 	if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- 		return -ENOMEM;
- 
--	phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+	phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
- 
- 	for (i = 0; i < cnt; i++) {
- 		struct mtk_tx_dma_v2 *txd;
- 
--		txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+		txd = eth->scratch_ring + i * soc->tx.desc_size;
- 		txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- 		if (i < cnt - 1)
- 			txd->txd2 = eth->phy_scratch_ring +
--				    (i + 1) * soc->txrx.txd_size;
-+				    (i + 1) * soc->tx.desc_size;
- 
- 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- 		txd->txd4 = 0;
-@@ -1555,7 +1555,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	if (itxd == ring->last_free)
- 		return -ENOMEM;
- 
--	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+	itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 	memset(itx_buf, 0, sizeof(*itx_buf));
- 
- 	txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1596,7 +1596,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- 			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- 			txd_info.size = min_t(unsigned int, frag_size,
--					      soc->txrx.dma_max_len);
-+					      soc->tx.dma_max_len);
- 			txd_info.qid = queue;
- 			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- 					!(frag_size - txd_info.size);
-@@ -1609,7 +1609,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 			mtk_tx_set_dma_desc(dev, txd, &txd_info);
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			if (new_desc)
- 				memset(tx_buf, 0, sizeof(*tx_buf));
- 			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1652,7 +1652,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 	} else {
- 		int next_idx;
- 
--		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+		next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- 					 ring->dma_size);
- 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- 	}
-@@ -1661,7 +1661,7 @@ static int mtk_tx_map(struct sk_buff *sk
- 
- err_dma:
- 	do {
--		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- 
- 		/* unmap dma */
- 		mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1686,7 +1686,7 @@ static int mtk_cal_txd_req(struct mtk_et
- 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- 			frag = &skb_shinfo(skb)->frags[i];
- 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
--					       eth->soc->txrx.dma_max_len);
-+					       eth->soc->tx.dma_max_len);
- 		}
- 	} else {
- 		nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1827,7 +1827,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
- 
- 		ring = &eth->rx_ring[i];
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		if (rxd->rxd2 & RX_DMA_DONE) {
- 			ring->calc_idx_update = true;
- 			return ring;
-@@ -1995,7 +1995,7 @@ static int mtk_xdp_submit_frame(struct m
- 	}
- 	htxd = txd;
- 
--	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+	tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- 	memset(tx_buf, 0, sizeof(*tx_buf));
- 	htx_buf = tx_buf;
- 
-@@ -2014,7 +2014,7 @@ static int mtk_xdp_submit_frame(struct m
- 				goto unmap;
- 
- 			tx_buf = mtk_desc_to_tx_buf(ring, txd,
--						    soc->txrx.txd_size);
-+						    soc->tx.desc_size);
- 			memset(tx_buf, 0, sizeof(*tx_buf));
- 			n_desc++;
- 		}
-@@ -2052,7 +2052,7 @@ static int mtk_xdp_submit_frame(struct m
- 	} else {
- 		int idx;
- 
--		idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+		idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- 		mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- 			MT7628_TX_CTX_IDX0);
- 	}
-@@ -2063,7 +2063,7 @@ static int mtk_xdp_submit_frame(struct m
- 
- unmap:
- 	while (htxd != txd) {
--		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+		tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- 		mtk_tx_unmap(eth, tx_buf, NULL, false);
- 
- 		htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2194,7 +2194,7 @@ static int mtk_poll_rx(struct napi_struc
- 			goto rx_done;
- 
- 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
--		rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + idx * eth->soc->rx.desc_size;
- 		data = ring->data[idx];
- 
- 		if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2329,7 +2329,7 @@ static int mtk_poll_rx(struct napi_struc
- 			rxdcsum = &trxd.rxd4;
- 		}
- 
--		if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+		if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- 			skb->ip_summed = CHECKSUM_UNNECESSARY;
- 		else
- 			skb_checksum_none_assert(skb);
-@@ -2453,7 +2453,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- 			break;
- 
- 		tx_buf = mtk_desc_to_tx_buf(ring, desc,
--					    eth->soc->txrx.txd_size);
-+					    eth->soc->tx.desc_size);
- 		if (!tx_buf->data)
- 			break;
- 
-@@ -2504,7 +2504,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- 		}
- 		mtk_tx_unmap(eth, tx_buf, &bq, true);
- 
--		desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+		desc = ring->dma + cpu * eth->soc->tx.desc_size;
- 		ring->last_free = desc;
- 		atomic_inc(&ring->free_count);
- 
-@@ -2594,7 +2594,7 @@ static int mtk_napi_rx(struct napi_struc
- 	do {
- 		int rx_done;
- 
--		mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+		mtk_w32(eth, eth->soc->rx.irq_done_mask,
- 			reg_map->pdma.irq_status);
- 		rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- 		rx_done_total += rx_done;
-@@ -2610,10 +2610,10 @@ static int mtk_napi_rx(struct napi_struc
- 			return budget;
- 
- 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &
--		 eth->soc->txrx.rx_irq_done_mask);
-+		 eth->soc->rx.irq_done_mask);
- 
- 	if (napi_complete_done(napi, rx_done_total))
--		mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- 
- 	return rx_done_total;
- }
-@@ -2622,7 +2622,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- 	const struct mtk_soc_data *soc = eth->soc;
- 	struct mtk_tx_ring *ring = &eth->tx_ring;
--	int i, sz = soc->txrx.txd_size;
-+	int i, sz = soc->tx.desc_size;
- 	struct mtk_tx_dma_v2 *txd;
- 	int ring_size;
- 	u32 ofs, val;
-@@ -2745,14 +2745,14 @@ static void mtk_tx_clean(struct mtk_eth
- 	}
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
- 
- 	if (ring->dma_pdma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * soc->txrx.txd_size,
-+				  ring->dma_size * soc->tx.desc_size,
- 				  ring->dma_pdma, ring->phys_pdma);
- 		ring->dma_pdma = NULL;
- 	}
-@@ -2807,15 +2807,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- 	    rx_flag != MTK_RX_FLAGS_NORMAL) {
- 		ring->dma = dma_alloc_coherent(eth->dma_dev,
--					       rx_dma_size * eth->soc->txrx.rxd_size,
--					       &ring->phys, GFP_KERNEL);
-+				rx_dma_size * eth->soc->rx.desc_size,
-+				&ring->phys, GFP_KERNEL);
- 	} else {
- 		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
- 
- 		ring->dma = tx_ring->dma + tx_ring_size *
--			    eth->soc->txrx.txd_size * (ring_no + 1);
-+			    eth->soc->tx.desc_size * (ring_no + 1);
- 		ring->phys = tx_ring->phys + tx_ring_size *
--			     eth->soc->txrx.txd_size * (ring_no + 1);
-+			     eth->soc->tx.desc_size * (ring_no + 1);
- 	}
- 
- 	if (!ring->dma)
-@@ -2826,7 +2826,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 		dma_addr_t dma_addr;
- 		void *data;
- 
--		rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+		rxd = ring->dma + i * eth->soc->rx.desc_size;
- 		if (ring->page_pool) {
- 			data = mtk_page_pool_get_buff(ring->page_pool,
- 						      &dma_addr, GFP_KERNEL);
-@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
- 			if (!ring->data[i])
- 				continue;
- 
--			rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+			rxd = ring->dma + i * eth->soc->rx.desc_size;
- 			if (!rxd->rxd1)
- 				continue;
- 
-@@ -2934,7 +2934,7 @@ static void mtk_rx_clean(struct mtk_eth
- 
- 	if (!in_sram && ring->dma) {
- 		dma_free_coherent(eth->dma_dev,
--				  ring->dma_size * eth->soc->txrx.rxd_size,
-+				  ring->dma_size * eth->soc->rx.desc_size,
- 				  ring->dma, ring->phys);
- 		ring->dma = NULL;
- 	}
-@@ -3297,7 +3297,7 @@ static void mtk_dma_free(struct mtk_eth
- 			netdev_reset_queue(eth->netdev[i]);
- 	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- 		dma_free_coherent(eth->dma_dev,
--				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+				  MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- 				  eth->scratch_ring, eth->phy_scratch_ring);
- 		eth->scratch_ring = NULL;
- 		eth->phy_scratch_ring = 0;
-@@ -3347,7 +3347,7 @@ static irqreturn_t mtk_handle_irq_rx(int
- 
- 	eth->rx_events++;
- 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
--		mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 		__napi_schedule(&eth->rx_napi);
- 	}
- 
-@@ -3373,9 +3373,9 @@ static irqreturn_t mtk_handle_irq(int ir
- 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- 
- 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &
--	    eth->soc->txrx.rx_irq_done_mask) {
-+	    eth->soc->rx.irq_done_mask) {
- 		if (mtk_r32(eth, reg_map->pdma.irq_status) &
--		    eth->soc->txrx.rx_irq_done_mask)
-+		    eth->soc->rx.irq_done_mask)
- 			mtk_handle_irq_rx(irq, _eth);
- 	}
- 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3393,10 +3393,10 @@ static void mtk_poll_controller(struct n
- 	struct mtk_eth *eth = mac->hw;
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	mtk_handle_irq_rx(eth->irq[2], dev);
- 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
- 
-@@ -3563,7 +3563,7 @@ static int mtk_open(struct net_device *d
- 		napi_enable(&eth->tx_napi);
- 		napi_enable(&eth->rx_napi);
- 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
--		mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+		mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- 		refcount_set(&eth->dma_refcnt, 1);
- 	}
- 	else
-@@ -3647,7 +3647,7 @@ static int mtk_stop(struct net_device *d
- 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
- 
- 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
--	mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+	mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- 	napi_disable(&eth->tx_napi);
- 	napi_disable(&eth->rx_napi);
- 
-@@ -4126,9 +4126,9 @@ static int mtk_hw_init(struct mtk_eth *e
- 
- 	/* FE int grouping */
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
--	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+	mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
- 
- 	if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5305,11 +5305,15 @@ static const struct mtk_soc_data mt2701_
- 	.required_clks = MT7623_CLKS_BITMAP,
- 	.required_pctl = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5325,11 +5329,15 @@ static const struct mtk_soc_data mt7621_
- 	.offload_version = 1,
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5347,11 +5355,15 @@ static const struct mtk_soc_data mt7622_
- 	.hash_offset = 2,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5368,11 +5380,15 @@ static const struct mtk_soc_data mt7623_
- 	.hash_offset = 2,
- 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- 	.disable_pll_modes = true,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5387,11 +5403,15 @@ static const struct mtk_soc_data mt7629_
- 	.required_pctl = false,
- 	.has_accounting = true,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
-@@ -5409,11 +5429,15 @@ static const struct mtk_soc_data mt7981_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5431,11 +5455,15 @@ static const struct mtk_soc_data mt7986_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5453,11 +5481,15 @@ static const struct mtk_soc_data mt7988_
- 	.hash_offset = 4,
- 	.has_accounting = true,
- 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma_v2),
--		.rxd_size = sizeof(struct mtk_rx_dma_v2),
--		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma_v2),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+		.dma_len_offset = 8,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma_v2),
-+		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.dma_l4_valid = RX_DMA_L4_VALID_V2,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- 		.dma_len_offset = 8,
- 	},
-@@ -5470,11 +5502,15 @@ static const struct mtk_soc_data rt5350_
- 	.required_clks = MT7628_CLKS_BITMAP,
- 	.required_pctl = false,
- 	.version = 1,
--	.txrx = {
--		.txd_size = sizeof(struct mtk_tx_dma),
--		.rxd_size = sizeof(struct mtk_rx_dma),
--		.rx_irq_done_mask = MTK_RX_DONE_INT,
--		.rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+	.tx = {
-+		.desc_size = sizeof(struct mtk_tx_dma),
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
-+	},
-+	.rx = {
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
-+		.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- 		.dma_max_len = MTK_TX_DMA_BUF_LEN,
- 		.dma_len_offset = 16,
- 	},
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -327,8 +327,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU	BIT(31)
- #define TX_DMA_LS0		BIT(30)
--#define TX_DMA_PLEN0(x)		(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x)		(((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x)		((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC		BIT(14)
- #define TX_DMA_PQID		GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
-@@ -348,8 +348,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE		BIT(31)
- #define RX_DMA_LSO		BIT(30)
--#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG		BIT(15)
- #define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
-  * @foe_entry_size		Foe table entry size.
-  * @has_accounting		Bool indicating support for accounting of
-  *				offloaded flows.
-- * @txd_size			Tx DMA descriptor size.
-- * @rxd_size			Rx DMA descriptor size.
-- * @rx_irq_done_mask		Rx irq done register mask.
-- * @rx_dma_l4_valid		Rx DMA valid register mask.
-+ * @desc_size			Tx/Rx DMA descriptor size.
-+ * @irq_done_mask		Rx irq done register mask.
-+ * @dma_l4_valid		Rx DMA valid register mask.
-  * @dma_max_len			Max DMA tx/rx buffer length.
-  * @dma_len_offset		Tx/Rx DMA length field offset.
-  */
-@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
- 	bool		has_accounting;
- 	bool		disable_pll_modes;
- 	struct {
--		u32	txd_size;
--		u32	rxd_size;
--		u32	rx_irq_done_mask;
--		u32	rx_dma_l4_valid;
-+		u32	desc_size;
- 		u32	dma_max_len;
- 		u32	dma_len_offset;
--	} txrx;
-+	} tx;
-+	struct {
-+		u32	desc_size;
-+		u32	irq_done_mask;
-+		u32	dma_l4_valid;
-+		u32	dma_max_len;
-+		u32	dma_len_offset;
-+	} rx;
- };
- 
- #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
diff --git a/target/linux/mediatek/patches-6.6/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-6.6/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
deleted file mode 100644
index 6b84f70110..0000000000
--- a/target/linux/mediatek/patches-6.6/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -113,16 +113,16 @@ static const struct mtk_reg_map mt7986_r
- 	.tx_irq_mask		= 0x461c,
- 	.tx_irq_status		= 0x4618,
- 	.pdma = {
--		.rx_ptr		= 0x6100,
--		.rx_cnt_cfg	= 0x6104,
--		.pcrx_ptr	= 0x6108,
--		.glo_cfg	= 0x6204,
--		.rst_idx	= 0x6208,
--		.delay_irq	= 0x620c,
--		.irq_status	= 0x6220,
--		.irq_mask	= 0x6228,
--		.adma_rx_dbg0	= 0x6238,
--		.int_grp	= 0x6250,
-+		.rx_ptr		= 0x4100,
-+		.rx_cnt_cfg	= 0x4104,
-+		.pcrx_ptr	= 0x4108,
-+		.glo_cfg	= 0x4204,
-+		.rst_idx	= 0x4208,
-+		.delay_irq	= 0x420c,
-+		.irq_status	= 0x4220,
-+		.irq_mask	= 0x4228,
-+		.adma_rx_dbg0	= 0x4238,
-+		.int_grp	= 0x4250,
- 	},
- 	.qdma = {
- 		.qtx_cfg	= 0x4400,
-@@ -1249,7 +1249,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- 	}
-@@ -2201,7 +2201,7 @@ static int mtk_poll_rx(struct napi_struc
- 			break;
- 
- 		/* find out which mac the packet come from. values start at 1 */
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
- 
- 			switch (val) {
-@@ -2313,7 +2313,7 @@ static int mtk_poll_rx(struct napi_struc
- 		skb->dev = netdev;
- 		bytes += skb->len;
- 
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- 			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2863,7 +2863,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- 
- 		rxd->rxd3 = 0;
- 		rxd->rxd4 = 0;
--		if (mtk_is_netsys_v2_or_greater(eth)) {
-+		if (mtk_is_netsys_v3_or_greater(eth)) {
- 			rxd->rxd5 = 0;
- 			rxd->rxd6 = 0;
- 			rxd->rxd7 = 0;
-@@ -4072,7 +4072,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 	else
- 		mtk_hw_reset(eth);
- 
--	if (mtk_is_netsys_v2_or_greater(eth)) {
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
- 		/* Set FE to PDMAv2 if necessary */
- 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
- 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5435,11 +5435,11 @@ static const struct mtk_soc_data mt7981_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
-@@ -5461,11 +5461,11 @@ static const struct mtk_soc_data mt7986_
- 		.dma_len_offset = 8,
- 	},
- 	.rx = {
--		.desc_size = sizeof(struct mtk_rx_dma_v2),
--		.irq_done_mask = MTK_RX_DONE_INT_V2,
-+		.desc_size = sizeof(struct mtk_rx_dma),
-+		.irq_done_mask = MTK_RX_DONE_INT,
- 		.dma_l4_valid = RX_DMA_L4_VALID_V2,
--		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
--		.dma_len_offset = 8,
-+		.dma_max_len = MTK_TX_DMA_BUF_LEN,
-+		.dma_len_offset = 16,
- 	},
- };
- 
diff --git a/target/linux/mediatek/patches-6.6/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/target/linux/mediatek/patches-6.6/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
deleted file mode 100644
index 9974073d25..0000000000
--- a/target/linux/mediatek/patches-6.6/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1072,13 +1072,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+	mtk_wed_dma_disable(dev);
- 	mtk_wed_set_ext_int(dev, false);
- 
- 	wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- 	wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
--	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- 
- 	if (!mtk_wed_get_rx_capa(dev))
- 		return;
-@@ -1091,7 +1091,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- 	mtk_wed_stop(dev);
--	mtk_wed_dma_disable(dev);
- 
- 	wed_clr(dev, MTK_WED_CTRL,
- 		MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2622,9 +2621,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
--	if (!dev->running)
--		return;
--
- 	mtk_wed_set_ext_int(dev, !!mask);
- 	wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
diff --git a/target/linux/mpc85xx/base-files/etc/board.d/01_leds b/target/linux/mpc85xx/base-files/etc/board.d/01_leds
index 7e1d379efe..6b4faf7697 100644
--- a/target/linux/mpc85xx/base-files/etc/board.d/01_leds
+++ b/target/linux/mpc85xx/base-files/etc/board.d/01_leds
@@ -16,6 +16,9 @@ extreme-networks,ws-ap3825i)
 	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
 	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth0"
 	;;
+hpe,msm460)
+	ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
+	;;
 esac
 
 board_config_flush
diff --git a/target/linux/mpc85xx/base-files/etc/board.d/02_network b/target/linux/mpc85xx/base-files/etc/board.d/02_network
index 41859362b5..caf00ef414 100644
--- a/target/linux/mpc85xx/base-files/etc/board.d/02_network
+++ b/target/linux/mpc85xx/base-files/etc/board.d/02_network
@@ -16,6 +16,9 @@ aerohive,hiveap-330|\
 enterasys,ws-ap3715i)
 	ucidef_set_interfaces_lan_wan "eth1" "eth0"
 	;;
+hpe,msm460)
+	ucidef_set_interface_lan "eth0"
+	;;	
 ocedo,panda)
 	ucidef_set_interface_wan "eth1"
 	ucidef_add_switch "switch0" \
diff --git a/target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac b/target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
index 20ad8eb44f..0e27dfb8cc 100644
--- a/target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
+++ b/target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac
@@ -20,6 +20,11 @@ enterasys,ws-ap3710i|\
 extreme-networks,ws-ap3825i)
 	mtd_get_mac_ascii cfg2 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress
 	;;
+hpe,msm460)
+	wifi_mac=$(mtd_get_mac_binary colubris-bid 0x1f9bd)
+	[ "$PHYNBR" -eq 0 ] && echo "$wifi_mac" > /sys${DEVPATH}/macaddress
+	[ "$PHYNBR" -eq 1 ] && echo "$(macaddr_add $wifi_mac 16)" > /sys${DEVPATH}/macaddress
+	;;
 ocedo,panda)
 	mtd_get_mac_ascii uboot-env0 wmac$(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress
 	;;
diff --git a/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
index 226b40a906..5d111676ae 100755
--- a/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
@@ -13,6 +13,7 @@ platform_do_upgrade() {
 	local board=$(board_name)
 
 	case "$board" in
+	hpe,msm460|\
 	ocedo,panda|\
 	sophos,red-15w-rev1|\
 	watchguard,firebox-t10)
diff --git a/target/linux/mpc85xx/config-6.1 b/target/linux/mpc85xx/config-6.1
index c3e0414a78..c017422714 100644
--- a/target/linux/mpc85xx/config-6.1
+++ b/target/linux/mpc85xx/config-6.1
@@ -150,6 +150,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_MSGR is not set
 CONFIG_MPIC_TIMER=y
 CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
 # CONFIG_MTD_CFI is not set
 CONFIG_MTD_NAND_CORE=y
 CONFIG_MTD_NAND_ECC=y
diff --git a/target/linux/mpc85xx/config-6.6 b/target/linux/mpc85xx/config-6.6
index 34ff126851..ef08a51979 100644
--- a/target/linux/mpc85xx/config-6.6
+++ b/target/linux/mpc85xx/config-6.6
@@ -158,6 +158,7 @@ CONFIG_MPIC=y
 # CONFIG_MPIC_MSGR is not set
 CONFIG_MPIC_TIMER=y
 CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
 # CONFIG_MTD_CFI is not set
 CONFIG_MTD_NAND_CORE=y
 CONFIG_MTD_NAND_ECC=y
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/msm460.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/msm460.dts
new file mode 100644
index 0000000000..46f8e514c9
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/msm460.dts
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "Hewlett-Packard MSM460";
+	compatible = "hpe,msm460";
+
+	aliases {
+		led-boot = &system_green;
+		led-failsafe = &system_green;
+		led-running = &system_green;
+		led-upgrade = &system_green;
+		label-mac-device = &enet0;
+	};
+
+	chosen {
+		/* Needed for initramfs */
+		bootargs-override = "console=ttyS0,115200 ubi.mtd=5,2048";
+		stdout-path = &serial0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+		nand@1,0 {
+			compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+			reg = <0x1 0x0 0x40000>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0xc0000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				partition@c0000 {
+					reg = <0xc0000 0x40000>;
+					label = "colubris-bid";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_1f822: macaddr@1f822 {
+							/* ETH */
+							compatible = "mac-base";
+							reg = <0x1f822 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+
+						macaddr_hwinfo_1f9bd: macaddr@1f9bd {
+							/* WLAN */
+							compatible = "mac-base";
+							reg = <0x1f9bd 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				/* uenv{0,1} and ubi occupy kernel and slash partitions */
+
+				partition@100000 {
+					reg = <0x100000 0x80000>;
+					label = "uboot-env0";
+				};
+
+				partition@180000 {
+					reg = <0x180000 0x80000>;
+					label = "uboot-env1";
+				};
+
+				partition@200000 {
+					reg = <0x200000 0x300000>;
+					label = "reserved";
+				};
+
+				partition@500000 {
+					reg = <0x500000 0x5f00000>;
+					label = "ubi";
+				};
+
+				partition@6500000 {
+					reg = <0x6500000 0x400000>;
+					label = "pool";
+					read-only;
+				};
+
+				partition@6900000 {
+					reg = <0x6900000 0x15e0000>;
+					label = "flash";
+					read-only;
+				};
+
+				partition@7ee0000 {
+					reg = <0x7ee0000 0x20000>;
+					label = "pf";
+					read-only;
+				};
+
+				/* BBT is at the end of the flash - 100000@7f00000 */
+			};
+		};
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		i2c@3000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				reg = <0x0>;
+				reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+				reset-assert-us = <10000>;
+				reset-deassert-us = <10000>;
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			phy-handle = <&phy0>;
+			nvmem-cells = <&macaddr_hwinfo_1f822 0>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		usb@22000 {
+			status = "disabled";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+		reg = <0 0xffe09000 0 0x1000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0 0xffe0a000 0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system_green: power {
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			default-state = "on";
+		};
+
+		lan {
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+		};
+
+		radio1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <1>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		radio2 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+			function-enumerator = <2>;
+			linux,default-trigger = "phy1tpt";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset-btn";
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts
index 72b8f7a9d6..4068bdb51e 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts
@@ -9,6 +9,8 @@
 	compatible = "enterasys,ws-ap3710i";
 
 	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet2;
 		led-boot = &led_power_green;
 		led-failsafe = &led_power_red;
 		led-running = &led_power_green;
@@ -16,6 +18,11 @@
 		label-mac-device = &enet0;
 	};
 
+	chosen {
+		bootargs-override = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
 	memory {
 		device_type = "memory";
 	};
@@ -74,7 +81,7 @@
 				#size-cells = <1>;
 
 				partition@0 {
-					compatible = "denx,fit";
+					compatible = "denx,uimage";
 					reg = <0x0 0x1d80000>;
 					label = "firmware";
 				};
@@ -145,6 +152,13 @@
 		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 		reg = <0 0xffe09000 0 0x1000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+			      0x00 0x100000 0x42000000 0x00 0x00 0x00
+			      0x00 0x00 0x10000000>;
+
 		pcie@0 {
 			ranges = <0x2000000 0x0 0xa0000000
 				  0x2000000 0x0 0xa0000000
@@ -160,6 +174,13 @@
 		reg = <0 0xffe0a000 0 0x1000>;
 		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+		/* Filled by U-Boot */
+		bus-range = <0x00 0x01>;
+		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+			      0xffe00000 0x00 0x100000 0x42000000
+			      0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
 		pcie@0 {
 			ranges = <0x2000000 0x0 0x80000000
 				  0x2000000 0x0 0x80000000
@@ -174,6 +195,87 @@
 };
 /include/ "fsl/p1020si-post.dtsi"
 
+/ {
+	cpus {
+		PowerPC,P1020@0 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff280>;
+			status = "okay";
+			enable-method = "spin-table";
+		};
+
+		PowerPC,P1020@1 {
+			bus-frequency = <399999996>;
+			timebase-frequency = <50000000>;
+			clock-frequency = <799999992>;
+			d-cache-block-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			i-cache-block-size = <0x20>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x80>;
+			cpu-release-addr = <0x0 0x0ffff2a0>;
+			status = "disabled";
+			enable-method = "spin-table";
+		};
+	};
+
+	memory {
+		reg = <0x0 0x0 0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpu1-bootpage@ff00000 {
+			/* Reserve upper 1 MB for second-core-bootpage */
+			reg = <0x0 0xff00000 0x0 0x100000>;
+		};
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <399999996>;
+
+		serial@4600 {
+			clock-frequency = <399999996>;
+		};
+
+		serial@4500 {
+			clock-frequency = <399999996>;
+		};
+
+		pic@40000 {
+			clock-frequency = <399999996>;
+		};
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <24999999>;
+	};
+};
+
+&enet0 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
+&enet2 {
+	rx-stash-idx = <0x00>;
+	rx-stash-len = <0x60>;
+	bd-stash;
+};
+
 /*
  * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
  * aliases to determine PCI domain numbers, drop aliases so as not to
diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/msm460.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/msm460.c
new file mode 100644
index 0000000000..a4f547d313
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/msm460.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * HPE MSM460 Board Setup
+ *
+ * Copyright (C) 2022 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ *   mpc85xx_rdb.c:
+ *      MPC85xx RDB Board Setup
+ *      Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init msm_pic_init(void)
+{
+	struct mpic *mpic;
+
+	mpic = mpic_alloc(NULL, 0,
+	  MPIC_BIG_ENDIAN |
+	  MPIC_SINGLE_DEST_CPU,
+	  0, 256, " OpenPIC  ");
+
+	BUG_ON(mpic == NULL);
+	mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init msm_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("msm_setup_arch()", 0);
+
+	mpc85xx_smp_init();
+
+	fsl_pci_assign_primary();
+
+	pr_info("MSM460 board from HPE\n");
+}
+
+machine_arch_initcall(msm, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init msm_probe(void)
+{
+	if (of_machine_is_compatible("hpe,msm460"))
+		return 1;
+	return 0;
+}
+
+define_machine(msm) {
+	.name			= "P1020 RDB",
+	.probe			= msm_probe,
+	.setup_arch		= msm_setup_arch,
+	.init_IRQ		= msm_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
+#endif
+	.get_irq		= mpic_get_irq,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+};
diff --git a/target/linux/mpc85xx/image/p1020.mk b/target/linux/mpc85xx/image/p1020.mk
index 26b8167553..e3902d23d6 100644
--- a/target/linux/mpc85xx/image/p1020.mk
+++ b/target/linux/mpc85xx/image/p1020.mk
@@ -67,7 +67,11 @@ define Device/enterasys_ws-ap3710i
   DEVICE_VENDOR := Enterasys
   DEVICE_MODEL := WS-AP3710i
   BLOCKSIZE := 128k
-  KERNEL = kernel-bin | lzma | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb
+  KERNEL_NAME := simpleImage.ws-ap3710i
+  KERNEL_ENTRY := 0x1500000
+  KERNEL_LOADADDR := 0x1500000
+  KERNEL = kernel-bin | uImage none
+  KERNEL_INITRAMFS := kernel-bin | uImage none
   IMAGES := sysupgrade.bin
   IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
 endef
@@ -87,6 +91,24 @@ define Device/extreme-networks_ws-ap3825i
 endef
 TARGET_DEVICES += extreme-networks_ws-ap3825i
 
+define Device/hpe_msm460
+  DEVICE_VENDOR := Hewlett-Packard
+  DEVICE_MODEL := MSM460
+  KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
+  KERNEL_NAME := zImage.la3000000
+  KERNEL_ENTRY := 0x3000000
+  KERNEL_LOADADDR := 0x3000000
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  SUBPAGESIZE := 2048
+  KERNEL_IN_UBI := 1
+  UBINIZE_OPTS := -E 5
+  IMAGES := factory.bin sysupgrade.bin
+  IMAGE/factory.bin := append-ubi
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += hpe_msm460
+
 define Device/ocedo_panda
   DEVICE_VENDOR := OCEDO
   DEVICE_MODEL := Panda
@@ -100,4 +122,3 @@ define Device/ocedo_panda
   IMAGE/fdt.bin := append-dtb
 endef
 TARGET_DEVICES += ocedo_panda
-
diff --git a/target/linux/mpc85xx/p1020/config-default b/target/linux/mpc85xx/p1020/config-default
index 573ff362f9..d1c0532582 100644
--- a/target/linux/mpc85xx/p1020/config-default
+++ b/target/linux/mpc85xx/p1020/config-default
@@ -12,6 +12,7 @@ CONFIG_GPIO_74X164=y
 CONFIG_HAVE_RCU_TABLE_FREE=y
 CONFIG_HIVEAP_330=y
 CONFIG_PANDA=y
+CONFIG_MSM460=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_LP55XX_COMMON=y
diff --git a/target/linux/mpc85xx/p1020/target.mk b/target/linux/mpc85xx/p1020/target.mk
index 5a5d0bf07d..498d8981a1 100644
--- a/target/linux/mpc85xx/p1020/target.mk
+++ b/target/linux/mpc85xx/p1020/target.mk
@@ -1,5 +1,5 @@
 BOARDNAME:=P1020
-KERNEL_IMAGES:=simpleImage.ws-ap3825i simpleImage.hiveap-330
+KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330 zImage.la3000000
 
 define Target/Description
 	Build firmware images for Freescale P1020 based boards.
diff --git a/target/linux/mpc85xx/patches-6.1/010-powerpc-add-compressed-zImage-for-mpc85xx.patch b/target/linux/mpc85xx/patches-6.1/010-powerpc-add-compressed-zImage-for-mpc85xx.patch
new file mode 100644
index 0000000000..16ef37bd78
--- /dev/null
+++ b/target/linux/mpc85xx/patches-6.1/010-powerpc-add-compressed-zImage-for-mpc85xx.patch
@@ -0,0 +1,61 @@
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper  | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -175,6 +175,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot
+ src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
+ src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
+ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
++src-plat-$(CONFIG_PPC_ZIMAGE_LA3000000) += fixed-head.S
+ src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+@@ -345,6 +346,7 @@ image-$(CONFIG_MPC836x_MDS)		+= cuImage.
+ image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
+ 
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-$(CONFIG_PPC_ZIMAGE_LA3000000)   += zImage.la3000000
+ image-$(CONFIG_MPC8540_ADS)		+= cuImage.mpc8540ads
+ image-$(CONFIG_MPC8560_ADS)		+= cuImage.mpc8560ads
+ image-$(CONFIG_MPC85xx_CDS)		+= cuImage.mpc8541cds \
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -254,6 +254,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+ 
+ case "$platform" in
++la3000000)
++    binary=y
++    platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++    link_address='0x3000000'
++    ;;
+ of)
+     platformo="$object/of.o $object/epapr.o"
+     make_space=n
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -74,6 +74,10 @@ config NMI_IPI
+ 	depends on SMP && (DEBUGGER || KEXEC_CORE || HARDLOCKUP_DETECTOR)
+ 	default y
+ 
++config PPC_ZIMAGE_LA3000000
++       bool
++       default n
++
+ config PPC_WATCHDOG
+ 	bool
+ 	depends on HARDLOCKUP_DETECTOR
diff --git a/target/linux/mpc85xx/patches-6.1/100-powerpc-85xx-tl-wdr4900-v1-support.patch b/target/linux/mpc85xx/patches-6.1/100-powerpc-85xx-tl-wdr4900-v1-support.patch
index a7253a9794..5f8d84ccee 100644
--- a/target/linux/mpc85xx/patches-6.1/100-powerpc-85xx-tl-wdr4900-v1-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/100-powerpc-85xx-tl-wdr4900-v1-support.patch
@@ -19,7 +19,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
 
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -179,6 +179,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
@@ -27,7 +27,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
  
-@@ -359,7 +360,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+@@ -361,7 +362,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
@@ -38,7 +38,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
  
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,11 @@ adder875-redboot)
+@@ -346,6 +346,11 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
diff --git a/target/linux/mpc85xx/patches-6.1/101-powerpc-85xx-hiveap-330-support.patch b/target/linux/mpc85xx/patches-6.1/101-powerpc-85xx-hiveap-330-support.patch
index e8b6632f2b..18466216c0 100644
--- a/target/linux/mpc85xx/patches-6.1/101-powerpc-85xx-hiveap-330-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/101-powerpc-85xx-hiveap-330-support.patch
@@ -30,7 +30,7 @@
  obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -179,6 +179,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
@@ -38,7 +38,7 @@
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -360,6 +361,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+@@ -362,6 +363,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
@@ -48,7 +48,7 @@
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,7 @@ adder875-redboot)
+@@ -346,6 +346,7 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
diff --git a/target/linux/mpc85xx/patches-6.1/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-6.1/102-powerpc-add-cmdline-override.patch
index b83e5f86d2..2ac10eae8e 100644
--- a/target/linux/mpc85xx/patches-6.1/102-powerpc-add-cmdline-override.patch
+++ b/target/linux/mpc85xx/patches-6.1/102-powerpc-add-cmdline-override.patch
@@ -1,6 +1,6 @@
 --- a/arch/powerpc/Kconfig
 +++ b/arch/powerpc/Kconfig
-@@ -954,6 +954,14 @@ config CMDLINE_FORCE
+@@ -958,6 +958,14 @@ config CMDLINE_FORCE
  
  endchoice
  
diff --git a/target/linux/mpc85xx/patches-6.1/106-powerpc-85xx-ws-ap3710i-support.patch b/target/linux/mpc85xx/patches-6.1/106-powerpc-85xx-ws-ap3710i-support.patch
index 5ac3f2f2d9..742fe7c2c0 100644
--- a/target/linux/mpc85xx/patches-6.1/106-powerpc-85xx-ws-ap3710i-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/106-powerpc-85xx-ws-ap3710i-support.patch
@@ -28,3 +28,33 @@
  obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
  obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
  obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -365,6 +366,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -347,7 +347,8 @@ adder875-redboot)
+     binary=y
+     ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y
diff --git a/target/linux/mpc85xx/patches-6.1/107-powerpc-85xx-add-ws-ap3825i-support.patch b/target/linux/mpc85xx/patches-6.1/107-powerpc-85xx-add-ws-ap3825i-support.patch
index 63e7e46bbc..346001271b 100644
--- a/target/linux/mpc85xx/patches-6.1/107-powerpc-85xx-add-ws-ap3825i-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/107-powerpc-85xx-add-ws-ap3825i-support.patch
@@ -37,29 +37,31 @@ WS-AP3825i AP.
  obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
  src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
 +src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
  
-@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
- image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+@@ -367,6 +368,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 +image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
  # Board ports in arch/powerpc/platform/86xx/Kconfig
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
  
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
-     binary=y
+@@ -348,7 +348,8 @@ adder875-redboot)
      ;;
  simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
      platformo="$object/fixed-head.o $object/simpleboot.o"
      link_address='0x1500000'
+     binary=y
diff --git a/target/linux/mpc85xx/patches-6.1/109-powerpc-85xx-add-ws-ap3715i-support.patch b/target/linux/mpc85xx/patches-6.1/109-powerpc-85xx-add-ws-ap3715i-support.patch
index f8e33ae637..a9f7079866 100644
--- a/target/linux/mpc85xx/patches-6.1/109-powerpc-85xx-add-ws-ap3715i-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/109-powerpc-85xx-add-ws-ap3715i-support.patch
@@ -30,21 +30,19 @@
  obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -364,6 +364,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
- image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -368,6 +369,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 +image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
  image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
  # Board ports in arch/powerpc/platform/86xx/Kconfig
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
-     binary=y
-     ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
-     platformo="$object/fixed-head.o $object/simpleboot.o"
diff --git a/target/linux/mpc85xx/patches-6.1/110-powerpc-85xx-br200-wp-support.patch b/target/linux/mpc85xx/patches-6.1/110-powerpc-85xx-br200-wp-support.patch
index b063b3dab7..a58d12aef2 100644
--- a/target/linux/mpc85xx/patches-6.1/110-powerpc-85xx-br200-wp-support.patch
+++ b/target/linux/mpc85xx/patches-6.1/110-powerpc-85xx-br200-wp-support.patch
@@ -29,29 +29,29 @@
  obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -179,6 +179,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -180,6 +180,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
 +src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -362,6 +363,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -366,6 +367,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
 +image-$(CONFIG_BR200_WP)		+= simpleImage.br200-wp
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,7 @@ adder875-redboot)
+@@ -346,6 +346,7 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
 +simpleboot-br200-wp|\
  simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
diff --git a/target/linux/mpc85xx/patches-6.1/111-powerpc-85xx-hpe-msm-support.patch b/target/linux/mpc85xx/patches-6.1/111-powerpc-85xx-hpe-msm-support.patch
new file mode 100644
index 0000000000..4b9c6f8219
--- /dev/null
+++ b/target/linux/mpc85xx/patches-6.1/111-powerpc-85xx-hpe-msm-support.patch
@@ -0,0 +1,31 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,18 @@ config FIREBOX_T10
+ 	  This board is a VPN Gateway-Router with a
+ 	  Freescale P1010 SoC.
+ 
++config MSM460
++	bool "HPE MSM460"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	select PPC_ZIMAGE_LA3000000
++	help
++	  This option enables support for the HPE MSM460 board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.
+ obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460)      += msm460.o
+ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
diff --git a/target/linux/mpc85xx/patches-6.1/900-powerpc-bootwrapper-disable-uImage-generation.patch b/target/linux/mpc85xx/patches-6.1/900-powerpc-bootwrapper-disable-uImage-generation.patch
index 648aa0421d..a997a1b9b7 100644
--- a/target/linux/mpc85xx/patches-6.1/900-powerpc-bootwrapper-disable-uImage-generation.patch
+++ b/target/linux/mpc85xx/patches-6.1/900-powerpc-bootwrapper-disable-uImage-generation.patch
@@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -291,7 +291,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
+@@ -294,7 +294,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
  image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
  image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
  image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
@@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
  
  #
-@@ -427,15 +426,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -432,15 +431,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
  $(obj)/vmlinux.strip: vmlinux
  	$(STRIP) -s -R .comment $< -o $@
  
diff --git a/target/linux/mpc85xx/patches-6.6/010-powerpc-add-compressed-zImage-for-mpc85xx.patch b/target/linux/mpc85xx/patches-6.6/010-powerpc-add-compressed-zImage-for-mpc85xx.patch
new file mode 100644
index 0000000000..eeb501dfeb
--- /dev/null
+++ b/target/linux/mpc85xx/patches-6.6/010-powerpc-add-compressed-zImage-for-mpc85xx.patch
@@ -0,0 +1,61 @@
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper  | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -177,6 +177,7 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot
+ src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
+ src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
+ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
++src-plat-$(CONFIG_PPC_ZIMAGE_LA3000000) += fixed-head.S
+ src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
+ src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
+ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
+@@ -342,6 +343,7 @@ image-$(CONFIG_MPC834x_ITX)		+= cuImage.
+ image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
+ 
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-$(CONFIG_PPC_ZIMAGE_LA3000000)	+= zImage.la3000000
+ image-$(CONFIG_MPC85xx_MDS)		+= cuImage.mpc8568mds
+ image-$(CONFIG_MPC85xx_DS)		+= cuImage.mpc8544ds \
+ 					   cuImage.mpc8572ds
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -258,6 +258,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+ 
+ case "$platform" in
++la3000000)
++    binary=y
++    platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++    link_address='0x3000000'
++    ;;
+ of)
+     platformo="$object/of.o $object/epapr.o"
+     make_space=n
+--- a/arch/powerpc/Kconfig
++++ b/arch/powerpc/Kconfig
+@@ -88,6 +88,10 @@ config NMI_IPI
+ 	depends on SMP && (DEBUGGER || KEXEC_CORE || HARDLOCKUP_DETECTOR)
+ 	default y
+ 
++config PPC_ZIMAGE_LA3000000
++       bool
++       default n
++
+ config PPC_WATCHDOG
+ 	bool
+ 	depends on HARDLOCKUP_DETECTOR_ARCH
diff --git a/target/linux/mpc85xx/patches-6.6/100-powerpc-85xx-tl-wdr4900-v1-support.patch b/target/linux/mpc85xx/patches-6.6/100-powerpc-85xx-tl-wdr4900-v1-support.patch
index 800341c6e1..2f8d4d4e3d 100644
--- a/target/linux/mpc85xx/patches-6.6/100-powerpc-85xx-tl-wdr4900-v1-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/100-powerpc-85xx-tl-wdr4900-v1-support.patch
@@ -19,7 +19,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
 
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
@@ -27,7 +27,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
  
-@@ -351,7 +352,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+@@ -353,7 +354,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
@@ -38,7 +38,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
  
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,11 @@ adder875-redboot)
+@@ -350,6 +350,11 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
diff --git a/target/linux/mpc85xx/patches-6.6/101-powerpc-85xx-hiveap-330-support.patch b/target/linux/mpc85xx/patches-6.6/101-powerpc-85xx-hiveap-330-support.patch
index 952df5e8a6..85de47bfb5 100644
--- a/target/linux/mpc85xx/patches-6.6/101-powerpc-85xx-hiveap-330-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/101-powerpc-85xx-hiveap-330-support.patch
@@ -30,7 +30,7 @@
  obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o $(obj8259-y)
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
@@ -38,7 +38,7 @@
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -352,6 +353,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+@@ -354,6 +355,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
@@ -48,7 +48,7 @@
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,7 @@ adder875-redboot)
+@@ -350,6 +350,7 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
diff --git a/target/linux/mpc85xx/patches-6.6/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-6.6/102-powerpc-add-cmdline-override.patch
index 17aee6dafe..1aa7c3dbd3 100644
--- a/target/linux/mpc85xx/patches-6.6/102-powerpc-add-cmdline-override.patch
+++ b/target/linux/mpc85xx/patches-6.6/102-powerpc-add-cmdline-override.patch
@@ -1,6 +1,6 @@
 --- a/arch/powerpc/Kconfig
 +++ b/arch/powerpc/Kconfig
-@@ -1005,6 +1005,14 @@ config CMDLINE_FORCE
+@@ -1009,6 +1009,14 @@ config CMDLINE_FORCE
  
  endchoice
  
diff --git a/target/linux/mpc85xx/patches-6.6/106-powerpc-85xx-ws-ap3710i-support.patch b/target/linux/mpc85xx/patches-6.6/106-powerpc-85xx-ws-ap3710i-support.patch
index 469b696833..983772131c 100644
--- a/target/linux/mpc85xx/patches-6.6/106-powerpc-85xx-ws-ap3710i-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/106-powerpc-85xx-ws-ap3710i-support.patch
@@ -28,3 +28,33 @@
  obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
  obj-$(CONFIG_FB_FSL_DIU)	+= t1042rdb_diu.o
  obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+ 
+@@ -357,6 +358,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
+ image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
+ 
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -351,7 +351,8 @@ adder875-redboot)
+     binary=y
+     ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+     platformo="$object/fixed-head.o $object/simpleboot.o"
+     link_address='0x1500000'
+     binary=y
diff --git a/target/linux/mpc85xx/patches-6.6/107-powerpc-85xx-add-ws-ap3825i-support.patch b/target/linux/mpc85xx/patches-6.6/107-powerpc-85xx-add-ws-ap3825i-support.patch
index 8a42064570..29e3b22133 100644
--- a/target/linux/mpc85xx/patches-6.6/107-powerpc-85xx-add-ws-ap3825i-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/107-powerpc-85xx-add-ws-ap3825i-support.patch
@@ -37,29 +37,31 @@ WS-AP3825i AP.
  obj-$(CONFIG_RED_15W_REV1)	+= red15w_rev1.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -183,6 +183,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -185,6 +185,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
  src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
 +src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
  
  src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
  
-@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
- image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+@@ -359,6 +360,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 +image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
  # Board ports in arch/powerpc/platform/86xx/Kconfig
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
  
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
-     binary=y
+@@ -352,7 +352,8 @@ adder875-redboot)
      ;;
  simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
      platformo="$object/fixed-head.o $object/simpleboot.o"
      link_address='0x1500000'
+     binary=y
diff --git a/target/linux/mpc85xx/patches-6.6/109-powerpc-85xx-add-ws-ap3715i-support.patch b/target/linux/mpc85xx/patches-6.6/109-powerpc-85xx-add-ws-ap3715i-support.patch
index d6c59e8f72..aa1126569f 100644
--- a/target/linux/mpc85xx/patches-6.6/109-powerpc-85xx-add-ws-ap3715i-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/109-powerpc-85xx-add-ws-ap3715i-support.patch
@@ -30,21 +30,19 @@
  obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -356,6 +356,7 @@ image-$(CONFIG_TQM8560)			+= cuImage.tqm
- image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
+@@ -185,6 +185,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+ 
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -360,6 +361,7 @@ image-$(CONFIG_KSI8560)			+= cuImage.ksi
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 +image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
  image-$(CONFIG_WS_AP3825I)		+= simpleImage.ws-ap3825i
  # Board ports in arch/powerpc/platform/86xx/Kconfig
  image-$(CONFIG_MVME7100)                += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
-     binary=y
-     ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
-     platformo="$object/fixed-head.o $object/simpleboot.o"
diff --git a/target/linux/mpc85xx/patches-6.6/110-powerpc-85xx-br200-wp-support.patch b/target/linux/mpc85xx/patches-6.6/110-powerpc-85xx-br200-wp-support.patch
index f3ec26ec99..28a2bed017 100644
--- a/target/linux/mpc85xx/patches-6.6/110-powerpc-85xx-br200-wp-support.patch
+++ b/target/linux/mpc85xx/patches-6.6/110-powerpc-85xx-br200-wp-support.patch
@@ -29,29 +29,29 @@
  obj8259-$(CONFIG_PPC_I8259)   += mpc85xx_8259.o
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie
  src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
  src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
  src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
 +src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
  src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -354,6 +355,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -358,6 +359,7 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm
  image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
  image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
  image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
 +image-$(CONFIG_BR200_WP)		+= simpleImage.br200-wp
  image-$(CONFIG_HIVEAP_330)		+= simpleImage.hiveap-330
  image-$(CONFIG_TL_WDR4900_V1)		+= simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I)		+= simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I)		+= simpleImage.ws-ap3710i
 --- a/arch/powerpc/boot/wrapper
 +++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,7 @@ adder875-redboot)
+@@ -350,6 +350,7 @@ adder875-redboot)
      platformo="$object/fixed-head.o $object/redboot-8xx.o"
      binary=y
      ;;
 +simpleboot-br200-wp|\
  simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
diff --git a/target/linux/mpc85xx/patches-6.6/111-powerpc-85xx-hpe-msm-support.patch b/target/linux/mpc85xx/patches-6.6/111-powerpc-85xx-hpe-msm-support.patch
new file mode 100644
index 0000000000..1d1fb4f54f
--- /dev/null
+++ b/target/linux/mpc85xx/patches-6.6/111-powerpc-85xx-hpe-msm-support.patch
@@ -0,0 +1,31 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,18 @@ config FIREBOX_T10
+ 	  This board is a VPN Gateway-Router with a
+ 	  Freescale P1010 SoC.
+ 
++config MSM460
++	bool "HPE MSM460"
++	select DEFAULT_UIMAGE
++	select ARCH_REQUIRE_GPIOLIB
++	select GPIO_MPC8XXX
++	select PPC_ZIMAGE_LA3000000
++	help
++	  This option enables support for the HPE MSM460 board.
++
++	  This board is a Concurrent Dual-Band wireless access point with a
++	  Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ 	bool "Freescale MPC8540 ADS"
+ 	select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -19,6 +19,7 @@ obj8259-$(CONFIG_PPC_I8259)   += mpc85xx
+ obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o $(obj8259-y)
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460)      += msm460.o
+ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
+ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
diff --git a/target/linux/mpc85xx/patches-6.6/900-powerpc-bootwrapper-disable-uImage-generation.patch b/target/linux/mpc85xx/patches-6.6/900-powerpc-bootwrapper-disable-uImage-generation.patch
index d5bef03387..5ffc32e9de 100644
--- a/target/linux/mpc85xx/patches-6.6/900-powerpc-bootwrapper-disable-uImage-generation.patch
+++ b/target/linux/mpc85xx/patches-6.6/900-powerpc-bootwrapper-disable-uImage-generation.patch
@@ -16,7 +16,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
-@@ -293,7 +293,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
+@@ -296,7 +296,6 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
  image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
  image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
  image-$(CONFIG_PPC_HOLLY)		+= dtbImage.holly
@@ -24,7 +24,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  image-$(CONFIG_EPAPR_BOOT)		+= zImage.epapr
  
  #
-@@ -418,15 +417,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -423,15 +422,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
  $(obj)/vmlinux.strip: vmlinux
  	$(STRIP) -s -R .comment $< -o $@
  
diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile
index 26bd4d4240..b279d818ed 100644
--- a/target/linux/mvebu/Makefile
+++ b/target/linux/mvebu/Makefile
@@ -9,8 +9,7 @@ BOARDNAME:=Marvell EBU Armada
 FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz
 SUBTARGETS:=cortexa9 cortexa53 cortexa72
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/mvebu/config-6.1 b/target/linux/mvebu/config-6.1
deleted file mode 100644
index 88e5fff4d9..0000000000
--- a/target/linux/mvebu/config-6.1
+++ /dev/null
@@ -1,447 +0,0 @@
-CONFIG_AHCI_MVEBU=y
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_IRQ=y
-CONFIG_ARMADA_370_XP_TIMER=y
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-CONFIG_ARMADA_38X_CLK=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_LEDS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_FEROCEON_L2 is not set
-CONFIG_CACHE_L2X0=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_MARVELL=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRYPTO_ESSIV=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MVEBU_UART0=y
-# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
-# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWBM=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_PXA is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_JBD2=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PCA963X=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-# CONFIG_MACH_ARMADA_375 is not set
-CONFIG_MACH_ARMADA_38X=y
-# CONFIG_MACH_ARMADA_39X is not set
-CONFIG_MACH_ARMADA_XP=y
-# CONFIG_MACH_DOVE is not set
-CONFIG_MACH_MVEBU_ANY=y
-CONFIG_MACH_MVEBU_V7=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MANGLE_BOOTARGS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_PXAV3=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVNETA_BM=y
-CONFIG_MVNETA_BM_ENABLE=y
-# CONFIG_MVPP2 is not set
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6XXX=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
-# CONFIG_PHY_MVEBU_A3700_UTMI is not set
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_38X=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PLAT_ORION=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ARMADA38X=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_MV=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SENSORS_PWM_FAN=y
-CONFIG_SENSORS_TMP421=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SFP=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_ARMADA_3700 is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ORION=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mvebu/cortexa53/config-6.1 b/target/linux/mvebu/cortexa53/config-6.1
deleted file mode 100644
index d8dd985365..0000000000
--- a/target/linux/mvebu/cortexa53/config-6.1
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=y
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PINCTRL_AC5=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TURRIS_MOX_RWTM=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa72/config-6.1 b/target/linux/mvebu/cortexa72/config-6.1
deleted file mode 100644
index 3c398dcd8f..0000000000
--- a/target/linux/mvebu/cortexa72/config-6.1
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CPU_CLK=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_8K_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CRC_CCITT=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
-CONFIG_LEDS_IS31FL319X=y
-CONFIG_MARVELL_10G_PHY=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_IEI_WT61P803_PUZZLE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_MVPP2=y
-CONFIG_MV_XOR_V2=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_LAYOUT_ONIE_TLV=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-# CONFIG_PCI_AARDVARK is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_UTMI=y
-CONFIG_PINCTRL_AC5=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
-CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network
index b9ac2bb1ae..680af1ce67 100644
--- a/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network
@@ -28,7 +28,11 @@ mvebu_setup_interfaces()
 	linksys,wrt32x)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
 		;;
-	fortinet,fg-50e)
+	fortinet,fg-50e|\
+	fortinet,fg-51e|\
+	fortinet,fg-52e|\
+	fortinet,fwf-50e-2r|\
+	fortinet,fwf-51e)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2"
 		;;
 	iij,sa-w2)
diff --git a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh
index 7f45aa8a91..a15823d8c6 100755
--- a/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh
@@ -53,7 +53,11 @@ platform_do_upgrade() {
 		legacy_sdcard_do_upgrade "$1"
 		;;
 	fortinet,fg-30e|\
-	fortinet,fg-50e)
+	fortinet,fg-50e|\
+	fortinet,fg-51e|\
+	fortinet,fg-52e|\
+	fortinet,fwf-50e-2r|\
+	fortinet,fwf-51e)
 		fortinet_do_upgrade "$1"
 		;;
 	iij,sa-w2)
diff --git a/target/linux/mvebu/cortexa9/config-6.1 b/target/linux/mvebu/cortexa9/config-6.1
deleted file mode 100644
index 7f825a806b..0000000000
--- a/target/linux/mvebu/cortexa9/config-6.1
+++ /dev/null
@@ -1,12 +0,0 @@
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_IRQSTACKS=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_MTD_SPLIT_SEIL_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_POWER_RESET_QNAP=y
-CONFIG_RTC_DRV_MV=y
-CONFIG_THREAD_INFO_IN_TASK=y
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
deleted file mode 100644
index 11be6a4028..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls220de.dts
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Buffalo LinkStation LS220DE
- *
- * Copyright (C) 2023 Daniel González Cabanelas <dgcbueu@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include "mvebu-linkstation-fan.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	model = "Buffalo LinkStation LS220DE";
-	compatible = "buffalo,ls220de", "marvell,armada370", "marvell,armada-370-xp";
-
-	aliases {
-		led-boot = &led_boot;
-		led-failsafe = &led_failsafe;
-		led-running = &led_power;
-		led-upgrade = &led_upgrade;
-	};
-
-	chosen {
-		bootargs = "earlycon";
-		stdout-path = "serial0:115200n8";
-		append-rootblock = "nullparameter="; /* override the bootloader args */
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x10000000>; /* 256 MB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
-	};
-
-	system_fan: gpio_fan {
-		gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
-			 &gpio0 14 GPIO_ACTIVE_HIGH>;
-		alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-
-		#cooling-cells = <2>;
-	};
-
-	thermal-zones {
-		hdd-thermal {
-			polling-delay = <20000>;
-			polling-delay-passive = <2000>;
-
-			thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
-
-			trips {
-				hdd_alert1: trip1 {
-					temperature = <34000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-				hdd_alert2: trip2 {
-					temperature = <40000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-				hdd_alert3: trip3 {
-					temperature = <45000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				hdd_hot {
-					temperature = <50000>;
-					hysteresis = <2000>;
-					type = "hot";
-				};
-				hdd_crit {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map1 {
-					trip = <&hdd_alert1>;
-					cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
-				};
-				map2 {
-					trip = <&hdd_alert2>;
-					cooling-device = <&system_fan 2 2>;
-				};
-				map3 {
-					trip = <&hdd_alert3>;
-					cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
-				};
-			};
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&pmx_buttons>;
-		pinctrl-names = "default";
-
-		power {
-			label = "Power Switch";
-			linux,code = <KEY_POWER>;
-			linux,input-type = <EV_SW>;
-			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-		};
-
-		function {
-			label = "Function Button";
-			linux,code = <KEY_CONFIG>;
-			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
-
-		indicator_red {
-			function = LED_FUNCTION_INDICATOR;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		led_power: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led_failsafe: power_red {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_upgrade: power_orange {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_AMBER>;
-			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_boot: indicator_white {
-			function = LED_FUNCTION_INDICATOR;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		};
-
-		hdd1_red {
-			function = LED_FUNCTION_DISK;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ata1";
-			function-enumerator = <1>;
-		};
-
-		hdd2_red {
-			function = LED_FUNCTION_DISK;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ata2";
-			function-enumerator = <2>;
-		};
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_hdd1 &pmx_power_hdd2>;
-		pinctrl-names = "default";
-
-		sata1_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "HDD1";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			startup-delay-us = <2000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		sata2_power: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "HDD2";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			startup-delay-us = <4000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&coherencyfab {
-	broken-idle;
-};
-
-&eth1 {
-	pinctrl-0 = <&ge1_rgmii_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "rgmii-id";
-};
-
-&mdio {
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-
-	ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
-		reg = <0>;
-		marvell,reg-init = <0x3 0x10 0xf000 0x091A>, /* LED function */
-				   <0x3 0x11 0x0000 0x4401>, /* LED polarity */
-				   <0x3 0x12 0x0000 0x4905>; /* LED timer */
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&nand_controller {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		label = "pxa3xx_nand-0";
-		nand-rb = <0>;
-		marvell,nand-keep-config;
-		nand-on-flash-bbt;
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ubi_kernel";
-				reg = <0x00000000 0x02000000>; /* 32 MiB */
-			};
-
-			partition@2000000 {
-				label = "ubi";
-				reg = <0x02000000 0x1df00000>; /* 479 MiB */
-			};
-		};
-	};
-};
-
-&sata {
-	nr-ports = <2>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hdd0_temp: sata-port@0 {
-		reg = <0>;
-		#thermal-sensor-cells = <0>;
-	};
-
-	hdd1_temp: sata-port@1 {
-		reg = <1>;
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-0 = <&spi0_pins2>;
-	pinctrl-names = "default";
-
-	spi-flash@0 {
-		compatible = "mxicy,mx25l8005", "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x00000 0xf0000>; /* 960 KiB*/
-				label = "u-boot";
-				read-only;
-			};
-			partition@f0000 {
-				reg = <0xf0000 0x10000>; /* 64 KiB */
-				label = "u-boot-env";
-			};
-		};
-	};
-};
-
-&pmsu {
-	pinctrl-0 = <&pmx_power_cpu>;
-	pinctrl-names = "default";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&pinctrl {
-	pmx_power_hdd2: pmx-power-hdd2 {
-		marvell,pins = "mpp2";
-		marvell,function = "gpio";
-	};
-
-	pmx_power_cpu: pmx-power-cpu {
-		marvell,pins = "mpp4";
-		marvell,function = "vdd";
-	};
-
-	pmx_power_hdd1: pmx-power-hdd1 {
-		marvell,pins = "mpp8";
-		marvell,function = "gpio";
-	};
-
-	pmx_fan_lock: pmx-fan-lock {
-		marvell,pins = "mpp10";
-		marvell,function = "gpio";
-	};
-
-	pmx_hdd_present: pmx-hdd-present {
-		marvell,pins = "mpp11", "mpp12";
-		marvell,function = "gpio";
-	};
-
-	pmx_fan_high: pmx-fan-high {
-		marvell,pins = "mpp13";
-		marvell,function = "gpio";
-	};
-
-	pmx_fan_low: pmx-fan-low {
-		marvell,pins = "mpp14";
-		marvell,function = "gpio";
-	};
-
-	pmx_buttons: pmx-buttons {
-		marvell,pins = "mpp15", "mpp16";
-		marvell,function = "gpio";
-	};
-
-	pmx_leds1: pmx-leds {
-		marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
-		marvell,function = "gpo";
-	};
-
-	pmx_leds2: pmx-leds {
-		marvell,pins = "mpp55", "mpp57", "mpp62";
-		marvell,function = "gpio";
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts
deleted file mode 100644
index 59400839a7..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts
+++ /dev/null
@@ -1,448 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Buffalo LinkStation LS421DE
- *
- * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include "mvebu-linkstation-fan.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-	model = "Buffalo LinkStation LS421DE";
-	compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp";
-
-	aliases {
-		led-boot = &led_boot;
-		led-failsafe = &led_failsafe;
-		led-running = &led_power;
-		led-upgrade = &led_upgrade;
-	};
-
-	chosen {
-		bootargs = "earlycon";
-		stdout-path = "serial0:115200n8";
-		append-rootblock = "nullparameter="; /* override the bootloader args */
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x20000000>; /* 512 MB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
-	};
-
-	system_fan: gpio_fan {
-		gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
-			 &gpio0 14 GPIO_ACTIVE_HIGH>;
-		alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-
-		#cooling-cells = <2>;
-	};
-
-	thermal-zones {
-		hdd-thermal {
-			polling-delay = <20000>;
-			polling-delay-passive = <2000>;
-
-			thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
-
-			trips {
-				hdd_alert1: trip1 {
-					temperature = <36000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-				hdd_alert2: trip2 {
-					temperature = <44000>;
-					hysteresis = <2000>;
-					type = "active";
-				};
-				hdd_alert3: trip3 {
-					temperature = <52000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				hdd_crit: trip4 {
-					temperature = <60000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map1 {
-					trip = <&hdd_alert1>;
-					cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
-				};
-				map2 {
-					trip = <&hdd_alert2>;
-					cooling-device = <&system_fan 2 2>;
-				};
-				map3 {
-					trip = <&hdd_alert3>;
-					cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
-				};
-			};
-		};
-
-		ethphy-thermal {
-			polling-delay = <20000>;
-			polling-delay-passive = <2000>;
-
-			thermal-sensors = <&ethphy0>;
-
-			trips {
-				ethphy_alert1: trip1 {
-					temperature = <65000>;
-					hysteresis = <4000>;
-					type = "passive";
-				};
-
-				ethphy_crit: trip2 {
-					temperature = <100000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map1 {
-					trip = <&ethphy_alert1>;
-					cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-
-			};
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&pmx_buttons>;
-		pinctrl-names = "default";
-
-		power {
-			label = "Power Switch";
-			linux,code = <KEY_POWER>;
-			linux,input-type = <EV_SW>;
-			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-		};
-
-		function {
-			label = "Function Button";
-			linux,code = <KEY_CONFIG>;
-			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
-
-		system_red {
-			label = "ls421de:red:system";
-			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_power: power_white {
-			label = "ls421de:white:power";
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		led_failsafe: power_red {
-			label = "ls421de:red:power";
-			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_upgrade: power_orange {
-			label = "ls421de:orange:power";
-			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
-		};
-
-		led_boot: system_white {
-			label = "ls421de:white:system";
-			gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		};
-
-		hdd1_red {
-			label = "ls421de:red:hdd1";
-			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ata1";
-		};
-
-		hdd2_red {
-			label = "ls421de:red:hdd2";
-			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "ata2";
-		};
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;
-		pinctrl-names = "default";
-
-		usb_power: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "USB";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
-		};
-
-		sata1_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "HDD1";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			startup-delay-us = <2000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-		};
-
-		sata2_power: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "HDD2";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			startup-delay-us = <4000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&coherencyfab {
-	broken-idle;
-};
-
-&eth1 {
-	pinctrl-0 = <&ge1_rgmii_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "rgmii-id";
-};
-
-&i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <100000>;
-	status = "okay";
-
-	rs5c372a: rs5c372a@32 {
-		compatible = "ricoh,rs5c372a";
-		reg = <0x32>;
-		wakeup-source;
-	};
-};
-
-&mdio {
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-
-	ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
-		reg = <0>;
-		marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
-				   <0x3 0x10 0x0000 0x1991>, /* LED function */
-				   <0x3 0x11 0x0000 0x4401>, /* LED polarity */
-				   <0x3 0x12 0x0000 0x4905>; /* LED timer */
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&pciec {
-	status = "okay";
-	pinctrl-0 = <&pmx_pcie>;
-	pinctrl-names = "default";
-
-	/* Connected to uPD720202 USB 3.0 Host */
-	pcie@1,0 {
-		status = "okay";
-	};
-};
-
-&pmsu {
-	pinctrl-0 = <&pmx_power_cpu>;
-	pinctrl-names = "default";
-};
-
-&rtc {
-	status = "disabled";
-};
-
-&sata {
-	nr-ports = <2>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hdd0_temp: sata-port@0 {
-		reg = <0>;
-		#thermal-sensor-cells = <0>;
-	};
-
-	hdd1_temp: sata-port@1 {
-		reg = <1>;
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&sdio {
-	pinctrl-0 = <&sdio_pins2>;
-	pinctrl-names = "default";
-	status = "okay";
-	/* No CD or WP GPIOs */
-	broken-cd;
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&nand_controller {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		label = "pxa3xx_nand-0";
-		nand-rb = <0>;
-		marvell,nand-keep-config;
-		nand-on-flash-bbt;
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "kernel";
-				reg = <0x00000000 0x02000000>;  /* 32 MiB */
-			};
-
-			partition@2000000 {
-				label = "ubi";
-				reg = <0x02000000 0x1e000000>;  /* 480 MiB */
-			};
-		};
-	};
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-0 = <&spi0_pins2>;
-	pinctrl-names = "default";
-
-	spi-flash@0 {
-		compatible = "mxicy,mx25l8005", "jedec,spi-nor";
-		reg = <0>; /* Chip select 0 */
-		spi-max-frequency = <50000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x00000 0xf0000>; /* 960 KiB*/
-				label = "u-boot";
-				read-only;
-			};
-			partition@f0000 {
-				reg = <0xf0000 0x10000>; /* 64 KiB */
-				label = "u-boot-env";
-			};
-		};
-	};
-};
-
-&pinctrl {
-	pmx_power_cpu: pmx-power-cpu {
-		marvell,pins = "mpp4";
-		marvell,function = "vdd";
-	};
-
-	pmx_power_usb: pmx-power-usb {
-		marvell,pins = "mpp5";
-		marvell,function = "gpo";
-	};
-
-	pmx_power_hdd1: pmx-power-hdd1 {
-		marvell,pins = "mpp8";
-		marvell,function = "gpio";
-	};
-
-	pmx_power_hdd2: pmx-power-hdd2 {
-		marvell,pins = "mpp9";
-		marvell,function = "gpo";
-	};
-
-	pmx_fan_lock: pmx-fan-lock {
-		marvell,pins = "mpp10";
-		marvell,function = "gpio";
-	};
-
-	pmx_hdd_present: pmx-hdd-present {
-		marvell,pins = "mpp11", "mpp12";
-		marvell,function = "gpio";
-	};
-
-	pmx_fan_high: pmx-fan-high {
-		marvell,pins = "mpp13";
-		marvell,function = "gpio";
-	};
-
-	pmx_fan_low: pmx-fan-low {
-		marvell,pins = "mpp14";
-		marvell,function = "gpio";
-	};
-
-	pmx_buttons: pmx-buttons {
-		marvell,pins = "mpp15", "mpp16";
-		marvell,function = "gpio";
-	};
-
-	pmx_leds1: pmx-leds {
-		marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
-		marvell,function = "gpo";
-	};
-
-	pmx_leds2: pmx-leds {
-		marvell,pins = "mpp55", "mpp57", "mpp62";
-		marvell,function = "gpio";
-	};
-
-	pmx_pcie: pmx-pcie {
-		marvell,pins = "mpp56", "mpp60";
-		marvell,function = "pcie";
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts
deleted file mode 100644
index 0d5ec567ea..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-370-c200-v2.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Ctera C200-V2
- *
- * Copyright (C) 2021 Pawel Dembicki <paweldembicki@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Ctera C200 V2";
-	compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
-
-	aliases {
-		led-boot = &led_status_green;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_red;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x00000000 0x40000000>; /* 1024 MB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
-	};
-
-	thermal-zones {
-		ethphy-thermal {
-			polling-delay = <20000>;
-			polling-delay-passive = <2000>;
-
-			thermal-sensors = <&ethphy0>;
-
-			trips {
-				ethphy_alert1: trip1 {
-					temperature = <65000>;
-					hysteresis = <4000>;
-					type = "passive";
-				};
-
-				ethphy_crit: trip2 {
-					temperature = <100000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&pmx_buttons>;
-		pinctrl-names = "default";
-
-		power {
-			label = "Power Button";
-			linux,code = <KEY_POWER>;
-			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-		};
-
-		reset {
-			label = "Reset Button";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-		};
-
-		usb1 {
-			label = "USB1 Button";
-			linux,code = <BTN_0>;
-			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
-		};
-
-		usb2 {
-			label = "USB2 Button";
-			linux,code = <BTN_1>;
-			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-poweroff {
-		compatible = "gpio-poweroff";
-		pinctrl-0 = <&pmx_poweroff>;
-		pinctrl-names = "default";
-		gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
-		pinctrl-names = "default";
-
-		led-0 {
-			function = LED_FUNCTION_USB;
-			function-enumerator = <2>;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-		};
-
-		led-1 {
-			function = LED_FUNCTION_USB;
-			function-enumerator = <2>;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&usb1_port 1>, <&usb2_port 1>;
-		};
-
-		led-2 {
-			function = LED_FUNCTION_USB;
-			function-enumerator = <1>;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-		};
-
-		led-3 {
-			function = LED_FUNCTION_USB;
-			function-enumerator = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&usb1_port 2>, <&usb2_port 2>;
-		};
-
-		led-4 {
-			function = LED_FUNCTION_DISK;
-			function-enumerator = <2>;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "ata2";
-		};
-
-		led-5 {
-			function = LED_FUNCTION_DISK;
-			function-enumerator = <1>;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
-		};
-
-		led-6 {
-			function = LED_FUNCTION_DISK;
-			function-enumerator = <2>;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-		};
-
-		led-7 {
-			function = LED_FUNCTION_INDICATOR;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
-		};
-
-		led-8 {
-			function = LED_FUNCTION_DISK_ERR;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
-		};
-
-		led-9 {
-			function = LED_FUNCTION_DISK_ERR;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
-		};
-
-		led_status_red: led-10 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_RED>;
-			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
-		};
-
-		led-11 {
-			function = LED_FUNCTION_DISK;
-			function-enumerator = <1>;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "ata1";
-		};
-
-		led_status_green: led-12 {
-			function = LED_FUNCTION_STATUS;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&coherencyfab {
-	broken-idle;
-};
-
-&eth1 {
-	pinctrl-0 = <&ge1_rgmii_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "rgmii-id";
-};
-
-&i2c0 {
-	pinctrl-0 = <&i2c0_pins>;
-	pinctrl-names = "default";
-	clock-frequency = <100000>;
-	status = "okay";
-
-	hwmon@2a {
-		compatible = "nuvoton,nct7802";
-		reg = <0x2a>;
-	};
-
-	rtc@30 {
-		compatible = "sii,s35390a";
-		reg = <0x30>;
-	};
-};
-
-&mdio {
-	pinctrl-0 = <&mdio_pins>;
-	pinctrl-names = "default";
-
-	ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
-		reg = <0>;
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&nand_controller {
-	status = "okay";
-
-	nand@0 {
-		reg = <0>;
-		label = "pxa3xx_nand-0";
-		nand-rb = <0>;
-		marvell,nand-keep-config;
-		nand-on-flash-bbt;
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "uboot";
-				reg = <0x0000000 0x200000>;
-				read-only;
-			};
-
-			partition@200000 {
-				label = "certificate";
-				reg = <0x0200000 0x100000>;
-				read-only;
-			};
-
-			partition@300000 {
-				label = "preset_cfg";
-				reg = <0x0300000 0x100000>;
-				read-only;
-			};
-
-			partition@400000 {
-				label = "dev_params";
-				reg = <0x0400000 0x100000>;
-				read-only;
-			};
-			partition@500000 {
-				label = "active_bank";
-				reg = <0x0500000 0x0100000>;
-			};
-
-			partition@600000 {
-				label = "magic";
-				reg = <0x0600000 0x0100000>;
-				read-only;
-			};
-
-			partition@700000 {
-				label = "bank1";
-				reg = <0x0700000 0x2800000>;
-			};
-
-			partition@2f00000 {
-				label = "bank2";
-				reg = <0x2f00000 0x2800000>;
-			};
-
-			/* 0x5700000-0x5a00000 undefined in vendor firmware */
-
-			partition@5a00000 {
-				label = "reserved";
-				reg = <0x5a00000 0x2000000>;
-			};
-
-			partition@7a00000 {
-				label = "ubi";
-				reg = <0x7a00000 0x8600000>;
-			};
-		};
-	};
-};
-
-&pciec {
-	status = "okay";
-
-	pcie@1,0 {
-		pinctrl-0 = <&pmx_pcie>;
-		pinctrl-names = "default";
-		status = "okay";
-		reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
-
-		/* -[0000:00]---01.0-[01]----00.0 */
-		/* usbport trigger won't work */
-		bridge@0,1 {
-			compatible = "pci11ab,6710";
-			reg = <0x3800 0 0 0 0>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-
-			usb@1,0 {
-				/* Renesas uPD720202 */
-				compatible = "pci1912,0015";
-				reg = <0x1000 0 0 0 0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-
-				usb1_port: port@1 {
-					reg = <1>;
-					#trigger-source-cells = <1>;
-				};
-
-				usb2_port: port@2 {
-					reg = <2>;
-					#trigger-source-cells = <1>;
-				};
-			};
-		};
-	};
-};
-
-&pinctrl {
-	pmx_poweroff: pmx-poweroff {
-		marvell,pins = "mpp7";
-		marvell,function = "gpo";
-	};
-
-	pmx_power_cpu: pmx-power-cpu {
-		marvell,pins = "mpp4";
-		marvell,function = "vdd";
-	};
-
-	pmx_buttons: pmx-buttons {
-		marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32";
-		marvell,function = "gpio";
-	};
-
-	pmx_leds1: pmx-leds1 {
-		marvell,pins = "mpp47";
-		marvell,function = "gpo";
-	};
-
-	pmx_leds2: pmx-leds2 {
-		marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51",
-			       "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58";
-		marvell,function = "gpio";
-	};
-
-	pmx_pcie: pmx-pcie {
-		marvell,pins = "mpp59";
-		marvell,function = "gpio";
-	};
-
-	/* this gpio is connected to the pin of buzzer
-	 * leave it as is due lack of proper driver
-	 */
-	pmx_buzzer: pmx-buzzer {
-		marvell,pins = "mpp63";
-		marvell,function = "gpio";
-	};
-};
-
-&pmsu {
-	pinctrl-0 = <&pmx_power_cpu>;
-	pinctrl-names = "default";
-};
-
-&rtc {
-	status = "disabled";
-};
-
-&sata {
-	nr-ports = <2>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	hdd0_temp: sata-port@0 {
-		reg = <0>;
-		#thermal-sensor-cells = <0>;
-	};
-
-	hdd1_temp: sata-port@1 {
-		reg = <1>;
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
deleted file mode 100644
index 01c1ef675b..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-380-iij-sa-w2.dts
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-380.dtsi"
-
-/ {
-	model = "IIJ SA-W2";
-	compatible = "iij,sa-w2", "marvell,armada380";
-
-	aliases {
-		led-boot = &led_power_green;
-		led-failsafe = &led_power_red;
-		led-running = &led_power_green;
-		led-upgrade = &led_power_green;
-		label-mac-device = &ge0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x10000000>; /* 256MB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
-			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
-			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-
-		pcie {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-
-			pcie@3,0 {
-				status = "okay";
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_keys_pins>;
-
-		button-init {
-			label = "init";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_leds_pins>;
-
-		led-0 {
-			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN_5GHZ;
-			linux,default-trigger = "phy0tpt";
-		};
-
-		led-1 {
-			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WLAN_5GHZ;
-		};
-
-		led-2 {
-			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_STATUS;
-		};
-
-		led-3 {
-			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_STATUS;
-		};
-
-		led-4 {
-			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_MOBILE;
-		};
-
-		led-5 {
-			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_MOBILE;
-		};
-
-		led-6 {
-			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_WLAN_2GHZ;
-			linux,default-trigger = "phy1tpt";
-		};
-
-		led-7 {
-			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_WLAN_2GHZ;
-		};
-
-		led_power_green: led-8 {
-			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led_power_red: led-9 {
-			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_POWER;
-		};
-
-		led-10 {
-			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_USB;
-			function-enumerator = <1>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&hub_port2>;
-		};
-
-		led-11 {
-			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_USB;
-			function-enumerator = <0>;
-			linux,default-trigger = "usbport";
-			trigger-sources = <&hub_port1>;
-		};
-	};
-
-	regulator-vbus-usb0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbus-usb0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		regulator-always-on;
-	};
-
-	regulator-vbus-usb1 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbus-usb1";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		regulator-always-on;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&pinctrl {
-	pmx_usb_pins: usb-pins {
-		marvell,pins = "mpp2",		 /* smsc usb2514b reset */
-			       "mpp48", "mpp49", /* port over current */
-			       "mpp52", "mpp53"; /* port vbus */
-		marvell,function = "gpio";
-	};
-
-	pmx_keys_pins: keys-pins {
-		marvell,pins = "mpp18";
-		marvell,function = "gpio";
-	};
-
-	pmx_leds_pins: leds-pins {
-		marvell,pins = "mpp19", "mpp20", "mpp33", "mpp34", "mpp35",
-			       "mpp36", "mpp44", "mpp45", "mpp46", "mpp47",
-			       "mpp54", "mpp55";
-		marvell,function = "gpio";
-	};
-};
-
-&gpio0 {
-	usb-hub-reset {
-		gpio-hog;
-		gpios = <2 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-};
-
-&usb0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pmx_usb_pins>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	/* SMSC USB2514B on PCB */
-	hub@1 {
-		compatible = "usb424,2514";
-		reg = <1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		hub_port1: port@1 {
-			reg = <1>;
-			#trigger-source-cells = <0>;
-		};
-
-		hub_port2: port@2 {
-			reg = <2>;
-			#trigger-source-cells = <0>;
-		};
-	};
-};
-
-&bm {
-	status = "okay";
-};
-
-&bm_bppi {
-	status = "okay";
-};
-
-&eth1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&ge1_rgmii_pins>;
-	status = "okay";
-
-	phy-connection-type = "rgmii-id";
-	buffer-manager = <&bm>;
-	bm,pool-long = <2>;
-	bm,pool-short = <3>;
-
-	nvmem-cells = <&macaddr_bdinfo_6 1>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>;
-	status = "okay";
-
-	/* Marvell 88E6172 */
-	switch@0 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x0>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "ge1_0";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "ge1_1";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "ge1_2";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "ge1_3";
-			};
-
-			ge0: port@4 {
-				reg = <4>;
-				label = "ge0";
-				nvmem-cells = <&macaddr_bdinfo_6 0>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			/*
-			 * eth0 is connected to port5 for WAN connection
-			 * on port4 ("GE0")
-			 */
-
-			port@6 {
-				reg = <6>;
-				label = "cpu";
-				ethernet = <&eth1>;
-				phy-connection-type = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-	};
-};
-
-&rtc {
-	status = "disabled";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x0 0x100000>;
-				label = "bootloader";
-				read-only;
-			};
-
-			partition@100000 {
-				reg = <0x100000 0x10000>;
-				label = "bootloader-env";
-				read-only;
-			};
-
-			partition@110000 {
-				reg = <0x110000 0xf0000>;
-				label = "board_info";
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_bdinfo_6: macaddr@6 {
-						compatible = "mac-base";
-						reg = <0x6 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@200000 {
-				compatible = "iij,seil-firmware";
-				reg = <0x200000 0xf00000>;
-				label = "firmware";
-				iij,bootdev-name = "flash";
-				iij,seil-id = <0x5345494c 0x32303135>;
-			};
-
-			partition@1100000 {
-				compatible = "iij,seil-firmware";
-				reg = <0x1100000 0xf00000>;
-				label = "rescue";
-				iij,bootdev-name = "rescue";
-				iij,seil-id = <0x5345494c 0x32303135>;
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
deleted file mode 100644
index dca6fbacf0..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-30e.dts
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "armada-385-fortinet-fg-x0e.dtsi"
-
-/ {
-	model = "Fortinet FortiGate 30E";
-	compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x40000000>; /* 1GB */
-	};
-};
-
-&gpio_leds {
-	led-14 {
-		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_AMBER>;
-		function = LED_FUNCTION_SPEED_WAN;
-		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
-	};
-
-	led-15 {
-		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
-	};
-};
-
-&pinctrl {
-	pmx_switch_pins: switch-pins {
-		marvell,pins = "mpp19";
-		marvell,function = "gpio";
-	};
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
-
-	/* Marvell 88E6176 */
-	switch@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2>;
-		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "wan";
-				nvmem-cells = <&macaddr_bdinfo_d880 1>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				nvmem-cells = <&macaddr_bdinfo_d880 5>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				nvmem-cells = <&macaddr_bdinfo_d880 4>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				nvmem-cells = <&macaddr_bdinfo_d880 3>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				nvmem-cells = <&macaddr_bdinfo_d880 2>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@6 {
-				reg = <6>;
-				ethernet = <&eth0>;
-				phy-connection-type = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
deleted file mode 100644
index cf13bb5fda..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-50e.dts
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "armada-385-fortinet-fg-x0e.dtsi"
-
-/ {
-	model = "Fortinet FortiGate 50E";
-	compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000>; /* 2GB */
-	};
-};
-
-&gpio_leds {
-	led-14 {
-		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		function-enumerator = <1>;
-		linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
-	};
-
-	led-15 {
-		gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		function-enumerator = <2>;
-		linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
-	};
-
-	led-16 {
-		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_AMBER>;
-		function = LED_FUNCTION_SPEED_LAN;
-		function-enumerator = <5>;
-		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
-	};
-
-	led-17 {
-		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_LAN;
-		function-enumerator = <5>;
-		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
-	};
-};
-
-&pinctrl {
-	pmx_phy_switch_pins: phy-switch-pins {
-		marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
-		marvell,function = "gpio";
-	};
-};
-
-&eth1 {
-	status = "okay";
-
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "sgmii";
-	buffer-manager = <&bm>;
-	bm,pool-long = <2>;
-	nvmem-cells = <&macaddr_bdinfo_d880 1>;
-	nvmem-cell-names = "mac-address";
-};
-
-&eth2 {
-	status = "okay";
-
-	phy-handle = <&ethphy1>;
-	phy-connection-type = "sgmii";
-	buffer-manager = <&bm>;
-	bm,pool-long = <3>;
-	nvmem-cells = <&macaddr_bdinfo_d880 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
-
-	/* Marvell 88E1512 */
-	ethphy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-id0141,0dd1",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <10000>;
-		/*
-		 * LINK/ACT   (Green): LED[0], Active Low
-		 * SPEED 100M (Amber): LED[1], Active High
-		 */
-		marvell,reg-init = <3 16 0 0x71>,
-				   <3 17 0 0x4>;
-	};
-
-	/* Marvell 88E1512 */
-	ethphy1: ethernet-phy@1 {
-		compatible = "ethernet-phy-id0141,0dd1",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <10000>;
-		/*
-		 * LINK/ACT   (Green): LED[0], Active Low
-		 * SPEED 100M (Amber): LED[1], Active High
-		 */
-		marvell,reg-init = <3 16 0 0x71>,
-				   <3 17 0 0x4>;
-	};
-
-	/* Marvell 88E6176 */
-	switch@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2>;
-		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "lan5";
-				nvmem-cells = <&macaddr_bdinfo_d880 7>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				nvmem-cells = <&macaddr_bdinfo_d880 6>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				nvmem-cells = <&macaddr_bdinfo_d880 5>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				nvmem-cells = <&macaddr_bdinfo_d880 4>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				nvmem-cells = <&macaddr_bdinfo_d880 3>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@6 {
-				reg = <6>;
-				ethernet = <&eth0>;
-				phy-connection-type = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts
deleted file mode 100644
index a2ca3158cf..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-linksys-venom.dts
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Device Tree file for the Linksys WRT32X (Venom)
- *
- * Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is licensed under the terms of the GNU General Public
- *     License version 2.  This program is licensed "as is" without
- *     any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "armada-385-linksys.dtsi"
-
-/ {
-	model = "Linksys WRT32X";
-	compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385",
-		     "marvell,armada385", "marvell,armada380";
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-		stdout-path = "serial0:115200n8";
-		append-rootblock = "root=/dev/mtdblock";
-	};
-};
-
-&expander0 {
-	wan_amber@0 {
-		label = "venom:amber:wan";
-		reg = <0x0>;
-	};
-
-	wan_blue@1 {
-		label = "venom:blue:wan";
-		reg = <0x1>;
-	};
-
-	usb2@5 {
-		label = "venom:blue:usb2";
-		reg = <0x5>;
-	};
-
-	usb3_1@6 {
-		label = "venom:blue:usb3_1";
-		reg = <0x6>;
-	};
-
-	usb3_2@7 {
-		label = "venom:blue:usb3_2";
-		reg = <0x7>;
-	};
-
-	wps_blue@8 {
-		label = "venom:blue:wps";
-		reg = <0x8>;
-	};
-
-	wps_amber@9 {
-		label = "venom:amber:wps";
-		reg = <0x9>;
-	};
-};
-
-&gpio_leds {
-	power {
-		gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-		label = "venom:blue:power";
-	};
-
-	sata {
-		gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
-		label = "venom:blue:sata";
-	};
-
-	wlan_2g {
-		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
-		label = "venom:blue:wlan_2g";
-	};
-
-	wlan_5g {
-		gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
-		label = "venom:blue:wlan_5g";
-	};
-};
-
-&gpio_leds_pins {
-	marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
-};
-
-&nand {
-	/* Spansion S34ML02G2 256MiB, OEM Layout */
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "u-boot";
-			reg = <0x0000000 0x200000>;	/* 2MB */
-			read-only;
-		};
-
-		partition@200000 {
-			label = "u_env";
-			reg = <0x200000 0x20000>;	/* 128KB */
-		};
-
-		partition@220000 {
-			label = "s_env";
-			reg = <0x220000 0x40000>;	/* 256KB */
-		};
-
-		partition@180000 {
-			label = "unused_area";
-			reg = <0x260000 0x5c0000>;	/* 5.75MB */
-		};
-
-		partition@7e0000 {
-			label = "devinfo";
-			reg = <0x7e0000 0x40000>;	/* 256KB */
-			read-only;
-		};
-
-		/* kernel1 overlaps with rootfs1 by design */
-		partition@900000 {
-			label = "kernel1";
-			reg = <0x900000 0x7b00000>;	/* 123MB */
-		};
-
-		partition@f00000 {
-			label = "rootfs1";
-			reg = <0xf00000 0x7500000>;	/* 117MB */
-		};
-
-		/* kernel2 overlaps with rootfs2 by design */
-		partition@8400000 {
-			label = "kernel2";
-			reg = <0x8400000 0x7b00000>;	/* 123MB */
-		};
-
-		partition@8a00000 {
-			label = "rootfs2";
-			reg = <0x8a00000 0x7500000>;	/* 117MB */
-		};
-
-		/* last MB is for the BBT, not writable */
-		partition@ff00000 {
-			label = "BBT";
-			reg = <0xff00000 0x100000>;
-		};
-	};
-};
-
-
-&pcie1 {
-	mwlwifi {
-		marvell,chainmask = <4 4>;
-	};
-};
-
-&pcie2 {
-	mwlwifi {
-		marvell,chainmask = <4 4>;
-	};
-};
-
-&sdhci {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhci_pins>;
-	no-1-8-v;
-	non-removable;
-	wp-inverted;
-	bus-width = <8>;
-	status = "okay";
-};
-
-&usb3_1_vbus {
-	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-};
-
-&usb3_1_vbus_pins {
-	marvell,pins = "mpp44";
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts b/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts
deleted file mode 100644
index f1fd72a93c..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-nas1dual.dts
+++ /dev/null
@@ -1,322 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
-/*
- * Device Tree file for ipTIME NAS1dual
- *
- * Copyright (C) 2020 Sungbo Eo <mans0n@gorani.run>
- *
- * Based on armada-385-linksys.dtsi
- * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-385.dtsi"
-
-/ {
-	model = "ipTIME NAS1dual";
-	compatible = "iptime,nas1dual", "marvell,armada385", "marvell,armada380";
-
-	aliases {
-		led-boot = &led_ready;
-		led-failsafe = &led_ready;
-		led-running = &led_ready;
-		led-upgrade = &led_ready;
-		label-mac-device = &eth0;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200n8";
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000>; /* 2GB */
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
-		          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-		          MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-		          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
-		          MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gpio_keys_pins>;
-
-		power {
-			label = "Power Button";
-			linux,input-type = <EV_SW>;
-			linux,code = <KEY_POWER>;
-			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
-		};
-
-		reset {
-			label = "Reset Button";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
-		};
-
-		copy {
-			label = "USB Copy Button";
-			linux,code = <KEY_COPY>;
-			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gpio_leds_pins>;
-
-		led_ready: ready {
-			label = "blue:ready";
-			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-		};
-
-		hdd {
-			label = "blue:hdd";
-			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "disk-activity";
-		};
-
-		usb {
-			function = LED_FUNCTION_USB;
-			color = <LED_COLOR_ID_BLUE>;
-			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
-			trigger-sources = <&usb3_0_port1 &usb3_0_port2>;
-			linux,default-trigger = "usbport";
-		};
-	};
-
-	gpio-fan {
-		compatible = "gpio-fan";
-		pinctrl-names = "default";
-		pinctrl-0 = <&gpio_fan_pins>;
-		gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>,
-		        <&gpio1 18 GPIO_ACTIVE_HIGH>;
-		/* We don't know the exact rpm, just use dummy values here. */
-		gpio-fan,speed-map = <0 0>, <1 1>, <2 2>;
-		#cooling-cells = <2>;
-	};
-
-	gpio-poweroff {
-		compatible = "gpio-poweroff";
-		gpios = <&pca9536 1 GPIO_ACTIVE_LOW>;
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&sata_power_pins>;
-
-		reg_sata_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "sata-power";
-			regulator-min-microvolt = <12000000>;
-			regulator-max-microvolt = <12000000>;
-			gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
-			regulator-always-on;
-		};
-	};
-};
-
-&ahci0 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	sata-port@0 {
-		reg = <0>;
-		target-supply = <&reg_sata_power>;
-		#thermal-sensor-cells = <0>;
-	};
-};
-
-&bm {
-	status = "okay";
-};
-
-&bm_bppi {
-	status = "okay";
-};
-
-&eth0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&ge0_rgmii_pins>;
-	status = "okay";
-	phy-handle = <&ethphy1>;
-	phy-connection-type = "rgmii-id";
-	buffer-manager = <&bm>;
-	bm,pool-long = <0>;
-	bm,pool-short = <1>;
-	nvmem-cells = <&macaddr_uboot_fffa8>;
-	nvmem-cell-names = "mac-address";
-};
-
-&eth1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&ge1_rgmii_pins>;
-	status = "okay";
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "rgmii-id";
-	buffer-manager = <&bm>;
-	bm,pool-long = <2>;
-	bm,pool-short = <3>;
-	nvmem-cells = <&macaddr_uboot_fffa8>;
-	nvmem-cell-names = "mac-address";
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	pca9536: gpio@41 {
-		compatible = "nxp,pca9536";
-		reg = <0x41>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-line-names = "power-led", "power-board";
-	};
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>;
-
-	/* LED1: On - Link, Blink - Activity, Off - No Link */
-
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-		marvell,reg-init = <3 16 0 0x1017>;
-	};
-
-	ethphy1: ethernet-phy@1 {
-		reg = <1>;
-		marvell,reg-init = <3 16 0 0x1017>;
-	};
-};
-
-&pinctrl {
-	gpio_keys_pins: gpio-keys-pins {
-		marvell,pins = "mpp24", "mpp26", "mpp48";
-		marvell,function = "gpio";
-	};
-
-	gpio_leds_pins: gpio-leds-pins {
-		marvell,pins = "mpp18", "mpp20", "mpp51";
-		marvell,function = "gpio";
-	};
-
-	gpio_fan_pins: gpio-fan-pins {
-		marvell,pins = "mpp25", "mpp50";
-		marvell,function = "gpio";
-	};
-
-	sata_power_pins: sata-power-pins {
-		marvell,pins = "mpp52";
-		marvell,function = "gpio";
-	};
-
-	uart1_pins_alt: uart-pins-1-alt {
-		marvell,pins = "mpp45", "mpp46";
-		marvell,function = "ua1";
-	};
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <40000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x00000000 0x00100000>;
-				label = "u-boot";
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_uboot_fffa8: macaddr@fffa8 {
-						reg = <0xfffa8 0x6>;
-					};
-				};
-			};
-
-			partition@100000 {
-				reg = <0x00100000 0x03ec0000>;
-				label = "firmware";
-
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				partition@0 {
-					reg = <0x00000000 0x00600000>;
-					label = "kernel";
-				};
-
-				partition@600000 {
-					reg = <0x00600000 0x038c0000>;
-					label = "rootfs";
-				};
-			};
-
-			partition@3fc0000 {
-				reg = <0x03fc0000 0x00040000>;
-				label = "config";
-				read-only;
-			};
-		};
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins_alt>;
-	status = "okay";
-};
-
-&usb3_0 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	usb3_0_port1: port@1 {
-		reg = <1>;
-		#trigger-source-cells = <0>;
-	};
-
-	usb3_0_port2: port@2 {
-		reg = <2>;
-		#trigger-source-cells = <0>;
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
deleted file mode 100644
index 35f107b63b..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "armada-3720-uDPU.dtsi"
-
-/ {
-	model = "Methode eDPU Board";
-	compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710";
-};
-
-/* PHY mode is set to 1000Base-X despite Maxlinear IC being capable of
- * 2500Base-X since until 5.15 support for mvebu is available trying to
- * use 2500Base-X will cause buffer overruns for which the fix is not
- * easily backportable.
- */
-&eth0 {
-	phy-mode = "1000base-x";
-};
-
-/*
- * External MV88E6361 switch is only available on v2 of the board.
- * U-Boot will enable the MDIO bus and switch nodes.
- */
-&mdio {
-	status = "disabled";
-	pinctrl-names = "default";
-	pinctrl-0 = <&smi_pins>;
-
-	/* Actual device is MV88E6361 */
-	switch: switch@0 {
-		compatible = "marvell,mv88e6190";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0>;
-		status = "disabled";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "cpu";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				ethernet = <&eth0>;
-			};
-
-			port@9 {
-				reg = <9>;
-				label = "downlink";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-			};
-
-			port@a {
-				reg = <10>;
-				label = "uplink";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				sfp = <&sfp_eth1>;
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
deleted file mode 100644
index 1a6594e3cd..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+++ /dev/null
@@ -1,240 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for ESPRESSObin-Ultra
- * Copyright (C) 2019 Globalscale technologies, Inc.
- *
- * Jason Hung <jhung@globalscaletechnologies.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
-	model = "Globalscale Marvell ESPRESSOBin Ultra Board";
-	compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
-		     "marvell,armada3710";
-
-	aliases {
-		/* for dsa slave device */
-		ethernet1 = &switch0port1;
-		ethernet2 = &switch0port2;
-		ethernet3 = &switch0port3;
-		ethernet4 = &switch0port4;
-		ethernet5 = &switch0port5;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-
-	reg_usb3_vbus: usb3-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usb3-vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-		gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
-	};
-
-	usb3_phy: usb3-phy {
-		compatible = "usb-nop-xceiv";
-		vcc-supply = <&reg_usb3_vbus>;
-	};
-
-	leds {
-		pinctrl-names = "default";
-		compatible = "gpio-leds";
-		/* No assigned functions to the LEDs by default */
-		led1 {
-			label = "ebin-ultra:blue:led1";
-			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
-		};
-		led2 {
-			label = "ebin-ultra:green:led2";
-			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
-		};
-		led3 {
-			label = "ebin-ultra:red:led3";
-			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
-		};
-		led4 {
-			label = "ebin-ultra:yellow:led4";
-			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&pcie0 {
-	status = "okay";
-};
-
-&sata {
-	status = "okay";
-};
-
-&sdhci0 {
-	status = "okay";
-	non-removable;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,pad-type = "fixed-1-8v";
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_quad_pins>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <108000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "firmware";
-				reg = <0x0 0x3e0000>;
-			};
-			partition@3e0000 {
-				label = "hw-info";
-				reg = <0x3e0000 0x10000>;
-				read-only;
-			};
-			partition@3f0000 {
-				label = "u-boot-env";
-				reg = <0x3f0000 0x10000>;
-			};
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-};
-
-&i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-
-	clock-frequency = <100000>;
-
-	rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-	};
-};
-
-&usb3 {
-	status = "okay";
-	usb-phy = <&usb3_phy>;
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&eth0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	phy-mode = "rgmii-id";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&mdio {
-	status = "okay";
-
-	extphy: ethernet-phy@0 {
-		reg = <1>;
-	};
-
-	switch0: switch0@1 {
-		compatible = "marvell,mv88e6085";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <3>;
-
-		dsa,member = <0 0>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0port0: port@0 {
-				reg = <0>;
-				ethernet = <&eth0>;
-			};
-
-			switch0port1: port@1 {
-				reg = <1>;
-				label = "lan0";
-				phy-handle = <&switch0phy1>;
-			};
-
-			switch0port2: port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-handle = <&switch0phy2>;
-			};
-
-			switch0port3: port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-handle = <&switch0phy3>;
-			};
-
-			switch0port4: port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-handle = <&switch0phy4>;
-			};
-
-			switch0port5: port@5 {
-				reg = <5>;
-				label = "wan";
-				phy-handle = <&extphy>;
-				phy-mode = "sgmii";
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0phy1: switch0phy1@11 {
-				reg = <0x11>;
-			};
-			switch0phy2: switch0phy2@12 {
-				reg = <0x12>;
-			};
-			switch0phy3: switch0phy3@13 {
-				reg = <0x13>;
-			};
-			switch0phy4: switch0phy4@14 {
-				reg = <0x14>;
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
deleted file mode 100644
index 07400fce3a..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
+++ /dev/null
@@ -1,250 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-372x.dtsi"
-
-/ {
-	model = "GL.iNet GL-MV1000";
-	compatible = "glinet,gl-mv1000", "marvell,armada3720";
-
-	aliases {
-		led-boot = &led_power;
-		led-failsafe = &led_power;
-		led-running = &led_power;
-		led-upgrade = &led_power;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-
-	vcc_sd_reg1: regulator {
-		compatible = "regulator-gpio";
-		regulator-name = "vcc_sd1";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-
-		gpios-states = <0>;
-		states = <1800000 0x1
-			3300000 0x0>;
-		enable-active-high;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
-		};
-
-		switch {
-			label = "switch";
-			linux,code = <BTN_0>;
-			gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		vpn {
-			label = "green:vpn";
-			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
-		};
-
-		wan {
-			function = LED_FUNCTION_WAN;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
-		};
-
-		led_power: power {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_GREEN>;
-			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
-			default-state = "on";
-		};
-	};
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <104000000>;
-		m25p,fast-read;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0 0xf0000>;
-				read-only;
-			};
-
-			partition@f0000 {
-				label = "u-boot-env";
-				reg = <0xf0000 0x8000>;
-				read-only;
-			};
-
-			factory: partition@f8000 {
-				label = "factory";
-				reg = <0xf8000 0x8000>;
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_factory_0: macaddr@0 {
-						reg = <0x0 0x6>;
-					};
-
-					macaddr_factory_6: macaddr@6 {
-						reg = <0x6 0x6>;
-					};
-				};
-			};
-
-			partition@100000 {
-				label = "gl-firmware-dtb";
-				reg = <0x100000 0x10000>;
-				read-only;
-			};
-
-			partition@110000 {
-				label = "gl-firmware";
-				reg = <0x110000 0xef0000>;
-				read-only;
-			};
-
-			partition@ef0000 {
-				label = "gl-firmware-jffs2";
-				reg = <0xef0000 0x110000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&sdhci1 {
-	wp-inverted;
-	bus-width = <4>;
-	cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;
-	marvell,pad-type = "sd";
-	no-1-8-v;
-	vqmmc-supply = <&vcc_sd_reg1>;
-	status = "okay";
-};
-
-&sdhci0 {
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	non-removable;
-	no-sd;
-	no-sdio;
-	marvell,pad-type = "fixed-1-8v";
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&mdio {
-	switch0: switch0@1 {
-		compatible = "marvell,mv88e6085";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <1>;
-
-		dsa,member = <0 0>;
-
-		ports: ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				ethernet = <&eth0>;
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-handle = <&switch0phy0>;
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan0";
-				phy-handle = <&switch0phy1>;
-
-				nvmem-cells = <&macaddr_factory_6>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan1";
-				phy-handle = <&switch0phy2>;
-
-				nvmem-cells = <&macaddr_factory_6>;
-				nvmem-cell-names = "mac-address";
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0phy0: switch0phy0@11 {
-				reg = <0x11>;
-			};
-			switch0phy1: switch0phy1@12 {
-				reg = <0x12>;
-			};
-			switch0phy2: switch0phy2@13 {
-				reg = <0x13>;
-			};
-		};
-	};
-};
-
-&eth0 {
-	nvmem-cells = <&macaddr_factory_0>;
-	nvmem-cell-names = "mac-address";
-	phy-mode = "rgmii-id";
-	status = "okay";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
deleted file mode 100644
index 186a5e7d7d..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "armada-3720-uDPU.dtsi"
-
-/ {
-	model = "Methode uDPU Board";
-	compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710";
-
-	sfp_eth0: sfp-eth0 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c0>;
-		los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&pinctrl_nb {
-	i2c1_recovery_pins: i2c1-recovery-pins {
-		groups = "i2c1";
-		function = "gpio";
-	};
-};
-
-&i2c0 {
-	status = "okay";
-	pinctrl-names = "default", "recovery";
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-1 = <&i2c1_recovery_pins>;
-	/delete-property/mrvl,i2c-fast-mode;
-	scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&eth0 {
-	phy-mode = "2500base-x";
-	sfp = <&sfp_eth0>;
-};
-
-&eth1 {
-	phy-mode = "2500base-x";
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
deleted file mode 100644
index bc8d1f1020..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device tree for the uDPU board.
- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
- * Copyright (C) 2016 Marvell
- * Copyright (C) 2019 Methode Electronics
- * Copyright (C) 2019 Telus
- *
- * Vladimir Vid <vladimir.vid@sartura.hr>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-
-	aliases {
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led-power1 {
-			label = "udpu:green:power";
-			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
-		};
-
-		led-power2 {
-			label = "udpu:red:power";
-			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
-		};
-
-		led-network1 {
-			label = "udpu:green:network";
-			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
-		};
-
-		led-network2 {
-			label = "udpu:red:network";
-			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
-		};
-
-		led-alarm1 {
-			label = "udpu:green:alarm";
-			gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
-		};
-
-		led-alarm2 {
-			label = "udpu:red:alarm";
-			gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	sfp_eth1: sfp-eth1 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c1>;
-		los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-	};
-};
-
-&sdhci0 {
-	status = "okay";
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,pad-type = "fixed-1-8v";
-	non-removable;
-	no-sd;
-	no-sdio;
-};
-
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_quad_pins>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <54000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "firmware";
-				reg = <0x0 0x180000>;
-			};
-
-			partition@180000 {
-				label = "u-boot-env";
-				reg = <0x180000 0x10000>;
-			};
-		};
-	};
-};
-
-&pinctrl_nb {
-	i2c2_recovery_pins: i2c2-recovery-pins {
-		groups = "i2c2";
-		function = "gpio";
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	pinctrl-names = "default", "recovery";
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-1 = <&i2c2_recovery_pins>;
-	/delete-property/mrvl,i2c-fast-mode;
-	scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
-	temp-sensor@48 {
-		compatible = "ti,tmp75c";
-		reg = <0x48>;
-	};
-
-	temp-sensor@49 {
-		compatible = "ti,tmp75c";
-		reg = <0x49>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-	managed = "in-band-status";
-	phys = <&comphy1 0>;
-};
-
-&eth1 {
-	phy-mode = "sgmii";
-	status = "okay";
-	managed = "in-band-status";
-	phys = <&comphy0 1>;
-	sfp = <&sfp_eth1>;
-};
-
-&usb3 {
-	status = "okay";
-	phys = <&usb2_utmi_otg_phy>;
-	phy-names = "usb2-utmi-otg-phy";
-};
-
-&uart0 {
-	status = "okay";
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
deleted file mode 100644
index 26804a4875..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
+++ /dev/null
@@ -1,448 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Device Tree file for Globalscale MOCHAbin
- * Copyright (C) 2019 Globalscale technologies, Inc.
- * Copyright (C) 2021 Sartura Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-7040.dtsi"
-
-/ {
-	model = "Globalscale MOCHAbin";
-	compatible = "globalscale,mochabin", "marvell,armada7040",
-		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		ethernet0 = &cp0_eth0;
-		ethernet1 = &cp0_eth1;
-		ethernet2 = &cp0_eth2;
-		ethernet3 = &swport1;
-		ethernet4 = &swport2;
-		ethernet5 = &swport3;
-		ethernet6 = &swport4;
-	};
-
-	/* SFP+ 10G */
-	sfp_eth0: sfp-eth0 {
-		compatible = "sff,sfp";
-		i2c-bus = <&cp0_i2c1>;
-		los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
-	};
-
-	/* SFP 1G */
-	sfp_eth2: sfp-eth2 {
-		compatible = "sff,sfp";
-		i2c-bus = <&cp0_i2c0>;
-		los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio  = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-/* microUSB UART console */
-&uart0 {
-	status = "okay";
-
-	pinctrl-0 = <&uart0_pins>;
-	pinctrl-names = "default";
-};
-
-/* eMMC */
-&ap_sdhci0 {
-	status = "okay";
-
-	bus-width = <4>;
-	non-removable;
-	/delete-property/ marvell,xenon-phy-slow-mode;
-	no-1-8-v;
-};
-
-&cp0_pinctrl {
-	cp0_uart0_pins: cp0-uart0-pins {
-		marvell,pins = "mpp6", "mpp7";
-		marvell,function = "uart0";
-	};
-
-	cp0_spi0_pins: cp0-spi0-pins {
-		marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
-		marvell,function = "spi0";
-	};
-
-	cp0_spi1_pins: cp0-spi1-pins {
-		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
-		marvell,function = "spi1";
-	};
-
-	cp0_i2c0_pins: cp0-i2c0-pins {
-		marvell,pins = "mpp37", "mpp38";
-		marvell,function = "i2c0";
-	};
-
-	cp0_i2c1_pins: cp0-i2c1-pins {
-		marvell,pins = "mpp2", "mpp3";
-		marvell,function = "i2c1";
-	};
-
-	pca9554_int_pins: pca9554-int-pins {
-		marvell,pins = "mpp27";
-		marvell,function = "gpio";
-	};
-
-	cp0_rgmii1_pins: cp0-rgmii1-pins {
-		marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
-			       "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
-		marvell,function = "ge1";
-	};
-
-	is31_sdb_pins: is31-sdb-pins {
-		marvell,pins = "mpp30";
-		marvell,function = "gpio";
-	};
-
-	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
-		marvell,pins = "mpp9";
-		marvell,function = "gpio";
-	};
-
-	cp0_switch_pins: cp0-switch-pins {
-		marvell,pins = "mpp0", "mpp1";
-		marvell,function = "gpio";
-	};
-
-	cp0_phy_pins: cp0-phy-pins {
-		marvell,pins = "mpp12";
-		marvell,function = "gpio";
-	};
-};
-
-/* mikroBUS UART */
-&cp0_uart0 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_uart0_pins>;
-};
-
-/* mikroBUS SPI */
-&cp0_spi0 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi0_pins>;
-};
-
-/* SPI-NOR */
-&cp0_spi1{
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi1_pins>;
-
-	spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <20000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x0 0x3e0000>;
-				read-only;
-			};
-
-			partition@3e0000 {
-				label = "hw-info";
-				reg = <0x3e0000 0x10000>;
-				read-only;
-			};
-
-			partition@3f0000 {
-				label = "u-boot-env";
-				reg = <0x3f0000 0x10000>;
-			};
-		};
-	};
-};
-
-/* mikroBUS, 1G SFP and GPIO expander */
-&cp0_i2c0 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
-	clock-frequency = <100000>;
-
-	sfp_gpio: pca9554@39 {
-		compatible = "nxp,pca9554";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pca9554_int_pins>;
-		reg = <0x39>;
-
-		interrupt-parent = <&cp0_gpio1>;
-		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		/*
-		 * IO0_0: SFP+_TX_FAULT
-		 * IO0_1: SFP+_TX_DISABLE
-		 * IO0_2: SFP+_PRSNT
-		 * IO0_3: SFP+_LOSS
-		 * IO0_4: SFP_TX_FAULT
-		 * IO0_5: SFP_TX_DISABLE
-		 * IO0_6: SFP_PRSNT
-		 * IO0_7: SFP_LOSS
-		 */
-	};
-};
-
-/* IS31FL3199, mini-PCIe and 10G SFP+ */
-&cp0_i2c1 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c1_pins>;
-	clock-frequency = <100000>;
-
-	leds@64 {
-		compatible = "issi,is31fl3199";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&is31_sdb_pins>;
-		shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
-		reg = <0x64>;
-
-		led1_red: led@1 {
-			label = "red:led1";
-			reg = <1>;
-			led-max-microamp = <20000>;
-		};
-
-		led1_green: led@2 {
-			label = "green:led1";
-			reg = <2>;
-		};
-
-		led1_blue: led@3 {
-			label = "blue:led1";
-			reg = <3>;
-		};
-
-		led2_red: led@4 {
-			label = "red:led2";
-			reg = <4>;
-		};
-
-		led2_green: led@5 {
-			label = "green:led2";
-			reg = <5>;
-		};
-
-		led2_blue: led@6 {
-			label = "blue:led2";
-			reg = <6>;
-		};
-
-		led3_red: led@7 {
-			label = "red:led3";
-			reg = <7>;
-		};
-
-		led3_green: led@8 {
-			label = "green:led3";
-			reg = <8>;
-		};
-
-		led3_blue: led@9 {
-			label = "blue:led3";
-			reg = <9>;
-		};
-	};
-};
-
-&cp0_mdio {
-	status = "okay";
-
-	/* 88E1512 PHY */
-	eth2phy: ethernet-phy@1 {
-		reg = <1>;
-		sfp = <&sfp_eth2>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&cp0_phy_pins>;
-		reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
-	};
-
-	/* 88E6141 Topaz switch */
-	switch: switch@3 {
-		compatible = "marvell,mv88e6085";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <3>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&cp0_switch_pins>;
-		reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
-
-		interrupt-parent = <&cp0_gpio1>;
-		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			swport1: port@1 {
-				reg = <1>;
-				label = "lan0";
-				phy-handle = <&swphy1>;
-			};
-
-			swport2: port@2 {
-				reg = <2>;
-				label = "lan1";
-				phy-handle = <&swphy2>;
-			};
-
-			swport3: port@3 {
-				reg = <3>;
-				label = "lan2";
-				phy-handle = <&swphy3>;
-			};
-
-			swport4: port@4 {
-				reg = <4>;
-				label = "lan3";
-				phy-handle = <&swphy4>;
-			};
-
-			port@5 {
-				reg = <5>;
-				ethernet = <&cp0_eth1>;
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-			};
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			swphy1: swphy1@17 {
-				reg = <17>;
-			};
-
-			swphy2: swphy2@18 {
-				reg = <18>;
-			};
-
-			swphy3: swphy3@19 {
-				reg = <19>;
-			};
-
-			swphy4: swphy4@20 {
-				reg = <20>;
-			};
-		};
-	};
-};
-
-&cp0_ethernet {
-	status = "okay";
-};
-
-/* 10G SFP+ */
-&cp0_eth0 {
-	status = "okay";
-
-	phy-mode = "10gbase-r";
-	phys = <&cp0_comphy4 0>;
-	managed = "in-band-status";
-	sfp = <&sfp_eth0>;
-};
-
-/* Topaz switch uplink */
-&cp0_eth1 {
-	status = "okay";
-
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy0 1>;
-
-	fixed-link {
-		speed = <2500>;
-		full-duplex;
-	};
-};
-
-/* 1G SFP or 1G RJ45 */
-&cp0_eth2 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_rgmii1_pins>;
-
-	phy = <&eth2phy>;
-	phy-mode = "rgmii-id";
-};
-
-/* SMSC USB5434B hub */
-&cp0_usb3_0 {
-	status = "okay";
-
-	phys = <&cp0_comphy1 0>;
-	phy-names = "cp0-usb3h0-comphy";
-};
-
-/* miniPCI-E USB */
-&cp0_usb3_1 {
-	status = "okay";
-};
-
-&cp0_sata0 {
-	status = "okay";
-
-	/* 7 + 12 SATA connector (J24) */
-	sata-port@0 {
-		phys = <&cp0_comphy2 0>;
-		phy-names = "cp0-sata0-0-phy";
-	};
-
-	/* M.2-2250 B-key (J39) */
-	sata-port@1 {
-		phys = <&cp0_comphy3 1>;
-		phy-names = "cp0-sata0-1-phy";
-	};
-};
-
-/* miniPCI-E (J5) */
-&cp0_pcie2 {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_pcie_reset_pins>;
-	phys = <&cp0_comphy5 2>;
-	phy-names = "cp0-pcie2-x1-phy";
-	reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
-	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts
deleted file mode 100644
index b5cc630781..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9130-clearfog-pro.dts
+++ /dev/null
@@ -1,513 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright SolidRun Ltd.
- * Copyright (C) 2024 Tobias Schramm <tobias@t-sys.eu>
- *
- * Device tree for the CN9130-based ClearFog Pro
- */
-
-#include "cn9130.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "SolidRun ClearFog Pro";
-	compatible = "solidrun,clearfog-pro", "marvell,armada-ap807-quad",
-		     "marvell,armada-ap807";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		gpio1 = &cp0_gpio1;
-		gpio2 = &cp0_gpio2;
-		i2c0 = &cp0_i2c0;
-		ethernet0 = &cp0_eth0;
-		ethernet1 = &cp0_eth1;
-		ethernet2 = &cp0_eth2;
-		spi1 = &cp0_spi1;
-	};
-
-	memory@00000000 {
-		reg = <0x0 0x0 0x1 0x0>;
-		device_type = "memory";
-	};
-
-	/* Virtual regulator, root of power tree */
-	vin: regulator-vin {
-		compatible = "regulator-fixed";
-		regulator-name = "vin";
-		regulator-always-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	/* Regulators supplied by vin */
-	v_5v0: regulator-v_5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "v_5v0";
-		regulator-always-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vin>;
-	};
-
-	v_3v3: regulator-v_3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "v_3v3";
-		regulator-always-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vin>;
-	};
-
-	/* Regulators supplied by v_5v0 */
-	v_1v8: regulator-v_1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "v_1v8";
-		regulator-always-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&v_5v0>;
-	};
-
-	v_5v0_usb3_hst_vbus: regulator-v_5v0_usb3_hst_vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "v_5v0_usb3_hst_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
-		vin-supply = <&v_5v0>;
-	};
-
-	/* Regulators internal to SOM */
-	vqmmc: regulator-vqmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "vqmmc";
-		regulator-always-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&v_5v0>;
-	};
-
-	cp0_usb3_0_phy1: cp0_usb3_phy@1 {
-		compatible = "usb-nop-xceiv";
-		vbus-supply = <&v_5v0_usb3_hst_vbus>;
-	};
-
-	cp0_sfp_eth0: sfp-eth@0 {
-		compatible = "sff,sfp";
-		i2c-bus = <&cp0_i2c1>;
-		los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <2000>;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&cp0_button_pin>;
-
-		reset {
-			label = "Reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-/* on-board eMMC  */
-&ap_sdhci0 {
-	bus-width = <8>;
-	pinctrl-names = "default";
-	vqmmc-supply = <&vqmmc>;
-	status = "okay";
-};
-
-&cp0_crypto {
-	status = "okay";
-};
-
-&cp0_ethernet {
-	status = "okay";
-};
-
-&cp0_gpio1 {
-	status = "okay";
-};
-
-&cp0_gpio2 {
-	status = "okay";
-};
-
-&cp0_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
-	clock-frequency = <100000>;
-
-	/*
-	 * PCA9655 GPIO expander, up to 1MHz clock.
-	 *  0-CON3 CLKREQ#
-	 *  1-CON3 PERST#
-	 *  2-CON2 PERST#
-	 *  3-CON3 W_DISABLE
-	 *  4-CON2 CLKREQ#
-	 *  5-USB3 overcurrent
-	 *  6-USB3 power
-	 *  7-CON2 W_DISABLE
-	 *  8-JP4 P1
-	 *  9-JP4 P4
-	 * 10-JP4 P5
-	 * 11-m.2 DEVSLP
-	 * 12-SFP_LOS
-	 * 13-SFP_TX_FAULT
-	 * 14-SFP_TX_DISABLE
-	 * 15-SFP_MOD_DEF0
-	 */
-	expander0: gpio-expander@20 {
-		compatible = "nxp,pca9555";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&cp0_gpio1>;
-		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&cp0_expander0_pins>;
-		vcc-supply = <&v_3v3>;
-
-		pcie1_0_clkreq {
-			gpio-hog;
-			gpios = <0 GPIO_ACTIVE_LOW>;
-			input;
-			line-name = "pcie1.0-clkreq";
-		};
-
-		pcie1_0_w_disable {
-			gpio-hog;
-			gpios = <3 GPIO_ACTIVE_LOW>;
-			output-low;
-			line-name = "pcie1.0-w-disable";
-		};
-
-		pcie2_0_clkreq {
-			gpio-hog;
-			gpios = <4 GPIO_ACTIVE_LOW>;
-			input;
-			line-name = "pcie2.0-clkreq";
-		};
-
-		pcie2_0_w_disable {
-			gpio-hog;
-			gpios = <7 GPIO_ACTIVE_LOW>;
-			output-low;
-			line-name = "pcie2.0-w-disable";
-		};
-
-		usb3_ilimit {
-			gpio-hog;
-			gpios = <5 GPIO_ACTIVE_LOW>;
-			input;
-			line-name = "usb3-current-limit";
-		};
-
-		m2_devslp {
-			gpio-hog;
-			gpios = <11 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "m.2 devslp";
-		};
-	};
-
-	/* ADC only for mikroBUS connector */
-	mcp3021@4c {
-		compatible = "microchip,mcp3021";
-		reg = <0x4c>;
-	};
-
-	/* EEPROM on the SOM */
-	eeprom@53 {
-		compatible = "atmel,24c02";
-		reg = <0x53>;
-		pagesize = <16>;
-		read-only;
-
-		nvmem-layout {
-			compatible = "onie,tlv-layout";
-
-			onie_tlv_macaddr: mac-address {
-				#nvmem-cell-cells = <1>;
-			};
-		};
-	};
-};
-
-/* SMBUS on mini PCIe sockets */
-&cp0_i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c1_pins>;
-	clock-frequency = <100000>;
-};
-
-&cp0_mdio {
-	status = "okay";
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		/* Green led blinks on activity, orange LED on link */
-		marvell,reg-init = <3 16 0 0x0064>;
-	};
-
-	switch@4 {
-		compatible = "marvell,mv88e6085";
-		reg = <4>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&cp0_gpio1>;
-		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&cp0_dsa0_pins>;
-		reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
-
-		mdio-external {
-			compatible = "marvell,mv88e6xxx-mdio-external";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/* 88E1512 PHY */
-			port6_phy: ethernet-phy@1 {
-				reg = <1>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "lan5";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-			};
-
-			port@5 {
-				reg = <5>;
-				ethernet = <&cp0_eth1>;
-				label = "cpu";
-				phy-mode = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			port@6 {
-				/* 88E1512 external phy */
-				reg = <6>;
-				label = "lan6";
-				phy-handle = <&port6_phy>;
-				phy-mode = "rgmii-id";
-			};
-		};
-	};
-};
-
-/* SRDS #0 - SATA on bottom M.2 B-Key connector */
-&cp0_sata0 {
-	status = "okay";
-
-	sata-port@0 {
-		status = "disabled";
-	};
-
-	sata-port@1 {
-		phys = <&cp0_comphy0 1>;
-		target-supply = <&v_3v3>;
-	};
-};
-
-&cp0_utmi {
-	status = "okay";
-};
-
-/* mini PCIe slot far from SOM, USB 2.0 only, SS lanes unused */
-&cp0_usb3_0 {
-	status = "okay";
-	phys = <&cp0_utmi0>;
-	phy-names = "utmi";
-	dr_mode = "host";
-};
-
-/* SRDS #1 - USB-A 3.0 host port */
-&cp0_usb3_1 {
-	status = "okay";
-	phys = <&cp0_utmi1>, <&cp0_comphy1 0>;
-	phy-names = "utmi", "usb";
-	usb-phy = <&cp0_usb3_0_phy1>;
-	dr_mode = "host";
-};
-
-/* SRDS #2 - SFP+ 10GE */
-&cp0_eth0 {
-	status = "okay";
-	phy-mode = "10gbase-r";
-	phys = <&cp0_comphy2 0>;
-	managed = "in-band-status";
-	nvmem-cells = <&onie_tlv_macaddr 0>;
-	nvmem-cell-names = "mac-address";
-	sfp = <&cp0_sfp_eth0>;
-};
-
-/* SRDS #3 - SGMII 1GE to L2 switch */
-&cp0_eth1 {
-	status = "okay";
-	phys = <&cp0_comphy3 1>;
-	phy-mode = "sgmii";
-	nvmem-cells = <&onie_tlv_macaddr 1>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-/* SRDS #4 - mini PCIe slot near SOM */
-&cp0_pcie1 {
-	status = "okay";
-	phys = <&cp0_comphy4 1>;
-	num-lanes = <1>;
-	reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
-};
-
-/* SRDS #5 - mini PCIe slot far from SOM */
-&cp0_pcie2 {
-	status = "okay";
-	phys = <&cp0_comphy5 2>;
-	num-lanes = <1>;
-	reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
-};
-
-/* GE PHY RGMII */
-&cp0_eth2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_ge2_rgmii_pins>;
-	phy = <&phy0>;
-	phy-mode = "rgmii-id";
-	nvmem-cells = <&onie_tlv_macaddr 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-/* micro SD card slot */
-&cp0_sdhci0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_sdhci_pins &cp0_sdhci_cd_pins>;
-	bus-width = <4>;
-	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
-	no-1-8-v;
-	vqmmc-supply = <&v_3v3>;
-	vmmc-supply = <&v_3v3>;
-};
-
-&cp0_spi1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi1_pins>;
-
-	spi-flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		spi-max-frequency = <10000000>;
-	};
-};
-
-&cp0_syscon0 {
-	cp0_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-
-		cp0_i2c0_pins: cp0-i2c0-pins {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-
-		cp0_i2c1_pins: cp0-i2c1-pins {
-			marvell,pins = "mpp35", "mpp36";
-			marvell,function = "i2c1";
-		};
-
-		cp0_ge2_rgmii_pins: cp0-ge2-rgmii-pins {
-			marvell,pins = "mpp44", "mpp45", "mpp46",
-				       "mpp47", "mpp48", "mpp49",
-				       "mpp50", "mpp51", "mpp52",
-				       "mpp53", "mpp54", "mpp55";
-			marvell,function = "ge1";
-		};
-
-		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins {
-			marvell,pins = "mpp43";
-			marvell,function = "sdio";
-		};
-
-		cp0_sdhci_pins: cp0-sdhci-pins {
-			marvell,pins = "mpp56", "mpp57", "mpp58",
-				       "mpp59", "mpp60", "mpp61";
-			marvell,function = "sdio";
-		};
-
-		cp0_spi1_pins: cp0-spi1-pins {
-			marvell,pins = "mpp12", "mpp13", "mpp14",
-				       "mpp15", "mpp16";
-			marvell,function = "spi1";
-		};
-
-		cp0_dsa0_pins: cp0-dsa0-pins {
-			marvell,pins = "mpp27", "mpp29";
-			marvell,function = "gpio";
-		};
-
-		cp0_button_pin: cp0-button-pin {
-			marvell,pins = "mpp32";
-			marvell,function = "gpio";
-		};
-
-		cp0_expander0_pins: cp0-expander0-pins {
-			marvell,pins = "mpp4";
-			marvell,function = "gpio";
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
deleted file mode 100644
index d214853f1b..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
+++ /dev/null
@@ -1,410 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (C) 2019 Marvell International Ltd.
- *
- * Device tree for the CN9131-DB board.
- */
-
-#include "cn9130.dtsi"
-#include "puzzle-thermal.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "iEi Puzzle-M901";
-	compatible = "iei,puzzle-m901",
-		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		i2c0 = &cp1_i2c0;
-		i2c1 = &cp0_i2c0;
-		ethernet0 = &cp0_eth0;
-		ethernet1 = &cp0_eth1;
-		ethernet2 = &cp0_eth2;
-		ethernet3 = &cp1_eth0;
-		ethernet4 = &cp1_eth1;
-		ethernet5 = &cp1_eth2;
-		gpio1 = &cp0_gpio1;
-		gpio2 = &cp0_gpio2;
-		gpio3 = &cp1_gpio1;
-		gpio4 = &cp1_gpio2;
-		led-boot = &led_power;
-		led-failsafe = &led_info;
-		led-running = &led_power;
-		led-upgrade = &led_info;
-	};
-
-	memory@00000000 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x80000000>;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "Reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&cp0_uart0 {
-	status = "okay";
-
-	puzzle-mcu {
-		compatible = "iei,wt61p803-puzzle";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		current-speed = <115200>;
-		enable-beep;
-		status = "okay";
-
-		leds {
-			compatible = "iei,wt61p803-puzzle-leds";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "okay";
-
-			led@0 {
-				reg = <0>;
-				label = "white:network";
-				active-low;
-			};
-
-			led@1 {
-				reg = <1>;
-				label = "green:cloud";
-				active-low;
-			};
-
-			led_info: led@2 {
-				reg = <2>;
-				label = "orange:info";
-				active-low;
-			};
-
-			led_power: led@3 {
-				reg = <3>;
-				function = LED_FUNCTION_POWER;
-				color = <LED_COLOR_ID_YELLOW>;
-				active-low;
-				default-state = "on";
-			};
-		};
-
-		hwmon {
-			compatible = "iei,wt61p803-puzzle-hwmon";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			chassis_fan_group0: fan-group@0 {
-				#cooling-cells = <2>;
-				reg = <0x00>;
-				cooling-levels = <0 159 195 211 223 241 255>;
-			};
-		};
-	};
-};
-
-&ap_thermal_ic {
-	PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
-	pinctrl-names = "default";
-	bus-width = <8>;
-	status = "okay";
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-};
-
-&cp0_crypto {
-	status = "okay";
-};
-
-&cp0_xmdio {
-	status = "okay";
-	cp0_nbaset_phy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <2>;
-	};
-	cp0_nbaset_phy1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0>;
-	};
-	cp0_nbaset_phy2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <8>;
-	};
-};
-
-&cp0_ethernet {
-	status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy2 0>;
-	phy = <&cp0_nbaset_phy0>;
-};
-
-&cp0_eth1 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy4 1>;
-	phy = <&cp0_nbaset_phy1>;
-};
-
-&cp0_eth2 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy5 2>;
-	phy = <&cp0_nbaset_phy2>;
-};
-
-&cp0_gpio1 {
-	status = "okay";
-};
-
-&cp0_gpio2 {
-	status = "okay";
-};
-
-&cp0_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
-	status = "okay";
-	clock-frequency = <100000>;
-	rtc@32 {
-		compatible = "epson,rx8130";
-		reg = <0x32>;
-		wakeup-source;
-	};
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_pcie0 {
-	status = "okay";
-	num-lanes = <2>;
-	num-viewport = <8>;
-	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
-};
-
-/* U55 */
-&cp0_spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi0_pins>;
-	reg = <0x700680 0x50>,          /* control */
-	      <0x2000000 0x1000000>;    /* CS0 */
-	status = "okay";
-	spi-flash@0 {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <40000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "U-Boot";
-				reg = <0x0 0x1f0000>;
-			};
-			partition@1f0000 {
-				label = "U-Boot ENV Factory";
-				reg = <0x1f0000 0x10000>;
-			};
-			partition@200000 {
-				label = "Reserved";
-				reg = <0x200000 0x1f0000>;
-			};
-			partition@3f0000 {
-				label = "U-Boot ENV";
-				reg = <0x3f0000 0x10000>;
-			};
-		};
-	};
-};
-
-&cp0_rtc {
-	status = "disabled";
-};
-
-&cp0_syscon0 {
-	cp0_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-		cp0_i2c0_pins: cp0-i2c-pins-0 {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-		cp0_i2c1_pins: cp0-i2c-pins-1 {
-			marvell,pins = "mpp35", "mpp36";
-			marvell,function = "i2c1";
-		};
-		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
-			marvell,pins = "mpp0", "mpp1", "mpp2",
-				       "mpp3", "mpp4", "mpp5",
-				       "mpp6", "mpp7", "mpp8",
-				       "mpp9", "mpp10", "mpp11";
-			marvell,function = "ge0";
-		};
-		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
-			marvell,pins = "mpp44", "mpp45", "mpp46",
-				       "mpp47", "mpp48", "mpp49",
-				       "mpp50", "mpp51", "mpp52",
-				       "mpp53", "mpp54", "mpp55";
-			marvell,function = "ge1";
-		};
-		cp0_spi0_pins: cp0-spi-pins-0 {
-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
-			marvell,function = "spi1";
-		};
-	};
-};
-
-/*
- * Instantiate the first connected CP115
- */
-
-#define CP11X_NAME		cp1
-#define CP11X_BASE		f6000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE	f6600000
-#define CP11X_PCIE1_BASE	f6620000
-#define CP11X_PCIE2_BASE	f6640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp1_crypto {
-	status = "okay";
-};
-
-&cp1_xmdio {
-	status = "okay";
-	cp1_nbaset_phy0: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <2>;
-	};
-	cp1_nbaset_phy1: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0>;
-	};
-	cp1_nbaset_phy2: ethernet-phy@5 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <8>;
-	};
-};
-
-&cp1_ethernet {
-	status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp1_comphy2 0>;
-	phy = <&cp1_nbaset_phy0>;
-};
-
-&cp1_eth1 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp1_comphy4 1>;
-	phy = <&cp1_nbaset_phy1>;
-};
-
-&cp1_eth2 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp1_comphy5 2>;
-	phy = <&cp1_nbaset_phy2>;
-};
-
-&cp1_sata0 {
-	status = "okay";
-	sata-port@1 {
-		status = "okay";
-		phys = <&cp1_comphy0 1>;
-	};
-};
-
-&cp1_gpio1 {
-	status = "okay";
-};
-
-&cp1_gpio2 {
-	status = "okay";
-};
-
-&cp1_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp1_i2c0_pins>;
-	clock-frequency = <100000>;
-};
-
-&cp1_rtc {
-	status = "disabled";
-};
-
-&cp1_syscon0 {
-	cp1_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-		cp1_i2c0_pins: cp1-i2c-pins-0 {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-		cp1_spi0_pins: cp1-spi-pins-0 {
-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
-			marvell,function = "spi1";
-		};
-		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
-			marvell,pins = "mpp3";
-			marvell,function = "gpio";
-		};
-		cp1_sfp_pins: sfp-pins {
-			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
-			marvell,function = "gpio";
-		};
-	};
-};
-
-&cp1_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
-&cp1_usb3_1 {
-	status = "okay";
-	phys = <&cp1_comphy3 1>;
-	phy-names = "usb";
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
deleted file mode 100644
index 8c775e4a4f..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
+++ /dev/null
@@ -1,580 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (C) 2019 Marvell International Ltd.
- *
- * Device tree for the CN9132-DB board.
- */
-
-#include "cn9130.dtsi"
-#include "puzzle-thermal.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "iEi Puzzle-M902";
-	compatible = "iei,puzzle-m902",
-		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		i2c0 = &cp1_i2c0;
-		i2c1 = &cp0_i2c0;
-		gpio1 = &cp0_gpio1;
-		gpio2 = &cp0_gpio2;
-		gpio3 = &cp1_gpio1;
-		gpio4 = &cp1_gpio2;
-		gpio5 = &cp2_gpio1;
-		gpio6 = &cp2_gpio2;
-		ethernet0 = &cp0_eth0;
-		ethernet1 = &cp0_eth1;
-		ethernet2 = &cp0_eth2;
-		ethernet3 = &cp1_eth0;
-		ethernet4 = &cp1_eth1;
-		ethernet5 = &cp1_eth2;
-		ethernet6 = &cp2_eth0;
-		ethernet7 = &cp2_eth1;
-		ethernet8 = &cp2_eth2;
-		spi1 = &cp0_spi0;
-		spi2 = &cp0_spi1;
-		led-boot = &led_power;
-		led-failsafe = &led_info;
-		led-running = &led_power;
-		led-upgrade = &led_info;
-	};
-
-	memory@00000000 {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x80000000>;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "Reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
-		compatible = "regulator-fixed";
-		regulator-name = "cp2-xhci0-vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	cp2_usb3_0_phy0: cp2_usb3_phy0 {
-		compatible = "usb-nop-xceiv";
-		vcc-supply = <&cp2_reg_usb3_vbus0>;
-	};
-
-	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
-		compatible = "regulator-fixed";
-		regulator-name = "cp2-xhci1-vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
-	};
-
-	cp2_usb3_0_phy1: cp2_usb3_phy1 {
-		compatible = "usb-nop-xceiv";
-		vcc-supply = <&cp2_reg_usb3_vbus1>;
-	};
-
-	cp2_sfp_eth0: sfp-eth0 {
-		compatible = "sff,sfp";
-		i2c-bus = <&cp2_sfpp0_i2c>;
-		los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
-		status = "disabled";
-	};
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&cp0_uart0 {
-	status = "okay";
-
-	puzzle-mcu {
-		compatible = "iei,wt61p803-puzzle";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		current-speed = <115200>;
-		enable-beep;
-		status = "okay";
-
-		leds {
-			compatible = "iei,wt61p803-puzzle-leds";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "okay";
-
-			led@0 {
-				reg = <0>;
-				label = "white:network";
-				active-low;
-			};
-
-			led@1 {
-				reg = <1>;
-				label = "green:cloud";
-				active-low;
-			};
-
-			led_info: led@2 {
-				reg = <2>;
-				label = "orange:info";
-				active-low;
-			};
-
-			led_power: led@3 {
-				reg = <3>;
-				function = LED_FUNCTION_POWER;
-				color = <LED_COLOR_ID_YELLOW>;
-				active-low;
-				default-state = "on";
-			};
-		};
-
-		hwmon {
-			compatible = "iei,wt61p803-puzzle-hwmon";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			chassis_fan_group0: fan-group@0 {
-				#cooling-cells = <2>;
-				reg = <0x00>;
-				cooling-levels = <0 159 195 211 223 241 255>;
-			};
-		};
-	};
-};
-
-&ap_thermal_ic {
-	PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
-	pinctrl-names = "default";
-	bus-width = <8>;
-	status = "okay";
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-};
-
-&cp0_crypto {
-	status = "okay";
-};
-
-&cp0_xmdio {
-	status = "okay";
-	cp0_nbaset_phy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <2>;
-	};
-	cp0_nbaset_phy1: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0>;
-	};
-	cp0_nbaset_phy2: ethernet-phy@2 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <8>;
-	};
-};
-
-&cp0_ethernet {
-	status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
-	status = "okay";
-	phy-mode = "10gbase-kr";
-	phys = <&cp0_comphy2 0>;
-	phy = <&cp0_nbaset_phy0>;
-};
-
-&cp0_eth1 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy4 1>;
-	phy = <&cp0_nbaset_phy1>;
-};
-
-&cp0_eth2 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp0_comphy1 2>;
-	phy = <&cp0_nbaset_phy2>;
-};
-
-&cp0_gpio1 {
-	status = "okay";
-};
-
-&cp0_gpio2 {
-	status = "okay";
-};
-
-&cp0_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
-	status = "okay";
-	clock-frequency = <100000>;
-	rtc@32 {
-		compatible = "epson,rx8130";
-		reg = <0x32>;
-		wakeup-source;
-	};
-};
-
-&cp0_i2c1 {
-	clock-frequency = <100000>;
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_sata0 {
-	status = "okay";
-	sata-port@1 {
-		status = "okay";
-		phys = <&cp0_comphy0 1>;
-	};
-};
-
-&cp0_pcie2 {
-	status = "okay";
-	num-lanes = <1>;
-	num-viewport = <8>;
-	phys = <&cp0_comphy5 2>;
-};
-
-/* U55 */
-&cp0_spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi0_pins>;
-	reg = <0x700680 0x50>,          /* control */
-	      <0x2000000 0x1000000>;    /* CS0 */
-	status = "okay";
-	spi-flash@0 {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <40000000>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "U-Boot";
-				reg = <0x0 0x1f0000>;
-			};
-			partition@1f0000 {
-				label = "U-Boot ENV Factory";
-				reg = <0x1f0000 0x10000>;
-			};
-			partition@200000 {
-				label = "Reserved";
-				reg = <0x200000 0x1f0000>;
-			};
-			partition@3f0000 {
-				label = "U-Boot ENV";
-				reg = <0x3f0000 0x10000>;
-			};
-		};
-	};
-};
-
-&cp0_rtc {
-	status = "disabled";
-};
-
-&cp0_syscon0 {
-	cp0_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-		cp0_i2c0_pins: cp0-i2c-pins-0 {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-		cp0_i2c1_pins: cp0-i2c-pins-1 {
-			marvell,pins = "mpp35", "mpp36";
-			marvell,function = "i2c1";
-		};
-		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
-			marvell,pins = "mpp0", "mpp1", "mpp2",
-				       "mpp3", "mpp4", "mpp5",
-				       "mpp6", "mpp7", "mpp8",
-				       "mpp9", "mpp10", "mpp11";
-			marvell,function = "ge0";
-		};
-		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
-			marvell,pins = "mpp44", "mpp45", "mpp46",
-				       "mpp47", "mpp48", "mpp49",
-				       "mpp50", "mpp51", "mpp52",
-				       "mpp53", "mpp54", "mpp55";
-			marvell,function = "ge1";
-		};
-		cp0_spi0_pins: cp0-spi-pins-0 {
-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
-			marvell,function = "spi1";
-		};
-	};
-};
-
-&cp0_usb3_1 {
-	status = "okay";
-	phys = <&cp0_comphy3 1>;
-	phy-names = "usb";
-};
-
-/*
- * Instantiate the first connected CP115
- */
-
-#define CP11X_NAME		cp1
-#define CP11X_BASE		f4000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE	f4600000
-#define CP11X_PCIE1_BASE	f4620000
-#define CP11X_PCIE2_BASE	f4640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp1_crypto {
-	status = "okay";
-};
-
-&cp1_xmdio {
-	status = "okay";
-	cp1_nbaset_phy0: ethernet-phy@3 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <2>;
-	};
-	cp1_nbaset_phy1: ethernet-phy@4 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0>;
-	};
-	cp1_nbaset_phy2: ethernet-phy@5 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <8>;
-	};
-};
-
-&cp1_ethernet {
-	status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
-	status = "okay";
-	phy-mode = "10gbase-kr";
-	phys = <&cp1_comphy2 0>;
-	phy = <&cp1_nbaset_phy0>;
-};
-
-&cp1_eth1 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp1_comphy4 1>;
-	phy = <&cp1_nbaset_phy1>;
-};
-
-&cp1_eth2 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp1_comphy1 2>;
-	phy = <&cp1_nbaset_phy2>;
-};
-
-&cp1_gpio1 {
-	status = "okay";
-};
-
-&cp1_gpio2 {
-	status = "okay";
-};
-
-&cp1_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&cp1_i2c0_pins>;
-	clock-frequency = <100000>;
-};
-
-&cp1_rtc {
-	status = "disabled";
-};
-
-&cp1_syscon0 {
-	cp1_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-		cp1_i2c0_pins: cp1-i2c-pins-0 {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-		cp1_spi0_pins: cp1-spi-pins-0 {
-			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
-			marvell,function = "spi1";
-		};
-		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
-			marvell,pins = "mpp3";
-			marvell,function = "gpio";
-		};
-	};
-};
-
-&cp1_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
-/*
- * Instantiate the second connected CP115
- */
-
-#define CP11X_NAME		cp2
-#define CP11X_BASE		f6000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE	f6600000
-#define CP11X_PCIE1_BASE	f6620000
-#define CP11X_PCIE2_BASE	f6640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp2_crypto {
-	status = "okay";
-};
-
-&cp2_ethernet {
-	status = "okay";
-};
-
-&cp2_xmdio {
-	status = "okay";
-	cp2_nbaset_phy0: ethernet-phy@6 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <2>;
-	};
-	cp2_nbaset_phy1: ethernet-phy@7 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0>;
-	};
-	cp2_nbaset_phy2: ethernet-phy@8 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <8>;
-	};
-};
-
-/* SLM-1521-V2, CON9 */
-&cp2_eth0 {
-	status = "okay";
-	phy-mode = "10gbase-kr";
-	phys = <&cp2_comphy2 0>;
-	phy = <&cp2_nbaset_phy0>;
-};
-
-&cp2_eth1 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp2_comphy4 1>;
-	phy = <&cp2_nbaset_phy1>;
-};
-
-&cp2_eth2 {
-	status = "okay";
-	phy-mode = "2500base-x";
-	phys = <&cp2_comphy1 2>;
-	phy = <&cp2_nbaset_phy2>;
-};
-
-&cp2_gpio1 {
-	status = "okay";
-};
-
-&cp2_gpio2 {
-	status = "okay";
-};
-
-&cp2_i2c0 {
-	clock-frequency = <100000>;
-	/* SLM-1521-V2 - U3 */
-	i2c-mux@72 {
-		compatible = "nxp,pca9544";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x72>;
-		cp2_sfpp0_i2c: i2c@0 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-		};
-
-		i2c@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-			/* U12 */
-			cp2_module_expander1: pca9555@21 {
-				compatible = "nxp,pca9555";
-				pinctrl-names = "default";
-				gpio-controller;
-				#gpio-cells = <2>;
-				reg = <0x21>;
-			};
-		};
-	};
-};
-
-&cp2_rtc {
-	status = "disabled";
-};
-
-&cp2_syscon0 {
-	cp2_pinctrl: pinctrl {
-		compatible = "marvell,cp115-standalone-pinctrl";
-		cp2_i2c0_pins: cp2-i2c-pins-0 {
-			marvell,pins = "mpp37", "mpp38";
-			marvell,function = "i2c0";
-		};
-	};
-};
-
-&cp2_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi b/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
deleted file mode 100644
index ea79ab224e..0000000000
--- a/target/linux/mvebu/files-6.1/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-#define PUZZLE_FAN_THERMAL(_cname, _fan)					\
-	polling-delay-passive = <500>;						\
-	polling-delay = <1000>;							\
-										\
-	trips {									\
-		cpu-hot {							\
-			temperature = <75000>;					\
-			hysteresis = <5000>;					\
-			type = "hot";						\
-		};								\
-		_cname##_active_full: cpu-active-full {				\
-			temperature = <70000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_high: cpu-active-high {				\
-			temperature = <65000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_med: cpu-active-med {				\
-			temperature = <62500>;					\
-			hysteresis = <3000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_low: cpu-active-low {				\
-			temperature = <60000>;					\
-			hysteresis = <3000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_min: cpu-active-min {				\
-			temperature = <55000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_idle: cpu-active-idle {				\
-			temperature = <50000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-	};									\
-	cooling-maps {								\
-		cpu-active-full {						\
-			trip = <&_cname##_active_full>;				\
-			cooling-device = <_fan THERMAL_NO_LIMIT			\
-					       THERMAL_NO_LIMIT>;		\
-		};								\
-		cpu-active-high {						\
-			trip = <&_cname##_active_high>;				\
-			cooling-device = <_fan 4 5>;				\
-		};								\
-		cpu-active-med {						\
-			trip = <&_cname##_active_med>;				\
-			cooling-device = <_fan 3 4>;				\
-		};								\
-		cpu-active-low {						\
-			trip = <&_cname##_active_low>;				\
-			cooling-device = <_fan 2 3>;				\
-		};								\
-		cpu-active-min {						\
-			trip = <&_cname##_active_min>;				\
-			cooling-device = <_fan 1 2>;				\
-		};								\
-		cpu-active-idle {						\
-			trip = <&_cname##_active_idle>;				\
-			cooling-device = <_fan 0 0>;				\
-		};								\
-	}
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts
index dca6fbacf0..e9e6c29213 100644
--- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-30e.dts
@@ -1,99 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "armada-385-fortinet-fg-x0e.dtsi"
+#include "armada-385-fortinet-fg-3xe.dtsi"
 
 / {
 	model = "Fortinet FortiGate 30E";
 	compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x40000000>; /* 1GB */
-	};
-};
-
-&gpio_leds {
-	led-14 {
-		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_AMBER>;
-		function = LED_FUNCTION_SPEED_WAN;
-		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
-	};
-
-	led-15 {
-		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
-	};
-};
-
-&pinctrl {
-	pmx_switch_pins: switch-pins {
-		marvell,pins = "mpp19";
-		marvell,function = "gpio";
-	};
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
-
-	/* Marvell 88E6176 */
-	switch@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2>;
-		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "wan";
-				nvmem-cells = <&macaddr_bdinfo_d880 1>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				nvmem-cells = <&macaddr_bdinfo_d880 5>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				nvmem-cells = <&macaddr_bdinfo_d880 4>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				nvmem-cells = <&macaddr_bdinfo_d880 3>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				nvmem-cells = <&macaddr_bdinfo_d880 2>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@6 {
-				reg = <6>;
-				ethernet = <&eth0>;
-				phy-connection-type = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-	};
 };
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi
new file mode 100644
index 0000000000..44dd42201d
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-3xe.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-xxe.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1GB */
+	};
+};
+
+&gpio_leds {
+	led-14 {
+		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_AMBER>;
+		function = LED_FUNCTION_SPEED_WAN;
+		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
+	};
+
+	led-15 {
+		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_SPEED_WAN;
+		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
+	};
+};
+
+&pinctrl {
+	pmx_switch_pins: switch-pins {
+		marvell,pins = "mpp19";
+		marvell,function = "gpio";
+	};
+};
+
+&mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
+
+	/* Marvell 88E6176 */
+	switch@2 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x2>;
+		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "wan";
+				nvmem-cells = <&macaddr_bdinfo_d880 1>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+				nvmem-cells = <&macaddr_bdinfo_d880 5>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+				nvmem-cells = <&macaddr_bdinfo_d880 4>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+				nvmem-cells = <&macaddr_bdinfo_d880 3>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+				nvmem-cells = <&macaddr_bdinfo_d880 2>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@6 {
+				reg = <6>;
+				ethernet = <&eth0>;
+				phy-connection-type = "rgmii-id";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts
index cf13bb5fda..01a9e36826 100644
--- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-50e.dts
@@ -1,175 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "armada-385-fortinet-fg-x0e.dtsi"
+#include "armada-385-fortinet-fg-5xe.dtsi"
 
 / {
 	model = "Fortinet FortiGate 50E";
 	compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000>; /* 2GB */
-	};
-};
-
-&gpio_leds {
-	led-14 {
-		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		function-enumerator = <1>;
-		linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
-	};
-
-	led-15 {
-		gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_WAN;
-		function-enumerator = <2>;
-		linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
-	};
-
-	led-16 {
-		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_AMBER>;
-		function = LED_FUNCTION_SPEED_LAN;
-		function-enumerator = <5>;
-		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
-	};
-
-	led-17 {
-		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
-		color = <LED_COLOR_ID_GREEN>;
-		function = LED_FUNCTION_SPEED_LAN;
-		function-enumerator = <5>;
-		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
-	};
-};
-
-&pinctrl {
-	pmx_phy_switch_pins: phy-switch-pins {
-		marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
-		marvell,function = "gpio";
-	};
-};
-
-&eth1 {
-	status = "okay";
-
-	phy-handle = <&ethphy0>;
-	phy-connection-type = "sgmii";
-	buffer-manager = <&bm>;
-	bm,pool-long = <2>;
-	nvmem-cells = <&macaddr_bdinfo_d880 1>;
-	nvmem-cell-names = "mac-address";
-};
-
-&eth2 {
-	status = "okay";
-
-	phy-handle = <&ethphy1>;
-	phy-connection-type = "sgmii";
-	buffer-manager = <&bm>;
-	bm,pool-long = <3>;
-	nvmem-cells = <&macaddr_bdinfo_d880 2>;
-	nvmem-cell-names = "mac-address";
-};
-
-&mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
-
-	/* Marvell 88E1512 */
-	ethphy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-id0141,0dd1",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <10000>;
-		/*
-		 * LINK/ACT   (Green): LED[0], Active Low
-		 * SPEED 100M (Amber): LED[1], Active High
-		 */
-		marvell,reg-init = <3 16 0 0x71>,
-				   <3 17 0 0x4>;
-	};
-
-	/* Marvell 88E1512 */
-	ethphy1: ethernet-phy@1 {
-		compatible = "ethernet-phy-id0141,0dd1",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <10000>;
-		/*
-		 * LINK/ACT   (Green): LED[0], Active Low
-		 * SPEED 100M (Amber): LED[1], Active High
-		 */
-		marvell,reg-init = <3 16 0 0x71>,
-				   <3 17 0 0x4>;
-	};
-
-	/* Marvell 88E6176 */
-	switch@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2>;
-		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				label = "lan5";
-				nvmem-cells = <&macaddr_bdinfo_d880 7>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@1 {
-				reg = <1>;
-				label = "lan4";
-				nvmem-cells = <&macaddr_bdinfo_d880 6>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@2 {
-				reg = <2>;
-				label = "lan3";
-				nvmem-cells = <&macaddr_bdinfo_d880 5>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@3 {
-				reg = <3>;
-				label = "lan2";
-				nvmem-cells = <&macaddr_bdinfo_d880 4>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@4 {
-				reg = <4>;
-				label = "lan1";
-				nvmem-cells = <&macaddr_bdinfo_d880 3>;
-				nvmem-cell-names = "mac-address";
-			};
-
-			port@6 {
-				reg = <6>;
-				ethernet = <&eth0>;
-				phy-connection-type = "rgmii-id";
-
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-		};
-	};
 };
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts
new file mode 100644
index 0000000000..7bb61113c5
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-51e.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+	model = "Fortinet FortiGate 51E";
+	compatible = "fortinet,fg-51e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+	status = "okay";
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts
new file mode 100644
index 0000000000..bcb0d05627
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-52e.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+	model = "Fortinet FortiGate 52E";
+	compatible = "fortinet,fg-52e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+	status = "okay";
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi
new file mode 100644
index 0000000000..063632d888
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-5xe.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-xxe.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2GB */
+	};
+};
+
+&gpio_leds {
+	led-14 {
+		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_SPEED_WAN;
+		function-enumerator = <1>;
+		linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
+	};
+
+	led-15 {
+		gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_SPEED_WAN;
+		function-enumerator = <2>;
+		linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
+	};
+
+	led-16 {
+		gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_AMBER>;
+		function = LED_FUNCTION_SPEED_LAN;
+		function-enumerator = <5>;
+		linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
+	};
+
+	led-17 {
+		gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_SPEED_LAN;
+		function-enumerator = <5>;
+		linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
+	};
+};
+
+&pinctrl {
+	pmx_phy_switch_pins: phy-switch-pins {
+		marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
+		marvell,function = "gpio";
+	};
+};
+
+&eth1 {
+	status = "okay";
+
+	phy-handle = <&ethphy0>;
+	phy-connection-type = "sgmii";
+	buffer-manager = <&bm>;
+	bm,pool-long = <2>;
+	nvmem-cells = <&macaddr_bdinfo_d880 1>;
+	nvmem-cell-names = "mac-address";
+};
+
+&eth2 {
+	status = "okay";
+
+	phy-handle = <&ethphy1>;
+	phy-connection-type = "sgmii";
+	buffer-manager = <&bm>;
+	bm,pool-long = <3>;
+	nvmem-cells = <&macaddr_bdinfo_d880 2>;
+	nvmem-cell-names = "mac-address";
+};
+
+&mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
+
+	/* Marvell 88E1512 */
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0141,0dd1",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+		/*
+		 * LINK/ACT   (Green): LED[0], Active Low
+		 * SPEED 100M (Amber): LED[1], Active High
+		 */
+		marvell,reg-init = <3 16 0 0x71>,
+				   <3 17 0 0x4>;
+	};
+
+	/* Marvell 88E1512 */
+	ethphy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0141,0dd1",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+		/*
+		 * LINK/ACT   (Green): LED[0], Active Low
+		 * SPEED 100M (Amber): LED[1], Active High
+		 */
+		marvell,reg-init = <3 16 0 0x71>,
+				   <3 17 0 0x4>;
+	};
+
+	/* Marvell 88E6176 */
+	switch@2 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x2>;
+		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan5";
+				nvmem-cells = <&macaddr_bdinfo_d880 7>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+				nvmem-cells = <&macaddr_bdinfo_d880 6>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+				nvmem-cells = <&macaddr_bdinfo_d880 5>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan2";
+				nvmem-cells = <&macaddr_bdinfo_d880 4>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan1";
+				nvmem-cells = <&macaddr_bdinfo_d880 3>;
+				nvmem-cell-names = "mac-address";
+			};
+
+			port@6 {
+				reg = <6>;
+				ethernet = <&eth0>;
+				phy-connection-type = "rgmii-id";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-x0e.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-x0e.dtsi
deleted file mode 100644
index 6a5e016d30..0000000000
--- a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-x0e.dtsi
+++ /dev/null
@@ -1,346 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-385.dtsi"
-
-/ {
-	aliases {
-		led-boot = &led_status_green;
-		led-failsafe = &led_status_red;
-		led-running = &led_status_green;
-		led-upgrade = &led_status_green;
-		label-mac-device = &eth0;
-	};
-
-	chosen {
-		stdout-path = "serial0:9600n8";
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
-			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
-			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_gpio_keys_pins>;
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_leds: gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmx_gpio_leds_pins>;
-
-		led-0 {
-			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_ALARM;
-		};
-
-		led-1 {
-			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_RED>;
-			function = "ha";
-		};
-
-		led_status_green: led-2 {
-			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_STATUS;
-		};
-
-		led-3 {
-			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = "ha";
-		};
-
-		led-4 {
-			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_ALARM;
-		};
-
-		led_status_red: led-5 {
-			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_STATUS;
-		};
-
-		led-6 {
-			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <4>;
-			linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
-		};
-
-		led-7 {
-			gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <4>;
-			linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
-		};
-
-		led-8 {
-			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <3>;
-			linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
-		};
-
-		led-9 {
-			gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <3>;
-			linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
-		};
-
-		led-10 {
-			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <1>;
-			linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
-		};
-
-		led-11 {
-			gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <1>;
-			linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
-		};
-
-		led-12 {
-			gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <2>;
-			linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
-		};
-
-		led-13 {
-			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_AMBER>;
-			function = LED_FUNCTION_SPEED_LAN;
-			function-enumerator = <2>;
-			linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
-		};
-	};
-
-	reg_usb_vbus: regulator-usb-vbus {
-		compatible = "fixed-regulator";
-		regulator-name = "usb-vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
-		regulator-always-on;
-	};
-};
-
-&i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-	status = "okay";
-
-	gpio2: gpio@24 {
-		compatible = "nxp,pca9555";
-		reg = <0x24>;
-		gpio-controller;
-		#gpio-cells = <0x2>;
-	};
-
-	hwmon@28 {
-		compatible = "nuvoton,nct7802";
-		reg = <0x28>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&pinctrl {
-	pmx_gpio_leds_pins: gpio-leds-pins {
-		marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
-			       "mpp45", "mpp47";
-		marvell,function = "gpio";
-	};
-
-	pmx_usb_pins: usb-pins {
-		marvell,pins = "mpp53";
-		marvell,function = "gpio";
-	};
-
-	pmx_gpio_keys_pins: gpio-keys-pins {
-		marvell,pins = "mpp54";
-		marvell,function = "gpio";
-	};
-};
-
-&bm {
-	status = "okay";
-};
-
-&bm_bppi {
-	status = "okay";
-};
-
-&eth0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&ge0_rgmii_pins>;
-	status = "okay";
-
-	phy-connection-type = "rgmii-id";
-	buffer-manager = <&bm>;
-	bm,pool-long = <0>;
-	bm,pool-short = <1>;
-	nvmem-cells = <&macaddr_bdinfo_d880 0>;
-	nvmem-cell-names = "mac-address";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};
-
-&usb3_0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pmx_usb_pins>;
-	status = "okay";
-
-	vbus-supply = <&reg_usb_vbus>;
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi1_pins>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				reg = <0x0 0x1c0000>;
-				label = "u-boot";
-				read-only;
-			};
-
-			partition@1c0000 {
-				reg = <0x1c0000 0x10000>;
-				label = "firmware-info";
-
-				/*
-				 *  0x10 - 0x2f : image name (image1)
-				 *  0x30 - 0x4f : image name (image2)
-				 * 0x170 (1byte): active image (0x0/0x1)
-				 * 0x184 - 0x185: kernel block count (image1)
-				 * 0x18c - 0x18d: rootfs block count (image1)
-				 * 0x194 - 0x195: kernel block count (image2)
-				 * 0x19c - 0x19d: rootfs block count (image2)
-				 * 0x1be (1byte): bit7 -> active flag (image1)?
-				 * 0x1ce (1byte): bit7 -> active flag (image2)?
-				 *
-				 * Note: block size --> 0x200 (512 bytes)
-				 */
-			};
-
-			partition@1d0000 {
-				reg = <0x1d0000 0x10000>;
-				label = "dtb";
-				read-only;
-			};
-
-			partition@1e0000 {
-				reg = <0x1e0000 0x10000>;
-				label = "u-boot-env";
-				read-only;
-			};
-
-			partition@1f0000 {
-				reg = <0x1f0000 0x10000>;
-				label = "board-info";
-				read-only;
-
-				nvmem-layout {
-					compatible = "fixed-layout";
-					#address-cells = <1>;
-					#size-cells = <1>;
-
-					macaddr_bdinfo_d880: macaddr@d880 {
-						compatible = "mac-base";
-						reg = <0xd880 0x6>;
-						#nvmem-cell-cells = <1>;
-					};
-				};
-			};
-
-			partition@200000 {
-				reg = <0x200000 0x600000>;
-				label = "kernel";
-			};
-
-			partition@800000 {
-				reg = <0x800000 0x1800000>;
-				label = "rootfs";
-			};
-
-			partition@2000000 {
-				reg = <0x2000000 0x600000>;
-				label = "kn2";
-				read-only;
-			};
-
-			partition@2600000 {
-				reg = <0x2600000 0x1800000>;
-				label = "rfs2";
-				read-only;
-			};
-
-			partition@3e00000 {
-				reg = <0x3e00000 0x1200000>;
-				label = "part1";
-				read-only;
-			};
-
-			partition@5000000 {
-				reg = <0x5000000 0x1200000>;
-				label = "part2";
-				read-only;
-			};
-
-			partition@6200000 {
-				reg = <0x6200000 0x1e00000>;
-				label = "config";
-				read-only;
-			};
-		};
-	};
-};
diff --git a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi
index 6a5e016d30..6a5e016d30 100644
--- a/target/linux/mvebu/files-6.1/arch/arm/boot/dts/armada-385-fortinet-fg-x0e.dtsi
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fg-xxe.dtsi
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts
new file mode 100644
index 0000000000..eee9e6d942
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-50e-2r.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+	model = "Fortinet FortiWiFi 50E-2R";
+	compatible = "fortinet,fwf-50e-2r", "marvell,armada385", "marvell,armada380";
+};
+
+&pciec {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts
new file mode 100644
index 0000000000..d9ebd9f815
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm/boot/dts/marvell/armada-385-fortinet-fwf-51e.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+	model = "Fortinet FortiWiFi 51E";
+	compatible = "fortinet,fwf-51e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+	status = "okay";
+};
+
+&pciec {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
index d214853f1b..90d6e855be 100644
--- a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
+++ b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts
@@ -54,6 +54,48 @@
 			gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	thermal-zones {
+		chassis0-thermal {
+			thermal-sensors = <&puzzle_hwmon 0>;
+			PUZZLE_FAN_CHASSIS_THERMAL(chassis0, &chassis_fan_group0);
+		};
+
+		chassis1-thermal {
+			thermal-sensors = <&puzzle_hwmon 1>;
+			PUZZLE_FAN_CHASSIS_THERMAL(chassis1, &chassis_fan_group0);
+		};
+
+		cp0-phy0-thermal {
+			thermal-sensors = <&cp0_nbaset_phy0>;
+			PUZZLE_FAN_THERMAL(cp0_phy0, &chassis_fan_group0);
+		};
+
+		cp0-phy1-thermal {
+			thermal-sensors = <&cp0_nbaset_phy1>;
+			PUZZLE_FAN_THERMAL(cp0_phy1, &chassis_fan_group0);
+		};
+
+		cp0-phy2-thermal {
+			thermal-sensors = <&cp0_nbaset_phy2>;
+			PUZZLE_FAN_THERMAL(cp0_phy2, &chassis_fan_group0);
+		};
+
+		cp1-phy0-thermal {
+			thermal-sensors = <&cp1_nbaset_phy0>;
+			PUZZLE_FAN_THERMAL(cp1_phy0, &chassis_fan_group0);
+		};
+
+		cp1-phy1-thermal {
+			thermal-sensors = <&cp1_nbaset_phy1>;
+			PUZZLE_FAN_THERMAL(cp1_phy1, &chassis_fan_group0);
+		};
+
+		cp1-phy2-thermal {
+			thermal-sensors = <&cp1_nbaset_phy2>;
+			PUZZLE_FAN_THERMAL(cp1_phy2, &chassis_fan_group0);
+		};
+	};
 };
 
 &uart0 {
@@ -104,10 +146,11 @@
 			};
 		};
 
-		hwmon {
+		puzzle_hwmon: hwmon {
 			compatible = "iei,wt61p803-puzzle-hwmon";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
 
 			chassis_fan_group0: fan-group@0 {
 				#cooling-cells = <2>;
@@ -118,14 +161,6 @@
 	};
 };
 
-&ap_thermal_ic {
-	PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
 /* on-board eMMC - U9 */
 &ap_sdhci0 {
 	pinctrl-names = "default";
@@ -144,14 +179,17 @@
 	cp0_nbaset_phy0: ethernet-phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <2>;
+		#thermal-sensor-cells = <0>;
 	};
 	cp0_nbaset_phy1: ethernet-phy@1 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <0>;
+		#thermal-sensor-cells = <0>;
 	};
 	cp0_nbaset_phy2: ethernet-phy@2 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <8>;
+		#thermal-sensor-cells = <0>;
 	};
 };
 
@@ -313,14 +351,17 @@
 	cp1_nbaset_phy0: ethernet-phy@3 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <2>;
+		#thermal-sensor-cells = <0>;
 	};
 	cp1_nbaset_phy1: ethernet-phy@4 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <0>;
+		#thermal-sensor-cells = <0>;
 	};
 	cp1_nbaset_phy2: ethernet-phy@5 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <8>;
+		#thermal-sensor-cells = <0>;
 	};
 };
 
@@ -399,10 +440,6 @@
 	};
 };
 
-&cp1_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
 &cp1_usb3_1 {
 	status = "okay";
 	phys = <&cp1_comphy3 1>;
diff --git a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
index 8c775e4a4f..67dace4888 100644
--- a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
+++ b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts
@@ -99,6 +99,64 @@
 		tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
 		status = "disabled";
 	};
+
+	thermal-zones {
+		chassis0-thermal {
+			thermal-sensors = <&puzzle_hwmon 0>;
+			PUZZLE_FAN_CHASSIS_THERMAL(chassis0, &chassis_fan_group0);
+		};
+
+		chassis1-thermal {
+			thermal-sensors = <&puzzle_hwmon 1>;
+			PUZZLE_FAN_CHASSIS_THERMAL(chassis1, &chassis_fan_group0);
+		};
+
+		cp0-phy0-thermal {
+			thermal-sensors = <&cp0_nbaset_phy0>;
+			PUZZLE_FAN_THERMAL(cp0_phy0, &chassis_fan_group0);
+		};
+
+		cp0-phy1-thermal {
+			thermal-sensors = <&cp0_nbaset_phy1>;
+			PUZZLE_FAN_THERMAL(cp0_phy1, &chassis_fan_group0);
+		};
+
+		cp0-phy2-thermal {
+			thermal-sensors = <&cp0_nbaset_phy2>;
+			PUZZLE_FAN_THERMAL(cp0_phy2, &chassis_fan_group0);
+		};
+
+		cp1-phy0-thermal {
+			thermal-sensors = <&cp1_nbaset_phy0>;
+			PUZZLE_FAN_THERMAL(cp1_phy0, &chassis_fan_group0);
+		};
+
+		cp1-phy1-thermal {
+			thermal-sensors = <&cp1_nbaset_phy1>;
+			PUZZLE_FAN_THERMAL(cp1_phy1, &chassis_fan_group0);
+		};
+
+		cp1-phy2-thermal {
+			thermal-sensors = <&cp1_nbaset_phy2>;
+			PUZZLE_FAN_THERMAL(cp1_phy2, &chassis_fan_group0);
+		};
+
+		cp2-phy0-thermal {
+			thermal-sensors = <&cp2_nbaset_phy0>;
+			PUZZLE_FAN_THERMAL(cp2_phy0, &chassis_fan_group0);
+		};
+
+		cp2-phy1-thermal {
+			thermal-sensors = <&cp2_nbaset_phy1>;
+			PUZZLE_FAN_THERMAL(cp2_phy1, &chassis_fan_group0);
+		};
+
+		cp2-phy2-thermal {
+			thermal-sensors = <&cp2_nbaset_phy2>;
+			PUZZLE_FAN_THERMAL(cp2_phy2, &chassis_fan_group0);
+		};
+	};
+
 };
 
 &uart0 {
@@ -149,10 +207,11 @@
 			};
 		};
 
-		hwmon {
+		puzzle_hwmon: hwmon {
 			compatible = "iei,wt61p803-puzzle-hwmon";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
 
 			chassis_fan_group0: fan-group@0 {
 				#cooling-cells = <2>;
@@ -163,15 +222,6 @@
 	};
 };
 
-&ap_thermal_ic {
-	PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-
 /* on-board eMMC - U9 */
 &ap_sdhci0 {
 	pinctrl-names = "default";
@@ -187,17 +237,20 @@
 
 &cp0_xmdio {
 	status = "okay";
-	cp0_nbaset_phy0: ethernet-phy@0 {
+	cp0_nbaset_phy0: ethernet-phy@2 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <2>;
+		#thermal-sensor-cells = <0>;
 	};
-	cp0_nbaset_phy1: ethernet-phy@1 {
+	cp0_nbaset_phy1: ethernet-phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <0>;
+		#thermal-sensor-cells = <0>;
 	};
-	cp0_nbaset_phy2: ethernet-phy@2 {
+	cp0_nbaset_phy2: ethernet-phy@8 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <8>;
+		#thermal-sensor-cells = <0>;
 	};
 };
 
@@ -374,17 +427,20 @@
 
 &cp1_xmdio {
 	status = "okay";
-	cp1_nbaset_phy0: ethernet-phy@3 {
+	cp1_nbaset_phy0: ethernet-phy@2 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <2>;
+		#thermal-sensor-cells = <0>;
 	};
-	cp1_nbaset_phy1: ethernet-phy@4 {
+	cp1_nbaset_phy1: ethernet-phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <0>;
+		#thermal-sensor-cells = <0>;
 	};
-	cp1_nbaset_phy2: ethernet-phy@5 {
+	cp1_nbaset_phy2: ethernet-phy@8 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <8>;
+		#thermal-sensor-cells = <0>;
 	};
 };
 
@@ -451,10 +507,6 @@
 	};
 };
 
-&cp1_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
 /*
  * Instantiate the second connected CP115
  */
@@ -487,17 +539,20 @@
 
 &cp2_xmdio {
 	status = "okay";
-	cp2_nbaset_phy0: ethernet-phy@6 {
+	cp2_nbaset_phy0: ethernet-phy@2 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <2>;
+		#thermal-sensor-cells = <0>;
 	};
-	cp2_nbaset_phy1: ethernet-phy@7 {
+	cp2_nbaset_phy1: ethernet-phy@0 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <0>;
+		#thermal-sensor-cells = <0>;
 	};
 	cp2_nbaset_phy2: ethernet-phy@8 {
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <8>;
+		#thermal-sensor-cells = <0>;
 	};
 };
 
@@ -574,7 +629,3 @@
 		};
 	};
 };
-
-&cp2_thermal_ic {
-	PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
-};
diff --git a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
index ea79ab224e..eb8682b297 100644
--- a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
+++ b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/puzzle-thermal.dtsi
@@ -1,68 +1,98 @@
-#define PUZZLE_FAN_THERMAL(_cname, _fan)					\
-	polling-delay-passive = <500>;						\
-	polling-delay = <1000>;							\
-										\
-	trips {									\
-		cpu-hot {							\
-			temperature = <75000>;					\
-			hysteresis = <5000>;					\
-			type = "hot";						\
-		};								\
-		_cname##_active_full: cpu-active-full {				\
-			temperature = <70000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_high: cpu-active-high {				\
-			temperature = <65000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_med: cpu-active-med {				\
-			temperature = <62500>;					\
-			hysteresis = <3000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_low: cpu-active-low {				\
-			temperature = <60000>;					\
-			hysteresis = <3000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_min: cpu-active-min {				\
-			temperature = <55000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-		_cname##_active_idle: cpu-active-idle {				\
-			temperature = <50000>;					\
-			hysteresis = <5000>;					\
-			type = "active";					\
-		};								\
-	};									\
-	cooling-maps {								\
-		cpu-active-full {						\
-			trip = <&_cname##_active_full>;				\
-			cooling-device = <_fan THERMAL_NO_LIMIT			\
-					       THERMAL_NO_LIMIT>;		\
-		};								\
-		cpu-active-high {						\
-			trip = <&_cname##_active_high>;				\
-			cooling-device = <_fan 4 5>;				\
-		};								\
-		cpu-active-med {						\
-			trip = <&_cname##_active_med>;				\
-			cooling-device = <_fan 3 4>;				\
-		};								\
-		cpu-active-low {						\
-			trip = <&_cname##_active_low>;				\
-			cooling-device = <_fan 2 3>;				\
-		};								\
-		cpu-active-min {						\
-			trip = <&_cname##_active_min>;				\
-			cooling-device = <_fan 1 2>;				\
-		};								\
-		cpu-active-idle {						\
-			trip = <&_cname##_active_idle>;				\
-			cooling-device = <_fan 0 0>;				\
-		};								\
+#define PUZZLE_FAN_THERMAL(_cname, _fan)				\
+	polling-delay-passive = <0>;					\
+	polling-delay = <1000>;						\
+									\
+	trips {								\
+		_cname##_active_full: trip-point5 {			\
+			temperature = <70000>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_very_high: trip-point4 {		\
+			temperature = <67500>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_high: trip-point3 {			\
+			temperature = <65000>;				\
+			hysteresis = <5000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_med: trip-point2 {			\
+			temperature = <62500>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_low: trip-point1 {			\
+			temperature = <60000>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_min: trip-point0 {			\
+			temperature = <55000>;				\
+			hysteresis = <5000>;				\
+			type = "active";				\
+		};							\
+	};								\
+	cooling-maps {							\
+		map5 {							\
+			trip = <&_cname##_active_full>;			\
+			cooling-device = <_fan 6 6>;			\
+		};							\
+		map4 {							\
+			trip = <&_cname##_active_very_high>;		\
+			cooling-device = <_fan 5 5>;			\
+		};							\
+		map3 {							\
+			trip = <&_cname##_active_high>;			\
+			cooling-device = <_fan 4 4>;			\
+		};							\
+		map2 {							\
+			trip = <&_cname##_active_med>;			\
+			cooling-device = <_fan 3 3>;			\
+		};							\
+		map1 {							\
+			trip = <&_cname##_active_low>;			\
+			cooling-device = <_fan 2 2>;			\
+		};							\
+		map0 {							\
+			trip = <&_cname##_active_min>;			\
+			cooling-device = <_fan 1 1>;			\
+		};							\
+	}
+
+#define PUZZLE_FAN_CHASSIS_THERMAL(_cname, _fan)			\
+	polling-delay-passive = <0>;					\
+	polling-delay = <5000>;						\
+									\
+	trips {								\
+		_cname##_active_full: trip-point2 {			\
+			temperature = <70000>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_med: trip-point1 {			\
+			temperature = <62500>;				\
+			hysteresis = <3000>;				\
+			type = "active";				\
+		};							\
+		_cname##_active_min: trip-point0 {			\
+			temperature = <55000>;				\
+			hysteresis = <5000>;				\
+			type = "active";				\
+		};							\
+	};								\
+	cooling-maps {							\
+		map2 {							\
+			trip = <&_cname##_active_full>;			\
+			cooling-device = <_fan 6 6>;			\
+		};							\
+		map1 {							\
+			trip = <&_cname##_active_med>;			\
+			cooling-device = <_fan 3 3>;			\
+		};							\
+		map0 {							\
+			trip = <&_cname##_active_min>;			\
+			cooling-device = <_fan 1 1>;			\
+		};							\
 	}
diff --git a/target/linux/mvebu/image/cortexa9.mk b/target/linux/mvebu/image/cortexa9.mk
index 270c631474..b3b8960a32 100644
--- a/target/linux/mvebu/image/cortexa9.mk
+++ b/target/linux/mvebu/image/cortexa9.mk
@@ -3,9 +3,7 @@
 # Copyright (C) 2012-2016 OpenWrt.org
 # Copyright (C) 2016 LEDE-project.org
 
-ifneq ($(KERNEL),6.1)
 DTS_DIR := $(DTS_DIR)/marvell
-endif
 
 define Build/fortigate-header
   ( \
@@ -116,36 +114,73 @@ define Device/cznic_turris-omnia
 endef
 TARGET_DEVICES += cznic_turris-omnia
 
-define Device/fortinet_fg-30e
+define Device/fortinet
   DEVICE_VENDOR := Fortinet
-  DEVICE_MODEL := FortiGate 30E
   SOC := armada-385
   KERNEL := kernel-bin | append-dtb
-  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
-    gzip-filename FGT30E
   KERNEL_SIZE := 6144k
-  DEVICE_DTS := armada-385-fortinet-fg-30e
   IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \
     sysupgrade-tar rootfs=$$$$@ | append-metadata
   DEVICE_PACKAGES := kmod-hwmon-nct7802
 endef
+
+define Device/fortinet_fg-30e
+  $(Device/fortinet)
+  DEVICE_MODEL := FortiGate 30E
+  DEVICE_DTS := armada-385-fortinet-fg-30e
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+    gzip-filename FGT30E
+endef
 TARGET_DEVICES += fortinet_fg-30e
 
 define Device/fortinet_fg-50e
-  DEVICE_VENDOR := Fortinet
+  $(Device/fortinet)
   DEVICE_MODEL := FortiGate 50E
-  SOC := armada-385
-  KERNEL := kernel-bin | append-dtb
+  DEVICE_DTS := armada-385-fortinet-fg-50e
   KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
     gzip-filename FGT50E
-  KERNEL_SIZE := 6144k
-  DEVICE_DTS := armada-385-fortinet-fg-50e
-  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \
-    sysupgrade-tar rootfs=$$$$@ | append-metadata
-  DEVICE_PACKAGES := kmod-hwmon-nct7802
 endef
 TARGET_DEVICES += fortinet_fg-50e
 
+define Device/fortinet_fg-51e
+  $(Device/fortinet)
+  DEVICE_MODEL := FortiGate 51E
+  DEVICE_DTS := armada-385-fortinet-fg-51e
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+    gzip-filename FGT51E
+endef
+TARGET_DEVICES += fortinet_fg-51e
+
+define Device/fortinet_fg-52e
+  $(Device/fortinet)
+  DEVICE_MODEL := FortiGate 52E
+  DEVICE_DTS := armada-385-fortinet-fg-52e
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+    gzip-filename FGT52E
+endef
+TARGET_DEVICES += fortinet_fg-52e
+
+define Device/fortinet_fwf-50e-2r
+  $(Device/fortinet)
+  DEVICE_MODEL := FortiWiFi 50E-2R
+  DEVICE_DTS := armada-385-fortinet-fwf-50e-2r
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+    gzip-filename FW502R
+  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \
+    wpad-basic-mbedtls
+endef
+TARGET_DEVICES += fortinet_fwf-50e-2r
+
+define Device/fortinet_fwf-51e
+  $(Device/fortinet)
+  DEVICE_MODEL := FortiWiFi 51E
+  DEVICE_DTS := armada-385-fortinet-fwf-51e
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+    gzip-filename FWF51E
+  DEVICE_PACKAGES += kmod-ath9k wpad-basic-mbedtls
+endef
+TARGET_DEVICES += fortinet_fwf-51e
+
 define Device/globalscale_mirabox
   $(Device/NAND-512K)
   DEVICE_VENDOR := Globalscale
diff --git a/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch b/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch
deleted file mode 100644
index 354d262015..0000000000
--- a/target/linux/mvebu/patches-6.1/000-cpufreq-armada-8k-add-ap807-support.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 8eec6e740b564ec5e1da59ab7070b89aa23c9973 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Fri, 16 Jun 2023 12:41:30 +0100
-Subject: [PATCH] cpufreq: armada-8k: add ap807 support
-
-Add support for the Armada AP807 die to armada-8k. This uses a
-different compatible for the CPU clock which needs to be added to
-the cpufreq driver.
-
-This commit takes a different approach to the WindRiver patch
-"cpufreq: armada: enable ap807-cpu-clk" in that rather than calling
-of_find_compatible_node() for each compatible, we use a table of
-IDs instead.
-
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/armada-8k-cpufreq.c | 16 +++++++++-------
- 1 file changed, 9 insertions(+), 7 deletions(-)
-
---- a/drivers/cpufreq/armada-8k-cpufreq.c
-+++ b/drivers/cpufreq/armada-8k-cpufreq.c
-@@ -21,6 +21,13 @@
- #include <linux/pm_opp.h>
- #include <linux/slab.h>
- 
-+static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
-+	{ .compatible = "marvell,ap806-cpu-clock" },
-+	{ .compatible = "marvell,ap807-cpu-clock" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
-+
- /*
-  * Setup the opps list with the divider for the max frequency, that
-  * will be filled at runtime.
-@@ -127,7 +134,8 @@ static int __init armada_8k_cpufreq_init
- 	struct device_node *node;
- 	struct cpumask cpus;
- 
--	node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock");
-+	node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match,
-+					       NULL);
- 	if (!node || !of_device_is_available(node)) {
- 		of_node_put(node);
- 		return -ENODEV;
-@@ -204,12 +212,6 @@ static void __exit armada_8k_cpufreq_exi
- }
- module_exit(armada_8k_cpufreq_exit);
- 
--static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
--	{ .compatible = "marvell,ap806-cpu-clock" },
--	{ },
--};
--MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
--
- MODULE_AUTHOR("Gregory Clement <gregory.clement@bootlin.com>");
- MODULE_DESCRIPTION("Armada 8K cpufreq driver");
- MODULE_LICENSE("GPL");
diff --git a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch b/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
deleted file mode 100644
index 4936f6ad16..0000000000
--- a/target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
-Date:   Tue,  2 Aug 2022 14:38:16 +0200
-Message-Id: <20220802123816.21817-1-pali@kernel.org>
-X-Mailer: git-send-email 2.20.1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
-document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
-that PCIe IP does not support a strong-ordered model for inbound posted vs.
-outbound completion.
-
-As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
-register must be set. It disables the ordering check in the core between
-Completions and Posted requests received from the link.
-
-Marvell also suggests to do full memory barrier at the beginning of
-aardvark summary interrupt handler before calling interrupt handlers of
-endpoint drivers in order to minimize the risk for the race condition
-documented in the Erratum between the DMA done status reading and the
-completion of writing to the host memory.
-
-More details about this issue and suggested workarounds are in discussion:
-https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
-
-It was reported that enabling this workaround fixes instability issues and
-"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
-QCA6335 chip under significant load which were caused by interrupt status
-stuck in the outbound CMPLT queue traced back to this erratum.
-
-This workaround fixes also kernel panic triggered after some minutes of
-usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
-
-    Internal error: synchronous external abort: 96000210 [#1] SMP
-    Kernel panic - not syncing: Fatal exception in interrupt
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
-Cc: stable@vger.kernel.org
----
- drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/pci/controller/pci-aardvark.c
-+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -212,6 +212,8 @@ enum {
- };
- 
- #define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
-+#define DEBUG_MUX_CTRL_REG			(LMI_BASE_ADDR + 0x208)
-+#define     DIS_ORD_CHK				BIT(30)
- 
- /* PCIe core controller registers */
- #define CTRL_CORE_BASE_ADDR			0x18000
-@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
- 		PCIE_CORE_CTRL2_TD_ENABLE;
- 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
- 
-+	/* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
-+	reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
-+	reg |= DIS_ORD_CHK;
-+	advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
-+
- 	/* Set lane X1 */
- 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- 	reg &= ~LANE_CNT_MSK;
-@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
- 	struct advk_pcie *pcie = arg;
- 	u32 status;
- 
-+	/* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
-+	mb();
-+
- 	status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
- 	if (!(status & PCIE_IRQ_CORE_INT))
- 		return IRQ_NONE;
diff --git a/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch b/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch
deleted file mode 100644
index 3223861234..0000000000
--- a/target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/drivers/power/reset/linkstation-poweroff.c
-+++ b/drivers/power/reset/linkstation-poweroff.c
-@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
- }
- 
- static const struct of_device_id ls_poweroff_of_match[] = {
-+	{ .compatible = "buffalo,ls220d",
-+	  .data = &linkstation_power_off_cfg,
-+	},
-+	{ .compatible = "buffalo,ls220de",
-+	  .data = &linkstation_power_off_cfg,
-+	},
- 	{ .compatible = "buffalo,ls421d",
- 	  .data = &linkstation_power_off_cfg,
- 	},
diff --git a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
deleted file mode 100644
index 7ab735af4c..0000000000
--- a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
+++ /dev/null
@@ -1,279 +0,0 @@
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-
-This patch has been modified to be mvebu specific. The original patch 
-did not pass the bootloader cmdline on if no append-rootblock stanza 
-was found, resulting in blank cmdline and failure to boot.
-
-Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
----
- arch/arm/Kconfig                        | 11 ++++
- arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
- init/main.c                             | 16 +++++
- 3 files changed, 111 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- 	  The command-line arguments provided by the boot loader will be
- 	  appended to the the device tree bootargs property.
- 
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+	bool "Append rootblock parsing bootloader's kernel arguments"
-+	help
-+	  The command-line arguments provided by the boot loader will be
-+	  appended to a new device tree property: bootloader-args.
-+	  If there is a property "append-rootblock" in DT under /chosen 
-+	  and a root= option in bootloaders command line it will be parsed 
-+	  and added to DT bootargs with the form: <append-rootblock>XX.
-+	  Only command line ATAG will be processed, the rest of the ATAGs
-+	  sent by bootloader will be ignored.
-+
- endchoice
- 
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
- 
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- 	return offset;
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- 		   void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- 		return offset;
- 	return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
- 
- static int setprop_string(void *fdt, const char *node_path,
- 			  const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- 	return fdt_setprop_string(fdt, offset, property, string);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- 			const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- 		return offset;
- 	return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
- 
- static const void *getprop(const void *fdt, const char *node_path,
- 			   const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- 	return fdt_getprop(fdt, offset, property, len);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- 	int len;
-@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
- 	return cell_size;
- }
- 
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+	const char *ptr, *end;
-+	const char *root="root=";
-+	int i, l;
-+	const char *rootblock;
-+
-+	//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+	ptr = str - 1;
-+
-+	do {
-+		//first find an 'r' at the begining or after a space
-+		do {
-+			ptr++;
-+			ptr = strchr(ptr, 'r');
-+			if (!ptr)
-+				goto no_append;
-+
-+		} while (ptr != str && *(ptr-1) != ' ');
-+
-+		//then check for the rest
-+		for(i = 1; i <= 4; i++)
-+			if(*(ptr+i) != *(root+i)) break;
-+
-+	} while (i != 5);
-+
-+	end = strchr(ptr, ' ');
-+	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+	//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+	for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+	ptr = end + 1;
-+
-+	/* if append-rootblock property is set use it to append to command line */
-+	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+	if (rootblock == NULL)
-+		goto no_append;
-+
-+	if (*dest != ' ') {
-+		*dest = ' ';
-+		dest++;
-+		len++;
-+	}
-+
-+	if (len + l + i <= COMMAND_LINE_SIZE) {
-+		memcpy(dest, rootblock, l);
-+		dest += l - 1;
-+		memcpy(dest, ptr, i);
-+		dest += i;
-+	}
-+
-+	return dest;
-+
-+no_append:
-+	len = strlen(str);
-+	if (len + 1 < COMMAND_LINE_SIZE) {
-+		memcpy(dest, str, len);
-+		dest += len;
-+	}
-+
-+	return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- 	char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
- 
- 	/* and append the ATAG_CMDLINE */
- 	if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+		//save original bootloader args
-+		//and append ubi.mtd with root partition number to current cmdline
-+		setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+		ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- 		len = strlen(fdt_cmdline);
- 		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- 			*ptr++ = ' ';
- 			memcpy(ptr, fdt_cmdline, len);
- 			ptr += len;
- 		}
-+#endif
- 	}
- 	*ptr = '\0';
- 
- 	setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
- 
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- 	uint32_t digit;
-@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
- 	}
- 	*out = '\0';
- }
-+#endif
- 
- /*
-  * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
- 	struct tag *atag = atag_list;
- 	/* In the case of 64 bits memory size, need to reserve 2 cells for
- 	 * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- 	__be32 mem_reg_property[2 * 2 * NR_BANKS];
--	int memcount = 0;
--	int ret, memsize;
-+	int memsize, memcount = 0;
-+#endif
-+	int ret;
- 
- 	/* make sure we've got an aligned pointer */
- 	if ((u32)atag_list & 0x3)
-@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
- 			else
- 				setprop_string(fdt, "/chosen", "bootargs",
- 					       atag->u.cmdline.cmdline);
--		} else if (atag->hdr.tag == ATAG_MEM) {
-+		}
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+		else if (atag->hdr.tag == ATAG_MEM) {
- 			if (memcount >= sizeof(mem_reg_property)/4)
- 				continue;
- 			if (!atag->u.mem.size)
-@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
- 		setprop(fdt, "/memory", "reg", mem_reg_property,
- 			4 * memcount * memsize);
- 	}
-+#else
-+
-+	}
-+#endif
- 
- 	return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -113,6 +113,10 @@
- 
- #include <kunit/test.h>
- 
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
- 
- extern void init_IRQ(void);
-@@ -994,6 +998,18 @@ asmlinkage __visible void __init __no_sa
- 	page_alloc_init();
- 
- 	pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+	//Show bootloader's original command line for reference
-+	if(of_chosen) {
-+		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+		if(prop)
-+			pr_notice("Bootloader command line (ignored): %s\n", prop);
-+		else
-+			pr_notice("Bootloader command line not present\n");
-+	}
-+#endif
-+
- 	/* parameters may set static keys */
- 	jump_label_init();
- 	parse_early_param();
diff --git a/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch b/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch
deleted file mode 100644
index b75dcf596a..0000000000
--- a/target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
- 	select HAVE_ARM_TWD if SMP
- 	select MACH_MVEBU_V7
- 	select PINCTRL_ARMADA_38X
-+	select ARCH_WANT_LIBATA_LEDS
- 	help
- 	  Say 'Y' here if you want your kernel to support boards based
- 	  on the Marvell Armada 380/385 SoC with device tree.
diff --git a/target/linux/mvebu/patches-6.1/302-add_powertables.patch b/target/linux/mvebu/patches-6.1/302-add_powertables.patch
deleted file mode 100644
index d0c0dbeb0c..0000000000
--- a/target/linux/mvebu/patches-6.1/302-add_powertables.patch
+++ /dev/null
@@ -1,770 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -214,11 +214,19 @@
- &pcie1 {
- 	/* Marvell 88W8864, 5GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,2ghz = <0>;
-+	};
- };
- 
- &pcie2 {
- 	/* Marvell 88W8864, 2GHz-only */
- 	status = "okay";
-+
-+	mwlwifi {
-+		marvell,5ghz = <0>;
-+	};
- };
- 
- &pinctrl {
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
-+			CA =
-+				<36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+			CN =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
-+			ETSI =
-+				<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+				<149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
-+			FCC =
-+				<36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+				<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <2 2>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
-+			CN =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -142,3 +142,205 @@
- 		};
- 	};
- };
-+
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+				<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+				<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+			CA =
-+				<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+			CN =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+				<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+			ETSI =
-+				<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+				<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+			FCC =
-+				<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+				<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+				<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+				<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+				<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+				<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+		};
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+		marvell,powertable {
-+			AU =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			CA =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+			CN =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			ETSI =
-+				<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+				<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+			FCC =
-+				<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+				<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+				<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -157,6 +157,18 @@
- 	};
- };
- 
-+&pcie1 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
-+&pcie2 {
-+	mwlwifi {
-+		marvell,chainmask = <4 4>;
-+	};
-+};
-+
- &sdhci {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&sdhci_pins>;
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -223,12 +223,100 @@
- 	pcie@2,0 {
- 		/* Port 0, Lane 1 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,5ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
-+
-+				ETSI =
-+					<1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+					<13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
-+			};
-+		};
- 	};
- 
- 	/* Second mini-PCIe port */
- 	pcie@3,0 {
- 		/* Port 0, Lane 3 */
- 		status = "okay";
-+
-+		mwlwifi {
-+			marvell,2ghz = <0>;
-+			marvell,chainmask = <4 4>;
-+			marvell,powertable {
-+				FCC =
-+					<36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+					<52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+					<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+					<149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+					<165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
-+
-+				ETSI =
-+					<36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+					<149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
-+			};
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch b/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch
deleted file mode 100644
index 930c0f9494..0000000000
--- a/target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -237,12 +237,10 @@
- };
- 
- &i2c0 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11000 0x100>;
- };
- 
- &i2c1 {
--	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- 	reg = <0x11100 0x100>;
- };
- 
diff --git a/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch
deleted file mode 100644
index 31bd53b1f3..0000000000
--- a/target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-rd.dts
-+++ b/arch/arm/boot/dts/armada-388-rd.dts
-@@ -103,6 +103,16 @@
- 		compatible = "st,m25p128", "jedec,spi-nor";
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <108000000>;
-+
-+		partition@0 {
-+			label = "uboot";
-+			reg = <0 0x400000>;
-+		};
-+
-+		partition@1 {
-+			label = "firmware";
-+			reg = <0x400000 0xc00000>;
-+		};
- 	};
- };
- 
diff --git a/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch
deleted file mode 100644
index aee033d21f..0000000000
--- a/target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 13 Jan 2015 11:14:09 +0100
-Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/armada-385-db-ap.dts
-+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
-@@ -218,19 +218,19 @@
- 			#size-cells = <1>;
- 
- 			partition@0 {
--				label = "U-Boot";
-+				label = "u-boot";
- 				reg = <0x00000000 0x00800000>;
- 				read-only;
- 			};
- 
- 			partition@800000 {
--				label = "uImage";
-+				label = "kernel";
- 				reg = <0x00800000 0x00400000>;
- 				read-only;
- 			};
- 
- 			partition@c00000 {
--				label = "Root";
-+				label = "ubi";
- 				reg = <0x00c00000 0x3f400000>;
- 			};
- 		};
diff --git a/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch
deleted file mode 100644
index fc6d6239ca..0000000000
--- a/target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -483,3 +483,7 @@
- 		};
- 	};
- };
-+
-+&coherencyfab {
-+	broken-idle;
-+};
diff --git a/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch b/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch
deleted file mode 100644
index 389e03742e..0000000000
--- a/target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -385,7 +385,7 @@
- 
- 			port@4 {
- 				reg = <4>;
--				label = "internet";
-+				label = "wan";
- 			};
- 
- 			port@5 {
diff --git a/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch b/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch
deleted file mode 100644
index 0ef15f2943..0000000000
--- a/target/linux/mvebu/patches-6.1/309-linksys-status-led.patch
+++ /dev/null
@@ -1,50 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -14,6 +14,13 @@
- 	compatible = "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial0:115200n8";
- 	};
-@@ -71,7 +78,7 @@
- 		pinctrl-0 = <&gpio_leds_pins>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
- 		};
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -26,6 +26,13 @@
- 	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- 		     "marvell,armadaxp", "marvell,armada-370-xp";
- 
-+	aliases {
-+		led-boot = &led_power;
-+		led-failsafe = &led_power;
-+		led-running = &led_power;
-+		led-upgrade = &led_power;
-+	};
-+
- 	chosen {
- 		bootargs = "console=ttyS0,115200";
- 		stdout-path = &uart0;
-@@ -195,7 +202,7 @@
- 		pinctrl-0 = <&power_led_pin>;
- 		pinctrl-names = "default";
- 
--		power {
-+		led_power: power {
- 			label = "mamba:white:power";
- 			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- 			default-state = "on";
diff --git a/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch b/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch
deleted file mode 100644
index 84d49a004b..0000000000
--- a/target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -116,7 +116,7 @@
- };
- 
- &eth2 {
--	status = "okay";
-+	status = "disabled";
- 	phy-mode = "sgmii";
- 	buffer-manager = <&bm>;
- 	bm,pool-long = <2>;
-@@ -200,10 +200,10 @@
- 				label = "wan";
- 			};
- 
--			port@5 {
--				reg = <5>;
-+			port@6 {
-+				reg = <6>;
- 				label = "cpu";
--				ethernet = <&eth2>;
-+				ethernet = <&eth0>;
- 
- 				fixed-link {
- 					speed = <1000>;
diff --git a/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch b/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch
deleted file mode 100644
index a5d3e63810..0000000000
--- a/target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -12,8 +12,8 @@
- 
- / {
- 	model = "Linksys WRT3200ACM";
--	compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -22,9 +22,10 @@
- #include "armada-xp-mv78230.dtsi"
- 
- / {
--	model = "Linksys WRT1900AC";
--	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
--		     "marvell,armadaxp", "marvell,armada-370-xp";
-+	model = "Linksys WRT1900AC v1";
-+	compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
-+		     "marvell,armadaxp-mv78230", "marvell,armadaxp",
-+		     "marvell,armada-370-xp";
- 
- 	aliases {
- 		led-boot = &led_power;
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -9,8 +9,9 @@
- #include "armada-385-linksys.dtsi"
- 
- / {
--	model = "Linksys WRT1900ACv2";
--	compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
-+	model = "Linksys WRT1900AC v2";
-+	compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -10,8 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1200AC";
--	compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
--		     "marvell,armada380";
-+	compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
-+		     "marvell,armada385", "marvell,armada380";
- };
- 
- &expander0 {
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -10,7 +10,8 @@
- 
- / {
- 	model = "Linksys WRT1900ACS";
--	compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
-+	compatible = "linksys,wrt1900acs", "linksys,shelby",
-+		     "linksys,armada385", "marvell,armada385",
- 		     "marvell,armada380";
- };
- 
diff --git a/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
deleted file mode 100644
index f52417e83a..0000000000
--- a/target/linux/mvebu/patches-6.1/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 29 Nov 2016 10:15:45 +0000
-Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- .../arm/boot/dts/armada-388-clearfog-base.dts |  1 +
- .../armada-38x-solidrun-microsom-emmc.dtsi    | 62 +++++++++++++++++++
- 2 files changed, 63 insertions(+)
- create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
-@@ -7,6 +7,7 @@
- 
- /dts-v1/;
- #include "armada-388-clearfog.dtsi"
-+#include "armada-38x-solidrun-microsom-emmc.dtsi"
- 
- / {
- 	model = "SolidRun Clearfog Base A1";
---- /dev/null
-+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-@@ -0,0 +1,62 @@
-+/*
-+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
-+ *
-+ *  Copyright (C) 2015 Russell King
-+ *
-+ * This board is in development; the contents of this file work with
-+ * the A1 rev 2.0 of the board, which does not represent final
-+ * production board.  Things will change, don't expect this file to
-+ * remain compatible info the future.
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This file is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License
-+ *     version 2 as published by the Free Software Foundation.
-+ *
-+ *     This file is distributed in the hope that it will be useful
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/ {
-+	soc {
-+		internal-regs {
-+			sdhci@d8000 {
-+				bus-width = <4>;
-+				no-1-8-v;
-+				non-removable;
-+				pinctrl-0 = <&microsom_sdhci_pins>;
-+				pinctrl-names = "default";
-+				status = "okay";
-+				wp-inverted;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch b/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch
deleted file mode 100644
index 607f436297..0000000000
--- a/target/linux/mvebu/patches-6.1/313-helios4-dts-status-led-alias.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/arm/boot/dts/armada-388-helios4.dts
-+++ b/arch/arm/boot/dts/armada-388-helios4.dts
-@@ -15,6 +15,13 @@
- 	model = "Helios4";
- 	compatible = "kobol,helios4", "marvell,armada388",
- 		"marvell,armada385", "marvell,armada380";
-+		
-+	aliases {
-+		led-boot = &led_status;
-+		led-failsafe = &led_status;
-+		led-running = &led_status;
-+		led-upgrade = &led_status;
-+	};
- 
- 	memory {
- 		device_type = "memory";
-@@ -73,10 +80,9 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&helios_system_led_pins>;
- 
--		status-led {
-+		led_status: status-led {
- 			label = "helios4:green:status";
- 			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
--			linux,default-trigger = "heartbeat";
- 			default-state = "on";
- 		};
- 
diff --git a/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch b/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
deleted file mode 100644
index 7221e04de1..0000000000
--- a/target/linux/mvebu/patches-6.1/314-arm64-dts-marvell-enable-heartbeat-LED-by-default.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
-Date: Fri, 7 Jul 2023 19:06:05 +0200
-Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default
-
-Some boards could be placed in an enclosure, so enable LED18 by default,
-since that'll be the only visible indicator that the board is operating.
-
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
----
- arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-@@ -25,6 +25,7 @@
- 			function = LED_FUNCTION_HEARTBEAT;
- 			color = <LED_COLOR_ID_GREEN>;
- 			linux,default-trigger = "heartbeat";
-+			default-state = "on";
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch b/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch
deleted file mode 100644
index c333df2784..0000000000
--- a/target/linux/mvebu/patches-6.1/315-armada-xp-linksys-mamba-resize-kernel.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
-From: Tad <tad@spotco.us>
-Date: Fri, 5 Feb 2021 22:32:11 -0500
-Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
- partition to 4MB
-
-Signed-off-by: Tad Davanzo <tad@spotco.us>
----
- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -454,9 +454,9 @@
- 				reg = <0xa00000 0x2800000>;  /* 40MB */
- 			};
- 
--			partition@d00000 {
-+			partition@e00000 {
- 				label = "rootfs1";
--				reg = <0xd00000 0x2500000>;  /* 37MB */
-+				reg = <0xe00000 0x2400000>;  /* 36MB */
- 			};
- 
- 			/* kernel2 overlaps with rootfs2 by design */
-@@ -465,9 +465,9 @@
- 				reg = <0x3200000 0x2800000>; /* 40MB */
- 			};
- 
--			partition@3500000 {
-+			partition@3600000 {
- 				label = "rootfs2";
--				reg = <0x3500000 0x2500000>; /* 37MB */
-+				reg = <0x3600000 0x2400000>; /* 36MB */
- 			};
- 
- 			/*
diff --git a/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch
deleted file mode 100644
index b5ed5ece36..0000000000
--- a/target/linux/mvebu/patches-6.1/316-armada-370-dts-fix-crypto-engine.patch
+++ /dev/null
@@ -1,29 +0,0 @@
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -254,7 +254,7 @@
- 				clocks = <&gateclk 23>;
- 				clock-names = "cesa0";
- 				marvell,crypto-srams = <&crypto_sram>;
--				marvell,crypto-sram-size = <0x7e0>;
-+				marvell,crypto-sram-size = <0x800>;
- 			};
- 		};
- 
-@@ -275,12 +275,17 @@
- 			 * cpuidle workaround.
- 			 */
- 			idle-sram@0 {
-+				status = "disabled";
- 				reg = <0x0 0x20>;
- 			};
- 		};
- 	};
- };
- 
-+&coherencyfab {
-+	broken-idle;
-+};
-+
- /*
-  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
-  * board level if a different configuration is used.
diff --git a/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch b/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
deleted file mode 100644
index 280fc5957e..0000000000
--- a/target/linux/mvebu/patches-6.1/320-arm-dts-armada-370-synology-ds213j-mtd-parts.patch
+++ /dev/null
@@ -1,134 +0,0 @@
---- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-@@ -31,6 +31,7 @@
- 
- 	chosen {
- 		stdout-path = "serial0:115200n8";
-+		append-rootblock = "nullparameter="; /* override the bootloader args */
- 	};
- 
- 	memory@0 {
-@@ -94,6 +95,8 @@
- 			       status = "okay";
- 			       phy = <&phy1>;
- 			       phy-mode = "sgmii";
-+		               nvmem-cells = <&macaddr_vendor_0>;
-+        		       nvmem-cell-names = "mac-address";
- 			};
- 
- 			sata@a0000 {
-@@ -175,6 +178,24 @@
- 			gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
-+
-+	virtual_flash {
-+		compatible = "mtd-concat";
-+
-+		devices = <&mtd_kernel &mtd_gap &mtd_gap2>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				compatible = "openwrt,uimage", "denx,uimage";
-+				label = "firmware";
-+				reg = <0x0 0x0>;
-+			};
-+		};
-+	};
- };
- 
- &mdio {
-@@ -265,48 +286,52 @@
- 		reg = <0>; /* Chip select 0 */
- 		spi-max-frequency = <20000000>;
- 
--		/*
--		 * Warning!
--		 *
--		 * Synology u-boot uses its compiled-in environment
--		 * and it seems Synology did not care to change u-boot
--		 * default configuration in order to allow saving a
--		 * modified environment at a sensible location. So,
--		 * if you do a 'saveenv' under u-boot, your modified
--		 * environment will be saved at 1MB after the start
--		 * of the flash, i.e. in the middle of the uImage.
--		 * For that reason, it is strongly advised not to
--		 * change the default environment, unless you know
--		 * what you are doing.
--		 */
--		partition@0 { /* u-boot */
--			label = "RedBoot";
--			reg = <0x00000000 0x000c0000>; /* 768KB */
--		};
-+		partitions {
-+			compatible = "fixed-partitions";
- 
--		partition@c0000 { /* uImage */
--			label = "zImage";
--			reg = <0x000c0000 0x002d0000>; /* 2880KB */
--		};
-+			partition@0 { /* u-boot */
-+				label = "u-boot";
-+				reg = <0x00000000 0x000c0000>; /* 768KB */
-+				read-only;
-+			};
- 
--		partition@390000 { /* uInitramfs */
--			label = "rd.gz";
--			reg = <0x00390000 0x00440000>; /* 4250KB */
--		};
-+			mtd_gap: partition@c0000 { /* gap */
-+				label = "gap";
-+				reg = <0x000c0000 0x00040000>; /* 256KB */
-+			};
- 
--		partition@7d0000 { /* MAC address and serial number */
--			label = "vendor";
--			reg = <0x007d0000 0x00010000>; /* 64KB */
--		};
-+			partition@100000 { /* u-boot-env */
-+				label = "u-boot-env";
-+				reg = <0x00100000 0x00010000>; /* 64KB */
-+			};
- 
--		partition@7e0000 {
--			label = "RedBoot config";
--			reg = <0x007e0000 0x00010000>; /* 64KB */
--		};
-+			mtd_kernel: partition@110000 {
-+				label = "kernel";
-+				reg = <0x00110000 0x006c0000>; /* 6912KB */
-+			};
- 
--		partition@7f0000 {
--			label = "FIS directory";
--			reg = <0x007f0000 0x00010000>; /* 64KB */
-+			partition@7d0000 { /* MAC address and serial number */
-+				reg = <0x007d0000 0x00010000>; /* 64KB */
-+				label = "vendor";
-+				read-only;
-+
-+				compatible = "nvmem-cells";
-+
-+				nvmem-layout {
-+					compatible = "fixed-layout";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					macaddr_vendor_0: macaddr@0 {
-+						reg = <0x0 0x6>;
-+					};
-+				};
-+			};
-+
-+			mtd_gap2: partition@7e0000 {
-+				label = "gap2";
-+				reg = <0x007e0000 0x00020000>; /* 128KB */
-+			};
- 		};
- 	};
- };
diff --git a/target/linux/mvebu/patches-6.1/400-find_active_root.patch b/target/linux/mvebu/patches-6.1/400-find_active_root.patch
deleted file mode 100644
index 90164adcd4..0000000000
--- a/target/linux/mvebu/patches-6.1/400-find_active_root.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-The WRT1900AC among other Linksys routers uses a dual-firmware layout.
-Dynamically rename the active partition to "ubi".
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
---- a/drivers/mtd/parsers/ofpart_core.c
-+++ b/drivers/mtd/parsers/ofpart_core.c
-@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
- 	return of_get_property(pp, "compatible", NULL);
- }
- 
-+static int mangled_rootblock;
-+
- static int parse_fixed_partitions(struct mtd_info *master,
- 				  const struct mtd_partition **pparts,
- 				  struct mtd_part_parser_data *data)
-@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
- 	struct device_node *mtd_node;
- 	struct device_node *ofpart_node;
- 	const char *partname;
-+	const char *owrtpart = "ubi";
- 	struct device_node *pp;
- 	int nr_parts, i, ret = 0;
- 	bool dedicated = true;
-@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct
- 		parts[i].size = of_read_number(reg + a_cells, s_cells);
- 		parts[i].of_node = pp;
- 
--		partname = of_get_property(pp, "label", &len);
--		if (!partname)
--			partname = of_get_property(pp, "name", &len);
-+		if (mangled_rootblock && (i == mangled_rootblock)) {
-+			partname = owrtpart;
-+		} else {
-+			partname = of_get_property(pp, "label", &len);
-+			if (!partname)
-+				partname = of_get_property(pp, "name", &len);
-+		}
- 		parts[i].name = partname;
- 
- 		if (of_get_property(pp, "read-only", &len))
-@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi
- 	return 0;
- }
- 
-+static int __init active_root(char *str)
-+{
-+	get_option(&str, &mangled_rootblock);
-+
-+	if (!mangled_rootblock)
-+		return 1;
-+
-+	return 1;
-+}
-+
-+__setup("mangled_rootblock=", active_root);
-+
- static void __exit ofpart_parser_exit(void)
- {
- 	deregister_mtd_parser(&ofpart_parser);
diff --git a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
deleted file mode 100644
index 14f93592fe..0000000000
--- a/target/linux/mvebu/patches-6.1/700-mvneta-tx-queue-workaround.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Subject: mvneta: tx queue workaround
-
-The hardware queue scheduling is apparently configured with fixed
-priorities, which creates a nasty fairness issue where traffic from one
-CPU can starve traffic from all other CPUs.
-
-Work around this issue by forcing all tx packets to go through one CPU,
-until this issue is fixed properly.
-
-Ref: https://github.com/openwrt/openwrt/issues/5411
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de
- 	}
- }
- 
-+#ifndef CONFIG_ARM64
-+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
-+			       struct net_device *sb_dev)
-+{
-+	/* XXX: hardware queue scheduling is broken,
-+	 * use only one queue until it is fixed */
-+	return 0;
-+}
-+#endif
-+
- static const struct net_device_ops mvneta_netdev_ops = {
- 	.ndo_open            = mvneta_open,
- 	.ndo_stop            = mvneta_stop,
-@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet
- 	.ndo_fix_features    = mvneta_fix_features,
- 	.ndo_get_stats64     = mvneta_get_stats64,
- 	.ndo_eth_ioctl        = mvneta_ioctl,
-+#ifndef CONFIG_ARM64
-+	.ndo_select_queue    = mvneta_select_queue,
-+#endif
- 	.ndo_bpf	     = mvneta_xdp,
- 	.ndo_xdp_xmit        = mvneta_xdp_xmit,
- 	.ndo_setup_tc	     = mvneta_setup_tc,
diff --git a/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch b/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch
deleted file mode 100644
index 1c4194776a..0000000000
--- a/target/linux/mvebu/patches-6.1/701-mvpp2-read-mac-address-from-nvmem.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Tobias Schramm <tobias@t-sys.eu>
-Subject: mvpp2: support fetching mac address from nvmem
-
-The mvpp2 driver did not query nvmem for hardware mac addresses. This
-patch adds querying of mac addresses stored in nvmem cells as a further
-fallback option before assigning a random address.
-Purposely added separately to fwnode_get_mac_address() above to maintain
-existing behaviour with builtin adapter mac address still taking
-precedence.
-
-Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
----
---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -6134,6 +6134,12 @@ static void mvpp2_port_copy_mac_addr(str
- 		}
- 	}
- 
-+	if (!of_get_mac_address(to_of_node(fwnode), hw_mac_addr)) {
-+		*mac_from = "nvmem cell";
-+		eth_hw_addr_set(dev, hw_mac_addr);
-+		return;
-+	}
-+
- 	*mac_from = "random";
- 	eth_hw_addr_random(dev);
- }
diff --git a/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
deleted file mode 100644
index 29f36be460..0000000000
--- a/target/linux/mvebu/patches-6.1/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@arm.linux.org.uk>
-Date: Sat, 3 Oct 2015 09:13:05 +0100
-Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
-
-The cpuidle ->enter method expects the return value to be the sleep
-state we entered.  Returning negative numbers or other codes is not
-permissible since coupled CPU idle was merged.
-
-At least some of the mvebu_v7_cpu_suspend() implementations return the
-value from cpu_suspend(), which returns zero if the CPU vectors back
-into the kernel via cpu_resume() (the success case), or the non-zero
-return value of the suspend actor, or one (failure cases).
-
-We do not want to be returning the failure case value back to CPU idle
-as that indicates that we successfully entered one of the deeper idle
-states.  Always return zero instead, indicating that we slept for the
-shortest amount of time.
-
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
----
- drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/cpuidle/cpuidle-mvebu-v7.c
-+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
-@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
- 	ret = mvebu_v7_cpu_suspend(deepidle);
- 	cpu_pm_exit();
- 
-+	/*
-+	 * If we failed to enter the desired state, indicate that we
-+	 * slept lightly.
-+	 */
- 	if (ret)
--		return ret;
-+		return 0;
- 
- 	return index;
- }
diff --git a/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch
deleted file mode 100644
index d2995b375c..0000000000
--- a/target/linux/mvebu/patches-6.1/801-pci-mvebu-time-out-reset-on-link-up.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Sat, 9 Jul 2016 10:58:16 +0100
-Subject: pci: mvebu: time out reset on link up
-
-If the port reports that the link is up while we are resetting, there's
-little point in waiting for the full duration.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
---- a/drivers/pci/controller/pci-mvebu.c
-+++ b/drivers/pci/controller/pci-mvebu.c
-@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve
- 
- 	if (port->reset_gpio) {
- 		u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
-+		unsigned int i;
- 
- 		of_property_read_u32(port->dn, "reset-delay-us",
- 				     &reset_udelay);
-@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve
- 		udelay(100);
- 
- 		gpiod_set_value_cansleep(port->reset_gpio, 0);
--		msleep(reset_udelay / 1000);
-+		for (i = 0; i < reset_udelay; i += 1000) {
-+			if (mvebu_pcie_link_up(port))
-+				break;
-+			msleep(1);
-+		}
-+
-+		printk("%s: reset completed in %dus\n", port->name, i);
- 	}
- 
- 	return 0;
-@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf
- 		if (!child)
- 			continue;
- 
--		ret = mvebu_pcie_powerup(port);
--		if (ret < 0)
--			continue;
--
- 		port->base = mvebu_pcie_map_registers(pdev, child, port);
- 		if (IS_ERR(port->base)) {
- 			dev_err(dev, "%s: cannot map registers\n", port->name);
- 			port->base = NULL;
--			mvebu_pcie_powerdown(port);
-+			continue;
-+		}
-+
-+		ret = mvebu_pcie_powerup(port);
-+		if (ret < 0) {
-+			port->base = NULL;
- 			continue;
- 		}
- 
diff --git a/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
deleted file mode 100644
index fc5c804582..0000000000
--- a/target/linux/mvebu/patches-6.1/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch
+++ /dev/null
@@ -1,218 +0,0 @@
-From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:32 +0000
-Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803
- PUZZLE driver bindings
-
-Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED
-drivers. A new vendor prefix is also added accordingly for
-IEI Integration Corp.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei,wt61p803-puzzle-hwmon.yaml      | 53 ++++++++++++
- .../leds/iei,wt61p803-puzzle-leds.yaml        | 39 +++++++++
- .../bindings/mfd/iei,wt61p803-puzzle.yaml     | 82 +++++++++++++++++++
- .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
- 4 files changed, 176 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
- create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
- create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-@@ -0,0 +1,53 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The HWMON module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-hwmon
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+patternProperties:
-+  "^fan-group@[0-1]$":
-+    type: object
-+    properties:
-+      reg:
-+        minimum: 0
-+        maximum: 1
-+        description:
-+          Fan group ID
-+
-+      cooling-levels:
-+        minItems: 1
-+        maxItems: 255
-+        description:
-+          Cooling levels for the fans (PWM value mapping)
-+    description: |
-+      Properties for each fan group.
-+    required:
-+      - reg
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-@@ -0,0 +1,39 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+  The LED module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle-leds
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 0
-+
-+  led@0:
-+    type: object
-+    $ref: common.yaml
-+    description: |
-+      Properties for a single LED.
-+
-+required:
-+  - compatible
-+  - "#address-cells"
-+  - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-@@ -0,0 +1,82 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
-+
-+maintainers:
-+  - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+  IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
-+  It's used for controlling system power states, fans, LEDs and temperature
-+  sensors.
-+
-+  For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
-+  binding documents under the respective subsystem directories.
-+
-+properties:
-+  compatible:
-+    const: iei,wt61p803-puzzle
-+
-+  current-speed:
-+    description:
-+      Serial bus speed in bps
-+    maxItems: 1
-+
-+  enable-beep: true
-+
-+  hwmon:
-+    $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+
-+  leds:
-+    $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
-+
-+required:
-+  - compatible
-+  - current-speed
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/leds/common.h>
-+    serial {
-+        mcu {
-+            compatible = "iei,wt61p803-puzzle";
-+            current-speed = <115200>;
-+            enable-beep;
-+
-+            leds {
-+                compatible = "iei,wt61p803-puzzle-leds";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                led@0 {
-+                    reg = <0>;
-+                    function = LED_FUNCTION_POWER;
-+                    color = <LED_COLOR_ID_BLUE>;
-+                };
-+            };
-+
-+            hwmon {
-+                compatible = "iei,wt61p803-puzzle-hwmon";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+
-+                fan-group@0 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x00>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+
-+                fan-group@1 {
-+                    #cooling-cells = <2>;
-+                    reg = <0x01>;
-+                    cooling-levels = <64 102 170 230 250>;
-+                };
-+            };
-+        };
-+    };
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -579,6 +579,8 @@ patternProperties:
-     description: IC Plus Corp.
-   "^idt,.*":
-     description: Integrated Device Technologies, Inc.
-+  "^iei,.*":
-+    description: IEI Integration Corp.
-   "^ifi,.*":
-     description: Ingenieurburo Fur Ic-Technologie (I/F/I)
-   "^ilitek,.*":
diff --git a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
deleted file mode 100644
index 47d9e3a263..0000000000
--- a/target/linux/mvebu/patches-6.1/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch
+++ /dev/null
@@ -1,1034 +0,0 @@
-From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:33 +0000
-Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU
-
-Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some
-IEI Puzzle series devices. The microcontroller controls system power,
-temperature sensors, fans and LEDs.
-
-This driver implements the core functionality for device communication
-over the system serial (serdev bus). It handles MCU messages and the
-internal MCU properties. Some properties can be managed over sysfs.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mfd/Kconfig                     |   9 +
- drivers/mfd/Makefile                    |   1 +
- drivers/mfd/iei-wt61p803-puzzle.c       | 908 ++++++++++++++++++++++++
- include/linux/mfd/iei-wt61p803-puzzle.h |  66 ++
- 4 files changed, 984 insertions(+)
- create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
- create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
-
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -2222,6 +2222,15 @@ config SGI_MFD_IOC3
- 	  If you have an SGI Origin, Octane, or a PCI IOC3 card,
- 	  then say Y. Otherwise say N.
- 
-+config MFD_IEI_WT61P803_PUZZLE
-+	tristate "IEI WT61P803 PUZZLE MCU driver"
-+	depends on SERIAL_DEV_BUS
-+	select MFD_CORE
-+	help
-+	  IEI WT61P803 PUZZLE is a system power management microcontroller
-+	  used for fan control, temperature sensor reading, LED control
-+	  and system identification.
-+
- config MFD_INTEL_M10_BMC
- 	tristate "Intel MAX 10 Board Management Controller"
- 	depends on SPI_MASTER
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -244,6 +244,7 @@ obj-$(CONFIG_MFD_RT4831)	+= rt4831.o
- obj-$(CONFIG_MFD_RT5033)	+= rt5033.o
- obj-$(CONFIG_MFD_RT5120)	+= rt5120.o
- obj-$(CONFIG_MFD_SKY81452)	+= sky81452.o
-+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE)  += iei-wt61p803-puzzle.o
- 
- obj-$(CONFIG_INTEL_SOC_PMIC)		+= intel_soc_pmic_crc.o
- obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC)	+= intel_soc_pmic_bxtwc.o
---- /dev/null
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -0,0 +1,908 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/delay.h>
-+#include <linux/export.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/core.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/property.h>
-+#include <linux/sched.h>
-+#include <linux/serdev.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <asm/unaligned.h>
-+
-+/* start, payload and XOR checksum at end */
-+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH	(1 + 20 + 1)
-+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE	512
-+
-+#define IEI_WT61P803_PUZZLE_MAC_LENGTH			17
-+#define IEI_WT61P803_PUZZLE_SN_LENGTH			36
-+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH		 6
-+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH		16
-+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH	 8
-+#define IEI_WT61P803_PUZZLE_NB_MAC			 8
-+
-+/* Use HZ as a timeout value throughout the driver */
-+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ
-+
-+enum iei_wt61p803_puzzle_attribute_type {
-+	IEI_WT61P803_PUZZLE_VERSION,
-+	IEI_WT61P803_PUZZLE_BUILD_INFO,
-+	IEI_WT61P803_PUZZLE_BOOTLOADER_MODE,
-+	IEI_WT61P803_PUZZLE_PROTOCOL_VERSION,
-+	IEI_WT61P803_PUZZLE_SERIAL_NUMBER,
-+	IEI_WT61P803_PUZZLE_MAC_ADDRESS,
-+	IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS,
-+	IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY,
-+	IEI_WT61P803_PUZZLE_POWER_STATUS,
-+};
-+
-+struct iei_wt61p803_puzzle_device_attribute {
-+	struct device_attribute dev_attr;
-+	enum iei_wt61p803_puzzle_attribute_type type;
-+	u8 index;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state
-+ * @ac_recovery_status_flag:	AC Recovery Status Flag
-+ * @power_loss_recovery:	System recovery after power loss
-+ * @power_status:		System Power-on Method
-+ */
-+struct iei_wt61p803_puzzle_mcu_status {
-+	u8 ac_recovery_status_flag;
-+	u8 power_loss_recovery;
-+	u8 power_status;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_reply - MCU reply
-+ * @size:	Size of the MCU reply
-+ * @data:	Full MCU reply buffer
-+ * @state:	Current state of the packet
-+ * @received:	Was the response fullfilled
-+ */
-+struct iei_wt61p803_puzzle_reply {
-+	size_t size;
-+	unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE];
-+	struct completion received;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status
-+ * @version:		Primary firmware version
-+ * @build_info:		Build date and time
-+ * @bootloader_mode:	Status of the MCU operation
-+ * @protocol_version:	MCU communication protocol version
-+ * @serial_number:	Device factory serial number
-+ * @mac_address:	Device factory MAC addresses
-+ *
-+ * Last element of arrays is reserved for '\0'.
-+ */
-+struct iei_wt61p803_puzzle_mcu_version {
-+	char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1];
-+	char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1];
-+	bool bootloader_mode;
-+	char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1];
-+	char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1];
-+	char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver
-+ * @serdev:		Pointer to underlying serdev device
-+ * @dev:		Pointer to underlying dev device
-+ * @reply_lock:		Reply mutex lock
-+ * @reply:		Pointer to the iei_wt61p803_puzzle_reply struct
-+ * @version:		MCU version related data
-+ * @status:		MCU status related data
-+ * @response_buffer	Command response buffer allocation
-+ * @lock		General member mutex lock
-+ */
-+struct iei_wt61p803_puzzle {
-+	struct serdev_device *serdev;
-+	struct device *dev;
-+	struct mutex reply_lock; /* lock to prevent multiple firmware calls */
-+	struct iei_wt61p803_puzzle_reply *reply;
-+	struct iei_wt61p803_puzzle_mcu_version version;
-+	struct iei_wt61p803_puzzle_mcu_status status;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* lock to protect response buffer */
-+};
-+
-+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len)
-+{
-+	unsigned char checksum = 0;
-+	size_t i;
-+
-+	for (i = 0; i < len; i++)
-+		checksum ^= buf[i];
-+	return checksum;
-+}
-+
-+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu,
-+					    const unsigned char *raw_resp_data, size_t size)
-+{
-+	unsigned char checksum;
-+
-+	/* Check the incoming frame header */
-+	if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START ||
-+	      raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER ||
-+	     (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM &&
-+	      raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) {
-+		if (mcu->reply->size + size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Append the frame to existing data */
-+		memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size);
-+		mcu->reply->size += size;
-+	} else {
-+		if (size >= sizeof(mcu->reply->data))
-+			return -EIO;
-+
-+		/* Start processing a new frame */
-+		memcpy(mcu->reply->data, raw_resp_data, size);
-+		mcu->reply->size = size;
-+	}
-+
-+	checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1);
-+	if (checksum != mcu->reply->data[mcu->reply->size - 1]) {
-+		/* The checksum isn't matched yet, wait for new frames */
-+		return size;
-+	}
-+
-+	/* Received all the data */
-+	complete(&mcu->reply->received);
-+
-+	return size;
-+}
-+
-+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev,
-+					const unsigned char *data, size_t size)
-+{
-+	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
-+	int ret;
-+
-+	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
-+	/* Return the number of processed bytes if function returns error,
-+	 * discard the remaining incoming data, since the frame this data
-+	 * belongs to is broken anyway
-+	 */
-+	if (ret < 0)
-+		return size;
-+
-+	return ret;
-+}
-+
-+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = {
-+	.receive_buf  = iei_wt61p803_puzzle_recv_buf,
-+	.write_wakeup = serdev_device_write_wakeup,
-+};
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ * @reply_size: Pointer to size_t (size of reply_data)
-+ * @retry_count: Number of times to retry sending the command to the MCU
-+ */
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data,
-+					       size_t *reply_size, int retry_count)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret, i;
-+
-+	for (i = 0; i < retry_count; i++) {
-+		ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size,
-+							reply_data, reply_size);
-+		if (ret != -ETIMEDOUT)
-+			return ret;
-+	}
-+
-+	dev_err(dev, "Command response timed out. Retries: %d\n", retry_count);
-+
-+	return -ETIMEDOUT;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog);
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ *
-+ * Sends a structured command to the MCU.
-+ */
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data,
-+				      size_t *reply_size)
-+{
-+	struct device *dev = &mcu->serdev->dev;
-+	int ret;
-+
-+	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
-+		return -EINVAL;
-+
-+	mutex_lock(&mcu->reply_lock);
-+
-+	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
-+
-+	/* Initialize reply struct */
-+	reinit_completion(&mcu->reply->received);
-+	mcu->reply->size = 0;
-+	usleep_range(2000, 10000);
-+	serdev_device_write_flush(mcu->serdev);
-+	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+	if (ret < 0)
-+		goto exit;
-+
-+	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	ret = wait_for_completion_timeout(&mcu->reply->received,
-+					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+	if (ret == 0) {
-+		dev_err(dev, "Command reply receive timeout\n");
-+		ret = -ETIMEDOUT;
-+		goto exit;
-+	}
-+
-+	*reply_size = mcu->reply->size;
-+	/* Copy the received data, as it will not be available after a new frame is received */
-+	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
-+	ret = 0;
-+exit:
-+	mutex_unlock(&mcu->reply_lock);
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command);
-+
-+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char buzzer_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE;
-+	buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION,
-+	};
-+	unsigned char build_info_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD,
-+	};
-+	unsigned char bootloader_mode_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE,
-+	};
-+	unsigned char protocol_version_cmd[3] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION,
-+	};
-+	unsigned char *rb = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd),
-+						rb, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 7) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd,
-+						sizeof(build_info_cmd),	rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 15) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c",
-+		rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11],
-+		rb[12], rb[13]);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd,
-+						sizeof(bootloader_mode_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS)
-+		mcu->version.bootloader_mode = false;
-+	else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER)
-+		mcu->version.bootloader_mode = true;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd,
-+						sizeof(protocol_version_cmd), rb,
-+						&reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size < 9) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c",
-+		rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char mcu_status_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+		IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+	};
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	if (reply_size < 20) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Response format:
-+	 * (IDX	RESPONSE)
-+	 * 0	@
-+	 * 1	O
-+	 * 2	S
-+	 * 3	S
-+	 * ...
-+	 * 5	AC Recovery Status Flag
-+	 * ...
-+	 * 10	Power Loss Recovery
-+	 * ...
-+	 * 19	Power Status (system power on method)
-+	 * 20	XOR checksum
-+	 */
-+	if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	    resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER &&
-+	    resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS &&
-+	    resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) {
-+		mcu->status.ac_recovery_status_flag = resp_buf[5];
-+		mcu->status.power_loss_recovery = resp_buf[10];
-+		mcu->status.power_status = resp_buf[19];
-+	}
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x24,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+						sizeof(serial_number_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu,
-+						   unsigned char serial_number[36])
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char serial_number_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0xC,	/* Data length */
-+	};
-+	unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */
-+	int ret, sn_counter;
-+	size_t reply_size;
-+
-+	/* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */
-+	mutex_lock(&mcu->lock);
-+	for (sn_counter = 0; sn_counter < 3; sn_counter++) {
-+		serial_number_header[2] = 0x0 + 0xC * sn_counter;
-+
-+		memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header));
-+		memcpy(serial_number_cmd + sizeof(serial_number_header),
-+		       serial_number + 0xC * sn_counter, 0xC);
-+
-+		ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+							sizeof(serial_number_cmd),
-+							resp_buf, &reply_size);
-+		if (ret)
-+			goto err;
-+		if (reply_size != 3) {
-+			ret = -EIO;
-+			goto err;
-+		}
-+		if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+		      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+		      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+			ret = -EPROTO;
-+			goto err;
-+		}
-+	}
-+
-+	sprintf(mcu->version.serial_number, "%.*s",
-+		IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_cmd[5] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+		0x00,	/* EEPROM read address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu->lock);
-+	mac_address_cmd[2] = 0x24 + 0x11 * index;
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+
-+	if (reply_size < 22) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[index], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int
-+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH],
-+				      int mac_address_idx)
-+{
-+	unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char mac_address_header[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+		IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+		0x00,	/* EEPROM write address */
-+		0x11,	/* Data length */
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC)
-+		return -EINVAL;
-+
-+	mac_address_header[2] = 0x24 + 0x11 * mac_address_idx;
-+
-+	/* Concat mac_address_header, mac_address to mac_address_cmd */
-+	memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header));
-+	memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address,
-+	       IEI_WT61P803_PUZZLE_MAC_LENGTH);
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+						sizeof(mac_address_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto err;
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto err;
-+	}
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EPROTO;
-+		goto err;
-+	}
-+
-+	sprintf(mcu->version.mac_address[mac_address_idx], "%.*s",
-+		IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address);
-+err:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu,
-+							 int power_loss_recovery_action)
-+{
-+	unsigned char *resp_buf = mcu->response_buffer;
-+	unsigned char power_loss_recovery_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4)
-+		return -EINVAL;
-+
-+	power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER;
-+	power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS;
-+	power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action];
-+
-+	mutex_lock(&mcu->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd,
-+						sizeof(power_loss_recovery_cmd),
-+						resp_buf, &reply_size);
-+	if (ret)
-+		goto exit;
-+	mcu->status.power_loss_recovery = power_loss_recovery_action;
-+exit:
-+	mutex_unlock(&mcu->lock);
-+	return ret;
-+}
-+
-+#define to_puzzle_dev_attr(_attr) \
-+	container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr)
-+
-+static ssize_t show_output(struct device *dev,
-+			   struct device_attribute *attr, char *buf)
-+{
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version);
-+	case IEI_WT61P803_PUZZLE_BUILD_INFO:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info);
-+	case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE:
-+		return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode);
-+	case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION:
-+		return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version);
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		ret = iei_wt61p803_puzzle_get_serial_number(mcu);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index);
-+		if (!ret)
-+			ret = scnprintf(buf, PAGE_SIZE, "%s\n",
-+					mcu->version.mac_address[pattr->index]);
-+		else
-+			ret = 0;
-+		return ret;
-+	case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+	case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+		ret = iei_wt61p803_puzzle_get_mcu_status(mcu);
-+		if (ret)
-+			return ret;
-+
-+		mutex_lock(&mcu->lock);
-+		switch (pattr->type) {
-+		case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n",
-+					mcu->status.ac_recovery_status_flag);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery);
-+			break;
-+		case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+			ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status);
-+			break;
-+		default:
-+			ret = 0;
-+			break;
-+		}
-+		mutex_unlock(&mcu->lock);
-+		return ret;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t store_output(struct device *dev,
-+			    struct device_attribute *attr,
-+			    const char *buf, size_t len)
-+{
-+	unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH];
-+	unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH];
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+	struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+	int power_loss_recovery_action = 0;
-+	int ret;
-+
-+	switch (pattr->type) {
-+	case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1))
-+			return -EINVAL;
-+		memcpy(serial_number, buf, sizeof(serial_number));
-+		ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+		if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1))
-+			return -EINVAL;
-+
-+		memcpy(mac_address, buf, sizeof(mac_address));
-+
-+		if (strlen(attr->attr.name) != 13)
-+			return -EIO;
-+
-+		ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index);
-+		if (ret)
-+			return ret;
-+		return len;
-+	case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+		ret = kstrtoint(buf, 10, &power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu,
-+								    power_loss_recovery_action);
-+		if (ret)
-+			return ret;
-+		return len;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \
-+	struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \
-+		{ .dev_attr	= __ATTR(_name, _mode, _show, _store), \
-+		  .type		= _type, \
-+		  .index	= _index }
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id)
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \
-+	IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id)
-+
-+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0);
-+
-+static struct attribute *iei_wt61p803_puzzle_attrs[] = {
-+	&dev_attr_version.dev_attr.attr,
-+	&dev_attr_build_info.dev_attr.attr,
-+	&dev_attr_bootloader_mode.dev_attr.attr,
-+	&dev_attr_protocol_version.dev_attr.attr,
-+	&dev_attr_serial_number.dev_attr.attr,
-+	&dev_attr_mac_address_0.dev_attr.attr,
-+	&dev_attr_mac_address_1.dev_attr.attr,
-+	&dev_attr_mac_address_2.dev_attr.attr,
-+	&dev_attr_mac_address_3.dev_attr.attr,
-+	&dev_attr_mac_address_4.dev_attr.attr,
-+	&dev_attr_mac_address_5.dev_attr.attr,
-+	&dev_attr_mac_address_6.dev_attr.attr,
-+	&dev_attr_mac_address_7.dev_attr.attr,
-+	&dev_attr_ac_recovery_status.dev_attr.attr,
-+	&dev_attr_power_loss_recovery.dev_attr.attr,
-+	&dev_attr_power_status.dev_attr.attr,
-+	NULL
-+};
-+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle);
-+
-+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	int ret;
-+
-+	ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	if (ret)
-+		mfd_remove_devices(mcu->dev);
-+
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev,
-+					    struct iei_wt61p803_puzzle *mcu)
-+{
-+	/* Remove sysfs groups */
-+	sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+	mfd_remove_devices(mcu->dev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	u32 baud;
-+	int ret;
-+
-+	/* Read the baud rate from 'current-speed', because the MCU supports different rates */
-+	if (device_property_read_u32(dev, "current-speed", &baud)) {
-+		dev_err(dev,
-+			"'current-speed' is not specified in device node\n");
-+		return -EINVAL;
-+	}
-+	dev_dbg(dev, "Driver baud rate: %d\n", baud);
-+
-+	/* Allocate the memory */
-+	mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL);
-+	if (!mcu)
-+		return -ENOMEM;
-+
-+	mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL);
-+	if (!mcu->reply)
-+		return -ENOMEM;
-+
-+	/* Initialize device struct data */
-+	mcu->serdev = serdev;
-+	mcu->dev = dev;
-+	init_completion(&mcu->reply->received);
-+	mutex_init(&mcu->reply_lock);
-+	mutex_init(&mcu->lock);
-+
-+	/* Setup UART interface */
-+	serdev_device_set_drvdata(serdev, mcu);
-+	serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops);
-+	ret = devm_serdev_device_open(dev, serdev);
-+	if (ret)
-+		return ret;
-+	serdev_device_set_baudrate(serdev, baud);
-+	serdev_device_set_flow_control(serdev, false);
-+	ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
-+	if (ret) {
-+		dev_err(dev, "Failed to set parity\n");
-+		return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_get_version(mcu);
-+	if (ret)
-+		return ret;
-+
-+	dev_dbg(dev, "MCU version: %s\n", mcu->version.version);
-+	dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info);
-+	dev_dbg(dev, "MCU in bootloader mode: %s\n",
-+		mcu->version.bootloader_mode ? "true" : "false");
-+	dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version);
-+
-+	if (device_property_read_bool(dev, "enable-beep")) {
-+		ret = iei_wt61p803_puzzle_buzzer(mcu, false);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu);
-+	if (ret)
-+		return ret;
-+
-+	return devm_of_platform_populate(dev);
-+}
-+
-+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev)
-+{
-+	struct device *dev = &serdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+
-+	iei_wt61p803_puzzle_sysfs_remove(dev, mcu);
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = {
-+	{ .compatible = "iei,wt61p803-puzzle" },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids);
-+
-+static struct serdev_device_driver iei_wt61p803_puzzle_drv = {
-+	.probe			= iei_wt61p803_puzzle_probe,
-+	.remove			= iei_wt61p803_puzzle_remove,
-+	.driver = {
-+		.name		= "iei-wt61p803-puzzle",
-+		.of_match_table	= iei_wt61p803_puzzle_dt_ids,
-+	},
-+};
-+
-+module_serdev_device_driver(iei_wt61p803_puzzle_drv);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver");
---- /dev/null
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_
-+#define _MFD_IEI_WT61P803_PUZZLE_H_
-+
-+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512
-+
-+/* Command magic numbers */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START		0x40 /* @ */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER	0x25 /* % */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM		0xF7
-+
-+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK		0x30 /* 0 */
-+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK	0x70
-+
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ		0xA1
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE		0xA0
-+
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION		0x56 /* V */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD		0x42 /* B */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE	0x4D /* M */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER	0x30
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS		0x31
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION	0x50 /* P */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE		0x43 /* C */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER		0x4F /* O */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS	0x53 /* S */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN			0x46 /* F */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ		0x5A /* Z */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE		0x57 /* W */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE		0x30
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE		0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */
-+
-+struct iei_wt61p803_puzzle_mcu_version;
-+struct iei_wt61p803_puzzle_reply;
-+struct iei_wt61p803_puzzle;
-+
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+					       unsigned char *cmd, size_t size,
-+					       unsigned char *reply_data, size_t *reply_size,
-+					       int retry_count);
-+
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+				      unsigned char *cmd, size_t size,
-+				      unsigned char *reply_data, size_t *reply_size);
-+
-+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */
diff --git a/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch b/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
deleted file mode 100644
index a11b387d92..0000000000
--- a/target/linux/mvebu/patches-6.1/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch
+++ /dev/null
@@ -1,501 +0,0 @@
-From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:34 +0000
-Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver
-
-Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed
-control via PWM, reading fan speed and reading on-board temperature
-sensors.
-
-The driver registers a HWMON device and a simple thermal cooling device to
-enable in-kernel fan management.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Acked-by: Guenter Roeck <linux@roeck-us.net>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/hwmon/Kconfig                     |   8 +
- drivers/hwmon/Makefile                    |   1 +
- drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++
- 3 files changed, 454 insertions(+)
- create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV
- 	  This driver can also be built as a module. If so, the module
- 	  will be called ibmpowernv.
- 
-+config SENSORS_IEI_WT61P803_PUZZLE_HWMON
-+	tristate "IEI WT61P803 PUZZLE MFD HWMON Driver"
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed
-+	  and writing fan PWM values. It also supports reading on-board
-+	  temperature sensors.
-+
- config SENSORS_IIO_HWMON
- 	tristate "Hwmon driver that uses channels specified via iio maps"
- 	depends on IIO
---- a/drivers/hwmon/Makefile
-+++ b/drivers/hwmon/Makefile
-@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130)	+= hih6130
- obj-$(CONFIG_SENSORS_ULTRA45)	+= ultra45_env.o
- obj-$(CONFIG_SENSORS_I5500)	+= i5500_temp.o
- obj-$(CONFIG_SENSORS_I5K_AMB)	+= i5k_amb.o
-+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o
- obj-$(CONFIG_SENSORS_IBMAEM)	+= ibmaem.o
- obj-$(CONFIG_SENSORS_IBMPEX)	+= ibmpex.o
- obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o
---- /dev/null
-+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-@@ -0,0 +1,445 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU HWMON Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/hwmon.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/math64.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM	2
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL	255
-+
-+/**
-+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance
-+ * @mcu_hwmon:		Parent driver struct pointer
-+ * @tcdev:		Thermal cooling device pointer
-+ * @name:		Thermal cooling device name
-+ * @pwm_channel:	Controlled PWM channel (0 or 1)
-+ * @cooling_levels:	Thermal cooling device cooling levels (DT)
-+ * @cur_level:		Current cooling level
-+ * @num_levels:	Number of cooling levels
-+ */
-+struct iei_wt61p803_puzzle_thermal_cooling_device {
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct thermal_cooling_device *tcdev;
-+	char name[THERMAL_NAME_LENGTH];
-+	int pwm_channel;
-+	u32 *cooling_levels;
-+	int cur_level;
-+	u8 num_levels;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver
-+ * @mcu:				MCU struct pointer
-+ * @response_buffer			Global MCU response buffer
-+ * @thermal_cooling_dev_present:	Per-channel thermal cooling device control indicator
-+ * @cdev:				Per-channel thermal cooling device private structure
-+ */
-+struct iei_wt61p803_puzzle_hwmon {
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct iei_wt61p803_puzzle_thermal_cooling_device
-+		*cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+	struct mutex lock; /* mutex to protect response_buffer array */
-+};
-+
-+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)
-+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char temp_sensor_ntc_cmd[4] = {
-+		IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP,
-+		IEI_WT61P803_PUZZLE_CMD_TEMP_ALL,
-+	};
-+	size_t reply_size;
-+	int ret;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,
-+						sizeof(temp_sensor_ntc_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	/* Check the number of NTC values */
-+	if (resp_buf[3] != '2') {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)
-+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+					      int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char fan_speed_cmd[4] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,
-+						sizeof(fan_speed_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 7) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	*value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						 int channel, long pwm_set_val)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_set_cmd[6] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;
-+	pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+	pwm_set_cmd[4] = pwm_set_val;
-+
-+	mutex_lock(&mcu_hwmon->lock);
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,
-+						sizeof(pwm_set_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		goto exit;
-+
-+	if (reply_size != 3) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+		ret = -EIO;
-+		goto exit;
-+	}
-+exit:
-+	mutex_unlock(&mcu_hwmon->lock);
-+	return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+						int channel, long *value)
-+{
-+	unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+	unsigned char pwm_get_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+	pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;
-+	pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+
-+	ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,
-+						sizeof(pwm_get_cmd), resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 5)
-+		return -EIO;
-+
-+	if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)
-+		return -EIO;
-+
-+	*value = resp_buf[3];
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,
-+				    u32 attr, int channel, long *val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);
-+	case hwmon_fan:
-+		return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);
-+	case hwmon_temp:
-+		return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,
-+				     u32 attr, int channel, long val)
-+{
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);
-+}
-+
-+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,
-+					      u32 attr, int channel)
-+{
-+	const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;
-+
-+	switch (type) {
-+	case hwmon_pwm:
-+		if (mcu_hwmon->thermal_cooling_dev_present[channel])
-+			return 0444;
-+		if (attr == hwmon_pwm_input)
-+			return 0644;
-+		break;
-+	case hwmon_fan:
-+		if (attr == hwmon_fan_input)
-+			return 0444;
-+		break;
-+	case hwmon_temp:
-+		if (attr == hwmon_temp_input)
-+			return 0444;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {
-+	.is_visible = iei_wt61p803_puzzle_is_visible,
-+	.read = iei_wt61p803_puzzle_read,
-+	.write = iei_wt61p803_puzzle_write,
-+};
-+
-+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
-+	HWMON_CHANNEL_INFO(pwm,
-+			   HWMON_PWM_INPUT,
-+			   HWMON_PWM_INPUT),
-+	HWMON_CHANNEL_INFO(fan,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT,
-+			   HWMON_F_INPUT),
-+	HWMON_CHANNEL_INFO(temp,
-+			   HWMON_T_INPUT,
-+			   HWMON_T_INPUT),
-+	NULL
-+};
-+
-+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {
-+	.ops = &iei_wt61p803_puzzle_hwmon_ops,
-+	.info = iei_wt61p803_puzzle_info,
-+};
-+
-+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	*state = cdev->num_levels - 1;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long *state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (cdev->cur_level < 0)
-+		return -EAGAIN;
-+
-+	*state = cdev->cur_level;
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,
-+					     unsigned long state)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+	u8 pwm_level;
-+
-+	if (!cdev)
-+		return -EINVAL;
-+
-+	if (state >= cdev->num_levels)
-+		return -EINVAL;
-+
-+	if (state == cdev->cur_level)
-+		return 0;
-+
-+	cdev->cur_level = state;
-+	pwm_level = cdev->cooling_levels[state];
-+
-+	return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level);
-+}
-+
-+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {
-+	.get_max_state = iei_wt61p803_puzzle_get_max_state,
-+	.get_cur_state = iei_wt61p803_puzzle_get_cur_state,
-+	.set_cur_state = iei_wt61p803_puzzle_set_cur_state,
-+};
-+
-+static int
-+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,
-+					       struct fwnode_handle *child,
-+					       struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)
-+{
-+	struct iei_wt61p803_puzzle_thermal_cooling_device *cdev;
-+	u32 pwm_channel;
-+	u8 num_levels;
-+	int i, ret;
-+
-+	ret = fwnode_property_read_u32(child, "reg", &pwm_channel);
-+	if (ret)
-+		return ret;
-+
-+	mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;
-+
-+	num_levels = fwnode_property_count_u32(child, "cooling-levels");
-+	if (!num_levels)
-+		return -EINVAL;
-+
-+	cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
-+	if (!cdev)
-+		return -ENOMEM;
-+
-+	cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL);
-+	if (!cdev->cooling_levels)
-+		return -ENOMEM;
-+
-+	ret = fwnode_property_read_u32_array(child, "cooling-levels",
-+					     cdev->cooling_levels,
-+					     num_levels);
-+	if (ret) {
-+		dev_err(dev, "Couldn't read property 'cooling-levels'\n");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < num_levels; i++) {
-+		if (cdev->cooling_levels[i] >
-+		    IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) {
-+			dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i,
-+				cdev->cooling_levels[i],
-+				IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	cdev->mcu_hwmon = mcu_hwmon;
-+	cdev->pwm_channel = pwm_channel;
-+	cdev->num_levels = num_levels;
-+	cdev->cur_level = -1;
-+	mcu_hwmon->cdev[pwm_channel] = cdev;
-+
-+	snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel);
-+	cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name,
-+							      cdev, &iei_wt61p803_puzzle_cooling_ops);
-+	if (IS_ERR(cdev->tcdev))
-+		return PTR_ERR(cdev->tcdev);
-+
-+	return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+	struct fwnode_handle *child;
-+	struct device *hwmon_dev;
-+	int ret;
-+
-+	mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);
-+	if (!mcu_hwmon)
-+		return -ENOMEM;
-+
-+	mcu_hwmon->mcu = mcu;
-+	platform_set_drvdata(pdev, mcu_hwmon);
-+	mutex_init(&mcu_hwmon->lock);
-+
-+	hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle",
-+							 mcu_hwmon,
-+							 &iei_wt61p803_puzzle_chip_info,
-+							 NULL);
-+	if (IS_ERR(hwmon_dev))
-+		return PTR_ERR(hwmon_dev);
-+
-+	/* Control fans via PWM lines via Linux Kernel */
-+	if (IS_ENABLED(CONFIG_THERMAL)) {
-+		device_for_each_child_node(dev, child) {
-+			ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);
-+			if (ret) {
-+				dev_err(dev, "Enabling the PWM fan failed\n");
-+				fwnode_handle_put(child);
-+				return ret;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-hwmon" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);
-+
-+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-hwmon",
-+		.of_match_table = iei_wt61p803_puzzle_hwmon_id_table,
-+	},
-+	.probe = iei_wt61p803_puzzle_hwmon_probe,
-+};
-+
-+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
deleted file mode 100644
index 1abb1b9416..0000000000
--- a/target/linux/mvebu/patches-6.1/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:35 +0000
-Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver
-
-Add support for the IEI WT61P803 PUZZLE LED driver.
-Currently only the front panel power LED is supported,
-since it is the only LED on this board wired through the
-MCU.
-
-The LED is wired directly to the on-board MCU controller
-and is toggled using an MCU command.
-
-Support for more LEDs is going to be added in case more
-boards implement this microcontroller, as LEDs use many
-different GPIOs.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/leds/Kconfig                    |   8 ++
- drivers/leds/Makefile                   |   1 +
- drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++
- 3 files changed, 156 insertions(+)
- create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO
- 	  Choose this option if you want to use the notification LED on
- 	  Compaq/HP iPAQ h3100 and h3600.
- 
-+config LEDS_IEI_WT61P803_PUZZLE
-+	tristate "LED Support for the IEI WT61P803 PUZZLE MCU"
-+	depends on LEDS_CLASS
-+	depends on MFD_IEI_WT61P803_PUZZLE
-+	help
-+	  This option enables support for LEDs controlled by the IEI WT61P803
-+	  M801 MCU.
-+
- config LEDS_HP6XX
- 	tristate "LED Support for the HP Jornada 6xx"
- 	depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX)		+= leds-hp6xx.
- obj-$(CONFIG_LEDS_INTEL_SS4200)		+= leds-ss4200.o
- obj-$(CONFIG_LEDS_IP30)			+= leds-ip30.o
- obj-$(CONFIG_LEDS_IPAQ_MICRO)		+= leds-ipaq-micro.o
-+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE)	+= leds-iei-wt61p803-puzzle.o
- obj-$(CONFIG_LEDS_IS31FL319X)		+= leds-is31fl319x.o
- obj-$(CONFIG_LEDS_IS31FL32XX)		+= leds-is31fl32xx.o
- obj-$(CONFIG_LEDS_LM3530)		+= leds-lm3530.o
---- /dev/null
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -0,0 +1,147 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU LED Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/leds.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+
-+enum iei_wt61p803_puzzle_led_state {
-+	IEI_LED_OFF = 0x30,
-+	IEI_LED_ON = 0x31,
-+	IEI_LED_BLINK_5HZ = 0x32,
-+	IEI_LED_BLINK_1HZ = 0x33,
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_led - MCU LED Driver
-+ * @cdev:		LED classdev
-+ * @mcu:		MCU struct pointer
-+ * @response_buffer	Global MCU response buffer
-+ * @lock:		General mutex lock to protect simultaneous R/W access to led_power_state
-+ * @led_power_state:	State of the front panel power LED
-+ */
-+struct iei_wt61p803_puzzle_led {
-+	struct led_classdev cdev;
-+	struct iei_wt61p803_puzzle *mcu;
-+	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	struct mutex lock; /* mutex to protect led_power_state */
-+	int led_power_state;
-+};
-+
-+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-+	(struct led_classdev *led_cdev)
-+{
-+	return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);
-+}
-+
-+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,
-+							   enum led_brightness brightness)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	unsigned char *resp_buf = priv->response_buffer;
-+	unsigned char led_power_cmd[5] = {};
-+	size_t reply_size;
-+	int ret;
-+
-+	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
-+	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+
-+	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
-+						sizeof(led_power_cmd),
-+						resp_buf,
-+						&reply_size);
-+	if (ret)
-+		return ret;
-+
-+	if (reply_size != 3)
-+		return -EIO;
-+
-+	if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+	      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+	      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))
-+		return -EIO;
-+
-+	mutex_lock(&priv->lock);
-+	priv->led_power_state = brightness;
-+	mutex_unlock(&priv->lock);
-+
-+	return 0;
-+}
-+
-+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	int led_state;
-+
-+	mutex_lock(&priv->lock);
-+	led_state = priv->led_power_state;
-+	mutex_unlock(&priv->lock);
-+
-+	return led_state;
-+}
-+
-+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+	struct iei_wt61p803_puzzle_led *priv;
-+	struct led_init_data init_data = {};
-+	struct fwnode_handle *child;
-+	int ret;
-+
-+	if (device_get_child_node_count(dev) != 1)
-+		return -EINVAL;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->mcu = mcu;
-+	priv->led_power_state = 1;
-+	mutex_init(&priv->lock);
-+	dev_set_drvdata(dev, priv);
-+
-+	child = device_get_next_child_node(dev, NULL);
-+	init_data.fwnode = child;
-+
-+	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+	priv->cdev.max_brightness = 1;
-+
-+	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+	if (ret)
-+		dev_err(dev, "Could not register LED\n");
-+
-+	fwnode_handle_put(child);
-+	return ret;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {
-+	{ .compatible = "iei,wt61p803-puzzle-leds" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);
-+
-+static struct platform_driver iei_wt61p803_puzzle_led_driver = {
-+	.driver = {
-+		.name = "iei-wt61p803-puzzle-led",
-+		.of_match_table = iei_wt61p803_puzzle_led_of_match,
-+	},
-+	.probe = iei_wt61p803_puzzle_led_probe,
-+};
-+module_platform_driver(iei_wt61p803_puzzle_led_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle");
diff --git a/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch b/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
deleted file mode 100644
index b1d420ef0a..0000000000
--- a/target/linux/mvebu/patches-6.1/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:36 +0000
-Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs
- interface documentation
-
-Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow
-monitoring and control of the microcontroller from user space.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../testing/sysfs-driver-iei-wt61p803-puzzle  | 61 +++++++++++++++++++
- 1 file changed, 61 insertions(+)
- create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-@@ -0,0 +1,61 @@
-+What:		/sys/bus/serial/devices/.../mac_address_*
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned MAC address values
-+
-+What:		/sys/bus/serial/devices/.../serial_number
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Internal factory assigned serial number
-+
-+What:		/sys/bus/serial/devices/.../version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware version
-+
-+What:		/sys/bus/serial/devices/.../protocol_version
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU communication protocol version
-+
-+What:		/sys/bus/serial/devices/.../power_loss_recovery
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RW) Host platform power loss recovery settings
-+		Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA
-+
-+What:		/sys/bus/serial/devices/.../bootloader_mode
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU bootloader mode status
-+		Value mapping:
-+		0 - normal mode
-+		1 - bootloader mode
-+
-+What:		/sys/bus/serial/devices/.../power_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Power status indicates the host platform power on method.
-+		Value mapping (bitwise list):
-+		0x80 - Null
-+		0x40 - Firmware flag
-+		0x20 - Power loss detection flag (powered off)
-+		0x10 - Power loss detection flag (AC mode)
-+		0x08 - Button power on
-+		0x04 - Wake-on-LAN power on
-+		0x02 - RTC alarm power on
-+		0x01 - AC recover power on
-+
-+What:		/sys/bus/serial/devices/.../build_info
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Internal MCU firmware build date
-+		Format: yyyy/mm/dd hh:mm
-+
-+What:		/sys/bus/serial/devices/.../ac_recovery_status
-+Date:		September 2020
-+Contact:	Luka Kovacic <luka.kovacic@sartura.hr>
-+Description:	(RO) Host platform AC recovery status value
-+		Value mapping:
-+		0 - board has not been recovered from power down
-+		1 - board has been recovered from power down
diff --git a/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch b/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
deleted file mode 100644
index 0f1a6f306b..0000000000
--- a/target/linux/mvebu/patches-6.1/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:37 +0000
-Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver
- documentation
-
-Add the iei-wt61p803-puzzle driver hwmon driver interface documentation.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei-wt61p803-puzzle-hwmon.rst       | 43 +++++++++++++++++++
- Documentation/hwmon/index.rst                 |  1 +
- 2 files changed, 44 insertions(+)
- create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-
---- /dev/null
-+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-@@ -0,0 +1,43 @@
-+.. SPDX-License-Identifier: GPL-2.0-only
-+
-+Kernel driver iei-wt61p803-puzzle-hwmon
-+=======================================
-+
-+Supported chips:
-+ * IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+   Prefix: 'iei-wt61p803-puzzle-hwmon'
-+
-+Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+
-+Description
-+-----------
-+
-+This driver adds fan and temperature sensor reading for some IEI Puzzle
-+series boards.
-+
-+Sysfs attributes
-+----------------
-+
-+The following attributes are supported:
-+
-+- IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+/sys files in hwmon subsystem
-+-----------------------------
-+
-+================= == =====================================================
-+fan[1-5]_input    RO files for fan speed (in RPM)
-+pwm[1-2]          RW files for fan[1-2] target duty cycle (0..255)
-+temp[1-2]_input   RO files for temperature sensors, in millidegree Celsius
-+================= == =====================================================
-+
-+/sys files in thermal subsystem
-+-------------------------------
-+
-+================= == =====================================================
-+cur_state         RW file for current cooling state of the cooling device
-+                     (0..max_state)
-+max_state         RO file for maximum cooling state of the cooling device
-+================= == =====================================================
---- a/Documentation/hwmon/index.rst
-+++ b/Documentation/hwmon/index.rst
-@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers
-    ibmaem
-    ibm-cffps
-    ibmpowernv
-+   iei-wt61p803-puzzle-hwmon
-    ina209
-    ina2xx
-    ina238
diff --git a/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
deleted file mode 100644
index e72df378ef..0000000000
--- a/target/linux/mvebu/patches-6.1/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:38 +0000
-Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE
- driver
-
-Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- MAINTAINERS | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9900,6 +9900,22 @@ F:	include/net/nl802154.h
- F:	net/ieee802154/
- F:	net/mac802154/
- 
-+IEI WT61P803 M801 MFD DRIVER
-+M:	Luka Kovacic <luka.kovacic@sartura.hr>
-+M:	Luka Perkov <luka.perkov@sartura.hr>
-+M:	Goran Medic <goran.medic@sartura.hr>
-+L:	linux-kernel@vger.kernel.org
-+S:	Maintained
-+F:	Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle
-+F:	Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+F:	Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-+F:	Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-+F:	Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-+F:	drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-+F:	drivers/leds/leds-iei-wt61p803-puzzle.c
-+F:	drivers/mfd/iei-wt61p803-puzzle.c
-+F:	include/linux/mfd/iei-wt61p803-puzzle.h
-+
- IFE PROTOCOL
- M:	Yotam Gigi <yotam.gi@gmail.com>
- M:	Jamal Hadi Salim <jhs@mojatatu.com>
diff --git a/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch b/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch
deleted file mode 100644
index 150a65498c..0000000000
--- a/target/linux/mvebu/patches-6.1/910-drivers-leds-wt61p803-puzzle-improvements.patch
+++ /dev/null
@@ -1,271 +0,0 @@
---- a/drivers/leds/leds-iei-wt61p803-puzzle.c
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -9,9 +9,13 @@
- #include <linux/mfd/iei-wt61p803-puzzle.h>
- #include <linux/mod_devicetable.h>
- #include <linux/module.h>
-+#include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/property.h>
- #include <linux/slab.h>
-+#include <linux/workqueue.h>
-+
-+#define IEI_LEDS_MAX		4
- 
- enum iei_wt61p803_puzzle_led_state {
- 	IEI_LED_OFF = 0x30,
-@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {
- 	struct iei_wt61p803_puzzle *mcu;
- 	unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
- 	struct mutex lock; /* mutex to protect led_power_state */
-+	struct work_struct work;
- 	int led_power_state;
-+	int id;
-+	u8 blinking;
-+	bool active_low;
- };
- 
- static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh
- 	size_t reply_size;
- 	int ret;
- 
-+	if (priv->blinking) {
-+		if (brightness == LED_OFF)
-+			priv->blinking = 0;
-+		else
-+			return 0;
-+	}
-+
- 	led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
- 	led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
--	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
--	led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+	led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?
-+				IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;
- 
- 	ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
- 						sizeof(led_power_cmd),
-@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_
- 	return led_state;
- }
- 
-+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);
-+	unsigned char led_blink_cmd[5] = {};
-+	unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+	size_t reply_size;
-+
-+	led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+	led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+	led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+	led_blink_cmd[3] = priv->blinking;
-+
-+	iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,
-+					  sizeof(led_blink_cmd),
-+					  resp_buf,
-+					  &reply_size);
-+
-+	return;
-+}
-+
-+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,
-+					     unsigned long *delay_on,
-+					     unsigned long *delay_off)
-+{
-+	struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+	u8 blink_mode = 0;
-+	int ret = 0;
-+
-+	/* set defaults */
-+	if (!*delay_on && !*delay_off) {
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	}
-+
-+	/* minimum delay for soft-driven blinking is 100ms to keep load low */
-+	if (*delay_on < 100)
-+		*delay_on = 100;
-+
-+	if (*delay_off < 100)
-+		*delay_off = 100;
-+
-+	/* offload blinking to hardware, if possible */
-+	if (*delay_on != *delay_off) {
-+		ret = -EINVAL;
-+	} else if (*delay_on == 100) {
-+		blink_mode = IEI_LED_BLINK_5HZ;
-+		*delay_on = 100;
-+		*delay_off = 100;
-+	} else if (*delay_on <= 500) {
-+		blink_mode = IEI_LED_BLINK_1HZ;
-+		*delay_on = 500;
-+		*delay_off = 500;
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+	mutex_lock(&priv->lock);
-+	priv->blinking = blink_mode;
-+	mutex_unlock(&priv->lock);
-+
-+	if (blink_mode)
-+		schedule_work(&priv->work);
-+
-+	return ret;
-+}
-+
-+
-+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,
-+				     struct device_node *np)
-+{
-+	const char *state;
-+	int ret = 0;
-+
-+	state = of_get_property(np, "default-state", NULL);
-+	if (state) {
-+		if (!strcmp(state, "on")) {
-+			ret =
-+			iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, cdev->max_brightness);
-+		} else  {
-+			ret = iei_wt61p803_puzzle_led_brightness_set_blocking(
-+				cdev, LED_OFF);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
- static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev_of_node(dev);
-+	struct device_node *child;
- 	struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
- 	struct iei_wt61p803_puzzle_led *priv;
--	struct led_init_data init_data = {};
--	struct fwnode_handle *child;
- 	int ret;
-+	u32 reg;
- 
--	if (device_get_child_node_count(dev) != 1)
-+	if (device_get_child_node_count(dev) > IEI_LEDS_MAX)
- 		return -EINVAL;
- 
--	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
--	if (!priv)
--		return -ENOMEM;
--
--	priv->mcu = mcu;
--	priv->led_power_state = 1;
--	mutex_init(&priv->lock);
--	dev_set_drvdata(dev, priv);
--
--	child = device_get_next_child_node(dev, NULL);
--	init_data.fwnode = child;
--
--	priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
--	priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
--	priv->cdev.max_brightness = 1;
-+	for_each_available_child_of_node(np, child) {
-+		struct led_init_data init_data = {};
- 
--	ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
--	if (ret)
--		dev_err(dev, "Could not register LED\n");
-+		ret = of_property_read_u32(child, "reg", &reg);
-+		if (ret) {
-+			dev_err(dev, "Failed to read led 'reg' property\n");
-+			goto put_child_node;
-+		}
-+
-+		if (reg > IEI_LEDS_MAX) {
-+			dev_err(dev, "Invalid led reg %u\n", reg);
-+			ret = -EINVAL;
-+			goto put_child_node;
-+		}
-+
-+		priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+		if (!priv) {
-+			ret = -ENOMEM;
-+			goto put_child_node;
-+		}
-+
-+		mutex_init(&priv->lock);
-+
-+		dev_set_drvdata(dev, priv);
-+
-+		if (of_property_read_bool(child, "active-low"))
-+			priv->active_low = true;
-+
-+		priv->mcu = mcu;
-+		priv->id = reg;
-+		priv->led_power_state = 1;
-+		priv->blinking = 0;
-+		init_data.fwnode = of_fwnode_handle(child);
-+
-+		priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+		priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+		priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;
-+
-+		priv->cdev.max_brightness = 1;
-+
-+		INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);
-+
-+		ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);
-+		if (ret) {
-+			dev_err(dev, "Could apply default from DT\n");
-+			goto put_child_node;
-+		}
-+
-+		ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+		if (ret) {
-+			dev_err(dev, "Could not register LED\n");
-+			goto put_child_node;
-+		}
-+	}
-+
-+	return ret;
- 
--	fwnode_handle_put(child);
-+put_child_node:
-+	of_node_put(child);
- 	return ret;
- }
- 
---- a/include/linux/mfd/iei-wt61p803-puzzle.h
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -36,7 +36,7 @@
- #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
- 
- #define IEI_WT61P803_PUZZLE_CMD_LED			0x52 /* R */
--#define IEI_WT61P803_PUZZLE_CMD_LED_POWER		0x31 /* 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n)		(0x30 | (n))
- 
- #define IEI_WT61P803_PUZZLE_CMD_TEMP			0x54 /* T */
- #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL		0x41 /* A */
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(
- 	struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
- 	int ret;
- 
-+	print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE,
-+			     16, 1, data, size, false);
-+
- 	ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
- 	/* Return the number of processed bytes if function returns error,
- 	 * discard the remaining incoming data, since the frame this data
-@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st
- 
- 	cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
- 
-+	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
-+			     16, 1, cmd, size, false);
-+
- 	/* Initialize reply struct */
- 	reinit_completion(&mcu->reply->received);
- 	mcu->reply->size = 0;
diff --git a/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch b/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
deleted file mode 100644
index 2f0b1788ff..0000000000
--- a/target/linux/mvebu/patches-6.1/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch
+++ /dev/null
@@ -1,63 +0,0 @@
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st
- {
- 	struct device *dev = &mcu->serdev->dev;
- 	int ret;
-+	int retries;
- 
- 	if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
- 		return -EINVAL;
-@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st
- 	print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
- 			     16, 1, cmd, size, false);
- 
-+	retries = 3;
- 	/* Initialize reply struct */
--	reinit_completion(&mcu->reply->received);
--	mcu->reply->size = 0;
--	usleep_range(2000, 10000);
--	serdev_device_write_flush(mcu->serdev);
--	ret = serdev_device_write_buf(mcu->serdev, cmd, size);
--	if (ret < 0)
--		goto exit;
--
--	serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	ret = wait_for_completion_timeout(&mcu->reply->received,
--					  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
--	if (ret == 0) {
--		dev_err(dev, "Command reply receive timeout\n");
--		ret = -ETIMEDOUT;
--		goto exit;
-+	while (retries) {
-+		reinit_completion(&mcu->reply->received);
-+		mcu->reply->size = 0;
-+		usleep_range(2000, 10000);
-+		serdev_device_write_flush(mcu->serdev);
-+		ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+		if (ret < 0)
-+			goto exit;
-+
-+		serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		ret = wait_for_completion_timeout(&mcu->reply->received,
-+						  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+		retries--;
-+		if (ret == 0) {
-+			if (retries == 0) {
-+				dev_err(dev, "Command reply receive timeout\n");
-+				ret = -ETIMEDOUT;
-+				goto exit;
-+			}
-+		}
-+		else {
-+			if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+				mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+				mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) {
-+				break;
-+			}
-+		}
- 	}
--
- 	*reply_size = mcu->reply->size;
- 	/* Copy the received data, as it will not be available after a new frame is received */
- 	memcpy(reply_data, mcu->reply->data, mcu->reply->size);
diff --git a/target/linux/mvebu/patches-6.6/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-6.6/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
index 0cb1e75591..7463c8844e 100644
--- a/target/linux/mvebu/patches-6.6/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
+++ b/target/linux/mvebu/patches-6.6/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
@@ -258,7 +258,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
  static int kernel_init(void *);
  
  /*
-@@ -928,6 +932,18 @@ void start_kernel(void)
+@@ -930,6 +934,18 @@ void start_kernel(void)
  	boot_cpu_hotplug_init();
  
  	pr_notice("Kernel command line: %s\n", saved_command_line);
diff --git a/target/linux/mvebu/patches-6.6/350-drivers-thermal-step_wise-add-support-for-hysteresis.patch b/target/linux/mvebu/patches-6.6/350-drivers-thermal-step_wise-add-support-for-hysteresis.patch
new file mode 100644
index 0000000000..e7332b6df0
--- /dev/null
+++ b/target/linux/mvebu/patches-6.6/350-drivers-thermal-step_wise-add-support-for-hysteresis.patch
@@ -0,0 +1,65 @@
+From 9685ce100f0d302501117113ef0a526ad1acca1d Mon Sep 17 00:00:00 2001
+From: Ram Chandrasekar <rkumbako@codeaurora.org>
+Date: Mon, 7 May 2018 11:54:08 -0600
+Subject: [PATCH] drivers: thermal: step_wise: add support for hysteresis
+
+Step wise governor increases the mitigation level when the temperature
+goes above a threshold and will decrease the mitigation when the
+temperature falls below the threshold. If it were a case, where the
+temperature hovers around a threshold, the mitigation will be applied
+and removed at every iteration. This reaction to the temperature is
+inefficient for performance.
+
+The use of hysteresis temperature could avoid this ping-pong of
+mitigation by relaxing the mitigation to happen only when the
+temperature goes below this lower hysteresis value.
+
+Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
+Signed-off-by: Lina Iyer <ilina@codeaurora.org>
+[forward-ported for Linux 6.6, as stop-gap downstream solution]
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/thermal/gov_step_wise.c | 23 ++++++++++++++++-------
+ 1 file changed, 16 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/gov_step_wise.c
++++ b/drivers/thermal/gov_step_wise.c
+@@ -86,22 +86,31 @@ static void thermal_zone_trip_update(str
+ 	struct thermal_instance *instance;
+ 	bool throttle = false;
+ 	int old_target;
++	int hyst_temp;
+ 
+ 	trend = get_tz_trend(tz, trip_id);
+ 
+-	if (tz->temperature >= trip->temperature) {
+-		throttle = true;
+-		trace_thermal_zone_trip(tz, trip_id, trip->type);
+-	}
+-
+-	dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d]:trend=%d,throttle=%d\n",
+-		trip_id, trip->type, trip->temperature, trend, throttle);
++	hyst_temp =  trip->temperature - trip->hysteresis;
++	dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d,hyst=%d]:trend=%d,throttle=%d\n",
++		trip_id, trip->type, trip->temperature, hyst_temp, trend, throttle);
+ 
+ 	list_for_each_entry(instance, &tz->thermal_instances, tz_node) {
+ 		if (instance->trip != trip)
+ 			continue;
+ 
+ 		old_target = instance->target;
++		throttle = false;
++		/*
++		 * Lower the mitigation only if the temperature
++		 * goes below the hysteresis temperature.
++		 */
++		if (tz->temperature >= trip->temperature ||
++		   (tz->temperature >= hyst_temp &&
++		   old_target != THERMAL_NO_TARGET)) {
++			throttle = true;
++			trace_thermal_zone_trip(tz, trip_id, trip->type);
++		}
++
+ 		instance->target = get_target_state(instance, trend, throttle);
+ 		dev_dbg(&instance->cdev->device, "old_target=%d, target=%d\n",
+ 					old_target, (int)instance->target);
diff --git a/target/linux/mvebu/patches-6.6/912-drivers-hwmon-wt61p803-puzzle-thermal-zone.patch b/target/linux/mvebu/patches-6.6/912-drivers-hwmon-wt61p803-puzzle-thermal-zone.patch
new file mode 100644
index 0000000000..4633c03855
--- /dev/null
+++ b/target/linux/mvebu/patches-6.6/912-drivers-hwmon-wt61p803-puzzle-thermal-zone.patch
@@ -0,0 +1,10 @@
+--- a/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
++++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
+@@ -251,6 +251,7 @@ static const struct hwmon_ops iei_wt61p8
+ };
+ 
+ static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
++	HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
+ 	HWMON_CHANNEL_INFO(pwm,
+ 			   HWMON_PWM_INPUT,
+ 			   HWMON_PWM_INPUT),
diff --git a/target/linux/mxs/config-6.1 b/target/linux/mxs/config-6.1
deleted file mode 100644
index b23aef6969..0000000000
--- a/target/linux/mxs/config-6.1
+++ /dev/null
@@ -1,245 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_MXS=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEV_MXS_DCP=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FEC=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MXS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MXS=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_IIO_TRIGGER=y
-# CONFIG_IIO_TRIGGERED_BUFFER is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MXS=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MXS_LRADC=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MXS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MXS_DMA=y
-# CONFIG_MXS_LRADC_ADC is not set
-CONFIG_MXS_TIMER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MXS_OCOTP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX23=y
-CONFIG_PINCTRL_IMX28=y
-CONFIG_PINCTRL_MXS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RATIONAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_STMP=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
-CONFIG_SMSC_PHY=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_IMX23=y
-CONFIG_SOC_IMX28=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MXS=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STMP3XXX_RTC_WATCHDOG=y
-CONFIG_STMP_DEVICE=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-# CONFIG_UNUSED_BOARD_FILES is not set
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
diff --git a/target/linux/mxs/image/Makefile b/target/linux/mxs/image/Makefile
index 585211dc0b..fff7e7ca33 100644
--- a/target/linux/mxs/image/Makefile
+++ b/target/linux/mxs/image/Makefile
@@ -39,9 +39,7 @@ define Device/Default
   KERNEL_NAME := zImage
   KERNEL := kernel-bin | uImage none
   IMAGES := sdcard.img.gz
-ifneq ($(KERNEL),6.1)
   DTS_DIR := $(DTS_DIR)/nxp/mxs
-endif
   DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
 endef
 
diff --git a/target/linux/qualcommax/config-6.6 b/target/linux/qualcommax/config-6.6
index 71b54041c5..1d05868caf 100644
--- a/target/linux/qualcommax/config-6.6
+++ b/target/linux/qualcommax/config-6.6
@@ -216,6 +216,7 @@ CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 # CONFIG_KPSS_XCC is not set
+CONFIG_LEDS_TLC591XX=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
@@ -441,6 +442,7 @@ CONFIG_RANDSTRUCT_NONE=y
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
 CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_CPR3 is not set
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
index 5364daad45..23e89a9ae4 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts
@@ -193,6 +193,7 @@
 			};
 
 			partition@480000 {
+				compatible = "u-boot,env";
 				label = "0:appsblenv";
 				reg = <0x480000 0x10000>;
 			};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts
new file mode 100644
index 0000000000..70f4438ab0
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-mx8500.dts
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Linksys MX8500";
+	compatible = "linksys,mx8500", "qcom,ipq8074";
+
+	aliases {
+		serial0 = &blsp1_uart5;
+		serial1 = &blsp1_uart3;
+		led-boot = &led_system_blue;
+		led-running = &led_system_blue;
+		led-failsafe = &led_system_red;
+		led-upgrade = &led_system_green;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+	};
+
+	gpio_export {
+		compatible = "gpio-export";
+		#size-cells = <0>;
+
+		bt_pwr {
+			gpio-export,name = "bt_pwr";
+			gpio-export,output = <1>;
+			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		reset-button {
+			label = "reset";
+			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps-button {
+			label = "wps";
+			gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+};
+
+&tlmm {
+	button_pins: button-state {
+		pins = "gpio64", "gpio67";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+
+	mdio_pins: mdio-state {
+		mdc-pins {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart3 {
+	status = "okay";
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&prng {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	/*
+	 * Bootloader will find the NAND DT node by the compatible and
+	 * then "fixup" it by adding the partitions from the SMEM table
+	 * using the legacy bindings thus making it impossible for us
+	 * to change the partition table or utilize NVMEM for calibration.
+	 * So add a dummy partitions node that bootloader will populate
+	 * and set it as disabled so the kernel ignores it instead of
+	 * printing warnings due to the broken way bootloader adds the
+	 * partitions.
+	 */
+	partitions {
+		status = "disabled";
+	};
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:sbl1";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:mibib";
+				reg = <0x100000 0x100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:bootconfig";
+				reg = <0x200000 0x80000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "0:bootconfig1";
+				reg = <0x280000 0x80000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "0:qsee";
+				reg = <0x300000 0x300000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "0:qsee_1";
+				reg = <0x600000 0x300000>;
+				read-only;
+			};
+
+			partition@900000 {
+				label = "0:devcfg";
+				reg = <0x900000 0x80000>;
+				read-only;
+			};
+
+			partition@980000 {
+				label = "0:devcfg_1";
+				reg = <0x980000 0x80000>;
+				read-only;
+			};
+
+			partition@a00000 {
+				label = "0:apdp";
+				reg = <0xa00000 0x80000>;
+				read-only;
+			};
+
+			partition@a80000 {
+				label = "0:apdp_1";
+				reg = <0xa80000 0x80000>;
+				read-only;
+			};
+
+			partition@b00000 {
+				label = "0:rpm";
+				reg = <0xb00000 0x80000>;
+				read-only;
+			};
+
+			partition@b80000 {
+				label = "0:rpm_1";
+				reg = <0xb80000 0x80000>;
+				read-only;
+			};
+
+			partition@c00000 {
+				label = "0:cdt";
+				reg = <0xc00000 0x80000>;
+				read-only;
+			};
+
+			partition@c80000 {
+				label = "0:cdt_1";
+				reg = <0xc80000 0x80000>;
+				read-only;
+			};
+
+			partition@d00000 {
+				label = "0:appsblenv";
+				reg = <0xd00000 0x80000>;
+			};
+
+			partition@d80000 {
+				label = "0:appsbl";
+				reg = <0xd80000 0x100000>;
+				read-only;
+			};
+
+			partition@e80000 {
+				label = "0:appsbl_1";
+				reg = <0xe80000 0x100000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "0:art";
+				reg = <0xf80000 0x80000>;
+				read-only;
+			};
+
+			partition@1000000 {
+				label = "u_env";
+				reg = <0x1000000 0x40000>;
+			};
+
+			partition@1040000 {
+				label = "s_env";
+				reg = <0x1040000 0x20000>;
+			};
+
+			partition@1060000 {
+				label = "devinfo";
+				reg = <0x1060000 0x20000>;
+				read-only;
+			};
+
+			partition@1080000 {
+				label = "kernel";
+				reg = <0x1080000 0x9600000>;
+			};
+
+			partition@1680000 {
+				label = "rootfs";
+				reg = <0x1680000 0x9000000>;
+			};
+
+			partition@a680000 {
+				label = "alt_kernel";
+				reg = <0xa680000 0x9600000>;
+			};
+
+			partition@ac80000 {
+				label = "alt_rootfs";
+				reg = <0xac80000 0x9000000>;
+			};
+
+			partition@13c80000 {
+				label = "sysdiag";
+				reg = <0x13c80000 0x200000>;
+				read-only;
+			};
+
+			partition@13e80000 {
+				label = "0:ethphyfw";
+				reg = <0x13e80000 0x100000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					aqr_fw: firmware@0 {
+						/* Skip the QCOM MBN Header of 40 bytes */
+						reg = <0x28 0x60002>;
+					};
+				};
+			};
+
+			partition@13f80000 {
+				label = "syscfg";
+				reg = <0x13f80000 0xb180000>;
+				read-only;
+			};
+
+			partition@1f100000 {
+				label = "app_data";
+				reg = <0x1f100000 0x500000>;
+				read-only;
+			};
+
+			partition@1f600000 {
+				label = "0:wififw";
+				reg = <0x1f600000 0xa00000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&blsp1_i2c2 {
+	status = "okay";
+
+	led-controller@62 {
+		compatible = "nxp,pca9633";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x62>;
+		nxp,hw-blink;
+
+		led_system_red: led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_system_green: led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_system_blue: led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "qcom,qca8075-package";
+		reg = <0>;
+
+		qcom,package-mode = "qsgmii";
+
+		qca8075_0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+	};
+
+	aqr114c: ethernet-phy@8 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <8>;
+		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+		firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
+		nvmem-cells = <&aqr_fw>;
+		nvmem-cell-names = "firmware";
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+	switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+	switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+	switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
+
+	qcom,port_phyinfo {
+		port@1 {
+			port_id = <1>;
+			phy_address = <0>;
+		};
+
+		port@2 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+
+		port@3 {
+			port_id = <3>;
+			phy_address = <2>;
+		};
+
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+
+		port@6 {
+			port_id = <6>;
+			phy_address = <8>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+			ethernet-phy-ieee802.3-c45;
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+&dp1 {
+	status = "okay";
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_0>;
+	label = "lan1";
+};
+
+&dp2 {
+	status = "okay";
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_1>;
+	label = "lan2";
+};
+
+&dp3 {
+	status = "okay";
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_2>;
+	label = "lan3";
+};
+
+&dp4 {
+	status = "okay";
+	phy-mode = "qsgmii";
+	phy-handle = <&qca8075_3>;
+	label = "lan4";
+};
+
+&dp6_syn {
+	status = "okay";
+	phy-mode = "usxgmii";
+	phy-handle = <&aqr114c>;
+	label = "wan";
+};
+
+&ssphy_0 {
+	status = "okay";
+};
+
+&qusb_phy_0 {
+	status = "okay";
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&pcie_qmp0 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+	bridge@0,0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+
+		wifi@1,0 {
+			status = "okay";
+
+			/* ath11k has no DT compatible for PCI cards */
+			compatible = "pci17cb,1104";
+			reg = <0x00010000 0 0 0 0>;
+
+			qcom,ath11k-calibration-variant = "Linksys-MX8500";
+		};
+	};
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,ath11k-calibration-variant = "Linksys-MX8500";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts
index 01ac1c5fd6..fbb652a097 100644
--- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-sax1v1k.dts
@@ -136,6 +136,7 @@
 		compatible = "ethernet-phy-id004d.d101";
 		reg = <28>;
 		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+		reset-deassert-us = <10000>;
 	};
 };
 
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi
new file mode 100644
index 0000000000..7f8b813749
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxk80.dtsi
@@ -0,0 +1,541 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021, Flole <flole@flole.de>
+ * Copyright (c) 2023, Andrew Smith <gul.code@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-ess.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		serial0 = &blsp1_uart5;
+		led-boot = &led_front_blue;
+		led-failsafe = &led_front_red;
+		led-running = &led_front_green;
+		led-upgrade = &led_front_white;
+		label-mac-device = &dp2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_front_blue: front-blue {
+			function = LED_FUNCTION_STATUS;
+			gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+
+		led_front_green: front-green {
+			function = LED_FUNCTION_STATUS;
+			gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led_front_red: front-red {
+			function = LED_FUNCTION_STATUS;
+			gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led_front_white: front-white {
+			function = LED_FUNCTION_STATUS;
+			gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_WHITE>;
+		};
+
+		led_power_green: power-green {
+			function = LED_FUNCTION_POWER;
+			gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+		};
+
+		led_power_red: power-red {
+			function = LED_FUNCTION_POWER;
+			gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			panic-indicator;
+		};
+	};
+};
+
+&tlmm {
+	mdio_pins: mdio-pins {
+		mdc {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	leds_pins: leds_pinmux {
+		led_power_green {
+			pins = "gpio21";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_power_red {
+			pins = "gpio22";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_white {
+			pins = "gpio26";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_green {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_red {
+			pins = "gpio31";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_blue {
+			pins = "gpio33";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+};
+
+&blsp1_uart5 {
+	status = "okay";
+};
+
+&blsp1_i2c2 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	
+	tlc59208f@27 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "ti,tlc59108";
+		reg = <0x27>;
+		
+		led@0 {
+			label = "rgb:led0";
+			reg = <0>;
+			linux,default-trigger = "default-off";
+		};
+
+		led@1 {
+			label = "rgb:led1";
+			reg = <1>;
+			linux,default-trigger = "default-off";
+		};
+
+		led@2 {
+			label = "rgb:led2";
+			reg = <2>;
+			linux,default-trigger = "default-off";
+		};
+
+		led@3 {
+			label = "rgb:led3";
+			reg = <3>;
+			linux,default-trigger = "default-off";
+		};
+	};
+};
+
+&prng {
+	status = "okay";
+};
+
+&cryptobam {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
+
+&qpic_bam {
+	status = "okay";
+};
+
+&qpic_nand {
+	status = "okay";
+
+	/*
+	 * Bootloader will find the NAND DT node by the compatible and
+	 * then "fixup" it by adding the partitions from the SMEM table
+	 * using the legacy bindings thus making it impossible for us
+	 * to change the partition table or utilize NVMEM for calibration.
+	 * So add a dummy partitions node that bootloader will populate
+	 * and set it as disabled so the kernel ignores it instead of
+	 * printing warnings due to the broken way bootloader adds the
+	 * partitions.
+	 */
+	partitions {
+		status = "disabled";
+	};
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "0:sbl1";
+				reg = <0x00 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "0:mibib";
+				reg = <0x100000 0x100000>;
+				read-only;
+			};
+
+			partition@200000 {
+				label = "0:bootconfig";
+				reg = <0x200000 0x80000>;
+				read-only;
+			};
+
+			partition@280000 {
+				label = "0:bootconfig_1";
+				reg = <0x280000 0x80000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "0:qsee";
+				reg = <0x300000 0x300000>;
+				read-only;
+			};
+
+			partition@600000 {
+				label = "0:qsee_1";
+				reg = <0x600000 0x300000>;
+				read-only;
+			};
+
+			partition@900000 {
+				label = "0:devcfg";
+				reg = <0x900000 0x80000>;
+				read-only;
+			};
+
+			partition@980000 {
+				label = "0:devcfg_1";
+				reg = <0x980000 0x80000>;
+				read-only;
+			};
+
+			partition@a00000 {
+				label = "0:apdp";
+				reg = <0xa00000 0x80000>;
+				read-only;
+			};
+
+			partition@a80000 {
+				label = "0:apdp_1";
+				reg = <0xa80000 0x80000>;
+				read-only;
+			};
+
+			partition@b00000 {
+				label = "0:rpm";
+				reg = <0xb00000 0x80000>;
+				read-only;
+			};
+
+			partition@b80000 {
+				label = "0:rpm_1";
+				reg = <0xb80000 0x80000>;
+				read-only;
+			};
+
+			partition@c00000 {
+				label = "0:cdt";
+				reg = <0xc00000 0x80000>;
+				read-only;
+			};
+
+			partition@c80000 {
+				label = "0:cdt_1";
+				reg = <0xc80000 0x80000>;
+				read-only;
+			};
+
+			partition@d00000 {
+				label = "0:appsblenv";
+				reg = <0xd00000 0x80000>;
+			};
+
+			partition@d80000 {
+				label = "0:appsbl";
+				reg = <0xd80000 0x100000>;
+				read-only;
+			};
+
+			partition@e80000 {
+				label = "0:appsbl_1";
+				reg = <0xe80000 0x100000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "0:art";
+				reg = <0xf80000 0x80000>;
+				read-only;
+			};
+
+			partition@1000000 {
+				label = "0:art.bak";
+				reg = <0x1000000 0x80000>;
+				read-only;
+			};
+
+			partition@1080000 {
+				label = "config";
+				reg = <0x1080000 0x100000>;
+			};
+
+			partition@1180000 {
+				label = "boarddata1";
+				reg = <0x1180000 0x100000>;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_boarddata1_0: macaddr@0 {
+						reg = <0x0 0x6>;
+					};
+
+					macaddr_boarddata1_6: macaddr@6 {
+						reg = <0x6 0x6>;
+					};
+				};
+			};
+
+			partition@1280000 {
+				label = "boarddata2";
+				reg = <0x1280000 0x100000>;
+			};
+
+			partition@1380000 {
+				label = "pot";
+				reg = <0x1380000 0x100000>;
+				read-only;
+			};
+
+			partition@1480000 {
+				label = "dnidata";
+				reg = <0x1480000 0x500000>;
+				read-only;
+			};
+
+			partition@1980000 {
+				label = "kernel";
+				reg = <0x1980000 0x620000>;
+			};
+
+			partition@1fa0000 {
+				label = "rootfs";
+				reg = <0x1fa0000 0x66e0000>;
+			};
+
+			partition@8680000 {
+				label = "kernel2";
+				reg = <0x8680000 0x620000>;
+				read-only;
+			};
+
+			partition@8ca0000 {
+				label = "rootfs2";
+				reg = <0x8ca0000 0x66e0000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_pins>;
+	pinctrl-names = "default";
+	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+	ethernet-phy-package@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+
+		compatible = "qcom,qca8075-package";
+
+		qca8075_1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		qca8075_2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		qca8075_3: ethernet-phy@3 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <3>;
+		};
+
+		qca8075_4: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+
+	qca8081_28: ethernet-phy@28 {
+		compatible = "ethernet-phy-id004d.d101";
+		reg = <28>;
+		reset-deassert-us = <10000>;
+		reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&switch {
+	status = "okay";
+
+	switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
+	switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+	switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
+	switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
+
+	qcom,port_phyinfo {
+		port@2 {
+			port_id = <2>;
+			phy_address = <1>;
+		};
+		port@3 {
+			port_id = <3>;
+			phy_address = <2>;
+		};
+		port@4 {
+			port_id = <4>;
+			phy_address = <3>;
+		};
+		port@5 {
+			port_id = <5>;
+			phy_address = <4>;
+		};
+		port@6 {
+			port_id = <6>;
+			phy_address = <28>;
+			port_mac_sel = "QGMAC_PORT";
+		};
+	};
+};
+
+&edma {
+	status = "okay";
+};
+
+&dp2 {
+	status = "okay";
+	phy-handle = <&qca8075_1>;
+	label = "lan2";
+	nvmem-cells = <&macaddr_boarddata1_0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+	status = "okay";
+	phy-handle = <&qca8075_2>;
+	label = "lan3";
+	nvmem-cells = <&macaddr_boarddata1_0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+	status = "okay";
+	phy-handle = <&qca8075_3>;
+	label = "lan4";
+	nvmem-cells = <&macaddr_boarddata1_0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+	status = "okay";
+	phy-handle = <&qca8075_4>;
+	label = "lan5";
+	nvmem-cells = <&macaddr_boarddata1_0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&dp6 {
+	status = "okay";
+	phy-handle = <&qca8081_28>;
+	label = "wan";
+	nvmem-cells = <&macaddr_boarddata1_6>;
+	nvmem-cell-names = "mac-address";
+};
+
+&wifi {
+	status = "okay";
+
+	qcom,ath11k-calibration-variant = "Netgear-SXK80";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts
new file mode 100644
index 0000000000..d90e75da30
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxr80.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Flole <flole@flole.de> */
+
+/dts-v1/;
+
+#include "ipq8074-sxk80.dtsi"
+
+/ {
+	model = "Netgear SXR80";
+	compatible = "netgear,sxr80", "qcom,ipq8074";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxs80.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxs80.dts
new file mode 100644
index 0000000000..0d7240cf07
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-sxs80.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Flole <flole@flole.de> */
+
+/dts-v1/;
+
+#include "ipq8074-sxk80.dtsi"
+
+/ {
+	model = "Netgear SXS80";
+	compatible = "netgear,sxs80", "qcom,ipq8074";
+};
diff --git a/target/linux/qualcommax/image/ipq807x.mk b/target/linux/qualcommax/image/ipq807x.mk
index e32250d458..b305c9dbaa 100644
--- a/target/linux/qualcommax/image/ipq807x.mk
+++ b/target/linux/qualcommax/image/ipq807x.mk
@@ -103,20 +103,26 @@ define Device/edimax_cax1800
 endef
 TARGET_DEVICES += edimax_cax1800
 
-define Device/linksys_mx4200v1
+define Device/linksys_mx
 	$(call Device/FitImage)
 	DEVICE_VENDOR := Linksys
-	DEVICE_MODEL := MX4200
-	DEVICE_VARIANT := v1
 	BLOCKSIZE := 128k
 	PAGESIZE := 2048
 	KERNEL_SIZE := 6144k
 	IMAGE_SIZE := 147456k
 	NAND_SIZE := 512m
-	SOC := ipq8174
+	SOC := ipq8072
 	IMAGES += factory.bin
-	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX4200
-	DEVICE_PACKAGES := kmod-leds-pca963x ipq-wifi-linksys_mx4200 kmod-bluetooth
+	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=$$$$(DEVICE_MODEL)
+	DEVICE_PACKAGES := kmod-leds-pca963x
+endef
+
+define Device/linksys_mx4200v1
+	$(call Device/linksys_mx)
+	DEVICE_MODEL := MX4200
+	DEVICE_VARIANT := v1
+	SOC := ipq8174
+	DEVICE_PACKAGES += ipq-wifi-linksys_mx4200 kmod-bluetooth
 endef
 TARGET_DEVICES += linksys_mx4200v1
 
@@ -127,22 +133,21 @@ endef
 TARGET_DEVICES += linksys_mx4200v2
 
 define Device/linksys_mx5300
-	$(call Device/FitImage)
-	DEVICE_VENDOR := Linksys
+	$(call Device/linksys_mx)
 	DEVICE_MODEL := MX5300
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	KERNEL_SIZE := 6144k
-	IMAGE_SIZE := 147456k
-	NAND_SIZE := 512m
-	SOC := ipq8072
-	IMAGES += factory.bin
-	IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX5300
-	DEVICE_PACKAGES := kmod-leds-pca963x kmod-rtc-ds1307 \
-		ipq-wifi-linksys_mx5300 kmod-ath10k-ct ath10k-firmware-qca9984-ct
+	DEVICE_PACKAGES += kmod-rtc-ds1307 ipq-wifi-linksys_mx5300 \
+		kmod-ath10k-ct ath10k-firmware-qca9984-ct
 endef
 TARGET_DEVICES += linksys_mx5300
 
+define Device/linksys_mx8500
+	$(call Device/linksys_mx)
+	DEVICE_MODEL := MX8500
+	DEVICE_PACKAGES += ipq-wifi-linksys_mx8500 kmod-ath11k-pci \
+		ath11k-firmware-qcn9074 kmod-bluetooth
+endef
+TARGET_DEVICES += linksys_mx8500
+
 define Device/netgear_rax120v2
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
@@ -167,6 +172,33 @@ define Device/netgear_rax120v2
 endef
 TARGET_DEVICES += netgear_rax120v2
 
+define Device/netgear_sxk80
+	$(call Device/FitImage)
+	$(call Device/UbiFit)
+	DEVICE_PACKAGES += ipq-wifi-netgear_sxk80
+	DEVICE_VENDOR := Netgear
+	BLOCKSIZE := 128k
+	PAGESIZE := 2048
+	DEVICE_DTS_CONFIG := config@hk01
+	SOC := ipq8074
+	KERNEL_SIZE := 6272k
+	NETGEAR_HW_ID := 29766265+0+512+1024+4x4+4x4+4x4
+endef
+
+define Device/netgear_sxr80
+	$(call Device/netgear_sxk80)
+	DEVICE_MODEL := SXR80
+	NETGEAR_BOARD_ID := SXR80
+endef
+TARGET_DEVICES += netgear_sxr80
+
+define Device/netgear_sxs80
+	$(call Device/netgear_sxk80)
+	DEVICE_MODEL := SXS80
+	NETGEAR_BOARD_ID := SXS80
+endef
+TARGET_DEVICES += netgear_sxs80
+
 define Device/netgear_wax218
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
diff --git a/target/linux/qualcommax/ipq60xx/base-files/etc/init.d/bootcount b/target/linux/qualcommax/ipq60xx/base-files/etc/init.d/bootcount
index 6347976372..b34fbd82d7 100755
--- a/target/linux/qualcommax/ipq60xx/base-files/etc/init.d/bootcount
+++ b/target/linux/qualcommax/ipq60xx/base-files/etc/init.d/bootcount
@@ -2,13 +2,11 @@
 
 START=99
 
-. /lib/functions.sh
-
 boot() {
 	case $(board_name) in
-		yuncore,fap650)
-			fw_setenv owrt_bootcount 0
-		;;
-		esac
+	yuncore,fap650)
+		fw_setenv owrt_bootcount 0
+	;;
+	esac
 }
 
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
index d87e4246e1..0bf224f380 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network
@@ -15,6 +15,7 @@ ipq807x_setup_interfaces()
 	buffalo,wxr-5950ax12|\
 	dynalink,dl-wrx36|\
 	linksys,mx5300|\
+	linksys,mx8500|\
 	xiaomi,ax9000|\
 	zbtlink,zbt-z800ax)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
@@ -42,6 +43,10 @@ ipq807x_setup_interfaces()
 	netgear,rax120v2)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "wan"
 		;;
+	netgear,sxr80|\
+	netgear,sxs80)
+		ucidef_set_interfaces_lan_wan "lan2 lan3 lan4 lan5" "wan"
+		;;
 	netgear,wax218|\
 	netgear,wax620)
 		ucidef_set_interface_lan "lan" "dhcp"
@@ -76,6 +81,11 @@ ipq807x_setup_macs()
 			done
 			[ "$(mtd_get_mac_ascii u_env eth2addr)" != "$label_mac" ] && wan_mac=$label_mac
 		;;
+		linksys,mx8500)
+			label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
+			lan_mac=$(macaddr_add $label_mac 1)
+			wan_mac=$label_mac
+		;;
 	esac
 
 	[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
index 8f207a38b0..106a86be75 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
@@ -17,6 +17,8 @@ case "$FIRMWARE" in
 	edgecore,eap102|\
 	edimax,cax1800|\
 	linksys,mx5300|\
+	netgear,sxr80|\
+	netgear,sxs80|\
 	netgear,wax218|\
 	netgear,wax620|\
 	netgear,wax630|\
@@ -25,12 +27,11 @@ case "$FIRMWARE" in
 	xiaomi,ax3600|\
 	xiaomi,ax9000|\
 	yuncore,ax880|\
-	zbtlink,zbt-z800ax|\
-	zte,mf269|\
-	zyxel,nbg7815)
+	zte,mf269)
 		caldata_extract "0:art" 0x1000 0x20000
 		;;
-	linksys,mx4200v1)
+	linksys,mx4200v1|\
+	linksys,mx8500)
 		caldata_extract "0:art" 0x1000 0x20000
 		ath11k_remove_regdomain
 		;;
@@ -54,11 +55,30 @@ case "$FIRMWARE" in
 	spectrum,sax1v1k)
 		caldata_extract_mmc "0:ART" 0x1000 0x20000
 		;;
+	zbtlink,zbt-z800ax)
+		caldata_extract "0:art" 0x1000 0x20000
+		label_mac=$(get_mac_label)
+		ath11k_patch_mac $(macaddr_add $label_mac -1) 0
+		ath11k_patch_mac $(macaddr_add $label_mac -2) 1
+		ath11k_set_macflag
+		;;
+	zyxel,nbg7815)
+		caldata_extract "0:art" 0x1000 0x20000
+		label_mac=$(get_mac_label)
+		ath11k_patch_mac $(macaddr_add $label_mac 3) 0
+		ath11k_patch_mac $(macaddr_add $label_mac 2) 1
+		ath11k_patch_mac $(macaddr_add $label_mac 4) 2
+		ath11k_set_macflag
+		;;
 	esac
 	;;
 "ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\
 "ath11k/QCN9074/hw1.0/cal-pci-0001:01:00.0.bin")
 	case "$board" in
+	linksys,mx8500)
+		caldata_extract "0:art" 0x26800 0x20000
+		ath11k_remove_regdomain
+		;;
 	prpl,haze)
 		caldata_extract_mmc "0:ART" 0x26800 0x20000
 		;;
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
index 17284a0d9e..75a548d1c6 100644
--- a/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
@@ -23,8 +23,11 @@ case "$board" in
 		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
 		;;
-	zbtlink,zbt-z800ax)
-		[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) -1 > /sys${DEVPATH}/macaddress
-		[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) -2 > /sys${DEVPATH}/macaddress
+	netgear,sxr80|\
+	netgear,sxs80)
+		[ "$PHYNBR" = "0" ] && mtd_get_mac_binary boarddata1 0x0c > /sys${DEVPATH}/macaddress
+		#boarddata1 doesn't have a MAC for the 2G interface
+		[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(get_mac_label) > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "2" ] && mtd_get_mac_binary boarddata1 0x12 > /sys${DEVPATH}/macaddress
 		;;
 esac
diff --git a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
index 3e81caf63f..26da7cd614 100755
--- a/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
+++ b/target/linux/qualcommax/ipq807x/base-files/etc/init.d/bootcount
@@ -12,7 +12,8 @@ boot() {
 	;;
 	linksys,mx4200v1|\
 	linksys,mx4200v2|\
-	linksys,mx5300)
+	linksys,mx5300|\
+	linksys,mx8500)
 		mtd resetbc s_env || true
 	;;
 	esac
diff --git a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
index b9668d0af4..2008334213 100644
--- a/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh
@@ -49,6 +49,8 @@ platform_do_upgrade() {
 	dynalink,dl-wrx36|\
 	edimax,cax1800|\
 	netgear,rax120v2|\
+	netgear,sxr80|\
+	netgear,sxs80|\
 	netgear,wax218|\
 	netgear,wax620|\
 	netgear,wax630|\
@@ -77,7 +79,8 @@ platform_do_upgrade() {
 		;;
 	linksys,mx4200v1|\
 	linksys,mx4200v2|\
-	linksys,mx5300)
+	linksys,mx5300|\
+	linksys,mx8500)
 		boot_part="$(fw_printenv -n boot_part)"
 		if [ "$boot_part" -eq "1" ]; then
 			fw_setenv boot_part 2
diff --git a/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch b/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch
new file mode 100644
index 0000000000..e075c590fb
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.6/0063-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch
@@ -0,0 +1,32 @@
+From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 13 Mar 2024 11:27:06 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
+
+gpio16 will only be used for LCD support, as its NAND/LCDC data[8]
+so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8
+or 16-bit with only 8-bit one being supported in our case so that pin
+is unused.
+
+It should be dropped from the default NAND pinctrl configuration
+as its unused and only needed for LCD.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -372,7 +372,7 @@
+ 				       "gpio5", "gpio6", "gpio7",
+ 				       "gpio8", "gpio10", "gpio11",
+ 				       "gpio12", "gpio13", "gpio14",
+-				       "gpio15", "gpio16", "gpio17";
++				       "gpio15", "gpio17";
+ 				function = "qpic";
+ 				drive-strength = <8>;
+ 				bias-disable;
diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile
index fec2a2b1f8..1429fdd655 100644
--- a/target/linux/ramips/Makefile
+++ b/target/linux/ramips/Makefile
@@ -10,8 +10,7 @@ BOARDNAME:=MediaTek Ralink MIPS
 SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883
 FEATURES:=squashfs gpio
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware images for Ralink RT288x/RT3xxx based boards.
diff --git a/target/linux/ramips/dts/mt7620a.dtsi b/target/linux/ramips/dts/mt7620a.dtsi
index 0fa503e7a2..65122304c9 100644
--- a/target/linux/ramips/dts/mt7620a.dtsi
+++ b/target/linux/ramips/dts/mt7620a.dtsi
@@ -294,7 +294,7 @@
 		};
 
 		gdma: gdma@2800 {
-			compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
+			compatible = "ralink,rt3883-gdma";
 			reg = <0x2800 0x800>;
 
 			resets = <&sysc 14>;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
index 10756e3b3c..45cafdbcd1 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts
@@ -19,13 +19,13 @@
 	leds {
 		compatible = "gpio-leds";
 
-		lan {
+		led-0 {
 			function = LED_FUNCTION_LAN;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
-		usb {
+		led-1 {
 			function = LED_FUNCTION_USB;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
@@ -33,19 +33,19 @@
 			linux,default-trigger = "usbport";
 		};
 
-		led_wps: wps {
+		led_wps: led-2 {
 			function = LED_FUNCTION_WPS;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
-		wan {
+		led-3 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
-		wlan {
+		led-4 {
 			function = LED_FUNCTION_WLAN;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
@@ -55,7 +55,6 @@
 
 	rtl8367rb {
 		compatible = "realtek,rtl8367b";
-		cpu_port = <6>;
 		realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
 	};
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
index 285e27c357..6b49fa6793 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts
@@ -16,20 +16,20 @@
 	leds {
 		compatible = "gpio-leds";
 
-		lan {
+		led-0 {
 			function = LED_FUNCTION_LAN;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
-		led_power: power {
+		led_power: led-1 {
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
-		usb {
+		led-2 {
 			function = LED_FUNCTION_USB;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
@@ -37,31 +37,33 @@
 			linux,default-trigger = "usbport";
 		};
 
-		wan {
+		led-3 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		wan_orange {
+		led-4 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 		};
 
-		wlan5g {
-			label = "blue:wlan5g";
+		led-5 {
+			function = LED_FUNCTION_WLAN_5GHZ;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
-		wlan2g {
-			label = "blue:wlan2g";
+		led-6 {
+			function = LED_FUNCTION_WLAN_2GHZ;
+			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
 
-		wps {
+		led-7 {
 			function = LED_FUNCTION_WPS;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
index 12141a6e59..0e461ceba5 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts
@@ -17,13 +17,13 @@
 	leds {
 		compatible = "gpio-leds";
 
-		lan {
+		led-0 {
 			function = LED_FUNCTION_LAN;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
-		usb {
+		led-1 {
 			function = LED_FUNCTION_USB;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
@@ -31,19 +31,19 @@
 			linux,default-trigger = "usbport";
 		};
 
-		led_wps: wps {
+		led_wps: led-2 {
 			function = LED_FUNCTION_WPS;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
 
-		wan {
+		led-3 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 		};
 
-		wlan {
+		led-4 {
 			function = LED_FUNCTION_WLAN;
 			color = <LED_COLOR_ID_BLUE>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts
index 1ed156e8af..855e06e9f6 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c5-v4.dts
@@ -74,7 +74,6 @@
 
 	rtl8367s {
 		compatible = "realtek,rtl8367b";
-		cpu_port = <7>;
 		realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
 		phy-id = <29>;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts b/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
index 97b803470d..8581bbe49b 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts
@@ -16,20 +16,20 @@
 	leds {
 		compatible = "gpio-leds";
 
-		lan {
+		led-0 {
 			function = LED_FUNCTION_LAN;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
 		};
 
-		led_power: power {
+		led_power: led-1 {
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
 			default-state = "on";
 		};
 
-		usb {
+		led-2 {
 			function = LED_FUNCTION_USB;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
@@ -37,31 +37,33 @@
 			linux,default-trigger = "usbport";
 		};
 
-		wan {
+		led-3 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 		};
 
-		wan_orange {
+		led-4 {
 			function = LED_FUNCTION_WAN;
 			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 		};
 
-		wlan5g {
-			label = "green:wlan5g";
+		led-5 {
+			function = LED_FUNCTION_WLAN_5GHZ;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy0tpt";
 		};
 
-		wlan2g {
-			label = "green:wlan2g";
+		led-6 {
+			function = LED_FUNCTION_WLAN_2GHZ;
+			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 			linux,default-trigger = "phy1tpt";
 		};
 
-		wps {
+		led-7 {
 			function = LED_FUNCTION_WPS;
 			color = <LED_COLOR_ID_GREEN>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
diff --git a/target/linux/ramips/dts/mt7620a_tplink_ec220-g5-v2.dts b/target/linux/ramips/dts/mt7620a_tplink_ec220-g5-v2.dts
index 6ac1a9c5d5..7fc075aedd 100644
--- a/target/linux/ramips/dts/mt7620a_tplink_ec220-g5-v2.dts
+++ b/target/linux/ramips/dts/mt7620a_tplink_ec220-g5-v2.dts
@@ -82,7 +82,6 @@
 
 	rtl8367s {
 		compatible = "realtek,rtl8367b";
-		cpu_port = <7>;
 		realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
 		phy-id = <29>;
diff --git a/target/linux/ramips/dts/mt7620a_wavlink_wl-wn531g3.dts b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn531g3.dts
new file mode 100644
index 0000000000..d48f27fdc7
--- /dev/null
+++ b/target/linux/ramips/dts/mt7620a_wavlink_wl-wn531g3.dts
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "mt7620a.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "wavlink,wl-wn531g3", "ralink,mt7620a-soc";
+	model = "Wavlink WL-WN531G3";
+
+	aliases {
+		led-boot = &led_status_blue;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_blue;
+		led-upgrade = &led_status_red;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		turbo {
+			label = "turbo";
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_1>;
+		};
+
+		wps {
+			label = "wps";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		touchlink {
+			label = "touchlink";
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_blue: led_status_blue {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_red: led_status_red {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x30000>;
+				read-only;
+			};
+
+			partition@30000 {
+				label = "u-boot-env";
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			factory: partition@40000 {
+				label = "factory";
+				reg = <0x40000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_factory_28: macaddr@28 {
+						reg = <0x28 0x6>;
+					};
+
+					macaddr_factory_2e: macaddr@2e {
+						reg = <0x2e 0x6>;
+					};
+
+					eeprom_radio_0: eeprom@0 {
+						reg = <0x0 0x200>;
+					};
+
+					eeprom_radio_8000: eeprom@8000 {
+						reg = <0x8000 0x200>;
+					};
+				};
+			};
+
+			partition@50000 {
+				label = "params";
+				reg = <0x50000 0x10000>;
+				read-only;
+			};
+
+			partition@60000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x60000 0x7a0000>;
+			};
+		};
+	};
+};
+
+&ethernet {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii1_pins>, <&rgmii2_pins>, <&mdio_pins>;
+
+	nvmem-cells = <&macaddr_factory_28>;
+	nvmem-cell-names = "mac-address";
+
+	mediatek,portmap = "llllw";
+
+	port@4 {
+		status = "okay";
+		phy-handle = <&phy4>;
+		phy-mode = "rgmii";
+
+		nvmem-cells = <&macaddr_factory_2e>;
+		nvmem-cell-names = "mac-address";
+	};
+
+	port@5 {
+		status = "okay";
+		phy-handle = <&phy5>;
+		phy-mode = "rgmii";
+	};
+
+	mdio-bus {
+		status = "okay";
+
+		phy4: ethernet-phy@4 {
+			reg = <4>;
+			phy-mode = "rgmii";
+		};
+
+		phy5: ethernet-phy@5 {
+			reg = <5>;
+			phy-mode = "rgmii";
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	mt76@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_radio_8000>;
+		nvmem-cell-names = "eeprom";
+		ieee80211-freq-limit = <5000000 6000000>;
+	};
+};
+
+&gsw {
+	mediatek,port4-gmac;
+};
+
+&wmac {
+	nvmem-cells = <&eeprom_radio_0>;
+	nvmem-cell-names = "eeprom";
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uartf";
+		function = "gpio";
+	};
+};
diff --git a/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts b/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
index e96ca9ace6..0630e8a160 100644
--- a/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
+++ b/target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
@@ -85,7 +85,6 @@
 
 	rtl8367rb {
 		compatible = "realtek,rtl8367b";
-		cpu_port = <7>;
 		realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
 		mii-bus = <&mdio0>;
 	};
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 086719a43d..54fe13123d 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -474,6 +474,36 @@
 				#interrupt-cells = <1>;
 				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					ethphy0: ethernet-phy@0 {
+						reg = <0>;
+						interrupts = <0>;
+					};
+
+					ethphy1: ethernet-phy@1 {
+						reg = <1>;
+						interrupts = <1>;
+					};
+
+					ethphy2: ethernet-phy@2 {
+						reg = <2>;
+						interrupts = <2>;
+					};
+
+					ethphy3: ethernet-phy@3 {
+						reg = <3>;
+						interrupts = <3>;
+					};
+
+					ethphy4: ethernet-phy@4 {
+						reg = <4>;
+						interrupts = <4>;
+					};
+				};
+
 				ports {
 					#address-cells = <1>;
 					#size-cells = <0>;
@@ -482,30 +512,35 @@
 						status = "disabled";
 						reg = <0>;
 						label = "lan0";
+						phy-handle = <&ethphy0>;
 					};
 
 					port@1 {
 						status = "disabled";
 						reg = <1>;
 						label = "lan1";
+						phy-handle = <&ethphy1>;
 					};
 
 					port@2 {
 						status = "disabled";
 						reg = <2>;
 						label = "lan2";
+						phy-handle = <&ethphy2>;
 					};
 
 					port@3 {
 						status = "disabled";
 						reg = <3>;
 						label = "lan3";
+						phy-handle = <&ethphy3>;
 					};
 
 					port@4 {
 						status = "disabled";
 						reg = <4>;
 						label = "lan4";
+						phy-handle = <&ethphy4>;
 					};
 
 					port@6 {
diff --git a/target/linux/ramips/dts/mt7621_adslr_g7.dts b/target/linux/ramips/dts/mt7621_adslr_g7.dts
index 6ca9eccd2d..2dea282bf5 100644
--- a/target/linux/ramips/dts/mt7621_adslr_g7.dts
+++ b/target/linux/ramips/dts/mt7621_adslr_g7.dts
@@ -136,10 +136,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
index 4f942f1602..f2f5719af2 100644
--- a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
+++ b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts
@@ -155,10 +155,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
index 85fda96ce5..c0e208d33d 100644
--- a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
+++ b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts
@@ -176,10 +176,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts b/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts
index 07e0d23788..6280a643a9 100644
--- a/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts
+++ b/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts
@@ -13,10 +13,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
index 48506907eb..4a5194c363 100644
--- a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
+++ b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts
@@ -203,10 +203,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &pcie {
diff --git a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
index 78627b2157..ec9da152ce 100644
--- a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
+++ b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi
@@ -185,10 +185,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
index edfdc9b173..2f03082688 100644
--- a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
+++ b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi
@@ -111,10 +111,8 @@
 	status = "okay";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &gmac0 {
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
index 4915f8125e..d5b46b14ee 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts
@@ -170,10 +170,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
index 5bccddec0b..bee8afdc90 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
+++ b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi
@@ -166,10 +166,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
index faf58e0187..76645987b2 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts
@@ -183,10 +183,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
index 7bb375cb29..972b3d5bd8 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts
@@ -157,10 +157,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
index b18bd113da..d73dfe9421 100644
--- a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
+++ b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts
@@ -182,10 +182,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
index 12ff04ed28..e2fa019d07 100644
--- a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
+++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts
@@ -216,10 +216,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
index 84ec15b872..56080ff917 100644
--- a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
+++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts
@@ -209,10 +209,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
index 25fc335c56..be519abf6e 100644
--- a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
+++ b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts
@@ -162,10 +162,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
index c065997ea1..4346e4b9d2 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts
@@ -155,7 +155,7 @@
 			};
 
 			partition@50000 {
-				compatible = "openwrt,trx";
+				compatible = "brcm,trx";
 				label = "firmware";
 				reg = <0x50000 0xf90000>;
 			};
@@ -174,10 +174,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
index 66b47d2fa0..fe6fc6aab5 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts
@@ -159,7 +159,7 @@
 			};
 
 			partition@50000 {
-				compatible = "openwrt,trx";
+				compatible = "brcm,trx";
 				label = "firmware";
 				reg = <0x50000 0x7c0000>;
 			};
@@ -199,10 +199,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl2.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl2.dts
new file mode 100644
index 0000000000..d189a5ba09
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl2.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_buffalo_wsr-2533dhplx.dtsi"
+
+/ {
+	compatible = "buffalo,wsr-2533dhpl2", "mediatek,mt7621-soc";
+	model = "Buffalo WSR-2533DHPL2";
+
+	chosen {
+		bootargs = "console=ttyS0,57600n8 ubi.block=0,rootfs root=/dev/ubiblock0_0";
+	};
+};
+
+&nand {
+	status = "okay";
+
+	mediatek,bbt;
+	/*
+	 * -  u-boot - (kernel (6MiB, in "firmware"))
+	 * - Kernel2 - board_data
+	 */
+	mediatek,bmt-remap-range = <0x0 0x740000>,
+				   <0x3e60000 0x4120000>;
+};
+
+&partitions {
+	partition@100000 {
+		label = "factory";
+		reg = <0x100000 0x40000>;
+		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			eeprom_factory_0: eeprom@0 {
+				reg = <0x0 0x4da8>;
+			};
+
+			eeprom_factory_8000: eeprom@8000 {
+				reg = <0x8000 0x4da8>;
+			};
+		};
+	};
+
+	partition@140000 {
+		compatible = "brcm,trx";
+		brcm,trx-magic = <0x324c4850>;
+		label = "firmware";
+		reg = <0x140000 0x3d20000>;
+	};
+
+	partition@3e60000 {
+		label = "Kernel2";
+		reg = <0x3e60000 0x3d20000>;
+	};
+
+	partition@7b80000 {
+		label = "glbcfg";
+		reg = <0x7b80000 0x200000>;
+		read-only;
+	};
+
+	partition@7d80000 {
+		label = "board_data";
+		reg = <0x7d80000 0x200000>;
+		read-only;
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpls.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpls.dts
new file mode 100644
index 0000000000..9ed94cf7b2
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpls.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_buffalo_wsr-2533dhplx.dtsi"
+
+/ {
+	compatible = "buffalo,wsr-2533dhpls", "mediatek,mt7621-soc";
+	model = "Buffalo WSR-2533DHPLS";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 ubi.block=0,rootfs root=/dev/ubiblock0_0";
+	};
+};
+
+&nand {
+	status = "okay";
+
+	mediatek,nmbm;
+	/*
+	 * -  u-boot - (kernel (6MiB, in "firmware"))
+	 * - Kernel2 - WTB
+	 */
+	mediatek,bmt-remap-range = <0x0 0x780000>,
+				   <0x1980000 0x5b00000>;
+};
+
+&partitions {
+	partition@100000 {
+		label = "factory";
+		reg = <0x100000 0x80000>;
+		read-only;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			eeprom_factory_0: eeprom@0 {
+				reg = <0x0 0x4da8>;
+			};
+
+			eeprom_factory_8000: eeprom@8000 {
+				reg = <0x8000 0x4da8>;
+			};
+		};
+	};
+
+	partition@180000 {
+		compatible = "brcm,trx";
+		brcm,trx-magic = <0x534c4844>;
+		label = "firmware";
+		reg = <0x180000 0x1800000>;
+	};
+
+	partition@1980000 {
+		label = "Kernel2";
+		reg = <0x1980000 0x1800000>;
+	};
+
+	partition@3180000 {
+		label = "glbcfg";
+		reg = <0x3180000 0x200000>;
+		read-only;
+	};
+
+	partition@3380000 {
+		label = "board_data";
+		reg = <0x3380000 0x200000>;
+		read-only;
+	};
+
+	partition@3580000 {
+		label = "debug_log";
+		reg = <0x3580000 0x900000>;
+		read-only;
+	};
+
+	partition@3e80000 {
+		label = "WTB";
+		reg = <0x3e80000 0x3600000>;
+		read-only;
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhplx.dtsi b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhplx.dtsi
new file mode 100644
index 0000000000..33d23d4675
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhplx.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_amber;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = "router";
+		};
+
+		led-1 {
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_WLAN;
+		};
+
+		led-2 {
+			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_WAN_ONLINE;
+		};
+
+		led-3 {
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN_ONLINE;
+		};
+
+		led_power_green: led-4 {
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+		};
+
+		led_power_amber: led-5 {
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_POWER;
+		};
+
+		led-6 {
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN;
+		};
+
+		led-7 {
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = "router";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		button-aoss {
+			label = "aoss";
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		switch-router {
+			label = "router";
+			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+			linux,code = <BTN_0>;
+			linux,input-type = <EV_SW>;
+		};
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	label = "wan";
+	phy-handle = <&ethphy0>;
+};
+
+&ethphy0 {
+	/delete-property/ interrupts;
+};
+
+&switch0 {
+	ports {
+		port@1 {
+			status = "okay";
+			label = "lan1";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan3";
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partitions: partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <0x01>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0x00 0x80000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "u-boot-env";
+			reg = <0x80000 0x80000>;
+			read-only;
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi@0,0 {
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_0>;
+		nvmem-cell-names = "eeprom";
+		ieee80211-freq-limit = <2400000 2500000>;
+	};
+};
+
+&pcie1 {
+	wifi@0,0 {
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_8000>;
+		nvmem-cell-names = "eeprom";
+		ieee80211-freq-limit = <5000000 6000000>;
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uart2", "uart3";
+		function = "gpio";
+	};
+};
+
+&xhci {
+	status = "disabled";
+};
diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
index e3b165c640..00b2165836 100644
--- a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
+++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts
@@ -208,10 +208,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_cudy_m1800.dts b/target/linux/ramips/dts/mt7621_cudy_m1800.dts
index 12f5ce3ec9..1aa5821006 100644
--- a/target/linux/ramips/dts/mt7621_cudy_m1800.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_m1800.dts
@@ -66,10 +66,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &pcie {
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
index 9d5701a7cc..265b48143e 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts
@@ -193,10 +193,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
index 55da73dcda..da62648bc9 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
+++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi
@@ -153,10 +153,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
index 5b21cff130..8278551267 100644
--- a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
+++ b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts
@@ -208,10 +208,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
index 81a34e9302..0542640f13 100644
--- a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
+++ b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi
@@ -116,10 +116,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
index 90a5c196fc..cf924cffb6 100644
--- a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts
@@ -184,10 +184,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
index 13883f9f74..a818400342 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include <dt-bindings/leds/common.h>
-
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
 
 / {
 	compatible = "dlink,dir-1960-a1", "mediatek,mt7621-soc";
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-2055-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-2055-a1.dts
new file mode 100644
index 0000000000..b1c89a4b01
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-2055-a1.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_dlink_dir_nand_128m.dtsi"
+
+/ {
+	compatible = "dlink,dir-2055-a1", "mediatek,mt7621-soc";
+	model = "D-Link DIR-2055 A1";
+};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-2150-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-2150-a1.dts
new file mode 100755
index 0000000000..90a76de8ff
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-2150-a1.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_dlink_dir_nand_128m.dtsi"
+
+/ {
+	compatible = "dlink,dir-2150-a1", "mediatek,mt7621-soc";
+	model = "D-Link DIR-2150 A1";
+};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-2640-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-2640-a1.dts
index d4b8069a33..ba7b9a88dc 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-2640-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-2640-a1.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
 
 / {
 	compatible = "dlink,dir-2640-a1", "mediatek,mt7621-soc";
@@ -8,15 +8,19 @@
 };
 
 &leds {
-	usb2_white {
-		label = "white:usb2";
+	led-4 {
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_WHITE>;
+		function-enumerator = <2>;
 		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&ehci_port2>;
 		linux,default-trigger = "usbport";
 	};
 
-	usb3_white {
-		label = "white:usb3";
+	led-5 {
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_WHITE>;
+		function-enumerator = <3>;
 		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&xhci_ehci_port1>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-2660-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-2660-a1.dts
index a4590cb35f..2ee0b8a5c3 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-2660-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-2660-a1.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
 
 / {
 	compatible = "dlink,dir-2660-a1", "mediatek,mt7621-soc";
@@ -8,15 +8,19 @@
 };
 
 &leds {
-	usb2_white {
-		label = "white:usb2";
+	led-4 {
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_WHITE>;
+		function-enumerator = <2>;
 		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&ehci_port2>;
 		linux,default-trigger = "usbport";
 	};
 
-	usb3_white {
-		label = "white:usb3";
+	led-5 {
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_WHITE>;
+		function-enumerator = <3>;
 		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&xhci_ehci_port1>;
 		linux,default-trigger = "usbport";
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-3040-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-3040-a1.dts
index 4bb35a948d..5044ba3bdc 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-3040-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-3040-a1.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
 
 / {
 	compatible = "dlink,dir-3040-a1", "mediatek,mt7621-soc";
@@ -12,32 +12,32 @@
 };
 
 &leds {
-	usb2_white {
+	led-4 {
 		function = LED_FUNCTION_USB;
 		color = <LED_COLOR_ID_WHITE>;
-		function-enumerator = <0>;
+		function-enumerator = <2>;
 		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&ehci_port2>;
 		linux,default-trigger = "usbport";
 	};
 
-	usb3_white {
+	led-5 {
 		function = LED_FUNCTION_USB;
 		color = <LED_COLOR_ID_WHITE>;
-		function-enumerator = <1>;
+		function-enumerator = <3>;
 		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 		trigger-sources = <&xhci_ehci_port1>;
 		linux,default-trigger = "usbport";
 	};
 
-	wlan2g {
+	led-6 {
 		function = LED_FUNCTION_WLAN_2GHZ;
 		color = <LED_COLOR_ID_WHITE>;
 		gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 		linux,default-trigger = "phy0radio";
 	};
 
-	wlan5glb {
+	led-7 {
 		function = LED_FUNCTION_WLAN_5GHZ;
 		color = <LED_COLOR_ID_WHITE>;
 		function-enumerator = <0>;
@@ -45,7 +45,7 @@
 		linux,default-trigger = "phy1radio";
 	};
 
-	wlan5ghb {
+	led-8 {
 		function = LED_FUNCTION_WLAN_5GHZ;
 		color = <LED_COLOR_ID_WHITE>;
 		function-enumerator = <1>;
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
index f581095a81..89e1189cf7 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-3060-a1.dts
@@ -37,56 +37,67 @@
 	leds {
 		compatible = "gpio-leds";
 
-		led_power_orange: power_orange {
+		led_power_orange: led-0 {
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
-		led_power_white: power_white {
+		led_power_white: led-1 {
 			function = LED_FUNCTION_POWER;
 			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 
-		led_net_orange: net_orange {
-			label = "orange:net";
+		led_net_orange: led-2 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
 			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
 		};
 
-		net_white {
-			label = "white:net";
+		led-3 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
 		};
 
-		usb2_white {
-			label = "white:usb2";
+		led-4 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
+			function-enumerator = <2>;
 			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&ehci_port2>;
 			linux,default-trigger = "usbport";
 		};
 
-		usb3_white {
-			label = "white:usb3";
+		led-5 {
+			function = LED_FUNCTION_USB;
+			color = <LED_COLOR_ID_WHITE>;
+			function-enumerator = <3>;
 			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
 			trigger-sources = <&xhci_ehci_port1>;
 			linux,default-trigger = "usbport";
 		};
 
-		wlan2g {
-			label = "white:wlan2g";
+		led-6 {
+			function = LED_FUNCTION_WLAN_2GHZ;
+			color = <LED_COLOR_ID_WHITE>;
 			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy0radio";
 		};
 
-		wlan5glb {
-			label = "white:wlan5glb";
+		led-7 {
+			function = LED_FUNCTION_WLAN_5GHZ;
+			color = <LED_COLOR_ID_WHITE>;
+			function-enumerator = <0>;
 			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy1radio";
 		};
 
-		wlan5ghb {
-			label = "white:wlan5ghb";
+		led-8 {
+			function = LED_FUNCTION_WLAN_5GHZ;
+			color = <LED_COLOR_ID_WHITE>;
+			function-enumerator = <1>;
 			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "phy2radio";
 		};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
index 7e5809ed3a..7bc3a3f186 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
@@ -187,10 +187,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
index 434a6d9f1a..9d47674959 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts
@@ -203,10 +203,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
index a3753f37d4..25d2768d23 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts
@@ -120,10 +120,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
index 8939e523fe..589669c36a 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts
@@ -144,10 +144,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
index 11d673dc87..0f5b4f0d90 100644
--- a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
+++ b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi
@@ -110,10 +110,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi
deleted file mode 100644
index 57652fb278..0000000000
--- a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "mt7621.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	aliases {
-		label-mac-device = &gmac0;
-		led-boot = &led_power_orange;
-		led-failsafe = &led_power_white;
-		led-running = &led_power_white;
-		led-upgrade = &led_net_orange;
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-
-		wps: wps {
-			label = "wps";
-			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	leds: leds {
-		compatible = "gpio-leds";
-
-		led_power_orange: power_orange {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_ORANGE>;
-			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
-		};
-
-		led_power_white: power_white {
-			function = LED_FUNCTION_POWER;
-			color = <LED_COLOR_ID_WHITE>;
-			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
-		};
-
-		led_net_orange: net_orange {
-			label = "orange:net";
-			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
-		};
-
-		net_white {
-			label = "white:net";
-			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
-		};
-	};
-};
-
-&nand {
-	status = "okay";
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		partition@0 {
-			label = "Bootloader";
-			reg = <0x0 0x80000>;
-			read-only;
-		};
-
-		partition@80000 {
-			label = "config";
-			reg = <0x80000 0x80000>;
-			read-only;
-		};
-
-		partition@100000 {
-			label = "factory";
-			reg = <0x100000 0x40000>;
-			read-only;
-
-			nvmem-layout {
-				compatible = "fixed-layout";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				eeprom_factory_0: eeprom@0 {
-					reg = <0x0 0x4da8>;
-				};
-
-				eeprom_factory_8000: eeprom@8000 {
-					reg = <0x8000 0x4da8>;
-				};
-
-				macaddr_factory_e000: macaddr@e000 {
-					compatible = "mac-base";
-					reg = <0xe000 0x6>;
-					#nvmem-cell-cells = <1>;
-				};
-			};
-		};
-
-		partition@140000 {
-			label = "config2";
-			reg = <0x140000 0x40000>;
-			read-only;
-		};
-
-		partition@180000 {
-			label = "firmware";
-			compatible = "openwrt,uimage", "denx,uimage";
-			openwrt,padding = <96>;
-			reg = <0x180000 0x2800000>;
-		};
-
-		partition@2980000 {
-			label = "private";
-			reg = <0x2980000 0x2000000>;
-			read-only;
-		};
-
-		partition@4980000 {
-			label = "firmware2";
-			reg = <0x4980000 0x2800000>;
-		};
-
-		partition@7180000 {
-			label = "mydlink";
-			reg = <0x7180000 0x600000>;
-			read-only;
-		};
-
-		partition@7780000 {
-			label = "reserved";
-			reg = <0x7780000 0x880000>;
-			read-only;
-		};
-	};
-};
-
-&pcie {
-	status = "okay";
-};
-
-&pcie0 {
-	wifi0: wifi@0,0 {
-		compatible = "mediatek,mt76";
-		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
-		nvmem-cell-names = "eeprom", "mac-address";
-		ieee80211-freq-limit = <2400000 2500000>;
-
-		led {
-			led-active-low;
-		};
-	};
-};
-
-&pcie1 {
-	wifi1: wifi@0,0 {
-		compatible = "mediatek,mt76";
-		reg = <0x0000 0 0 0 0>;
-		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
-		nvmem-cell-names = "eeprom", "mac-address";
-		ieee80211-freq-limit = <5000000 6000000>;
-
-		led {
-			led-active-low;
-		};
-	};
-};
-
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_e000 0>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
-	status = "okay";
-	label = "wan";
-	phy-handle = <&ethphy4>;
-
-	nvmem-cells = <&macaddr_factory_e000 3>;
-	nvmem-cell-names = "mac-address";
-};
-
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-};
-
-&switch0 {
-	ports {
-		port@0 {
-			status = "okay";
-			label = "lan4";
-		};
-
-		port@1 {
-			status = "okay";
-			label = "lan3";
-		};
-
-		port@2 {
-			status = "okay";
-			label = "lan2";
-		};
-
-		port@3 {
-			status = "okay";
-			label = "lan1";
-		};
-	};
-};
-
-&state_default {
-	gpio {
-		groups = "i2c", "uart3", "jtag", "wdt";
-		function = "gpio";
-	};
-};
diff --git a/target/linux/ramips/dts/mt7621_dlink_dir_nand_128m.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir_nand_128m.dtsi
new file mode 100644
index 0000000000..147d64c4b0
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_dlink_dir_nand_128m.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		label-mac-device = &gmac0;
+		led-boot = &led_power_orange;
+		led-failsafe = &led_power_white;
+		led-running = &led_power_white;
+		led-upgrade = &led_net_orange;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		wps: wps {
+			label = "wps";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		led_power_orange: led-0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_ORANGE>;
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_white: led-1 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+		};
+
+		led_net_orange: led-2 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_ORANGE>;
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		led-3 {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "Bootloader";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "config";
+			reg = <0x80000 0x80000>;
+			read-only;
+		};
+
+		partition@100000 {
+			label = "factory";
+			reg = <0x100000 0x40000>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				eeprom_factory_0: eeprom@0 {
+					reg = <0x0 0x4da8>;
+				};
+
+				eeprom_factory_8000: eeprom@8000 {
+					reg = <0x8000 0x4da8>;
+				};
+
+				macaddr_factory_e000: macaddr@e000 {
+					compatible = "mac-base";
+					reg = <0xe000 0x6>;
+					#nvmem-cell-cells = <1>;
+				};
+			};
+		};
+
+		partition@140000 {
+			label = "config2";
+			reg = <0x140000 0x40000>;
+			read-only;
+		};
+
+		partition@180000 {
+			label = "firmware";
+			compatible = "openwrt,uimage", "denx,uimage";
+			openwrt,padding = <96>;
+			reg = <0x180000 0x2800000>;
+		};
+
+		partition@2980000 {
+			label = "private";
+			reg = <0x2980000 0x2000000>;
+			read-only;
+		};
+
+		partition@4980000 {
+			label = "firmware2";
+			reg = <0x4980000 0x2800000>;
+		};
+
+		partition@7180000 {
+			label = "mydlink";
+			reg = <0x7180000 0x600000>;
+			read-only;
+		};
+
+		partition@7780000 {
+			label = "reserved";
+			reg = <0x7780000 0x880000>;
+			read-only;
+		};
+	};
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi0: wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
+		nvmem-cell-names = "eeprom", "mac-address";
+		ieee80211-freq-limit = <2400000 2500000>;
+
+		led {
+			led-active-low;
+		};
+	};
+};
+
+&pcie1 {
+	wifi1: wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
+		nvmem-cell-names = "eeprom", "mac-address";
+		ieee80211-freq-limit = <5000000 6000000>;
+
+		led {
+			led-active-low;
+		};
+	};
+};
+
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_e000 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+	status = "okay";
+	label = "wan";
+	phy-handle = <&ethphy4>;
+
+	nvmem-cells = <&macaddr_factory_e000 3>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ethphy4 {
+	/delete-property/ interrupts;
+};
+
+&switch0 {
+	ports {
+		port@0 {
+			status = "okay";
+			label = "lan4";
+		};
+
+		port@1 {
+			status = "okay";
+			label = "lan3";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan1";
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uart3", "jtag", "wdt";
+		function = "gpio";
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
index d7309dbdfe..8e7652cac7 100644
--- a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
+++ b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi
@@ -151,10 +151,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts b/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts
new file mode 100644
index 0000000000..42517529af
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_elecom_wmc-m1267gst2.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_elecom_wrc-gs-1pci.dtsi"
+
+/ {
+	compatible = "elecom,wmc-m1267gst2", "mediatek,mt7621-soc";
+	model = "ELECOM WMC-M1267GST2";
+};
+
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_fff4>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+	nvmem-cells = <&macaddr_factory_fffa>;
+	nvmem-cell-names = "mac-address";
+};
+
+&partitions {
+	partition@50000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x50000 0x1800000>;
+	};
+
+	partition@1850000 {
+		label = "tm_pattern";
+		reg = <0x1850000 0x400000>;
+		read-only;
+	};
+
+	partition@1c50000 {
+		label = "tm_key";
+		reg = <0x1c50000 0x100000>;
+		read-only;
+	};
+
+	partition@1d50000 {
+		label = "nvram";
+		reg = <0x1d50000 0xb0000>;
+		read-only;
+	};
+
+	partition@1e00000 {
+		label = "user_data";
+		reg = <0x1e00000 0x200000>;
+		read-only;
+	};
+};
+
+&wifi {
+	nvmem-cells = <&macaddr_factory_4 (-1)>;
+	nvmem-cell-names = "mac-address";
+};
+
+&factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		macaddr_factory_4: macaddr@4 {
+			compatible = "mac-base";
+			reg = <0x4 0x6>;
+			#nvmem-cell-cells = <1>;
+		};
+
+		macaddr_factory_fff4: macaddr@fff4 {
+			reg = <0xfff4 0x6>;
+		};
+
+		macaddr_factory_fffa: macaddr@fffa {
+			reg = <0xfffa 0x6>;
+		};
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts b/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts
new file mode 100644
index 0000000000..942fa1cb46
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_elecom_wmc-s1267gs2.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_elecom_wrc-gs-1pci.dtsi"
+
+/ {
+	compatible = "elecom,wmc-s1267gs2", "mediatek,mt7621-soc";
+	model = "ELECOM WMC-S1267GS2";
+
+	aliases {
+		/*
+		 * A MAC address printed to the label is an address of
+		 * 5 GHz band on stock firmware, but there is no
+		 * per-band MAC address support on Linux Kernel and that
+		 * address is not assigned to any wlan devices now.
+		 */
+		/delete-property/ label-mac-device;
+	};
+};
+
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_fff4>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+	status = "disabled";
+};
+
+&partitions {
+	partition@50000 {
+		compatible = "denx,uimage";
+		label = "firmware";
+		reg = <0x50000 0x1800000>;
+	};
+
+	partition@1850000 {
+		label = "tm_pattern";
+		reg = <0x1850000 0x400000>;
+		read-only;
+	};
+
+	partition@1c50000 {
+		label = "tm_key";
+		reg = <0x1c50000 0x100000>;
+		read-only;
+	};
+
+	partition@1d50000 {
+		label = "nvram";
+		reg = <0x1d50000 0xb0000>;
+		read-only;
+	};
+
+	partition@1e00000 {
+		label = "user_data";
+		reg = <0x1e00000 0x200000>;
+		read-only;
+	};
+};
+
+&wifi {
+	nvmem-cells = <&macaddr_factory_4 (-1)>;
+	nvmem-cell-names = "mac-address";
+};
+
+&factory {
+	nvmem-layout {
+		compatible = "fixed-layout";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		macaddr_factory_4: macaddr@4 {
+			compatible = "mac-base";
+			reg = <0x4 0x6>;
+			#nvmem-cell-cells = <1>;
+		};
+
+		macaddr_factory_fff4: macaddr@fff4 {
+			reg = <0xfff4 0x6>;
+		};
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
index bbc135ad83..503ec40b50 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts
@@ -85,10 +85,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
index 418b0cfa9a..cdb94dcdc1 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi
@@ -124,10 +124,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
index dae247f4ce..4b61b9faf2 100644
--- a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi
@@ -94,10 +94,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts b/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts
new file mode 100644
index 0000000000..c0bb5e4969
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_elecom_wrc-x1800gs.dts
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "elecom,wrc-x1800gs", "mediatek,mt7621-soc";
+	model = "ELECOM WRC-X1800GS";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_green;
+		label-mac-device = &gmac0;
+	};
+
+	chosen {
+		bootargs-override = "console=ttyS0,115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/* available on 1st HW rev. */
+		led-0 {
+			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+			function-enumerator = <1>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led_power_green: led-1 {
+			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+		};
+
+		led_power_red: led-2 {
+			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+		};
+
+		led-3 {
+			gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+		};
+
+		led-4 {
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_WPS;
+		};
+
+		led-5 {
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_5GHZ;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		/* available on 2nd HW rev. */
+		led-6 {
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WLAN_2GHZ;
+			function-enumerator = <2>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led-7 {
+			gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_WLAN_5GHZ;
+		};
+
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		switch-ap {
+			label = "ap";
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+		};
+
+		switch-router {
+			label = "router";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_1>;
+		};
+
+		button-wps {
+			label = "wps";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+	pinctrl-0 = <&nand_pins>;
+	pinctrl-names = "default";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			reg = <0x0 0x100000>;
+			label = "u-boot";
+			read-only;
+		};
+
+		partition@100000 {
+			reg = <0x100000 0x100000>;
+			label = "u-boot-env";
+		};
+
+		partition@200000 {
+			reg = <0x200000 0x1c0000>;
+			label = "factory";
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				eeprom_factory_0: eeprom@0 {
+					reg = <0x0 0xe00>;
+				};
+
+				precal_factory_e10: precal@e10 {
+					reg = <0xe10 0x19c10>;
+				};
+
+				macaddr_factory_1fdf4: macaddr@1fdf4 {
+					reg = <0x1fdf4 0x6>;
+				};
+
+				macaddr_factory_1fdfa: macaddr@1fdfa {
+					reg = <0x1fdfa 0x6>;
+				};
+			};
+		};
+
+		/* "RAS1" on stock fw */
+		partition@3c0000 {
+			compatible = "fixed-partitions";
+			reg = <0x3c0000 0x3240000>;
+			label = "firmware";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0x800000>;
+				label = "kernel";
+			};
+
+			partition@800000 {
+				reg = <0x800000 0x2a40000>;
+				label = "ubi";
+			};
+		};
+
+		partition@3600000 {
+			reg = <0x3600000 0x100000>;
+			label = "Config";
+			read-only;
+		};
+
+		/* "RAS2" on stock fw */
+		partition@3700000 {
+			reg = <0x3700000 0x3240000>;
+			label = "firmware2";
+		};
+
+		partition@6940000 {
+			reg = <0x6940000 0x100000>;
+			label = "Config_2";
+			read-only;
+		};
+
+		partition@6a40000 {
+			reg = <0x6a40000 0x100000>;
+			label = "persist";
+		};
+
+		partition@6b40000 {
+			reg = <0x6b40000 0x100000>;
+			label = "mesh";
+			read-only;
+		};
+
+		partition@6c40000 {
+			reg = <0x6c40000 0x1340000>;
+			label = "backup";
+			read-only;
+		};
+	};
+};
+
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_1fdfa>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+	status = "okay";
+	label = "wan";
+	phy-handle = <&ethphy0>;
+
+	nvmem-cells = <&macaddr_factory_1fdf4>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ethphy0 {
+	/delete-property/ interrupts;
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie1 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_0>, <&precal_factory_e10>;
+		nvmem-cell-names = "eeprom", "precal";
+		mediatek,disable-radar-background;
+	};
+};
+
+&pcie2 {
+	status = "disabled";
+};
+
+&switch0 {
+	ports {
+		port@1 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan1";
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "uart3", "jtag", "wdt";
+		function = "gpio";
+	};
+};
+
+&uartlite {
+	pinctrl-0 = <&uart1_pins>;
+	pinctrl-names = "default";
+};
diff --git a/target/linux/ramips/dts/mt7621_etisalat_s3.dts b/target/linux/ramips/dts/mt7621_etisalat_s3.dts
index 2fb3aedaff..60452a63f4 100644
--- a/target/linux/ramips/dts/mt7621_etisalat_s3.dts
+++ b/target/linux/ramips/dts/mt7621_etisalat_s3.dts
@@ -209,10 +209,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
index 9030c051f1..a017baa1ba 100644
--- a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
+++ b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts
@@ -144,10 +144,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
index 849074111b..e4b254ebce 100644
--- a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
+++ b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
@@ -145,10 +145,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
index 7ef7201faf..2710aa6f3e 100644
--- a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
+++ b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts
@@ -116,10 +116,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
index 88148c6759..1520aaf5b1 100644
--- a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
+++ b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi
@@ -58,10 +58,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &nand {
diff --git a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
index 53c5912397..dd7b72707e 100644
--- a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
+++ b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi
@@ -73,10 +73,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &nand {
diff --git a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
index cae9f717b1..195a12b7d1 100644
--- a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
+++ b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts
@@ -77,10 +77,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
index 1bf6640137..5a8f32d723 100644
--- a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
+++ b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts
@@ -153,10 +153,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
index a7610070de..e764139451 100644
--- a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
+++ b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts
@@ -169,10 +169,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_humax_e10.dts b/target/linux/ramips/dts/mt7621_humax_e10.dts
index dfa91ad43a..39eac32d53 100644
--- a/target/linux/ramips/dts/mt7621_humax_e10.dts
+++ b/target/linux/ramips/dts/mt7621_humax_e10.dts
@@ -169,10 +169,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
index 4f84302417..9e64077e0c 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts
@@ -174,10 +174,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
index 4543f45a9f..86d8a93da6 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts
@@ -186,10 +186,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
index 9de7297405..bcb7e57678 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts
@@ -170,10 +170,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
index b055afc3ad..519c52065b 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts
@@ -160,10 +160,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
index b3063a333e..07187d8bfe 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
+++ b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi
@@ -161,10 +161,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
index 790668cc41..e322e4efdb 100644
--- a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
+++ b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts
@@ -153,10 +153,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
index e8c7f12d01..bfb6207199 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts
@@ -130,10 +130,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
index 6990d31e39..7c46635fb5 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts
@@ -134,10 +134,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
index a96e89b3f3..7b2465c14f 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts
@@ -135,10 +135,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
index 848891056a..6bfdffefb7 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
+++ b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi
@@ -152,10 +152,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
index 249904da6a..7f28d7af3f 100644
--- a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts
@@ -138,10 +138,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
index 88067a4fa5..8263c062dd 100644
--- a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts
@@ -148,10 +148,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_iptime_t5004.dts b/target/linux/ramips/dts/mt7621_iptime_t5004.dts
index f7a5e8ca17..4a7f9aaaa1 100644
--- a/target/linux/ramips/dts/mt7621_iptime_t5004.dts
+++ b/target/linux/ramips/dts/mt7621_iptime_t5004.dts
@@ -91,10 +91,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
index 05980caa6f..548ab7ba59 100644
--- a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts
@@ -168,10 +168,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_jcg_q20.dts b/target/linux/ramips/dts/mt7621_jcg_q20.dts
index 49f51ded7f..a8892ac8b1 100644
--- a/target/linux/ramips/dts/mt7621_jcg_q20.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_q20.dts
@@ -180,10 +180,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_jcg_y2.dts b/target/linux/ramips/dts/mt7621_jcg_y2.dts
index 54141cc2a2..5012bc3d62 100644
--- a/target/linux/ramips/dts/mt7621_jcg_y2.dts
+++ b/target/linux/ramips/dts/mt7621_jcg_y2.dts
@@ -121,10 +121,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts b/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts
new file mode 100644
index 0000000000..8512ff96b0
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621_jdcloud_re-cp-02.dts
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "jdcloud,re-cp-02", "mediatek,mt7621-soc";
+	model = "JDCloud RE-CP-02";
+
+	aliases {
+		label-mac-device = &gmac0;
+		led-boot = &led_status_blue;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_green;
+		led-upgrade = &led_status_blue;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_red: led-0 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_blue: led-1 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		led_status_green: led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			label = "wps";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				compatible = "u-boot,env";
+				label = "Config";
+				reg = <0x40000 0x10000>;
+			};
+
+			partition@50000 {
+				label = "Factory";
+				reg = <0x50000 0x40000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0xe00>;
+					};
+
+					macaddr_factory_3fff4: macaddr@3fff4 {
+						reg = <0x3fff4 0x6>;
+					};
+
+					macaddr_factory_3fffa: macaddr@3fffa {
+						reg = <0x3fffa 0x6>;
+					};
+				};
+			};
+
+			partition@90000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x90000 0xf70000>;
+			};
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "uart3", "jtag", "wdt";
+		function = "gpio";
+	};
+};
+
+&sdhci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie1 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_0>;
+		nvmem-cell-names = "eeprom";
+		mediatek,disable-radar-background;
+	};
+};
+
+&gmac0 {
+	nvmem-cells = <&macaddr_factory_3fff4>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+	status = "okay";
+	label = "wan";
+	phy-handle = <&ethphy4>;
+
+	nvmem-cells = <&macaddr_factory_3fffa>;
+	nvmem-cell-names = "mac-address";
+};
+
+&ethphy4 {
+	/delete-property/ interrupts;
+};
+
+&switch0 {
+	ports {
+		port@1 {
+			status = "okay";
+			label = "lan1";
+		};
+
+		port@2 {
+			status = "okay";
+			label = "lan2";
+		};
+
+		port@3 {
+			status = "okay";
+			label = "lan3";
+		};
+	};
+};
+
+&xhci {
+	status = "disabled";
+};
diff --git a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
index 35d09832f2..6ee20c29c5 100644
--- a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
+++ b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts
@@ -201,10 +201,8 @@
 	};
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &gmac0 {
diff --git a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
index 0323769990..3b6026f377 100644
--- a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
+++ b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts
@@ -179,10 +179,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_linksys_e5600.dts b/target/linux/ramips/dts/mt7621_linksys_e5600.dts
index a059fd0698..08fcbbc515 100644
--- a/target/linux/ramips/dts/mt7621_linksys_e5600.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_e5600.dts
@@ -175,10 +175,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_linksys_e7350.dts b/target/linux/ramips/dts/mt7621_linksys_e7350.dts
index 77c123720f..db7387ddec 100644
--- a/target/linux/ramips/dts/mt7621_linksys_e7350.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_e7350.dts
@@ -156,10 +156,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts b/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts
index 35a90ea070..83c86ee11d 100644
--- a/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts
@@ -16,14 +16,12 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethernet-phy@0 {
-		status = "disabled";
-	};
+&ethphy0 {
+	interrupts = <0>;
+};
 
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
index 5804f21591..70cf425b2c 100644
--- a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
+++ b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi
@@ -203,10 +203,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_linksys_re6500.dts b/target/linux/ramips/dts/mt7621_linksys_re6500.dts
index d269899980..3c026a41a5 100644
--- a/target/linux/ramips/dts/mt7621_linksys_re6500.dts
+++ b/target/linux/ramips/dts/mt7621_linksys_re6500.dts
@@ -148,10 +148,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
index aaa75b0573..c6fa3622ef 100644
--- a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
+++ b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts
@@ -138,10 +138,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts b/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts
index 2da7f983a9..ecce30330b 100644
--- a/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts
+++ b/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts
@@ -45,10 +45,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_meig_slt866.dts b/target/linux/ramips/dts/mt7621_meig_slt866.dts
index d364a91794..d4e040649e 100644
--- a/target/linux/ramips/dts/mt7621_meig_slt866.dts
+++ b/target/linux/ramips/dts/mt7621_meig_slt866.dts
@@ -185,11 +185,6 @@
 	};
 };
 
-&ethernet {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mdio_pins>;
-};
-
 &gmac0 {
 	nvmem-cells = <&macaddr_custom_40 0>;
 	nvmem-cell-names = "mac-address";
@@ -204,10 +199,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
index fb14bd7829..145b0eeb40 100644
--- a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
+++ b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
@@ -145,10 +145,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts
index aad8a6776d..faa4e53f09 100644
--- a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts
+++ b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts
@@ -42,10 +42,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts
index 223d03b9fd..11171d9535 100644
--- a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts
+++ b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts
@@ -96,10 +96,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
index 6e225c0825..f8dc6ebdbf 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi
@@ -118,10 +118,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
index 61c3ec3761..c125bcc4e3 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi
@@ -184,10 +184,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
index 13ce338588..273bb9469c 100644
--- a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
+++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi
@@ -115,10 +115,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netgear_wac104.dts b/target/linux/ramips/dts/mt7621_netgear_wac104.dts
index 9c706530d4..01583e8887 100644
--- a/target/linux/ramips/dts/mt7621_netgear_wac104.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_wac104.dts
@@ -170,10 +170,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netgear_wax202.dts b/target/linux/ramips/dts/mt7621_netgear_wax202.dts
index bf580de6b8..226c461543 100644
--- a/target/linux/ramips/dts/mt7621_netgear_wax202.dts
+++ b/target/linux/ramips/dts/mt7621_netgear_wax202.dts
@@ -244,10 +244,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_netis_wf2881.dts b/target/linux/ramips/dts/mt7621_netis_wf2881.dts
index 58d2c70655..0baf9d6483 100644
--- a/target/linux/ramips/dts/mt7621_netis_wf2881.dts
+++ b/target/linux/ramips/dts/mt7621_netis_wf2881.dts
@@ -162,10 +162,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
index 7b33efd6e6..b9bccf0f28 100644
--- a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
+++ b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts
@@ -156,10 +156,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
index 6a733698d2..92c76d4206 100644
--- a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
+++ b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts
@@ -146,10 +146,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_planex_vr500.dts b/target/linux/ramips/dts/mt7621_planex_vr500.dts
index 4d281670ef..df12331e24 100644
--- a/target/linux/ramips/dts/mt7621_planex_vr500.dts
+++ b/target/linux/ramips/dts/mt7621_planex_vr500.dts
@@ -104,10 +104,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
index 98a2ffad5f..f4d893a366 100644
--- a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
+++ b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts
@@ -163,10 +163,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
index b3aaffeafe..b567b14f8e 100644
--- a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
+++ b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts
@@ -140,10 +140,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts b/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts
index 8afe5f5485..1c2cb42fa0 100644
--- a/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts
+++ b/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts
@@ -228,10 +228,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
index 5afed4c695..2eeb932752 100644
--- a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
+++ b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts
@@ -129,6 +129,7 @@
 		reg = <0x0000 0 0 0 0>;
 		nvmem-cells = <&eeprom_factory_0>;
 		nvmem-cell-names = "eeprom";
+		ieee80211-freq-limit = <2400000 2500000>;
 	};
 };
 
@@ -146,10 +147,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
index fd952cbc93..b13b621d2f 100644
--- a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
+++ b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi
@@ -208,10 +208,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
index 6ea2c199e3..b287056bf1 100644
--- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
+++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts
@@ -90,10 +90,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &pcie {
diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
index 3b474819e1..cd0e7465ff 100644
--- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
+++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts
@@ -112,10 +112,8 @@
 	status = "okay";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &gmac0 {
diff --git a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
index 3448db5f03..4497531aee 100644
--- a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
+++ b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts
@@ -154,10 +154,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
index d1310ad954..42e39c3152 100644
--- a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
+++ b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts
@@ -125,10 +125,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
index 8c0062973d..e4937c55c5 100644
--- a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
+++ b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts
@@ -135,10 +135,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
index 24606904e1..e2d706c5db 100644
--- a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
+++ b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts
@@ -130,10 +130,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
index 71ef4bc6b6..ac03545eca 100644
--- a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
@@ -181,10 +181,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
index e9879128a3..b1a3e3e1bc 100644
--- a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts
@@ -206,10 +206,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
index d814cba261..bc56b82cd1 100644
--- a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts
@@ -189,10 +189,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
index 2aea6bbbc0..2694b3890f 100644
--- a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
@@ -182,10 +182,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
index 6203308515..02560669d5 100644
--- a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts
@@ -283,10 +283,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
index 33070ef6ca..b71b7ad914 100644
--- a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts
@@ -155,11 +155,8 @@
 	};
 };
 
-
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &state_default {
diff --git a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
index c501727ca8..d6f9a368e4 100644
--- a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
@@ -219,10 +219,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
index db460b43b2..234202ba87 100644
--- a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
+++ b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts
@@ -198,13 +198,10 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
-
 &switch0 {
 	ports {
 		port@1 {
diff --git a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts
index 4665f04f02..80467c88e9 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts
@@ -14,10 +14,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
index 0d6d500222..f2fb48cac2 100644
--- a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
+++ b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts
@@ -73,10 +73,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
index b193aed103..77c06545e8 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi
@@ -64,10 +64,8 @@
 	phy-handle = <&ethphy0>;
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
index 42f6cea2d3..79deb7559d 100644
--- a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
+++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi
@@ -81,10 +81,8 @@
 	phy-handle = <&ethphy4>;
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
index 05d8e4a5ae..7080dad145 100644
--- a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
+++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts
@@ -47,12 +47,6 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-};
-
 &pcie {
 	status = "okay";
 };
@@ -119,17 +113,6 @@
 	};
 };
 
-&gmac0 {
-	nvmem-cells = <&macaddr_factory_3fff4>;
-	nvmem-cell-names = "mac-address";
-};
-
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
-};
-
 &switch0 {
 	ports {
 		port@3 {
diff --git a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
index f9e37bee6e..78bc0ba4b0 100644
--- a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
+++ b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts
@@ -166,10 +166,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
index f0c7646b26..96054135ae 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts
@@ -224,10 +224,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
index 1dfded14b1..3b377fca7c 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts
@@ -85,10 +85,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
index 61359e8b21..2d2bf3d699 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi
@@ -47,10 +47,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
index ef637278af..598fafe871 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi
@@ -173,10 +173,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi
index 468f9456bf..e0950e7c64 100644
--- a/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi
+++ b/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi
@@ -45,10 +45,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
index f1227552e8..e04afc81ba 100644
--- a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
+++ b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts
@@ -111,10 +111,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
index c47e34a5d6..6475c142e7 100644
--- a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
+++ b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts
@@ -165,10 +165,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
index 9f4e8cf1ce..9d2491f634 100644
--- a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
+++ b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts
@@ -175,10 +175,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
index 0cdad1bfe5..316c180098 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts
@@ -174,10 +174,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
index 2cc3435a89..536b45e03f 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts
@@ -189,13 +189,10 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
-
 &switch0 {
 	gpio-controller;
 	#gpio-cells = <2>;
diff --git a/target/linux/ramips/dts/mt7621_yuncore_g720.dts b/target/linux/ramips/dts/mt7621_yuncore_g720.dts
index 4b88064b49..2170bc83ec 100644
--- a/target/linux/ramips/dts/mt7621_yuncore_g720.dts
+++ b/target/linux/ramips/dts/mt7621_yuncore_g720.dts
@@ -137,10 +137,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts b/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts
index 34b151be75..3acc1529e5 100644
--- a/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts
+++ b/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts
@@ -93,10 +93,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &nand {
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
index e15c676c8a..7dfe9a7699 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts
@@ -109,10 +109,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
index dfa49a2bc5..31a4e4482a 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts
@@ -133,10 +133,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
index bbf121036c..c3712fea7b 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi
@@ -187,10 +187,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
index b0182ee896..dcad7b26d2 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi
@@ -186,10 +186,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
index 321274bb15..fc8a91e398 100644
--- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
+++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi
@@ -156,10 +156,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy4: ethernet-phy@4 {
-		reg = <4>;
-	};
+&ethphy4 {
+	/delete-property/ interrupts;
 };
 
 &switch0 {
diff --git a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
index b82a8669b3..6bf65a0218 100644
--- a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
+++ b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts
@@ -193,10 +193,8 @@
 	nvmem-cell-names = "mac-address";
 };
 
-&mdio {
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
+&ethphy0 {
+	/delete-property/ interrupts;
 };
 
 &pcie {
diff --git a/target/linux/ramips/dts/mt7628an_cudy_tr1200-v1.dts b/target/linux/ramips/dts/mt7628an_cudy_tr1200-v1.dts
new file mode 100644
index 0000000000..d087530782
--- /dev/null
+++ b/target/linux/ramips/dts/mt7628an_cudy_tr1200-v1.dts
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7628an.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "cudy,tr1200", "mediatek,mt7628an-soc";
+	model = "Cudy TR1200";
+
+	aliases {
+		led-boot = &led_status;
+		led-running = &led_status;
+		led-failsafe = &led_status;
+		led-upgrade = &led_status;
+		label-mac-device = &ethernet;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		mode {
+			label = "mode";
+			linux,input-type = <EV_SW>;
+			linux,code = <BTN_0>;
+			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: led_0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+		};
+
+		led_1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_export {
+		compatible = "gpio-export";
+
+		usb {
+			gpio-export,name = "usb";
+			gpio-export,output = <1>;
+			gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x30000>;
+				read-only;
+			};
+
+			partition@30000 {
+				label = "u-boot-env";
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "factory";
+				reg = <0x40000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x400>;
+					};
+
+					eeprom_factory_8000: eeprom@8000 {
+						reg = <0x8000 0x4da8>;
+					};
+				};
+			};
+
+			partition@50000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x50000 0xf80000>;
+			};
+
+			partition@fd0000 {
+				label = "debug";
+				reg = <0xfd0000 0x10000>;
+				read-only;
+			};
+
+			partition@fe0000 {
+				label = "backup";
+				reg = <0xfe000 0x10000>;
+				read-only;
+			};
+
+			partition@ff0000 {
+				label = "bdinfo";
+				reg = <0xff0000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_bdinfo_de00: macaddr@de00 {
+						compatible = "mac-base";
+						reg = <0xde00 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "gpio", "wdt", "p0led_an", "wled_an";
+		function = "gpio";
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	wifi@0,0 {
+		compatible = "mediatek,mt76";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_bdinfo_de00 2>;
+		nvmem-cell-names = "eeprom", "mac-address";
+		ieee80211-freq-limit = <5000000 6000000>;
+	};
+};
+
+&wmac {
+	status = "okay";
+
+	nvmem-cells = <&eeprom_factory_0>, <&macaddr_bdinfo_de00 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
+};
+
+&ethernet {
+	nvmem-cells = <&macaddr_bdinfo_de00 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&esw {
+	mediatek,portmap = <0x3d>;
+	mediatek,portdisable = <0x3c>;
+};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts
new file mode 100644
index 0000000000..177cd4db8a
--- /dev/null
+++ b/target/linux/ramips/dts/mt7628an_tplink_archer-mr200-v5.dts
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7628an.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "tplink,archer-mr200-v5", "mediatek,mt7628an-soc";
+	model = "TP-Link Archer MR200 v5";
+
+	aliases {
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+		label-mac-device = &ethernet;
+	};
+	
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		lan {
+			function = LED_FUNCTION_LAN;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		wan {
+			function = LED_FUNCTION_WAN;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power: power {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
+		};
+
+		signal1 {
+			label = "white:signal1";
+			gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+		};
+
+		signal2 {
+			label = "white:signal2";
+			gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+		};
+
+		signal3 {
+			label = "white:signal3";
+			gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
+		};
+
+		wlan {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_WHITE>;
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+
+		rfkill {
+			label = "rfkill";
+			gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RFKILL>;
+		};
+	};	
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <104000000>;
+		m25p,fast-read;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x20000>;
+				read-only;
+			};
+
+			partition@20000 {
+				compatible = "tplink,firmware";
+				label = "firmware";
+				reg = <0x20000 0x7b0000>;
+			};
+
+			partition@7d0000 {
+				label = "config";
+				reg = <0x7d0000 0x10000>;
+				read-only;
+			};
+
+			partition@7e0000 {
+				label = "romfile";
+				reg = <0x7e0000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_romfile_f100: macaddr@f100 {
+						compatible = "mac-base";
+						reg = <0xf100 0x6>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+
+			partition@7f0000 {
+				label = "radio";
+				reg = <0x7f0000 0x10000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_radio_0: eeprom@0 {
+						reg = <0x0 0x400>;
+					};
+
+					eeprom_radio_8000: eeprom@8000 {
+						reg = <0x8000 0x200>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&state_default {
+	gpio {
+		groups = "i2c", "p0led_an", "p1led_an", "p2led_an", "p3led_an", "p4led_an", "uart1", "wdt";
+		function = "gpio";
+	};
+};
+
+&wmac {
+	nvmem-cells = <&eeprom_radio_0>, <&macaddr_romfile_f100 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
+	status = "okay";
+};
+
+&esw {
+	mediatek,portdisable = <0x30>;
+};
+
+&ethernet {
+	nvmem-cells = <&macaddr_romfile_f100 0>;
+	nvmem-cell-names = "mac-address";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&pcie0 {
+	mt76@0,0 {
+		reg = <0x0000 0 0 0 0>;
+		ieee80211-freq-limit = <5000000 6000000>;
+		nvmem-cells = <&eeprom_radio_8000>, <&macaddr_romfile_f100 (-1)>;
+		nvmem-cell-names = "eeprom", "mac-address";
+	};
+};
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
index 21d1e48336..67cc54650f 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts
@@ -89,12 +89,14 @@
 };
 
 &wmac {
-	nvmem-cells = <&macaddr_factory_1f100>;
-	nvmem-cell-names = "mac-address";
+	status = "okay";
+
+	nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
 
 &ethernet {
-	nvmem-cells = <&macaddr_factory_1f100>;
+	nvmem-cells = <&macaddr_factory_1f100 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -105,7 +107,9 @@
 		#size-cells = <1>;
 
 		macaddr_factory_1f100: macaddr@1f100 {
+			compatible = "mac-base";
 			reg = <0x1f100 0x6>;
+			#nvmem-cell-cells = <1>;
 		};
 	};
 };
diff --git a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
index 1bd35fc334..609452dfe1 100644
--- a/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
+++ b/target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts
@@ -89,12 +89,14 @@
 };
 
 &wmac {
-	nvmem-cells = <&macaddr_factory_1f100>;
-	nvmem-cell-names = "mac-address";
+	status = "okay";
+
+	nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+	nvmem-cell-names = "eeprom", "mac-address";
 };
 
 &ethernet {
-	nvmem-cells = <&macaddr_factory_1f100>;
+	nvmem-cells = <&macaddr_factory_1f100 0>;
 	nvmem-cell-names = "mac-address";
 };
 
@@ -105,7 +107,9 @@
 		#size-cells = <1>;
 
 		macaddr_factory_1f100: macaddr@1f100 {
+			compatible = "mac-base";
 			reg = <0x1f100 0x6>;
+			#nvmem-cell-cells = <1>;
 		};
 	};
 };
diff --git a/target/linux/ramips/files/drivers/dma/ralink-gdma.c b/target/linux/ramips/files/drivers/dma/ralink-gdma.c
new file mode 100644
index 0000000000..e510a05ebb
--- /dev/null
+++ b/target/linux/ramips/files/drivers/dma/ralink-gdma.c
@@ -0,0 +1,915 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  GDMA4740 DMAC support
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/of_dma.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+
+#include "virt-dma.h"
+
+#define GDMA_REG_SRC_ADDR(x)		(0x00 + (x) * 0x10)
+#define GDMA_REG_DST_ADDR(x)		(0x04 + (x) * 0x10)
+
+#define GDMA_REG_CTRL0(x)		(0x08 + (x) * 0x10)
+#define GDMA_REG_CTRL0_TX_MASK		0xffff
+#define GDMA_REG_CTRL0_TX_SHIFT		16
+#define GDMA_REG_CTRL0_CURR_MASK	0xff
+#define GDMA_REG_CTRL0_CURR_SHIFT	8
+#define	GDMA_REG_CTRL0_SRC_ADDR_FIXED	BIT(7)
+#define GDMA_REG_CTRL0_DST_ADDR_FIXED	BIT(6)
+#define GDMA_REG_CTRL0_BURST_MASK	0x7
+#define GDMA_REG_CTRL0_BURST_SHIFT	3
+#define	GDMA_REG_CTRL0_DONE_INT		BIT(2)
+#define	GDMA_REG_CTRL0_ENABLE		BIT(1)
+#define GDMA_REG_CTRL0_SW_MODE          BIT(0)
+
+#define GDMA_REG_CTRL1(x)		(0x0c + (x) * 0x10)
+#define GDMA_REG_CTRL1_SEG_MASK		0xf
+#define GDMA_REG_CTRL1_SEG_SHIFT	22
+#define GDMA_REG_CTRL1_REQ_MASK		0x3f
+#define GDMA_REG_CTRL1_SRC_REQ_SHIFT	16
+#define GDMA_REG_CTRL1_DST_REQ_SHIFT	8
+#define GDMA_REG_CTRL1_NEXT_MASK	0x1f
+#define GDMA_REG_CTRL1_NEXT_SHIFT	3
+#define GDMA_REG_CTRL1_COHERENT		BIT(2)
+#define GDMA_REG_CTRL1_FAIL		BIT(1)
+#define GDMA_REG_CTRL1_MASK		BIT(0)
+
+#define GDMA_REG_UNMASK_INT		0x200
+#define GDMA_REG_DONE_INT		0x204
+
+#define GDMA_REG_GCT			0x220
+#define GDMA_REG_GCT_CHAN_MASK		0x3
+#define GDMA_REG_GCT_CHAN_SHIFT		3
+#define GDMA_REG_GCT_VER_MASK		0x3
+#define GDMA_REG_GCT_VER_SHIFT		1
+#define GDMA_REG_GCT_ARBIT_RR		BIT(0)
+
+#define GDMA_REG_REQSTS			0x2a0
+#define GDMA_REG_ACKSTS			0x2a4
+#define GDMA_REG_FINSTS			0x2a8
+
+/* for RT305X gdma registers */
+#define GDMA_RT305X_CTRL0_REQ_MASK	0xf
+#define GDMA_RT305X_CTRL0_SRC_REQ_SHIFT	12
+#define GDMA_RT305X_CTRL0_DST_REQ_SHIFT	8
+
+#define GDMA_RT305X_CTRL1_FAIL		BIT(4)
+#define GDMA_RT305X_CTRL1_NEXT_MASK	0x7
+#define GDMA_RT305X_CTRL1_NEXT_SHIFT	1
+
+#define GDMA_RT305X_STATUS_INT		0x80
+#define GDMA_RT305X_STATUS_SIGNAL	0x84
+#define GDMA_RT305X_GCT			0x88
+
+/* for MT7621 gdma registers */
+#define GDMA_REG_PERF_START(x)		(0x230 + (x) * 0x8)
+#define GDMA_REG_PERF_END(x)		(0x234 + (x) * 0x8)
+
+enum gdma_dma_transfer_size {
+	GDMA_TRANSFER_SIZE_4BYTE	= 0,
+	GDMA_TRANSFER_SIZE_8BYTE	= 1,
+	GDMA_TRANSFER_SIZE_16BYTE	= 2,
+	GDMA_TRANSFER_SIZE_32BYTE	= 3,
+	GDMA_TRANSFER_SIZE_64BYTE	= 4,
+};
+
+struct gdma_dma_sg {
+	dma_addr_t src_addr;
+	dma_addr_t dst_addr;
+	u32 len;
+};
+
+struct gdma_dma_desc {
+	struct virt_dma_desc vdesc;
+
+	enum dma_transfer_direction direction;
+	bool cyclic;
+
+	u32 residue;
+	unsigned int num_sgs;
+	struct gdma_dma_sg sg[];
+};
+
+struct gdma_dmaengine_chan {
+	struct virt_dma_chan vchan;
+	unsigned int id;
+	unsigned int slave_id;
+
+	dma_addr_t fifo_addr;
+	enum gdma_dma_transfer_size burst_size;
+
+	struct gdma_dma_desc *desc;
+	unsigned int next_sg;
+};
+
+struct gdma_dma_dev {
+	struct dma_device ddev;
+	struct device_dma_parameters dma_parms;
+	struct gdma_data *data;
+	void __iomem *base;
+	struct tasklet_struct task;
+	volatile unsigned long chan_issued;
+	atomic_t cnt;
+
+	struct gdma_dmaengine_chan chan[];
+};
+
+struct gdma_data {
+	int chancnt;
+	u32 done_int_reg;
+	void (*init)(struct gdma_dma_dev *dma_dev);
+	int (*start_transfer)(struct gdma_dmaengine_chan *chan);
+};
+
+static struct gdma_dma_dev *gdma_dma_chan_get_dev(
+	struct gdma_dmaengine_chan *chan)
+{
+	return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
+		ddev);
+}
+
+static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
+}
+
+static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
+{
+	return container_of(vdesc, struct gdma_dma_desc, vdesc);
+}
+
+static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
+				     unsigned int reg)
+{
+	return readl(dma_dev->base + reg);
+}
+
+static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
+				  unsigned int reg, uint32_t val)
+{
+	writel(val, dma_dev->base + reg);
+}
+
+static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
+{
+	if (maxburst < 2)
+		return GDMA_TRANSFER_SIZE_4BYTE;
+	else if (maxburst < 4)
+		return GDMA_TRANSFER_SIZE_8BYTE;
+	else if (maxburst < 8)
+		return GDMA_TRANSFER_SIZE_16BYTE;
+	else if (maxburst < 16)
+		return GDMA_TRANSFER_SIZE_32BYTE;
+	else
+		return GDMA_TRANSFER_SIZE_64BYTE;
+}
+
+static int gdma_dma_config(struct dma_chan *c,
+			   struct dma_slave_config *config)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+
+	if (config->device_fc) {
+		dev_err(dma_dev->ddev.dev, "not support flow controller\n");
+		return -EINVAL;
+	}
+
+	switch (config->direction) {
+	case DMA_MEM_TO_DEV:
+		if (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
+			dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
+			return -EINVAL;
+		}
+		chan->fifo_addr = config->dst_addr;
+		chan->burst_size = gdma_dma_maxburst(config->dst_maxburst);
+		break;
+	case DMA_DEV_TO_MEM:
+		if (config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
+			dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
+			return -EINVAL;
+		}
+		chan->fifo_addr = config->src_addr;
+		chan->burst_size = gdma_dma_maxburst(config->src_maxburst);
+		break;
+	default:
+		dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+			config->direction);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int gdma_dma_terminate_all(struct dma_chan *c)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+	unsigned long flags, timeout;
+	LIST_HEAD(head);
+	int i = 0;
+
+	spin_lock_irqsave(&chan->vchan.lock, flags);
+	chan->desc = NULL;
+	clear_bit(chan->id, &dma_dev->chan_issued);
+	vchan_get_all_descriptors(&chan->vchan, &head);
+	spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&chan->vchan, &head);
+
+	/* wait dma transfer complete */
+	timeout = jiffies + msecs_to_jiffies(5000);
+	while (gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)) &
+			GDMA_REG_CTRL0_ENABLE) {
+		if (time_after_eq(jiffies, timeout)) {
+			dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n",
+				chan->id);
+			/* restore to init value */
+			gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0);
+			break;
+		}
+		cpu_relax();
+		i++;
+	}
+
+	if (i)
+		dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n",
+			chan->id, i);
+
+	return 0;
+}
+
+static void rt305x_dump_reg(struct gdma_dma_dev *dma_dev, int id)
+{
+	dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, intr %08x, signal %08x\n",
+		id,
+		gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
+		gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_INT),
+		gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_SIGNAL));
+}
+
+static int rt305x_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
+{
+	struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+	dma_addr_t src_addr, dst_addr;
+	struct gdma_dma_sg *sg;
+	u32 ctrl0, ctrl1;
+
+	/* verify chan is already stopped */
+	ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
+	if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
+		dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
+			chan->id, ctrl0);
+		rt305x_dump_reg(dma_dev, chan->id);
+		return -EINVAL;
+	}
+
+	sg = &chan->desc->sg[chan->next_sg];
+	if (chan->desc->direction == DMA_MEM_TO_DEV) {
+		src_addr = sg->src_addr;
+		dst_addr = chan->fifo_addr;
+		ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED |
+			(8 << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
+			(chan->slave_id << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
+	} else if (chan->desc->direction == DMA_DEV_TO_MEM) {
+		src_addr = chan->fifo_addr;
+		dst_addr = sg->dst_addr;
+		ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED |
+			(chan->slave_id << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
+			(8 << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
+	} else if (chan->desc->direction == DMA_MEM_TO_MEM) {
+		/*
+		 * TODO: memcpy function have bugs. sometime it will copy
+		 * more 8 bytes data when using dmatest verify.
+		 */
+		src_addr = sg->src_addr;
+		dst_addr = sg->dst_addr;
+		ctrl0 = GDMA_REG_CTRL0_SW_MODE |
+			(8 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+			(8 << GDMA_REG_CTRL1_DST_REQ_SHIFT);
+	} else {
+		dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+			chan->desc->direction);
+		return -EINVAL;
+	}
+
+	ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
+		 (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
+		 GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
+	ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
+
+	chan->next_sg++;
+	gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
+	gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
+	gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
+
+	/* make sure next_sg is update */
+	wmb();
+	gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
+
+	return 0;
+}
+
+static void rt3883_dump_reg(struct gdma_dma_dev *dma_dev, int id)
+{
+	dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, unmask %08x, done %08x, req %08x, ack %08x, fin %08x\n",
+		id,
+		gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
+		gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT),
+		gdma_dma_read(dma_dev, GDMA_REG_DONE_INT),
+		gdma_dma_read(dma_dev, GDMA_REG_REQSTS),
+		gdma_dma_read(dma_dev, GDMA_REG_ACKSTS),
+		gdma_dma_read(dma_dev, GDMA_REG_FINSTS));
+}
+
+static int rt3883_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
+{
+	struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+	dma_addr_t src_addr, dst_addr;
+	struct gdma_dma_sg *sg;
+	u32 ctrl0, ctrl1;
+
+	/* verify chan is already stopped */
+	ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
+	if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
+		dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
+			chan->id, ctrl0);
+		rt3883_dump_reg(dma_dev, chan->id);
+		return -EINVAL;
+	}
+
+	sg = &chan->desc->sg[chan->next_sg];
+	if (chan->desc->direction == DMA_MEM_TO_DEV) {
+		src_addr = sg->src_addr;
+		dst_addr = chan->fifo_addr;
+		ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED;
+		ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+			(chan->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT);
+	} else if (chan->desc->direction == DMA_DEV_TO_MEM) {
+		src_addr = chan->fifo_addr;
+		dst_addr = sg->dst_addr;
+		ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
+		ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+			(32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
+			GDMA_REG_CTRL1_COHERENT;
+	} else if (chan->desc->direction == DMA_MEM_TO_MEM) {
+		src_addr = sg->src_addr;
+		dst_addr = sg->dst_addr;
+		ctrl0 = GDMA_REG_CTRL0_SW_MODE;
+		ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+			(32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
+			GDMA_REG_CTRL1_COHERENT;
+	} else {
+		dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+			chan->desc->direction);
+		return -EINVAL;
+	}
+
+	ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
+		 (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
+		 GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
+	ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
+
+	chan->next_sg++;
+	gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
+	gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
+	gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
+
+	/* make sure next_sg is update */
+	wmb();
+	gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
+
+	return 0;
+}
+
+static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev,
+				      struct gdma_dmaengine_chan *chan)
+{
+	return dma_dev->data->start_transfer(chan);
+}
+
+static int gdma_next_desc(struct gdma_dmaengine_chan *chan)
+{
+	struct virt_dma_desc *vdesc;
+
+	vdesc = vchan_next_desc(&chan->vchan);
+	if (!vdesc) {
+		chan->desc = NULL;
+		return 0;
+	}
+	chan->desc = to_gdma_dma_desc(vdesc);
+	chan->next_sg = 0;
+
+	return 1;
+}
+
+static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev,
+			      struct gdma_dmaengine_chan *chan)
+{
+	struct gdma_dma_desc *desc;
+	unsigned long flags;
+	int chan_issued;
+
+	chan_issued = 0;
+	spin_lock_irqsave(&chan->vchan.lock, flags);
+	desc = chan->desc;
+	if (desc) {
+		if (desc->cyclic) {
+			vchan_cyclic_callback(&desc->vdesc);
+			if (chan->next_sg == desc->num_sgs)
+				chan->next_sg = 0;
+			chan_issued = 1;
+		} else {
+			desc->residue -= desc->sg[chan->next_sg - 1].len;
+			if (chan->next_sg == desc->num_sgs) {
+				list_del(&desc->vdesc.node);
+				vchan_cookie_complete(&desc->vdesc);
+				chan_issued = gdma_next_desc(chan);
+			} else {
+				chan_issued = 1;
+			}
+		}
+	} else {
+		dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n",
+			chan->id);
+	}
+	if (chan_issued)
+		set_bit(chan->id, &dma_dev->chan_issued);
+	spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static irqreturn_t gdma_dma_irq(int irq, void *devid)
+{
+	struct gdma_dma_dev *dma_dev = devid;
+	u32 done, done_reg;
+	unsigned int i;
+
+	done_reg = dma_dev->data->done_int_reg;
+	done = gdma_dma_read(dma_dev, done_reg);
+	if (unlikely(!done))
+		return IRQ_NONE;
+
+	/* clean done bits */
+	gdma_dma_write(dma_dev, done_reg, done);
+
+	i = 0;
+	while (done) {
+		if (done & 0x1) {
+			gdma_dma_chan_irq(dma_dev, &dma_dev->chan[i]);
+			atomic_dec(&dma_dev->cnt);
+		}
+		done >>= 1;
+		i++;
+	}
+
+	/* start only have work to do */
+	if (dma_dev->chan_issued)
+		tasklet_schedule(&dma_dev->task);
+
+	return IRQ_HANDLED;
+}
+
+static void gdma_dma_issue_pending(struct dma_chan *c)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&chan->vchan.lock, flags);
+	if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
+		if (gdma_next_desc(chan)) {
+			set_bit(chan->id, &dma_dev->chan_issued);
+			tasklet_schedule(&dma_dev->task);
+		} else {
+			dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n",
+				chan->id);
+		}
+	}
+	spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
+		struct dma_chan *c, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_desc *desc;
+	struct scatterlist *sg;
+	unsigned int i;
+
+	desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC);
+	if (!desc) {
+		dev_err(c->device->dev, "alloc sg decs error\n");
+		return NULL;
+	}
+	desc->residue = 0;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		if (direction == DMA_MEM_TO_DEV) {
+			desc->sg[i].src_addr = sg_dma_address(sg);
+		} else if (direction == DMA_DEV_TO_MEM) {
+			desc->sg[i].dst_addr = sg_dma_address(sg);
+		} else {
+			dev_err(c->device->dev, "direction type %d error\n",
+				direction);
+			goto free_desc;
+		}
+
+		if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) {
+			dev_err(c->device->dev, "sg len too large %d\n",
+				sg_dma_len(sg));
+			goto free_desc;
+		}
+		desc->sg[i].len = sg_dma_len(sg);
+		desc->residue += sg_dma_len(sg);
+	}
+
+	desc->num_sgs = sg_len;
+	desc->direction = direction;
+	desc->cyclic = false;
+
+	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+
+free_desc:
+	kfree(desc);
+	return NULL;
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_dma_memcpy(
+		struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
+		size_t len, unsigned long flags)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_desc *desc;
+	unsigned int num_periods, i;
+	size_t xfer_count;
+
+	if (len <= 0)
+		return NULL;
+
+	chan->burst_size = gdma_dma_maxburst(len >> 2);
+
+	xfer_count = GDMA_REG_CTRL0_TX_MASK;
+	num_periods = DIV_ROUND_UP(len, xfer_count);
+
+	desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
+	if (!desc) {
+		dev_err(c->device->dev, "alloc memcpy decs error\n");
+		return NULL;
+	}
+	desc->residue = len;
+
+	for (i = 0; i < num_periods; i++) {
+		desc->sg[i].src_addr = src;
+		desc->sg[i].dst_addr = dest;
+		if (len > xfer_count)
+			desc->sg[i].len = xfer_count;
+		else
+			desc->sg[i].len = len;
+		src += desc->sg[i].len;
+		dest += desc->sg[i].len;
+		len -= desc->sg[i].len;
+	}
+
+	desc->num_sgs = num_periods;
+	desc->direction = DMA_MEM_TO_MEM;
+	desc->cyclic = false;
+
+	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
+	struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
+	size_t period_len, enum dma_transfer_direction direction,
+	unsigned long flags)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct gdma_dma_desc *desc;
+	unsigned int num_periods, i;
+
+	if (buf_len % period_len)
+		return NULL;
+
+	if (period_len > GDMA_REG_CTRL0_TX_MASK) {
+		dev_err(c->device->dev, "cyclic len too large %d\n",
+			period_len);
+		return NULL;
+	}
+
+	num_periods = buf_len / period_len;
+	desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
+	if (!desc) {
+		dev_err(c->device->dev, "alloc cyclic decs error\n");
+		return NULL;
+	}
+	desc->residue = buf_len;
+
+	for (i = 0; i < num_periods; i++) {
+		if (direction == DMA_MEM_TO_DEV) {
+			desc->sg[i].src_addr = buf_addr;
+		} else if (direction == DMA_DEV_TO_MEM) {
+			desc->sg[i].dst_addr = buf_addr;
+		} else {
+			dev_err(c->device->dev, "direction type %d error\n",
+				direction);
+			goto free_desc;
+		}
+		desc->sg[i].len = period_len;
+		buf_addr += period_len;
+	}
+
+	desc->num_sgs = num_periods;
+	desc->direction = direction;
+	desc->cyclic = true;
+
+	return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+
+free_desc:
+	kfree(desc);
+	return NULL;
+}
+
+static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
+					  dma_cookie_t cookie,
+					  struct dma_tx_state *state)
+{
+	struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+	struct virt_dma_desc *vdesc;
+	enum dma_status status;
+	unsigned long flags;
+	struct gdma_dma_desc *desc;
+
+	status = dma_cookie_status(c, cookie, state);
+	if (status == DMA_COMPLETE || !state)
+		return status;
+
+	spin_lock_irqsave(&chan->vchan.lock, flags);
+	desc = chan->desc;
+	if (desc && (cookie == desc->vdesc.tx.cookie)) {
+		/*
+		 * We never update edesc->residue in the cyclic case, so we
+		 * can tell the remaining room to the end of the circular
+		 * buffer.
+		 */
+		if (desc->cyclic)
+			state->residue = desc->residue -
+				((chan->next_sg - 1) * desc->sg[0].len);
+		else
+			state->residue = desc->residue;
+	} else {
+		vdesc = vchan_find_desc(&chan->vchan, cookie);
+		if (vdesc)
+			state->residue = to_gdma_dma_desc(vdesc)->residue;
+	}
+	spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+	dev_dbg(c->device->dev, "tx residue %d bytes\n", state->residue);
+
+	return status;
+}
+
+static void gdma_dma_free_chan_resources(struct dma_chan *c)
+{
+	vchan_free_chan_resources(to_virt_chan(c));
+}
+
+static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
+{
+	kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
+}
+
+static void gdma_dma_tasklet(struct tasklet_struct *t)
+{
+	struct gdma_dma_dev *dma_dev = from_tasklet(dma_dev, t, task);
+	struct gdma_dmaengine_chan *chan;
+	static unsigned int last_chan;
+	unsigned int i, chan_mask;
+
+	/* record last chan to round robin all chans */
+	i = last_chan;
+	chan_mask = dma_dev->data->chancnt - 1;
+	do {
+		/*
+		 * on mt7621. when verify with dmatest with all
+		 * channel is enable. we need to limit only two
+		 * channel is working at the same time. otherwise the
+		 * data will have problem.
+		 */
+		if (atomic_read(&dma_dev->cnt) >= 2) {
+			last_chan = i;
+			break;
+		}
+
+		if (test_and_clear_bit(i, &dma_dev->chan_issued)) {
+			chan = &dma_dev->chan[i];
+			if (chan->desc) {
+				atomic_inc(&dma_dev->cnt);
+				gdma_start_transfer(dma_dev, chan);
+			} else {
+				dev_dbg(dma_dev->ddev.dev,
+					"chan %d no desc to issue\n",
+					chan->id);
+			}
+			if (!dma_dev->chan_issued)
+				break;
+		}
+
+		i = (i + 1) & chan_mask;
+	} while (i != last_chan);
+}
+
+static void rt305x_gdma_init(struct gdma_dma_dev *dma_dev)
+{
+	u32 gct;
+
+	/* all chans round robin */
+	gdma_dma_write(dma_dev, GDMA_RT305X_GCT, GDMA_REG_GCT_ARBIT_RR);
+
+	gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT);
+	dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
+		 (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+		 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+			GDMA_REG_GCT_CHAN_MASK));
+}
+
+static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev)
+{
+	u32 gct;
+
+	/* all chans round robin */
+	gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
+
+	gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
+	dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
+		 (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+		 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+			GDMA_REG_GCT_CHAN_MASK));
+}
+
+static struct gdma_data rt305x_gdma_data = {
+	.chancnt = 8,
+	.done_int_reg = GDMA_RT305X_STATUS_INT,
+	.init = rt305x_gdma_init,
+	.start_transfer = rt305x_gdma_start_transfer,
+};
+
+static struct gdma_data rt3883_gdma_data = {
+	.chancnt = 16,
+	.done_int_reg = GDMA_REG_DONE_INT,
+	.init = rt3883_gdma_init,
+	.start_transfer = rt3883_gdma_start_transfer,
+};
+
+static const struct of_device_id gdma_of_match_table[] = {
+	{ .compatible = "ralink,rt305x-gdma", .data = &rt305x_gdma_data },
+	{ .compatible = "ralink,rt3883-gdma", .data = &rt3883_gdma_data },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, gdma_of_match_table);
+
+static int gdma_dma_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	struct gdma_dmaengine_chan *chan;
+	struct gdma_dma_dev *dma_dev;
+	struct dma_device *dd;
+	unsigned int i;
+	int ret;
+	int irq;
+	void __iomem *base;
+	struct gdma_data *data;
+
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret)
+		return ret;
+
+	match = of_match_device(gdma_of_match_table, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+	data = (struct gdma_data *)match->data;
+
+	dma_dev = devm_kzalloc(&pdev->dev,
+			       struct_size(dma_dev, chan, data->chancnt),
+			       GFP_KERNEL);
+	if (!dma_dev)
+		return -EINVAL;
+	dma_dev->data = data;
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+	dma_dev->base = base;
+	tasklet_setup(&dma_dev->task, gdma_dma_tasklet);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -EINVAL;
+	ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq,
+			       0, dev_name(&pdev->dev), dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		return ret;
+	}
+
+	ret = device_reset(&pdev->dev);
+	if (ret)
+		dev_err(&pdev->dev, "failed to reset: %d\n", ret);
+
+	dd = &dma_dev->ddev;
+	dma_cap_set(DMA_MEMCPY, dd->cap_mask);
+	dma_cap_set(DMA_SLAVE, dd->cap_mask);
+	dma_cap_set(DMA_CYCLIC, dd->cap_mask);
+	dd->device_free_chan_resources = gdma_dma_free_chan_resources;
+	dd->device_prep_dma_memcpy = gdma_dma_prep_dma_memcpy;
+	dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
+	dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
+	dd->device_config = gdma_dma_config;
+	dd->device_terminate_all = gdma_dma_terminate_all;
+	dd->device_tx_status = gdma_dma_tx_status;
+	dd->device_issue_pending = gdma_dma_issue_pending;
+
+	dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+	dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+	dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+
+	dd->dev = &pdev->dev;
+	dd->dev->dma_parms = &dma_dev->dma_parms;
+	dma_set_max_seg_size(dd->dev, GDMA_REG_CTRL0_TX_MASK);
+	INIT_LIST_HEAD(&dd->channels);
+
+	for (i = 0; i < data->chancnt; i++) {
+		chan = &dma_dev->chan[i];
+		chan->id = i;
+		chan->vchan.desc_free = gdma_dma_desc_free;
+		vchan_init(&chan->vchan, dd);
+	}
+
+	/* init hardware */
+	data->init(dma_dev);
+
+	ret = dma_async_device_register(dd);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register dma device\n");
+		return ret;
+	}
+
+	ret = of_dma_controller_register(pdev->dev.of_node,
+					 of_dma_xlate_by_chan_id, dma_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register of dma controller\n");
+		goto err_unregister;
+	}
+
+	platform_set_drvdata(pdev, dma_dev);
+
+	return 0;
+
+err_unregister:
+	dma_async_device_unregister(dd);
+	return ret;
+}
+
+static int gdma_dma_remove(struct platform_device *pdev)
+{
+	struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
+
+	tasklet_kill(&dma_dev->task);
+	of_dma_controller_free(pdev->dev.of_node);
+	dma_async_device_unregister(&dma_dev->ddev);
+
+	return 0;
+}
+
+static struct platform_driver gdma_dma_driver = {
+	.probe = gdma_dma_probe,
+	.remove = gdma_dma_remove,
+	.driver = {
+		.name = "gdma-rt2880",
+		.of_match_table = gdma_of_match_table,
+	},
+};
+module_platform_driver(gdma_dma_driver);
+
+MODULE_DESCRIPTION("Ralink/MTK DMA driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
index ca3b6fb302..5d4cebb089 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c
@@ -199,20 +199,12 @@ static void fe_get_ethtool_stats(struct net_device *dev,
 	do {
 		data_src = &hwstats->tx_bytes;
 		data_dst = data;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 		start = u64_stats_fetch_begin(&hwstats->syncp);
-#else
-		start = u64_stats_fetch_begin_irq(&hwstats->syncp);
-#endif
 
 		for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
 			*data_dst++ = *data_src++;
 
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 	} while (u64_stats_fetch_retry(&hwstats->syncp, start));
-#else
-	} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
-#endif
 }
 
 static struct ethtool_ops fe_ethtool_ops = {
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
index 4365e398d3..c8afa4e3bb 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
@@ -487,11 +487,7 @@ static void fe_get_stats64(struct net_device *dev,
 	}
 
 	do {
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 		start = u64_stats_fetch_begin(&hwstats->syncp);
-#else
-		start = u64_stats_fetch_begin_irq(&hwstats->syncp);
-#endif
 		storage->rx_packets = hwstats->rx_packets;
 		storage->tx_packets = hwstats->tx_packets;
 		storage->rx_bytes = hwstats->rx_bytes;
@@ -503,11 +499,7 @@ static void fe_get_stats64(struct net_device *dev,
 		storage->rx_crc_errors = hwstats->rx_fcs_errors;
 		storage->rx_errors = hwstats->rx_checksum_errors;
 		storage->tx_aborted_errors = hwstats->tx_skip;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 	} while (u64_stats_fetch_retry(&hwstats->syncp, start));
-#else
-	} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
-#endif
 
 	storage->tx_errors = priv->netdev->stats.tx_errors;
 	storage->rx_dropped = priv->netdev->stats.rx_dropped;
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
index 364dd54a58..151caae1dc 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
@@ -21,7 +21,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/phy.h>
 #include <linux/ethtool.h>
-#include <linux/version.h>
 
 enum fe_reg {
 	FE_REG_PDMA_GLO_CFG = 0,
diff --git a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
index a429bb82a3..8b642e28b1 100644
--- a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
+++ b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c
@@ -16,7 +16,6 @@
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
-#include <linux/version.h>
 #include <linux/gpio/consumer.h>
 #include <linux/gpio/driver.h>
 #include <linux/pinctrl/pinconf.h>
@@ -810,11 +809,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)
 	gpiochip->set_multiple = aw9523_gpio_set_multiple;
 	gpiochip->set_config = gpiochip_generic_config;
 	gpiochip->parent = dev;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 	gpiochip->fwnode = dev->fwnode;
-#else
-	gpiochip->of_node = dev->of_node;
-#endif
 	gpiochip->owner = THIS_MODULE;
 	gpiochip->can_sleep = true;
 
@@ -988,12 +983,7 @@ static int aw9523_hw_init(struct aw9523 *awi)
 	return regmap_reinit_cache(awi->regmap, &aw9523_regmap);
 }
 
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
 static int aw9523_probe(struct i2c_client *client)
-#else
-static int aw9523_probe(struct i2c_client *client,
-			const struct i2c_device_id *id)
-#endif
 {
 	struct device *dev = &client->dev;
 	struct pinctrl_desc *pdesc;
diff --git a/target/linux/ramips/image/mt7620.mk b/target/linux/ramips/image/mt7620.mk
index f7238c2b1f..cb41e9bb5a 100644
--- a/target/linux/ramips/image/mt7620.mk
+++ b/target/linux/ramips/image/mt7620.mk
@@ -1340,6 +1340,15 @@ define Device/wavlink_wl-wn530hg4
 endef
 TARGET_DEVICES += wavlink_wl-wn530hg4
 
+define Device/wavlink_wl-wn531g3
+  SOC := mt7620a
+  IMAGE_SIZE := 7808k
+  DEVICE_VENDOR := Wavlink
+  DEVICE_MODEL := WL-WN531G3
+  DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek kmod-usb2 kmod-usb-ohci
+endef
+TARGET_DEVICES += wavlink_wl-wn531g3
+
 define Device/wavlink_wl-wn535k1
   SOC := mt7620a
   IMAGE_SIZE := 7360k
diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk
index 10e7857614..6827fdc1eb 100644
--- a/target/linux/ramips/image/mt7621.mk
+++ b/target/linux/ramips/image/mt7621.mk
@@ -7,7 +7,13 @@ include ./common-tp-link.mk
 
 DEFAULT_SOC := mt7621
 
-DEVICE_VARS += ELECOM_HWNAME LINKSYS_HWNAME DLINK_HWID
+DEVICE_VARS += BUFFALO_TRX_MAGIC ELECOM_HWNAME LINKSYS_HWNAME DLINK_HWID
+
+define Image/Prepare
+	# For UBI we want only one extra block
+	rm -f $(KDIR)/ubi_mark
+	echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark
+endef
 
 define Build/append-dlink-covr-metadata
 	echo -ne '{"supported_devices": "$(1)", "firmware": "' > $@metadata.tmp
@@ -99,13 +105,15 @@ endef
 
 define Build/znet-header
 	$(eval version=$(word 1,$(1)))
+	$(eval magic=$(if $(word 2,$(1)),$(word 2,$(1)),ZNET))
+	$(eval hdrlen=$(if $(word 3,$(1)),$(word 3,$(1)),0x30))
 	( \
 		data_size_crc="$$(dd if=$@ 2>/dev/null | gzip -c | \
 			tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \
 		payload_len="$$(dd if=$@ bs=4 count=1 skip=1 2>/dev/null | od -An -tdI --endian big | tr -d ' \n')"; \
 		payload_size_crc="$$(dd if=$@ ibs=1 count=$$payload_len 2>/dev/null | gzip -c | \
 			tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \
-		echo -ne "\x5A\x4E\x45\x54" | dd bs=4 count=1 conv=sync 2>/dev/null; \
+		echo -ne "$(magic)" | dd bs=4 count=1 conv=sync 2>/dev/null; \
 		echo -ne "$$(printf '%08x' $$(stat -c%s $@) | fold -s2 | xargs -I {} echo \\x{} | tac | tr -d '\n')" | \
 			dd bs=4 count=1 conv=sync 2>/dev/null; \
 		echo -ne "$$(echo $$data_size_crc | sed 's/../\\x&/g')" | \
@@ -114,7 +122,7 @@ define Build/znet-header
 			dd bs=4 count=1 conv=sync 2>/dev/null; \
 		echo -ne "\x12\x34\x56\x78" | dd bs=4 count=1 conv=sync 2>/dev/null; \
 		echo -ne "$(version)" | dd bs=28 count=1 conv=sync 2>/dev/null; \
-		dd if=/dev/zero bs=262096 count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \
+		dd if=/dev/zero bs=$$((0x40000 - $(hdrlen))) count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \
 		cat $@; \
 	) > $@.new
 	mv $@.new $@
@@ -531,6 +539,46 @@ define Device/buffalo_wsr-2533dhpl
 endef
 TARGET_DEVICES += buffalo_wsr-2533dhpl
 
+define Device/buffalo_wsr-2533dhplx
+  $(Device/dsa-migration)
+  DEVICE_VENDOR := Buffalo
+  DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools
+  BUFFALO_TAG_PLATFORM := MTK
+  BUFFALO_TAG_VERSION := 9.99
+  BUFFALO_TAG_MINOR := 9.99
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  UBINIZE_OPTS := -E 5
+  KERNEL_SIZE := 6144k
+  IMAGES += factory.bin factory-uboot.bin
+  IMAGE/factory.bin = append-ubi | \
+	buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark |\
+	buffalo-enc $$(DEVICE_MODEL) 9.99 -l | \
+	buffalo-tag-dhp $$(DEVICE_MODEL) JP JP | buffalo-enc-tag -l | \
+	buffalo-dhp-image
+  IMAGE/factory-uboot.bin := append-ubi | \
+	buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $$$$@ $(KDIR)/ubi_mark | append-metadata
+  IMAGE/sysupgrade.bin := \
+	buffalo-trx $$$$(BUFFALO_TRX_MAGIC) $(KDIR)/tmp/$$(DEVICE_NAME).null | \
+	sysupgrade-tar kernel=$$$$@ | append-metadata
+endef
+
+define Device/buffalo_wsr-2533dhpl2
+  $(Device/buffalo_wsr-2533dhplx)
+  DEVICE_MODEL := WSR-2533DHPL2
+  BUFFALO_TRX_MAGIC := 0x324c4850
+  IMAGE_SIZE := 62592k
+endef
+TARGET_DEVICES += buffalo_wsr-2533dhpl2
+
+define Device/buffalo_wsr-2533dhpls
+  $(Device/buffalo_wsr-2533dhplx)
+  DEVICE_MODEL := WSR-2533DHPLS
+  BUFFALO_TRX_MAGIC := 0x534c4844
+  IMAGE_SIZE := 24576k
+endef
+TARGET_DEVICES += buffalo_wsr-2533dhpls
+
 define Device/buffalo_wsr-600dhp
   $(Device/dsa-migration)
   $(Device/uimage-lzma-loader)
@@ -742,7 +790,7 @@ define Device/dlink_dir-8xx-r1
 	check-size | append-metadata
 endef
 
-define Device/dlink_dir-xx60-a1
+define Device/dlink_dir_nand_128m
   $(Device/nand)
   IMAGE_SIZE := 40960k
   DEVICE_VENDOR := D-Link
@@ -763,35 +811,53 @@ endef
 TARGET_DEVICES += dlink_dir-1935-a1
 
 define Device/dlink_dir-1960-a1
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-1960
   DEVICE_VARIANT := A1
 endef
 TARGET_DEVICES += dlink_dir-1960-a1
 
+define Device/dlink_dir-2055-a1
+  $(Device/dlink_dir_nand_128m)
+  DEVICE_PACKAGES += -kmod-usb-ledtrig-usbport
+  DEVICE_MODEL := DIR-2055
+  DEVICE_VARIANT := A1
+endef
+TARGET_DEVICES += dlink_dir-2055-a1
+
+define Device/dlink_dir-2150-a1
+  $(Device/dlink_dir_nand_128m)
+  DEVICE_MODEL := DIR-2150
+  DEVICE_VARIANT := A1
+  DEVICE_PACKAGES += kmod-mt7603 -kmod-usb3 -kmod-usb-ledtrig-usbport
+  IMAGES += factory.bin
+  IMAGE/factory.bin := $$(IMAGE/recovery.bin) | dlink-sge-image $$(DEVICE_MODEL)
+endef
+TARGET_DEVICES += dlink_dir-2150-a1
+
 define Device/dlink_dir-2640-a1
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-2640
   DEVICE_VARIANT := A1
 endef
 TARGET_DEVICES += dlink_dir-2640-a1
 
 define Device/dlink_dir-2660-a1
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-2660
   DEVICE_VARIANT := A1
 endef
 TARGET_DEVICES += dlink_dir-2660-a1
 
 define Device/dlink_dir-3040-a1
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-3040
   DEVICE_VARIANT := A1
 endef
 TARGET_DEVICES += dlink_dir-3040-a1
 
 define Device/dlink_dir-3060-a1
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-3060
   DEVICE_VARIANT := A1
 endef
@@ -806,7 +872,7 @@ endef
 TARGET_DEVICES += dlink_dir-853-a1
 
 define Device/dlink_dir-853-a3
-  $(Device/dlink_dir-xx60-a1)
+  $(Device/dlink_dir_nand_128m)
   DEVICE_MODEL := DIR-853
   DEVICE_VARIANT := A3
   IMAGES += factory.bin
@@ -969,28 +1035,44 @@ define Device/edimax_rg21s
 endef
 TARGET_DEVICES += edimax_rg21s
 
-define Device/elecom_wrc-1167ghbk2-s
+define Device/elecom_wrc-gs
   $(Device/dsa-migration)
-  IMAGE_SIZE := 15488k
+  $(Device/uimage-lzma-loader)
   DEVICE_VENDOR := ELECOM
-  DEVICE_MODEL := WRC-1167GHBK2-S
   IMAGES += factory.bin
   IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
-	elecom-wrc-gs-factory WRC-1167GHBK2-S 0.00
+	elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \
+	append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME)
   DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools
 endef
-TARGET_DEVICES += elecom_wrc-1167ghbk2-s
 
-define Device/elecom_wrc-gs
+define Device/elecom_wmc-m1267gst2
+  $(Device/elecom_wrc-gs)
+  IMAGE_SIZE := 24576k
+  DEVICE_MODEL := WMC-M1267GST2
+  ELECOM_HWNAME := WMC-DLGST2
+endef
+TARGET_DEVICES += elecom_wmc-m1267gst2
+
+define Device/elecom_wmc-s1267gs2
+  $(Device/elecom_wrc-gs)
+  IMAGE_SIZE := 24576k
+  DEVICE_MODEL := WMC-S1267GS2
+  ELECOM_HWNAME := WMC-DLGST2
+endef
+TARGET_DEVICES += elecom_wmc-s1267gs2
+
+define Device/elecom_wrc-1167ghbk2-s
   $(Device/dsa-migration)
-  $(Device/uimage-lzma-loader)
+  IMAGE_SIZE := 15488k
   DEVICE_VENDOR := ELECOM
+  DEVICE_MODEL := WRC-1167GHBK2-S
   IMAGES += factory.bin
   IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
-	elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \
-	append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME)
+	elecom-wrc-gs-factory WRC-1167GHBK2-S 0.00
   DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools
 endef
+TARGET_DEVICES += elecom_wrc-1167ghbk2-s
 
 define Device/elecom_wrc-1167gs2-b
   $(Device/elecom_wrc-gs)
@@ -1092,6 +1174,27 @@ define Device/elecom_wrc-2533gst2
 endef
 TARGET_DEVICES += elecom_wrc-2533gst2
 
+define Device/elecom_wrc-x1800gs
+  $(Device/nand)
+  DEVICE_VENDOR := ELECOM
+  DEVICE_MODEL := WRC-X1800GS
+  KERNEL := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb | \
+	znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS
+  KERNEL_INITRAMFS := kernel-bin | lzma | \
+	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  KERNEL_SIZE := 8192k
+  IMAGE_SIZE := 51456k
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+  ARTIFACTS := initramfs-factory.bin
+  ARTIFACT/initramfs-factory.bin := append-image-stage initramfs-kernel.bin | \
+	znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS | \
+	check-size
+endif
+  DEVICE_PACKAGES := kmod-mt7915-firmware
+endef
+TARGET_DEVICES += elecom_wrc-x1800gs
+
 define Device/etisalat_s3
   $(Device/sercomm_dxx)
   IMAGE_SIZE := 32768k
@@ -1524,6 +1627,15 @@ define Device/jcg_y2
 endef
 TARGET_DEVICES += jcg_y2
 
+define Device/jdcloud_re-cp-02
+  $(Device/dsa-migration)
+  IMAGE_SIZE := 16000k
+  DEVICE_VENDOR := JD-Cloud
+  DEVICE_MODEL := RE-CP-02
+  DEVICE_PACKAGES := kmod-mt7915-firmware kmod-sdhci-mt7620
+endef
+TARGET_DEVICES += jdcloud_re-cp-02
+
 define Device/keenetic_kn-3010
   $(Device/dsa-migration)
   $(Device/uimage-lzma-loader)
@@ -1704,7 +1816,7 @@ define Device/MikroTik
   DEVICE_PACKAGES := kmod-usb3 -uboot-envtools
   KERNEL_NAME := vmlinuz
   KERNEL := kernel-bin | append-dtb-elf
-  IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 | \
+  IMAGE/sysupgrade.bin := append-kernel | yaffs-filesystem -L | \
 	pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size | \
 	append-metadata
 endef
diff --git a/target/linux/ramips/image/mt76x8.mk b/target/linux/ramips/image/mt76x8.mk
index fc81266da9..b33a789398 100644
--- a/target/linux/ramips/image/mt76x8.mk
+++ b/target/linux/ramips/image/mt76x8.mk
@@ -147,6 +147,17 @@ define Device/comfast_cf-wr758ac-v2
 endef
 TARGET_DEVICES += comfast_cf-wr758ac-v2
 
+define Device/cudy_tr1200-v1
+  IMAGE_SIZE := 15872k
+  DEVICE_VENDOR := Cudy
+  DEVICE_MODEL := TR1200
+  DEVICE_VARIANT := v1
+  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \
+	kmod-mt7615e kmod-mt7663-firmware-ap
+  SUPPORTED_DEVICES += R46
+endef
+TARGET_DEVICES += cudy_tr1200-v1
+
 define Device/cudy_wr1000
   IMAGE_SIZE := 7872k
   IMAGES += factory.bin
@@ -606,6 +617,21 @@ define Device/tplink_archer-c50-v6
 endef
 TARGET_DEVICES += tplink_archer-c50-v6
 
+define Device/tplink_archer-mr200-v5
+  $(Device/tplink-v2)
+  IMAGE_SIZE := 7872k
+  DEVICE_MODEL := Archer MR200
+  DEVICE_VARIANT := v5
+  TPLINK_FLASHLAYOUT := 8MLmtk
+  TPLINK_HWID := 0x20000005
+  TPLINK_HWREV := 0x5
+  TPLINK_HWREVADD := 0x5
+  DEVICE_PACKAGES := kmod-mt76x0e uqmi kmod-usb2 kmod-usb-serial-option
+  IMAGES := sysupgrade.bin tftp-recovery.bin
+  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)
+endef
+TARGET_DEVICES += tplink_archer-mr200-v5
+
 define Device/tplink_re200-v2
   $(Device/tplink-safeloader)
   IMAGE_SIZE := 7808k
diff --git a/target/linux/ramips/modules.mk b/target/linux/ramips/modules.mk
index 429bb2cd26..f32b82aef8 100644
--- a/target/linux/ramips/modules.mk
+++ b/target/linux/ramips/modules.mk
@@ -74,19 +74,18 @@ $(eval $(call KernelPackage,i2c-mt7628))
 define KernelPackage/dma-ralink
   SUBMENU:=Other modules
   TITLE:=Ralink GDMA Engine
-  DEPENDS:=@TARGET_ramips
+  DEPENDS:=@TARGET_ramips @!TARGET_ramips_rt288x
   KCONFIG:= \
 	CONFIG_DMADEVICES=y \
-	CONFIG_DW_DMAC_PCI=n \
-	CONFIG_DMA_RALINK
+	CONFIG_RALINK_GDMA
   FILES:= \
 	$(LINUX_DIR)/drivers/dma/virt-dma.ko \
-	$(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko
+	$(LINUX_DIR)/drivers/dma/ralink-gdma.ko
   AUTOLOAD:=$(call AutoLoad,52,ralink-gdma)
 endef
 
 define KernelPackage/dma-ralink/description
- Kernel modules for enable ralink dma engine.
+ Kernel modules for enable ralink gdma engine.
 endef
 
 $(eval $(call KernelPackage,dma-ralink))
@@ -97,7 +96,6 @@ define KernelPackage/hsdma-mtk
   DEPENDS:=@TARGET_ramips @TARGET_ramips_mt7621
   KCONFIG:= \
 	CONFIG_DMADEVICES=y \
-	CONFIG_DW_DMAC_PCI=n \
 	CONFIG_MTK_HSDMA
   FILES:= \
 	$(LINUX_DIR)/drivers/dma/virt-dma.ko \
diff --git a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
index 63f7e41ac2..d23ec76327 100644
--- a/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt7620/base-files/etc/board.d/02_network
@@ -253,6 +253,10 @@ ramips_setup_interfaces()
 		ucidef_add_switch "switch1" \
 			"0:lan:3" "1:lan:2" "2:lan:1" "4:lan:4" "3:wan" "7@eth0"
 		;;
+	wavlink,wl-wn531g3)
+		ucidef_add_switch "switch0" \
+			"0:lan:4" "1:lan:3" "2:lan:2" "5:lan:1" "4:wan" "6@eth0"
+		;;
 	wavlink,wl-wn535k1)
 		ucidef_add_switch "switch0" \
 			"2:lan:2" "5:lan:1" "4:wan" "6@eth0"
@@ -426,13 +430,14 @@ ramips_setup_macs()
 	tplink,ec220-g5-v2)
 		wan_mac=$(macaddr_add "$(mtd_get_mac_binary rom 0xf100)" 1)
 		;;
+	wavlink,wl-wn531g3|\
+	zbtlink,zbt-we1026-5g-16m)
+		label_mac=$(mtd_get_mac_binary factory 0x4)
+		;;
 	wavlink,wl-wn535k1)
 		wan_mac=$(mtd_get_mac_binary factory 0x2e)
 		label_mac=$(mtd_get_mac_binary factory 0x8004)
 		;;
-	zbtlink,zbt-we1026-5g-16m)
-		label_mac=$(mtd_get_mac_binary factory 0x4)
-		;;
 	zyxel,keenetic-lite-iii-a)
 		lan_mac=$(mtd_get_mac_binary RF-EEPROM 0x4)
 		wan_mac=$(mtd_get_mac_binary RF-EEPROM 0x28)
diff --git a/target/linux/ramips/mt7620/config-6.1 b/target/linux/ramips/mt7620/config-6.1
deleted file mode 100644
index 111a59ab00..0000000000
--- a/target/linux/ramips/mt7620/config-6.1
+++ /dev/null
@@ -1,215 +0,0 @@
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_OMEGA2P is not set
-CONFIG_DTB_RT_NONE=y
-# CONFIG_DTB_VOCORE2 is not set
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_JIMAGE_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_MT7620=y
-CONFIG_NET_RALINK_MT7620=y
-# CONFIG_NET_RALINK_RT3050 is not set
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_MEDIATEK is not set
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_MT7620=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/mt7620/config-6.6 b/target/linux/ramips/mt7620/config-6.6
index 839b201cf1..bf96543344 100644
--- a/target/linux/ramips/mt7620/config-6.6
+++ b/target/linux/ramips/mt7620/config-6.6
@@ -179,6 +179,7 @@ CONFIG_PINCTRL_MTK_MTMIPS=y
 CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
 CONFIG_RALINK_WDT=y
 CONFIG_RANDSTRUCT_NONE=y
 CONFIG_RATIONAL=y
diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds
index 6848bebd00..21b1e8ea91 100644
--- a/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds
+++ b/target/linux/ramips/mt7621/base-files/etc/board.d/01_leds
@@ -92,14 +92,16 @@ dlink,dap-x1860-a1)
 	ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "green:rssihigh" "wlan1" "76" "100"
 	;;
 dlink,dir-1960-a1|\
+dlink,dir-2055-a1|\
+dlink,dir-2150-a1|\
 dlink,dir-2640-a1|\
 dlink,dir-2660-a1)
-	ucidef_set_led_netdev "wan" "wan" "white:net" "wan"
+	ucidef_set_led_netdev "wan" "wan" "white:wan" "wan"
 	;;
 dlink,dir-3040-a1|\
 dlink,dir-3060-a1)
-	ucidef_set_led_netdev "net_white" "WAN Link" "white:net" "wan" "link"
-	ucidef_set_led_netdev "net_orange" "WAN Activity" "orange:net" "wan" "tx rx"
+	ucidef_set_led_netdev "net_white" "WAN Link" "white:wan" "wan" "link"
+	ucidef_set_led_netdev "net_orange" "WAN Activity" "orange:wan" "wan" "tx rx"
 	;;
 dlink,dir-853-a1|\
 dlink,dir-853-a3)
diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
index d932313cf1..247a27d145 100644
--- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network
@@ -11,6 +11,8 @@ ramips_setup_interfaces()
 	alfa-network,ax1800rm|\
 	ampedwireless,ally-r1900k|\
 	asus,rt-ax53u|\
+	buffalo,wsr-2533dhpl2|\
+	buffalo,wsr-2533dhpls|\
 	gehua,ghl-r-001|\
 	h3c,tx1800-plus|\
 	h3c,tx1801-plus|\
@@ -71,6 +73,7 @@ ramips_setup_interfaces()
 	asiarf,ap7621-nv1|\
 	beeline,smartbox-flash|\
 	beeline,smartbox-giga|\
+	elecom,wrc-x1800gs|\
 	glinet,gl-mt1300|\
 	iodata,wn-deax1800gr|\
 	iptime,a3002mesh|\
@@ -102,17 +105,18 @@ ramips_setup_interfaces()
 	dlink,covr-x1860-a1)
 		ucidef_set_interfaces_lan_wan "ethernet" "internet"
 		;;
+	elecom,wmc-s1267gs2|\
+	linksys,re6500|\
+	netgear,wac104|\
+	zyxel,lte3301-plus)
+		ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+		;;
 	gnubee,gb-pc1)
 		ucidef_set_interface_lan "ethblack ethblue"
 		;;
 	gnubee,gb-pc2)
 		ucidef_set_interface_lan "ethblack ethblue ethyellow"
 		;;
-	linksys,re6500|\
-	netgear,wac104|\
-	zyxel,lte3301-plus)
-		ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
-		;;
 	mikrotik,routerboard-750gr3)
 		ucidef_set_interfaces_lan_wan "lan2 lan3 lan4 lan5" "wan"
 		;;
@@ -213,7 +217,9 @@ ramips_setup_macs()
 		label_mac=$(macaddr_add "$wan_mac" 3)
 		lan_mac=$label_mac
 		;;
-	buffalo,wsr-1166dhp)
+	buffalo,wsr-1166dhp|\
+	buffalo,wsr-2533dhpl2|\
+	buffalo,wsr-2533dhpls)
 		wan_mac=$(mtd_get_mac_ascii board_data "mac")
 		lan_mac=$wan_mac
 		label_mac=$wan_mac
diff --git a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
index 0ec46bb0ea..9350d67466 100644
--- a/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
+++ b/target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
@@ -27,6 +27,13 @@ case "$board" in
 		hw_mac_addr=$(macaddr_unsetbit $hw_mac_addr 28)
 		[ "$PHYNBR" = "1" ] && macaddr_setbit_la $hw_mac_addr > /sys${DEVPATH}/macaddress
 		;;
+	buffalo,wsr-2533dhpls)
+		lan_mac_addr=$(mtd_get_mac_ascii board_data "mac")
+		[ "$PHYNBR" = "0" ] && \
+			macaddr_add $lan_mac_addr 1 > /sys${DEVPATH}/macaddress
+		[ "$PHYNBR" = "1" ] && \
+			macaddr_add $lan_mac_addr 8 > /sys${DEVPATH}/macaddress
+		;;
 	comfast,cf-e390ax)
 		[ "$PHYNBR" = "0" ] && echo -n "$(mtd_get_mac_binary factory 0x0004)" > /sys${DEVPATH}/macaddress
 		[ "$PHYNBR" = "1" ] && echo -n "$(mtd_get_mac_binary factory 0x8004)" > /sys${DEVPATH}/macaddress
diff --git a/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount b/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount
index c558247341..06846cd4ca 100755
--- a/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount
+++ b/target/linux/ramips/mt7621/base-files/etc/init.d/bootcount
@@ -15,6 +15,9 @@ boot() {
 			$((0xff)) ]] || printf '\xff' | dd of=/dev/mtdblock3 \
 			count=1 bs=1 seek=$((0x20001))
 		;;
+	jdcloud,re-cp-02)
+		echo -e "bootcount 0\nbootlimit 5\nupgrade_available 1"  | /usr/sbin/fw_setenv -s -
+		;;
 	linksys,e5600|\
 	linksys,ea6350-v4|\
 	linksys,ea7300-v1|\
diff --git a/target/linux/ramips/mt7621/base-files/etc/uci-defaults/04_led_migration b/target/linux/ramips/mt7621/base-files/etc/uci-defaults/04_led_migration
index b595ae6fd1..30860346f4 100644
--- a/target/linux/ramips/mt7621/base-files/etc/uci-defaults/04_led_migration
+++ b/target/linux/ramips/mt7621/base-files/etc/uci-defaults/04_led_migration
@@ -4,6 +4,13 @@
 board=$(board_name)
 
 case "$board" in
+dlink,dir-1960-a1|\
+dlink,dir-2640-a1|\
+dlink,dir-2660-a1|\
+dlink,dir-3040-a1|\
+dlink,dir-3060-a1)
+	migrate_leds ':net=:wan'
+	;;
 tplink,archer-a6-v3|\
 tplink,archer-c6-v3)
 	migrate_leds ':wifi2g$=:wlan-2' ':wifi5g$=:wlan-5'
diff --git a/target/linux/ramips/mt7621/base-files/etc/uci-defaults/09_fix_crc b/target/linux/ramips/mt7621/base-files/etc/uci-defaults/09_fix_crc
new file mode 100644
index 0000000000..80e6d71d90
--- /dev/null
+++ b/target/linux/ramips/mt7621/base-files/etc/uci-defaults/09_fix_crc
@@ -0,0 +1,22 @@
+. /lib/functions.sh
+
+# don't modify FW data when booting with initramfs image
+fstype="$(/bin/mount | awk '($3 ~ /^\/$/) && ($5 !~ /rootfs/) { print $5 }')"
+[ "$fstype" = "tmpfs" ] && \
+	exit 0
+
+fixup_trx_crc() {
+	local trx_magic="$1"
+	local kernel_size=$(sed -n 's/mtd[0-9]*: \([0-9a-f]*\).*"\(kernel\|linux\)".*/\1/p' /proc/mtd)
+
+	mtd -M $trx_magic ${kernel_size:+-c 0x$kernel_size} fixtrx firmware
+}
+
+case "$(board_name)" in
+buffalo,wsr-2533dhpl2)
+	fixup_trx_crc 0x50484c32
+	;;
+buffalo,wsr-2533dhpls)
+	fixup_trx_crc 0x44484C53
+	;;
+esac
diff --git a/target/linux/ramips/mt7621/base-files/lib/preinit/04_set_netdev_label b/target/linux/ramips/mt7621/base-files/lib/preinit/04_set_netdev_label
new file mode 100644
index 0000000000..110e023b96
--- /dev/null
+++ b/target/linux/ramips/mt7621/base-files/lib/preinit/04_set_netdev_label
@@ -0,0 +1,15 @@
+set_netdev_labels() {
+	local dir
+	local label
+	local netdev
+
+	for dir in /sys/class/net/*; do
+		[ -r "$dir/of_node/label" ] || continue
+		read -r label < "$dir/of_node/label"
+		netdev="${dir##*/}"
+		[ "$netdev" = "$label" ] && continue
+		ip link set "$netdev" name "$label"
+	done
+}
+
+boot_hook_add preinit_main set_netdev_labels
diff --git a/target/linux/ramips/mt7621/base-files/lib/upgrade/buffalo.sh b/target/linux/ramips/mt7621/base-files/lib/upgrade/buffalo.sh
new file mode 100644
index 0000000000..5d3e184d08
--- /dev/null
+++ b/target/linux/ramips/mt7621/base-files/lib/upgrade/buffalo.sh
@@ -0,0 +1,112 @@
+# The mtd partitions "firmware" and "Kernel2" on NAND flash are os-image
+# partitions. These partitions are called as "Image1/Image2" in U-Boot
+# on WSR-2533DHPLx devices, and they are checked conditions when booting.
+# "Image1" is always used for booting.
+#
+# == U-Boot Behaviors ==
+#
+# - "Image1"/"Image2" images are good, images are different or
+#   "Image2" image is broken
+#   -> copy os-image to "Image2" from "Image1"
+#
+# - "Image1" image is broken
+#   -> copy os-image to "Image1" from "Image2"
+#
+# - "Image1"/"Image2" images are broken
+#   -> fall to U-Boot command line
+
+# TRX magic numbers of each model
+case "$(board_name)" in
+buffalo,wsr-2533dhpl2)
+	BUFFALO_TRX_MAGIC="50484c32" # "PHL2"
+	;;
+buffalo,wsr-2533dhpls)
+	BUFFALO_TRX_MAGIC="44484c53" # "DHLS"
+	;;
+esac
+
+buffalo_check_image() {
+	local board="$1"
+	local boardname="$(echo $board | tr ',' '_')"
+	local magic="$2"
+	local fw_image="$3"
+
+	# return error state if TRX + UBI formatted image specified
+	# to notify about configurations
+	if [ "$magic" = "$BUFFALO_TRX_MAGIC" ]; then
+		echo "Your configurations won't be saved if factory-uboot.bin image specified."
+		echo "But if you want to upgrade, please execute sysupgrade with \"-F\" option."
+		return 1
+	fi
+
+	# check if valid tar file specifed
+	if ! tar tf "$fw_image" &>/dev/null; then
+		echo "Specified file is not a tar archive: $fw_image"
+		return 1
+	fi
+
+	local control_len=$( (tar xf $fw_image sysupgrade-$boardname/CONTROL -O | wc -c) 2> /dev/null)
+
+	# check if valid sysupgrade tar archive
+	if [ "$control_len" = "0" ]; then
+		echo "Invalid sysupgrade file: $fw_image"
+		return 1
+	fi
+
+	local kern_part_len=$(grep "\"linux\"" /proc/mtd | sed "s/mtd[0-9]*:[ \t]*\([^ \t]*\).*/\1/")
+	[ -z "$kern_part_len" ] && {
+		echo "Unable to get \"linux\" partition size"
+		return 1
+	}
+	kern_part_len=$((0x$kern_part_len))
+
+	# this also checks if the sysupgrade image is for correct models
+	local kern_bin_len=$( (tar xf $fw_image sysupgrade-${boardname}/kernel -O | wc -c) 2> /dev/null)
+	if [ -z "$kern_bin_len" ]; then
+		echo "Failed to get new kernel size, is valid sysupgrade image specified for the device?"
+		return 1
+	fi
+
+	# kernel binary has a trx header (len: 28 (0x1c))
+	kern_bin_len=$((kern_bin_len - 28))
+
+	if [ "$kern_bin_len" != "$kern_part_len" ]; then
+		echo -n "The length of new kernel is invalid for current "
+		echo "\"linux\" partition, please use factory-uboot.bin image."
+		echo "\"linux\" partition: $kern_part_len, new kernel: $kern_bin_len"
+		return 1
+	fi
+}
+
+# for TRX + UBI formatted image
+buffalo_upgrade_ubinized() {
+	sync
+	echo 3 > /proc/sys/vm/drop_caches
+
+	local mtdnum="$( find_mtd_index "ubi" )"
+	# if no "ubi", don't return error for the purpose of recovery
+	# ex: recovery after accidental erasing "firmware" partition
+	if [ ! "$mtdnum" ]; then
+		echo "cannot find ubi mtd partition \"ubi\", skip detachment"
+	else
+		ubidetach -m "$mtdnum"
+	fi
+
+	# erase all data in "firmware"
+	mtd erase "${PART_NAME}"
+	# write TRX + UBI formatted image to "firmware"
+	get_image "$1" | mtd $MTD_ARGS write - "${PART_NAME:-firmware}"
+	if [ $? -ne 0 ]; then
+		echo "Failed to write the specified image."
+		exit 1
+	fi
+}
+
+buffalo_do_upgrade() {
+	if [ "$(get_magic_long "$1")" = "$BUFFALO_TRX_MAGIC" ]; then
+		buffalo_upgrade_ubinized "$1"
+	else
+		CI_KERNPART="firmware"
+		nand_do_upgrade "$1"
+	fi
+}
diff --git a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh
index 93fbc470ad..32dad72944 100755
--- a/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh
@@ -9,6 +9,18 @@ RAMFS_COPY_BIN='fw_printenv fw_setenv'
 RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
 
 platform_check_image() {
+	local board=$(board_name)
+	local magic="$(get_magic_long "$1")"
+
+	[ "$#" -gt 1 ] && return 1
+
+	case "$board" in
+	buffalo,wsr-2533dhpl2|\
+	buffalo,wsr-2533dhpls)
+		buffalo_check_image "$board" "$magic" "$1" || return 1
+		;;
+	esac
+
 	return 0
 }
 
@@ -71,6 +83,8 @@ platform_do_upgrade() {
 	dlink,covr-x1860-a1|\
 	dlink,dap-x1860-a1|\
 	dlink,dir-1960-a1|\
+        dlink,dir-2055-a1|\
+	dlink,dir-2150-a1|\
 	dlink,dir-2640-a1|\
 	dlink,dir-2660-a1|\
 	dlink,dir-3040-a1|\
@@ -130,6 +144,16 @@ platform_do_upgrade() {
 	zyxel,nwa55axe)
 		nand_do_upgrade "$1"
 		;;
+	buffalo,wsr-2533dhpl2|\
+	buffalo,wsr-2533dhpls)
+		buffalo_do_upgrade "$1"
+		;;
+	elecom,wrc-x1800gs)
+		[ "$(fw_printenv -n bootmenu_delay)" != "0" ] || \
+			fw_setenv bootmenu_delay 3
+		iodata_mstc_set_flag "bootnum" "persist" "0x4" "1,2" "1"
+		nand_do_upgrade "$1"
+		;;
 	iodata,wn-ax1167gr2|\
 	iodata,wn-ax2033gr|\
 	iodata,wn-dx1167r|\
diff --git a/target/linux/ramips/mt7621/config-6.1 b/target/linux/ramips/mt7621/config-6.1
deleted file mode 100644
index 8f2355c564..0000000000
--- a/target/linux/ramips/mt7621/config-6.1
+++ /dev/null
@@ -1,312 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_AT803X_PHY=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLK_MT7621=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DIMLIB=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_GRO_CELLS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_MT7621=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIKROTIK=y
-CONFIG_MIKROTIK_RB_SYSFS=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPS=y
-# CONFIG_MIPS_CPS_NS16550_BOOL is not set
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_NR_CPU_NR_MAP=4
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MT7621=y
-CONFIG_MTD_NAND_MTK_BMT=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_ROUTERBOOT_PARTS=y
-CONFIG_MTD_SERCOMM_PARTS=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_MINOR_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_TRX_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_RALINK is not set
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIE_MT7621=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_DRIVERS_GENERIC=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MT7621_PCI=y
-# CONFIG_PHY_RALINK_USB is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AW9523=y
-CONFIG_PINCTRL_MT7621=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SX150X=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCOM_NET_PHYLIB=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BQ32K=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_SMT=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_MT7621=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ramips/mt7621/config-6.6 b/target/linux/ramips/mt7621/config-6.6
index 9225a9c35c..e77ea238e7 100644
--- a/target/linux/ramips/mt7621/config-6.6
+++ b/target/linux/ramips/mt7621/config-6.6
@@ -161,6 +161,7 @@ CONFIG_MTD_NAND_ECC_SW_HAMMING=y
 CONFIG_MTD_NAND_MT7621=y
 CONFIG_MTD_NAND_MTK_BMT=y
 # CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PARSER_TRX=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MTD_ROUTERBOOT_PARTS=y
@@ -171,7 +172,6 @@ CONFIG_MTD_SPLIT_FIT_FW=y
 CONFIG_MTD_SPLIT_MINOR_FW=y
 CONFIG_MTD_SPLIT_SEAMA_FW=y
 CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_TRX_FW=y
 CONFIG_MTD_SPLIT_UIMAGE_FW=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_BEB_LIMIT=20
@@ -242,6 +242,7 @@ CONFIG_QCOM_NET_PHYLIB=y
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
 CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
 # CONFIG_RALINK_WDT is not set
 CONFIG_RANDSTRUCT_NONE=y
 CONFIG_RATIONAL=y
diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds
index da3ef154c0..324b57124f 100644
--- a/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds
+++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds
@@ -83,6 +83,10 @@ tplink,archer-c50-v6)
 	ucidef_set_led_wlan "wlan2g" "wlan2g" "green:wlan2g" "phy0tpt"
 	ucidef_set_led_wlan "wlan5g" "wlan5g" "green:wlan5g" "phy1tpt"
 	;;
+tplink,archer-mr200-v5)
+	ucidef_set_led_netdev "lan" "lan" "white:lan" "eth0"
+	ucidef_set_led_netdev "wan" "wan" "white:wan" "wwan0"
+	;;
 tplink,re200-v2|\
 tplink,re200-v3|\
 tplink,re200-v4|\
diff --git a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network
index fd8c086a85..bec8e9e3df 100644
--- a/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network
+++ b/target/linux/ramips/mt76x8/base-files/etc/board.d/02_network
@@ -94,6 +94,10 @@ ramips_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"4:lan" "6@eth0"
 		;;
+	cudy,tr1200)
+		ucidef_add_switch "switch0" \
+			"0:lan" "1:wan" "6@eth0"
+		;;
 	cudy,wr1000)
 		ucidef_add_switch "switch0" \
 			"2:lan:2" "3:lan:1" "4:wan" "6@eth0"
@@ -153,6 +157,11 @@ ramips_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0:wan" "1:lan" "2:lan" "3:lan" "4:lan" "6t@eth0"
 		;;
+	tplink,archer-mr200-v5)
+		ucidef_add_switch "switch0" \
+			"0:lan" "1:lan" "2:lan" "3:lan" "6t@eth0"
+		ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
+		;;
 	tplink,tl-mr3020-v3)
 		ucidef_add_switch "switch0" \
 			"0:lan" "6@eth0"
diff --git a/target/linux/ramips/mt76x8/config-6.1 b/target/linux/ramips/mt76x8/config-6.1
deleted file mode 100644
index be779b03d8..0000000000
--- a/target/linux/ramips/mt76x8/config-6.1
+++ /dev/null
@@ -1,215 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_OMEGA2P is not set
-CONFIG_DTB_RT_NONE=y
-# CONFIG_DTB_VOCORE2 is not set
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_ESW_RT3050=y
-# CONFIG_NET_RALINK_MT7620 is not set
-CONFIG_NET_RALINK_RT3050=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_MEDIATEK is not set
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_MT7620=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/mt76x8/config-6.6 b/target/linux/ramips/mt76x8/config-6.6
index b03b220a71..db1281ad54 100644
--- a/target/linux/ramips/mt76x8/config-6.6
+++ b/target/linux/ramips/mt76x8/config-6.6
@@ -173,6 +173,7 @@ CONFIG_PINCTRL_MTK_MTMIPS=y
 CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
 # CONFIG_RALINK_WDT is not set
 CONFIG_RANDSTRUCT_NONE=y
 CONFIG_RATIONAL=y
diff --git a/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch b/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch
deleted file mode 100644
index 4574f7977f..0000000000
--- a/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 6 Feb 2023 09:33:05 +0100
-Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
-
-Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
-
-UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
-shift exponent 131072 is too large for 32-bit type 'long unsigned int'
-CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
-Stack : ...
-
-Call Trace:
-[<80009a58>] show_stack+0x38/0x118
-[<8045ce04>] dump_stack_lvl+0x60/0x80
-[<80458868>] ubsan_epilogue+0x10/0x54
-[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
-[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
-[<804bb774>] clk_core_is_enabled+0x34/0x90
-[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
-[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
-[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
-[<80aad900>] clk_disable_unused+0x78/0x120
-[<80002030>] do_one_initcall+0x54/0x1f0
-[<80a922a4>] kernel_init_freeable+0x280/0x31c
-[<808047c4>] kernel_init+0x20/0x118
-[<80003e58>] ret_from_kernel_thread+0x14/0x1c
-
-Shifting a value (131032) larger than the type (32 bit unsigned integer)
-is undefined behaviour in C.
-
-The problem is in 'mt7621_gate_is_enabled()' function which is using the
-'BIT()' kernel macro with the bit index for the clock gate to check if the
-bit is set. When the clock gates structure is created driver is already
-setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
-'BIT()' mask here. Removing it solve the problem and makes this function
-correct. However when clock gating is correctly working, the kernel starts
-disabling those clocks that are not requested. Some drivers for this SoC
-are older than this clock driver itself. So to avoid the kernel to disable
-clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
-flag on gates initialization code.
-
-Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/ralink/clk-mt7621.c
-+++ b/drivers/clk/ralink/clk-mt7621.c
-@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
- 	if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
- 		return 0;
- 
--	return val & BIT(clk_gate->bit_idx);
-+	return val & clk_gate->bit_idx;
- }
- 
- static const struct clk_ops mt7621_gate_ops = {
-@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
- static int mt7621_gate_ops_init(struct device *dev,
- 				struct mt7621_gate *sclk)
- {
-+	/*
-+	 * There are drivers for this SoC that are older
-+	 * than clock driver and are not prepared for the clock.
-+	 * We don't want the kernel to disable anything so we
-+	 * add CLK_IS_CRITICAL flag here.
-+	 */
- 	struct clk_init_data init = {
--		.flags = CLK_SET_RATE_PARENT,
-+		.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- 		.num_parents = 1,
- 		.parent_names = &sclk->parent_name,
- 		.ops = &mt7621_gate_ops,
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch b/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
deleted file mode 100644
index 94784f7885..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:33 +0200
-Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
-
-Adds device tree binding documentation for system controller node present
-in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
-for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
-RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- .../bindings/clock/mediatek,mtmips-sysc.yaml       | 64 ++++++++++++++++++++++
- 1 file changed, 64 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MTMIPS SoCs System Controller
-+
-+maintainers:
-+  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+
-+description: |
-+  MediaTek MIPS and Ralink SoCs provides a system controller to allow
-+  to access to system control registers. These registers include clock
-+  and reset related ones so this node is both clock and reset provider
-+  for the rest of the world.
-+
-+  These SoCs have an XTAL from where the cpu clock is
-+  provided as well as derived clocks for the bus and the peripherals.
-+
-+properties:
-+  compatible:
-+    items:
-+      - enum:
-+          - ralink,mt7620-sysc
-+          - ralink,mt7628-sysc
-+          - ralink,mt7688-sysc
-+          - ralink,rt2880-sysc
-+          - ralink,rt3050-sysc
-+          - ralink,rt3052-sysc
-+          - ralink,rt3352-sysc
-+          - ralink,rt3883-sysc
-+          - ralink,rt5350-sysc
-+      - const: syscon
-+
-+  reg:
-+    maxItems: 1
-+
-+  '#clock-cells':
-+    description:
-+      The first cell indicates the clock number.
-+    const: 1
-+
-+  '#reset-cells':
-+    description:
-+      The first cell indicates the reset bit within the register.
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - '#clock-cells'
-+  - '#reset-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    syscon@0 {
-+      compatible = "ralink,rt5350-sysc", "syscon";
-+      reg = <0x0 0x100>;
-+      #clock-cells = <1>;
-+      #reset-cells = <1>;
-+    };
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch b/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch
deleted file mode 100644
index cef39978e0..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch
+++ /dev/null
@@ -1,1221 +0,0 @@
-From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:34 +0200
-Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
-
-Until now, clock related code for old ralink SoCs was based in fixed clocks
-using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
-and not using device tree at all for their definition. Including this driver
-is an effort to be able to define proper clocks using device tree and also
-cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
-This clock and reset driver covers all the ralink SoCs but MT7621 which is
-the newest and provides gating and some differences that make it different
-from its predecesors. It has its own driver since some time ago. The ralink
-SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
-RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
-been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
-driver APIs. The clock plans for this SoCs only talks about relation between
-CPU frequency and BUS frequency. This relation is different depending on the
-particular SoC. CPU clock is derived from XTAL frequencies.
-
-Depending on the SoC we have the following frequencies:
-* RT2880 SoC:
-    - XTAL: 40 MHz.
-    - CPU: 250, 266, 280 or 300 MHz.
-    - BUS: CPU / 2 MHz.
-* RT3050, RT3052, RT3350:
-    - XTAL: 40 MHz.
-    - CPU: 320 or 384 MHz.
-    - BUS: CPU / 3 MHz.
-* RT3352:
-    - XTAL: 40 MHz.
-    - CPU: 384 or 400 MHz.
-    - BUS: CPU / 3 MHz.
-    - PERIPH: 40 MHz.
-* RT3383:
-    - XTAL: 40 MHz.
-    - CPU: 250, 384, 480 or 500 MHz.
-    - BUS: Depends on RAM Type and CPU:
-        + RAM DDR2: 125. ELSE 83 MHz.
-        + RAM DDR2: 128. ELSE 96 MHz.
-        + RAM DDR2: 160. ELSE 120 MHz.
-        + RAM DDR2: 166. ELSE 125 MHz.
-* RT5350:
-    - XTAL: 40 MHz.
-    - CPU: 300, 320 or 360 MHz.
-    - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
-    - PERIPH: 40 MHz.
-* MT7628 and MT7688:
-    - XTAL: 20 MHz or 40 MHz.
-    - CPU: 575 or 580 MHz.
-    - BUS: CPU / 3.
-    - PCMI2S: 480 MHz.
-    - PERIPH: 40 MHz.
-* MT7620:
-    - XTAL: 20 MHz or 40 MHz.
-    - PLL: XTAL, 480, 600 MHz.
-    - CPU: depends on PLL and some mult and dividers.
-    - BUS: depends on PLL and some mult and dividers.
-    - PERIPH: 40 or XTAL MHz.
-
-MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
-register reads and predividers. To derive CPU and BUS frequencies in the
-MT7620 SoC 'mt7620_calc_rate()' helper is used.
-
-In the case XTAL can have different frequencies and we need a different
-clock frequency for peripherals 'periph' clock in introduced.
-
-The rest of the peripherals present in the SoC just follow their parent
-frequencies.
-
-With this information the clk driver will provide all the clock and reset
-functionality from a set of hardcoded clocks allowing to define a nice
-device tree without fixed clocks.
-
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- drivers/clk/ralink/Kconfig      |    7 +
- drivers/clk/ralink/Makefile     |    1 +
- drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 1123 insertions(+)
- create mode 100644 drivers/clk/ralink/clk-mtmips.c
-
---- a/drivers/clk/ralink/Kconfig
-+++ b/drivers/clk/ralink/Kconfig
-@@ -9,3 +9,10 @@ config CLK_MT7621
- 	select MFD_SYSCON
- 	help
- 	  This driver supports MediaTek MT7621 basic clocks.
-+
-+config CLK_MTMIPS
-+	bool "Clock driver for MTMIPS SoCs"
-+	depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
-+	select MFD_SYSCON
-+	help
-+	  This driver supports MTMIPS basic clocks.
---- a/drivers/clk/ralink/Makefile
-+++ b/drivers/clk/ralink/Makefile
-@@ -1,2 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
-+obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o
---- /dev/null
-+++ b/drivers/clk/ralink/clk-mtmips.c
-@@ -0,0 +1,1115 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MTMIPS SoCs Clock Driver
-+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/clk-provider.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset-controller.h>
-+#include <linux/slab.h>
-+
-+/* Configuration registers */
-+#define SYSC_REG_SYSTEM_CONFIG		0x10
-+#define SYSC_REG_CLKCFG0		0x2c
-+#define SYSC_REG_RESET_CTRL		0x34
-+#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
-+#define SYSC_REG_CPLL_CONFIG0		0x54
-+#define SYSC_REG_CPLL_CONFIG1		0x58
-+
-+/* RT2880 SoC */
-+#define RT2880_CONFIG_CPUCLK_SHIFT	20
-+#define RT2880_CONFIG_CPUCLK_MASK	0x3
-+#define RT2880_CONFIG_CPUCLK_250	0x0
-+#define RT2880_CONFIG_CPUCLK_266	0x1
-+#define RT2880_CONFIG_CPUCLK_280	0x2
-+#define RT2880_CONFIG_CPUCLK_300	0x3
-+
-+/* RT305X SoC */
-+#define RT305X_SYSCFG_CPUCLK_SHIFT	18
-+#define RT305X_SYSCFG_CPUCLK_MASK	0x1
-+#define RT305X_SYSCFG_CPUCLK_LOW	0x0
-+#define RT305X_SYSCFG_CPUCLK_HIGH	0x1
-+
-+/* RT3352 SoC */
-+#define RT3352_SYSCFG0_CPUCLK_SHIFT	8
-+#define RT3352_SYSCFG0_CPUCLK_MASK	0x1
-+#define RT3352_SYSCFG0_CPUCLK_LOW	0x0
-+#define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
-+
-+/* RT3383 SoC */
-+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2	BIT(17)
-+#define RT3883_SYSCFG0_CPUCLK_SHIFT	8
-+#define RT3883_SYSCFG0_CPUCLK_MASK	0x3
-+#define RT3883_SYSCFG0_CPUCLK_250	0x0
-+#define RT3883_SYSCFG0_CPUCLK_384	0x1
-+#define RT3883_SYSCFG0_CPUCLK_480	0x2
-+#define RT3883_SYSCFG0_CPUCLK_500	0x3
-+
-+/* RT5350 SoC */
-+#define RT5350_CLKCFG0_XTAL_SEL		BIT(20)
-+#define RT5350_SYSCFG0_CPUCLK_SHIFT	8
-+#define RT5350_SYSCFG0_CPUCLK_MASK	0x3
-+#define RT5350_SYSCFG0_CPUCLK_360	0x0
-+#define RT5350_SYSCFG0_CPUCLK_320	0x2
-+#define RT5350_SYSCFG0_CPUCLK_300	0x3
-+
-+/* MT7620 and MT76x8 SoCs */
-+#define MT7620_XTAL_FREQ_SEL		BIT(6)
-+#define CPLL_CFG0_SW_CFG		BIT(31)
-+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT	16
-+#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
-+#define CPLL_CFG0_LC_CURFCK		BIT(15)
-+#define CPLL_CFG0_BYPASS_REF_CLK	BIT(14)
-+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT	10
-+#define CPLL_CFG0_PLL_DIV_RATIO_MASK	0x3
-+#define CPLL_CFG1_CPU_AUX1		BIT(25)
-+#define CPLL_CFG1_CPU_AUX0		BIT(24)
-+#define CLKCFG0_PERI_CLK_SEL		BIT(4)
-+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT	16
-+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK	0xf
-+#define CPU_SYS_CLKCFG_OCP_RATIO_1	0	/* 1:1   (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5	1	/* 1:1.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_2	2	/* 1:2   */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5	3       /* 1:2.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_3	4	/* 1:3   */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5	5	/* 1:3.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_4	6	/* 1:4   */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_5	7	/* 1:5   */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_10	8	/* 1:10  */
-+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT	8
-+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK	0x1f
-+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT	0
-+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK	0x1f
-+
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK		0x1f00
-+#define CLKCFG_FDIV_USB_VAL		0x0300
-+#define CLKCFG_FFRAC_MASK		0x001f
-+#define CLKCFG_FFRAC_USB_VAL		0x0003
-+
-+struct mtmips_clk;
-+struct mtmips_clk_fixed;
-+struct mtmips_clk_factor;
-+
-+struct mtmips_clk_data {
-+	struct mtmips_clk *clk_base;
-+	size_t num_clk_base;
-+	struct mtmips_clk_fixed *clk_fixed;
-+	size_t num_clk_fixed;
-+	struct mtmips_clk_factor *clk_factor;
-+	size_t num_clk_factor;
-+	struct mtmips_clk *clk_periph;
-+	size_t num_clk_periph;
-+};
-+
-+struct mtmips_clk_priv {
-+	struct regmap *sysc;
-+	const struct mtmips_clk_data *data;
-+};
-+
-+struct mtmips_clk {
-+	struct clk_hw hw;
-+	struct mtmips_clk_priv *priv;
-+};
-+
-+struct mtmips_clk_fixed {
-+	const char *name;
-+	const char *parent;
-+	unsigned long rate;
-+	struct clk_hw *hw;
-+};
-+
-+struct mtmips_clk_factor {
-+	const char *name;
-+	const char *parent;
-+	int mult;
-+	int div;
-+	unsigned long flags;
-+	struct clk_hw *hw;
-+};
-+
-+static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	return parent_rate;
-+}
-+
-+static const struct clk_ops mtmips_periph_clk_ops = {
-+	.recalc_rate = mtmips_pherip_clk_rate,
-+};
-+
-+#define CLK_PERIPH(_name, _parent) {				\
-+	.init = &(const struct clk_init_data) {			\
-+		.name = _name,					\
-+		.ops = &mtmips_periph_clk_ops,			\
-+		.parent_data = &(const struct clk_parent_data) {\
-+			.name = _parent,			\
-+			.fw_name = _parent			\
-+		},						\
-+		.num_parents = 1,				\
-+		/*						\
-+		 * There are drivers for these SoCs that are	\
-+		 * older than clock driver and are not prepared \
-+		 * for the clock. We don't want the kernel to   \
-+		 * disable anything so we add CLK_IS_CRITICAL	\
-+		 * flag here.					\
-+		 */						\
-+		.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL	\
-+	},							\
-+}
-+
-+static struct mtmips_clk rt2880_pherip_clks[] = {
-+	{ CLK_PERIPH("300100.timer", "bus") },
-+	{ CLK_PERIPH("300120.watchdog", "bus") },
-+	{ CLK_PERIPH("300500.uart", "bus") },
-+	{ CLK_PERIPH("300900.i2c", "bus") },
-+	{ CLK_PERIPH("300c00.uartlite", "bus") },
-+	{ CLK_PERIPH("400000.ethernet", "bus") },
-+	{ CLK_PERIPH("480000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk rt305x_pherip_clks[] = {
-+	{ CLK_PERIPH("10000100.timer", "bus") },
-+	{ CLK_PERIPH("10000120.watchdog", "bus") },
-+	{ CLK_PERIPH("10000500.uart", "bus") },
-+	{ CLK_PERIPH("10000900.i2c", "bus") },
-+	{ CLK_PERIPH("10000a00.i2s", "bus") },
-+	{ CLK_PERIPH("10000b00.spi", "bus") },
-+	{ CLK_PERIPH("10000b40.spi", "bus") },
-+	{ CLK_PERIPH("10000c00.uartlite", "bus") },
-+	{ CLK_PERIPH("10100000.ethernet", "bus") },
-+	{ CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk rt5350_pherip_clks[] = {
-+	{ CLK_PERIPH("10000100.timer", "bus") },
-+	{ CLK_PERIPH("10000120.watchdog", "bus") },
-+	{ CLK_PERIPH("10000500.uart", "periph") },
-+	{ CLK_PERIPH("10000900.i2c", "periph") },
-+	{ CLK_PERIPH("10000a00.i2s", "periph") },
-+	{ CLK_PERIPH("10000b00.spi", "bus") },
-+	{ CLK_PERIPH("10000b40.spi", "bus") },
-+	{ CLK_PERIPH("10000c00.uartlite", "periph") },
-+	{ CLK_PERIPH("10100000.ethernet", "bus") },
-+	{ CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk mt7620_pherip_clks[] = {
-+	{ CLK_PERIPH("10000100.timer", "periph") },
-+	{ CLK_PERIPH("10000120.watchdog", "periph") },
-+	{ CLK_PERIPH("10000500.uart", "periph") },
-+	{ CLK_PERIPH("10000900.i2c", "periph") },
-+	{ CLK_PERIPH("10000a00.i2s", "periph") },
-+	{ CLK_PERIPH("10000b00.spi", "bus") },
-+	{ CLK_PERIPH("10000b40.spi", "bus") },
-+	{ CLK_PERIPH("10000c00.uartlite", "periph") },
-+	{ CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk mt76x8_pherip_clks[] = {
-+	{ CLK_PERIPH("10000100.timer", "periph") },
-+	{ CLK_PERIPH("10000120.watchdog", "periph") },
-+	{ CLK_PERIPH("10000900.i2c", "periph") },
-+	{ CLK_PERIPH("10000a00.i2s", "pcmi2s") },
-+	{ CLK_PERIPH("10000b00.spi", "bus") },
-+	{ CLK_PERIPH("10000b40.spi", "bus") },
-+	{ CLK_PERIPH("10000c00.uart0", "periph") },
-+	{ CLK_PERIPH("10000d00.uart1", "periph") },
-+	{ CLK_PERIPH("10000e00.uart2", "periph") },
-+	{ CLK_PERIPH("10300000.wmac", "xtal") }
-+};
-+
-+static int mtmips_register_pherip_clocks(struct device_node *np,
-+					 struct clk_hw_onecell_data *clk_data,
-+					 struct mtmips_clk_priv *priv)
-+{
-+	struct clk_hw **hws = clk_data->hws;
-+	struct mtmips_clk *sclk;
-+	size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
-+			   priv->data->num_clk_factor;
-+	int ret, i;
-+
-+	for (i = 0; i < priv->data->num_clk_periph; i++) {
-+		int idx = idx_start + i;
-+
-+		sclk = &priv->data->clk_periph[i];
-+		ret = of_clk_hw_register(np, &sclk->hw);
-+		if (ret) {
-+			pr_err("Couldn't register peripheral clock %d\n", idx);
-+			goto err_clk_unreg;
-+		}
-+
-+		hws[idx] = &sclk->hw;
-+	}
-+
-+	return 0;
-+
-+err_clk_unreg:
-+	while (--i >= 0) {
-+		sclk = &priv->data->clk_periph[i];
-+		clk_hw_unregister(&sclk->hw);
-+	}
-+	return ret;
-+}
-+
-+#define CLK_FIXED(_name, _parent, _rate) \
-+	{				 \
-+		.name = _name,		 \
-+		.parent = _parent,	 \
-+		.rate = _rate		 \
-+	}
-+
-+static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
-+	CLK_FIXED("xtal", NULL, 40000000)
-+};
-+
-+static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
-+	CLK_FIXED("periph", "xtal", 40000000)
-+};
-+
-+static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
-+	CLK_FIXED("pcmi2s", "xtal", 480000000),
-+	CLK_FIXED("periph", "xtal", 40000000)
-+};
-+
-+static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
-+					struct mtmips_clk_priv *priv)
-+{
-+	struct clk_hw **hws = clk_data->hws;
-+	struct mtmips_clk_fixed *sclk;
-+	size_t idx_start = priv->data->num_clk_base;
-+	int ret, i;
-+
-+	for (i = 0; i < priv->data->num_clk_fixed; i++) {
-+		int idx = idx_start + i;
-+
-+		sclk = &priv->data->clk_fixed[i];
-+		sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
-+						      sclk->parent, 0,
-+						      sclk->rate);
-+		if (IS_ERR(sclk->hw)) {
-+			pr_err("Couldn't register fixed clock %d\n", idx);
-+			goto err_clk_unreg;
-+		}
-+
-+		hws[idx] = sclk->hw;
-+	}
-+
-+	return 0;
-+
-+err_clk_unreg:
-+	while (--i >= 0) {
-+		sclk = &priv->data->clk_fixed[i];
-+		clk_hw_unregister_fixed_rate(sclk->hw);
-+	}
-+	return ret;
-+}
-+
-+#define CLK_FACTOR(_name, _parent, _mult, _div)		\
-+	{						\
-+		.name = _name,				\
-+		.parent = _parent,			\
-+		.mult = _mult,				\
-+		.div = _div,				\
-+		.flags = CLK_SET_RATE_PARENT		\
-+	}
-+
-+static struct mtmips_clk_factor rt2880_factor_clocks[] = {
-+	CLK_FACTOR("bus", "cpu", 1, 2)
-+};
-+
-+static struct mtmips_clk_factor rt305x_factor_clocks[] = {
-+	CLK_FACTOR("bus", "cpu", 1, 3)
-+};
-+
-+static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
-+					 struct mtmips_clk_priv *priv)
-+{
-+	struct clk_hw **hws = clk_data->hws;
-+	struct mtmips_clk_factor *sclk;
-+	size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
-+	int ret, i;
-+
-+	for (i = 0; i < priv->data->num_clk_factor; i++) {
-+		int idx = idx_start + i;
-+
-+		sclk = &priv->data->clk_factor[i];
-+		sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
-+						  sclk->parent, sclk->flags,
-+						  sclk->mult, sclk->div);
-+		if (IS_ERR(sclk->hw)) {
-+			pr_err("Couldn't register factor clock %d\n", idx);
-+			goto err_clk_unreg;
-+		}
-+
-+		hws[idx] = sclk->hw;
-+	}
-+
-+	return 0;
-+
-+err_clk_unreg:
-+	while (--i >= 0) {
-+		sclk = &priv->data->clk_factor[i];
-+		clk_hw_unregister_fixed_factor(sclk->hw);
-+	}
-+	return ret;
-+}
-+
-+static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
-+{
-+	return container_of(hw, struct mtmips_clk, hw);
-+}
-+
-+static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
-+					     unsigned long parent_rate)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 val;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
-+	if (!(val & RT5350_CLKCFG0_XTAL_SEL))
-+		return 20000000;
-+
-+	return 40000000;
-+}
-+
-+static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
-+
-+	switch (t) {
-+	case RT5350_SYSCFG0_CPUCLK_360:
-+		return 360000000;
-+	case RT5350_SYSCFG0_CPUCLK_320:
-+		return 320000000;
-+	case RT5350_SYSCFG0_CPUCLK_300:
-+		return 300000000;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	if (parent_rate == 320000000)
-+		return parent_rate / 4;
-+
-+	return parent_rate / 3;
-+}
-+
-+static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
-+
-+	switch (t) {
-+	case RT3352_SYSCFG0_CPUCLK_LOW:
-+		return 384000000;
-+	case RT3352_SYSCFG0_CPUCLK_HIGH:
-+		return 400000000;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
-+
-+	switch (t) {
-+	case RT305X_SYSCFG_CPUCLK_LOW:
-+		return 320000000;
-+	case RT305X_SYSCFG_CPUCLK_HIGH:
-+		return 384000000;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
-+
-+	switch (t) {
-+	case RT3883_SYSCFG0_CPUCLK_250:
-+		return 250000000;
-+	case RT3883_SYSCFG0_CPUCLK_384:
-+		return 384000000;
-+	case RT3883_SYSCFG0_CPUCLK_480:
-+		return 480000000;
-+	case RT3883_SYSCFG0_CPUCLK_500:
-+		return 500000000;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 ddr2;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
-+
-+	switch (parent_rate) {
-+	case 250000000:
-+		return (ddr2) ? 125000000 : 83000000;
-+	case 384000000:
-+		return (ddr2) ? 128000000 : 96000000;
-+	case 480000000:
-+		return (ddr2) ? 160000000 : 120000000;
-+	case 500000000:
-+		return (ddr2) ? 166000000 : 125000000;
-+	default:
-+		WARN_ON_ONCE(parent_rate == 0);
-+		return parent_rate / 4;
-+	}
-+}
-+
-+static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
-+
-+	switch (t) {
-+	case RT2880_CONFIG_CPUCLK_250:
-+		return 250000000;
-+	case RT2880_CONFIG_CPUCLK_266:
-+		return 266000000;
-+	case RT2880_CONFIG_CPUCLK_280:
-+		return 280000000;
-+	case RT2880_CONFIG_CPUCLK_300:
-+		return 300000000;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
-+{
-+	u64 t;
-+
-+	t = ref_rate;
-+	t *= mul;
-+	t = div_u64(t, div);
-+
-+	return t;
-+}
-+
-+static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	static const u32 clk_divider[] = { 2, 3, 4, 8 };
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	unsigned long cpu_pll;
-+	u32 t;
-+	u32 mul;
-+	u32 div;
-+
-+	regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
-+	if (t & CPLL_CFG0_BYPASS_REF_CLK) {
-+		cpu_pll = parent_rate;
-+	} else if ((t & CPLL_CFG0_SW_CFG) == 0) {
-+		cpu_pll = 600000000;
-+	} else {
-+		mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
-+			CPLL_CFG0_PLL_MULT_RATIO_MASK;
-+		mul += 24;
-+		if (t & CPLL_CFG0_LC_CURFCK)
-+			mul *= 2;
-+
-+		div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
-+			CPLL_CFG0_PLL_DIV_RATIO_MASK;
-+
-+		WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
-+
-+		cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
-+	}
-+
-+	regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
-+	if (t & CPLL_CFG1_CPU_AUX1)
-+		return parent_rate;
-+
-+	if (t & CPLL_CFG1_CPU_AUX0)
-+		return 480000000;
-+
-+	return cpu_pll;
-+}
-+
-+static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+	u32 mul;
-+	u32 div;
-+
-+	regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+	mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
-+	div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
-+		CPU_SYS_CLKCFG_CPU_FDIV_MASK;
-+
-+	return mt7620_calc_rate(parent_rate, mul, div);
-+}
-+
-+static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
-+					    unsigned long parent_rate)
-+{
-+	static const u32 ocp_dividers[16] = {
-+		[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
-+		[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
-+		[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
-+		[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
-+		[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
-+	};
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+	u32 ocp_ratio;
-+	u32 div;
-+
-+	regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+	ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
-+		CPU_SYS_CLKCFG_OCP_RATIO_MASK;
-+
-+	if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
-+		return parent_rate;
-+
-+	div = ocp_dividers[ocp_ratio];
-+
-+	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
-+		return parent_rate;
-+
-+	return parent_rate / div;
-+}
-+
-+static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
-+					       unsigned long parent_rate)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
-+	if (t & CLKCFG0_PERI_CLK_SEL)
-+		return parent_rate;
-+
-+	return 40000000;
-+}
-+
-+static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
-+					     unsigned long parent_rate)
-+{
-+	struct mtmips_clk *clk = to_mtmips_clk(hw);
-+	struct regmap *sysc = clk->priv->sysc;
-+	u32 t;
-+
-+	regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+	if (t & MT7620_XTAL_FREQ_SEL)
-+		return 40000000;
-+
-+	return 20000000;
-+}
-+
-+static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
-+					    unsigned long xtal_clk)
-+{
-+	if (xtal_clk == 40000000)
-+		return 580000000;
-+
-+	return 575000000;
-+}
-+
-+#define CLK_BASE(_name, _parent, _recalc) {				\
-+	.init = &(const struct clk_init_data) {				\
-+		.name = _name,						\
-+		.ops = &(const struct clk_ops) {			\
-+			.recalc_rate = _recalc,				\
-+		},							\
-+		.parent_data = &(const struct clk_parent_data) {	\
-+			.name = _parent,				\
-+			.fw_name = _parent				\
-+		},							\
-+		.num_parents = _parent ? 1 : 0				\
-+	},								\
-+}
-+
-+static struct mtmips_clk rt2880_clks_base[] = {
-+	{ CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt305x_clks_base[] = {
-+	{ CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt3352_clks_base[] = {
-+	{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
-+	{ CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt3883_clks_base[] = {
-+	{ CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
-+	{ CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt5350_clks_base[] = {
-+	{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
-+	{ CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
-+	{ CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk mt7620_clks_base[] = {
-+	{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
-+	{ CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
-+	{ CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
-+	{ CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
-+	{ CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk mt76x8_clks_base[] = {
-+	{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
-+	{ CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
-+};
-+
-+static int mtmips_register_clocks(struct device_node *np,
-+				  struct clk_hw_onecell_data *clk_data,
-+				  struct mtmips_clk_priv *priv)
-+{
-+	struct clk_hw **hws = clk_data->hws;
-+	struct mtmips_clk *sclk;
-+	int ret, i;
-+
-+	for (i = 0; i < priv->data->num_clk_base; i++) {
-+		sclk = &priv->data->clk_base[i];
-+		sclk->priv = priv;
-+		ret = of_clk_hw_register(np, &sclk->hw);
-+		if (ret) {
-+			pr_err("Couldn't register top clock %i\n", i);
-+			goto err_clk_unreg;
-+		}
-+
-+		hws[i] = &sclk->hw;
-+	}
-+
-+	return 0;
-+
-+err_clk_unreg:
-+	while (--i >= 0) {
-+		sclk = &priv->data->clk_base[i];
-+		clk_hw_unregister(&sclk->hw);
-+	}
-+	return ret;
-+}
-+
-+static const struct mtmips_clk_data rt2880_clk_data = {
-+	.clk_base = rt2880_clks_base,
-+	.num_clk_base = ARRAY_SIZE(rt2880_clks_base),
-+	.clk_fixed = rt305x_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+	.clk_factor = rt2880_factor_clocks,
-+	.num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
-+	.clk_periph = rt2880_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt305x_clk_data = {
-+	.clk_base = rt305x_clks_base,
-+	.num_clk_base = ARRAY_SIZE(rt305x_clks_base),
-+	.clk_fixed = rt305x_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+	.clk_factor = rt305x_factor_clocks,
-+	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+	.clk_periph = rt305x_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt3352_clk_data = {
-+	.clk_base = rt3352_clks_base,
-+	.num_clk_base = ARRAY_SIZE(rt3352_clks_base),
-+	.clk_fixed = rt3352_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
-+	.clk_factor = rt305x_factor_clocks,
-+	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+	.clk_periph = rt5350_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt3883_clk_data = {
-+	.clk_base = rt3883_clks_base,
-+	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
-+	.clk_fixed = rt305x_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+	.clk_factor = NULL,
-+	.num_clk_factor = 0,
-+	.clk_periph = rt5350_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt5350_clk_data = {
-+	.clk_base = rt5350_clks_base,
-+	.num_clk_base = ARRAY_SIZE(rt5350_clks_base),
-+	.clk_fixed = rt3352_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
-+	.clk_factor = NULL,
-+	.num_clk_factor = 0,
-+	.clk_periph = rt5350_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data mt7620_clk_data = {
-+	.clk_base = mt7620_clks_base,
-+	.num_clk_base = ARRAY_SIZE(mt7620_clks_base),
-+	.clk_fixed = NULL,
-+	.num_clk_fixed = 0,
-+	.clk_factor = NULL,
-+	.num_clk_factor = 0,
-+	.clk_periph = mt7620_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data mt76x8_clk_data = {
-+	.clk_base = mt76x8_clks_base,
-+	.num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
-+	.clk_fixed = mt76x8_fixed_clocks,
-+	.num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
-+	.clk_factor = rt305x_factor_clocks,
-+	.num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+	.clk_periph = mt76x8_pherip_clks,
-+	.num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
-+};
-+
-+static const struct of_device_id mtmips_of_match[] = {
-+	{
-+		.compatible = "ralink,rt2880-sysc",
-+		.data = &rt2880_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,rt3050-sysc",
-+		.data = &rt305x_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,rt3052-sysc",
-+		.data = &rt305x_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,rt3352-sysc",
-+		.data = &rt3352_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,rt3883-sysc",
-+		.data = &rt3883_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,rt5350-sysc",
-+		.data = &rt5350_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,mt7620-sysc",
-+		.data = &mt7620_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,mt7628-sysc",
-+		.data = &mt76x8_clk_data,
-+	},
-+	{
-+		.compatible = "ralink,mt7688-sysc",
-+		.data = &mt76x8_clk_data,
-+	},
-+	{}
-+};
-+
-+static void __init mtmips_clk_regs_init(struct device_node *node,
-+					struct mtmips_clk_priv *priv)
-+{
-+	u32 t;
-+
-+	if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
-+		return;
-+
-+	/*
-+	 * When the CPU goes into sleep mode, the BUS
-+	 * clock will be too low for USB to function properly.
-+	 * Adjust the busses fractional divider to fix this
-+	 */
-+	regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+	t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+	t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+	regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
-+}
-+
-+static void __init mtmips_clk_init(struct device_node *node)
-+{
-+	const struct of_device_id *match;
-+	const struct mtmips_clk_data *data;
-+	struct mtmips_clk_priv *priv;
-+	struct clk_hw_onecell_data *clk_data;
-+	int ret, i, count;
-+
-+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return;
-+
-+	priv->sysc = syscon_node_to_regmap(node);
-+	if (IS_ERR(priv->sysc)) {
-+		pr_err("Could not get sysc syscon regmap\n");
-+		goto free_clk_priv;
-+	}
-+
-+	mtmips_clk_regs_init(node, priv);
-+
-+	match = of_match_node(mtmips_of_match, node);
-+	if (WARN_ON(!match))
-+		return;
-+
-+	data = match->data;
-+	priv->data = data;
-+	count = priv->data->num_clk_base + priv->data->num_clk_fixed +
-+		priv->data->num_clk_factor + priv->data->num_clk_periph;
-+	clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
-+	if (!clk_data)
-+		goto free_clk_priv;
-+
-+	ret = mtmips_register_clocks(node, clk_data, priv);
-+	if (ret) {
-+		pr_err("Couldn't register top clocks\n");
-+		goto free_clk_data;
-+	}
-+
-+	ret = mtmips_register_fixed_clocks(clk_data, priv);
-+	if (ret) {
-+		pr_err("Couldn't register fixed clocks\n");
-+		goto unreg_clk_top;
-+	}
-+
-+	ret = mtmips_register_factor_clocks(clk_data, priv);
-+	if (ret) {
-+		pr_err("Couldn't register factor clocks\n");
-+		goto unreg_clk_fixed;
-+	}
-+
-+	ret = mtmips_register_pherip_clocks(node, clk_data, priv);
-+	if (ret) {
-+		pr_err("Couldn't register peripheral clocks\n");
-+		goto unreg_clk_factor;
-+	}
-+
-+	clk_data->num = count;
-+
-+	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+	if (ret) {
-+		pr_err("Couldn't add clk hw provider\n");
-+		goto unreg_clk_periph;
-+	}
-+
-+	return;
-+
-+unreg_clk_periph:
-+	for (i = 0; i < priv->data->num_clk_periph; i++) {
-+		struct mtmips_clk *sclk = &priv->data->clk_periph[i];
-+
-+		clk_hw_unregister(&sclk->hw);
-+	}
-+
-+unreg_clk_factor:
-+	for (i = 0; i < priv->data->num_clk_factor; i++) {
-+		struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
-+
-+		clk_hw_unregister_fixed_factor(sclk->hw);
-+	}
-+
-+unreg_clk_fixed:
-+	for (i = 0; i < priv->data->num_clk_fixed; i++) {
-+		struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
-+
-+		clk_hw_unregister_fixed_rate(sclk->hw);
-+	}
-+
-+unreg_clk_top:
-+	for (i = 0; i < priv->data->num_clk_base; i++) {
-+		struct mtmips_clk *sclk = &priv->data->clk_base[i];
-+
-+		clk_hw_unregister(&sclk->hw);
-+	}
-+
-+free_clk_data:
-+	kfree(clk_data);
-+
-+free_clk_priv:
-+	kfree(priv);
-+}
-+CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
-+
-+struct mtmips_rst {
-+	struct reset_controller_dev rcdev;
-+	struct regmap *sysc;
-+};
-+
-+static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
-+{
-+	return container_of(dev, struct mtmips_rst, rcdev);
-+}
-+
-+static int mtmips_assert_device(struct reset_controller_dev *rcdev,
-+				unsigned long id)
-+{
-+	struct mtmips_rst *data = to_mtmips_rst(rcdev);
-+	struct regmap *sysc = data->sysc;
-+
-+	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
-+}
-+
-+static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
-+				  unsigned long id)
-+{
-+	struct mtmips_rst *data = to_mtmips_rst(rcdev);
-+	struct regmap *sysc = data->sysc;
-+
-+	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
-+}
-+
-+static int mtmips_reset_device(struct reset_controller_dev *rcdev,
-+			       unsigned long id)
-+{
-+	int ret;
-+
-+	ret = mtmips_assert_device(rcdev, id);
-+	if (ret < 0)
-+		return ret;
-+
-+	return mtmips_deassert_device(rcdev, id);
-+}
-+
-+static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
-+			    const struct of_phandle_args *reset_spec)
-+{
-+	unsigned long id = reset_spec->args[0];
-+
-+	if (id == 0 || id >= rcdev->nr_resets)
-+		return -EINVAL;
-+
-+	return id;
-+}
-+
-+static const struct reset_control_ops reset_ops = {
-+	.reset = mtmips_reset_device,
-+	.assert = mtmips_assert_device,
-+	.deassert = mtmips_deassert_device
-+};
-+
-+static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
-+{
-+	struct mtmips_rst *rst_data;
-+
-+	rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
-+	if (!rst_data)
-+		return -ENOMEM;
-+
-+	rst_data->sysc = sysc;
-+	rst_data->rcdev.ops = &reset_ops;
-+	rst_data->rcdev.owner = THIS_MODULE;
-+	rst_data->rcdev.nr_resets = 32;
-+	rst_data->rcdev.of_reset_n_cells = 1;
-+	rst_data->rcdev.of_xlate = mtmips_rst_xlate;
-+	rst_data->rcdev.of_node = dev_of_node(dev);
-+
-+	return devm_reset_controller_register(dev, &rst_data->rcdev);
-+}
-+
-+static int mtmips_clk_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device *dev = &pdev->dev;
-+	struct mtmips_clk_priv *priv;
-+	int ret;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->sysc = syscon_node_to_regmap(np);
-+	if (IS_ERR(priv->sysc))
-+		return dev_err_probe(dev, PTR_ERR(priv->sysc),
-+				     "Could not get sysc syscon regmap\n");
-+
-+	ret = mtmips_reset_init(dev, priv->sysc);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Could not init reset controller\n");
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id mtmips_clk_of_match[] = {
-+	{ .compatible = "ralink,rt2880-reset" },
-+	{ .compatible = "ralink,rt2880-sysc" },
-+	{ .compatible = "ralink,rt3050-sysc" },
-+	{ .compatible = "ralink,rt3052-sysc" },
-+	{ .compatible = "ralink,rt3352-sysc" },
-+	{ .compatible = "ralink,rt3883-sysc" },
-+	{ .compatible = "ralink,rt5350-sysc" },
-+	{ .compatible = "ralink,mt7620-sysc" },
-+	{ .compatible = "ralink,mt7628-sysc" },
-+	{ .compatible = "ralink,mt7688-sysc" },
-+	{}
-+};
-+
-+static struct platform_driver mtmips_clk_driver = {
-+	.probe = mtmips_clk_probe,
-+	.driver = {
-+		.name = "mtmips-clk",
-+		.of_match_table = mtmips_clk_of_match,
-+	},
-+};
-+
-+static int __init mtmips_clk_reset_init(void)
-+{
-+	return platform_driver_register(&mtmips_clk_driver);
-+}
-+arch_initcall(mtmips_clk_reset_init);
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
deleted file mode 100644
index df4208b23d..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:35 +0200
-Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
- arch/mips/ralink/rt288x.c                  | 31 ------------------------------
- 2 files changed, 41 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt288x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
-@@ -17,7 +17,6 @@
- #define SYSC_REG_CHIP_NAME1		0x04
- #define SYSC_REG_CHIP_ID		0x0c
- #define SYSC_REG_SYSTEM_CONFIG		0x10
--#define SYSC_REG_CLKCFG			0x30
- 
- #define RT2880_CHIP_NAME0		0x38325452
- #define RT2880_CHIP_NAME1		0x20203038
-@@ -26,15 +25,6 @@
- #define CHIP_ID_ID_SHIFT		8
- #define CHIP_ID_REV_MASK		0xff
- 
--#define SYSTEM_CONFIG_CPUCLK_SHIFT	20
--#define SYSTEM_CONFIG_CPUCLK_MASK	0x3
--#define SYSTEM_CONFIG_CPUCLK_250	0x0
--#define SYSTEM_CONFIG_CPUCLK_266	0x1
--#define SYSTEM_CONFIG_CPUCLK_280	0x2
--#define SYSTEM_CONFIG_CPUCLK_300	0x3
--
--#define CLKCFG_SRAM_CS_N_WDT		BIT(9)
--
- #define RT2880_SDRAM_BASE		0x08000000
- #define RT2880_MEM_SIZE_MIN		2
- #define RT2880_MEM_SIZE_MAX		128
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,37 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_clk_init(void)
--{
--	unsigned long cpu_rate, wmac_rate = 40000000;
--	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
--	t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
--
--	switch (t) {
--	case SYSTEM_CONFIG_CPUCLK_250:
--		cpu_rate = 250000000;
--		break;
--	case SYSTEM_CONFIG_CPUCLK_266:
--		cpu_rate = 266666667;
--		break;
--	case SYSTEM_CONFIG_CPUCLK_280:
--		cpu_rate = 280000000;
--		break;
--	case SYSTEM_CONFIG_CPUCLK_300:
--		cpu_rate = 300000000;
--		break;
--	}
--
--	ralink_clk_add("cpu", cpu_rate);
--	ralink_clk_add("300100.timer", cpu_rate / 2);
--	ralink_clk_add("300120.watchdog", cpu_rate / 2);
--	ralink_clk_add("300500.uart", cpu_rate / 2);
--	ralink_clk_add("300900.i2c", cpu_rate / 2);
--	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
--	ralink_clk_add("400000.ethernet", cpu_rate / 2);
--	ralink_clk_add("480000.wmac", wmac_rate);
--}
--
- void __init ralink_of_remap(void)
- {
- 	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch
deleted file mode 100644
index 12b4623b73..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:36 +0200
-Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
- arch/mips/ralink/rt305x.c                  | 78 ------------------------------
- 2 files changed, 99 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
- #define CHIP_ID_ID_SHIFT		8
- #define CHIP_ID_REV_MASK		0xff
- 
--#define RT305X_SYSCFG_CPUCLK_SHIFT		18
--#define RT305X_SYSCFG_CPUCLK_MASK		0x1
--#define RT305X_SYSCFG_CPUCLK_LOW		0x0
--#define RT305X_SYSCFG_CPUCLK_HIGH		0x1
--
- #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT	2
--#define RT305X_SYSCFG_CPUCLK_MASK		0x1
- #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT		0x1
- 
--#define RT3352_SYSCFG0_CPUCLK_SHIFT	8
--#define RT3352_SYSCFG0_CPUCLK_MASK	0x1
--#define RT3352_SYSCFG0_CPUCLK_LOW	0x0
--#define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
--
--#define RT5350_SYSCFG0_CPUCLK_SHIFT	8
--#define RT5350_SYSCFG0_CPUCLK_MASK	0x3
--#define RT5350_SYSCFG0_CPUCLK_360	0x0
--#define RT5350_SYSCFG0_CPUCLK_320	0x2
--#define RT5350_SYSCFG0_CPUCLK_300	0x3
--
- #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
- #define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
- #define RT5350_SYSCFG0_DRAM_SIZE_2M     0
-@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
- 
- #define RT3352_SYSC_REG_SYSCFG0		0x010
- #define RT3352_SYSC_REG_SYSCFG1         0x014
--#define RT3352_SYSC_REG_CLKCFG1         0x030
- #define RT3352_SYSC_REG_RSTCTRL         0x034
- #define RT3352_SYSC_REG_USB_PS          0x05c
- 
--#define RT3352_CLKCFG0_XTAL_SEL		BIT(20)
--#define RT3352_CLKCFG1_UPHY0_CLK_EN	BIT(18)
--#define RT3352_CLKCFG1_UPHY1_CLK_EN	BIT(20)
- #define RT3352_RSTCTRL_UHST		BIT(22)
- #define RT3352_RSTCTRL_UDEV		BIT(25)
- #define RT3352_SYSCFG1_USB0_HOST_MODE	BIT(10)
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
- 	return ret;
- }
- 
--void __init ralink_clk_init(void)
--{
--	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
--	unsigned long wmac_rate = 40000000;
--
--	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
--
--	if (soc_is_rt305x() || soc_is_rt3350()) {
--		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
--		     RT305X_SYSCFG_CPUCLK_MASK;
--		switch (t) {
--		case RT305X_SYSCFG_CPUCLK_LOW:
--			cpu_rate = 320000000;
--			break;
--		case RT305X_SYSCFG_CPUCLK_HIGH:
--			cpu_rate = 384000000;
--			break;
--		}
--		sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
--	} else if (soc_is_rt3352()) {
--		t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
--		     RT3352_SYSCFG0_CPUCLK_MASK;
--		switch (t) {
--		case RT3352_SYSCFG0_CPUCLK_LOW:
--			cpu_rate = 384000000;
--			break;
--		case RT3352_SYSCFG0_CPUCLK_HIGH:
--			cpu_rate = 400000000;
--			break;
--		}
--		sys_rate = wdt_rate = cpu_rate / 3;
--		uart_rate = 40000000;
--	} else if (soc_is_rt5350()) {
--		t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
--		     RT5350_SYSCFG0_CPUCLK_MASK;
--		switch (t) {
--		case RT5350_SYSCFG0_CPUCLK_360:
--			cpu_rate = 360000000;
--			sys_rate = cpu_rate / 3;
--			break;
--		case RT5350_SYSCFG0_CPUCLK_320:
--			cpu_rate = 320000000;
--			sys_rate = cpu_rate / 4;
--			break;
--		case RT5350_SYSCFG0_CPUCLK_300:
--			cpu_rate = 300000000;
--			sys_rate = cpu_rate / 3;
--			break;
--		default:
--			BUG();
--		}
--		uart_rate = 40000000;
--		wdt_rate = sys_rate;
--	} else {
--		BUG();
--	}
--
--	if (soc_is_rt3352() || soc_is_rt5350()) {
--		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
--
--		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
--			wmac_rate = 20000000;
--	}
--
--	ralink_clk_add("cpu", cpu_rate);
--	ralink_clk_add("sys", sys_rate);
--	ralink_clk_add("10000900.i2c", uart_rate);
--	ralink_clk_add("10000a00.i2s", uart_rate);
--	ralink_clk_add("10000b00.spi", sys_rate);
--	ralink_clk_add("10000b40.spi", sys_rate);
--	ralink_clk_add("10000100.timer", wdt_rate);
--	ralink_clk_add("10000120.watchdog", wdt_rate);
--	ralink_clk_add("10000500.uart", uart_rate);
--	ralink_clk_add("10000c00.uartlite", uart_rate);
--	ralink_clk_add("10100000.ethernet", sys_rate);
--	ralink_clk_add("10180000.wmac", wmac_rate);
--}
--
- void __init ralink_of_remap(void)
- {
- 	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
deleted file mode 100644
index c13c4215f3..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:37 +0200
-Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt3883.h |  8 ------
- arch/mips/ralink/rt3883.c                  | 44 ------------------------------
- 2 files changed, 52 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -90,14 +90,6 @@
- #define RT3883_REVID_VER_ID_SHIFT	8
- #define RT3883_REVID_ECO_ID_MASK	0x0f
- 
--#define RT3883_SYSCFG0_DRAM_TYPE_DDR2	BIT(17)
--#define RT3883_SYSCFG0_CPUCLK_SHIFT	8
--#define RT3883_SYSCFG0_CPUCLK_MASK	0x3
--#define RT3883_SYSCFG0_CPUCLK_250	0x0
--#define RT3883_SYSCFG0_CPUCLK_384	0x1
--#define RT3883_SYSCFG0_CPUCLK_480	0x2
--#define RT3883_SYSCFG0_CPUCLK_500	0x3
--
- #define RT3883_SYSCFG1_USB0_HOST_MODE	BIT(10)
- #define RT3883_SYSCFG1_PCIE_RC_MODE	BIT(8)
- #define RT3883_SYSCFG1_PCI_HOST_MODE	BIT(7)
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,50 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_clk_init(void)
--{
--	unsigned long cpu_rate, sys_rate;
--	u32 syscfg0;
--	u32 clksel;
--	u32 ddr2;
--
--	syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
--	clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
--		RT3883_SYSCFG0_CPUCLK_MASK);
--	ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
--
--	switch (clksel) {
--	case RT3883_SYSCFG0_CPUCLK_250:
--		cpu_rate = 250000000;
--		sys_rate = (ddr2) ? 125000000 : 83000000;
--		break;
--	case RT3883_SYSCFG0_CPUCLK_384:
--		cpu_rate = 384000000;
--		sys_rate = (ddr2) ? 128000000 : 96000000;
--		break;
--	case RT3883_SYSCFG0_CPUCLK_480:
--		cpu_rate = 480000000;
--		sys_rate = (ddr2) ? 160000000 : 120000000;
--		break;
--	case RT3883_SYSCFG0_CPUCLK_500:
--		cpu_rate = 500000000;
--		sys_rate = (ddr2) ? 166000000 : 125000000;
--		break;
--	}
--
--	ralink_clk_add("cpu", cpu_rate);
--	ralink_clk_add("10000100.timer", sys_rate);
--	ralink_clk_add("10000120.watchdog", sys_rate);
--	ralink_clk_add("10000500.uart", 40000000);
--	ralink_clk_add("10000900.i2c", 40000000);
--	ralink_clk_add("10000a00.i2s", 40000000);
--	ralink_clk_add("10000b00.spi", sys_rate);
--	ralink_clk_add("10000b40.spi", sys_rate);
--	ralink_clk_add("10000c00.uartlite", 40000000);
--	ralink_clk_add("10100000.ethernet", sys_rate);
--	ralink_clk_add("10180000.wmac", 40000000);
--}
--
- void __init ralink_of_remap(void)
- {
- 	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch
deleted file mode 100644
index 7b83cf54b4..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch
+++ /dev/null
@@ -1,327 +0,0 @@
-From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:38 +0200
-Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code
-
-A proper clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-Since this is the last clock related code removal, remove also remaining
-prototypes in 'common.h' header file.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/mt7620.h |  35 -----
- arch/mips/ralink/common.h                  |   3 -
- arch/mips/ralink/mt7620.c                  | 226 -----------------------------
- 3 files changed, 264 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -19,52 +19,17 @@
- #define SYSC_REG_CHIP_REV		0x0c
- #define SYSC_REG_SYSTEM_CONFIG0		0x10
- #define SYSC_REG_SYSTEM_CONFIG1		0x14
--#define SYSC_REG_CLKCFG0		0x2c
--#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
--#define SYSC_REG_CPLL_CONFIG0		0x54
--#define SYSC_REG_CPLL_CONFIG1		0x58
- 
- #define MT7620_CHIP_NAME0		0x3637544d
- #define MT7620_CHIP_NAME1		0x20203032
- #define MT7628_CHIP_NAME1		0x20203832
- 
--#define SYSCFG0_XTAL_FREQ_SEL		BIT(6)
--
- #define CHIP_REV_PKG_MASK		0x1
- #define CHIP_REV_PKG_SHIFT		16
- #define CHIP_REV_VER_MASK		0xf
- #define CHIP_REV_VER_SHIFT		8
- #define CHIP_REV_ECO_MASK		0xf
- 
--#define CLKCFG0_PERI_CLK_SEL		BIT(4)
--
--#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT	16
--#define CPU_SYS_CLKCFG_OCP_RATIO_MASK	0xf
--#define CPU_SYS_CLKCFG_OCP_RATIO_1	0	/* 1:1   (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_1_5	1	/* 1:1.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_2	2	/* 1:2   */
--#define CPU_SYS_CLKCFG_OCP_RATIO_2_5	3       /* 1:2.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_3	4	/* 1:3   */
--#define CPU_SYS_CLKCFG_OCP_RATIO_3_5	5	/* 1:3.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_4	6	/* 1:4   */
--#define CPU_SYS_CLKCFG_OCP_RATIO_5	7	/* 1:5   */
--#define CPU_SYS_CLKCFG_OCP_RATIO_10	8	/* 1:10  */
--#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT	8
--#define CPU_SYS_CLKCFG_CPU_FDIV_MASK	0x1f
--#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT	0
--#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK	0x1f
--
--#define CPLL_CFG0_SW_CFG		BIT(31)
--#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT	16
--#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
--#define CPLL_CFG0_LC_CURFCK		BIT(15)
--#define CPLL_CFG0_BYPASS_REF_CLK	BIT(14)
--#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT	10
--#define CPLL_CFG0_PLL_DIV_RATIO_MASK	0x3
--
--#define CPLL_CFG1_CPU_AUX1		BIT(25)
--#define CPLL_CFG1_CPU_AUX0		BIT(24)
--
- #define SYSCFG0_DRAM_TYPE_MASK		0x3
- #define SYSCFG0_DRAM_TYPE_SHIFT		4
- #define SYSCFG0_DRAM_TYPE_SDRAM		0
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
- 
- extern void ralink_of_remap(void);
- 
--extern void ralink_clk_init(void);
--extern void ralink_clk_add(const char *dev, unsigned long rate);
--
- extern void ralink_rst_init(void);
- 
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -34,12 +34,6 @@
- #define PMU1_CFG		0x8C
- #define DIG_SW_SEL		BIT(25)
- 
--/* clock scaling */
--#define CLKCFG_FDIV_MASK	0x1f00
--#define CLKCFG_FDIV_USB_VAL	0x0300
--#define CLKCFG_FFRAC_MASK	0x001f
--#define CLKCFG_FFRAC_USB_VAL	0x0003
--
- /* EFUSE bits */
- #define EFUSE_MT7688		0x100000
- 
-@@ -49,226 +43,6 @@
- /* does the board have sdram or ddram */
- static int dram_type;
- 
--static __init u32
--mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
--{
--	u64 t;
--
--	t = ref_rate;
--	t *= mul;
--	do_div(t, div);
--
--	return t;
--}
--
--#define MHZ(x)		((x) * 1000 * 1000)
--
--static __init unsigned long
--mt7620_get_xtal_rate(void)
--{
--	u32 reg;
--
--	reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
--	if (reg & SYSCFG0_XTAL_FREQ_SEL)
--		return MHZ(40);
--
--	return MHZ(20);
--}
--
--static __init unsigned long
--mt7620_get_periph_rate(unsigned long xtal_rate)
--{
--	u32 reg;
--
--	reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
--	if (reg & CLKCFG0_PERI_CLK_SEL)
--		return xtal_rate;
--
--	return MHZ(40);
--}
--
--static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
--
--static __init unsigned long
--mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
--{
--	u32 reg;
--	u32 mul;
--	u32 div;
--
--	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
--	if (reg & CPLL_CFG0_BYPASS_REF_CLK)
--		return xtal_rate;
--
--	if ((reg & CPLL_CFG0_SW_CFG) == 0)
--		return MHZ(600);
--
--	mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
--	      CPLL_CFG0_PLL_MULT_RATIO_MASK;
--	mul += 24;
--	if (reg & CPLL_CFG0_LC_CURFCK)
--		mul *= 2;
--
--	div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
--	      CPLL_CFG0_PLL_DIV_RATIO_MASK;
--
--	WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
--
--	return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
--}
--
--static __init unsigned long
--mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
--{
--	u32 reg;
--
--	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
--	if (reg & CPLL_CFG1_CPU_AUX1)
--		return xtal_rate;
--
--	if (reg & CPLL_CFG1_CPU_AUX0)
--		return MHZ(480);
--
--	return cpu_pll_rate;
--}
--
--static __init unsigned long
--mt7620_get_cpu_rate(unsigned long pll_rate)
--{
--	u32 reg;
--	u32 mul;
--	u32 div;
--
--	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
--	mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
--	div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
--	      CPU_SYS_CLKCFG_CPU_FDIV_MASK;
--
--	return mt7620_calc_rate(pll_rate, mul, div);
--}
--
--static const u32 mt7620_ocp_dividers[16] __initconst = {
--	[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
--	[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
--	[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
--	[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
--	[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
--};
--
--static __init unsigned long
--mt7620_get_dram_rate(unsigned long pll_rate)
--{
--	if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
--		return pll_rate / 4;
--
--	return pll_rate / 3;
--}
--
--static __init unsigned long
--mt7620_get_sys_rate(unsigned long cpu_rate)
--{
--	u32 reg;
--	u32 ocp_ratio;
--	u32 div;
--
--	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
--	ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
--		    CPU_SYS_CLKCFG_OCP_RATIO_MASK;
--
--	if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
--		return cpu_rate;
--
--	div = mt7620_ocp_dividers[ocp_ratio];
--	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
--		return cpu_rate;
--
--	return cpu_rate / div;
--}
--
--void __init ralink_clk_init(void)
--{
--	unsigned long xtal_rate;
--	unsigned long cpu_pll_rate;
--	unsigned long pll_rate;
--	unsigned long cpu_rate;
--	unsigned long sys_rate;
--	unsigned long dram_rate;
--	unsigned long periph_rate;
--	unsigned long pcmi2s_rate;
--
--	xtal_rate = mt7620_get_xtal_rate();
--
--#define RFMT(label)	label ":%lu.%03luMHz "
--#define RINT(x)		((x) / 1000000)
--#define RFRAC(x)	(((x) / 1000) % 1000)
--
--	if (is_mt76x8()) {
--		if (xtal_rate == MHZ(40))
--			cpu_rate = MHZ(580);
--		else
--			cpu_rate = MHZ(575);
--		dram_rate = sys_rate = cpu_rate / 3;
--		periph_rate = MHZ(40);
--		pcmi2s_rate = MHZ(480);
--
--		ralink_clk_add("10000d00.uartlite", periph_rate);
--		ralink_clk_add("10000e00.uartlite", periph_rate);
--	} else {
--		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
--		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
--
--		cpu_rate = mt7620_get_cpu_rate(pll_rate);
--		dram_rate = mt7620_get_dram_rate(pll_rate);
--		sys_rate = mt7620_get_sys_rate(cpu_rate);
--		periph_rate = mt7620_get_periph_rate(xtal_rate);
--		pcmi2s_rate = periph_rate;
--
--		pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
--			 RINT(xtal_rate), RFRAC(xtal_rate),
--			 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
--			 RINT(pll_rate), RFRAC(pll_rate));
--
--		ralink_clk_add("10000500.uart", periph_rate);
--	}
--
--	pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
--		 RINT(cpu_rate), RFRAC(cpu_rate),
--		 RINT(dram_rate), RFRAC(dram_rate),
--		 RINT(sys_rate), RFRAC(sys_rate),
--		 RINT(periph_rate), RFRAC(periph_rate));
--#undef RFRAC
--#undef RINT
--#undef RFMT
--
--	ralink_clk_add("cpu", cpu_rate);
--	ralink_clk_add("10000100.timer", periph_rate);
--	ralink_clk_add("10000120.watchdog", periph_rate);
--	ralink_clk_add("10000900.i2c", periph_rate);
--	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
--	ralink_clk_add("10000b00.spi", sys_rate);
--	ralink_clk_add("10000b40.spi", sys_rate);
--	ralink_clk_add("10000c00.uartlite", periph_rate);
--	ralink_clk_add("10000d00.uart1", periph_rate);
--	ralink_clk_add("10000e00.uart2", periph_rate);
--	ralink_clk_add("10180000.wmac", xtal_rate);
--
--	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
--		/*
--		 * When the CPU goes into sleep mode, the BUS clock will be
--		 * too low for USB to function properly. Adjust the busses
--		 * fractional divider to fix this
--		 */
--		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
--		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
--		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
--
--		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
--	}
--}
--
- void __init ralink_of_remap(void)
- {
- 	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch
deleted file mode 100644
index e96a9084a6..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:39 +0200
-Subject: [PATCH 7/9] mips: ralink: remove reset related code
-
-A proper clock driver for ralink SoCs has been added. This driver is also
-a reset provider for the SoC. Hence there is no need to have reset related
-code in 'arch/mips/ralink' folder anymore. The only code that remains is
-the one related with mips_reboot_setup where a PCI reset is performed.
-We maintain this because I cannot test old ralink board with PCI to be
-sure all works if we remove also this code.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/common.h |  2 --
- arch/mips/ralink/of.c     |  4 ----
- arch/mips/ralink/reset.c  | 61 -----------------------------------------------
- 3 files changed, 67 deletions(-)
-
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info;
- 
- extern void ralink_of_remap(void);
- 
--extern void ralink_rst_init(void);
--
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
- 
- __iomem void *plat_of_remap_node(const char *node);
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -81,10 +81,6 @@ static int __init plat_of_setup(void)
- {
- 	__dt_register_buses(soc_info.compatible, "palmbus");
- 
--	/* make sure that the reset controller is setup early */
--	if (ralink_soc != MT762X_SOC_MT7621AT)
--		ralink_rst_init();
--
- 	return 0;
- }
- 
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -10,7 +10,6 @@
- #include <linux/io.h>
- #include <linux/of.h>
- #include <linux/delay.h>
--#include <linux/reset-controller.h>
- 
- #include <asm/reboot.h>
- 
-@@ -22,66 +21,6 @@
- #define RSTCTL_RESET_PCI	BIT(26)
- #define RSTCTL_RESET_SYSTEM	BIT(0)
- 
--static int ralink_assert_device(struct reset_controller_dev *rcdev,
--				unsigned long id)
--{
--	u32 val;
--
--	if (id == 0)
--		return -1;
--
--	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
--	val |= BIT(id);
--	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
--
--	return 0;
--}
--
--static int ralink_deassert_device(struct reset_controller_dev *rcdev,
--				  unsigned long id)
--{
--	u32 val;
--
--	if (id == 0)
--		return -1;
--
--	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
--	val &= ~BIT(id);
--	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
--
--	return 0;
--}
--
--static int ralink_reset_device(struct reset_controller_dev *rcdev,
--			       unsigned long id)
--{
--	ralink_assert_device(rcdev, id);
--	return ralink_deassert_device(rcdev, id);
--}
--
--static const struct reset_control_ops reset_ops = {
--	.reset = ralink_reset_device,
--	.assert = ralink_assert_device,
--	.deassert = ralink_deassert_device,
--};
--
--static struct reset_controller_dev reset_dev = {
--	.ops			= &reset_ops,
--	.owner			= THIS_MODULE,
--	.nr_resets		= 32,
--	.of_reset_n_cells	= 1,
--};
--
--void ralink_rst_init(void)
--{
--	reset_dev.of_node = of_find_compatible_node(NULL, NULL,
--						"ralink,rt2880-reset");
--	if (!reset_dev.of_node)
--		pr_err("Failed to find reset controller node");
--	else
--		reset_controller_register(&reset_dev);
--}
--
- static void ralink_restart(char *command)
- {
- 	if (IS_ENABLED(CONFIG_PCI)) {
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
deleted file mode 100644
index 2430c1f375..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:40 +0200
-Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
-
-At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
-This timer frequency is a half of the CPU frequency. To get clocks properly
-set we need to call to 'of_clk_init()' and properly get cpu clock frequency
-afterwards. Depending on the SoC, CPU clock index and compatible differs, so
-use them to get the proper clock frm the clock provider. Hence, adapt code
-to be aligned with new clock driver.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
- 1 file changed, 52 insertions(+), 9 deletions(-)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -11,29 +11,72 @@
- #include <linux/clkdev.h>
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
-+#include <asm/mach-ralink/ralink_regs.h>
- 
- #include <asm/time.h>
- 
- #include "common.h"
- 
--void ralink_clk_add(const char *dev, unsigned long rate)
-+static const char *clk_cpu(int *idx)
- {
--	struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
--
--	if (!clk)
--		panic("failed to add clock");
--
--	clkdev_create(clk, NULL, "%s", dev);
-+	switch (ralink_soc) {
-+	case RT2880_SOC:
-+		*idx = 0;
-+		return "ralink,rt2880-sysc";
-+	case RT3883_SOC:
-+		*idx = 0;
-+		return "ralink,rt3883-sysc";
-+	case RT305X_SOC_RT3050:
-+		*idx = 0;
-+		return "ralink,rt3050-sysc";
-+	case RT305X_SOC_RT3052:
-+		*idx = 0;
-+		return "ralink,rt3052-sysc";
-+	case RT305X_SOC_RT3350:
-+		*idx = 1;
-+		return "ralink,rt3350-sysc";
-+	case RT305X_SOC_RT3352:
-+		*idx = 1;
-+		return "ralink,rt3352-sysc";
-+	case RT305X_SOC_RT5350:
-+		*idx = 1;
-+		return "ralink,rt5350-sysc";
-+	case MT762X_SOC_MT7620A:
-+		*idx = 2;
-+		return "ralink,mt7620-sysc";
-+	case MT762X_SOC_MT7620N:
-+		*idx = 2;
-+		return "ralink,mt7620-sysc";
-+	case MT762X_SOC_MT7628AN:
-+		*idx = 1;
-+		return "ralink,mt7628-sysc";
-+	case MT762X_SOC_MT7688:
-+		*idx = 1;
-+		return "ralink,mt7688-sysc";
-+	default:
-+		*idx = -1;
-+		return "invalid";
-+	}
- }
- 
- void __init plat_time_init(void)
- {
-+	struct of_phandle_args clkspec;
-+	const char *compatible;
- 	struct clk *clk;
-+	int cpu_clk_idx;
- 
- 	ralink_of_remap();
- 
--	ralink_clk_init();
--	clk = clk_get_sys("cpu", NULL);
-+	compatible = clk_cpu(&cpu_clk_idx);
-+	if (cpu_clk_idx == -1)
-+		panic("unable to get CPU clock index");
-+
-+	of_clk_init(NULL);
-+	clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
-+	clkspec.args_count = 1;
-+	clkspec.args[0] = cpu_clk_idx;
-+	clk = of_clk_get_from_provider(&clkspec);
- 	if (IS_ERR(clk))
- 		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
- 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
diff --git a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
deleted file mode 100644
index f7ab99bc76..0000000000
--- a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From fc15a7193a4d37d79e873fa06cc423180ddd2ddf Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:41 +0200
-Subject: [PATCH 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer
-
-Adding myself as maintainer for Mediatek MTMIPS clock driver.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- MAINTAINERS | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -13021,6 +13021,12 @@ S:	Maintained
- F:	Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
- F:	drivers/clk/ralink/clk-mt7621.c
- 
-+MEDIATEK MTMIPS CLOCK DRIVER
-+M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+S:	Maintained
-+F:	Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-+F:	drivers/clk/ralink/clk-mtmips.c
-+
- MEDIATEK MT7621/28/88 I2C DRIVER
- M:	Stefan Roese <sr@denx.de>
- L:	linux-i2c@vger.kernel.org
diff --git a/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch b/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch
deleted file mode 100644
index f5c148101f..0000000000
--- a/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch
+++ /dev/null
@@ -1,191 +0,0 @@
-From fd99ac5055d4705e91c73d1adba18bc71c8511a8 Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 19:44:32 +0800
-Subject: [PATCH] mips: ralink: introduce commonly used remap node function
-
-The ralink_of_remap() function is repeated several times on SoC specific
-source files. They have the same structure, but just differ in compatible
-strings. In order to make commonly use of these codes, this patch
-introduces a newly designed mtmips_of_remap_node() function to match and
-remap all supported system controller and memory controller nodes.
-
-Build and run tested on MT7620 and MT7628.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/common.h |  2 --
- arch/mips/ralink/mt7620.c |  9 ---------
- arch/mips/ralink/mt7621.c |  9 ---------
- arch/mips/ralink/of.c     | 42 +++++++++++++++++++++++++++++++++++-------
- arch/mips/ralink/rt288x.c |  9 ---------
- arch/mips/ralink/rt305x.c |  9 ---------
- arch/mips/ralink/rt3883.c |  9 ---------
- 7 files changed, 35 insertions(+), 54 deletions(-)
-
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -25,6 +25,4 @@ extern void ralink_of_remap(void);
- 
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
- 
--__iomem void *plat_of_remap_node(const char *node);
--
- #endif /* _RALINK_COMMON_H__ */
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -43,15 +43,6 @@
- /* does the board have sdram or ddram */
- static int dram_type;
- 
--void __init ralink_of_remap(void)
--{
--	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
--	rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
--
--	if (!rt_sysc_membase || !rt_memc_membase)
--		panic("Failed to remap core resources");
--}
--
- static __init void
- mt7620_dram_init(struct ralink_soc_info *soc_info)
- {
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(
- 	memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
- }
- 
--void __init ralink_of_remap(void)
--{
--	rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
--	rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
--
--	if (!rt_sysc_membase || !rt_memc_membase)
--		panic("Failed to remap core resources");
--}
--
- static unsigned int __init mt7621_get_soc_name0(void)
- {
- 	return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -29,28 +29,56 @@ __iomem void *rt_sysc_membase;
- __iomem void *rt_memc_membase;
- EXPORT_SYMBOL_GPL(rt_sysc_membase);
- 
--__iomem void *plat_of_remap_node(const char *node)
-+static const struct of_device_id mtmips_memc_match[] = {
-+	{ .compatible = "mediatek,mt7621-memc" },
-+	{ .compatible = "ralink,mt7620a-memc" },
-+	{ .compatible = "ralink,rt2880-memc" },
-+	{ .compatible = "ralink,rt3050-memc" },
-+	{ .compatible = "ralink,rt3883-memc" },
-+	{}
-+};
-+
-+static const struct of_device_id mtmips_sysc_match[] = {
-+	{ .compatible = "mediatek,mt7621-sysc" },
-+	{ .compatible = "ralink,mt7620a-sysc" },
-+	{ .compatible = "ralink,rt2880-sysc" },
-+	{ .compatible = "ralink,rt3050-sysc" },
-+	{ .compatible = "ralink,rt3883-sysc" },
-+	{}
-+};
-+
-+static __iomem void *
-+mtmips_of_remap_node(const struct of_device_id *match, const char *type)
- {
- 	struct resource res;
- 	struct device_node *np;
- 
--	np = of_find_compatible_node(NULL, NULL, node);
-+	np = of_find_matching_node(NULL, match);
- 	if (!np)
--		panic("Failed to find %s node", node);
-+		panic("Failed to find %s controller node", type);
- 
- 	if (of_address_to_resource(np, 0, &res))
--		panic("Failed to get resource for %s", node);
--
--	of_node_put(np);
-+		panic("Failed to get resource for %s node", np->name);
- 
- 	if (!request_mem_region(res.start,
- 				resource_size(&res),
- 				res.name))
--		panic("Failed to request resources for %s", node);
-+		panic("Failed to request resources for %s node", np->name);
-+
-+	of_node_put(np);
- 
- 	return ioremap(res.start, resource_size(&res));
- }
- 
-+void __init ralink_of_remap(void)
-+{
-+	rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system");
-+	rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory");
-+
-+	if (!rt_sysc_membase || !rt_memc_membase)
-+		panic("Failed to remap core resources");
-+}
-+
- void __init plat_mem_setup(void)
- {
- 	void *dtb;
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,15 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_of_remap(void)
--{
--	rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
--	rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
--
--	if (!rt_sysc_membase || !rt_memc_membase)
--		panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -53,15 +53,6 @@ static unsigned long rt5350_get_mem_size
- 	return ret;
- }
- 
--void __init ralink_of_remap(void)
--{
--	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
--	rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
--
--	if (!rt_sysc_membase || !rt_memc_membase)
--		panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,15 +17,6 @@
- 
- #include "common.h"
- 
--void __init ralink_of_remap(void)
--{
--	rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
--	rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
--
--	if (!rt_sysc_membase || !rt_memc_membase)
--		panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- 	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
diff --git a/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch b/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch
deleted file mode 100644
index c0c2a6e204..0000000000
--- a/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001
-From: Nathan Chancellor <nathan@kernel.org>
-Date: Thu, 22 Jun 2023 15:56:19 +0000
-Subject: clk: ralink: mtmips: Fix uninitialized use of ret in
- mtmips_register_{fixed,factor}_clocks()
-
-Clang warns:
-
-  drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
-    309 |         return ret;
-        |                ^~~
-  drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
-    285 |         int ret, i;
-        |                ^
-        |                 = 0
-  drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
-    359 |         return ret;
-        |                ^~~
-  drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
-    335 |         int ret, i;
-        |                ^
-        |                 = 0
-  2 errors generated.
-
-Set ret to the return value of clk_hw_register_fixed_rate() using the
-PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
-up the warning.
-
-Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
-Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
-Signed-off-by: Nathan Chancellor <nathan@kernel.org>
-Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
-Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- drivers/clk/ralink/clk-mtmips.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/clk/ralink/clk-mtmips.c
-+++ b/drivers/clk/ralink/clk-mtmips.c
-@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(
- 						      sclk->parent, 0,
- 						      sclk->rate);
- 		if (IS_ERR(sclk->hw)) {
-+			ret = PTR_ERR(sclk->hw);
- 			pr_err("Couldn't register fixed clock %d\n", idx);
- 			goto err_clk_unreg;
- 		}
-@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks
- 						  sclk->parent, sclk->flags,
- 						  sclk->mult, sclk->div);
- 		if (IS_ERR(sclk->hw)) {
-+			ret = PTR_ERR(sclk->hw);
- 			pr_err("Couldn't register factor clock %d\n", idx);
- 			goto err_clk_unreg;
- 		}
diff --git a/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch b/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch
deleted file mode 100644
index 6940a2b4b9..0000000000
--- a/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 670f77f76f650b1b341d31d009cc2fb03a4d1fcf Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Fri, 23 Jun 2023 08:17:48 +0800
-Subject: mips: ralink: match all supported system controller compatible
- strings
-
-Recently, A new clock and reset controller driver has been introduced to
-the ralink mips target[1]. It provides proper system control and adds more
-SoC specific compatible strings. In order to better initialize CPUs, this
-patch removes the outdated "ralink,mt7620a-sysc" and add all dt-binding
-documented compatible strings to the system controller match table.
-
-[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com/
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/of.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -40,10 +40,15 @@ static const struct of_device_id mtmips_
- 
- static const struct of_device_id mtmips_sysc_match[] = {
- 	{ .compatible = "mediatek,mt7621-sysc" },
--	{ .compatible = "ralink,mt7620a-sysc" },
-+	{ .compatible = "ralink,mt7620-sysc" },
-+	{ .compatible = "ralink,mt7628-sysc" },
-+	{ .compatible = "ralink,mt7688-sysc" },
- 	{ .compatible = "ralink,rt2880-sysc" },
- 	{ .compatible = "ralink,rt3050-sysc" },
-+	{ .compatible = "ralink,rt3052-sysc" },
-+	{ .compatible = "ralink,rt3352-sysc" },
- 	{ .compatible = "ralink,rt3883-sysc" },
-+	{ .compatible = "ralink,rt5350-sysc" },
- 	{}
- };
- 
diff --git a/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch b/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch
deleted file mode 100644
index e06d5621e1..0000000000
--- a/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch
+++ /dev/null
@@ -1,213 +0,0 @@
-From 783c7cb4659b53b5e1b809dac5e8cdf250145919 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 14 Feb 2023 11:39:35 +0100
-Subject: [PATCH 1/2] watchdog: mt7621-wdt: avoid static global declarations
-
-Instead of using static global definitions in driver code, refactor code
-introducing a new watchdog driver data structure and use it along the
-code.
-
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20230214103936.1061078-5-sergio.paracuellos@gmail.com
-[groeck: unsigned -> unsigned int]
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mt7621_wdt.c | 102 +++++++++++++++++++++++++++---------------
- 1 file changed, 65 insertions(+), 37 deletions(-)
-
---- a/drivers/watchdog/mt7621_wdt.c
-+++ b/drivers/watchdog/mt7621_wdt.c
-@@ -31,8 +31,11 @@
- #define TMR1CTL_RESTART			BIT(9)
- #define TMR1CTL_PRESCALE_SHIFT		16
- 
--static void __iomem *mt7621_wdt_base;
--static struct reset_control *mt7621_wdt_reset;
-+struct mt7621_wdt_data {
-+	void __iomem *base;
-+	struct reset_control *rst;
-+	struct watchdog_device wdt;
-+};
- 
- static bool nowayout = WATCHDOG_NOWAYOUT;
- module_param(nowayout, bool, 0);
-@@ -40,27 +43,31 @@ MODULE_PARM_DESC(nowayout,
- 		 "Watchdog cannot be stopped once started (default="
- 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
- 
--static inline void rt_wdt_w32(unsigned reg, u32 val)
-+static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
- {
--	iowrite32(val, mt7621_wdt_base + reg);
-+	iowrite32(val, base + reg);
- }
- 
--static inline u32 rt_wdt_r32(unsigned reg)
-+static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
- {
--	return ioread32(mt7621_wdt_base + reg);
-+	return ioread32(base + reg);
- }
- 
- static int mt7621_wdt_ping(struct watchdog_device *w)
- {
--	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
-+	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
-+	rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
- 
- 	return 0;
- }
- 
- static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
- {
-+	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
- 	w->timeout = t;
--	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
-+	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
- 	mt7621_wdt_ping(w);
- 
- 	return 0;
-@@ -68,29 +75,31 @@ static int mt7621_wdt_set_timeout(struct
- 
- static int mt7621_wdt_start(struct watchdog_device *w)
- {
-+	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
- 	u32 t;
- 
- 	/* set the prescaler to 1ms == 1000us */
--	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
-+	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
- 
- 	mt7621_wdt_set_timeout(w, w->timeout);
- 
--	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
- 	t |= TMR1CTL_ENABLE;
--	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
- 
- 	return 0;
- }
- 
- static int mt7621_wdt_stop(struct watchdog_device *w)
- {
-+	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
- 	u32 t;
- 
- 	mt7621_wdt_ping(w);
- 
--	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+	t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
- 	t &= ~TMR1CTL_ENABLE;
--	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+	rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
- 
- 	return 0;
- }
-@@ -105,7 +114,9 @@ static int mt7621_wdt_bootcause(void)
- 
- static int mt7621_wdt_is_running(struct watchdog_device *w)
- {
--	return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
-+	struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
-+	return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
- }
- 
- static const struct watchdog_info mt7621_wdt_info = {
-@@ -121,30 +132,39 @@ static const struct watchdog_ops mt7621_
- 	.set_timeout = mt7621_wdt_set_timeout,
- };
- 
--static struct watchdog_device mt7621_wdt_dev = {
--	.info = &mt7621_wdt_info,
--	.ops = &mt7621_wdt_ops,
--	.min_timeout = 1,
--	.max_timeout = 0xfffful / 1000,
--};
--
- static int mt7621_wdt_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
--	mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
--	if (IS_ERR(mt7621_wdt_base))
--		return PTR_ERR(mt7621_wdt_base);
--
--	mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
--	if (!IS_ERR(mt7621_wdt_reset))
--		reset_control_deassert(mt7621_wdt_reset);
--
--	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
--
--	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
--			      dev);
--	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
--	if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
-+	struct watchdog_device *mt7621_wdt;
-+	struct mt7621_wdt_data *drvdata;
-+	int err;
-+
-+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-+	if (!drvdata)
-+		return -ENOMEM;
-+
-+	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(drvdata->base))
-+		return PTR_ERR(drvdata->base);
-+
-+	drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
-+	if (!IS_ERR(drvdata->rst))
-+		reset_control_deassert(drvdata->rst);
-+
-+	mt7621_wdt = &drvdata->wdt;
-+	mt7621_wdt->info = &mt7621_wdt_info;
-+	mt7621_wdt->ops = &mt7621_wdt_ops;
-+	mt7621_wdt->min_timeout = 1;
-+	mt7621_wdt->max_timeout = 0xfffful / 1000;
-+	mt7621_wdt->parent = dev;
-+
-+	mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
-+
-+	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
-+	watchdog_set_nowayout(mt7621_wdt, nowayout);
-+	watchdog_set_drvdata(mt7621_wdt, drvdata);
-+
-+	if (mt7621_wdt_is_running(mt7621_wdt)) {
- 		/*
- 		 * Make sure to apply timeout from watchdog core, taking
- 		 * the prescaler of this driver here into account (the
-@@ -154,17 +174,25 @@ static int mt7621_wdt_probe(struct platf
- 		 * we first disable the watchdog, set the new prescaler
- 		 * and timeout, and then re-enable the watchdog.
- 		 */
--		mt7621_wdt_stop(&mt7621_wdt_dev);
--		mt7621_wdt_start(&mt7621_wdt_dev);
--		set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
-+		mt7621_wdt_stop(mt7621_wdt);
-+		mt7621_wdt_start(mt7621_wdt);
-+		set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
- 	}
- 
--	return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
-+	err = devm_watchdog_register_device(dev, &drvdata->wdt);
-+	if (err)
-+		return err;
-+
-+	platform_set_drvdata(pdev, drvdata);
-+
-+	return 0;
- }
- 
- static void mt7621_wdt_shutdown(struct platform_device *pdev)
- {
--	mt7621_wdt_stop(&mt7621_wdt_dev);
-+	struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
-+
-+	mt7621_wdt_stop(&drvdata->wdt);
- }
- 
- static const struct of_device_id mt7621_wdt_match[] = {
diff --git a/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch b/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch
deleted file mode 100644
index 7e4e45df13..0000000000
--- a/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From ff8ec4ac39ad413b580d611dbf68e1d8a82eba56 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 14 Feb 2023 11:39:36 +0100
-Subject: [PATCH 2/2] watchdog: mt7621-wdt: avoid ralink architecture dependent code
-
-MT7621 SoC has a system controller node. Watchdog need to access to reset
-status register. Ralink architecture and related driver are old and from
-the beggining they are using some architecture dependent operations for
-accessing this shared registers through 'asm/mach-ralink/ralink_regs.h'
-header file. However this is not ideal from a driver perspective which can
-just access to the system controller registers in an arch independent way
-using regmap syscon APIs. Update Kconfig accordingly to select new added
-dependencies and allow driver to be compile tested.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20230214103936.1061078-6-sergio.paracuellos@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/Kconfig      |  4 +++-
- drivers/watchdog/mt7621_wdt.c | 22 +++++++++++++++++-----
- 2 files changed, 20 insertions(+), 6 deletions(-)
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1865,7 +1865,9 @@ config GXP_WATCHDOG
- config MT7621_WDT
- 	tristate "Mediatek SoC watchdog"
- 	select WATCHDOG_CORE
--	depends on SOC_MT7620 || SOC_MT7621
-+	select REGMAP_MMIO
-+	select MFD_SYSCON
-+	depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
- 	help
- 	  Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer.
- 
---- a/drivers/watchdog/mt7621_wdt.c
-+++ b/drivers/watchdog/mt7621_wdt.c
-@@ -15,8 +15,8 @@
- #include <linux/moduleparam.h>
- #include <linux/platform_device.h>
- #include <linux/mod_devicetable.h>
--
--#include <asm/mach-ralink/ralink_regs.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- #define SYSC_RSTSTAT			0x38
- #define WDT_RST_CAUSE			BIT(1)
-@@ -34,6 +34,7 @@
- struct mt7621_wdt_data {
- 	void __iomem *base;
- 	struct reset_control *rst;
-+	struct regmap *sysc;
- 	struct watchdog_device wdt;
- };
- 
-@@ -104,9 +105,12 @@ static int mt7621_wdt_stop(struct watchd
- 	return 0;
- }
- 
--static int mt7621_wdt_bootcause(void)
-+static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
- {
--	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
-+	u32 val;
-+
-+	regmap_read(d->sysc, SYSC_RSTSTAT, &val);
-+	if (val & WDT_RST_CAUSE)
- 		return WDIOF_CARDRESET;
- 
- 	return 0;
-@@ -134,6 +138,7 @@ static const struct watchdog_ops mt7621_
- 
- static int mt7621_wdt_probe(struct platform_device *pdev)
- {
-+	struct device_node *np = pdev->dev.of_node;
- 	struct device *dev = &pdev->dev;
- 	struct watchdog_device *mt7621_wdt;
- 	struct mt7621_wdt_data *drvdata;
-@@ -143,6 +148,13 @@ static int mt7621_wdt_probe(struct platf
- 	if (!drvdata)
- 		return -ENOMEM;
- 
-+	drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
-+	if (IS_ERR(drvdata->sysc)) {
-+		drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
-+		if (IS_ERR(drvdata->sysc))
-+			return PTR_ERR(drvdata->sysc);
-+	}
-+
- 	drvdata->base = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(drvdata->base))
- 		return PTR_ERR(drvdata->base);
-@@ -158,7 +170,7 @@ static int mt7621_wdt_probe(struct platf
- 	mt7621_wdt->max_timeout = 0xfffful / 1000;
- 	mt7621_wdt->parent = dev;
- 
--	mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
-+	mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
- 
- 	watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
- 	watchdog_set_nowayout(mt7621_wdt, nowayout);
diff --git a/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch b/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch
deleted file mode 100644
index 704e861b82..0000000000
--- a/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 9f9a035e6156a57d9da062b26d2a48d031744a1e Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 18:43:22 +0800
-Subject: [PATCH 1/2] mips: pci-mt7620: do not print NFTS register value as
- error log
-
-These codes are used to read NFTS_TIMEOUT_DELAY register value and
-write it into kernel log after writing the register. they are only
-used for debugging during driver development, so there is no need
-to keep them now.
-
-Tested on MT7628AN router Motorola MWR03.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/pci/pci-mt7620.c | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct pla
- 	val |= 0x50 << 8;
- 	pci_config_write(NULL, 0, 0x70c, 4, val);
- 
--	pci_config_read(NULL, 0, 0x70c, 4, &val);
--	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
--
- 	return 0;
- }
- 
diff --git a/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch b/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch
deleted file mode 100644
index 5898a110ea..0000000000
--- a/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 89ec9bbe60b61cc6ae3eddd6d4f43e128f8a88de Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 18:43:23 +0800
-Subject: [PATCH 2/2] mips: pci-mt7620: use dev_info() to log PCIe device
- detection result
-
-Usually, We only need to print the error log when there is a PCIe card but
-initialization fails. Whether the driver finds the PCIe card or not is the
-expected behavior. So it's better to log these information with dev_info().
-
-Tested on MT7628AN router Motorola MWR03.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/pci/pci-mt7620.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -331,7 +331,7 @@ static int mt7620_pci_probe(struct platf
- 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- 		if (ralink_soc == MT762X_SOC_MT7620A)
- 			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
--		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
-+		dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
- 		return -1;
- 	}
- 
-@@ -374,7 +374,7 @@ int pcibios_map_irq(const struct pci_dev
- 			dev->bus->number, slot);
- 		return 0;
- 	}
--	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
-+	dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
- 		dev->bus->number, slot, irq);
- 
- 	/* configure the cache line size to 0x14 */
diff --git a/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch b/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch
deleted file mode 100644
index ad2191e655..0000000000
--- a/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 50233e105a0332ec0f3bc83180c416e6b200471e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Fri, 24 Mar 2023 08:37:33 +0100
-Subject: PCI: mt7621: Use dev_info() to log PCIe card detection
-
-When there is no card plugged on a PCIe port a log reporting that
-the port will be disabled is flagged as an error (dev_err()).
-
-Since this is not an error at all, change the log level by using
-dev_info() instead.
-
-Link: https://lore.kernel.org/r/20230324073733.1596231-1-sergio.paracuellos@gmail.com
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
----
- drivers/pci/controller/pcie-mt7621.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -378,8 +378,8 @@ static int mt7621_pcie_init_ports(struct
- 		u32 slot = port->slot;
- 
- 		if (!mt7621_pcie_port_is_linkup(port)) {
--			dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
--				slot);
-+			dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",
-+				 slot);
- 			mt7621_control_assert(port);
- 			port->enabled = false;
- 			num_disabled++;
diff --git a/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch b/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch
deleted file mode 100644
index c52c12526b..0000000000
--- a/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -166,6 +166,7 @@ source "drivers/net/ethernet/pensando/Kc
- source "drivers/net/ethernet/qlogic/Kconfig"
- source "drivers/net/ethernet/brocade/Kconfig"
- source "drivers/net/ethernet/qualcomm/Kconfig"
-+source "drivers/net/ethernet/ralink/Kconfig"
- source "drivers/net/ethernet/rdc/Kconfig"
- source "drivers/net/ethernet/realtek/Kconfig"
- source "drivers/net/ethernet/renesas/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
- obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
- obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
- obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
-+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/
- obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
- obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
- obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
diff --git a/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch b/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch
deleted file mode 100644
index 4f4fe9018a..0000000000
--- a/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void)
- 	return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
- }
- 
-+static inline int mt7620_get_chipver(void)
-+{
-+	return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &
-+		CHIP_REV_VER_MASK;
-+}
-+
-+static inline int mt7620_get_pkg(void)
-+{
-+	return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &
-+		CHIP_REV_PKG_MASK;
-+}
-+
- #endif
diff --git a/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
deleted file mode 100644
index 172cf98ad1..0000000000
--- a/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k
- irq
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -1,12 +1,17 @@
- # SPDX-License-Identifier: GPL-2.0
- if RALINK
- 
-+config CEVT_SYSTICK_QUIRK
-+	bool
-+	default n
-+
- config CLKEVT_RT3352
- 	bool
- 	depends on SOC_RT305X || SOC_MT7620
- 	default y
- 	select TIMER_OF
- 	select CLKSRC_MMIO
-+	select CEVT_SYSTICK_QUIRK
- 
- config RALINK_ILL_ACC
- 	bool
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -16,6 +16,31 @@
- #include <asm/time.h>
- #include <asm/cevt-r4k.h>
- 
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+static int mips_state_oneshot(struct clock_event_device *evt)
-+{
-+	unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
-+	if (!cp0_timer_irq_installed) {
-+		cp0_timer_irq_installed = 1;
-+		if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer",
-+					c0_compare_interrupt))
-+			pr_err("Failed to request irq %d (timer)\n", evt->irq);
-+	}
-+
-+	return 0;
-+}
-+
-+static int mips_state_shutdown(struct clock_event_device *evt)
-+{
-+	if (cp0_timer_irq_installed) {
-+		cp0_timer_irq_installed = 0;
-+		free_irq(evt->irq, NULL);
-+	}
-+
-+	return 0;
-+}
-+#endif
-+
- static int mips_next_event(unsigned long delta,
- 			   struct clock_event_device *evt)
- {
-@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif
- 
- int r4k_clockevent_init(void)
- {
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- 	unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
-+#endif
- 	unsigned int cpu = smp_processor_id();
- 	struct clock_event_device *cd;
- 	unsigned int irq, min_delta;
-@@ -322,11 +349,16 @@ int r4k_clockevent_init(void)
- 	cd->rating		= 300;
- 	cd->irq			= irq;
- 	cd->cpumask		= cpumask_of(cpu);
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+	cd->set_state_shutdown	= mips_state_shutdown;
-+	cd->set_state_oneshot	= mips_state_oneshot;
-+#endif
- 	cd->set_next_event	= mips_next_event;
- 	cd->event_handler	= mips_event_handler;
- 
- 	clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
- 
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- 	if (cp0_timer_irq_installed)
- 		return 0;
- 
-@@ -335,6 +367,7 @@ int r4k_clockevent_init(void)
- 	if (request_irq(irq, c0_compare_interrupt, flags, "timer",
- 			c0_compare_interrupt))
- 		pr_err("Failed to request irq %d (timer)\n", irq);
-+#endif
- 
- 	return 0;
- }
diff --git a/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch
deleted file mode 100644
index 0d70770941..0000000000
--- a/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch
+++ /dev/null
@@ -1,195 +0,0 @@
-From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 16:26:41 +0200
-Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling
-
-This feature will break udelay() and cause the delay loop to have longer delays
-when the frequency is scaled causing a performance hit.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c |   38 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -29,6 +29,10 @@
- /* enable the counter */
- #define CFG_CNT_EN		0x1
- 
-+/* mt7620 frequency scaling defines */
-+#define CLK_LUT_CFG	0x40
-+#define SLEEP_EN	BIT(31)
-+
- struct systick_device {
- 	void __iomem *membase;
- 	struct clock_event_device dev;
-@@ -36,21 +40,53 @@ struct systick_device {
- 	int freq_scale;
- };
- 
-+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
-+
- static int systick_set_oneshot(struct clock_event_device *evt);
- static int systick_shutdown(struct clock_event_device *evt);
- 
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+	if (sdev->freq_scale == status)
-+		return;
-+
-+	sdev->freq_scale = status;
-+
-+	pr_info("%s: %s autosleep mode\n", sdev->dev.name,
-+			(status) ? ("enable") : ("disable"));
-+	if (status)
-+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+	else
-+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+
-+static inline unsigned int read_count(struct systick_device *sdev)
-+{
-+	return ioread32(sdev->membase + SYSTICK_COUNT);
-+}
-+
-+static inline unsigned int read_compare(struct systick_device *sdev)
-+{
-+	return ioread32(sdev->membase + SYSTICK_COMPARE);
-+}
-+
-+static inline void write_compare(struct systick_device *sdev, unsigned int val)
-+{
-+	iowrite32(val, sdev->membase + SYSTICK_COMPARE);
-+}
-+
- static int systick_next_event(unsigned long delta,
- 				struct clock_event_device *evt)
- {
- 	struct systick_device *sdev;
--	u32 count;
-+	int res;
- 
- 	sdev = container_of(evt, struct systick_device, dev);
--	count = ioread32(sdev->membase + SYSTICK_COUNT);
--	count = (count + delta) % SYSTICK_FREQ;
--	iowrite32(count, sdev->membase + SYSTICK_COMPARE);
-+	delta += read_count(sdev);
-+	write_compare(sdev, delta);
-+	res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;
- 
--	return 0;
-+	return res;
- }
- 
- static void systick_event_handler(struct clock_event_device *dev)
-@@ -60,20 +96,25 @@ static void systick_event_handler(struct
- 
- static irqreturn_t systick_interrupt(int irq, void *dev_id)
- {
--	struct clock_event_device *dev = (struct clock_event_device *) dev_id;
-+	int ret = 0;
-+	struct clock_event_device *cdev;
-+	struct systick_device *sdev;
- 
--	dev->event_handler(dev);
-+	if (read_c0_cause() & STATUSF_IP7) {
-+		cdev = (struct clock_event_device *) dev_id;
-+		sdev = container_of(cdev, struct systick_device, dev);
-+
-+		/* Clear Count/Compare Interrupt */
-+		write_compare(sdev, read_compare(sdev));
-+		cdev->event_handler(cdev);
-+		ret = 1;
-+	}
- 
--	return IRQ_HANDLED;
-+	return IRQ_RETVAL(ret);
- }
- 
- static struct systick_device systick = {
- 	.dev = {
--		/*
--		 * cevt-r4k uses 300, make sure systick
--		 * gets used if available
--		 */
--		.rating			= 310,
- 		.features		= CLOCK_EVT_FEAT_ONESHOT,
- 		.set_next_event		= systick_next_event,
- 		.set_state_shutdown	= systick_shutdown,
-@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock
- 	if (sdev->irq_requested)
- 		free_irq(systick.dev.irq, &systick.dev);
- 	sdev->irq_requested = 0;
--	iowrite32(0, systick.membase + SYSTICK_CONFIG);
-+	iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-+
-+	if (systick_freq_scaling)
-+		systick_freq_scaling(sdev, 0);
-+
-+	if (systick_freq_scaling)
-+		systick_freq_scaling(sdev, 1);
- 
- 	return 0;
- }
-@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl
- 	return 0;
- }
- 
-+static const struct of_device_id systick_match[] = {
-+	{ .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling},
-+	{},
-+};
-+
- static int __init ralink_systick_init(struct device_node *np)
- {
--	int ret;
-+	const struct of_device_id *match;
-+	int rating = 200;
- 
- 	systick.membase = of_iomap(np, 0);
- 	if (!systick.membase)
- 		return -ENXIO;
- 
--	systick.dev.name = np->name;
--	clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
--	systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
--	systick.dev.max_delta_ticks = 0x7fff;
--	systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
--	systick.dev.min_delta_ticks = 0x3;
-+	match = of_match_node(systick_match, np);
-+	if (match) {
-+		systick_freq_scaling = match->data;
-+		/*
-+		 * cevt-r4k uses 300, make sure systick
-+		 * gets used if available
-+		 */
-+		rating = 310;
-+	}
-+
-+	/* enable counter than register clock source */
-+	iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-+	clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-+			SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);
-+
-+	/* register clock event */
- 	systick.dev.irq = irq_of_parse_and_map(np, 0);
- 	if (!systick.dev.irq) {
- 		pr_err("%pOFn: request_irq failed", np);
- 		return -EINVAL;
- 	}
- 
--	ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
--				    SYSTICK_FREQ, 301, 16,
--				    clocksource_mmio_readl_up);
--	if (ret)
--		return ret;
--
--	clockevents_register_device(&systick.dev);
-+	systick.dev.name = np->name;
-+	systick.dev.rating = rating;
-+	systick.dev.cpumask = cpumask_of(0);
-+	clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);
- 
- 	pr_info("%pOFn: running - mult: %d, shift: %d\n",
- 			np, systick.dev.mult, systick.dev.shift);
diff --git a/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch
deleted file mode 100644
index 26a28167c6..0000000000
--- a/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Thu, 31 Dec 2020 18:49:12 +0100
-Subject: [PATCH] MIPS: add bootargs-override property
-
-Add support for the bootargs-override property to the chosen node
-similar to the one used on ipq806x or mpc85xx.
-
-This is necessary, as the U-Boot used on some boards, notably the
-Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen
-node leading to a kernel panic when loading OpenWrt.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/arch/mips/kernel/setup.c
-+++ b/arch/mips/kernel/setup.c
-@@ -557,8 +557,28 @@ static int __init bootcmdline_scan_chose
- 
- #endif /* CONFIG_OF_EARLY_FLATTREE */
- 
-+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,
-+						   int depth, void *data)
-+{
-+	bool *dt_bootargs = data;
-+	const char *p;
-+	int l;
-+
-+	if (depth != 1 || !data || strcmp(uname, "chosen") != 0)
-+		return 0;
-+
-+	p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+	if (p != NULL && l > 0) {
-+		strlcpy(boot_command_line, p, COMMAND_LINE_SIZE);
-+		*dt_bootargs = true;
-+	}
-+
-+	return 1;
-+}
-+
- static void __init bootcmdline_init(void)
- {
-+	bool dt_bootargs_override = false;
- 	bool dt_bootargs = false;
- 
- 	/*
-@@ -572,6 +592,14 @@ static void __init bootcmdline_init(void
- 	}
- 
- 	/*
-+	 * If bootargs-override in the chosen node is set, use this as the
-+	 * command line
-+	 */
-+	of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);
-+	if (dt_bootargs_override)
-+		return;
-+
-+	/*
- 	 * If the user specified a built-in command line &
- 	 * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is
- 	 * prepended to arguments from the bootloader or DT so we'll copy them
diff --git a/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch
deleted file mode 100644
index c31e6d7cde..0000000000
--- a/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:15:32 +0100
-Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/kernel/setup.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/kernel/setup.c
-+++ b/arch/mips/kernel/setup.c
-@@ -699,7 +699,6 @@ static void __init arch_mem_init(char **
- 	mips_reserve_vmcore();
- 
- 	mips_parse_crashkernel();
--	device_tree_init();
- 
- 	/*
- 	 * In order to reduce the possibility of kernel panic when failed to
-@@ -834,6 +833,7 @@ void __init setup_arch(char **cmdline_p)
- 
- 	cpu_cache_init();
- 	paging_init();
-+	device_tree_init();
- 
- 	memblock_dump_all();
- 
diff --git a/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch
deleted file mode 100644
index 1dc54ccf23..0000000000
--- a/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:18:05 +0100
-Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by
- default
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig |    4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -14,9 +14,9 @@ config CLKEVT_RT3352
- 	select CEVT_SYSTICK_QUIRK
- 
- config RALINK_ILL_ACC
--	bool
-+	bool "illegal access irq"
- 	depends on SOC_RT305X
--	default y
-+	default n
- 
- config IRQ_INTC
- 	bool
diff --git a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
deleted file mode 100644
index ef54835f89..0000000000
--- a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Wed, 7 Apr 2021 13:07:38 -0700
-Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
-
-Most MT7621 SoCs have 2 cores, which is detected and supported properly
-by CPS.
-
-Unfortunately, MT7621 SoC has a less common S variant with only one core.
-On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
-starting SMP. CPULAUNCH registers can be used in that case to detect the
-absence of the second core and override the GCR_CONFIG PCORES field.
-
-Rework a long-standing OpenWrt patch to override the value of
-mips_cps_numcores on single-core MT7621 systems.
-
-Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
-MT7621 device (Netgear R6220).
-
-Original 4.14 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
-Current 5.10 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
-
-Suggested-by: Felix Fietkau <nbd@nbd.name>
-Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/mips-cps.h
-+++ b/arch/mips/include/asm/mips-cps.h
-@@ -11,6 +11,8 @@
- #include <linux/io.h>
- #include <linux/types.h>
- 
-+#include <asm/mips-boards/launch.h>
-+
- extern unsigned long __cps_access_bad_size(void)
- 	__compiletime_error("Bad size for CPS accessor");
- 
-@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_
-  */
- static inline unsigned int mips_cps_numcores(unsigned int cluster)
- {
-+	unsigned int ncores;
-+
- 	if (!mips_cm_present())
- 		return 0;
- 
- 	/* Add one before masking to handle 0xff indicating no cores */
--	return FIELD_GET(CM_GCR_CONFIG_PCORES,
-+	ncores = FIELD_GET(CM_GCR_CONFIG_PCORES,
- 			 mips_cps_cluster_config(cluster) + 1);
-+
-+	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-+		struct cpulaunch *launch;
-+
-+		/*
-+		 * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
-+		 * always reports 2 cores. Check the second core's LAUNCH_FREADY
-+		 * flag to detect if the second core is missing. This method
-+		 * only works before the core has been started.
-+		 */
-+		launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+		launch += 2; /* MT7621 has 2 VPEs per core */
-+		if (!(launch->flags & LAUNCH_FREADY))
-+			ncores = 1;
-+	}
-+
-+	return ncores;
- }
- 
- /**
diff --git a/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch
deleted file mode 100644
index dfeac7eb99..0000000000
--- a/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/arch/mips/ralink/irq-gic.c
-+++ b/arch/mips/ralink/irq-gic.c
-@@ -13,6 +13,12 @@
- 
- int get_c0_perfcount_int(void)
- {
-+	/*
-+	 * Performance counter events are routed through GIC.
-+	 * Prevent them from firing on CPU IRQ7 as well
-+	 */
-+	clear_c0_status(IE_SW0 << 7);
-+
- 	return gic_get_c0_perfcount_int();
- }
- EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
diff --git a/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch
deleted file mode 100644
index 7011bbe50b..0000000000
--- a/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 15 Jul 2013 00:39:21 +0200
-Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write
-
----
- drivers/mtd/chips/cfi_cmdset_0002.c |    9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -40,7 +40,7 @@
- #include <linux/mtd/xip.h>
- 
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
-+#define FORCE_WORD_WRITE 1
- 
- #define MAX_RETRIES 3
- 
diff --git a/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch
deleted file mode 100644
index 3b88f78602..0000000000
--- a/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Thu, 6 May 2021 17:49:55 +0200
-Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
-
-Add MTD support for the BoHong bh25q128as SPI NOR chip.
-The chip has 16MB of total capacity, divided into a total of 256
-sectors, each 64KB sized. The chip also supports 4KB sectors.
-Additionally, it supports dual and quad read modes.
-
-Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/mtd/spi-nor/Makefile |  1 +
- drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
- drivers/mtd/spi-nor/core.c   |  1 +
- drivers/mtd/spi-nor/core.h   |  1 +
- 4 files changed, 24 insertions(+)
- create mode 100644 drivers/mtd/spi-nor/bohong.c
-
---- a/drivers/mtd/spi-nor/Makefile
-+++ b/drivers/mtd/spi-nor/Makefile
-@@ -2,6 +2,7 @@
- 
- spi-nor-objs			:= core.o sfdp.o swp.o otp.o sysfs.o
- spi-nor-objs			+= atmel.o
-+spi-nor-objs			+= bohong.o
- spi-nor-objs			+= catalyst.o
- spi-nor-objs			+= eon.o
- spi-nor-objs			+= esmt.o
---- /dev/null
-+++ b/drivers/mtd/spi-nor/bohong.c
-@@ -0,0 +1,21 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2005, Intec Automation Inc.
-+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
-+ */
-+
-+#include <linux/mtd/spi-nor.h>
-+
-+#include "core.h"
-+
-+static const struct flash_info bohong_parts[] = {
-+	/* BoHong Microelectronics */
-+	{ "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256)
-+		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+};
-+
-+const struct spi_nor_manufacturer spi_nor_bohong = {
-+	.name = "bohong",
-+	.parts = bohong_parts,
-+	.nparts = ARRAY_SIZE(bohong_parts),
-+};
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -1620,6 +1620,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
- 
- static const struct spi_nor_manufacturer *manufacturers[] = {
- 	&spi_nor_atmel,
-+	&spi_nor_bohong,
- 	&spi_nor_catalyst,
- 	&spi_nor_eon,
- 	&spi_nor_esmt,
---- a/drivers/mtd/spi-nor/core.h
-+++ b/drivers/mtd/spi-nor/core.h
-@@ -617,6 +617,7 @@ struct sfdp {
- 
- /* Manufacturer drivers. */
- extern const struct spi_nor_manufacturer spi_nor_atmel;
-+extern const struct spi_nor_manufacturer spi_nor_bohong;
- extern const struct spi_nor_manufacturer spi_nor_catalyst;
- extern const struct spi_nor_manufacturer spi_nor_eon;
- extern const struct spi_nor_manufacturer spi_nor_esmt;
diff --git a/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch b/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch
deleted file mode 100644
index 438cc1ea8f..0000000000
--- a/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 1 Apr 2020 02:07:58 +0800
-Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand
- flash controller
-
-This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
-
-The NAND flash controller is similar with controllers described in
-mtk_nand.c, except that the controller from MT7621 doesn't support DMA
-transmission, and some registers' offset and fields are different.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/mtd/nand/raw/Kconfig       |    8 +
- drivers/mtd/nand/raw/Makefile      |    1 +
- drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1357 insertions(+)
- create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c
-
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -352,6 +352,14 @@ config MTD_NAND_QCOM
- 	  Enables support for NAND flash chips on SoCs containing the EBI2 NAND
- 	  controller. This controller is found on IPQ806x SoC.
- 
-+config MTD_NAND_MT7621
-+	tristate "MT7621 NAND controller"
-+	depends on SOC_MT7621 || COMPILE_TEST
-+	depends on HAS_IOMEM
-+	help
-+	  Enables support for NAND controller on MT7621 SoC.
-+	  This driver uses PIO mode for data transmission instead of DMA mode.
-+
- config MTD_NAND_MTK
- 	tristate "MTK NAND controller"
- 	depends on MTD_NAND_ECC_MEDIATEK
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
-+obj-$(CONFIG_MTD_NAND_MT7621)		+= mt7621_nand.o
- obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC)		+= mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA)		+= tegra_nand.o
diff --git a/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch b/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch
deleted file mode 100644
index 3d122c10c0..0000000000
--- a/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 1 Apr 2020 02:07:59 +0800
-Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
-
-This patch adds documentation for MediaTek MT7621 NAND flash controller
-driver.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- .../bindings/mtd/mediatek,mt7621-nfc.yaml          | 68 ++++++++++++++++++++++
- 1 file changed, 68 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
-@@ -0,0 +1,68 @@
-+# SPDX-License-Identifier: GPL-2.0
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
-+
-+maintainers:
-+  - Weijie Gao <weijie.gao@mediatek.com>
-+
-+description: |
-+  This driver uses a single node to describe both NAND Flash controller
-+  interface (NFI) and ECC engine for MT7621 SoC.
-+  MT7621 supports only one chip select.
-+
-+properties:
-+  "#address-cells": false
-+  "#size-cells": false
-+
-+  compatible:
-+    enum:
-+      - mediatek,mt7621-nfc
-+
-+  reg:
-+    items:
-+      - description: Register base of NFI core
-+      - description: Register base of ECC engine
-+
-+  reg-names:
-+    items:
-+      - const: nfi
-+      - const: ecc
-+
-+  clocks:
-+    items:
-+      - description: Source clock for NFI core, fixed 125MHz
-+
-+  clock-names:
-+    items:
-+      - const: nfi_clk
-+
-+required:
-+  - compatible
-+  - reg
-+  - reg-names
-+  - clocks
-+  - clock-names
-+
-+examples:
-+  - |
-+    nficlock: nficlock {
-+    	#clock-cells = <0>;
-+    	compatible = "fixed-clock";
-+
-+    	clock-frequency = <125000000>;
-+    };
-+
-+    nand@1e003000 {
-+    	compatible = "mediatek,mt7621-nfc";
-+
-+    	reg = <0x1e003000 0x800
-+    	       0x1e003800 0x800>;
-+    	reg-names = "nfi", "ecc";
-+
-+    	clocks = <&nficlock>;
-+    	clock-names = "nfi_clk";
-+    };
diff --git a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
deleted file mode 100644
index a6e2aa04ca..0000000000
--- a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
-Date: Fri, 21 Jun 2019 10:04:05 +0200
-Subject: [PATCH] net: ethernet: mediatek: support net-labels
-
-With this patch, device name can be set within dts file in the same way as dsa
-port can.
-Add: label = "wan"; to GMAC node.
-
-Signed-off-by: René van Dorst <opensource@vdorst.com>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n
- 
- static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
- {
-+	const char *name = of_get_property(np, "label", NULL);
- 	const __be32 *_id = of_get_property(np, "reg", NULL);
- 	struct device_node *pcs_np;
- 	phy_interface_t phy_mode;
-@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e
- 		register_netdevice_notifier(&mac->device_notifier);
- 	}
- 
-+	if (name)
-+		strlcpy(eth->netdev[id]->name, name, IFNAMSIZ);
-+
- 	return 0;
- 
- free_netdev:
diff --git a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
deleted file mode 100644
index 91159f2c63..0000000000
--- a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Sat, 27 Feb 2021 20:20:07 -0800
-Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments"
-
-This reverts commit a307593a644443db12888f45eed0dafb5869e2cc.
-
-This brings back the do_carrier flags used by the (hacky) next patch,
-still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
----
- drivers/net/phy/phy.c        | 12 ++++++------
- drivers/net/phy/phy_device.c | 12 +++++++-----
- drivers/net/phy/phylink.c    |  3 ++-
- include/linux/phy.h          |  2 +-
- 4 files changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -71,13 +71,13 @@ static void phy_process_state_change(str
- 
- static void phy_link_up(struct phy_device *phydev)
- {
--	phydev->phy_link_change(phydev, true);
-+	phydev->phy_link_change(phydev, true, true);
- 	phy_led_trigger_change_speed(phydev);
- }
- 
--static void phy_link_down(struct phy_device *phydev)
-+static void phy_link_down(struct phy_device *phydev, bool do_carrier)
- {
--	phydev->phy_link_change(phydev, false);
-+	phydev->phy_link_change(phydev, false, do_carrier);
- 	phy_led_trigger_change_speed(phydev);
- }
- 
-@@ -595,7 +595,7 @@ int phy_start_cable_test(struct phy_devi
- 		goto out;
- 
- 	/* Mark the carrier down until the test is complete */
--	phy_link_down(phydev);
-+	phy_link_down(phydev, true);
- 
- 	netif_testing_on(dev);
- 	err = phydev->drv->cable_test_start(phydev);
-@@ -666,7 +666,7 @@ int phy_start_cable_test_tdr(struct phy_
- 		goto out;
- 
- 	/* Mark the carrier down until the test is complete */
--	phy_link_down(phydev);
-+	phy_link_down(phydev, true);
- 
- 	netif_testing_on(dev);
- 	err = phydev->drv->cable_test_tdr_start(phydev, config);
-@@ -738,7 +738,7 @@ static int phy_check_link_status(struct
- 		phy_link_up(phydev);
- 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
- 		phydev->state = PHY_NOLINK;
--		phy_link_down(phydev);
-+		phy_link_down(phydev, true);
- 	}
- 
- 	return 0;
-@@ -1224,7 +1224,7 @@ void phy_state_machine(struct work_struc
- 	case PHY_HALTED:
- 		if (phydev->link) {
- 			phydev->link = 0;
--			phy_link_down(phydev);
-+			phy_link_down(phydev, true);
- 		}
- 		do_suspend = true;
- 		break;
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1037,14 +1037,16 @@ struct phy_device *phy_find_first(struct
- }
- EXPORT_SYMBOL(phy_find_first);
- 
--static void phy_link_change(struct phy_device *phydev, bool up)
-+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
- {
- 	struct net_device *netdev = phydev->attached_dev;
- 
--	if (up)
--		netif_carrier_on(netdev);
--	else
--		netif_carrier_off(netdev);
-+	if (do_carrier) {
-+		if (up)
-+			netif_carrier_on(netdev);
-+		else
-+			netif_carrier_off(netdev);
-+	}
- 	phydev->adjust_link(netdev);
- 	if (phydev->mii_ts && phydev->mii_ts->link_state)
- 		phydev->mii_ts->link_state(phydev->mii_ts, phydev);
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -1687,7 +1687,8 @@ bool phylink_expects_phy(struct phylink
- }
- EXPORT_SYMBOL_GPL(phylink_expects_phy);
- 
--static void phylink_phy_change(struct phy_device *phydev, bool up)
-+static void phylink_phy_change(struct phy_device *phydev, bool up,
-+			       bool do_carrier)
- {
- 	struct phylink *pl = phydev->phylink;
- 	bool tx_pause, rx_pause;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -739,7 +739,7 @@ struct phy_device {
- 
- 	int pma_extable;
- 
--	void (*phy_link_change)(struct phy_device *phydev, bool up);
-+	void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
- 	void (*adjust_link)(struct net_device *dev);
- 
- #if IS_ENABLED(CONFIG_MACSEC)
diff --git a/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch
deleted file mode 100644
index 2594c66048..0000000000
--- a/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 34/53] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c |    9 ++++++---
- include/linux/phy.h   |    1 +
- 2 files changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -738,7 +738,10 @@ static int phy_check_link_status(struct
- 		phy_link_up(phydev);
- 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
- 		phydev->state = PHY_NOLINK;
--		phy_link_down(phydev, true);
-+		if (!phydev->no_auto_carrier_off)
-+			phy_link_down(phydev, true);
-+		else
-+			phy_link_down(phydev, false);
- 	}
- 
- 	return 0;
-@@ -1224,7 +1227,10 @@ void phy_state_machine(struct work_struc
- 	case PHY_HALTED:
- 		if (phydev->link) {
- 			phydev->link = 0;
--			phy_link_down(phydev, true);
-+			if (!phydev->no_auto_carrier_off)
-+				phy_link_down(phydev, true);
-+			else
-+				phy_link_down(phydev, false);
- 		}
- 		do_suspend = true;
- 		break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -647,6 +647,7 @@ struct phy_device {
- 	unsigned downshifted_rate:1;
- 	unsigned is_on_sfp_module:1;
- 	unsigned mac_managed_pm:1;
-+	unsigned no_auto_carrier_off:1;
- 
- 	unsigned autoneg:1;
- 	/* The most recently read link state */
diff --git a/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch b/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch
deleted file mode 100644
index a793011223..0000000000
--- a/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent@systemli.org>
-Date: Fri, 26 May 2023 19:46:33 +0200
-Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621
-
-Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
-removed the mt7621-dma driver. Move the driver from staging to the
-folder "drivers/dma/mediatek" containing already other mediatek dma
-driver implementations and maintain it downstream in OpenWrt.
-
-This patch will not be sent to upstream linux. It is just a workaround.
-
-Signed-off-by: Nick Hainke <vincent@systemli.org>
----
- drivers/dma/mediatek/Kconfig  | 6 ++++++
- drivers/dma/mediatek/Makefile | 1 +
- 2 files changed, 7 insertions(+)
-
---- a/drivers/dma/mediatek/Kconfig
-+++ b/drivers/dma/mediatek/Kconfig
-@@ -36,3 +36,9 @@ config MTK_UART_APDMA
- 	  When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
- 	  you can enable the config. The DMA engine can only be used
- 	  with MediaTek SoCs.
-+
-+config MTK_HSDMA
-+	tristate "MTK HSDMA support"
-+	depends on RALINK && SOC_MT7621
-+	select DMA_ENGINE
-+	select DMA_VIRTUAL_CHANNELS
---- a/drivers/dma/mediatek/Makefile
-+++ b/drivers/dma/mediatek/Makefile
-@@ -2,3 +2,4 @@
- obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
- obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
- obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
-+obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
diff --git a/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch
deleted file mode 100644
index 93dabf8776..0000000000
--- a/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 19:45:30 +0200
-Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
-
-Describe gpio-ralink binding.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: devicetree@vger.kernel.org
-Cc: linux-gpio@vger.kernel.org
----
- .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++
- 1 file changed, 40 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -0,0 +1,40 @@
-+Ralink SoC GPIO controller bindings
-+
-+Required properties:
-+- compatible:
-+  - "ralink,rt2880-gpio" for Ralink controllers
-+- #gpio-cells : Should be two.
-+  - first cell is the pin number
-+  - second cell is used to specify optional parameters (unused)
-+- gpio-controller : Marks the device node as a GPIO controller
-+- reg : Physical base address and length of the controller's registers
-+- interrupt-parent: phandle to the INTC device node
-+- interrupts : Specify the INTC interrupt number
-+- ngpios : Specify the number of GPIOs
-+- ralink,register-map : The register layout depends on the GPIO bank and actual
-+		SoC type. Register offsets need to be in this order.
-+		[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
-+
-+Optional properties:
-+- ralink,gpio-base : Specify the GPIO chips base number
-+
-+Example:
-+
-+	gpio0: gpio@600 {
-+		compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
-+
-+		#gpio-cells = <2>;
-+		gpio-controller;
-+
-+		reg = <0x600 0x34>;
-+
-+		interrupt-parent = <&intc>;
-+		interrupts = <6>;
-+
-+		ngpios = <24>;
-+		ralink,gpio-base = <0>;
-+		ralink,register-map = [ 00 04 08 0c
-+				20 24 28 2c
-+				30 34 ];
-+
-+	};
diff --git a/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
deleted file mode 100644
index ff60b33cd4..0000000000
--- a/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
+++ /dev/null
@@ -1,416 +0,0 @@
-From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 20:36:29 +0200
-Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
-
-Add gpio driver for Ralink SoC. This driver makes the gpio core on
-RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: linux-gpio@vger.kernel.org
----
- arch/mips/include/asm/mach-ralink/gpio.h |   24 ++
- drivers/gpio/Kconfig                     |    6 +
- drivers/gpio/Makefile                    |    1 +
- drivers/gpio/gpio-ralink.c               |  355 ++++++++++++++++++++++++++++++
- 4 files changed, 386 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
- create mode 100644 drivers/gpio/gpio-ralink.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/gpio.h
-@@ -0,0 +1,24 @@
-+/*
-+ *  Ralink SoC GPIO API support
-+ *
-+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_MACH_RALINK_GPIO_H
-+#define __ASM_MACH_RALINK_GPIO_H
-+
-+#define ARCH_NR_GPIOS	128
-+#include <asm-generic/gpio.h>
-+
-+#define gpio_get_value	__gpio_get_value
-+#define gpio_set_value	__gpio_set_value
-+#define gpio_cansleep	__gpio_cansleep
-+#define gpio_to_irq	__gpio_to_irq
-+
-+#endif /* __ASM_MACH_RALINK_GPIO_H */
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -585,6 +585,12 @@ config GPIO_SNPS_CREG
- 	  where only several fields in register belong to GPIO lines and
- 	  each GPIO line owns a field with different length and on/off value.
- 
-+config GPIO_RALINK
-+	bool "Ralink GPIO Support"
-+	depends on RALINK
-+	help
-+	  Say yes here to support the Ralink SoC GPIO device
-+
- config GPIO_SPEAR_SPICS
- 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
- 	depends on PLAT_SPEAR
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PISOSR)		+= gpio-pisos
- obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
- obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
- obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
-+obj-$(CONFIG_GPIO_RALINK)		+= gpio-ralink.o
- obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
- obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
- obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -0,0 +1,341 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/spinlock.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+
-+enum ralink_gpio_reg {
-+	GPIO_REG_INT = 0,
-+	GPIO_REG_EDGE,
-+	GPIO_REG_RENA,
-+	GPIO_REG_FENA,
-+	GPIO_REG_DATA,
-+	GPIO_REG_DIR,
-+	GPIO_REG_POL,
-+	GPIO_REG_SET,
-+	GPIO_REG_RESET,
-+	GPIO_REG_TOGGLE,
-+	GPIO_REG_MAX
-+};
-+
-+struct ralink_gpio_chip {
-+	struct gpio_chip chip;
-+	u8 regs[GPIO_REG_MAX];
-+
-+	spinlock_t lock;
-+	void __iomem *membase;
-+	struct irq_domain *domain;
-+	int irq;
-+
-+	u32 rising;
-+	u32 falling;
-+};
-+
-+#define MAP_MAX	4
-+static struct irq_domain *irq_map[MAP_MAX];
-+static int irq_map_count;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
-+{
-+	struct ralink_gpio_chip *rg;
-+
-+	rg = container_of(chip, struct ralink_gpio_chip, chip);
-+
-+	return rg;
-+}
-+
-+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
-+{
-+	iowrite32(val, rg->membase + rg->regs[reg]);
-+}
-+
-+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
-+{
-+	return ioread32(rg->membase + rg->regs[reg]);
-+}
-+
-+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+	rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
-+}
-+
-+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+	return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+	unsigned long flags;
-+	u32 t;
-+
-+	spin_lock_irqsave(&rg->lock, flags);
-+	t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+	t &= ~BIT(offset);
-+	rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+	spin_unlock_irqrestore(&rg->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int ralink_gpio_direction_output(struct gpio_chip *chip,
-+					unsigned offset, int value)
-+{
-+	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+	unsigned long flags;
-+	u32 t;
-+
-+	spin_lock_irqsave(&rg->lock, flags);
-+	ralink_gpio_set(chip, offset, value);
-+	t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+	t |= BIT(offset);
-+	rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+	spin_unlock_irqrestore(&rg->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+	if (rg->irq < 1)
-+		return -1;
-+
-+	return irq_create_mapping(rg->domain, pin);
-+}
-+
-+static void ralink_gpio_irq_handler(struct irq_desc *desc)
-+{
-+	int i;
-+
-+	for (i = 0; i < irq_map_count; i++) {
-+		struct irq_domain *domain = irq_map[i];
-+		struct ralink_gpio_chip *rg;
-+		unsigned long pending;
-+		int bit;
-+
-+		rg = (struct ralink_gpio_chip *) domain->host_data;
-+		pending = rt_gpio_r32(rg, GPIO_REG_INT);
-+
-+		for_each_set_bit(bit, &pending, rg->chip.ngpio) {
-+			u32 map = irq_find_mapping(domain, bit);
-+			generic_handle_irq(map);
-+			rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
-+		}
-+	}
-+}
-+
-+static void ralink_gpio_irq_unmask(struct irq_data *d)
-+{
-+	struct ralink_gpio_chip *rg;
-+	unsigned long flags;
-+	u32 rise, fall;
-+
-+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+	rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+	fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+	spin_lock_irqsave(&rg->lock, flags);
-+	rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
-+	rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
-+	spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void ralink_gpio_irq_mask(struct irq_data *d)
-+{
-+	struct ralink_gpio_chip *rg;
-+	unsigned long flags;
-+	u32 rise, fall;
-+
-+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+	rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+	fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+	spin_lock_irqsave(&rg->lock, flags);
-+	rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
-+	rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
-+	spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+	struct ralink_gpio_chip *rg;
-+	u32 mask = BIT(d->hwirq);
-+
-+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+
-+	if (type == IRQ_TYPE_PROBE) {
-+		if ((rg->rising | rg->falling) & mask)
-+			return 0;
-+
-+		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+	}
-+
-+	if (type & IRQ_TYPE_EDGE_RISING)
-+		rg->rising |= mask;
-+	else
-+		rg->rising &= ~mask;
-+
-+	if (type & IRQ_TYPE_EDGE_FALLING)
-+		rg->falling |= mask;
-+	else
-+		rg->falling &= ~mask;
-+
-+	return 0;
-+}
-+
-+static struct irq_chip ralink_gpio_irq_chip = {
-+	.name		= "GPIO",
-+	.irq_unmask	= ralink_gpio_irq_unmask,
-+	.irq_mask	= ralink_gpio_irq_mask,
-+	.irq_mask_ack	= ralink_gpio_irq_mask,
-+	.irq_set_type	= ralink_gpio_irq_type,
-+};
-+
-+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+	irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
-+	irq_set_handler_data(irq, d);
-+
-+	return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+	.xlate = irq_domain_xlate_onecell,
-+	.map = gpio_map,
-+};
-+
-+static void ralink_gpio_irq_init(struct device_node *np,
-+				 struct ralink_gpio_chip *rg)
-+{
-+	if (irq_map_count >= MAP_MAX)
-+		return;
-+
-+	rg->irq = irq_of_parse_and_map(np, 0);
-+	if (!rg->irq)
-+		return;
-+
-+	rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
-+					   &irq_domain_ops, rg);
-+	if (!rg->domain) {
-+		dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
-+		return;
-+	}
-+
-+	irq_map[irq_map_count++] = rg->domain;
-+
-+	rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
-+	rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
-+
-+	if (!atomic_read(&irq_refcount))
-+		irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
-+	atomic_inc(&irq_refcount);
-+
-+	dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
-+}
-+
-+static int ralink_gpio_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np = pdev->dev.of_node;
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	struct ralink_gpio_chip *rg;
-+	const __be32 *ngpio, *gpiobase;
-+
-+	if (!res) {
-+		dev_err(&pdev->dev, "failed to find resource\n");
-+		return -ENOMEM;
-+	}
-+
-+	rg = devm_kzalloc(&pdev->dev,
-+			sizeof(struct ralink_gpio_chip), GFP_KERNEL);
-+	if (!rg)
-+		return -ENOMEM;
-+
-+	rg->membase = devm_ioremap_resource(&pdev->dev, res);
-+	if (!rg->membase) {
-+		dev_err(&pdev->dev, "cannot remap I/O memory region\n");
-+		return -ENOMEM;
-+	}
-+
-+	if (of_property_read_u8_array(np, "ralink,register-map",
-+			rg->regs, GPIO_REG_MAX)) {
-+		dev_err(&pdev->dev, "failed to read register definition\n");
-+		return -EINVAL;
-+	}
-+
-+	ngpio = of_get_property(np, "ngpios", NULL);
-+	if (!ngpio) {
-+		dev_err(&pdev->dev, "failed to read number of pins\n");
-+		return -EINVAL;
-+	}
-+
-+	gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+	if (gpiobase)
-+		rg->chip.base = be32_to_cpu(*gpiobase);
-+	else
-+		rg->chip.base = -1;
-+
-+	spin_lock_init(&rg->lock);
-+
-+	rg->chip.parent = &pdev->dev;
-+	rg->chip.label = dev_name(&pdev->dev);
-+	rg->chip.of_node = np;
-+	rg->chip.ngpio = be32_to_cpu(*ngpio);
-+	rg->chip.direction_input = ralink_gpio_direction_input;
-+	rg->chip.direction_output = ralink_gpio_direction_output;
-+	rg->chip.get = ralink_gpio_get;
-+	rg->chip.set = ralink_gpio_set;
-+	rg->chip.request = gpiochip_generic_request;
-+	rg->chip.to_irq = ralink_gpio_to_irq;
-+	rg->chip.free = gpiochip_generic_free;
-+
-+	/* set polarity to low for all lines */
-+	rt_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+	dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+	ralink_gpio_irq_init(np, rg);
-+
-+	return gpiochip_add(&rg->chip);
-+}
-+
-+static const struct of_device_id ralink_gpio_match[] = {
-+	{ .compatible = "ralink,rt2880-gpio" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
-+
-+static struct platform_driver ralink_gpio_driver = {
-+	.probe = ralink_gpio_probe,
-+	.driver = {
-+		.name = "rt2880_gpio",
-+		.owner = THIS_MODULE,
-+		.of_match_table = ralink_gpio_match,
-+	},
-+};
-+
-+static int __init ralink_gpio_init(void)
-+{
-+	return platform_driver_register(&ralink_gpio_driver);
-+}
-+
-+subsys_initcall(ralink_gpio_init);
diff --git a/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch b/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch
deleted file mode 100644
index 8520ce32ff..0000000000
--- a/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001
-From: Daniel Santos <daniel.santos@pobox.com>
-Date: Sun, 4 Nov 2018 20:24:32 -0600
-Subject: gpio-ralink: Add support for GPIO as interrupt-controller
-
-Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
----
- Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++
- drivers/gpio/gpio-ralink.c                             | 2 +-
- 2 files changed, 7 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -17,6 +17,9 @@ Required properties:
- 
- Optional properties:
- - ralink,gpio-base : Specify the GPIO chips base number
-+- interrupt-controller : marks this as an interrupt controller
-+- #interrupt-cells : a standard two-cell interrupt flag, see
-+  interrupt-controller/interrupts.txt
- 
- Example:
- 
-@@ -28,6 +31,9 @@ Example:
- 
- 		reg = <0x600 0x34>;
- 
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+
- 		interrupt-parent = <&intc>;
- 		interrupts = <6>;
- 
---- a/drivers/gpio/gpio-ralink.c
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d
- }
- 
- static const struct irq_domain_ops irq_domain_ops = {
--	.xlate = irq_domain_xlate_onecell,
-+	.xlate = irq_domain_xlate_twocell,
- 	.map = gpio_map,
- };
- 
diff --git a/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch b/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch
deleted file mode 100644
index f9fa791fe1..0000000000
--- a/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From: AngeloGioacchino Del Regno
-        <angelogioacchino.delregno@somainline.org>
-To: linus.walleij@linaro.org
-Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org,
-        marijn.suijten@somainline.org, martin.botka@somainline.org,
-        phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org,
-        devicetree@vger.kernel.org, robh+dt@kernel.org,
-        AngeloGioacchino Del Regno
-        <angelogioacchino.delregno@somainline.org>
-Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO
- Expander
-Date: Mon, 25 Jan 2021 19:22:18 +0100
-
-The Awinic AW9523(B) is a multi-function I2C gpio expander in a
-TQFN-24L package, featuring PWM (max 37mA per pin, or total max
-power 3.2Watts) for LED driving capability.
-
-It has two ports with 8 pins per port (for a total of 16 pins),
-configurable as either PWM with 1/256 stepping or GPIO input/output,
-1.8V logic input; each GPIO can be configured as input or output
-independently from each other.
-
-This IC also has an internal interrupt controller, which is capable
-of generating an interrupt for each GPIO, depending on the
-configuration, and will raise an interrupt on the INTN pin to
-advertise this to an external interrupt controller.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
----
- drivers/pinctrl/Kconfig          |   17 +
- drivers/pinctrl/Makefile         |    1 +
- drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++
- 3 files changed, 1140 insertions(+)
- create mode 100644 drivers/pinctrl/pinctrl-aw9523.c
-
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -113,6 +113,24 @@ config PINCTRL_AT91PIO4
- 	  Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
- 	  controller available on sama5d2 SoC.
- 
-+config PINCTRL_AW9523
-+	bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver"
-+	depends on OF && I2C
-+	select PINMUX
-+	select PINCONF
-+	select GENERIC_PINCONF
-+	select GPIOLIB
-+	select GPIOLIB_IRQCHIP
-+	select REGMAP
-+	select REGMAP_I2C
-+	help
-+	  The Awinic AW9523/AW9523B is a multi-function I2C GPIO
-+	  expander with PWM functionality. This driver bundles a
-+	  pinctrl driver to select the function muxing and a GPIO
-+	  driver to handle GPIO, when the GPIO function is selected.
-+
-+	  Say yes to enable pinctrl and GPIO support for the AW9523(B).
-+
- config PINCTRL_AXP209
- 	tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
- 	depends on MFD_AXP20X
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6)	+= pinctrl
- obj-$(CONFIG_PINCTRL_AS3722)	+= pinctrl-as3722.o
- obj-$(CONFIG_PINCTRL_AT91)	+= pinctrl-at91.o
- obj-$(CONFIG_PINCTRL_AT91PIO4)	+= pinctrl-at91-pio4.o
-+obj-$(CONFIG_PINCTRL_AW9523)	+= pinctrl-aw9523.o
- obj-$(CONFIG_PINCTRL_AXP209)	+= pinctrl-axp209.o
- obj-$(CONFIG_PINCTRL_BM1880)	+= pinctrl-bm1880.o
- obj-$(CONFIG_PINCTRL_CY8C95X0)	+= pinctrl-cy8c95x0.o
diff --git a/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch b/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch
deleted file mode 100644
index 047808f1e6..0000000000
--- a/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Wed, 26 Jul 2023 01:32:55 +0800
-Subject: [PATCH] pinctrl: mtmips: support requesting different functions for
- same group
-
-Sometimes pinctrl consumers may request different functions for the
-same pin group in different situations. This patch can help to reset
-the group function flag when requesting a different function.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
----
- drivers/pinctrl/ralink/pinctrl-ralink.c | 21 +++++++++++++++++----
- 1 file changed, 17 insertions(+), 4 deletions(-)
-
---- a/drivers/pinctrl/ralink/pinctrl-ralink.c
-+++ b/drivers/pinctrl/ralink/pinctrl-ralink.c
-@@ -123,11 +123,24 @@ static int ralink_pmx_group_enable(struc
- 	int i;
- 	int shift;
- 
--	/* dont allow double use */
-+	/*
-+	 * for the same pin group, if request a different function,
-+	 * then clear the group function flag and continue, else exit.
-+	 */
- 	if (p->groups[group].enabled) {
--		dev_err(p->dev, "%s is already enabled\n",
--			p->groups[group].name);
--		return 0;
-+		for (i = 0; i < p->groups[group].func_count; i++) {
-+			if (p->groups[group].func[i].enabled == 1) {
-+				if (!strcmp(p->func[func]->name,
-+					p->groups[group].func[i].name))
-+					return 0;
-+				p->groups[group].func[i].enabled = 0;
-+				break;
-+			}
-+		}
-+
-+		/* exit if request the "gpio" function again */
-+		if (i == p->groups[group].func_count && func == 0)
-+			return 0;
- 	}
- 
- 	p->groups[group].enabled = 1;
diff --git a/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch
deleted file mode 100644
index d48b668484..0000000000
--- a/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch
+++ /dev/null
@@ -1,244 +0,0 @@
-From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 19 Sep 2013 01:50:59 +0200
-Subject: [PATCH 31/53] uvc: add iPassion iP2970 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/media/usb/uvc/uvc_driver.c |   12 +++
- drivers/media/usb/uvc/uvc_status.c |    2 +
- drivers/media/usb/uvc/uvc_video.c  |  147 ++++++++++++++++++++++++++++++++++++
- drivers/media/usb/uvc/uvcvideo.h   |    5 +-
- 4 files changed, 165 insertions(+), 1 deletion(-)
-
---- a/drivers/media/usb/uvc/uvc_driver.c
-+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -2981,6 +2981,18 @@ static const struct usb_device_id uvc_id
- 	  .bInterfaceSubClass	= 1,
- 	  .bInterfaceProtocol	= 0,
- 	  .driver_info		= UVC_INFO_META(V4L2_META_FMT_D4XX) },
-+	/* iPassion iP2970 */
-+	{ .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
-+				| USB_DEVICE_ID_MATCH_INT_INFO,
-+	 .idVendor		= 0x1B3B,
-+	 .idProduct		= 0x2970,
-+	 .bInterfaceClass	= USB_CLASS_VIDEO,
-+	 .bInterfaceSubClass	= 1,
-+	 .bInterfaceProtocol	= 0,
-+	 .driver_info		= UVC_QUIRK_PROBE_MINMAX
-+				| UVC_QUIRK_STREAM_NO_FID
-+				| UVC_QUIRK_MOTION
-+				| UVC_QUIRK_SINGLE_ISO },
- 	/* Generic USB Video Class */
- 	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },
- 	{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
---- a/drivers/media/usb/uvc/uvc_status.c
-+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u
- 			if (uvc_event_control(urb, status, len))
- 				/* The URB will be resubmitted in work context. */
- 				return;
-+			dev->motion = 1;
- 			break;
- 		}
- 
-@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d
- 	}
- 
- 	pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
-+	dev->motion = 0;
- 
- 	/*
- 	 * For high-speed interrupt endpoints, the bInterval value is used as
---- a/drivers/media/usb/uvc/uvc_video.c
-+++ b/drivers/media/usb/uvc/uvc_video.c
-@@ -19,6 +19,11 @@
- #include <linux/wait.h>
- #include <linux/atomic.h>
- #include <asm/unaligned.h>
-+#include <linux/skbuff.h>
-+#include <linux/kobject.h>
-+#include <linux/netlink.h>
-+#include <linux/kobject.h>
-+#include <linux/workqueue.h>
- 
- #include <media/v4l2-common.h>
- 
-@@ -1231,9 +1236,149 @@ static void uvc_video_decode_data(struct
- 	uvc_urb->async_operations++;
- }
- 
-+struct bh_priv {
-+	unsigned long	seen;
-+};
-+
-+struct bh_event {
-+	const char		*name;
-+	struct sk_buff		*skb;
-+	struct work_struct	work;
-+};
-+
-+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
-+#define BH_DBG(fmt, args...) do {} while (0)
-+#define BH_SKB_SIZE     2048
-+
-+extern u64 uevent_next_seqnum(void);
-+static int seen = 0;
-+
-+static int bh_event_add_var(struct bh_event *event, int argv,
-+		const char *format, ...)
-+{
-+	static char buf[128];
-+	char *s;
-+	va_list args;
-+	int len;
-+
-+	if (argv)
-+		return 0;
-+
-+	va_start(args, format);
-+	len = vsnprintf(buf, sizeof(buf), format, args);
-+	va_end(args);
-+
-+	if (len >= sizeof(buf)) {
-+		BH_ERR("buffer size too small\n");
-+		WARN_ON(1);
-+		return -ENOMEM;
-+	}
-+
-+	s = skb_put(event->skb, len + 1);
-+	strcpy(s, buf);
-+
-+	BH_DBG("added variable '%s'\n", s);
-+
-+	return 0;
-+}
-+
-+static int motion_hotplug_fill_event(struct bh_event *event)
-+{
-+	int s = jiffies;
-+	int ret;
-+
-+	if (!seen)
-+		seen = jiffies;
-+
-+	ret = bh_event_add_var(event, 0, "HOME=%s", "/");
-+	if (ret)
-+		return ret;
-+
-+	ret = bh_event_add_var(event, 0, "PATH=%s",
-+		"/sbin:/bin:/usr/sbin:/usr/bin");
-+	if (ret)
-+		return ret;
-+
-+	ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
-+	if (ret)
-+		return ret;
-+
-+	ret = bh_event_add_var(event, 0, "ACTION=motion");
-+	if (ret)
-+		return ret;
-+
-+	ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
-+	if (ret)
-+		return ret;
-+	seen = s;
-+
-+	ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
-+
-+	return ret;
-+}
-+
-+static void motion_hotplug_work(struct work_struct *work)
-+{
-+	struct bh_event *event = container_of(work, struct bh_event, work);
-+	int ret = 0;
-+
-+	event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
-+	if (!event->skb)
-+		goto out_free_event;
-+
-+	ret = bh_event_add_var(event, 0, "%s@", "add");
-+	if (ret)
-+		goto out_free_skb;
-+
-+	ret = motion_hotplug_fill_event(event);
-+	if (ret)
-+		goto out_free_skb;
-+
-+	NETLINK_CB(event->skb).dst_group = 1;
-+	broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
-+
-+out_free_skb:
-+	if (ret) {
-+		BH_ERR("work error %d\n", ret);
-+		kfree_skb(event->skb);
-+	}
-+out_free_event:
-+	kfree(event);
-+}
-+
-+static int motion_hotplug_create_event(void)
-+{
-+	struct bh_event *event;
-+
-+	event = kzalloc(sizeof(*event), GFP_KERNEL);
-+	if (!event)
-+		return -ENOMEM;
-+
-+	event->name = "motion";
-+
-+	INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
-+	schedule_work(&event->work);
-+
-+	return 0;
-+}
-+
-+#define MOTION_FLAG_OFFSET	4
- static void uvc_video_decode_end(struct uvc_streaming *stream,
- 		struct uvc_buffer *buf, const u8 *data, int len)
- {
-+	if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
-+			(data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
-+		u8 *mem;
-+		buf->state = UVC_BUF_STATE_READY;
-+		mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
-+		if ( stream->dev->motion ) {
-+			stream->dev->motion = 0;
-+			motion_hotplug_create_event();
-+		} else {
-+			*mem &= 0x7f;
-+		}
-+	}
-+
- 	/* Mark the buffer as done if the EOF marker is set. */
- 	if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
- 		uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
-@@ -1815,6 +1960,8 @@ static int uvc_init_video_isoc(struct uv
- 	if (npackets == 0)
- 		return -ENOMEM;
- 
-+	if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
-+		npackets = 1;
- 	size = npackets * psize;
- 
- 	for_each_uvc_urb(uvc_urb, stream) {
---- a/drivers/media/usb/uvc/uvcvideo.h
-+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -75,6 +75,8 @@
- #define UVC_QUIRK_FORCE_Y8		0x00000800
- #define UVC_QUIRK_FORCE_BPP		0x00001000
- #define UVC_QUIRK_WAKE_AUTOSUSPEND	0x00002000
-+#define UVC_QUIRK_MOTION		0x00004000
-+#define UVC_QUIRK_SINGLE_ISO		0x00008000
- 
- /* Format flags */
- #define UVC_FMT_FLAG_COMPRESSED		0x00000001
-@@ -562,6 +564,7 @@ struct uvc_device {
- 	u8 *status;
- 	struct input_dev *input;
- 	char input_phys[64];
-+	int motion;
- 
- 	struct uvc_ctrl_work {
- 		struct work_struct work;
diff --git a/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch
deleted file mode 100644
index e2643e3f25..0000000000
--- a/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 9 Aug 2013 20:12:59 +0200
-Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880
-
-Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/spi/spi-rt2880.txt         |   28 ++++++++++++++++++++
- 1 file changed, 28 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
-@@ -0,0 +1,28 @@
-+Ralink SoC RT2880 SPI master controller.
-+
-+This SPI controller is found on most wireless SoCs made by ralink.
-+
-+Required properties:
-+- compatible : "ralink,rt2880-spi"
-+- reg : The register base for the controller.
-+- #address-cells : <1>, as required by generic SPI binding.
-+- #size-cells : <0>, also as required by generic SPI binding.
-+
-+Child nodes as per the generic SPI binding.
-+
-+Example:
-+
-+	spi@b00 {
-+		compatible = "ralink,rt2880-spi";
-+		reg = <0xb00 0x100>;
-+
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		m25p80@0 {
-+			compatible = "m25p80";
-+			reg = <0>;
-+			spi-max-frequency = <10000000>;
-+		};
-+	};
-+
diff --git a/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch
deleted file mode 100644
index 9aaf86ffc7..0000000000
--- a/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch
+++ /dev/null
@@ -1,579 +0,0 @@
-From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 11:15:12 +0100
-Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
-
-Add the driver needed to make SPI work on Ralink SoC.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: John Crispin <blogic@openwrt.org>
----
- drivers/spi/Kconfig      |    6 +
- drivers/spi/Makefile     |    1 +
- drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 537 insertions(+)
- create mode 100644 drivers/spi/spi-rt2880.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -823,6 +823,12 @@ config SPI_QCOM_GENI
- 	  This driver can also be built as a module.  If so, the module
- 	  will be called spi-geni-qcom.
- 
-+config SPI_RT2880
-+	tristate "Ralink RT288x SPI Controller"
-+	depends on RALINK
-+	help
-+	  This selects a driver for the Ralink RT288x/RT305x SPI Controller.
-+
- config SPI_S3C24XX
- 	tristate "Samsung S3C24XX series SPI"
- 	depends on ARCH_S3C24XX
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX)			+= spi-rb4xx.o
- obj-$(CONFIG_MACH_REALTEK_RTL)		+= spi-realtek-rtl.o
- obj-$(CONFIG_SPI_RPCIF)			+= spi-rpc-if.o
- obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
-+obj-$(CONFIG_SPI_RT2880)		+= spi-rt2880.o
- obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
- spi-s3c24xx-hw-y			:= spi-s3c24xx.o
- obj-$(CONFIG_SPI_S3C64XX)		+= spi-s3c64xx.o
---- /dev/null
-+++ b/drivers/spi/spi-rt2880.c
-@@ -0,0 +1,535 @@
-+/*
-+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
-+ *
-+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
-+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Some parts are based on spi-orion.c:
-+ *   Author: Shadi Ammouri <shadi@marvell.com>
-+ *   Copyright (C) 2007-2008 Marvell Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/reset.h>
-+#include <linux/spi/spi.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio.h>
-+
-+#define DRIVER_NAME			"spi-rt2880"
-+
-+#define RAMIPS_SPI_STAT			0x00
-+#define RAMIPS_SPI_CFG			0x10
-+#define RAMIPS_SPI_CTL			0x14
-+#define RAMIPS_SPI_DATA			0x20
-+#define RAMIPS_SPI_ADDR			0x24
-+#define RAMIPS_SPI_BS			0x28
-+#define RAMIPS_SPI_USER			0x2C
-+#define RAMIPS_SPI_TXFIFO		0x30
-+#define RAMIPS_SPI_RXFIFO		0x34
-+#define RAMIPS_SPI_FIFO_STAT		0x38
-+#define RAMIPS_SPI_MODE			0x3C
-+#define RAMIPS_SPI_DEV_OFFSET		0x40
-+#define RAMIPS_SPI_DMA			0x80
-+#define RAMIPS_SPI_DMASTAT		0x84
-+#define RAMIPS_SPI_ARBITER		0xF0
-+
-+/* SPISTAT register bit field */
-+#define SPISTAT_BUSY			BIT(0)
-+
-+/* SPICFG register bit field */
-+#define SPICFG_ADDRMODE			BIT(12)
-+#define SPICFG_RXENVDIS			BIT(11)
-+#define SPICFG_RXCAP			BIT(10)
-+#define SPICFG_SPIENMODE		BIT(9)
-+#define SPICFG_MSBFIRST			BIT(8)
-+#define SPICFG_SPICLKPOL		BIT(6)
-+#define SPICFG_RXCLKEDGE_FALLING	BIT(5)
-+#define SPICFG_TXCLKEDGE_FALLING	BIT(4)
-+#define SPICFG_HIZSPI			BIT(3)
-+#define SPICFG_SPICLK_PRESCALE_MASK	0x7
-+#define SPICFG_SPICLK_DIV2		0
-+#define SPICFG_SPICLK_DIV4		1
-+#define SPICFG_SPICLK_DIV8		2
-+#define SPICFG_SPICLK_DIV16		3
-+#define SPICFG_SPICLK_DIV32		4
-+#define SPICFG_SPICLK_DIV64		5
-+#define SPICFG_SPICLK_DIV128		6
-+#define SPICFG_SPICLK_DISABLE		7
-+
-+/* SPICTL register bit field */
-+#define SPICTL_START			BIT(4)
-+#define SPICTL_HIZSDO			BIT(3)
-+#define SPICTL_STARTWR			BIT(2)
-+#define SPICTL_STARTRD			BIT(1)
-+#define SPICTL_SPIENA			BIT(0)
-+
-+/* SPIUSER register bit field */
-+#define SPIUSER_USERMODE		BIT(21)
-+#define SPIUSER_INSTR_PHASE		BIT(20)
-+#define SPIUSER_ADDR_PHASE_MASK		0x7
-+#define SPIUSER_ADDR_PHASE_OFFSET	17
-+#define SPIUSER_MODE_PHASE		BIT(16)
-+#define SPIUSER_DUMMY_PHASE_MASK	0x3
-+#define SPIUSER_DUMMY_PHASE_OFFSET	14
-+#define SPIUSER_DATA_PHASE_MASK		0x3
-+#define SPIUSER_DATA_PHASE_OFFSET	12
-+#define SPIUSER_DATA_READ		(BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
-+#define SPIUSER_DATA_WRITE		(BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
-+#define SPIUSER_ADDR_TYPE_OFFSET	9
-+#define SPIUSER_MODE_TYPE_OFFSET	6
-+#define SPIUSER_DUMMY_TYPE_OFFSET	3
-+#define SPIUSER_DATA_TYPE_OFFSET	0
-+#define SPIUSER_TRANSFER_MASK		0x7
-+#define SPIUSER_TRANSFER_SINGLE		BIT(0)
-+#define SPIUSER_TRANSFER_DUAL		BIT(1)
-+#define SPIUSER_TRANSFER_QUAD		BIT(2)
-+
-+#define SPIUSER_TRANSFER_TYPE(type) ( \
-+	(type << SPIUSER_ADDR_TYPE_OFFSET) | \
-+	(type << SPIUSER_MODE_TYPE_OFFSET) | \
-+	(type << SPIUSER_DUMMY_TYPE_OFFSET) | \
-+	(type << SPIUSER_DATA_TYPE_OFFSET) \
-+)
-+
-+/* SPIFIFOSTAT register bit field */
-+#define SPIFIFOSTAT_TXEMPTY		BIT(19)
-+#define SPIFIFOSTAT_RXEMPTY		BIT(18)
-+#define SPIFIFOSTAT_TXFULL		BIT(17)
-+#define SPIFIFOSTAT_RXFULL		BIT(16)
-+#define SPIFIFOSTAT_FIFO_MASK		0xff
-+#define SPIFIFOSTAT_TX_OFFSET		8
-+#define SPIFIFOSTAT_RX_OFFSET		0
-+
-+#define SPI_FIFO_DEPTH			16
-+
-+/* SPIMODE register bit field */
-+#define SPIMODE_MODE_OFFSET		24
-+#define SPIMODE_DUMMY_OFFSET		0
-+
-+/* SPIARB register bit field */
-+#define SPICTL_ARB_EN			BIT(31)
-+#define SPICTL_CSCTL1			BIT(16)
-+#define SPI1_POR			BIT(1)
-+#define SPI0_POR			BIT(0)
-+
-+#define RT2880_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
-+		SPI_CS_HIGH)
-+
-+static atomic_t hw_reset_count = ATOMIC_INIT(0);
-+
-+struct rt2880_spi {
-+	struct spi_master	*master;
-+	void __iomem		*base;
-+	u32			speed;
-+	u16			wait_loops;
-+	u16			mode;
-+	struct clk		*clk;
-+};
-+
-+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
-+{
-+	return spi_master_get_devdata(spi->master);
-+}
-+
-+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
-+{
-+	return ioread32(rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
-+		const u32 val)
-+{
-+	iowrite32(val, rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+	void __iomem *addr = rs->base + reg;
-+
-+	iowrite32((ioread32(addr) | mask), addr);
-+}
-+
-+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+	void __iomem *addr = rs->base + reg;
-+
-+	iowrite32((ioread32(addr) & ~mask), addr);
-+}
-+
-+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
-+{
-+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+	u32 rate;
-+	u32 prescale;
-+
-+	/*
-+	 * the supported rates are: 2, 4, 8, ... 128
-+	 * round up as we look for equal or less speed
-+	 */
-+	rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
-+	rate = roundup_pow_of_two(rate);
-+
-+	/* Convert the rate to SPI clock divisor value.	*/
-+	prescale = ilog2(rate / 2);
-+
-+	/* some tolerance. double and add 100 */
-+	rs->wait_loops = (8 * HZ * loops_per_jiffy) /
-+		(clk_get_rate(rs->clk) / rate);
-+	rs->wait_loops = (rs->wait_loops << 1) + 100;
-+	rs->speed = speed;
-+
-+	dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
-+			clk_get_rate(rs->clk) / rate, speed, rate, prescale,
-+			rs->wait_loops);
-+
-+	return prescale;
-+}
-+
-+static u32 get_arbiter_offset(struct spi_master *master)
-+{
-+	u32 offset;
-+
-+	offset = RAMIPS_SPI_ARBITER;
-+	if (master->bus_num == 1)
-+		offset -= RAMIPS_SPI_DEV_OFFSET;
-+
-+	return offset;
-+}
-+
-+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+
-+	if (enable)
-+		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+	else
-+		rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+}
-+
-+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
-+{
-+	int loop = rs->wait_loops * len;
-+
-+	while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
-+		cpu_relax();
-+
-+	if (loop)
-+		return 0;
-+
-+	return -ETIMEDOUT;
-+}
-+
-+static void rt2880_dump_reg(struct spi_master *master)
-+{
-+	struct rt2880_spi *rs = spi_master_get_devdata(master);
-+
-+	dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
-+			"data: %08x, arb: %08x\n",
-+			rt2880_spi_read(rs, RAMIPS_SPI_STAT),
-+			rt2880_spi_read(rs, RAMIPS_SPI_CFG),
-+			rt2880_spi_read(rs, RAMIPS_SPI_CTL),
-+			rt2880_spi_read(rs, RAMIPS_SPI_DATA),
-+			rt2880_spi_read(rs, get_arbiter_offset(master)));
-+}
-+
-+static int rt2880_spi_transfer_one(struct spi_master *master,
-+		struct spi_device *spi, struct spi_transfer *xfer)
-+{
-+	struct rt2880_spi *rs = spi_master_get_devdata(master);
-+	unsigned len;
-+	const u8 *tx = xfer->tx_buf;
-+	u8 *rx = xfer->rx_buf;
-+	int err = 0;
-+
-+	/* change clock speed  */
-+	if (unlikely(rs->speed != xfer->speed_hz)) {
-+		u32 reg;
-+		reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
-+		reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
-+		reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
-+		rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
-+	}
-+
-+	if (tx) {
-+		len = xfer->len;
-+		while (len-- > 0) {
-+			rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
-+			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
-+			err = rt2880_spi_wait_ready(rs, 1);
-+			if (err) {
-+				dev_err(&spi->dev, "TX failed, err=%d\n", err);
-+				goto out;
-+			}
-+		}
-+	}
-+
-+	if (rx) {
-+		len = xfer->len;
-+		while (len-- > 0) {
-+			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
-+			err = rt2880_spi_wait_ready(rs, 1);
-+			if (err) {
-+				dev_err(&spi->dev, "RX failed, err=%d\n", err);
-+				goto out;
-+			}
-+			*rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
-+		}
-+	}
-+
-+out:
-+	return err;
-+}
-+
-+/* copy from spi.c */
-+static void spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+	if (spi->mode & SPI_CS_HIGH)
-+		enable = !enable;
-+
-+	if (spi->cs_gpiod)
-+		gpiod_set_value(spi->cs_gpiod, !enable);
-+	else if (spi->master->set_cs)
-+		spi->master->set_cs(spi, !enable);
-+}
-+
-+static int rt2880_spi_setup(struct spi_device *spi)
-+{
-+	struct spi_master *master = spi->master;
-+	struct rt2880_spi *rs = spi_master_get_devdata(master);
-+	u32 reg, old_reg, arbit_off;
-+
-+	if ((spi->max_speed_hz > master->max_speed_hz) ||
-+			(spi->max_speed_hz < master->min_speed_hz)) {
-+		dev_err(&spi->dev, "invalide requested speed %d Hz\n",
-+				spi->max_speed_hz);
-+		return -EINVAL;
-+	}
-+
-+	if (!(master->bits_per_word_mask &
-+				BIT(spi->bits_per_word - 1))) {
-+		dev_err(&spi->dev, "invalide bits_per_word %d\n",
-+				spi->bits_per_word);
-+		return -EINVAL;
-+	}
-+
-+	/* the hardware seems can't work on mode0 force it to mode3 */
-+	if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
-+		dev_warn(&spi->dev, "force spi mode3\n");
-+		spi->mode |= SPI_MODE_3;
-+	}
-+
-+	/* chip polarity */
-+	arbit_off = get_arbiter_offset(master);
-+	reg = old_reg = rt2880_spi_read(rs, arbit_off);
-+	if (spi->mode & SPI_CS_HIGH) {
-+		switch (master->bus_num) {
-+		case 1:
-+			reg |= SPI1_POR;
-+			break;
-+		default:
-+			reg |= SPI0_POR;
-+			break;
-+		}
-+	} else {
-+		switch (master->bus_num) {
-+		case 1:
-+			reg &= ~SPI1_POR;
-+			break;
-+		default:
-+			reg &= ~SPI0_POR;
-+			break;
-+		}
-+	}
-+
-+	/* enable spi1 */
-+	if (master->bus_num == 1)
-+		reg |= SPICTL_ARB_EN;
-+
-+	if (reg != old_reg)
-+		rt2880_spi_write(rs, arbit_off, reg);
-+
-+	/* deselected the spi device */
-+	spi_set_cs(spi, false);
-+
-+	rt2880_dump_reg(master);
-+
-+	return 0;
-+}
-+
-+static int rt2880_spi_prepare_message(struct spi_master *master,
-+		struct spi_message *msg)
-+{
-+	struct rt2880_spi *rs = spi_master_get_devdata(master);
-+	struct spi_device *spi = msg->spi;
-+	u32 reg;
-+
-+	if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
-+		return 0;
-+
-+#if 0
-+	/* set spido to tri-state */
-+	rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
-+#endif
-+
-+	reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
-+
-+	reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
-+			SPICFG_RXCLKEDGE_FALLING |
-+			SPICFG_TXCLKEDGE_FALLING |
-+			SPICFG_SPICLK_PRESCALE_MASK);
-+
-+	/* MSB */
-+	if (!(spi->mode & SPI_LSB_FIRST))
-+		reg |= SPICFG_MSBFIRST;
-+
-+	/* spi mode */
-+	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
-+	case SPI_MODE_0:
-+		reg |= SPICFG_TXCLKEDGE_FALLING;
-+		break;
-+	case SPI_MODE_1:
-+		reg |= SPICFG_RXCLKEDGE_FALLING;
-+		break;
-+	case SPI_MODE_2:
-+		reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
-+		break;
-+	case SPI_MODE_3:
-+		reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
-+		break;
-+	}
-+	rs->mode = spi->mode;
-+
-+#if 0
-+	/* set spiclk and spiena to tri-state */
-+	reg |= SPICFG_HIZSPI;
-+#endif
-+
-+	/* clock divide */
-+	reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
-+
-+	rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
-+
-+	return 0;
-+}
-+
-+static int rt2880_spi_probe(struct platform_device *pdev)
-+{
-+	struct spi_master *master;
-+	struct rt2880_spi *rs;
-+	void __iomem *base;
-+	struct resource *r;
-+	struct clk *clk;
-+	int ret;
-+
-+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	base = devm_ioremap_resource(&pdev->dev, r);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "unable to get SYS clock\n");
-+		return PTR_ERR(clk);
-+	}
-+
-+	ret = clk_prepare_enable(clk);
-+	if (ret)
-+		goto err_clk;
-+
-+	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
-+	if (master == NULL) {
-+		dev_dbg(&pdev->dev, "master allocation failed\n");
-+		ret = -ENOMEM;
-+		goto err_clk;
-+	}
-+
-+	master->dev.of_node = pdev->dev.of_node;
-+	master->mode_bits = RT2880_SPI_MODE_BITS;
-+	master->bits_per_word_mask = SPI_BPW_MASK(8);
-+	master->min_speed_hz = clk_get_rate(clk) / 128;
-+	master->max_speed_hz = clk_get_rate(clk) / 2;
-+	master->flags = SPI_MASTER_HALF_DUPLEX;
-+	master->setup = rt2880_spi_setup;
-+	master->prepare_message = rt2880_spi_prepare_message;
-+	master->set_cs = rt2880_spi_set_cs;
-+	master->transfer_one = rt2880_spi_transfer_one,
-+
-+	dev_set_drvdata(&pdev->dev, master);
-+
-+	rs = spi_master_get_devdata(master);
-+	rs->master = master;
-+	rs->base = base;
-+	rs->clk = clk;
-+
-+	if (atomic_inc_return(&hw_reset_count) == 1) {
-+		ret = device_reset(&pdev->dev);
-+		if (ret) {
-+			dev_err(&pdev->dev, "device_reset error.\n");
-+			goto err_master;
-+		}
-+	}
-+
-+	ret = devm_spi_register_master(&pdev->dev, master);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "devm_spi_register_master error.\n");
-+		goto err_master;
-+	}
-+
-+	return ret;
-+
-+err_master:
-+	spi_master_put(master);
-+	kfree(master);
-+err_clk:
-+	clk_disable_unprepare(clk);
-+
-+	return ret;
-+}
-+
-+static int rt2880_spi_remove(struct platform_device *pdev)
-+{
-+	struct spi_master *master;
-+	struct rt2880_spi *rs;
-+
-+	master = dev_get_drvdata(&pdev->dev);
-+	rs = spi_master_get_devdata(master);
-+
-+	clk_disable_unprepare(rs->clk);
-+	atomic_dec(&hw_reset_count);
-+
-+	return 0;
-+}
-+
-+MODULE_ALIAS("platform:" DRIVER_NAME);
-+
-+static const struct of_device_id rt2880_spi_match[] = {
-+	{ .compatible = "ralink,rt2880-spi" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
-+
-+static struct platform_driver rt2880_spi_driver = {
-+	.driver = {
-+		.name = DRIVER_NAME,
-+		.owner = THIS_MODULE,
-+		.of_match_table = rt2880_spi_match,
-+	},
-+	.probe = rt2880_spi_probe,
-+	.remove = rt2880_spi_remove,
-+};
-+
-+module_platform_driver(rt2880_spi_driver);
-+
-+MODULE_DESCRIPTION("Ralink SPI driver");
-+MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch
deleted file mode 100644
index 461cf6e222..0000000000
--- a/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch
+++ /dev/null
@@ -1,512 +0,0 @@
-From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:52:56 +0100
-Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++
- drivers/i2c/busses/Kconfig                         |    4 +
- drivers/i2c/busses/Makefile                        |    1 +
- drivers/i2c/busses/i2c-ralink.c                    |  327 ++++++++++++++++++++
- 4 files changed, 359 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
- create mode 100644 drivers/i2c/busses/i2c-ralink.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
-@@ -0,0 +1,27 @@
-+I2C for Ralink platforms
-+
-+Required properties :
-+- compatible : Must be "link,rt3052-i2c"
-+- reg: physical base address of the controller and length of memory mapped
-+     region.
-+- #address-cells = <1>;
-+- #size-cells = <0>;
-+
-+Optional properties:
-+- Child nodes conforming to i2c bus binding
-+
-+Example :
-+
-+palmbus@10000000 {
-+	i2c@900 {
-+		compatible = "link,rt3052-i2c";
-+		reg = <0x900 0x100>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		hwmon@4b {
-+			compatible = "national,lm92";
-+			reg = <0x4b>;
-+		};
-+	};
-+};
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -998,6 +998,11 @@ config I2C_RK3X
- 	  This driver can also be built as a module. If so, the module will
- 	  be called i2c-rk3x.
- 
-+config I2C_RALINK
-+	tristate "Ralink I2C Controller"
-+	depends on RALINK && !SOC_MT7621
-+	select OF_I2C
-+
- config I2C_RZV2M
- 	tristate "Renesas RZ/V2M adapter"
- 	depends on ARCH_RENESAS || COMPILE_TEST
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM)	+= i2c-pc
- obj-$(CONFIG_I2C_PNX)		+= i2c-pnx.o
- obj-$(CONFIG_I2C_PXA)		+= i2c-pxa.o
- obj-$(CONFIG_I2C_PXA_PCI)	+= i2c-pxa-pci.o
-+obj-$(CONFIG_I2C_RALINK)	+= i2c-ralink.o
- obj-$(CONFIG_I2C_QCOM_CCI)	+= i2c-qcom-cci.o
- obj-$(CONFIG_I2C_QCOM_GENI)	+= i2c-qcom-geni.o
- obj-$(CONFIG_I2C_QUP)		+= i2c-qup.o
---- /dev/null
-+++ b/drivers/i2c/busses/i2c-ralink.c
-@@ -0,0 +1,440 @@
-+/*
-+ * drivers/i2c/busses/i2c-ralink.c
-+ *
-+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
-+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
-+ *
-+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
-+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/reset.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/i2c.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+
-+#define REG_CONFIG_REG		0x00
-+#define REG_CLKDIV_REG		0x04
-+#define REG_DEVADDR_REG		0x08
-+#define REG_ADDR_REG		0x0C
-+#define REG_DATAOUT_REG		0x10
-+#define REG_DATAIN_REG		0x14
-+#define REG_STATUS_REG		0x18
-+#define REG_STARTXFR_REG	0x1C
-+#define REG_BYTECNT_REG		0x20
-+
-+/* REG_CONFIG_REG */
-+#define I2C_ADDRLEN_OFFSET	5
-+#define I2C_DEVADLEN_OFFSET	2
-+#define I2C_ADDRLEN_MASK	0x3
-+#define I2C_ADDR_DIS		BIT(1)
-+#define I2C_DEVADDR_DIS		BIT(0)
-+#define I2C_ADDRLEN_8		(7 << I2C_ADDRLEN_OFFSET)
-+#define I2C_DEVADLEN_7		(6 << I2C_DEVADLEN_OFFSET)
-+#define I2C_CONF_DEFAULT	(I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
-+
-+/* REG_CLKDIV_REG */
-+#define I2C_CLKDIV_MASK		0xffff
-+
-+/* REG_DEVADDR_REG */
-+#define I2C_DEVADDR_MASK	0x7f
-+
-+/* REG_ADDR_REG */
-+#define I2C_ADDR_MASK		0xff
-+
-+/* REG_STATUS_REG */
-+#define I2C_STARTERR		BIT(4)
-+#define I2C_ACKERR		BIT(3)
-+#define I2C_DATARDY		BIT(2)
-+#define I2C_SDOEMPTY		BIT(1)
-+#define I2C_BUSY		BIT(0)
-+
-+/* REG_STARTXFR_REG */
-+#define NOSTOP_CMD		BIT(2)
-+#define NODATA_CMD		BIT(1)
-+#define READ_CMD		BIT(0)
-+
-+/* REG_BYTECNT_REG */
-+#define BYTECNT_MAX		64
-+#define SET_BYTECNT(x)		(x - 1)
-+
-+/* timeout waiting for I2C devices to respond (clock streching) */
-+#define TIMEOUT_MS              1000
-+#define DELAY_INTERVAL_US       100
-+
-+struct rt_i2c {
-+	void __iomem *base;
-+	struct clk *clk;
-+	struct device *dev;
-+	struct i2c_adapter adap;
-+	u32 cur_clk;
-+	u32 clk_div;
-+	u32 flags;
-+};
-+
-+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
-+{
-+	iowrite32(val, i2c->base + reg);
-+}
-+
-+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
-+{
-+	return ioread32(i2c->base + reg);
-+}
-+
-+static int poll_down_timeout(void __iomem *addr, u32 mask)
-+{
-+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
-+
-+	do {
-+		if (!(readl_relaxed(addr) & mask))
-+			return 0;
-+
-+		usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
-+	} while (time_before(jiffies, timeout));
-+
-+	return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
-+}
-+
-+static int rt_i2c_wait_idle(struct rt_i2c *i2c)
-+{
-+	int ret;
-+
-+	ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
-+	if (ret < 0)
-+		dev_dbg(i2c->dev, "idle err(%d)\n", ret);
-+
-+	return ret;
-+}
-+
-+static int poll_up_timeout(void __iomem *addr, u32 mask)
-+{
-+	unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
-+	u32 status;
-+
-+	do {
-+		status = readl_relaxed(addr);
-+
-+		/* check error status */
-+		if (status & I2C_STARTERR)
-+			return -EAGAIN;
-+		else if (status & I2C_ACKERR)
-+			return -ENXIO;
-+		else if (status & mask)
-+			return 0;
-+
-+		usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
-+	} while (time_before(jiffies, timeout));
-+
-+	return -ETIMEDOUT;
-+}
-+
-+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
-+{
-+	int ret;
-+
-+	ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
-+	if (ret < 0)
-+		dev_dbg(i2c->dev, "rx err(%d)\n", ret);
-+
-+	return ret;
-+}
-+
-+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
-+{
-+	int ret;
-+
-+	ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
-+	if (ret < 0)
-+		dev_dbg(i2c->dev, "tx err(%d)\n", ret);
-+
-+	return ret;
-+}
-+
-+static void rt_i2c_reset(struct rt_i2c *i2c)
-+{
-+	int ret;
-+
-+	ret = device_reset(i2c->adap.dev.parent);
-+	if (ret)
-+		dev_err(i2c->dev, "Failed to reset device");
-+
-+	barrier();
-+	rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
-+}
-+
-+static void rt_i2c_dump_reg(struct rt_i2c *i2c)
-+{
-+	dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
-+			"addr %08x, dataout %08x, datain %08x, " \
-+			"status %08x, startxfr %08x, bytecnt %08x\n",
-+			rt_i2c_r32(i2c, REG_CONFIG_REG),
-+			rt_i2c_r32(i2c, REG_CLKDIV_REG),
-+			rt_i2c_r32(i2c, REG_DEVADDR_REG),
-+			rt_i2c_r32(i2c, REG_ADDR_REG),
-+			rt_i2c_r32(i2c, REG_DATAOUT_REG),
-+			rt_i2c_r32(i2c, REG_DATAIN_REG),
-+			rt_i2c_r32(i2c, REG_STATUS_REG),
-+			rt_i2c_r32(i2c, REG_STARTXFR_REG),
-+			rt_i2c_r32(i2c, REG_BYTECNT_REG));
-+}
-+
-+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-+		int num)
-+{
-+	struct rt_i2c *i2c;
-+	struct i2c_msg *pmsg;
-+	unsigned char addr;
-+	int i, j, ret;
-+	u32 cmd;
-+
-+	i2c = i2c_get_adapdata(adap);
-+
-+	for (i = 0; i < num; i++) {
-+		pmsg = &msgs[i];
-+		if (i == (num - 1))
-+			cmd = 0;
-+		else
-+			cmd = NOSTOP_CMD;
-+
-+		dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
-+				pmsg->addr, pmsg->len, pmsg->flags,
-+				(cmd == 0)? 1 : 0);
-+
-+		/* wait hardware idle */
-+		if ((ret = rt_i2c_wait_idle(i2c)))
-+			goto err_timeout;
-+
-+		if (pmsg->flags & I2C_M_TEN) {
-+			rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
-+			/* 10 bits address */
-+			addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
-+			rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
-+					REG_DEVADDR_REG);
-+			rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
-+					REG_ADDR_REG);
-+		} else {
-+			rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
-+					REG_CONFIG_REG);
-+			/* 7 bits address */
-+			rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
-+					REG_DEVADDR_REG);
-+		}
-+
-+		/* buffer length */
-+		if (pmsg->len == 0)
-+			cmd |= NODATA_CMD;
-+		else
-+			rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
-+					REG_BYTECNT_REG);
-+
-+		j = 0;
-+		if (pmsg->flags & I2C_M_RD) {
-+			cmd |= READ_CMD;
-+			/* start transfer */
-+			barrier();
-+			rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
-+			do {
-+				/* wait */
-+				if ((ret = rt_i2c_wait_rx_done(i2c)))
-+					goto err_timeout;
-+				/* read data */
-+				if (pmsg->len)
-+					pmsg->buf[j] = rt_i2c_r32(i2c,
-+							REG_DATAIN_REG);
-+				j++;
-+			} while (j < pmsg->len);
-+		} else {
-+			do {
-+				/* write data */
-+				if (pmsg->len)
-+					rt_i2c_w32(i2c, pmsg->buf[j],
-+							REG_DATAOUT_REG);
-+				/* start transfer */
-+				if (j == 0) {
-+					barrier();
-+					rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
-+				}
-+				/* wait */
-+				if ((ret = rt_i2c_wait_tx_done(i2c)))
-+					goto err_timeout;
-+				j++;
-+			} while (j < pmsg->len);
-+		}
-+	}
-+	/* the return value is number of executed messages */
-+	ret = i;
-+
-+	return ret;
-+
-+err_timeout:
-+	rt_i2c_dump_reg(i2c);
-+	rt_i2c_reset(i2c);
-+	return ret;
-+}
-+
-+static u32 rt_i2c_func(struct i2c_adapter *a)
-+{
-+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static const struct i2c_algorithm rt_i2c_algo = {
-+	.master_xfer	= rt_i2c_master_xfer,
-+	.functionality	= rt_i2c_func,
-+};
-+
-+static const struct of_device_id i2c_rt_dt_ids[] = {
-+	{ .compatible = "ralink,rt2880-i2c" },
-+	{ /* sentinel */ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
-+
-+static struct i2c_adapter_quirks rt_i2c_quirks = {
-+        .max_write_len = BYTECNT_MAX,
-+        .max_read_len = BYTECNT_MAX,
-+};
-+
-+static int rt_i2c_init(struct rt_i2c *i2c)
-+{
-+	u32 reg;
-+
-+	/* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
-+	i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
-+		(2 * i2c->cur_clk);
-+	if (i2c->clk_div < 8)
-+		i2c->clk_div = 8;
-+	if (i2c->clk_div > I2C_CLKDIV_MASK)
-+		i2c->clk_div = I2C_CLKDIV_MASK;
-+
-+	/* check support combinde/repeated start message */
-+	rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
-+	reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
-+
-+	rt_i2c_reset(i2c);
-+
-+	return reg;
-+}
-+
-+static int rt_i2c_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	struct rt_i2c *i2c;
-+	struct i2c_adapter *adap;
-+	const struct of_device_id *match;
-+	int ret, restart;
-+
-+	match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "no memory resource found\n");
-+		return -ENODEV;
-+	}
-+
-+	i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
-+	if (!i2c) {
-+		dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
-+		return -ENOMEM;
-+	}
-+
-+	i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(i2c->base))
-+		return PTR_ERR(i2c->base);
-+
-+	i2c->clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(i2c->clk)) {
-+		dev_err(&pdev->dev, "no clock defined\n");
-+		return -ENODEV;
-+	}
-+	clk_prepare_enable(i2c->clk);
-+	i2c->dev = &pdev->dev;
-+
-+	if (of_property_read_u32(pdev->dev.of_node,
-+				"clock-frequency", &i2c->cur_clk))
-+		i2c->cur_clk = 100000;
-+
-+	adap = &i2c->adap;
-+	adap->owner = THIS_MODULE;
-+	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
-+	adap->algo = &rt_i2c_algo;
-+	adap->retries = 3;
-+	adap->dev.parent = &pdev->dev;
-+	i2c_set_adapdata(adap, i2c);
-+	adap->dev.of_node = pdev->dev.of_node;
-+	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+	adap->quirks = &rt_i2c_quirks;
-+
-+	platform_set_drvdata(pdev, i2c);
-+
-+	restart = rt_i2c_init(i2c);
-+
-+	ret = i2c_add_adapter(adap);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to add adapter\n");
-+		clk_disable_unprepare(i2c->clk);
-+		return ret;
-+	}
-+
-+	dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
-+			i2c->cur_clk/1000, restart ? "" : "not ");
-+
-+	return ret;
-+}
-+
-+static int rt_i2c_remove(struct platform_device *pdev)
-+{
-+	struct rt_i2c *i2c = platform_get_drvdata(pdev);
-+
-+	i2c_del_adapter(&i2c->adap);
-+	clk_disable_unprepare(i2c->clk);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver rt_i2c_driver = {
-+	.probe		= rt_i2c_probe,
-+	.remove		= rt_i2c_remove,
-+	.driver		= {
-+		.owner	= THIS_MODULE,
-+		.name	= "i2c-ralink",
-+		.of_match_table = i2c_rt_dt_ids,
-+	},
-+};
-+
-+static int __init i2c_rt_init (void)
-+{
-+	return platform_driver_register(&rt_i2c_driver);
-+}
-+subsys_initcall(i2c_rt_init);
-+
-+static void __exit i2c_rt_exit (void)
-+{
-+	platform_driver_unregister(&rt_i2c_driver);
-+}
-+module_exit(i2c_rt_exit);
-+
-+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
-+MODULE_DESCRIPTION("Ralink I2c host driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:Ralink-I2C");
diff --git a/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
deleted file mode 100644
index 37a10589a3..0000000000
--- a/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 13 Nov 2014 19:08:40 +0100
-Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mmc/host/Kconfig             |    2 +
- drivers/mmc/host/Makefile            |    1 +
- drivers/mmc/host/mtk-mmc/Kconfig     |   16 +
- drivers/mmc/host/mtk-mmc/Makefile    |   42 +
- drivers/mmc/host/mtk-mmc/board.h     |  137 ++
- drivers/mmc/host/mtk-mmc/dbg.c       |  347 ++++
- drivers/mmc/host/mtk-mmc/dbg.h       |  156 ++
- drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
- drivers/mmc/host/mtk-mmc/sd.c        | 3060 ++++++++++++++++++++++++++++++++++
- 9 files changed, 4762 insertions(+)
- create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
- create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
- create mode 100644 drivers/mmc/host/mtk-mmc/board.h
- create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
- create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
- create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
- create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
-
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -1102,6 +1102,8 @@ config MMC_OWL
- config MMC_SDHCI_EXTERNAL_DMA
- 	bool
- 
-+source "drivers/mmc/host/mtk-mmc/Kconfig"
-+
- config MMC_LITEX
- 	tristate "LiteX MMC Host Controller support"
- 	depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -3,6 +3,7 @@
- # Makefile for MMC/SD host controller drivers
- #
- 
-+obj-$(CONFIG_MTK_MMC) 		+= mtk-mmc/
- obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
- armmmci-y := mmci.o
- armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
diff --git a/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch
deleted file mode 100644
index 57f0ec2c50..0000000000
--- a/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch
+++ /dev/null
@@ -1,1031 +0,0 @@
-From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:31:47 +0100
-Subject: [PATCH 48/53] asoc: add mt7620 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c            |    2 +
- sound/soc/Kconfig                |    1 +
- sound/soc/Makefile               |    1 +
- sound/soc/ralink/Kconfig         |   15 ++
- sound/soc/ralink/Makefile        |   11 +
- sound/soc/ralink/mt7620-i2s.c    |  436 ++++++++++++++++++++++++++++++++++++++
- sound/soc/ralink/mt7620-wm8960.c |  233 ++++++++++++++++++++
- 7 files changed, 699 insertions(+)
- create mode 100644 sound/soc/ralink/Kconfig
- create mode 100644 sound/soc/ralink/Makefile
- create mode 100644 sound/soc/ralink/mt7620-i2s.c
- create mode 100644 sound/soc/ralink/mt7620-wm8960.c
-
---- a/sound/soc/Kconfig
-+++ b/sound/soc/Kconfig
-@@ -86,6 +86,7 @@ source "sound/soc/mxs/Kconfig"
- source "sound/soc/pxa/Kconfig"
- source "sound/soc/qcom/Kconfig"
- source "sound/soc/rockchip/Kconfig"
-+source "sound/soc/ralink/Kconfig"
- source "sound/soc/samsung/Kconfig"
- source "sound/soc/sh/Kconfig"
- source "sound/soc/sof/Kconfig"
---- a/sound/soc/Makefile
-+++ b/sound/soc/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_SND_SOC)	+= kirkwood/
- obj-$(CONFIG_SND_SOC)	+= pxa/
- obj-$(CONFIG_SND_SOC)	+= qcom/
- obj-$(CONFIG_SND_SOC)	+= rockchip/
-+obj-$(CONFIG_SND_SOC)	+= ralink/
- obj-$(CONFIG_SND_SOC)	+= samsung/
- obj-$(CONFIG_SND_SOC)	+= sh/
- obj-$(CONFIG_SND_SOC)	+= sof/
---- /dev/null
-+++ b/sound/soc/ralink/Kconfig
-@@ -0,0 +1,8 @@
-+config SND_RALINK_SOC_I2S
-+	depends on RALINK && SND_SOC && !SOC_RT288X
-+	select SND_SOC_GENERIC_DMAENGINE_PCM
-+	select REGMAP_MMIO
-+	tristate "SoC Audio (I2S protocol) for Ralink SoC"
-+	help
-+	  Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
-+	  based boards.
---- /dev/null
-+++ b/sound/soc/ralink/Makefile
-@@ -0,0 +1,6 @@
-+#
-+# Ralink/MediaTek Platform Support
-+#
-+snd-soc-ralink-i2s-objs := ralink-i2s.o
-+
-+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
---- /dev/null
-+++ b/sound/soc/ralink/ralink-i2s.c
-@@ -0,0 +1,968 @@
-+/*
-+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
-+ *  Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under  the terms of the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the License, or (at your
-+ *  option) any later version.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+#include <linux/debugfs.h>
-+#include <linux/of_device.h>
-+#include <sound/pcm_params.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define DRV_NAME "ralink-i2s"
-+
-+#define I2S_REG_CFG0		0x00
-+#define I2S_REG_INT_STATUS	0x04
-+#define I2S_REG_INT_EN		0x08
-+#define I2S_REG_FF_STATUS	0x0c
-+#define I2S_REG_WREG		0x10
-+#define I2S_REG_RREG		0x14
-+#define I2S_REG_CFG1		0x18
-+#define I2S_REG_DIVCMP		0x20
-+#define I2S_REG_DIVINT		0x24
-+
-+/* I2S_REG_CFG0 */
-+#define I2S_REG_CFG0_EN		BIT(31)
-+#define I2S_REG_CFG0_DMA_EN	BIT(30)
-+#define I2S_REG_CFG0_BYTE_SWAP	BIT(28)
-+#define I2S_REG_CFG0_TX_EN	BIT(24)
-+#define I2S_REG_CFG0_RX_EN	BIT(20)
-+#define I2S_REG_CFG0_SLAVE	BIT(16)
-+#define I2S_REG_CFG0_RX_THRES	12
-+#define I2S_REG_CFG0_TX_THRES	4
-+#define I2S_REG_CFG0_THRES_MASK	(0xf << I2S_REG_CFG0_RX_THRES) | \
-+	(4 << I2S_REG_CFG0_TX_THRES)
-+#define I2S_REG_CFG0_DFT_THRES	(4 << I2S_REG_CFG0_RX_THRES) | \
-+	(4 << I2S_REG_CFG0_TX_THRES)
-+/* RT305x */
-+#define I2S_REG_CFG0_CLK_DIS	BIT(8)
-+#define I2S_REG_CFG0_TXCH_SWAP	BIT(3)
-+#define I2S_REG_CFG0_TXCH1_OFF	BIT(2)
-+#define I2S_REG_CFG0_TXCH0_OFF	BIT(1)
-+#define I2S_REG_CFG0_SLAVE_EN	BIT(0)
-+/* RT3883 */
-+#define I2S_REG_CFG0_RXCH_SWAP	BIT(11)
-+#define I2S_REG_CFG0_RXCH1_OFF	BIT(10)
-+#define I2S_REG_CFG0_RXCH0_OFF	BIT(9)
-+#define I2S_REG_CFG0_WS_INV	BIT(0)
-+/* MT7628 */
-+#define I2S_REG_CFG0_FMT_LE	BIT(29)
-+#define I2S_REG_CFG0_SYS_BE	BIT(28)
-+#define I2S_REG_CFG0_NORM_24	BIT(18)
-+#define I2S_REG_CFG0_DATA_24	BIT(17)
-+
-+/* I2S_REG_INT_STATUS */
-+#define I2S_REG_INT_RX_FAULT	BIT(7)
-+#define I2S_REG_INT_RX_OVRUN	BIT(6)
-+#define I2S_REG_INT_RX_UNRUN	BIT(5)
-+#define I2S_REG_INT_RX_THRES	BIT(4)
-+#define I2S_REG_INT_TX_FAULT	BIT(3)
-+#define I2S_REG_INT_TX_OVRUN	BIT(2)
-+#define I2S_REG_INT_TX_UNRUN	BIT(1)
-+#define I2S_REG_INT_TX_THRES	BIT(0)
-+#define I2S_REG_INT_TX_MASK	0xf
-+#define I2S_REG_INT_RX_MASK	0xf0
-+
-+/* I2S_REG_INT_STATUS */
-+#define I2S_RX_AVCNT(x)		((x >> 4) & 0xf)
-+#define I2S_TX_AVCNT(x)		(x & 0xf)
-+/* MT7628 */
-+#define MT7628_I2S_RX_AVCNT(x)	((x >> 8) & 0x1f)
-+#define MT7628_I2S_TX_AVCNT(x)	(x & 0x1f)
-+
-+/* I2S_REG_CFG1 */
-+#define I2S_REG_CFG1_LBK	BIT(31)
-+#define I2S_REG_CFG1_EXTLBK	BIT(30)
-+/* RT3883 */
-+#define I2S_REG_CFG1_LEFT_J	BIT(0)
-+#define I2S_REG_CFG1_RIGHT_J	BIT(1)
-+#define I2S_REG_CFG1_FMT_MASK	0x3
-+
-+/* I2S_REG_DIVCMP */
-+#define I2S_REG_DIVCMP_CLKEN	BIT(31)
-+#define I2S_REG_DIVCMP_DIVCOMP_MASK	0x1ff
-+
-+/* I2S_REG_DIVINT */
-+#define I2S_REG_DIVINT_MASK	0x3ff
-+
-+/* BCLK dividers */
-+#define RALINK_I2S_DIVCMP	0
-+#define RALINK_I2S_DIVINT	1
-+
-+/* FIFO */
-+#define RALINK_I2S_FIFO_SIZE	32
-+
-+/* feature flags */
-+#define RALINK_FLAGS_TXONLY	BIT(0)
-+#define RALINK_FLAGS_LEFT_J	BIT(1)
-+#define RALINK_FLAGS_RIGHT_J	BIT(2)
-+#define RALINK_FLAGS_ENDIAN	BIT(3)
-+#define RALINK_FLAGS_24BIT	BIT(4)
-+
-+#define RALINK_I2S_INT_EN	0
-+
-+struct ralink_i2s_stats {
-+	u32 dmafault;
-+	u32 overrun;
-+	u32 underrun;
-+	u32 belowthres;
-+};
-+
-+struct ralink_i2s {
-+	struct device *dev;
-+	void __iomem *regs;
-+	struct clk *clk;
-+	struct regmap *regmap;
-+	u32 flags;
-+	unsigned int fmt;
-+	u16 txdma_req;
-+	u16 rxdma_req;
-+
-+	struct snd_dmaengine_dai_dma_data playback_dma_data;
-+	struct snd_dmaengine_dai_dma_data capture_dma_data;
-+
-+	struct dentry *dbg_dir;
-+        struct dentry *dbg_stats;
-+	struct ralink_i2s_stats txstats;
-+	struct ralink_i2s_stats rxstats;
-+};
-+
-+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
-+{
-+	u32 buf[10];
-+	int ret;
-+
-+	ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
-+			buf, ARRAY_SIZE(buf));
-+
-+	dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
-+			"FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
-+			"CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
-+			buf[0], buf[1], buf[2], buf[3], buf[4],
-+			buf[5], buf[6], buf[8], buf[9]);
-+}
-+
-+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
-+                              int clk_id, unsigned int freq, int dir)
-+{
-+	return 0;
-+}
-+
-+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+	unsigned long clk = clk_get_rate(i2s->clk);
-+	int div;
-+	uint32_t data;
-+
-+	/* disable clock at slave mode */
-+	if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
-+			SND_SOC_DAIFMT_CBM_CFM) {
-+		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+				I2S_REG_CFG0_CLK_DIS,
-+				I2S_REG_CFG0_CLK_DIS);
-+		return 0;
-+	}
-+
-+	/* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
-+	div = (clk / rate ) - 1;
-+
-+	data = rt_sysc_r32(0x30);
-+	data &= (0xff << 8);
-+	data |= (0x1 << 15) | (div << 8);
-+	rt_sysc_w32(data, 0x30);
-+
-+	/* enable clock */
-+	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
-+
-+	dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
-+			clk, rate, div);
-+
-+	return 0;
-+}
-+
-+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+	unsigned long clk = clk_get_rate(i2s->clk);
-+	int divint, divcomp;
-+
-+	/* disable clock at slave mode */
-+	if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
-+			SND_SOC_DAIFMT_CBM_CFM) {
-+		regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
-+				I2S_REG_DIVCMP_CLKEN, 0);
-+		return 0;
-+	}
-+
-+	/* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
-+	clk = clk / (2 * 2 * width);
-+	divint = clk / rate;
-+	divcomp = ((clk % rate) * 512) / rate;
-+
-+	if ((divint > I2S_REG_DIVINT_MASK) ||
-+			(divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
-+		return -EINVAL;
-+
-+	regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
-+			I2S_REG_DIVINT_MASK, divint);
-+	regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
-+			I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
-+
-+	/* enable clock */
-+	regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
-+			I2S_REG_DIVCMP_CLKEN);
-+
-+	dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
-+			clk_get_rate(i2s->clk), rate, divint, divcomp);
-+
-+	return 0;
-+}
-+
-+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+	unsigned int cfg0 = 0, cfg1 = 0;
-+
-+	/* set master/slave audio interface */
-+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		if (i2s->flags & RALINK_FLAGS_TXONLY)
-+			cfg0 |= I2S_REG_CFG0_SLAVE_EN;
-+		else
-+			cfg0 |= I2S_REG_CFG0_SLAVE;
-+		break;
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* interface format */
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		break;
-+	case SND_SOC_DAIFMT_RIGHT_J:
-+		if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
-+			cfg1 |= I2S_REG_CFG1_RIGHT_J;
-+			break;
-+		}
-+		return -EINVAL;
-+	case SND_SOC_DAIFMT_LEFT_J:
-+		if (i2s->flags & RALINK_FLAGS_LEFT_J) {
-+			cfg1 |= I2S_REG_CFG1_LEFT_J;
-+			break;
-+		}
-+		return -EINVAL;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* clock inversion */
-+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_NB_NF:
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (i2s->flags & RALINK_FLAGS_TXONLY) {
-+		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+				I2S_REG_CFG0_SLAVE_EN, cfg0);
-+	} else {
-+		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+				I2S_REG_CFG0_SLAVE, cfg0);
-+	}
-+	regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
-+			I2S_REG_CFG1_FMT_MASK, cfg1);
-+	i2s->fmt = fmt;
-+
-+	return 0;
-+}
-+
-+static int ralink_i2s_startup(struct snd_pcm_substream *substream,
-+		struct snd_soc_dai *dai)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+	if (snd_soc_dai_active(dai))
-+		return 0;
-+
-+	/* setup status interrupt */
-+#if (RALINK_I2S_INT_EN)
-+	regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
-+#else
-+	regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
-+#endif
-+
-+	/* enable */
-+	regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+			I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
-+			I2S_REG_CFG0_THRES_MASK,
-+			I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
-+			I2S_REG_CFG0_DFT_THRES);
-+
-+	return 0;
-+}
-+
-+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
-+		struct snd_soc_dai *dai)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+	/* If both streams are stopped, disable module and clock */
-+	if (snd_soc_dai_active(dai))
-+		return;
-+
-+	/*
-+	 * datasheet mention when disable all control regs are cleared
-+	 * to initial values. need reinit at startup.
-+	 */
-+	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
-+}
-+
-+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
-+		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+	int width;
-+	int ret;
-+
-+	width = params_width(params);
-+	switch (width) {
-+	case 16:
-+		if (i2s->flags & RALINK_FLAGS_24BIT)
-+			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+					I2S_REG_CFG0_DATA_24, 0);
-+		break;
-+	case 24:
-+		if (i2s->flags & RALINK_FLAGS_24BIT) {
-+			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+					I2S_REG_CFG0_DATA_24,
-+					I2S_REG_CFG0_DATA_24);
-+			break;
-+		}
-+		return -EINVAL;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	switch (params_channels(params)) {
-+	case 2:
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (i2s->flags & RALINK_FLAGS_ENDIAN) {
-+		/* system endian */
-+#ifdef SNDRV_LITTLE_ENDIAN
-+		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+				I2S_REG_CFG0_SYS_BE, 0);
-+#else
-+		regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+				I2S_REG_CFG0_SYS_BE,
-+				I2S_REG_CFG0_SYS_BE);
-+#endif
-+
-+		/* data endian */
-+		switch (params_format(params)) {
-+		case SNDRV_PCM_FORMAT_S16_LE:
-+		case SNDRV_PCM_FORMAT_S24_LE:
-+			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+					I2S_REG_CFG0_FMT_LE,
-+					I2S_REG_CFG0_FMT_LE);
-+			break;
-+		case SNDRV_PCM_FORMAT_S16_BE:
-+		case SNDRV_PCM_FORMAT_S24_BE:
-+			regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+					I2S_REG_CFG0_FMT_LE, 0);
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+	}
-+
-+	/* setup bclk rate */
-+	if (i2s->flags & RALINK_FLAGS_TXONLY)
-+		ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
-+	else
-+		ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
-+
-+	return ret;
-+}
-+
-+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
-+		struct snd_soc_dai *dai)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+	unsigned int mask, val;
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		mask = I2S_REG_CFG0_TX_EN;
-+	else
-+		mask = I2S_REG_CFG0_RX_EN;
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+		val = mask;
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+		val = 0;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
-+
-+	return 0;
-+}
-+
-+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
-+		struct resource *res)
-+{
-+	struct snd_dmaengine_dai_dma_data *dma_data;
-+
-+	/* Playback */
-+	dma_data = &i2s->playback_dma_data;
-+	dma_data->addr = res->start + I2S_REG_WREG;
-+	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+	dma_data->maxburst = 1;
-+
-+	if (i2s->flags & RALINK_FLAGS_TXONLY)
-+		return;
-+
-+	/* Capture */
-+	dma_data = &i2s->capture_dma_data;
-+	dma_data->addr = res->start + I2S_REG_RREG;
-+	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+	dma_data->maxburst = 1;
-+}
-+
-+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
-+{
-+	struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
-+			&i2s->capture_dma_data);
-+
-+	return 0;
-+}
-+
-+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
-+{
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
-+	.set_sysclk = ralink_i2s_set_sysclk,
-+	.set_fmt = ralink_i2s_set_fmt,
-+	.startup = ralink_i2s_startup,
-+	.shutdown = ralink_i2s_shutdown,
-+	.hw_params = ralink_i2s_hw_params,
-+	.trigger = ralink_i2s_trigger,
-+};
-+
-+static struct snd_soc_dai_driver ralink_i2s_dai = {
-+	.name = DRV_NAME,
-+	.probe = ralink_i2s_dai_probe,
-+	.remove = ralink_i2s_dai_remove,
-+	.ops = &ralink_i2s_dai_ops,
-+	.capture = {
-+		.stream_name = "I2S Capture",
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rate_min = 5512,
-+		.rate_max = 192000,
-+		.rates = SNDRV_PCM_RATE_CONTINUOUS,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
-+	},
-+	.playback = {
-+		.stream_name = "I2S Playback",
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rate_min = 5512,
-+		.rate_max = 192000,
-+		.rates = SNDRV_PCM_RATE_CONTINUOUS,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
-+	},
-+	.symmetric_rate = 1,
-+};
-+
-+static struct snd_pcm_hardware ralink_pcm_hardware = {
-+	.info = SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_MMAP_VALID |
-+		SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_BLOCK_TRANSFER,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE,
-+	.channels_min		= 2,
-+	.channels_max		= 2,
-+	.period_bytes_min	= PAGE_SIZE,
-+	.period_bytes_max	= PAGE_SIZE * 2,
-+	.periods_min		= 2,
-+	.periods_max		= 128,
-+	.buffer_bytes_max	= 128 * 1024,
-+	.fifo_size		= RALINK_I2S_FIFO_SIZE,
-+};
-+
-+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
-+	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
-+	.pcm_hardware = &ralink_pcm_hardware,
-+	.prealloc_buffer_size = 256 * PAGE_SIZE,
-+};
-+
-+static const struct snd_soc_component_driver ralink_i2s_component = {
-+	.name = DRV_NAME,
-+};
-+
-+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
-+{
-+	return true;
-+}
-+
-+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+	switch (reg) {
-+	case I2S_REG_INT_STATUS:
-+	case I2S_REG_FF_STATUS:
-+		return true;
-+	}
-+	return false;
-+}
-+
-+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
-+{
-+	switch (reg) {
-+	case I2S_REG_FF_STATUS:
-+	case I2S_REG_RREG:
-+		return false;
-+	}
-+	return true;
-+}
-+
-+static const struct regmap_config ralink_i2s_regmap_config = {
-+	.reg_bits = 32,
-+	.reg_stride = 4,
-+	.val_bits = 32,
-+	.writeable_reg = ralink_i2s_writeable_reg,
-+	.readable_reg = ralink_i2s_readable_reg,
-+	.volatile_reg = ralink_i2s_volatile_reg,
-+	.max_register = I2S_REG_DIVINT,
-+};
-+
-+#if (RALINK_I2S_INT_EN)
-+static irqreturn_t ralink_i2s_irq(int irq, void *devid)
-+{
-+	struct ralink_i2s *i2s = devid;
-+	u32 status;
-+
-+	regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
-+	if (unlikely(!status))
-+		return IRQ_NONE;
-+
-+	/* tx stats */
-+	if (status & I2S_REG_INT_TX_MASK) {
-+		if (status & I2S_REG_INT_TX_THRES)
-+			i2s->txstats.belowthres++;
-+		if (status & I2S_REG_INT_TX_UNRUN)
-+			i2s->txstats.underrun++;
-+		if (status & I2S_REG_INT_TX_OVRUN)
-+			i2s->txstats.overrun++;
-+		if (status & I2S_REG_INT_TX_FAULT)
-+			i2s->txstats.dmafault++;
-+	}
-+
-+	/* rx stats */
-+	if (status & I2S_REG_INT_RX_MASK) {
-+		if (status & I2S_REG_INT_RX_THRES)
-+			i2s->rxstats.belowthres++;
-+		if (status & I2S_REG_INT_RX_UNRUN)
-+			i2s->rxstats.underrun++;
-+		if (status & I2S_REG_INT_RX_OVRUN)
-+			i2s->rxstats.overrun++;
-+		if (status & I2S_REG_INT_RX_FAULT)
-+			i2s->rxstats.dmafault++;
-+	}
-+
-+	/* clean status bits */
-+	regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
-+
-+	return IRQ_HANDLED;
-+}
-+#endif
-+
-+#if IS_ENABLED(CONFIG_DEBUG_FS)
-+static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
-+{
-+        struct ralink_i2s *i2s = s->private;
-+
-+	seq_printf(s, "tx stats\n");
-+	seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
-+	seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
-+	seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
-+	seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
-+
-+	seq_printf(s, "rx stats\n");
-+	seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
-+	seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
-+	seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
-+	seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
-+
-+	ralink_i2s_dump_regs(i2s);
-+
-+	return 0;
-+}
-+
-+static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
-+{
-+        return single_open(file, ralink_i2s_stats_show, inode->i_private);
-+}
-+
-+static const struct file_operations ralink_i2s_stats_ops = {
-+        .open = ralink_i2s_stats_open,
-+        .read = seq_read,
-+        .llseek = seq_lseek,
-+        .release = single_release,
-+};
-+
-+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
-+{
-+        i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
-+        if (!i2s->dbg_dir)
-+                return -ENOMEM;
-+
-+        i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
-+                        i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
-+        if (!i2s->dbg_stats) {
-+                debugfs_remove(i2s->dbg_dir);
-+                return -ENOMEM;
-+        }
-+
-+        return 0;
-+}
-+
-+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
-+{
-+	debugfs_remove(i2s->dbg_stats);
-+	debugfs_remove(i2s->dbg_dir);
-+}
-+#else
-+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
-+{
-+	return 0;
-+}
-+
-+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
-+{
-+}
-+#endif
-+
-+/*
-+ * TODO: these refclk setup functions should use
-+ * clock framework instead. hardcode it now.
-+ */
-+static void rt3350_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data |= (0x1 << 8);
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void rt3883_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data &= ~(0x3 << 13);
-+	data |= (0x1 << 13);
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void rt3552_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data &= ~(0xf << 8);
-+	data |= (0x3 << 8);
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7620_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data &= ~(0x7 << 9);
-+	data |= 0x1 << 9;
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7621_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data &= ~(0x1f << 18);
-+	data |= (0x19 << 18);
-+	data &= ~(0x1f << 12);
-+	data |= (0x1 << 12);
-+	data &= ~(0x7 << 9);
-+	data |= (0x5 << 9);
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7628_refclk_setup(void)
-+{
-+	uint32_t data;
-+
-+	/* set i2s and refclk digital pad */
-+	data = rt_sysc_r32(0x3c);
-+	data |= 0x1f;
-+	rt_sysc_w32(data, 0x3c);
-+
-+	/* Adjust REFCLK0's driving strength */
-+	data = rt_sysc_r32(0x1354);
-+	data &= ~(0x1 << 5);
-+	rt_sysc_w32(data, 0x1354);
-+	data = rt_sysc_r32(0x1364);
-+	data |= ~(0x1 << 5);
-+	rt_sysc_w32(data, 0x1364);
-+
-+	/* set refclk output 12Mhz clock */
-+	data = rt_sysc_r32(0x2c);
-+	data &= ~(0x7 << 9);
-+	data |= 0x1 << 9;
-+	rt_sysc_w32(data, 0x2c);
-+}
-+
-+struct rt_i2s_data {
-+	u32 flags;
-+	void (*refclk_setup)(void);
-+};
-+
-+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
-+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
-+	.refclk_setup = rt3350_refclk_setup };
-+struct rt_i2s_data rt3883_i2s_data = {
-+	.flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
-+	.refclk_setup = rt3883_refclk_setup };
-+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
-+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
-+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
-+struct rt_i2s_data mt7628_i2s_data = {
-+	.flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
-+			RALINK_FLAGS_LEFT_J),
-+	.refclk_setup = mt7628_refclk_setup};
-+
-+static const struct of_device_id ralink_i2s_match_table[] = {
-+	{ .compatible = "ralink,rt3050-i2s",
-+		.data = (void *)&rt3050_i2s_data },
-+	{ .compatible = "ralink,rt3350-i2s",
-+		.data = (void *)&rt3350_i2s_data },
-+	{ .compatible = "ralink,rt3883-i2s",
-+		.data = (void *)&rt3883_i2s_data },
-+	{ .compatible = "ralink,rt3352-i2s",
-+		.data = (void *)&rt3352_i2s_data },
-+	{ .compatible = "mediatek,mt7620-i2s",
-+		.data = (void *)&mt7620_i2s_data },
-+	{ .compatible = "mediatek,mt7621-i2s",
-+		.data = (void *)&mt7621_i2s_data },
-+	{ .compatible = "mediatek,mt7628-i2s",
-+		.data = (void *)&mt7628_i2s_data },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
-+
-+static int ralink_i2s_probe(struct platform_device *pdev)
-+{
-+	const struct of_device_id *match;
-+	struct device_node *np = pdev->dev.of_node;
-+	struct ralink_i2s *i2s;
-+	struct resource *res;
-+	int irq, ret;
-+	u32 dma_req;
-+	struct rt_i2s_data *data;
-+
-+	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
-+	if (!i2s)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, i2s);
-+	i2s->dev = &pdev->dev;
-+
-+	match = of_match_device(ralink_i2s_match_table, &pdev->dev);
-+	if (!match)
-+		return -EINVAL;
-+	data = (struct rt_i2s_data *)match->data;
-+	i2s->flags = data->flags;
-+	/* setup out 12Mhz refclk to codec as mclk */
-+	if (data->refclk_setup)
-+		data->refclk_setup();
-+
-+	if (of_property_read_u32(np, "txdma-req", &dma_req)) {
-+		dev_err(&pdev->dev, "no txdma-req define\n");
-+		return -EINVAL;
-+	}
-+	i2s->txdma_req = (u16)dma_req;
-+	if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
-+		if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
-+			dev_err(&pdev->dev, "no rxdma-req define\n");
-+			return -EINVAL;
-+		}
-+		i2s->rxdma_req = (u16)dma_req;
-+	}
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	i2s->regs = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(i2s->regs))
-+		return PTR_ERR(i2s->regs);
-+
-+	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
-+			&ralink_i2s_regmap_config);
-+	if (IS_ERR(i2s->regmap)) {
-+		dev_err(&pdev->dev, "regmap init failed\n");
-+		return PTR_ERR(i2s->regmap);
-+	}
-+
-+        irq = platform_get_irq(pdev, 0);
-+        if (irq < 0) {
-+                dev_err(&pdev->dev, "failed to get irq\n");
-+                return -EINVAL;
-+        }
-+
-+#if (RALINK_I2S_INT_EN)
-+	ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
-+			0, dev_name(&pdev->dev), i2s);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to request irq\n");
-+		return ret;
-+	}
-+#endif
-+
-+	i2s->clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(i2s->clk)) {
-+		dev_err(&pdev->dev, "no clock defined\n");
-+		return PTR_ERR(i2s->clk);
-+	}
-+
-+	ret = clk_prepare_enable(i2s->clk);
-+	if (ret)
-+		return ret;
-+
-+	ralink_i2s_init_dma_data(i2s, res);
-+
-+	ret = device_reset(&pdev->dev);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to reset device\n");
-+		goto err_clk_disable;
-+	}
-+
-+	ret = ralink_i2s_debugfs_create(i2s);
-+	if (ret) {
-+		dev_err(&pdev->dev, "create debugfs failed\n");
-+		goto err_clk_disable;
-+	}
-+
-+	/* enable 24bits support */
-+	if (i2s->flags & RALINK_FLAGS_24BIT) {
-+		ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
-+		ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
-+	}
-+
-+	/* enable big endian support */
-+	if (i2s->flags & RALINK_FLAGS_ENDIAN) {
-+		ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+		ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+		ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+		if (i2s->flags & RALINK_FLAGS_24BIT) {
-+			ralink_i2s_dai.capture.formats |=
-+				SNDRV_PCM_FMTBIT_S24_BE;
-+			ralink_i2s_dai.playback.formats |=
-+				SNDRV_PCM_FMTBIT_S24_BE;
-+			ralink_pcm_hardware.formats |=
-+				SNDRV_PCM_FMTBIT_S24_BE;
-+		}
-+	}
-+
-+	/* disable capture support */
-+	if (i2s->flags & RALINK_FLAGS_TXONLY)
-+		memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
-+				0);
-+
-+	ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
-+			&ralink_i2s_dai, 1);
-+	if (ret)
-+		goto err_debugfs;
-+
-+	ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
-+			&ralink_dmaengine_pcm_config,
-+			SND_DMAENGINE_PCM_FLAG_COMPAT);
-+	if (ret)
-+		goto err_debugfs;
-+
-+	dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000);
-+
-+	return 0;
-+
-+err_debugfs:
-+	ralink_i2s_debugfs_remove(i2s);
-+
-+err_clk_disable:
-+	clk_disable_unprepare(i2s->clk);
-+
-+	return ret;
-+}
-+
-+static int ralink_i2s_remove(struct platform_device *pdev)
-+{
-+	struct ralink_i2s *i2s = platform_get_drvdata(pdev);
-+
-+	ralink_i2s_debugfs_remove(i2s);
-+	clk_disable_unprepare(i2s->clk);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver ralink_i2s_driver = {
-+	.probe = ralink_i2s_probe,
-+	.remove = ralink_i2s_remove,
-+	.driver = {
-+		.name = DRV_NAME,
-+		.of_match_table = ralink_i2s_match_table,
-+	},
-+};
-+module_platform_driver(ralink_i2s_driver);
-+
-+MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
-+MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch
deleted file mode 100644
index 42a15a935c..0000000000
--- a/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:31:08 +0100
-Subject: [PATCH 51/53] serial: add ugly custom baud rate hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/tty/serial/serial_core.c |    3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/tty/serial/serial_core.c
-+++ b/drivers/tty/serial/serial_core.c
-@@ -445,6 +445,9 @@ uart_get_baud_rate(struct uart_port *por
- 		break;
- 	}
- 
-+	if (tty_termios_baud_rate(termios) == 2500000)
-+		return 250000;
-+
- 	for (try = 0; try < 2; try++) {
- 		baud = tty_termios_baud_rate(termios);
- 
diff --git a/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch
deleted file mode 100644
index ab164f5ab8..0000000000
--- a/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:16:50 +0100
-Subject: [PATCH 52/53] pwm: add mediatek support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/pwm/Kconfig        |    9 +++
- drivers/pwm/Makefile       |    1 +
- drivers/pwm/pwm-mediatek.c |  173 ++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 183 insertions(+)
- create mode 100644 drivers/pwm/pwm-mediatek.c
-
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -393,6 +393,15 @@ config PWM_MEDIATEK
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called pwm-mediatek.
- 
-+config PWM_MEDIATEK_RAMIPS
-+	tristate "Mediatek PWM support"
-+	depends on RALINK && OF
-+	help
-+	  Generic PWM framework driver for Mediatek ARM SoC.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called pwm-mxs.
-+
- config PWM_MXS
- 	tristate "Freescale MXS PWM support"
- 	depends on ARCH_MXS || COMPILE_TEST
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI)	+= pwm-lpss-p
- obj-$(CONFIG_PWM_LPSS_PLATFORM)	+= pwm-lpss-platform.o
- obj-$(CONFIG_PWM_MESON)		+= pwm-meson.o
- obj-$(CONFIG_PWM_MEDIATEK)	+= pwm-mediatek.o
-+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS)	+= pwm-mediatek-ramips.o
- obj-$(CONFIG_PWM_MTK_DISP)	+= pwm-mtk-disp.o
- obj-$(CONFIG_PWM_MXS)		+= pwm-mxs.o
- obj-$(CONFIG_PWM_NTXEC)		+= pwm-ntxec.o
---- /dev/null
-+++ b/drivers/pwm/pwm-mediatek-ramips.c
-@@ -0,0 +1,197 @@
-+/*
-+ * Mediatek Pulse Width Modulator driver
-+ *
-+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pwm.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+
-+#define NUM_PWM		4
-+
-+/* PWM registers and bits definitions */
-+#define PWMCON			0x00
-+#define PWMHDUR			0x04
-+#define PWMLDUR			0x08
-+#define PWMGDUR			0x0c
-+#define PWMWAVENUM		0x28
-+#define PWMDWIDTH		0x2c
-+#define PWMTHRES		0x30
-+
-+/**
-+ * struct mtk_pwm_chip - struct representing pwm chip
-+ *
-+ * @mmio_base: base address of pwm chip
-+ * @chip: linux pwm chip representation
-+ */
-+struct mtk_pwm_chip {
-+	void __iomem *mmio_base;
-+	struct pwm_chip chip;
-+};
-+
-+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
-+{
-+	return container_of(chip, struct mtk_pwm_chip, chip);
-+}
-+
-+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
-+				  unsigned long offset)
-+{
-+	return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
-+}
-+
-+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
-+				    unsigned int num, unsigned long offset,
-+				    unsigned long val)
-+{
-+	iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
-+}
-+
-+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-+			    int duty_ns, int period_ns)
-+{
-+	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+	u32 resolution = 100 / 4;
-+	u32 clkdiv = 0;
-+
-+	while (period_ns / resolution  > 8191) {
-+		clkdiv++;
-+		resolution *= 2;
-+	}
-+
-+	if (clkdiv > 7)
-+		return -1;
-+
-+	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
-+	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
-+	mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
-+	return 0;
-+}
-+
-+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+	u32 val;
-+
-+	val = ioread32(pc->mmio_base);
-+	val |= BIT(pwm->hwpwm);
-+	iowrite32(val, pc->mmio_base);
-+
-+	return 0;
-+}
-+
-+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+	u32 val;
-+
-+	val = ioread32(pc->mmio_base);
-+	val &= ~BIT(pwm->hwpwm);
-+	iowrite32(val, pc->mmio_base);
-+}
-+
-+static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
-+			 const struct pwm_state *state)
-+{
-+	int err;
-+	bool enabled = pwm->state.enabled;
-+
-+	if (!state->enabled) {
-+		if (enabled)
-+			mtk_pwm_disable(chip, pwm);
-+
-+		return 0;
-+	}
-+
-+	err = mtk_pwm_config(pwm->chip, pwm,
-+			     state->duty_cycle, state->period);
-+	if (err)
-+		return err;
-+
-+	if (!enabled)
-+		err = mtk_pwm_enable(chip, pwm);
-+
-+	return err;
-+}
-+
-+static const struct pwm_ops mtk_pwm_ops = {
-+	.apply = mtk_pwm_apply,
-+	.owner = THIS_MODULE,
-+};
-+
-+static int mtk_pwm_probe(struct platform_device *pdev)
-+{
-+	struct mtk_pwm_chip *pc;
-+	struct resource *r;
-+	int ret;
-+
-+	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
-+	if (!pc)
-+		return -ENOMEM;
-+
-+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
-+	if (IS_ERR(pc->mmio_base))
-+		return PTR_ERR(pc->mmio_base);
-+
-+	platform_set_drvdata(pdev, pc);
-+
-+	pc->chip.dev = &pdev->dev;
-+	pc->chip.ops = &mtk_pwm_ops;
-+	pc->chip.base = -1;
-+	pc->chip.npwm = NUM_PWM;
-+
-+	ret = pwmchip_add(&pc->chip);
-+	if (ret < 0)
-+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int mtk_pwm_remove(struct platform_device *pdev)
-+{
-+	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
-+	int i;
-+
-+	for (i = 0; i < NUM_PWM; i++)
-+		pwm_disable(&pc->chip.pwms[i]);
-+
-+	pwmchip_remove(&pc->chip);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id mtk_pwm_of_match[] = {
-+	{ .compatible = "mediatek,mt7628-pwm" },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
-+
-+static struct platform_driver mtk_pwm_driver = {
-+	.driver = {
-+		.name = "mtk-pwm",
-+		.owner = THIS_MODULE,
-+		.of_match_table = mtk_pwm_of_match,
-+	},
-+	.probe = mtk_pwm_probe,
-+	.remove = mtk_pwm_remove,
-+};
-+
-+module_platform_driver(mtk_pwm_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_ALIAS("platform:mtk-pwm");
diff --git a/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch b/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch
deleted file mode 100644
index 01ce44d700..0000000000
--- a/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch
+++ /dev/null
@@ -1,15 +0,0 @@
---- a/drivers/usb/dwc2/platform.c
-+++ b/drivers/usb/dwc2/platform.c
-@@ -462,6 +462,12 @@ static int dwc2_driver_probe(struct plat
- 	if (retval)
- 		return retval;
- 
-+	/* Enable USB port before any regs access */
-+	if (readl(hsotg->regs + PCGCTL) & 0x0f) {
-+		writel(0x00, hsotg->regs + PCGCTL);
-+		/* TODO: mdelay(25) here? vendor driver don't use it */
-+	}
-+
- 	hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
- 
- 	retval = dwc2_get_dr_mode(hsotg);
diff --git a/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch b/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch
deleted file mode 100644
index cd81601a72..0000000000
--- a/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch
+++ /dev/null
@@ -1,97 +0,0 @@
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -50,6 +50,7 @@ obj-$(CONFIG_ECHO)		+= echo/
- obj-$(CONFIG_CXL_BASE)		+= cxl/
- obj-$(CONFIG_DW_XDATA_PCIE)	+= dw-xdata-pcie.o
- obj-$(CONFIG_PCI_ENDPOINT_TEST)	+= pci_endpoint_test.o
-+obj-$(CONFIG_SOC_MT7620)	+= linkit.o
- obj-$(CONFIG_OCXL)		+= ocxl/
- obj-$(CONFIG_BCM_VK)		+= bcm-vk/
- obj-y				+= cardreader/
---- /dev/null
-+++ b/drivers/misc/linkit.c
-@@ -0,0 +1,84 @@
-+/*
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License version 2 as
-+ *  publishhed by the Free Software Foundation.
-+ *
-+ *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/of.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/gpio.h>
-+
-+#define LINKIT_LATCH_GPIO	11
-+
-+struct linkit_hw_data {
-+	char board[16];
-+	char rev[16];
-+};
-+
-+static void sanify_string(char *s)
-+{
-+	int i;
-+
-+	for (i = 0; i < 15; i++)
-+		if (s[i] <= 0x20)
-+			s[i] = '\0';
-+	s[15] = '\0';
-+}
-+
-+static int linkit_probe(struct platform_device *pdev)
-+{
-+	struct linkit_hw_data hw;
-+	struct mtd_info *mtd;
-+	size_t retlen;
-+	int ret;
-+
-+	mtd = get_mtd_device_nm("factory");
-+	if (IS_ERR(mtd))
-+		return PTR_ERR(mtd);
-+
-+	ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw);
-+	put_mtd_device(mtd);
-+
-+	sanify_string(hw.board);
-+	sanify_string(hw.rev);
-+
-+	dev_info(&pdev->dev, "Version  : %s\n", hw.board);
-+	dev_info(&pdev->dev, "Revision : %s\n", hw.rev);
-+
-+	if (!strcmp(hw.board, "LINKITS7688")) {
-+		dev_info(&pdev->dev, "setting up bootstrap latch\n");
-+
-+		if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) {
-+			dev_err(&pdev->dev, "failed to setup bootstrap gpio\n");
-+			return -1;
-+		}
-+		gpio_direction_output(LINKIT_LATCH_GPIO, 0);
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id linkit_match[] = {
-+	{ .compatible = "mediatek,linkit" },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, linkit_match);
-+
-+static struct platform_driver linkit_driver = {
-+	.probe = linkit_probe,
-+	.driver = {
-+		.name = "mtk-linkit",
-+		.owner = THIS_MODULE,
-+		.of_match_table = linkit_match,
-+	},
-+};
-+
-+int __init linkit_init(void)
-+{
-+	return platform_driver_register(&linkit_driver);
-+}
-+late_initcall_sync(linkit_init);
diff --git a/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch b/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch
deleted file mode 100644
index 275b81e715..0000000000
--- a/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch
+++ /dev/null
@@ -1,3276 +0,0 @@
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/Kconfig
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: GPL-2.0
-+config CRYPTO_DEV_EIP93_SKCIPHER
-+	tristate
-+
-+config CRYPTO_DEV_EIP93_HMAC
-+	tristate
-+
-+config CRYPTO_DEV_EIP93
-+	tristate "Support for EIP93 crypto HW accelerators"
-+	depends on SOC_MT7621 || COMPILE_TEST
-+	help
-+	  EIP93 have various crypto HW accelerators. Select this if
-+	  you want to use the EIP93 modules for any of the crypto algorithms.
-+
-+if CRYPTO_DEV_EIP93
-+
-+config CRYPTO_DEV_EIP93_AES
-+	bool "Register AES algorithm implementations with the Crypto API"
-+	default y
-+	select CRYPTO_DEV_EIP93_SKCIPHER
-+	select CRYPTO_LIB_AES
-+	select CRYPTO_SKCIPHER
-+	help
-+	  Selecting this will offload AES - ECB, CBC and CTR crypto
-+	  to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_DES
-+	bool "Register legacy DES / 3DES algorithm with the Crypto API"
-+	default y
-+	select CRYPTO_DEV_EIP93_SKCIPHER
-+	select CRYPTO_LIB_DES
-+	select CRYPTO_SKCIPHER
-+	help
-+	  Selecting this will offload DES and 3DES ECB and CBC
-+	  crypto to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_AEAD
-+  	bool "Register AEAD algorithm with the Crypto API"
-+  	default y
-+	select CRYPTO_DEV_EIP93_HMAC
-+	select CRYPTO_AEAD
-+	select CRYPTO_AUTHENC
-+	select CRYPTO_MD5
-+	select CRYPTO_SHA1
-+	select CRYPTO_SHA256
-+	help
-+	  Selecting this will offload AEAD authenc(hmac(x), cipher(y))
-+	  crypto to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN
-+	int "Max skcipher software fallback length"
-+	default 256
-+	help
-+	  Max length of crypt request which
-+	  will fallback to software crypt of skcipher *except* AES-128.
-+
-+config CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN
-+	int "Max AES-128 skcipher software fallback length"
-+	default 512
-+	help
-+	  Max length of crypt request which
-+	  will fallback to software crypt of AES-128 skcipher.
-+
-+endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/Makefile
-@@ -0,0 +1,7 @@
-+obj-$(CONFIG_CRYPTO_DEV_EIP93) += crypto-hw-eip93.o
-+
-+crypto-hw-eip93-y += eip93-main.o eip93-common.o
-+
-+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) += eip93-cipher.o
-+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_AEAD) += eip93-aead.o
-+
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aead.c
-@@ -0,0 +1,768 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <crypto/aead.h>
-+#include <crypto/aes.h>
-+#include <crypto/authenc.h>
-+#include <crypto/ctr.h>
-+#include <crypto/hmac.h>
-+#include <crypto/internal/aead.h>
-+#include <crypto/md5.h>
-+#include <crypto/null.h>
-+#include <crypto/sha1.h>
-+#include <crypto/sha2.h>
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include <crypto/internal/des.h>
-+#endif
-+
-+#include <linux/crypto.h>
-+#include <linux/dma-mapping.h>
-+
-+#include "eip93-aead.h"
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-regs.h"
-+
-+void mtk_aead_handle_result(struct crypto_async_request *async, int err)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+	struct mtk_device *mtk = ctx->mtk;
-+	struct aead_request *req = aead_request_cast(async);
-+	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+
-+	mtk_unmap_dma(mtk, rctx, req->src, req->dst);
-+	mtk_handle_result(mtk, rctx, req->iv);
-+
-+	if (err == 1)
-+		err = -EBADMSG;
-+	/* let software handle anti-replay errors */
-+	if (err == 4)
-+		err = 0;
-+
-+	aead_request_complete(req, err);
-+}
-+
-+static int mtk_aead_send_req(struct crypto_async_request *async)
-+{
-+	struct aead_request *req = aead_request_cast(async);
-+	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+	int err;
-+
-+	err = check_valid_request(rctx);
-+	if (err) {
-+		aead_request_complete(req, err);
-+		return err;
-+	}
-+
-+	return mtk_send_req(async, req->iv, rctx);
-+}
-+
-+/* Crypto aead API functions */
-+static int mtk_aead_cra_init(struct crypto_tfm *tfm)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+				struct mtk_alg_template, alg.aead.base);
-+	u32 flags = tmpl->flags;
-+	char *alg_base;
-+
-+	crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
-+			sizeof(struct mtk_cipher_reqctx));
-+
-+	ctx->mtk = tmpl->mtk;
-+	ctx->in_first = true;
-+	ctx->out_first = true;
-+
-+	ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+	if (!ctx->sa_in)
-+		return -ENOMEM;
-+
-+	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+	ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+	if (!ctx->sa_out)
-+		return -ENOMEM;
-+
-+	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+	/* software workaround for now */
-+	if (IS_HASH_MD5(flags))
-+		alg_base = "md5";
-+	if (IS_HASH_SHA1(flags))
-+		alg_base = "sha1";
-+	if (IS_HASH_SHA224(flags))
-+		alg_base = "sha224";
-+	if (IS_HASH_SHA256(flags))
-+		alg_base = "sha256";
-+
-+	ctx->shash = crypto_alloc_shash(alg_base, 0, CRYPTO_ALG_NEED_FALLBACK);
-+
-+	if (IS_ERR(ctx->shash)) {
-+		dev_err(ctx->mtk->dev, "base driver %s could not be loaded.\n",
-+				alg_base);
-+		return PTR_ERR(ctx->shash);
-+	}
-+
-+	return 0;
-+}
-+
-+static void mtk_aead_cra_exit(struct crypto_tfm *tfm)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+	if (ctx->shash)
-+		crypto_free_shash(ctx->shash);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	kfree(ctx->sa_in);
-+	kfree(ctx->sa_out);
-+}
-+
-+static int mtk_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
-+			unsigned int len)
-+{
-+	struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+				struct mtk_alg_template, alg.skcipher.base);
-+	u32 flags = tmpl->flags;
-+	u32 nonce = 0;
-+	struct crypto_authenc_keys keys;
-+	struct crypto_aes_ctx aes;
-+	struct saRecord_s *saRecord = ctx->sa_out;
-+	int sa_size = sizeof(struct saRecord_s);
-+	int err = -EINVAL;
-+
-+
-+	if (crypto_authenc_extractkeys(&keys, key, len))
-+		return err;
-+
-+	if (IS_RFC3686(flags)) {
-+		if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
-+			return err;
-+
-+		keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
-+		memcpy(&nonce, keys.enckey + keys.enckeylen,
-+						CTR_RFC3686_NONCE_SIZE);
-+	}
-+
-+	switch ((flags & MTK_ALG_MASK)) {
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+	case MTK_ALG_DES:
-+		err = verify_aead_des_key(ctfm, keys.enckey, keys.enckeylen);
-+		break;
-+	case MTK_ALG_3DES:
-+		if (keys.enckeylen != DES3_EDE_KEY_SIZE)
-+			return -EINVAL;
-+
-+		err = verify_aead_des3_key(ctfm, keys.enckey, keys.enckeylen);
-+		break;
-+#endif
-+	case MTK_ALG_AES:
-+		err = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
-+	}
-+	if (err)
-+		return err;
-+
-+	ctx->blksize = crypto_aead_blocksize(ctfm);
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
-+								DMA_TO_DEVICE);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
-+								DMA_TO_DEVICE);
-+	/* Encryption key */
-+	mtk_set_saRecord(saRecord, keys.enckeylen, flags);
-+	saRecord->saCmd0.bits.opCode = 1;
-+	saRecord->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+
-+	memcpy(saRecord->saKey, keys.enckey, keys.enckeylen);
-+	ctx->saNonce = nonce;
-+	saRecord->saNonce = nonce;
-+
-+	/* authentication key */
-+	err = mtk_authenc_setkey(ctx->shash, saRecord, keys.authkey,
-+							keys.authkeylen);
-+
-+	saRecord->saCmd0.bits.direction = 0;
-+	memcpy(ctx->sa_in, saRecord, sa_size);
-+	ctx->sa_in->saCmd0.bits.direction = 1;
-+	ctx->sa_in->saCmd1.bits.copyDigest = 0;
-+
-+	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
-+								DMA_TO_DEVICE);
-+	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
-+								DMA_TO_DEVICE);
-+	ctx->in_first = true;
-+	ctx->out_first = true;
-+
-+	return err;
-+}
-+
-+static int mtk_aead_setauthsize(struct crypto_aead *ctfm,
-+				unsigned int authsize)
-+{
-+	struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+	ctx->authsize = authsize;
-+	ctx->sa_in->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+	ctx->sa_out->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+
-+	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	return 0;
-+}
-+
-+static void mtk_aead_setassoc(struct mtk_crypto_ctx *ctx,
-+			struct aead_request *req, bool in)
-+{
-+	struct saRecord_s *saRecord;
-+
-+	if (in) {
-+		dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+		saRecord = ctx->sa_in;
-+		saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
-+
-+		ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+		ctx->assoclen_in = req->assoclen;
-+	} else {
-+		dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+		saRecord = ctx->sa_out;
-+		saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
-+
-+		ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+		ctx->assoclen_out = req->assoclen;
-+	}
-+}
-+
-+static int mtk_aead_crypt(struct aead_request *req)
-+{
-+	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+	struct crypto_async_request *async = &req->base;
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+
-+	rctx->textsize = req->cryptlen;
-+	rctx->blksize = ctx->blksize;
-+	rctx->assoclen = req->assoclen;
-+	rctx->authsize = ctx->authsize;
-+	rctx->sg_src = req->src;
-+	rctx->sg_dst = req->dst;
-+	rctx->ivsize = crypto_aead_ivsize(aead);
-+	rctx->flags |= MTK_DESC_AEAD;
-+
-+	if IS_DECRYPT(rctx->flags)
-+		rctx->textsize -= rctx->authsize;
-+
-+	return mtk_aead_send_req(async);
-+}
-+
-+static int mtk_aead_encrypt(struct aead_request *req)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+				struct mtk_alg_template, alg.aead.base);
-+
-+	rctx->flags = tmpl->flags;
-+	rctx->flags |= MTK_ENCRYPT;
-+	if (ctx->out_first) {
-+		mtk_aead_setassoc(ctx, req, false);
-+		ctx->out_first = false;
-+	}
-+
-+	if (req->assoclen != ctx->assoclen_out) {
-+		dev_err(ctx->mtk->dev, "Request AAD length error\n");
-+		return -EINVAL;
-+	}
-+
-+	rctx->saRecord_base = ctx->sa_base_out;
-+
-+	return mtk_aead_crypt(req);
-+}
-+
-+static int mtk_aead_decrypt(struct aead_request *req)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+				struct mtk_alg_template, alg.aead.base);
-+
-+	rctx->flags = tmpl->flags;
-+	rctx->flags |= MTK_DECRYPT;
-+	if (ctx->in_first) {
-+		mtk_aead_setassoc(ctx, req, true);
-+		ctx->in_first = false;
-+	}
-+
-+	if (req->assoclen != ctx->assoclen_in) {
-+		dev_err(ctx->mtk->dev, "Request AAD length error\n");
-+		return -EINVAL;
-+	}
-+
-+	rctx->saRecord_base = ctx->sa_base_in;
-+
-+	return mtk_aead_crypt(req);
-+}
-+
-+/* Available authenc algorithms in this module */
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = MD5_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(md5),cbc(aes))",
-+			.cra_driver_name =
-+				"authenc(hmac(md5-eip93), cbc(aes-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA1_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha1),cbc(aes))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha1-eip93),cbc(aes-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA224_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha224),cbc(aes))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha224-eip93),cbc(aes-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA256_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha256),cbc(aes))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha256-eip93),cbc(aes-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 |
-+			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= CTR_RFC3686_IV_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = MD5_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(md5),rfc3686(ctr(aes)))",
-+			.cra_driver_name =
-+			"authenc(hmac(md5-eip93),rfc3686(ctr(aes-eip93)))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 |
-+			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= CTR_RFC3686_IV_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA1_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
-+			.cra_driver_name =
-+			"authenc(hmac(sha1-eip93),rfc3686(ctr(aes-eip93)))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 |
-+			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= CTR_RFC3686_IV_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA224_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
-+			.cra_driver_name =
-+			"authenc(hmac(sha224-eip93),rfc3686(ctr(aes-eip93)))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 |
-+			MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= CTR_RFC3686_IV_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA256_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
-+			.cra_driver_name =
-+			"authenc(hmac(sha256-eip93),rfc3686(ctr(aes-eip93)))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = MD5_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(md5),cbc(des))",
-+			.cra_driver_name =
-+				"authenc(hmac(md5-eip93),cbc(des-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA1_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha1),cbc(des))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha1-eip93),cbc(des-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA224_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha224),cbc(des))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha224-eip93),cbc(des-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA256_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha256),cbc(des))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha256-eip93),cbc(des-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_3DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES3_EDE_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = MD5_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
-+			.cra_driver_name =
-+				"authenc(hmac(md5-eip93),cbc(des3_ede-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0x0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_3DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES3_EDE_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA1_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
-+			.cra_driver_name =
-+				"authenc(hmac(sha1-eip93),cbc(des3_ede-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0x0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_3DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES3_EDE_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA224_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
-+			.cra_driver_name =
-+			"authenc(hmac(sha224-eip93),cbc(des3_ede-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0x0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede = {
-+	.type = MTK_ALG_TYPE_AEAD,
-+	.flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_3DES,
-+	.alg.aead = {
-+		.setkey = mtk_aead_setkey,
-+		.encrypt = mtk_aead_encrypt,
-+		.decrypt = mtk_aead_decrypt,
-+		.ivsize	= DES3_EDE_BLOCK_SIZE,
-+		.setauthsize = mtk_aead_setauthsize,
-+		.maxauthsize = SHA256_DIGEST_SIZE,
-+		.base = {
-+			.cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
-+			.cra_driver_name =
-+			"authenc(hmac(sha256-eip93),cbc(des3_ede-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0x0,
-+			.cra_init = mtk_aead_cra_init,
-+			.cra_exit = mtk_aead_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aead.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_AEAD_H_
-+#define _EIP93_AEAD_H_
-+
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede;
-+#endif
-+
-+void mtk_aead_handle_result(struct crypto_async_request *async, int err);
-+
-+#endif /* _EIP93_AEAD_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aes.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_AES_H_
-+#define _EIP93_AES_H_
-+
-+extern struct mtk_alg_template mtk_alg_ecb_aes;
-+extern struct mtk_alg_template mtk_alg_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_ctr_aes;
-+extern struct mtk_alg_template mtk_alg_rfc3686_aes;
-+
-+#endif /* _EIP93_AES_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-cipher.c
-@@ -0,0 +1,483 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+#include <crypto/aes.h>
-+#include <crypto/ctr.h>
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include <crypto/internal/des.h>
-+#endif
-+#include <linux/dma-mapping.h>
-+
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-regs.h"
-+
-+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+	struct mtk_device *mtk = ctx->mtk;
-+	struct skcipher_request *req = skcipher_request_cast(async);
-+	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+
-+	mtk_unmap_dma(mtk, rctx, req->src, req->dst);
-+	mtk_handle_result(mtk, rctx, req->iv);
-+
-+	skcipher_request_complete(req, err);
-+}
-+
-+static inline bool mtk_skcipher_is_fallback(const struct crypto_tfm *tfm,
-+					    u32 flags)
-+{
-+	return (tfm->__crt_alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) &&
-+	       !IS_RFC3686(flags);
-+}
-+
-+static int mtk_skcipher_send_req(struct crypto_async_request *async)
-+{
-+	struct skcipher_request *req = skcipher_request_cast(async);
-+	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+	int err;
-+
-+	err = check_valid_request(rctx);
-+
-+	if (err) {
-+		skcipher_request_complete(req, err);
-+		return err;
-+	}
-+
-+	return mtk_send_req(async, req->iv, rctx);
-+}
-+
-+/* Crypto skcipher API functions */
-+static int mtk_skcipher_cra_init(struct crypto_tfm *tfm)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+				struct mtk_alg_template, alg.skcipher.base);
-+	bool fallback = mtk_skcipher_is_fallback(tfm, tmpl->flags);
-+
-+	if (fallback) {
-+		ctx->fallback = crypto_alloc_skcipher(
-+			crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_NEED_FALLBACK);
-+		if (IS_ERR(ctx->fallback))
-+			return PTR_ERR(ctx->fallback);
-+	}
-+
-+	crypto_skcipher_set_reqsize(
-+		__crypto_skcipher_cast(tfm),
-+		sizeof(struct mtk_cipher_reqctx) +
-+			(fallback ? crypto_skcipher_reqsize(ctx->fallback) :
-+					  0));
-+
-+	ctx->mtk = tmpl->mtk;
-+
-+	ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+	if (!ctx->sa_in)
-+		return -ENOMEM;
-+
-+	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+	ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+	if (!ctx->sa_out)
-+		return -ENOMEM;
-+
-+	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+				sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	return 0;
-+}
-+
-+static void mtk_skcipher_cra_exit(struct crypto_tfm *tfm)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+			sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+	kfree(ctx->sa_in);
-+	kfree(ctx->sa_out);
-+
-+	crypto_free_skcipher(ctx->fallback);
-+}
-+
-+static int mtk_skcipher_setkey(struct crypto_skcipher *ctfm, const u8 *key,
-+				 unsigned int len)
-+{
-+	struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+	struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+				struct mtk_alg_template, alg.skcipher.base);
-+	struct saRecord_s *saRecord = ctx->sa_out;
-+	u32 flags = tmpl->flags;
-+	u32 nonce = 0;
-+	unsigned int keylen = len;
-+	int sa_size = sizeof(struct saRecord_s);
-+	int err = -EINVAL;
-+
-+	if (!key || !keylen)
-+		return err;
-+
-+	ctx->keylen = keylen;
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+	if (IS_RFC3686(flags)) {
-+		if (len < CTR_RFC3686_NONCE_SIZE)
-+			return err;
-+
-+		keylen = len - CTR_RFC3686_NONCE_SIZE;
-+		memcpy(&nonce, key + keylen, CTR_RFC3686_NONCE_SIZE);
-+	}
-+#endif
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+	if (flags & MTK_ALG_DES) {
-+		ctx->blksize = DES_BLOCK_SIZE;
-+		err = verify_skcipher_des_key(ctfm, key);
-+	}
-+	if (flags & MTK_ALG_3DES) {
-+		ctx->blksize = DES3_EDE_BLOCK_SIZE;
-+		err = verify_skcipher_des3_key(ctfm, key);
-+	}
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+	if (flags & MTK_ALG_AES) {
-+		struct crypto_aes_ctx aes;
-+		bool fallback = mtk_skcipher_is_fallback(tfm, flags);
-+
-+		if (fallback && !IS_RFC3686(flags)) {
-+			err = crypto_skcipher_setkey(ctx->fallback, key,
-+						     keylen);
-+			if (err)
-+				return err;
-+		}
-+
-+		ctx->blksize = AES_BLOCK_SIZE;
-+		err = aes_expandkey(&aes, key, keylen);
-+	}
-+#endif
-+	if (err)
-+		return err;
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
-+								DMA_TO_DEVICE);
-+
-+	dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
-+								DMA_TO_DEVICE);
-+
-+	mtk_set_saRecord(saRecord, keylen, flags);
-+
-+	memcpy(saRecord->saKey, key, keylen);
-+	ctx->saNonce = nonce;
-+	saRecord->saNonce = nonce;
-+	saRecord->saCmd0.bits.direction = 0;
-+
-+	memcpy(ctx->sa_in, saRecord, sa_size);
-+	ctx->sa_in->saCmd0.bits.direction = 1;
-+
-+	ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
-+								DMA_TO_DEVICE);
-+
-+	ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
-+								DMA_TO_DEVICE);
-+	return err;
-+}
-+
-+static int mtk_skcipher_crypt(struct skcipher_request *req, bool encrypt)
-+{
-+	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+	struct crypto_async_request *async = &req->base;
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	bool fallback = mtk_skcipher_is_fallback(req->base.tfm, rctx->flags);
-+
-+	if (!req->cryptlen)
-+		return 0;
-+
-+	/*
-+	 * ECB and CBC algorithms require message lengths to be
-+	 * multiples of block size.
-+	 */
-+	if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
-+		if (!IS_ALIGNED(req->cryptlen,
-+				crypto_skcipher_blocksize(skcipher)))
-+			return -EINVAL;
-+
-+	if (fallback &&
-+	    req->cryptlen <= (AES_KEYSIZE_128 ?
-+				      CONFIG_CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN :
-+				      CONFIG_CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN)) {
-+		skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
-+		skcipher_request_set_callback(&rctx->fallback_req,
-+					      req->base.flags,
-+					      req->base.complete,
-+					      req->base.data);
-+		skcipher_request_set_crypt(&rctx->fallback_req, req->src,
-+					   req->dst, req->cryptlen, req->iv);
-+		return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
-+				 crypto_skcipher_decrypt(&rctx->fallback_req);
-+	}
-+
-+	rctx->assoclen = 0;
-+	rctx->textsize = req->cryptlen;
-+	rctx->authsize = 0;
-+	rctx->sg_src = req->src;
-+	rctx->sg_dst = req->dst;
-+	rctx->ivsize = crypto_skcipher_ivsize(skcipher);
-+	rctx->blksize = ctx->blksize;
-+	rctx->flags |= MTK_DESC_SKCIPHER;
-+	if (!IS_ECB(rctx->flags))
-+		rctx->flags |= MTK_DESC_DMA_IV;
-+
-+	return mtk_skcipher_send_req(async);
-+}
-+
-+static int mtk_skcipher_encrypt(struct skcipher_request *req)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+				struct mtk_alg_template, alg.skcipher.base);
-+
-+	rctx->flags = tmpl->flags;
-+	rctx->flags |= MTK_ENCRYPT;
-+	rctx->saRecord_base = ctx->sa_base_out;
-+
-+	return mtk_skcipher_crypt(req, true);
-+}
-+
-+static int mtk_skcipher_decrypt(struct skcipher_request *req)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+	struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+	struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+				struct mtk_alg_template, alg.skcipher.base);
-+
-+	rctx->flags = tmpl->flags;
-+	rctx->flags |= MTK_DECRYPT;
-+	rctx->saRecord_base = ctx->sa_base_in;
-+
-+	return mtk_skcipher_crypt(req, false);
-+}
-+
-+/* Available algorithms in this module */
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+struct mtk_alg_template mtk_alg_ecb_aes = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_ECB | MTK_ALG_AES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = AES_MIN_KEY_SIZE,
-+		.max_keysize = AES_MAX_KEY_SIZE,
-+		.ivsize	= 0,
-+		.base = {
-+			.cra_name = "ecb(aes)",
-+			.cra_driver_name = "ecb(aes-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_NEED_FALLBACK |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0xf,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_aes = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_CBC | MTK_ALG_AES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = AES_MIN_KEY_SIZE,
-+		.max_keysize = AES_MAX_KEY_SIZE,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.base = {
-+			.cra_name = "cbc(aes)",
-+			.cra_driver_name = "cbc(aes-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_NEED_FALLBACK |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = AES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0xf,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_ctr_aes = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_CTR | MTK_ALG_AES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = AES_MIN_KEY_SIZE,
-+		.max_keysize = AES_MAX_KEY_SIZE,
-+		.ivsize	= AES_BLOCK_SIZE,
-+		.base = {
-+			.cra_name = "ctr(aes)",
-+			.cra_driver_name = "ctr(aes-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+				     CRYPTO_ALG_NEED_FALLBACK |
-+				     CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0xf,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_rfc3686_aes = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
-+		.max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
-+		.ivsize	= CTR_RFC3686_IV_SIZE,
-+		.base = {
-+			.cra_name = "rfc3686(ctr(aes))",
-+			.cra_driver_name = "rfc3686(ctr(aes-eip93))",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_NEED_FALLBACK |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = 1,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0xf,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+struct mtk_alg_template mtk_alg_ecb_des = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_ECB | MTK_ALG_DES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = DES_KEY_SIZE,
-+		.max_keysize = DES_KEY_SIZE,
-+		.ivsize	= 0,
-+		.base = {
-+			.cra_name = "ecb(des)",
-+			.cra_driver_name = "ebc(des-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_des = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_CBC | MTK_ALG_DES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = DES_KEY_SIZE,
-+		.max_keysize = DES_KEY_SIZE,
-+		.ivsize	= DES_BLOCK_SIZE,
-+		.base = {
-+			.cra_name = "cbc(des)",
-+			.cra_driver_name = "cbc(des-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_ecb_des3_ede = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_ECB | MTK_ALG_3DES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = DES3_EDE_KEY_SIZE,
-+		.max_keysize = DES3_EDE_KEY_SIZE,
-+		.ivsize	= 0,
-+		.base = {
-+			.cra_name = "ecb(des3_ede)",
-+			.cra_driver_name = "ecb(des3_ede-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_des3_ede = {
-+	.type = MTK_ALG_TYPE_SKCIPHER,
-+	.flags = MTK_MODE_CBC | MTK_ALG_3DES,
-+	.alg.skcipher = {
-+		.setkey = mtk_skcipher_setkey,
-+		.encrypt = mtk_skcipher_encrypt,
-+		.decrypt = mtk_skcipher_decrypt,
-+		.min_keysize = DES3_EDE_KEY_SIZE,
-+		.max_keysize = DES3_EDE_KEY_SIZE,
-+		.ivsize	= DES3_EDE_BLOCK_SIZE,
-+		.base = {
-+			.cra_name = "cbc(des3_ede)",
-+			.cra_driver_name = "cbc(des3_ede-eip93)",
-+			.cra_priority = MTK_CRA_PRIORITY,
-+			.cra_flags = CRYPTO_ALG_ASYNC |
-+					CRYPTO_ALG_KERN_DRIVER_ONLY,
-+			.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			.cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+			.cra_alignmask = 0,
-+			.cra_init = mtk_skcipher_cra_init,
-+			.cra_exit = mtk_skcipher_cra_exit,
-+			.cra_module = THIS_MODULE,
-+		},
-+	},
-+};
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-cipher.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_CIPHER_H_
-+#define _EIP93_CIPHER_H_
-+
-+#include "eip93-main.h"
-+
-+struct mtk_crypto_ctx {
-+	struct mtk_device		*mtk;
-+	struct saRecord_s		*sa_in;
-+	dma_addr_t			sa_base_in;
-+	struct saRecord_s		*sa_out;
-+	dma_addr_t			sa_base_out;
-+	uint32_t			saNonce;
-+	int				blksize;
-+	/* AEAD specific */
-+	unsigned int			authsize;
-+	unsigned int			assoclen_in;
-+	unsigned int			assoclen_out;
-+	bool				in_first;
-+	bool				out_first;
-+	struct crypto_shash		*shash;
-+	unsigned int keylen;
-+	struct crypto_skcipher *fallback;
-+};
-+
-+struct mtk_cipher_reqctx {
-+	unsigned long			flags;
-+	unsigned int			blksize;
-+	unsigned int			ivsize;
-+	unsigned int			textsize;
-+	unsigned int			assoclen;
-+	unsigned int			authsize;
-+	dma_addr_t			saRecord_base;
-+	struct saState_s		*saState;
-+	dma_addr_t			saState_base;
-+	uint32_t			saState_idx;
-+	struct eip93_descriptor_s	*cdesc;
-+	struct scatterlist		*sg_src;
-+	struct scatterlist		*sg_dst;
-+	int				src_nents;
-+	int				dst_nents;
-+	struct saState_s		*saState_ctr;
-+	dma_addr_t			saState_base_ctr;
-+	uint32_t			saState_ctr_idx;
-+	struct skcipher_request fallback_req; // keep at the end
-+};
-+
-+int check_valid_request(struct mtk_cipher_reqctx *rctx);
-+
-+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+			struct scatterlist *reqsrc, struct scatterlist *reqdst);
-+
-+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err);
-+
-+int mtk_send_req(struct crypto_async_request *async,
-+			const u8 *reqiv, struct mtk_cipher_reqctx *rctx);
-+
-+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+			u8 *reqiv);
-+
-+#endif /* _EIP93_CIPHER_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-common.c
-@@ -0,0 +1,749 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <crypto/aes.h>
-+#include <crypto/ctr.h>
-+#include <crypto/hmac.h>
-+#include <crypto/sha1.h>
-+#include <crypto/sha2.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/scatterlist.h>
-+
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-main.h"
-+#include "eip93-regs.h"
-+
-+inline void *mtk_ring_next_wptr(struct mtk_device *mtk,
-+						struct mtk_desc_ring *ring)
-+{
-+	void *ptr = ring->write;
-+
-+	if ((ring->write == ring->read - ring->offset) ||
-+		(ring->read == ring->base && ring->write == ring->base_end))
-+		return ERR_PTR(-ENOMEM);
-+
-+	if (ring->write == ring->base_end)
-+		ring->write = ring->base;
-+	else
-+		ring->write += ring->offset;
-+
-+	return ptr;
-+}
-+
-+inline void *mtk_ring_next_rptr(struct mtk_device *mtk,
-+						struct mtk_desc_ring *ring)
-+{
-+	void *ptr = ring->read;
-+
-+	if (ring->write == ring->read)
-+		return ERR_PTR(-ENOENT);
-+
-+	if (ring->read == ring->base_end)
-+		ring->read = ring->base;
-+	else
-+		ring->read += ring->offset;
-+
-+	return ptr;
-+}
-+
-+inline int mtk_put_descriptor(struct mtk_device *mtk,
-+					struct eip93_descriptor_s *desc)
-+{
-+	struct eip93_descriptor_s *cdesc;
-+	struct eip93_descriptor_s *rdesc;
-+	unsigned long irqflags;
-+
-+	spin_lock_irqsave(&mtk->ring->write_lock, irqflags);
-+
-+	rdesc = mtk_ring_next_wptr(mtk, &mtk->ring->rdr);
-+
-+	if (IS_ERR(rdesc)) {
-+		spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+		return -ENOENT;
-+	}
-+
-+	cdesc = mtk_ring_next_wptr(mtk, &mtk->ring->cdr);
-+
-+	if (IS_ERR(cdesc)) {
-+		spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+		return -ENOENT;
-+	}
-+
-+	memset(rdesc, 0, sizeof(struct eip93_descriptor_s));
-+	memcpy(cdesc, desc, sizeof(struct eip93_descriptor_s));
-+
-+	atomic_dec(&mtk->ring->free);
-+	spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+
-+	return 0;
-+}
-+
-+inline void *mtk_get_descriptor(struct mtk_device *mtk)
-+{
-+	struct eip93_descriptor_s *cdesc;
-+	void *ptr;
-+	unsigned long irqflags;
-+
-+	spin_lock_irqsave(&mtk->ring->read_lock, irqflags);
-+
-+	cdesc = mtk_ring_next_rptr(mtk, &mtk->ring->cdr);
-+
-+	if (IS_ERR(cdesc)) {
-+		spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+		return ERR_PTR(-ENOENT);
-+	}
-+
-+	memset(cdesc, 0, sizeof(struct eip93_descriptor_s));
-+
-+	ptr = mtk_ring_next_rptr(mtk, &mtk->ring->rdr);
-+	if (IS_ERR(ptr)) {
-+		spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+		return ERR_PTR(-ENOENT);
-+	}
-+
-+	atomic_inc(&mtk->ring->free);
-+	spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+
-+	return ptr;
-+}
-+
-+inline int mtk_get_free_saState(struct mtk_device *mtk)
-+{
-+	struct mtk_state_pool *saState_pool;
-+	int i;
-+
-+	for (i = 0; i < MTK_RING_SIZE; i++) {
-+		saState_pool = &mtk->ring->saState_pool[i];
-+		if (saState_pool->in_use == false) {
-+			saState_pool->in_use = true;
-+			return i;
-+		}
-+
-+	}
-+
-+	return -ENOENT;
-+}
-+
-+static inline void mtk_free_sg_copy(const int len, struct scatterlist **sg)
-+{
-+	if (!*sg || !len)
-+		return;
-+
-+	free_pages((unsigned long)sg_virt(*sg), get_order(len));
-+	kfree(*sg);
-+	*sg = NULL;
-+}
-+
-+static inline int mtk_make_sg_copy(struct scatterlist *src,
-+			struct scatterlist **dst,
-+			const uint32_t len, const bool copy)
-+{
-+	void *pages;
-+
-+	*dst = kmalloc(sizeof(**dst), GFP_KERNEL);
-+	if (!*dst)
-+		return -ENOMEM;
-+
-+
-+	pages = (void *)__get_free_pages(GFP_KERNEL | GFP_DMA,
-+					get_order(len));
-+
-+	if (!pages) {
-+		kfree(*dst);
-+		*dst = NULL;
-+		return -ENOMEM;
-+	}
-+
-+	sg_init_table(*dst, 1);
-+	sg_set_buf(*dst, pages, len);
-+
-+	/* copy only as requested */
-+	if (copy)
-+		sg_copy_to_buffer(src, sg_nents(src), pages, len);
-+
-+	return 0;
-+}
-+
-+static inline bool mtk_is_sg_aligned(struct scatterlist *sg, u32 len,
-+						const int blksize)
-+{
-+	int nents;
-+
-+	for (nents = 0; sg; sg = sg_next(sg), ++nents) {
-+		if (!IS_ALIGNED(sg->offset, 4))
-+			return false;
-+
-+		if (len <= sg->length) {
-+			if (!IS_ALIGNED(len, blksize))
-+				return false;
-+
-+			return true;
-+		}
-+
-+		if (!IS_ALIGNED(sg->length, blksize))
-+			return false;
-+
-+		len -= sg->length;
-+	}
-+	return false;
-+}
-+
-+int check_valid_request(struct mtk_cipher_reqctx *rctx)
-+{
-+	struct scatterlist *src = rctx->sg_src;
-+	struct scatterlist *dst = rctx->sg_dst;
-+	uint32_t src_nents, dst_nents;
-+	u32 textsize = rctx->textsize;
-+	u32 authsize = rctx->authsize;
-+	u32 blksize = rctx->blksize;
-+	u32 totlen_src = rctx->assoclen + rctx->textsize;
-+	u32 totlen_dst = rctx->assoclen + rctx->textsize;
-+	u32 copy_len;
-+	bool src_align, dst_align;
-+	int err = -EINVAL;
-+
-+	if (!IS_CTR(rctx->flags)) {
-+		if (!IS_ALIGNED(textsize, blksize))
-+			return err;
-+	}
-+
-+	if (authsize) {
-+		if (IS_ENCRYPT(rctx->flags))
-+			totlen_dst += authsize;
-+		else
-+			totlen_src += authsize;
-+	}
-+
-+	src_nents = sg_nents_for_len(src, totlen_src);
-+	dst_nents = sg_nents_for_len(dst, totlen_dst);
-+
-+	if (src == dst) {
-+		src_nents = max(src_nents, dst_nents);
-+		dst_nents = src_nents;
-+		if (unlikely((totlen_src || totlen_dst) && (src_nents <= 0)))
-+			return err;
-+
-+	} else {
-+		if (unlikely(totlen_src && (src_nents <= 0)))
-+			return err;
-+
-+		if (unlikely(totlen_dst && (dst_nents <= 0)))
-+			return err;
-+	}
-+
-+	if (authsize) {
-+		if (dst_nents == 1 && src_nents == 1) {
-+			src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
-+			if (src ==  dst)
-+				dst_align = src_align;
-+			else
-+				dst_align = mtk_is_sg_aligned(dst,
-+						totlen_dst, blksize);
-+		} else {
-+			src_align = false;
-+			dst_align = false;
-+		}
-+	} else {
-+		src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
-+		if (src == dst)
-+			dst_align = src_align;
-+		else
-+			dst_align = mtk_is_sg_aligned(dst, totlen_dst, blksize);
-+	}
-+
-+	copy_len = max(totlen_src, totlen_dst);
-+	if (!src_align) {
-+		err = mtk_make_sg_copy(src, &rctx->sg_src, copy_len, true);
-+		if (err)
-+			return err;
-+	}
-+
-+	if (!dst_align) {
-+		err = mtk_make_sg_copy(dst, &rctx->sg_dst, copy_len, false);
-+		if (err)
-+			return err;
-+	}
-+
-+	rctx->src_nents = sg_nents_for_len(rctx->sg_src, totlen_src);
-+	rctx->dst_nents = sg_nents_for_len(rctx->sg_dst, totlen_dst);
-+
-+	return 0;
-+}
-+/*
-+ * Set saRecord function:
-+ * Even saRecord is set to "0", keep " = 0" for readability.
-+ */
-+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
-+				const u32 flags)
-+{
-+	saRecord->saCmd0.bits.ivSource = 2;
-+	if (IS_ECB(flags))
-+		saRecord->saCmd0.bits.saveIv = 0;
-+	else
-+		saRecord->saCmd0.bits.saveIv = 1;
-+
-+	saRecord->saCmd0.bits.opGroup = 0;
-+	saRecord->saCmd0.bits.opCode = 0;
-+
-+	switch ((flags & MTK_ALG_MASK)) {
-+	case MTK_ALG_AES:
-+		saRecord->saCmd0.bits.cipher = 3;
-+		saRecord->saCmd1.bits.aesKeyLen = keylen >> 3;
-+		break;
-+	case MTK_ALG_3DES:
-+		saRecord->saCmd0.bits.cipher = 1;
-+		break;
-+	case MTK_ALG_DES:
-+		saRecord->saCmd0.bits.cipher = 0;
-+		break;
-+	default:
-+		saRecord->saCmd0.bits.cipher = 15;
-+	}
-+
-+	switch ((flags & MTK_HASH_MASK)) {
-+	case MTK_HASH_SHA256:
-+		saRecord->saCmd0.bits.hash = 3;
-+		break;
-+	case MTK_HASH_SHA224:
-+		saRecord->saCmd0.bits.hash = 2;
-+		break;
-+	case MTK_HASH_SHA1:
-+		saRecord->saCmd0.bits.hash = 1;
-+		break;
-+	case MTK_HASH_MD5:
-+		saRecord->saCmd0.bits.hash = 0;
-+		break;
-+	default:
-+		saRecord->saCmd0.bits.hash = 15;
-+	}
-+
-+	saRecord->saCmd0.bits.hdrProc = 0;
-+	saRecord->saCmd0.bits.padType = 3;
-+	saRecord->saCmd0.bits.extPad = 0;
-+	saRecord->saCmd0.bits.scPad = 0;
-+
-+	switch ((flags & MTK_MODE_MASK)) {
-+	case MTK_MODE_CBC:
-+		saRecord->saCmd1.bits.cipherMode = 1;
-+		break;
-+	case MTK_MODE_CTR:
-+		saRecord->saCmd1.bits.cipherMode = 2;
-+		break;
-+	case MTK_MODE_ECB:
-+		saRecord->saCmd1.bits.cipherMode = 0;
-+		break;
-+	}
-+
-+	saRecord->saCmd1.bits.byteOffset = 0;
-+	saRecord->saCmd1.bits.hashCryptOffset = 0;
-+	saRecord->saCmd0.bits.digestLength = 0;
-+	saRecord->saCmd1.bits.copyPayload = 0;
-+
-+	if (IS_HMAC(flags)) {
-+		saRecord->saCmd1.bits.hmac = 1;
-+		saRecord->saCmd1.bits.copyDigest = 1;
-+		saRecord->saCmd1.bits.copyHeader = 1;
-+	} else {
-+		saRecord->saCmd1.bits.hmac = 0;
-+		saRecord->saCmd1.bits.copyDigest = 0;
-+		saRecord->saCmd1.bits.copyHeader = 0;
-+	}
-+
-+	saRecord->saCmd1.bits.seqNumCheck = 0;
-+	saRecord->saSpi = 0x0;
-+	saRecord->saSeqNumMask[0] = 0xFFFFFFFF;
-+	saRecord->saSeqNumMask[1] = 0x0;
-+}
-+
-+/*
-+ * Poor mans Scatter/gather function:
-+ * Create a Descriptor for every segment to avoid copying buffers.
-+ * For performance better to wait for hardware to perform multiple DMA
-+ *
-+ */
-+static inline int mtk_scatter_combine(struct mtk_device *mtk,
-+			struct mtk_cipher_reqctx *rctx,
-+			u32 datalen, u32 split, int offsetin)
-+{
-+	struct eip93_descriptor_s *cdesc = rctx->cdesc;
-+	struct scatterlist *sgsrc = rctx->sg_src;
-+	struct scatterlist *sgdst = rctx->sg_dst;
-+	unsigned int remainin = sg_dma_len(sgsrc);
-+	unsigned int remainout = sg_dma_len(sgdst);
-+	dma_addr_t saddr = sg_dma_address(sgsrc);
-+	dma_addr_t daddr = sg_dma_address(sgdst);
-+	dma_addr_t stateAddr;
-+	u32 srcAddr, dstAddr, len, n;
-+	bool nextin = false;
-+	bool nextout = false;
-+	int offsetout = 0;
-+	int ndesc_cdr = 0, err;
-+
-+	if (IS_ECB(rctx->flags))
-+		rctx->saState_base = 0;
-+
-+	if (split < datalen) {
-+		stateAddr = rctx->saState_base_ctr;
-+		n = split;
-+	} else {
-+		stateAddr = rctx->saState_base;
-+		n = datalen;
-+	}
-+
-+	do {
-+		if (nextin) {
-+			sgsrc = sg_next(sgsrc);
-+			remainin = sg_dma_len(sgsrc);
-+			if (remainin == 0)
-+				continue;
-+
-+			saddr = sg_dma_address(sgsrc);
-+			offsetin = 0;
-+			nextin = false;
-+		}
-+
-+		if (nextout) {
-+			sgdst = sg_next(sgdst);
-+			remainout = sg_dma_len(sgdst);
-+			if (remainout == 0)
-+				continue;
-+
-+			daddr = sg_dma_address(sgdst);
-+			offsetout = 0;
-+			nextout = false;
-+		}
-+		srcAddr = saddr + offsetin;
-+		dstAddr = daddr + offsetout;
-+
-+		if (remainin == remainout) {
-+			len = remainin;
-+			if (len > n) {
-+				len = n;
-+				remainin -= n;
-+				remainout -= n;
-+				offsetin += n;
-+				offsetout += n;
-+			} else {
-+				nextin = true;
-+				nextout = true;
-+			}
-+		} else if (remainin < remainout) {
-+			len = remainin;
-+			if (len > n) {
-+				len = n;
-+				remainin -= n;
-+				remainout -= n;
-+				offsetin += n;
-+				offsetout += n;
-+			} else {
-+				offsetout += len;
-+				remainout -= len;
-+				nextin = true;
-+			}
-+		} else {
-+			len = remainout;
-+			if (len > n) {
-+				len = n;
-+				remainin -= n;
-+				remainout -= n;
-+				offsetin += n;
-+				offsetout += n;
-+			} else {
-+				offsetin += len;
-+				remainin -= len;
-+				nextout = true;
-+			}
-+		}
-+		n -= len;
-+
-+		cdesc->srcAddr = srcAddr;
-+		cdesc->dstAddr = dstAddr;
-+		cdesc->stateAddr = stateAddr;
-+		cdesc->peLength.bits.peReady = 0;
-+		cdesc->peLength.bits.byPass = 0;
-+		cdesc->peLength.bits.length = len;
-+		cdesc->peLength.bits.hostReady = 1;
-+
-+		if (n == 0) {
-+			n = datalen - split;
-+			split = datalen;
-+			stateAddr = rctx->saState_base;
-+		}
-+
-+		if (n == 0)
-+			cdesc->userId |= MTK_DESC_LAST;
-+
-+		/* Loop - Delay - No need to rollback
-+		 * Maybe refine by slowing down at MTK_RING_BUSY
-+		 */
-+again:
-+		err = mtk_put_descriptor(mtk, cdesc);
-+		if (err) {
-+			udelay(500);
-+			goto again;
-+		}
-+		/* Writing new descriptor count starts DMA action */
-+		writel(1, mtk->base + EIP93_REG_PE_CD_COUNT);
-+
-+		ndesc_cdr++;
-+	} while (n);
-+
-+	return -EINPROGRESS;
-+}
-+
-+int mtk_send_req(struct crypto_async_request *async,
-+			const u8 *reqiv, struct mtk_cipher_reqctx *rctx)
-+{
-+	struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+	struct mtk_device *mtk = ctx->mtk;
-+	struct scatterlist *src = rctx->sg_src;
-+	struct scatterlist *dst = rctx->sg_dst;
-+	struct saState_s *saState;
-+	struct mtk_state_pool *saState_pool;
-+	struct eip93_descriptor_s cdesc;
-+	u32 flags = rctx->flags;
-+	int idx;
-+	int offsetin = 0, err = -ENOMEM;
-+	u32 datalen = rctx->assoclen + rctx->textsize;
-+	u32 split = datalen;
-+	u32 start, end, ctr, blocks;
-+	u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
-+
-+	rctx->saState_ctr = NULL;
-+	rctx->saState = NULL;
-+
-+	if (IS_ECB(flags))
-+		goto skip_iv;
-+
-+	memcpy(iv, reqiv, rctx->ivsize);
-+
-+	if (!IS_ALIGNED((u32)reqiv, rctx->ivsize) || IS_RFC3686(flags)) {
-+		rctx->flags &= ~MTK_DESC_DMA_IV;
-+		flags = rctx->flags;
-+	}
-+
-+	if (IS_DMA_IV(flags)) {
-+		rctx->saState = (void *)reqiv;
-+	} else  {
-+		idx = mtk_get_free_saState(mtk);
-+		if (idx < 0)
-+			goto send_err;
-+		saState_pool = &mtk->ring->saState_pool[idx];
-+		rctx->saState_idx = idx;
-+		rctx->saState = saState_pool->base;
-+		rctx->saState_base = saState_pool->base_dma;
-+		memcpy(rctx->saState->stateIv, iv, rctx->ivsize);
-+	}
-+
-+	saState = rctx->saState;
-+
-+	if (IS_RFC3686(flags)) {
-+		saState->stateIv[0] = ctx->saNonce;
-+		saState->stateIv[1] = iv[0];
-+		saState->stateIv[2] = iv[1];
-+		saState->stateIv[3] = cpu_to_be32(1);
-+	} else if (!IS_HMAC(flags) && IS_CTR(flags)) {
-+		/* Compute data length. */
-+		blocks = DIV_ROUND_UP(rctx->textsize, AES_BLOCK_SIZE);
-+		ctr = be32_to_cpu(iv[3]);
-+		/* Check 32bit counter overflow. */
-+		start = ctr;
-+		end = start + blocks - 1;
-+		if (end < start) {
-+			split = AES_BLOCK_SIZE * -start;
-+			/*
-+			 * Increment the counter manually to cope with
-+			 * the hardware counter overflow.
-+			 */
-+			iv[3] = 0xffffffff;
-+			crypto_inc((u8 *)iv, AES_BLOCK_SIZE);
-+			idx = mtk_get_free_saState(mtk);
-+			if (idx < 0)
-+				goto free_state;
-+			saState_pool = &mtk->ring->saState_pool[idx];
-+			rctx->saState_ctr_idx = idx;
-+			rctx->saState_ctr = saState_pool->base;
-+			rctx->saState_base_ctr = saState_pool->base_dma;
-+
-+			memcpy(rctx->saState_ctr->stateIv, reqiv, rctx->ivsize);
-+			memcpy(saState->stateIv, iv, rctx->ivsize);
-+		}
-+	}
-+
-+	if (IS_DMA_IV(flags)) {
-+		rctx->saState_base = dma_map_single(mtk->dev, (void *)reqiv,
-+						rctx->ivsize, DMA_TO_DEVICE);
-+		if (dma_mapping_error(mtk->dev, rctx->saState_base))
-+			goto free_state;
-+	}
-+skip_iv:
-+	cdesc.peCrtlStat.bits.hostReady = 1;
-+	cdesc.peCrtlStat.bits.prngMode = 0;
-+	cdesc.peCrtlStat.bits.hashFinal = 0;
-+	cdesc.peCrtlStat.bits.padCrtlStat = 0;
-+	cdesc.peCrtlStat.bits.peReady = 0;
-+	cdesc.saAddr = rctx->saRecord_base;
-+	cdesc.arc4Addr = (uint32_t)async;
-+	cdesc.userId = flags;
-+	rctx->cdesc = &cdesc;
-+
-+	/* map DMA_BIDIRECTIONAL to invalidate cache on destination
-+	 * implies __dma_cache_wback_inv
-+	 */
-+	dma_map_sg(mtk->dev, dst, rctx->dst_nents, DMA_BIDIRECTIONAL);
-+	if (src != dst)
-+		dma_map_sg(mtk->dev, src, rctx->src_nents, DMA_TO_DEVICE);
-+
-+	err = mtk_scatter_combine(mtk, rctx, datalen, split, offsetin);
-+
-+	return err;
-+
-+free_state:
-+	if (rctx->saState) {
-+		saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
-+		saState_pool->in_use = false;
-+	}
-+
-+	if (rctx->saState_ctr) {
-+		saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
-+		saState_pool->in_use = false;
-+	}
-+send_err:
-+	return err;
-+}
-+
-+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+			struct scatterlist *reqsrc, struct scatterlist *reqdst)
-+{
-+	u32 len = rctx->assoclen + rctx->textsize;
-+	u32 authsize = rctx->authsize;
-+	u32 flags = rctx->flags;
-+	u32 *otag;
-+	int i;
-+
-+	if (rctx->sg_src == rctx->sg_dst) {
-+		dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
-+							DMA_BIDIRECTIONAL);
-+		goto process_tag;
-+	}
-+
-+	dma_unmap_sg(mtk->dev, rctx->sg_src, rctx->src_nents,
-+							DMA_TO_DEVICE);
-+
-+	if (rctx->sg_src != reqsrc)
-+		mtk_free_sg_copy(len +  rctx->authsize, &rctx->sg_src);
-+
-+	dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
-+							DMA_BIDIRECTIONAL);
-+
-+	/* SHA tags need conversion from net-to-host */
-+process_tag:
-+	if (IS_DECRYPT(flags))
-+		authsize = 0;
-+
-+	if (authsize) {
-+		if (!IS_HASH_MD5(flags)) {
-+			otag = sg_virt(rctx->sg_dst) + len;
-+			for (i = 0; i < (authsize / 4); i++)
-+				otag[i] = ntohl(otag[i]);
-+		}
-+	}
-+
-+	if (rctx->sg_dst != reqdst) {
-+		sg_copy_from_buffer(reqdst, sg_nents(reqdst),
-+				sg_virt(rctx->sg_dst), len + authsize);
-+		mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_dst);
-+	}
-+}
-+
-+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+			u8 *reqiv)
-+{
-+	struct mtk_state_pool *saState_pool;
-+
-+	if (IS_DMA_IV(rctx->flags))
-+		dma_unmap_single(mtk->dev, rctx->saState_base, rctx->ivsize,
-+						DMA_TO_DEVICE);
-+
-+	if (!IS_ECB(rctx->flags))
-+		memcpy(reqiv, rctx->saState->stateIv, rctx->ivsize);
-+
-+	if ((rctx->saState) && !(IS_DMA_IV(rctx->flags))) {
-+		saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
-+		saState_pool->in_use = false;
-+	}
-+
-+	if (rctx->saState_ctr) {
-+		saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
-+		saState_pool->in_use = false;
-+	}
-+}
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+/* basically this is set hmac - key */
-+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
-+			const u8 *authkey, unsigned int authkeylen)
-+{
-+	int bs = crypto_shash_blocksize(cshash);
-+	int ds = crypto_shash_digestsize(cshash);
-+	int ss = crypto_shash_statesize(cshash);
-+	u8 *ipad, *opad;
-+	unsigned int i, err;
-+
-+	SHASH_DESC_ON_STACK(shash, cshash);
-+
-+	shash->tfm = cshash;
-+
-+	/* auth key
-+	 *
-+	 * EIP93 can only authenticate with hash of the key
-+	 * do software shash until EIP93 hash function complete.
-+	 */
-+	ipad = kcalloc(2, SHA256_BLOCK_SIZE + ss, GFP_KERNEL);
-+	if (!ipad)
-+		return -ENOMEM;
-+
-+	opad = ipad + SHA256_BLOCK_SIZE + ss;
-+
-+	if (authkeylen > bs) {
-+		err = crypto_shash_digest(shash, authkey,
-+					authkeylen, ipad);
-+		if (err)
-+			return err;
-+
-+		authkeylen = ds;
-+	} else
-+		memcpy(ipad, authkey, authkeylen);
-+
-+	memset(ipad + authkeylen, 0, bs - authkeylen);
-+	memcpy(opad, ipad, bs);
-+
-+	for (i = 0; i < bs; i++) {
-+		ipad[i] ^= HMAC_IPAD_VALUE;
-+		opad[i] ^= HMAC_OPAD_VALUE;
-+	}
-+
-+	err = crypto_shash_init(shash) ?:
-+		crypto_shash_update(shash, ipad, bs) ?:
-+		crypto_shash_export(shash, ipad) ?:
-+		crypto_shash_init(shash) ?:
-+		crypto_shash_update(shash, opad, bs) ?:
-+		crypto_shash_export(shash, opad);
-+
-+	if (err)
-+		return err;
-+
-+	/* add auth key */
-+	memcpy(&sa->saIDigest, ipad, SHA256_DIGEST_SIZE);
-+	memcpy(&sa->saODigest, opad, SHA256_DIGEST_SIZE);
-+
-+	kfree(ipad);
-+	return 0;
-+}
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-common.h
-@@ -0,0 +1,28 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#ifndef _EIP93_COMMON_H_
-+#define _EIP93_COMMON_H_
-+
-+#include "eip93-main.h"
-+
-+inline int mtk_put_descriptor(struct mtk_device *mtk,
-+					struct eip93_descriptor_s *desc);
-+
-+inline void *mtk_get_descriptor(struct mtk_device *mtk);
-+
-+inline int mtk_get_free_saState(struct mtk_device *mtk);
-+
-+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
-+				const u32 flags);
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
-+			const u8 *authkey, unsigned int authkeylen);
-+#endif
-+
-+#endif /* _EIP93_COMMON_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-des.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_DES_H_
-+#define _EIP93_DES_H_
-+
-+extern struct mtk_alg_template mtk_alg_ecb_des;
-+extern struct mtk_alg_template mtk_alg_cbc_des;
-+extern struct mtk_alg_template mtk_alg_ecb_des3_ede;
-+extern struct mtk_alg_template mtk_alg_cbc_des3_ede;
-+
-+#endif /* _EIP93_DES_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-main.c
-@@ -0,0 +1,467 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+
-+#include "eip93-main.h"
-+#include "eip93-regs.h"
-+#include "eip93-common.h"
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
-+#include "eip93-cipher.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+#include "eip93-aes.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include "eip93-des.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+#include "eip93-aead.h"
-+#endif
-+
-+static struct mtk_alg_template *mtk_algs[] = {
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+	&mtk_alg_ecb_des,
-+	&mtk_alg_cbc_des,
-+	&mtk_alg_ecb_des3_ede,
-+	&mtk_alg_cbc_des3_ede,
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+	&mtk_alg_ecb_aes,
-+	&mtk_alg_cbc_aes,
-+	&mtk_alg_ctr_aes,
-+	&mtk_alg_rfc3686_aes,
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+	&mtk_alg_authenc_hmac_md5_cbc_des,
-+	&mtk_alg_authenc_hmac_sha1_cbc_des,
-+	&mtk_alg_authenc_hmac_sha224_cbc_des,
-+	&mtk_alg_authenc_hmac_sha256_cbc_des,
-+	&mtk_alg_authenc_hmac_md5_cbc_des3_ede,
-+	&mtk_alg_authenc_hmac_sha1_cbc_des3_ede,
-+	&mtk_alg_authenc_hmac_sha224_cbc_des3_ede,
-+	&mtk_alg_authenc_hmac_sha256_cbc_des3_ede,
-+#endif
-+	&mtk_alg_authenc_hmac_md5_cbc_aes,
-+	&mtk_alg_authenc_hmac_sha1_cbc_aes,
-+	&mtk_alg_authenc_hmac_sha224_cbc_aes,
-+	&mtk_alg_authenc_hmac_sha256_cbc_aes,
-+	&mtk_alg_authenc_hmac_md5_rfc3686_aes,
-+	&mtk_alg_authenc_hmac_sha1_rfc3686_aes,
-+	&mtk_alg_authenc_hmac_sha224_rfc3686_aes,
-+	&mtk_alg_authenc_hmac_sha256_rfc3686_aes,
-+#endif
-+};
-+
-+inline void mtk_irq_disable(struct mtk_device *mtk, u32 mask)
-+{
-+	__raw_writel(mask, mtk->base + EIP93_REG_MASK_DISABLE);
-+}
-+
-+inline void mtk_irq_enable(struct mtk_device *mtk, u32 mask)
-+{
-+	__raw_writel(mask, mtk->base + EIP93_REG_MASK_ENABLE);
-+}
-+
-+inline void mtk_irq_clear(struct mtk_device *mtk, u32 mask)
-+{
-+	__raw_writel(mask, mtk->base + EIP93_REG_INT_CLR);
-+}
-+
-+static void mtk_unregister_algs(unsigned int i)
-+{
-+	unsigned int j;
-+
-+	for (j = 0; j < i; j++) {
-+		switch (mtk_algs[j]->type) {
-+		case MTK_ALG_TYPE_SKCIPHER:
-+			crypto_unregister_skcipher(&mtk_algs[j]->alg.skcipher);
-+			break;
-+		case MTK_ALG_TYPE_AEAD:
-+			crypto_unregister_aead(&mtk_algs[j]->alg.aead);
-+			break;
-+		}
-+	}
-+}
-+
-+static int mtk_register_algs(struct mtk_device *mtk)
-+{
-+	unsigned int i;
-+	int err = 0;
-+
-+	for (i = 0; i < ARRAY_SIZE(mtk_algs); i++) {
-+		mtk_algs[i]->mtk = mtk;
-+
-+		switch (mtk_algs[i]->type) {
-+		case MTK_ALG_TYPE_SKCIPHER:
-+			err = crypto_register_skcipher(&mtk_algs[i]->alg.skcipher);
-+			break;
-+		case MTK_ALG_TYPE_AEAD:
-+			err = crypto_register_aead(&mtk_algs[i]->alg.aead);
-+			break;
-+		}
-+		if (err)
-+			goto fail;
-+	}
-+
-+	return 0;
-+
-+fail:
-+	mtk_unregister_algs(i);
-+
-+	return err;
-+}
-+
-+static void mtk_handle_result_descriptor(struct mtk_device *mtk)
-+{
-+	struct crypto_async_request *async;
-+	struct eip93_descriptor_s *rdesc;
-+	bool last_entry;
-+	u32 flags;
-+	int handled, ready, err;
-+	union peCrtlStat_w done1;
-+	union peLength_w done2;
-+
-+get_more:
-+	handled = 0;
-+
-+	ready = readl(mtk->base + EIP93_REG_PE_RD_COUNT) & GENMASK(10, 0);
-+
-+	if (!ready) {
-+		mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+		mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+		return;
-+	}
-+
-+	last_entry = false;
-+
-+	while (ready) {
-+		rdesc = mtk_get_descriptor(mtk);
-+		if (IS_ERR(rdesc)) {
-+			dev_err(mtk->dev, "Ndesc: %d nreq: %d\n",
-+				handled, ready);
-+			err = -EIO;
-+			break;
-+		}
-+		/* make sure DMA is finished writing */
-+		do {
-+			done1.word = READ_ONCE(rdesc->peCrtlStat.word);
-+			done2.word = READ_ONCE(rdesc->peLength.word);
-+		} while ((!done1.bits.peReady) || (!done2.bits.peReady));
-+
-+		err = rdesc->peCrtlStat.bits.errStatus;
-+
-+		flags = rdesc->userId;
-+		async = (struct crypto_async_request *)rdesc->arc4Addr;
-+
-+		writel(1, mtk->base + EIP93_REG_PE_RD_COUNT);
-+		mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+
-+		handled++;
-+		ready--;
-+
-+		if (flags & MTK_DESC_LAST) {
-+			last_entry = true;
-+			break;
-+		}
-+	}
-+
-+	if (!last_entry)
-+		goto get_more;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
-+	if (flags & MTK_DESC_SKCIPHER)
-+		mtk_skcipher_handle_result(async, err);
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+	if (flags & MTK_DESC_AEAD)
-+		mtk_aead_handle_result(async, err);
-+#endif
-+	goto get_more;
-+}
-+
-+static void mtk_done_task(unsigned long data)
-+{
-+	struct mtk_device *mtk = (struct mtk_device *)data;
-+
-+	mtk_handle_result_descriptor(mtk);
-+}
-+
-+static irqreturn_t mtk_irq_handler(int irq, void *dev_id)
-+{
-+	struct mtk_device *mtk = (struct mtk_device *)dev_id;
-+	u32 irq_status;
-+
-+	irq_status = readl(mtk->base + EIP93_REG_INT_MASK_STAT);
-+
-+	if (irq_status & EIP93_INT_PE_RDRTHRESH_REQ) {
-+		mtk_irq_disable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+		tasklet_schedule(&mtk->ring->done_task);
-+		return IRQ_HANDLED;
-+	}
-+
-+	mtk_irq_clear(mtk, irq_status);
-+	if (irq_status)
-+		mtk_irq_disable(mtk, irq_status);
-+
-+	return IRQ_NONE;
-+}
-+
-+static void mtk_initialize(struct mtk_device *mtk)
-+{
-+	union peConfig_w peConfig;
-+	union peEndianCfg_w peEndianCfg;
-+	union peIntCfg_w peIntCfg;
-+	union peClockCfg_w peClockCfg;
-+	union peBufThresh_w peBufThresh;
-+	union peRingThresh_w peRingThresh;
-+
-+	/* Reset Engine and setup Mode */
-+	peConfig.word = 0;
-+	peConfig.bits.resetPE = 1;
-+	peConfig.bits.resetRing = 1;
-+	peConfig.bits.peMode = 3;
-+	peConfig.bits.enCDRupdate = 1;
-+
-+	writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
-+
-+	udelay(10);
-+
-+	peConfig.bits.resetPE = 0;
-+	peConfig.bits.resetRing = 0;
-+
-+	writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
-+
-+	/* Initialize the BYTE_ORDER_CFG register */
-+	peEndianCfg.word = 0;
-+	writel(peEndianCfg.word, mtk->base + EIP93_REG_PE_ENDIAN_CONFIG);
-+
-+	/* Initialize the INT_CFG register */
-+	peIntCfg.word = 0;
-+	writel(peIntCfg.word, mtk->base + EIP93_REG_INT_CFG);
-+
-+	/* Config Clocks */
-+	peClockCfg.word = 0;
-+	peClockCfg.bits.enPEclk = 1;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+	peClockCfg.bits.enDESclk = 1;
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+	peClockCfg.bits.enAESclk = 1;
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+	peClockCfg.bits.enHASHclk = 1;
-+#endif
-+	writel(peClockCfg.word, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
-+
-+	/* Config DMA thresholds */
-+	peBufThresh.word = 0;
-+	peBufThresh.bits.inputBuffer  = 128;
-+	peBufThresh.bits.outputBuffer = 128;
-+
-+	writel(peBufThresh.word, mtk->base + EIP93_REG_PE_BUF_THRESH);
-+
-+	/* Clear/ack all interrupts before disable all */
-+	mtk_irq_clear(mtk, 0xFFFFFFFF);
-+	mtk_irq_disable(mtk, 0xFFFFFFFF);
-+
-+	/* Config Ring Threshold */
-+	peRingThresh.word = 0;
-+	peRingThresh.bits.CDRThresh = MTK_RING_SIZE - MTK_RING_BUSY;
-+	peRingThresh.bits.RDRThresh = 0;
-+	peRingThresh.bits.RDTimeout = 5;
-+	peRingThresh.bits.enTimeout = 1;
-+
-+	writel(peRingThresh.word, mtk->base + EIP93_REG_PE_RING_THRESH);
-+}
-+
-+static void mtk_desc_free(struct mtk_device *mtk)
-+{
-+	writel(0, mtk->base + EIP93_REG_PE_RING_CONFIG);
-+	writel(0, mtk->base + EIP93_REG_PE_CDR_BASE);
-+	writel(0, mtk->base + EIP93_REG_PE_RDR_BASE);
-+}
-+
-+static int mtk_set_ring(struct mtk_device *mtk, struct mtk_desc_ring *ring,
-+			int Offset)
-+{
-+	ring->offset = Offset;
-+	ring->base = dmam_alloc_coherent(mtk->dev, Offset * MTK_RING_SIZE,
-+					&ring->base_dma, GFP_KERNEL);
-+	if (!ring->base)
-+		return -ENOMEM;
-+
-+	ring->write = ring->base;
-+	ring->base_end = ring->base + Offset * (MTK_RING_SIZE - 1);
-+	ring->read  = ring->base;
-+
-+	return 0;
-+}
-+
-+static int mtk_desc_init(struct mtk_device *mtk)
-+{
-+	struct mtk_state_pool *saState_pool;
-+	struct mtk_desc_ring *cdr = &mtk->ring->cdr;
-+	struct mtk_desc_ring *rdr = &mtk->ring->rdr;
-+	union peRingCfg_w peRingCfg;
-+	int RingOffset, err, i;
-+
-+	RingOffset = sizeof(struct eip93_descriptor_s);
-+
-+	err = mtk_set_ring(mtk, cdr, RingOffset);
-+	if (err)
-+		return err;
-+
-+	err = mtk_set_ring(mtk, rdr, RingOffset);
-+	if (err)
-+		return err;
-+
-+	writel((u32)cdr->base_dma, mtk->base + EIP93_REG_PE_CDR_BASE);
-+	writel((u32)rdr->base_dma, mtk->base + EIP93_REG_PE_RDR_BASE);
-+
-+	peRingCfg.word = 0;
-+	peRingCfg.bits.ringSize = MTK_RING_SIZE - 1;
-+	peRingCfg.bits.ringOffset =  RingOffset / 4;
-+
-+	writel(peRingCfg.word, mtk->base + EIP93_REG_PE_RING_CONFIG);
-+
-+	atomic_set(&mtk->ring->free, MTK_RING_SIZE - 1);
-+	/* Create State record DMA pool */
-+	RingOffset = sizeof(struct saState_s);
-+	mtk->ring->saState = dmam_alloc_coherent(mtk->dev,
-+					RingOffset * MTK_RING_SIZE,
-+					&mtk->ring->saState_dma, GFP_KERNEL);
-+	if (!mtk->ring->saState)
-+		return -ENOMEM;
-+
-+	mtk->ring->saState_pool = devm_kcalloc(mtk->dev, 1,
-+				sizeof(struct mtk_state_pool) * MTK_RING_SIZE,
-+				GFP_KERNEL);
-+
-+	for (i = 0; i < MTK_RING_SIZE; i++) {
-+		saState_pool = &mtk->ring->saState_pool[i];
-+		saState_pool->base = mtk->ring->saState + (i * RingOffset);
-+		saState_pool->base_dma = mtk->ring->saState_dma + (i * RingOffset);
-+		saState_pool->in_use = false;
-+	}
-+
-+	return 0;
-+}
-+
-+static void mtk_cleanup(struct mtk_device *mtk)
-+{
-+	tasklet_kill(&mtk->ring->done_task);
-+
-+	/* Clear/ack all interrupts before disable all */
-+	mtk_irq_clear(mtk, 0xFFFFFFFF);
-+	mtk_irq_disable(mtk, 0xFFFFFFFF);
-+
-+	writel(0, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
-+
-+	mtk_desc_free(mtk);
-+}
-+
-+static int mtk_crypto_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct mtk_device *mtk;
-+	struct resource *res;
-+	int err;
-+
-+	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
-+	if (!mtk)
-+		return -ENOMEM;
-+
-+	mtk->dev = dev;
-+	platform_set_drvdata(pdev, mtk);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	mtk->base = devm_ioremap_resource(&pdev->dev, res);
-+
-+	if (IS_ERR(mtk->base))
-+		return PTR_ERR(mtk->base);
-+
-+	mtk->irq = platform_get_irq(pdev, 0);
-+
-+	if (mtk->irq < 0)
-+		return mtk->irq;
-+
-+	err = devm_request_threaded_irq(mtk->dev, mtk->irq, mtk_irq_handler,
-+					NULL, IRQF_ONESHOT,
-+					dev_name(mtk->dev), mtk);
-+
-+	mtk->ring = devm_kcalloc(mtk->dev, 1, sizeof(*mtk->ring), GFP_KERNEL);
-+
-+	if (!mtk->ring)
-+		return -ENOMEM;
-+
-+	err = mtk_desc_init(mtk);
-+	if (err)
-+		return err;
-+
-+	tasklet_init(&mtk->ring->done_task, mtk_done_task, (unsigned long)mtk);
-+
-+	spin_lock_init(&mtk->ring->read_lock);
-+	spin_lock_init(&mtk->ring->write_lock);
-+
-+	mtk_initialize(mtk);
-+
-+	/* Init. finished, enable RDR interupt */
-+	mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+
-+	err = mtk_register_algs(mtk);
-+	if (err) {
-+		mtk_cleanup(mtk);
-+		return err;
-+	}
-+
-+	dev_info(mtk->dev, "EIP93 Crypto Engine Initialized.");
-+
-+	return 0;
-+}
-+
-+static int mtk_crypto_remove(struct platform_device *pdev)
-+{
-+	struct mtk_device *mtk = platform_get_drvdata(pdev);
-+
-+	mtk_unregister_algs(ARRAY_SIZE(mtk_algs));
-+	mtk_cleanup(mtk);
-+	dev_info(mtk->dev, "EIP93 removed.\n");
-+
-+	return 0;
-+}
-+
-+#if defined(CONFIG_OF)
-+static const struct of_device_id mtk_crypto_of_match[] = {
-+	{ .compatible = "mediatek,mtk-eip93", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, mtk_crypto_of_match);
-+#endif
-+
-+static struct platform_driver mtk_crypto_driver = {
-+	.probe = mtk_crypto_probe,
-+	.remove = mtk_crypto_remove,
-+	.driver = {
-+		.name = "mtk-eip93",
-+		.of_match_table = of_match_ptr(mtk_crypto_of_match),
-+	},
-+};
-+module_platform_driver(mtk_crypto_driver);
-+
-+MODULE_AUTHOR("Richard van Schagen <vschagen@cs.com>");
-+MODULE_ALIAS("platform:" KBUILD_MODNAME);
-+MODULE_DESCRIPTION("Mediatek EIP-93 crypto engine driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-main.h
-@@ -0,0 +1,146 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_MAIN_H_
-+#define _EIP93_MAIN_H_
-+
-+#include <crypto/internal/aead.h>
-+#include <crypto/internal/hash.h>
-+#include <crypto/internal/rng.h>
-+#include <crypto/internal/skcipher.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+
-+#define MTK_RING_SIZE			512
-+#define MTK_RING_BUSY			32
-+#define MTK_CRA_PRIORITY		1500
-+
-+/* cipher algorithms */
-+#define MTK_ALG_DES			BIT(0)
-+#define MTK_ALG_3DES			BIT(1)
-+#define MTK_ALG_AES			BIT(2)
-+#define MTK_ALG_MASK			GENMASK(2, 0)
-+/* hash and hmac algorithms */
-+#define MTK_HASH_MD5			BIT(3)
-+#define MTK_HASH_SHA1			BIT(4)
-+#define MTK_HASH_SHA224			BIT(5)
-+#define MTK_HASH_SHA256			BIT(6)
-+#define MTK_HASH_HMAC			BIT(7)
-+#define MTK_HASH_MASK			GENMASK(6, 3)
-+/* cipher modes */
-+#define MTK_MODE_CBC			BIT(8)
-+#define MTK_MODE_ECB			BIT(9)
-+#define MTK_MODE_CTR			BIT(10)
-+#define MTK_MODE_RFC3686		BIT(11)
-+#define MTK_MODE_MASK			GENMASK(10, 8)
-+
-+/* cipher encryption/decryption operations */
-+#define MTK_ENCRYPT			BIT(12)
-+#define MTK_DECRYPT			BIT(13)
-+
-+#define MTK_BUSY			BIT(14)
-+
-+/* descriptor flags */
-+#define MTK_DESC_ASYNC			BIT(31)
-+#define MTK_DESC_SKCIPHER		BIT(30)
-+#define MTK_DESC_AEAD			BIT(29)
-+#define MTK_DESC_AHASH			BIT(28)
-+#define MTK_DESC_PRNG			BIT(27)
-+#define MTK_DESC_FAKE_HMAC		BIT(26)
-+#define MTK_DESC_LAST			BIT(25)
-+#define MTK_DESC_FINISH			BIT(24)
-+#define MTK_DESC_IPSEC			BIT(23)
-+#define MTK_DESC_DMA_IV			BIT(22)
-+
-+#define IS_DES(flags)			(flags & MTK_ALG_DES)
-+#define IS_3DES(flags)			(flags & MTK_ALG_3DES)
-+#define IS_AES(flags)			(flags & MTK_ALG_AES)
-+
-+#define IS_HASH_MD5(flags)		(flags & MTK_HASH_MD5)
-+#define IS_HASH_SHA1(flags)		(flags & MTK_HASH_SHA1)
-+#define IS_HASH_SHA224(flags)		(flags & MTK_HASH_SHA224)
-+#define IS_HASH_SHA256(flags)		(flags & MTK_HASH_SHA256)
-+#define IS_HMAC(flags)			(flags & MTK_HASH_HMAC)
-+
-+#define IS_CBC(mode)			(mode & MTK_MODE_CBC)
-+#define IS_ECB(mode)			(mode & MTK_MODE_ECB)
-+#define IS_CTR(mode)			(mode & MTK_MODE_CTR)
-+#define IS_RFC3686(mode)		(mode & MTK_MODE_RFC3686)
-+
-+#define IS_BUSY(flags)			(flags & MTK_BUSY)
-+#define IS_DMA_IV(flags)		(flags & MTK_DESC_DMA_IV)
-+
-+#define IS_ENCRYPT(dir)			(dir & MTK_ENCRYPT)
-+#define IS_DECRYPT(dir)			(dir & MTK_DECRYPT)
-+
-+#define IS_CIPHER(flags)		(flags & (MTK_ALG_DES || \
-+						MTK_ALG_3DES ||  \
-+						MTK_ALG_AES))
-+
-+#define IS_HASH(flags)			(flags & (MTK_HASH_MD5 ||  \
-+						MTK_HASH_SHA1 ||   \
-+						MTK_HASH_SHA224 || \
-+						MTK_HASH_SHA256))
-+
-+/**
-+ * struct mtk_device - crypto engine device structure
-+ */
-+struct mtk_device {
-+	void __iomem		*base;
-+	struct device		*dev;
-+	struct clk		*clk;
-+	int			irq;
-+	struct mtk_ring		*ring;
-+	struct mtk_state_pool	*saState_pool;
-+};
-+
-+struct mtk_desc_ring {
-+	void			*base;
-+	void			*base_end;
-+	dma_addr_t		base_dma;
-+	/* write and read pointers */
-+	void			*read;
-+	void			*write;
-+	/* descriptor element offset */
-+	u32			offset;
-+};
-+
-+struct mtk_state_pool {
-+	void			*base;
-+	dma_addr_t		base_dma;
-+	bool			in_use;
-+};
-+
-+struct mtk_ring {
-+	struct tasklet_struct		done_task;
-+	/* command/result rings */
-+	struct mtk_desc_ring		cdr;
-+	struct mtk_desc_ring		rdr;
-+	spinlock_t			write_lock;
-+	spinlock_t			read_lock;
-+	atomic_t			free;
-+	/* saState */
-+	struct mtk_state_pool		*saState_pool;
-+	void				*saState;
-+	dma_addr_t			saState_dma;
-+};
-+
-+enum mtk_alg_type {
-+	MTK_ALG_TYPE_AEAD,
-+	MTK_ALG_TYPE_SKCIPHER,
-+};
-+
-+struct mtk_alg_template {
-+	struct mtk_device	*mtk;
-+	enum mtk_alg_type	type;
-+	u32			flags;
-+	union {
-+		struct aead_alg		aead;
-+		struct skcipher_alg	skcipher;
-+	} alg;
-+};
-+
-+#endif /* _EIP93_MAIN_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-regs.h
-@@ -0,0 +1,382 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef REG_EIP93_H
-+#define REG_EIP93_H
-+
-+#define EIP93_REG_WIDTH			4
-+/*-----------------------------------------------------------------------------
-+ * Register Map
-+ */
-+#define DESP_BASE			0x0000000
-+#define EIP93_REG_PE_CTRL_STAT		((DESP_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_SOURCE_ADDR	((DESP_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_DEST_ADDR		((DESP_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_SA_ADDR		((DESP_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_ADDR		((DESP_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_USER_ID		((DESP_BASE)+(0x06 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_LENGTH		((DESP_BASE)+(0x07 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE RING configuration registers
-+#define PE_RNG_BASE			0x0000080
-+
-+#define EIP93_REG_PE_CDR_BASE		((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RDR_BASE		((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_CONFIG	((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_THRESH	((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_CD_COUNT		((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RD_COUNT		((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_RW_PNTR	((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE  configuration registers
-+#define PE_CFG_BASE			0x0000100
-+#define EIP93_REG_PE_CONFIG		((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_STATUS		((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_BUF_THRESH		((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_INBUF_COUNT	((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_OUTBUF_COUNT	((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_BUF_RW_PNTR	((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE endian config
-+#define EN_CFG_BASE			0x00001CC
-+#define EIP93_REG_PE_ENDIAN_CONFIG	((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+
-+//EIP93 CLOCK control registers
-+#define CLOCK_BASE			0x01E8
-+#define EIP93_REG_PE_CLOCK_CTRL		((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH))
-+
-+//EIP93 Device Option and Revision Register
-+#define REV_BASE			0x01F4
-+#define EIP93_REG_PE_OPTION_1		((REV_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_OPTION_0		((REV_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_REVISION		((REV_BASE)+(0x02 * EIP93_REG_WIDTH))
-+
-+//EIP93 Interrupt Control Register
-+#define INT_BASE			0x0200
-+#define EIP93_REG_INT_UNMASK_STAT	((INT_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_MASK_STAT		((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_CLR		((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_MASK		((INT_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_CFG		((INT_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_MASK_ENABLE		((INT_BASE)+(0X04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_MASK_DISABLE		((INT_BASE)+(0X05 * EIP93_REG_WIDTH))
-+
-+//EIP93 SA Record register
-+#define SA_BASE				0x0400
-+#define EIP93_REG_SA_CMD_0		((SA_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_SA_CMD_1		((SA_BASE)+(0x01 * EIP93_REG_WIDTH))
-+
-+//#define EIP93_REG_SA_READY		((SA_BASE)+(31 * EIP93_REG_WIDTH))
-+
-+//State save register
-+#define STATE_BASE			0x0500
-+#define EIP93_REG_STATE_IV_0		((STATE_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_STATE_IV_1		((STATE_BASE)+(0x01 * EIP93_REG_WIDTH))
-+
-+#define EIP93_PE_ARC4STATE_BASEADDR_REG	0x0700
-+
-+//RAM buffer start address
-+#define EIP93_INPUT_BUFFER		0x0800
-+#define EIP93_OUTPUT_BUFFER		0x0800
-+
-+//EIP93 PRNG Configuration Register
-+#define PRNG_BASE			0x0300
-+#define EIP93_REG_PRNG_STAT		((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_CTRL		((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_0		((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_1		((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_2		((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_3		((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_0		((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_1		((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_2		((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_3		((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_0		((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_1		((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_2		((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_3		((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_LFSR_0		((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_LFSR_1		((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH))
-+
-+/*-----------------------------------------------------------------------------
-+ * Constants & masks
-+ */
-+
-+#define EIP93_SUPPORTED_INTERRUPTS_MASK	0xffff7f00
-+#define EIP93_PRNG_DT_TEXT_LOWERHALF	0xDEAD
-+#define EIP93_PRNG_DT_TEXT_UPPERHALF	0xC0DE
-+#define EIP93_10BITS_MASK		0X3FF
-+#define EIP93_12BITS_MASK		0XFFF
-+#define EIP93_4BITS_MASK		0X04
-+#define EIP93_20BITS_MASK		0xFFFFF
-+
-+#define EIP93_MIN_DESC_DONE_COUNT	0
-+#define EIP93_MAX_DESC_DONE_COUNT	15
-+
-+#define EIP93_MIN_DESC_PENDING_COUNT	0
-+#define EIP93_MAX_DESC_PENDING_COUNT	1023
-+
-+#define EIP93_MIN_TIMEOUT_COUNT		0
-+#define EIP93_MAX_TIMEOUT_COUNT		15
-+
-+#define EIP93_MIN_PE_INPUT_THRESHOLD	1
-+#define EIP93_MAX_PE_INPUT_THRESHOLD	511
-+
-+#define EIP93_MIN_PE_OUTPUT_THRESHOLD	1
-+#define EIP93_MAX_PE_OUTPUT_THRESHOLD	432
-+
-+#define EIP93_MIN_PE_RING_SIZE		1
-+#define EIP93_MAX_PE_RING_SIZE		1023
-+
-+#define EIP93_MIN_PE_DESCRIPTOR_SIZE	7
-+#define EIP93_MAX_PE_DESCRIPTOR_SIZE	15
-+
-+//3DES keys,seed,known data and its result
-+#define EIP93_KEY_0			0x133b3454
-+#define EIP93_KEY_1			0x5e5b890b
-+#define EIP93_KEY_2			0x5eb30757
-+#define EIP93_KEY_3			0x93ab15f7
-+#define EIP93_SEED_0			0x62c4bf5e
-+#define EIP93_SEED_1			0x972667c8
-+#define EIP93_SEED_2			0x6345bf67
-+#define EIP93_SEED_3			0xcb3482bf
-+#define EIP93_LFSR_0			0xDEADC0DE
-+#define EIP93_LFSR_1			0xBEEFF00D
-+
-+/*-----------------------------------------------------------------------------
-+ * EIP93 device initialization specifics
-+ */
-+
-+/*----------------------------------------------------------------------------
-+ * Byte Order Reversal Mechanisms Supported in EIP93
-+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
-+ * EIP93_BO_REVERSE_WORD :  reverse the byte order within a word
-+ * EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word
-+ * EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word
-+ */
-+enum EIP93_Byte_Order_Value_t {
-+	EIP93_BO_REVERSE_HALF_WORD = 1,
-+	EIP93_BO_REVERSE_WORD = 2,
-+	EIP93_BO_REVERSE_DUAL_WORD = 4,
-+	EIP93_BO_REVERSE_QUAD_WORD = 8,
-+};
-+
-+/*----------------------------------------------------------------------------
-+ * Byte Order Reversal Mechanisms Supported in EIP93 for Target Data
-+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
-+ * EIP93_BO_REVERSE_WORD :  reverse the byte order within a word
-+ */
-+enum EIP93_Byte_Order_Value_TD_t {
-+	EIP93_BO_REVERSE_HALF_WORD_TD = 1,
-+	EIP93_BO_REVERSE_WORD_TD = 2,
-+};
-+
-+// BYTE_ORDER_CFG register values
-+#define EIP93_BYTE_ORDER_PD		EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_SA		EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_DATA		EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_TD		EIP93_BO_REVERSE_WORD_TD
-+
-+// INT_CFG register values
-+#define EIP93_INT_HOST_OUTPUT_TYPE	0
-+#define EIP93_INT_PULSE_CLEAR		0
-+
-+/*
-+ * Interrupts of EIP93
-+ */
-+
-+enum EIP93_InterruptSource_t {
-+	EIP93_INT_PE_CDRTHRESH_REQ =	BIT(0),
-+	EIP93_INT_PE_RDRTHRESH_REQ =	BIT(1),
-+	EIP93_INT_PE_OPERATION_DONE =	BIT(9),
-+	EIP93_INT_PE_INBUFTHRESH_REQ =	BIT(10),
-+	EIP93_INT_PE_OUTBURTHRSH_REQ =	BIT(11),
-+	EIP93_INT_PE_PRNG_IRQ =		BIT(12),
-+	EIP93_INT_PE_ERR_REG =		BIT(13),
-+	EIP93_INT_PE_RD_DONE_IRQ =	BIT(16),
-+};
-+
-+union peConfig_w {
-+	u32 word;
-+	struct {
-+		u32 resetPE		:1;
-+		u32 resetRing		:1;
-+		u32 reserved		:6;
-+		u32 peMode		:2;
-+		u32 enCDRupdate		:1;
-+		u32 reserved2		:5;
-+		u32 swapCDRD		:1;
-+		u32 swapSA		:1;
-+		u32 swapData		:1;
-+		u32 reserved3		:13;
-+	} bits;
-+} __packed;
-+
-+union peEndianCfg_w {
-+	u32 word;
-+	struct {
-+		u32 masterByteSwap	:8;
-+		u32 reserved		:8;
-+		u32 targetByteSwap	:8;
-+		u32 reserved2		:8;
-+	} bits;
-+} __packed;
-+
-+union peIntCfg_w {
-+	u32 word;
-+	struct {
-+		u32 PulseClear		:1;
-+		u32 IntType		:1;
-+		u32 reserved		:30;
-+	} bits;
-+} __packed;
-+
-+union peClockCfg_w {
-+	u32 word;
-+	struct {
-+		u32 enPEclk		:1;
-+		u32 enDESclk		:1;
-+		u32 enAESclk		:1;
-+		u32 reserved		:1;
-+		u32 enHASHclk		:1;
-+		u32 reserved2		:27;
-+	} bits;
-+} __packed;
-+
-+union peBufThresh_w {
-+	u32 word;
-+	struct {
-+		u32 inputBuffer		:8;
-+		u32 reserved		:8;
-+		u32 outputBuffer	:8;
-+		u32 reserved2		:8;
-+	} bits;
-+} __packed;
-+
-+union peRingThresh_w {
-+	u32 word;
-+	struct {
-+		u32 CDRThresh		:10;
-+		u32 reserved		:6;
-+		u32 RDRThresh		:10;
-+		u32 RDTimeout		:4;
-+		u32 reserved2		:1;
-+		u32 enTimeout		:1;
-+	} bits;
-+} __packed;
-+
-+union peRingCfg_w {
-+	u32 word;
-+	struct {
-+		u32 ringSize		:10;
-+		u32 reserved		:6;
-+		u32 ringOffset		:8;
-+		u32 reserved2		:8;
-+	} bits;
-+} __packed;
-+
-+union saCmd0 {
-+	u32	word;
-+	struct {
-+		u32 opCode		:3;
-+		u32 direction		:1;
-+		u32 opGroup		:2;
-+		u32 padType		:2;
-+		u32 cipher		:4;
-+		u32 hash		:4;
-+		u32 reserved2		:1;
-+		u32 scPad		:1;
-+		u32 extPad		:1;
-+		u32 hdrProc		:1;
-+		u32 digestLength	:4;
-+		u32 ivSource		:2;
-+		u32 hashSource		:2;
-+		u32 saveIv		:1;
-+		u32 saveHash		:1;
-+		u32 reserved1		:2;
-+	} bits;
-+} __packed;
-+
-+union saCmd1 {
-+	u32	word;
-+	struct {
-+		u32 copyDigest		:1;
-+		u32 copyHeader		:1;
-+		u32 copyPayload		:1;
-+		u32 copyPad		:1;
-+		u32 reserved4		:4;
-+		u32 cipherMode		:2;
-+		u32 reserved3		:1;
-+		u32 sslMac		:1;
-+		u32 hmac		:1;
-+		u32 byteOffset		:1;
-+		u32 reserved2		:2;
-+		u32 hashCryptOffset	:8;
-+		u32 aesKeyLen		:3;
-+		u32 reserved1		:1;
-+		u32 aesDecKey		:1;
-+		u32 seqNumCheck		:1;
-+		u32 reserved0		:2;
-+	} bits;
-+} __packed;
-+
-+struct saRecord_s {
-+	union saCmd0	saCmd0;
-+	union saCmd1	saCmd1;
-+	u32		saKey[8];
-+	u32		saIDigest[8];
-+	u32		saODigest[8];
-+	u32		saSpi;
-+	u32		saSeqNum[2];
-+	u32		saSeqNumMask[2];
-+	u32		saNonce;
-+} __packed;
-+
-+struct saState_s {
-+	u32	stateIv[4];
-+	u32	stateByteCnt[2];
-+	u32	stateIDigest[8];
-+} __packed;
-+
-+union peCrtlStat_w {
-+	u32 word;
-+	struct {
-+		u32 hostReady		:1;
-+		u32 peReady		:1;
-+		u32 reserved		:1;
-+		u32 initArc4		:1;
-+		u32 hashFinal		:1;
-+		u32 haltMode		:1;
-+		u32 prngMode		:2;
-+		u32 padValue		:8;
-+		u32 errStatus		:8;
-+		u32 padCrtlStat		:8;
-+	} bits;
-+} __packed;
-+
-+union  peLength_w {
-+	u32 word;
-+	struct {
-+		u32 length		:20;
-+		u32 reserved		:2;
-+		u32 hostReady		:1;
-+		u32 peReady		:1;
-+		u32 byPass		:8;
-+	} bits;
-+} __packed;
-+
-+struct eip93_descriptor_s {
-+	union peCrtlStat_w	peCrtlStat;
-+	u32			srcAddr;
-+	u32			dstAddr;
-+	u32			saAddr;
-+	u32			stateAddr;
-+	u32			arc4Addr;
-+	u32			userId;
-+	union peLength_w	peLength;
-+} __packed;
-+
-+#endif
---- a/drivers/crypto/Kconfig
-+++ b/drivers/crypto/Kconfig
-@@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL
- source "drivers/crypto/keembay/Kconfig"
- source "drivers/crypto/aspeed/Kconfig"
- 
-+source "drivers/crypto/mtk-eip93/Kconfig"
-+
- endif # CRYPTO_HW
---- a/drivers/crypto/Makefile
-+++ b/drivers/crypto/Makefile
-@@ -53,3 +53,4 @@ obj-y += xilinx/
- obj-y += hisilicon/
- obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
- obj-y += keembay/
-+obj-$(CONFIG_CRYPTO_DEV_EIP93) += mtk-eip93/
diff --git a/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch
index f9975986fe..ac3f3b7aba 100644
--- a/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch
+++ b/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch
@@ -17,7 +17,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 
 --- a/arch/mips/kernel/setup.c
 +++ b/arch/mips/kernel/setup.c
-@@ -563,8 +563,28 @@ static int __init bootcmdline_scan_chose
+@@ -564,8 +564,28 @@ static int __init bootcmdline_scan_chose
  
  #endif /* CONFIG_OF_EARLY_FLATTREE */
  
@@ -46,7 +46,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  	bool dt_bootargs = false;
  
  	/*
-@@ -578,6 +598,14 @@ static void __init bootcmdline_init(void
+@@ -579,6 +599,14 @@ static void __init bootcmdline_init(void
  	}
  
  	/*
diff --git a/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch
index 04f0a67325..2bb3d55d70 100644
--- a/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch
+++ b/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch
@@ -10,7 +10,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/arch/mips/kernel/setup.c
 +++ b/arch/mips/kernel/setup.c
-@@ -705,7 +705,6 @@ static void __init arch_mem_init(char **
+@@ -706,7 +706,6 @@ static void __init arch_mem_init(char **
  	mips_reserve_vmcore();
  
  	mips_parse_crashkernel();
@@ -18,7 +18,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	/*
  	 * In order to reduce the possibility of kernel panic when failed to
-@@ -841,6 +840,7 @@ void __init setup_arch(char **cmdline_p)
+@@ -842,6 +841,7 @@ void __init setup_arch(char **cmdline_p)
  
  	cpu_cache_init();
  	paging_init();
diff --git a/target/linux/ramips/patches-6.6/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-6.6/700-net-ethernet-mediatek-support-net-labels.patch
deleted file mode 100644
index 0a7f7785db..0000000000
--- a/target/linux/ramips/patches-6.6/700-net-ethernet-mediatek-support-net-labels.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
-Date: Fri, 21 Jun 2019 10:04:05 +0200
-Subject: [PATCH] net: ethernet: mediatek: support net-labels
-
-With this patch, device name can be set within dts file in the same way as dsa
-port can.
-Add: label = "wan"; to GMAC node.
-
-Signed-off-by: René van Dorst <opensource@vdorst.com>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4662,6 +4662,7 @@ static const struct net_device_ops mtk_n
- 
- static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
- {
-+	const char *name = of_get_property(np, "label", NULL);
- 	const __be32 *_id = of_get_property(np, "reg", NULL);
- 	struct device_node *pcs_np;
- 	phy_interface_t phy_mode;
-@@ -4875,6 +4876,9 @@ static int mtk_add_mac(struct mtk_eth *e
- 						NETDEV_XDP_ACT_NDO_XMIT |
- 						NETDEV_XDP_ACT_NDO_XMIT_SG;
- 
-+	if (name)
-+		strlcpy(eth->netdev[id]->name, name, IFNAMSIZ);
-+
- 	return 0;
- 
- free_netdev:
diff --git a/target/linux/ramips/patches-6.6/720-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-6.6/720-NET-no-auto-carrier-off-support.patch
new file mode 100644
index 0000000000..df47096818
--- /dev/null
+++ b/target/linux/ramips/patches-6.6/720-NET-no-auto-carrier-off-support.patch
@@ -0,0 +1,31 @@
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:38:50 +0100
+Subject: [PATCH] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h          | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1075,7 +1075,7 @@ static void phy_link_change(struct phy_d
+ 
+ 	if (up)
+ 		netif_carrier_on(netdev);
+-	else
++	else if (!phydev->no_auto_carrier_off)
+ 		netif_carrier_off(netdev);
+ 	phydev->adjust_link(netdev);
+ 	if (phydev->mii_ts && phydev->mii_ts->link_state)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -659,6 +659,7 @@ struct phy_device {
+ 	unsigned downshifted_rate:1;
+ 	unsigned is_on_sfp_module:1;
+ 	unsigned mac_managed_pm:1;
++	unsigned no_auto_carrier_off:1;
+ 	unsigned wol_enabled:1;
+ 
+ 	unsigned autoneg:1;
diff --git a/target/linux/ramips/patches-6.6/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-6.6/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
deleted file mode 100644
index f45544369d..0000000000
--- a/target/linux/ramips/patches-6.6/720-Revert-net-phy-simplify-phy_link_change-arguments.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Sat, 27 Feb 2021 20:20:07 -0800
-Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments"
-
-This reverts commit a307593a644443db12888f45eed0dafb5869e2cc.
-
-This brings back the do_carrier flags used by the (hacky) next patch,
-still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
----
- drivers/net/phy/phy.c        | 12 ++++++------
- drivers/net/phy/phy_device.c | 12 +++++++-----
- drivers/net/phy/phylink.c    |  3 ++-
- include/linux/phy.h          |  2 +-
- 4 files changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -72,13 +72,13 @@ static void phy_process_state_change(str
- 
- static void phy_link_up(struct phy_device *phydev)
- {
--	phydev->phy_link_change(phydev, true);
-+	phydev->phy_link_change(phydev, true, true);
- 	phy_led_trigger_change_speed(phydev);
- }
- 
--static void phy_link_down(struct phy_device *phydev)
-+static void phy_link_down(struct phy_device *phydev, bool do_carrier)
- {
--	phydev->phy_link_change(phydev, false);
-+	phydev->phy_link_change(phydev, false, do_carrier);
- 	phy_led_trigger_change_speed(phydev);
- 	WRITE_ONCE(phydev->link_down_events, phydev->link_down_events + 1);
- }
-@@ -823,7 +823,7 @@ int phy_start_cable_test(struct phy_devi
- 		goto out;
- 
- 	/* Mark the carrier down until the test is complete */
--	phy_link_down(phydev);
-+	phy_link_down(phydev, true);
- 
- 	netif_testing_on(dev);
- 	err = phydev->drv->cable_test_start(phydev);
-@@ -894,7 +894,7 @@ int phy_start_cable_test_tdr(struct phy_
- 		goto out;
- 
- 	/* Mark the carrier down until the test is complete */
--	phy_link_down(phydev);
-+	phy_link_down(phydev, true);
- 
- 	netif_testing_on(dev);
- 	err = phydev->drv->cable_test_tdr_start(phydev, config);
-@@ -966,7 +966,7 @@ static int phy_check_link_status(struct
- 		phy_link_up(phydev);
- 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
- 		phydev->state = PHY_NOLINK;
--		phy_link_down(phydev);
-+		phy_link_down(phydev, true);
- 	}
- 
- 	return 0;
-@@ -1485,7 +1485,7 @@ void phy_state_machine(struct work_struc
- 	case PHY_ERROR:
- 		if (phydev->link) {
- 			phydev->link = 0;
--			phy_link_down(phydev);
-+			phy_link_down(phydev, true);
- 		}
- 		do_suspend = true;
- 		break;
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1069,14 +1069,16 @@ struct phy_device *phy_find_first(struct
- }
- EXPORT_SYMBOL(phy_find_first);
- 
--static void phy_link_change(struct phy_device *phydev, bool up)
-+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
- {
- 	struct net_device *netdev = phydev->attached_dev;
- 
--	if (up)
--		netif_carrier_on(netdev);
--	else
--		netif_carrier_off(netdev);
-+	if (do_carrier) {
-+		if (up)
-+			netif_carrier_on(netdev);
-+		else
-+			netif_carrier_off(netdev);
-+	}
- 	phydev->adjust_link(netdev);
- 	if (phydev->mii_ts && phydev->mii_ts->link_state)
- 		phydev->mii_ts->link_state(phydev->mii_ts, phydev);
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -1724,7 +1724,8 @@ bool phylink_expects_phy(struct phylink
- }
- EXPORT_SYMBOL_GPL(phylink_expects_phy);
- 
--static void phylink_phy_change(struct phy_device *phydev, bool up)
-+static void phylink_phy_change(struct phy_device *phydev, bool up,
-+			       bool do_carrier)
- {
- 	struct phylink *pl = phydev->phylink;
- 	bool tx_pause, rx_pause;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -758,7 +758,7 @@ struct phy_device {
- 
- 	unsigned int link_down_events;
- 
--	void (*phy_link_change)(struct phy_device *phydev, bool up);
-+	void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
- 	void (*adjust_link)(struct net_device *dev);
- 
- #if IS_ENABLED(CONFIG_MACSEC)
diff --git a/target/linux/ramips/patches-6.6/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-6.6/721-NET-no-auto-carrier-off-support.patch
deleted file mode 100644
index e594ead86f..0000000000
--- a/target/linux/ramips/patches-6.6/721-NET-no-auto-carrier-off-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 34/53] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c |    9 ++++++---
- include/linux/phy.h   |    1 +
- 2 files changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -966,7 +966,10 @@ static int phy_check_link_status(struct
- 		phy_link_up(phydev);
- 	} else if (!phydev->link && phydev->state != PHY_NOLINK) {
- 		phydev->state = PHY_NOLINK;
--		phy_link_down(phydev, true);
-+		if (!phydev->no_auto_carrier_off)
-+			phy_link_down(phydev, true);
-+		else
-+			phy_link_down(phydev, false);
- 	}
- 
- 	return 0;
-@@ -1485,7 +1488,10 @@ void phy_state_machine(struct work_struc
- 	case PHY_ERROR:
- 		if (phydev->link) {
- 			phydev->link = 0;
--			phy_link_down(phydev, true);
-+			if (!phydev->no_auto_carrier_off)
-+				phy_link_down(phydev, true);
-+			else
-+				phy_link_down(phydev, false);
- 		}
- 		do_suspend = true;
- 		break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -659,6 +659,7 @@ struct phy_device {
- 	unsigned downshifted_rate:1;
- 	unsigned is_on_sfp_module:1;
- 	unsigned mac_managed_pm:1;
-+	unsigned no_auto_carrier_off:1;
- 	unsigned wol_enabled:1;
- 
- 	unsigned autoneg:1;
diff --git a/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch b/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch
new file mode 100644
index 0000000000..3d2bdbaf40
--- /dev/null
+++ b/target/linux/ramips/patches-6.6/804-dma-ralink-add-back-gdma-driver.patch
@@ -0,0 +1,39 @@
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Mon, 27 May 2024 08:25:57 +0000
+Subject: [PATCH] dma: ralink: add back gdma driver
+
+The upstream staging driver has been removed[1] since kernel v5.17.
+
+[1] 5bfc10690c6c ("staging: ralink-gdma: remove driver from tree")
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/dma/Kconfig  | 6 ++++++
+ drivers/dma/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -532,6 +532,12 @@ config PLX_DMA
+ 	  These are exposed via extra functions on the switch's
+ 	  upstream port. Each function exposes one DMA channel.
+ 
++config RALINK_GDMA
++	tristate "RALINK GDMA support"
++	depends on RALINK && !SOC_RT288X
++	select DMA_ENGINE
++	select DMA_VIRTUAL_CHANNELS
++
+ config STE_DMA40
+ 	bool "ST-Ericsson DMA40 support"
+ 	depends on ARCH_U8500
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -64,6 +64,7 @@ obj-$(CONFIG_PL330_DMA) += pl330.o
+ obj-$(CONFIG_PLX_DMA) += plx_dma.o
+ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
+ obj-$(CONFIG_PXA_DMA) += pxa_dma.o
++obj-$(CONFIG_RALINK_GDMA) += ralink-gdma.o
+ obj-$(CONFIG_RENESAS_DMA) += sh/
+ obj-$(CONFIG_SF_PDMA) += sf-pdma/
+ obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
diff --git a/target/linux/ramips/patches-6.6/840-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-6.6/840-serial-add-ugly-custom-baud-rate-hack.patch
index 3d90286470..c21c286edf 100644
--- a/target/linux/ramips/patches-6.6/840-serial-add-ugly-custom-baud-rate-hack.patch
+++ b/target/linux/ramips/patches-6.6/840-serial-add-ugly-custom-baud-rate-hack.patch
@@ -10,7 +10,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- a/drivers/tty/serial/serial_core.c
 +++ b/drivers/tty/serial/serial_core.c
-@@ -467,6 +467,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -480,6 +480,9 @@ uart_get_baud_rate(struct uart_port *por
  		break;
  	}
  
diff --git a/target/linux/ramips/rt288x/config-6.1 b/target/linux/ramips/rt288x/config-6.1
deleted file mode 100644
index d8b89934b9..0000000000
--- a/target/linux/ramips/rt288x/config-6.1
+++ /dev/null
@@ -1,201 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT2880_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP17XX_PHY=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_AUTO_PFN_OFFSET=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=4
-CONFIG_MIPS_L1_CACHE_SHIFT_4=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_LZMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RALINK_RT2880=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NLS=m
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-# CONFIG_PHY_RALINK_USB is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-CONFIG_SOC_RT288X=y
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB=m
-CONFIG_USB_COMMON=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/rt305x/config-6.1 b/target/linux/ramips/rt305x/config-6.1
deleted file mode 100644
index 8b1b17033a..0000000000
--- a/target/linux/ramips/rt305x/config-6.1
+++ /dev/null
@@ -1,196 +0,0 @@
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT305X_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_JIMAGE_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_ESW_RT3050=y
-CONFIG_NET_RALINK_RT3050=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT305X=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-CONFIG_SOC_RT305X=y
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/rt305x/config-6.6 b/target/linux/ramips/rt305x/config-6.6
index 5d2e4f3766..27bf316c68 100644
--- a/target/linux/ramips/rt305x/config-6.6
+++ b/target/linux/ramips/rt305x/config-6.6
@@ -159,6 +159,7 @@ CONFIG_PINCTRL_RT305X=y
 CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
 # CONFIG_RALINK_ILL_ACC is not set
 CONFIG_RALINK_WDT=y
 CONFIG_RANDSTRUCT_NONE=y
diff --git a/target/linux/ramips/rt3883/config-6.1 b/target/linux/ramips/rt3883/config-6.1
deleted file mode 100644
index 2aaebdc702..0000000000
--- a/target/linux/ramips/rt3883/config-6.1
+++ /dev/null
@@ -1,196 +0,0 @@
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT3883_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RALINK_RT3883=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT3883=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTL8366_SMI=y
-CONFIG_RTL8367B_PHY=y
-CONFIG_RTL8367_PHY=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-CONFIG_SOC_RT3883=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
diff --git a/target/linux/ramips/rt3883/config-6.6 b/target/linux/ramips/rt3883/config-6.6
index afb3fb6787..b272c751ed 100644
--- a/target/linux/ramips/rt3883/config-6.6
+++ b/target/linux/ramips/rt3883/config-6.6
@@ -159,6 +159,7 @@ CONFIG_PINCTRL_RT3883=y
 CONFIG_PREEMPT_NONE_BUILD=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
 CONFIG_RALINK_WDT=y
 CONFIG_RANDSTRUCT_NONE=y
 CONFIG_RATIONAL=y
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
index ff81a4c77b..9eb444515f 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/dsa.c
@@ -155,6 +155,12 @@ static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
 		priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
 }
 
+static void rtl83xx_setup_lldp_traps(struct rtl838x_switch_priv *priv)
+{
+	for (int i = 0; i < priv->cpu_port; i++)
+		priv->r->set_receive_management_action(i, LLDP, TRAP2CPU);
+}
+
 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
 				   int port, bool enable)
 {
@@ -207,6 +213,7 @@ static int rtl83xx_setup(struct dsa_switch *ds)
 	rtl83xx_vlan_setup(priv);
 
 	rtl83xx_setup_bpdu_traps(priv);
+	rtl83xx_setup_lldp_traps(priv);
 
 	ds->configure_vlan_while_not_filtering = true;
 
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c
index adff404fdd..d93087f5b1 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c
@@ -1678,9 +1678,9 @@ void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_typ
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
 			    RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
 		break;
-	case LLTP:
+	case LLDP:
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
-			    RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
+			    RTL838X_RMA_LLDP_CTRL + ((port >> 4) << 2));
 		break;
 	default:
 		break;
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h
index a642c74775..261af32bb4 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.h
@@ -425,7 +425,7 @@ typedef enum {
 	PTP,
 	PTP_UDP,
 	PTP_ETH2,
-	LLTP,
+	LLDP,
 	EAPOL,
 	GRATARP,
 } rma_ctrl_t;
@@ -449,10 +449,10 @@ typedef enum {
 #define RTL930X_RMA_PTP_CTRL			(0x9E88)
 #define RTL931X_RMA_PTP_CTRL			(0x8834)
 
-#define RTL838X_RMA_LLTP_CTRL			(0x4340)
-#define RTL839X_RMA_LLTP_CTRL			(0x124C)
-#define RTL930X_RMA_LLTP_CTRL			(0x9EFC)
-#define RTL931X_RMA_LLTP_CTRL			(0x8918)
+#define RTL838X_RMA_LLDP_CTRL			(0x4340)
+#define RTL839X_RMA_LLDP_CTRL			(0x124C)
+#define RTL930X_RMA_LLDP_CTRL			(0x9EFC)
+#define RTL931X_RMA_LLDP_CTRL			(0x8918)
 
 #define RTL930X_RMA_EAPOL_CTRL			(0x9F08)
 #define RTL931X_RMA_EAPOL_CTRL			(0x8930)
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c
index ff80a9074e..5889cea6d6 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl839x.c
@@ -1814,9 +1814,9 @@ void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_typ
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
 			    RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
 		break;
-	case LLTP:
+	case LLDP:
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
-			    RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
+			    RTL839X_RMA_LLDP_CTRL + ((port >> 4) << 2));
 		break;
 	default:
 		break;
diff --git a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c
index 07ac25c743..25ad4eaa11 100644
--- a/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c
+++ b/target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl931x.c
@@ -516,8 +516,8 @@ void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_typ
 	case PTP_ETH2:
 		sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
 	break;
-	case LLTP:
-		sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2));
+	case LLDP:
+		sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLDP_CTRL + ((port / 10) << 2));
 	break;
 	case EAPOL:
 		sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2));
diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c
index 54e592aeaa..71e7937336 100644
--- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c
@@ -1658,7 +1658,7 @@ static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in
 	int err;
 	struct rtl838x_eth_priv *priv = bus->priv;
 
-	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+	if (priv->phy_is_internal[mii_id])
 		return rtl839x_read_sds_phy(mii_id, regnum);
 
 	if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
@@ -1797,7 +1797,7 @@ static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,
 	struct rtl838x_eth_priv *priv = bus->priv;
 	int err;
 
-	if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+	if (priv->phy_is_internal[mii_id])
 		return rtl839x_write_sds_phy(mii_id, regnum, value);
 
 	if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
index 56e8a7f49d..490020989f 100644
--- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
+++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c
@@ -46,6 +46,8 @@ extern struct mutex smi_lock;
 /* external RTL821X PHY uses register 0x1e to select media page */
 #define RTL821XEXT_MEDIA_PAGE_SELECT	0x1e
 
+#define RTL821X_CHIP_ID			0x6276
+
 #define RTL821X_MEDIA_PAGE_AUTO		0
 #define RTL821X_MEDIA_PAGE_COPPER	1
 #define RTL821X_MEDIA_PAGE_FIBRE	3
@@ -834,7 +836,7 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
 	/* Read internal PHY ID */
 	phy_write_paged(phydev, 31, 27, 0x0002);
 	val = phy_read_paged(phydev, 31, 28);
-	if (val != 0x6276) {
+	if (val != RTL821X_CHIP_ID) {
 		phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
 		return -1;
 	}
@@ -1331,7 +1333,7 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
 	phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
 	phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
 	val = phy_read_paged(phydev, 0x1f, 0x1c);
-	if (val != 0x6276) {
+	if (val != RTL821X_CHIP_ID) {
 		phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
 		return -1;
 	}
diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile
index 42d75e3b4f..26af6855ac 100644
--- a/target/linux/rockchip/Makefile
+++ b/target/linux/rockchip/Makefile
@@ -7,7 +7,7 @@ BOARDNAME:=Rockchip
 FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
 SUBTARGETS:=armv8
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware image for Rockchip SoC devices.
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index d6e97b91fa..8729bd52f2 100644
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -23,6 +23,9 @@ rockchip_setup_interfaces()
 	friendlyarm,nanopi-r5s)
 		ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0'
 		;;
+	sinovoip,rk3568-bpi-r2pro)
+		ucidef_set_interfaces_lan_wan 'lan0 lan1 lan2 lan3' 'eth0'
+		;;
 	*)
 		ucidef_set_interface_lan 'eth0'
 		;;
@@ -44,7 +47,8 @@ rockchip_setup_macs()
 		;;
 	friendlyarm,nanopi-r2c-plus|\
 	friendlyarm,nanopi-r4s|\
-	friendlyarm,nanopi-r5s)
+	friendlyarm,nanopi-r5s|\
+	sinovoip,rk3568-bpi-r2pro)
 		wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
 		lan_mac=$(macaddr_add "$wan_mac" 1)
 		;;
diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
index 5753d1e856..8bbce1c328 100644
--- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
+++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
@@ -44,7 +44,8 @@ friendlyarm,nanopi-r4s-enterprise)
 	set_interface_core 20 "eth1"
 	;;
 friendlyarm,nanopi-r5c|\
-radxa,e25)
+radxa,e25|\
+sinovoip,rk3568-bpi-r2pro)
 	set_interface_core 2 "eth0"
 	set_interface_core 4 "eth1"
 	;;
diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1
deleted file mode 100644
index 1830a89c93..0000000000
--- a/target/linux/rockchip/armv8/config-6.1
+++ /dev/null
@@ -1,697 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_EPAN=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=48
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MHU=y
-CONFIG_ARM_MHU_V2=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
-CONFIG_ARM_SCMI_CPUFREQ=y
-CONFIG_ARM_SCMI_HAVE_SHMEM=y
-CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
-CONFIG_ARM_SCMI_POWER_CONTROL=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=y
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
-CONFIG_ARM_SCPI_CPUFREQ=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMMU=y
-CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CHARGER_GPIO=y
-# CONFIG_CHARGER_RK817 is not set
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_COMMON_CLK_SCMI=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC64=y
-CONFIG_CRC64_ROCKSOFT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC64_ROCKSOFT=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_POLYVAL=y
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SM3=y
-CONFIG_CRYPTO_SM3_NEON=y
-CONFIG_CRYPTO_SM4=y
-CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
-CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_GENPD=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_DWC_QOS_ETH=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DW_WATCHDOG=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EMAC_ROCKCHIP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FORTIFY_SOURCE is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_ROCKCHIP=y
-CONFIG_GPIO_SYSCON=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_RK3X=y
-CONFIG_IIO=y
-# CONFIG_IIO_SCMI is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INDIRECT_PIO=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_MATRIXKMAP=y
-CONFIG_INPUT_RK805_PWRKEY=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_DART is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEXEC_FILE=y
-CONFIG_KSM=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_KHADAS_MCU is not set
-CONFIG_MFD_RK808=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MOTORCOMM_PHY=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=256
-CONFIG_NVMEM=y
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-# CONFIG_NVMEM_ROCKCHIP_OTP is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_STUB=y
-CONFIG_PCS_XPCS=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_ROCKCHIP_DP=y
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-CONFIG_PHY_ROCKCHIP_EMMC=y
-# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RK805=y
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PL330_DMA=y
-CONFIG_PLATFORM_MHU=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_RAID_ATTRS=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ARM_SCMI=y
-CONFIG_REGULATOR_FAN53555=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_RK808=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SCMI=y
-CONFIG_RFS_ACCEL=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_ROCKCHIP_MBOX=y
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_SARADC is not set
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RK808=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_NVMEM=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SAS_LIBSAS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SENSORS_ARM_SCMI=y
-CONFIG_SENSORS_ARM_SCPI=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ROCKCHIP=y
-CONFIG_SPI_ROCKCHIP_SFC=y
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_PER_TASK=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_SWAP is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_SYSCALL=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_TRANS_TABLE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_ANX7411 is not set
-CONFIG_TYPEC_FUSB302=y
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_FSA4480 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_RT1719 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-# CONFIG_TYPEC_TCPCI is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_TYPEC_WUSB3801 is not set
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HOST=y
-CONFIG_USB_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PLATFORM=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6
new file mode 100644
index 0000000000..fb57fc6260
--- /dev/null
+++ b/target/linux/rockchip/armv8/config-6.6
@@ -0,0 +1,729 @@
+CONFIG_64BIT=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_MHU_V2=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CHARGER_GPIO=y
+# CONFIG_CHARGER_RK817 is not set
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_POLYVAL=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM3_NEON=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_SYSCON=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_IIO=y
+# CONFIG_IIO_SCMI is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+# CONFIG_MEDIATEK_GE_SOC_PHY is not set
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK8XX=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_HWMON is not set
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_XPCS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index d457058282..df0ca6ffb5 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -130,6 +130,15 @@ define Device/radxa_rock-pi-e
 endef
 TARGET_DEVICES += radxa_rock-pi-e
 
+define Device/sinovoip_bpi-r2-pro
+  DEVICE_VENDOR := Sinovoip
+  DEVICE_MODEL := Bananapi-R2 Pro
+  SOC := rk3568
+  SUPPORTED_DEVICES := sinovoip,rk3568-bpi-r2pro
+  DEVICE_PACKAGES := kmod-ata-ahci-dwc
+endef
+TARGET_DEVICES += sinovoip_bpi-r2-pro
+
 define Device/xunlong_orangepi-r1-plus
   DEVICE_VENDOR := Xunlong
   DEVICE_MODEL := Orange Pi R1 Plus
diff --git a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch b/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch
deleted file mode 100644
index 2bb542be36..0000000000
--- a/target/linux/rockchip/patches-6.1/001-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay-for.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
-From: Shawn Lin <shawn.lin@rock-chips.com>
-Date: Thu, 2 Feb 2023 08:35:16 +0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
- rockchip platform
-
-For Rockchip platform, DLL bypass bit and start bit need to be set if
-DLL is not locked. And adjust pre-change delay to 0x3 for better signal
-test result.
-
-Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
-Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -48,6 +48,7 @@
- #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL	29
- #define DWCMSHC_EMMC_DLL_START_POINT	16
- #define DWCMSHC_EMMC_DLL_INC		8
-+#define DWCMSHC_EMMC_DLL_BYPASS		BIT(24)
- #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
- #define DLL_TXCLK_TAPNUM_DEFAULT	0x10
- #define DLL_TXCLK_TAPNUM_90_DEGREES	0xA
-@@ -60,6 +61,7 @@
- #define DLL_RXCLK_NO_INVERTER		1
- #define DLL_RXCLK_INVERTER		0
- #define DLL_CMDOUT_TAPNUM_90_DEGREES	0x8
-+#define DLL_RXCLK_ORI_GATE		BIT(31)
- #define DLL_CMDOUT_TAPNUM_FROM_SW	BIT(24)
- #define DLL_CMDOUT_SRC_CLK_NEG		BIT(28)
- #define DLL_CMDOUT_EN_SRC_CLK_NEG	BIT(29)
-@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
- 	sdhci_writel(host, extra, reg);
- 
- 	if (clock <= 52000000) {
--		/* Disable DLL and reset both of sample and drive clock */
--		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
--		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
-+		/*
-+		 * Disable DLL and reset both of sample and drive clock.
-+		 * The bypass bit and start bit need to be set if DLL is not locked.
-+		 */
-+		sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
-+		sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
- 		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
- 		sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
- 		/*
-@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
- 	}
- 
- 	extra = 0x1 << 16 | /* tune clock stop en */
--		0x2 << 17 | /* pre-change delay */
-+		0x3 << 17 | /* pre-change delay */
- 		0x3 << 19;  /* post-change delay */
- 	sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
- 
diff --git a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch b/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch
deleted file mode 100644
index 9d9c1b5c1c..0000000000
--- a/target/linux/rockchip/patches-6.1/002-v6.4-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Thu, 9 Mar 2023 17:03:49 -0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
- Rockchip
-
-Currently .get_max_clock returns the current clock rate for cclk_emmc
-on rk35xx, thus max clock gets set to whatever bootloader set it to.
-
-In case of u-boot, it is intentionally reset to 50 MHz if it boots
-from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
-HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
-clears appropriate caps if host->mmc->f_max is < 52MHz
-
-cclk_emmc is not a fixed clock on rk35xx, so using
-sdhci_pltfm_clk_get_max_clock is not appropriate here.
-
-Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
- 		return pltfm_host->clock;
- }
- 
-+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
-+{
-+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+
-+	return clk_round_rate(pltfm_host->clk, ULONG_MAX);
-+}
-+
- static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
- 				     struct mmc_request *mrq)
- {
-@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
- 	.set_clock		= dwcmshc_rk3568_set_clock,
- 	.set_bus_width		= sdhci_set_bus_width,
- 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
--	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
-+	.get_max_clock		= rk35xx_get_max_clock,
- 	.reset			= rk35xx_sdhci_reset,
- 	.adma_write_desc	= dwcmshc_adma_write_desc,
- };
diff --git a/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch
deleted file mode 100644
index 049c8ad1af..0000000000
--- a/target/linux/rockchip/patches-6.1/006-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:20 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
-
-The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
-chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |  1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c.dts   | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2C";
-+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8521s>;
-+	tx_delay = <0x22>;
-+	rx_delay = <0x12>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8521s: ethernet-phy@3 {
-+			compatible = "ethernet-phy-ieee802.3-c22";
-+			reg = <3>;
-+
-+			motorcomm,clk-out-frequency-hz = <125000000>;
-+			motorcomm,keep-pll-enabled;
-+			motorcomm,auto-sleep-disabled;
-+
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch
deleted file mode 100644
index 4e48218b89..0000000000
--- a/target/linux/rockchip/patches-6.1/007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch
+++ /dev/null
@@ -1,407 +0,0 @@
-From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sat, 3 Dec 2022 15:41:49 +0800
-Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
-
-Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
-
-This device is similar to the NanoPi R2S, and has a 16MB
-SPI NOR (mx25l12805d). The reset button is changed to
-directly reset the power supply, another detail is that
-both network ports have independent MAC addresses.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../dts/rockchip/rk3328-orangepi-r1-plus.dts  | 373 ++++++++++++++++++
- 2 files changed, 374 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,373 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Based on rk3328-nanopi-r2s.dts, which is:
-+ *   Copyright (c) 2020 David Bauer <mail@david-bauer.net>
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include "rk3328.dtsi"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus";
-+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+
-+	aliases {
-+		ethernet1 = &rtl8153;
-+		mmc0 = &sdmmc;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac_clk: gmac-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+		pinctrl-names = "default";
-+
-+		led-0 {
-+			function = LED_FUNCTION_LAN;
-+			color = <LED_COLOR_ID_GREEN>;
-+			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-1 {
-+			function = LED_FUNCTION_STATUS;
-+			color = <LED_COLOR_ID_RED>;
-+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "heartbeat";
-+		};
-+
-+		led-2 {
-+			function = LED_FUNCTION_WAN;
-+			color = <LED_COLOR_ID_GREEN>;
-+			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+
-+	vcc_sd: sdmmc-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+		pinctrl-0 = <&sdmmc0m1_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vcc_sd";
-+		regulator-boot-on;
-+		vin-supply = <&vcc_io>;
-+	};
-+
-+	vcc_sys: vcc-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vdd_5v_lan: vdd-5v-lan-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-0 = <&lan_vdd_pin>;
-+		pinctrl-names = "default";
-+		regulator-name = "vdd_5v_lan";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		vin-supply = <&vcc_sys>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_arm>;
-+};
-+
-+&display_subsystem {
-+	status = "disabled";
-+};
-+
-+&gmac2io {
-+	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+	clock_in_out = "input";
-+	phy-handle = <&rtl8211e>;
-+	phy-mode = "rgmii";
-+	phy-supply = <&vcc_io>;
-+	pinctrl-0 = <&rgmiim1_pins>;
-+	pinctrl-names = "default";
-+	snps,aal;
-+	rx_delay = <0x18>;
-+	tx_delay = <0x24>;
-+	status = "okay";
-+
-+	mdio {
-+		compatible = "snps,dwmac-mdio";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		rtl8211e: ethernet-phy@1 {
-+			reg = <1>;
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	status = "okay";
-+
-+	rk805: pmic@18 {
-+		compatible = "rockchip,rk805";
-+		reg = <0x18>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		clock-output-names = "xin32k", "rk805-clkout2";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		pinctrl-0 = <&pmic_int_l>;
-+		pinctrl-names = "default";
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc_sys>;
-+		vcc2-supply = <&vcc_sys>;
-+		vcc3-supply = <&vcc_sys>;
-+		vcc4-supply = <&vcc_sys>;
-+		vcc5-supply = <&vcc_io>;
-+		vcc6-supply = <&vcc_sys>;
-+
-+		regulators {
-+			vdd_log: DCDC_REG1 {
-+				regulator-name = "vdd_log";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+
-+			vdd_arm: DCDC_REG2 {
-+				regulator-name = "vdd_arm";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1450000>;
-+				regulator-ramp-delay = <12500>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <950000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc_io: DCDC_REG4 {
-+				regulator-name = "vcc_io";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc_18: LDO_REG1 {
-+				regulator-name = "vcc_18";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc18_emmc: LDO_REG2 {
-+				regulator-name = "vcc18_emmc";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdd_10: LDO_REG3 {
-+				regulator-name = "vdd_10";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1000000>;
-+				regulator-max-microvolt = <1000000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1000000>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&io_domains {
-+	pmuio-supply = <&vcc_io>;
-+	vccio1-supply = <&vcc_io>;
-+	vccio2-supply = <&vcc18_emmc>;
-+	vccio3-supply = <&vcc_io>;
-+	vccio4-supply = <&vcc_io>;
-+	vccio5-supply = <&vcc_io>;
-+	vccio6-supply = <&vcc_io>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	gmac2io {
-+		eth_phy_reset_pin: eth-phy-reset-pin {
-+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+	};
-+
-+	leds {
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		sys_led_pin: sys-led-pin {
-+			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	lan {
-+		lan_vdd_pin: lan-vdd-pin {
-+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&pwm2 {
-+	status = "okay";
-+};
-+
-+&sdmmc {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+	pinctrl-names = "default";
-+	vmmc-supply = <&vcc_sd>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <50000000>;
-+	};
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <0>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&u2phy {
-+	status = "okay";
-+};
-+
-+&u2phy_host {
-+	status = "okay";
-+};
-+
-+&u2phy_otg {
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb20_otg {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usbdrd3 {
-+	dr_mode = "host";
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	/* Second port is for USB 3.0 */
-+	rtl8153: device@2 {
-+		compatible = "usbbda,8153";
-+		reg = <2>;
-+	};
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
diff --git a/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch
deleted file mode 100644
index 78d3d51a17..0000000000
--- a/target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:22 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
-
-The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
-the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
-identical to OrangePi R1 Plus.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |  1 +
- .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
-+ * (http://www.orangepi.org)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus LTS";
-+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8531c>;
-+	tx_delay = <0x19>;
-+	rx_delay = <0x05>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8531c: ethernet-phy@0 {
-+			compatible = "ethernet-phy-ieee802.3-c22";
-+			reg = <0>;
-+
-+			motorcomm,clk-out-frequency-hz = <125000000>;
-+			motorcomm,keep-pll-enabled;
-+			motorcomm,auto-sleep-disabled;
-+
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <15000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch b/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch
deleted file mode 100644
index 3d502a65b6..0000000000
--- a/target/linux/rockchip/patches-6.1/009-v6.4-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch
+++ /dev/null
@@ -1,754 +0,0 @@
-From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Tue, 7 Mar 2023 22:32:40 -0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
-
-FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
-
-Board Specifications
-- Rockchip RK3568
-- 2 or 4GB LPDDR4X
-- 8GB or 16GB eMMC, SD card slot
-- GbE LAN (Native)
-- 2x 2.5G LAN (PCIe)
-- M.2 Connector
-- HDMI 2.0, MIPI DSI/CSI
-- 2xUSB 3.0 Host
-- USB Type C PD, 5V/9V/12V
-- GPIO: 12-pin 0.5mm FPC connector
-
-Based on Tianling Shen's <cnsztl@gmail.com> work.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts   | 713 ++++++++++++++++++
- 2 files changed, 714 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -0,0 +1,713 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R5S";
-+	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
-+
-+	aliases {
-+		ethernet0 = &gmac0;
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	hdmi-con {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_con_in: endpoint {
-+				remote-endpoint = <&hdmi_out_con>;
-+			};
-+		};
-+	};
-+
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
-+
-+		led-lan1 {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_LAN;
-+			function-enumerator = <1>;
-+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-lan2 {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_LAN;
-+			function-enumerator = <2>;
-+			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		power_led: led-power {
-+			color = <LED_COLOR_ID_RED>;
-+			function = LED_FUNCTION_POWER;
-+			linux,default-trigger = "heartbeat";
-+			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-wan {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_WAN;
-+			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+
-+	vdd_usbc: vdd-usbc-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_usbc";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc3v3_pcie: vcc3v3-pcie-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_pcie";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		enable-active-high;
-+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+		startup-delay-us = <200000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_usb: vcc5v0-usb-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb_host_en>;
-+		regulator-name = "vcc5v0_usb_host";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+		regulator-name = "vcc5v0_usb_otg";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd0v9";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd1v8";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+};
-+
-+&combphy0 {
-+	status = "okay";
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&combphy2 {
-+	status = "okay";
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac0 {
-+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-+	assigned-clock-rates = <0>, <125000000>;
-+	clock_in_out = "output";
-+	phy-handle = <&rgmii_phy0>;
-+	phy-mode = "rgmii-id";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac0_miim
-+		     &gmac0_tx_bus2
-+		     &gmac0_rx_bus2
-+		     &gmac0_rgmii_clk
-+		     &gmac0_rgmii_bus>;
-+	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 15ms, 50ms for rtl8211f */
-+	snps,reset-delays-us = <0 15000 50000>;
-+	tx_delay = <0x3c>;
-+	rx_delay = <0x2f>;
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	avdd-0v9-supply = <&vdda0v9_image>;
-+	avdd-1v8-supply = <&vcca1v8_image>;
-+	status = "okay";
-+};
-+
-+&hdmi_in {
-+	hdmi_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi>;
-+	};
-+};
-+
-+&hdmi_out {
-+	hdmi_out_con: endpoint {
-+		remote-endpoint = <&hdmi_con_in>;
-+	};
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <800000>;
-+		regulator-max-microvolt = <1150000>;
-+		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc5v0_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		wakeup-source;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-always-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-min-microvolt = <950000>;
-+				regulator-max-microvolt = <950000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+
-+	};
-+};
-+
-+&i2c5 {
-+	status = "okay";
-+
-+	hym8563: rtc@51 {
-+		compatible = "haoyu,hym8563";
-+		reg = <0x51>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <0>;
-+		clock-output-names = "rtcic_32kout";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&hym8563_int>;
-+		wakeup-source;
-+	};
-+};
-+
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
-+&i2s1_8ch {
-+	rockchip,trcm-sync-tx-only;
-+	status = "okay";
-+};
-+
-+&mdio0 {
-+	rgmii_phy0: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+		pinctrl-0 = <&eth_phy0_reset_pin>;
-+		pinctrl-names = "default";
-+		reset-assert-us = <10000>;
-+		reset-deassert-us = <50000>;
-+		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
-+	};
-+};
-+
-+&pcie2x1 {
-+	num-lanes = <1>;
-+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+	status = "okay";
-+};
-+
-+&pcie30phy {
-+	data-lanes = <1 2>;
-+	status = "okay";
-+};
-+
-+&pcie3x1 {
-+	num-lanes = <1>;
-+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pcie>;
-+	status = "okay";
-+};
-+
-+&pcie3x2 {
-+	num-lanes = <1>;
-+	num-ib-windows = <8>;
-+	num-ob-windows = <8>;
-+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pcie>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	gmac0 {
-+		eth_phy0_reset_pin: eth-phy0-reset-pin {
-+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		lan1_led_pin: lan1-led-pin {
-+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		lan2_led_pin: lan2-led-pin {
-+			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		power_led_pin: power-led-pin {
-+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	hym8563 {
-+		hym8563_int: hym8563-int {
-+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic-int {
-+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	max-frequency = <150000000>;
-+	no-sdio;
-+	no-mmc;
-+	bus-width = <4>;
-+	cap-mmc-highspeed;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	extcon = <&usb2phy0>;
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+	status = "okay";
-+};
-+
-+&usb2phy0 {
-+	status = "okay";
-+};
-+
-+&usb2phy0_host {
-+	phy-supply = <&vcc5v0_usb_host>;
-+	status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+	status = "okay";
-+};
-+
-+&usb2phy1 {
-+	status = "okay";
-+};
-+
-+&usb2phy1_host {
-+	phy-supply = <&vcc5v0_usb_otg>;
-+	status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+	status = "okay";
-+};
-+
-+&vop {
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi_in_vp0>;
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch b/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch
deleted file mode 100644
index cf9fe06ad0..0000000000
--- a/target/linux/rockchip/patches-6.1/010-v6.4-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-serie.patch
+++ /dev/null
@@ -1,1226 +0,0 @@
-From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:41 +0800
-Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series
-
-Create common dtsi for the FriendlyElec NanoPi R5 series.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts   | 575 +----------------
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi  | 596 ++++++++++++++++++
- 2 files changed, 597 insertions(+), 574 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -7,12 +7,7 @@
-  */
- 
- /dts-v1/;
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/input/input.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/pinctrl/rockchip.h>
--#include <dt-bindings/soc/rockchip,vop2.h>
--#include "rk3568.dtsi"
-+#include "rk3568-nanopi-r5s.dtsi"
- 
- / {
- 	model = "FriendlyElec NanoPi R5S";
-@@ -20,23 +15,6 @@
- 
- 	aliases {
- 		ethernet0 = &gmac0;
--		mmc0 = &sdmmc0;
--		mmc1 = &sdhci;
--	};
--
--	chosen: chosen {
--		stdout-path = "serial2:1500000n8";
--	};
--
--	hdmi-con {
--		compatible = "hdmi-connector";
--		type = "a";
--
--		port {
--			hdmi_con_in: endpoint {
--				remote-endpoint = <&hdmi_out_con>;
--			};
--		};
- 	};
- 
- 	gpio-leds {
-@@ -71,130 +49,6 @@
- 			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- 		};
- 	};
--
--	vdd_usbc: vdd-usbc-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "vdd_usbc";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--	};
--
--	vcc3v3_sys: vcc3v3-sys-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "vcc3v3_sys";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <3300000>;
--		regulator-max-microvolt = <3300000>;
--		vin-supply = <&vdd_usbc>;
--	};
--
--	vcc5v0_sys: vcc5v0-sys-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "vcc5v0_sys";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&vdd_usbc>;
--	};
--
--	vcc3v3_pcie: vcc3v3-pcie-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "vcc3v3_pcie";
--		regulator-min-microvolt = <3300000>;
--		regulator-max-microvolt = <3300000>;
--		enable-active-high;
--		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
--		startup-delay-us = <200000>;
--		vin-supply = <&vcc5v0_sys>;
--	};
--
--	vcc5v0_usb: vcc5v0-usb-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "vcc5v0_usb";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&vdd_usbc>;
--	};
--
--	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
--		compatible = "regulator-fixed";
--		enable-active-high;
--		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
--		pinctrl-names = "default";
--		pinctrl-0 = <&vcc5v0_usb_host_en>;
--		regulator-name = "vcc5v0_usb_host";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&vcc5v0_usb>;
--	};
--
--	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
--		compatible = "regulator-fixed";
--		enable-active-high;
--		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
--		pinctrl-names = "default";
--		pinctrl-0 = <&vcc5v0_usb_otg_en>;
--		regulator-name = "vcc5v0_usb_otg";
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&vcc5v0_usb>;
--	};
--
--	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "pcie30_avdd0v9";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <900000>;
--		regulator-max-microvolt = <900000>;
--		vin-supply = <&vcc3v3_sys>;
--	};
--
--	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
--		compatible = "regulator-fixed";
--		regulator-name = "pcie30_avdd1v8";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <1800000>;
--		regulator-max-microvolt = <1800000>;
--		vin-supply = <&vcc3v3_sys>;
--	};
--};
--
--&combphy0 {
--	status = "okay";
--};
--
--&combphy1 {
--	status = "okay";
--};
--
--&combphy2 {
--	status = "okay";
--};
--
--&cpu0 {
--	cpu-supply = <&vdd_cpu>;
--};
--
--&cpu1 {
--	cpu-supply = <&vdd_cpu>;
--};
--
--&cpu2 {
--	cpu-supply = <&vdd_cpu>;
--};
--
--&cpu3 {
--	cpu-supply = <&vdd_cpu>;
- };
- 
- &gmac0 {
-@@ -219,292 +73,6 @@
- 	status = "okay";
- };
- 
--&gpu {
--	mali-supply = <&vdd_gpu>;
--	status = "okay";
--};
--
--&hdmi {
--	avdd-0v9-supply = <&vdda0v9_image>;
--	avdd-1v8-supply = <&vcca1v8_image>;
--	status = "okay";
--};
--
--&hdmi_in {
--	hdmi_in_vp0: endpoint {
--		remote-endpoint = <&vp0_out_hdmi>;
--	};
--};
--
--&hdmi_out {
--	hdmi_out_con: endpoint {
--		remote-endpoint = <&hdmi_con_in>;
--	};
--};
--
--&hdmi_sound {
--	status = "okay";
--};
--
--&i2c0 {
--	status = "okay";
--
--	vdd_cpu: regulator@1c {
--		compatible = "tcs,tcs4525";
--		reg = <0x1c>;
--		fcs,suspend-voltage-selector = <1>;
--		regulator-name = "vdd_cpu";
--		regulator-always-on;
--		regulator-boot-on;
--		regulator-min-microvolt = <800000>;
--		regulator-max-microvolt = <1150000>;
--		regulator-ramp-delay = <2300>;
--		vin-supply = <&vcc5v0_sys>;
--
--		regulator-state-mem {
--			regulator-off-in-suspend;
--		};
--	};
--
--	rk809: pmic@20 {
--		compatible = "rockchip,rk809";
--		reg = <0x20>;
--		interrupt-parent = <&gpio0>;
--		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
--		#clock-cells = <1>;
--		pinctrl-names = "default";
--		pinctrl-0 = <&pmic_int>;
--		rockchip,system-power-controller;
--		vcc1-supply = <&vcc3v3_sys>;
--		vcc2-supply = <&vcc3v3_sys>;
--		vcc3-supply = <&vcc3v3_sys>;
--		vcc4-supply = <&vcc3v3_sys>;
--		vcc5-supply = <&vcc3v3_sys>;
--		vcc6-supply = <&vcc3v3_sys>;
--		vcc7-supply = <&vcc3v3_sys>;
--		vcc8-supply = <&vcc3v3_sys>;
--		vcc9-supply = <&vcc3v3_sys>;
--		wakeup-source;
--
--		regulators {
--			vdd_logic: DCDC_REG1 {
--				regulator-name = "vdd_logic";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-init-microvolt = <900000>;
--				regulator-initial-mode = <0x2>;
--				regulator-min-microvolt = <500000>;
--				regulator-max-microvolt = <1350000>;
--				regulator-ramp-delay = <6001>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vdd_gpu: DCDC_REG2 {
--				regulator-name = "vdd_gpu";
--				regulator-always-on;
--				regulator-init-microvolt = <900000>;
--				regulator-initial-mode = <0x2>;
--				regulator-min-microvolt = <500000>;
--				regulator-max-microvolt = <1350000>;
--				regulator-ramp-delay = <6001>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcc_ddr: DCDC_REG3 {
--				regulator-name = "vcc_ddr";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-initial-mode = <0x2>;
--
--				regulator-state-mem {
--					regulator-on-in-suspend;
--				};
--			};
--
--			vdd_npu: DCDC_REG4 {
--				regulator-name = "vdd_npu";
--				regulator-init-microvolt = <900000>;
--				regulator-initial-mode = <0x2>;
--				regulator-min-microvolt = <500000>;
--				regulator-max-microvolt = <1350000>;
--				regulator-ramp-delay = <6001>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcc_1v8: DCDC_REG5 {
--				regulator-name = "vcc_1v8";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <1800000>;
--				regulator-max-microvolt = <1800000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vdda0v9_image: LDO_REG1 {
--				regulator-name = "vdda0v9_image";
--				regulator-min-microvolt = <950000>;
--				regulator-max-microvolt = <950000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vdda_0v9: LDO_REG2 {
--				regulator-name = "vdda_0v9";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <900000>;
--				regulator-max-microvolt = <900000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vdda0v9_pmu: LDO_REG3 {
--				regulator-name = "vdda0v9_pmu";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <900000>;
--				regulator-max-microvolt = <900000>;
--
--				regulator-state-mem {
--					regulator-on-in-suspend;
--					regulator-suspend-microvolt = <900000>;
--				};
--			};
--
--			vccio_acodec: LDO_REG4 {
--				regulator-name = "vccio_acodec";
--				regulator-always-on;
--				regulator-min-microvolt = <3300000>;
--				regulator-max-microvolt = <3300000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vccio_sd: LDO_REG5 {
--				regulator-name = "vccio_sd";
--				regulator-min-microvolt = <1800000>;
--				regulator-max-microvolt = <3300000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcc3v3_pmu: LDO_REG6 {
--				regulator-name = "vcc3v3_pmu";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <3300000>;
--				regulator-max-microvolt = <3300000>;
--
--				regulator-state-mem {
--					regulator-on-in-suspend;
--					regulator-suspend-microvolt = <3300000>;
--				};
--			};
--
--			vcca_1v8: LDO_REG7 {
--				regulator-name = "vcca_1v8";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <1800000>;
--				regulator-max-microvolt = <1800000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcca1v8_pmu: LDO_REG8 {
--				regulator-name = "vcca1v8_pmu";
--				regulator-always-on;
--				regulator-boot-on;
--				regulator-min-microvolt = <1800000>;
--				regulator-max-microvolt = <1800000>;
--
--				regulator-state-mem {
--					regulator-on-in-suspend;
--					regulator-suspend-microvolt = <1800000>;
--				};
--			};
--
--			vcca1v8_image: LDO_REG9 {
--				regulator-name = "vcca1v8_image";
--				regulator-min-microvolt = <1800000>;
--				regulator-max-microvolt = <1800000>;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcc_3v3: SWITCH_REG1 {
--				regulator-name = "vcc_3v3";
--				regulator-always-on;
--				regulator-boot-on;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--
--			vcc3v3_sd: SWITCH_REG2 {
--				regulator-name = "vcc3v3_sd";
--				regulator-always-on;
--				regulator-boot-on;
--
--				regulator-state-mem {
--					regulator-off-in-suspend;
--				};
--			};
--		};
--
--	};
--};
--
--&i2c5 {
--	status = "okay";
--
--	hym8563: rtc@51 {
--		compatible = "haoyu,hym8563";
--		reg = <0x51>;
--		interrupt-parent = <&gpio0>;
--		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
--		#clock-cells = <0>;
--		clock-output-names = "rtcic_32kout";
--		pinctrl-names = "default";
--		pinctrl-0 = <&hym8563_int>;
--		wakeup-source;
--	};
--};
--
--&i2s0_8ch {
--	status = "okay";
--};
--
--&i2s1_8ch {
--	rockchip,trcm-sync-tx-only;
--	status = "okay";
--};
--
- &mdio0 {
- 	rgmii_phy0: ethernet-phy@1 {
- 		compatible = "ethernet-phy-ieee802.3-c22";
-@@ -568,146 +136,5 @@
- 			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- 		};
- 	};
--
--	hym8563 {
--		hym8563_int: hym8563-int {
--			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
--		};
--	};
--
--	pmic {
--		pmic_int: pmic-int {
--			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
--		};
--	};
--
--	usb {
--		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
--			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
--		};
--
--		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
--			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
--		};
--	};
--};
--
--&pmu_io_domains {
--	pmuio1-supply = <&vcc3v3_pmu>;
--	pmuio2-supply = <&vcc3v3_pmu>;
--	vccio1-supply = <&vccio_acodec>;
--	vccio3-supply = <&vccio_sd>;
--	vccio4-supply = <&vcc_1v8>;
--	vccio5-supply = <&vcc_3v3>;
--	vccio6-supply = <&vcc_1v8>;
--	vccio7-supply = <&vcc_3v3>;
--	status = "okay";
--};
--
--&saradc {
--	vref-supply = <&vcca_1v8>;
--	status = "okay";
--};
--
--&sdhci {
--	bus-width = <8>;
--	max-frequency = <200000000>;
--	non-removable;
--	pinctrl-names = "default";
--	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
--	status = "okay";
--};
--
--&sdmmc0 {
--	max-frequency = <150000000>;
--	no-sdio;
--	no-mmc;
--	bus-width = <4>;
--	cap-mmc-highspeed;
--	cap-sd-highspeed;
--	disable-wp;
--	vmmc-supply = <&vcc3v3_sd>;
--	vqmmc-supply = <&vccio_sd>;
--	pinctrl-names = "default";
--	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
--	status = "okay";
--};
--
--&tsadc {
--	rockchip,hw-tshut-mode = <1>;
--	rockchip,hw-tshut-polarity = <0>;
--	status = "okay";
--};
--
--&uart2 {
--	status = "okay";
--};
--
--&usb_host0_ehci {
--	status = "okay";
--};
--
--&usb_host0_ohci {
--	status = "okay";
--};
--
--&usb_host0_xhci {
--	extcon = <&usb2phy0>;
--	dr_mode = "host";
--	status = "okay";
--};
--
--&usb_host1_ehci {
--	status = "okay";
--};
--
--&usb_host1_ohci {
--	status = "okay";
- };
- 
--&usb_host1_xhci {
--	status = "okay";
--};
--
--&usb2phy0 {
--	status = "okay";
--};
--
--&usb2phy0_host {
--	phy-supply = <&vcc5v0_usb_host>;
--	status = "okay";
--};
--
--&usb2phy0_otg {
--	status = "okay";
--};
--
--&usb2phy1 {
--	status = "okay";
--};
--
--&usb2phy1_host {
--	phy-supply = <&vcc5v0_usb_otg>;
--	status = "okay";
--};
--
--&usb2phy1_otg {
--	status = "okay";
--};
--
--&vop {
--	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
--	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
--	status = "okay";
--};
--
--&vop_mmu {
--	status = "okay";
--};
--
--&vp0 {
--	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
--		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
--		remote-endpoint = <&hdmi_in_vp0>;
--	};
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -0,0 +1,596 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+	aliases {
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	hdmi-con {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_con_in: endpoint {
-+				remote-endpoint = <&hdmi_out_con>;
-+			};
-+		};
-+	};
-+
-+	vdd_usbc: vdd-usbc-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vdd_usbc";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc3v3_pcie: vcc3v3-pcie-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_pcie";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		enable-active-high;
-+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+		startup-delay-us = <200000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_usb: vcc5v0-usb-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vdd_usbc>;
-+	};
-+
-+	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb_host_en>;
-+		regulator-name = "vcc5v0_usb_host";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+		regulator-name = "vcc5v0_usb_otg";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd0v9";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd1v8";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+};
-+
-+&combphy0 {
-+	status = "okay";
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&combphy2 {
-+	status = "okay";
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	avdd-0v9-supply = <&vdda0v9_image>;
-+	avdd-1v8-supply = <&vcca1v8_image>;
-+	status = "okay";
-+};
-+
-+&hdmi_in {
-+	hdmi_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi>;
-+	};
-+};
-+
-+&hdmi_out {
-+	hdmi_out_con: endpoint {
-+		remote-endpoint = <&hdmi_con_in>;
-+	};
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <800000>;
-+		regulator-max-microvolt = <1150000>;
-+		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc5v0_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		wakeup-source;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-always-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-min-microvolt = <950000>;
-+				regulator-max-microvolt = <950000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+
-+	};
-+};
-+
-+&i2c5 {
-+	status = "okay";
-+
-+	hym8563: rtc@51 {
-+		compatible = "haoyu,hym8563";
-+		reg = <0x51>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <0>;
-+		clock-output-names = "rtcic_32kout";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&hym8563_int>;
-+		wakeup-source;
-+	};
-+};
-+
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
-+&i2s1_8ch {
-+	rockchip,trcm-sync-tx-only;
-+	status = "okay";
-+};
-+
-+&pcie30phy {
-+	data-lanes = <1 2>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	hym8563 {
-+		hym8563_int: hym8563-int {
-+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic-int {
-+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	max-frequency = <150000000>;
-+	no-sdio;
-+	no-mmc;
-+	bus-width = <4>;
-+	cap-mmc-highspeed;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	extcon = <&usb2phy0>;
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+	status = "okay";
-+};
-+
-+&usb2phy0 {
-+	status = "okay";
-+};
-+
-+&usb2phy0_host {
-+	phy-supply = <&vcc5v0_usb_host>;
-+	status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+	status = "okay";
-+};
-+
-+&usb2phy1 {
-+	status = "okay";
-+};
-+
-+&usb2phy1_host {
-+	phy-supply = <&vcc5v0_usb_otg>;
-+	status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+	status = "okay";
-+};
-+
-+&vop {
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi_in_vp0>;
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
deleted file mode 100644
index 47f76d54e7..0000000000
--- a/target/linux/rockchip/patches-6.1/011-v6.4-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:44 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
-
-- Changed phy-mode to rgmii.
-
-- Fixed pull type in pinctrl for gmac0.
-
-- Removed duplicate properties in mdio node.
-  These properties are defined in the gmac0 node already.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -57,7 +57,7 @@
- 	assigned-clock-rates = <0>, <125000000>;
- 	clock_in_out = "output";
- 	phy-handle = <&rgmii_phy0>;
--	phy-mode = "rgmii-id";
-+	phy-mode = "rgmii";
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&gmac0_miim
- 		     &gmac0_tx_bus2
-@@ -79,9 +79,6 @@
- 		reg = <1>;
- 		pinctrl-0 = <&eth_phy0_reset_pin>;
- 		pinctrl-names = "default";
--		reset-assert-us = <10000>;
--		reset-deassert-us = <50000>;
--		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
- 	};
- };
- 
-@@ -115,7 +112,7 @@
- &pinctrl {
- 	gmac0 {
- 		eth_phy0_reset_pin: eth-phy0-reset-pin {
--			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
- 		};
- 	};
- 
diff --git a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch b/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch
deleted file mode 100644
index 48021b226a..0000000000
--- a/target/linux/rockchip/patches-6.1/012-v6.4-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-NanoPi-R5.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:45 +0800
-Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5
- series
-
-This is for the audio output which does not exist on the boards.
-Also disable regulator-always-on for vccio_acodec since it's only
-used by the audio output.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
- 1 file changed, 6 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -330,7 +330,6 @@
- 
- 			vccio_acodec: LDO_REG4 {
- 				regulator-name = "vccio_acodec";
--				regulator-always-on;
- 				regulator-min-microvolt = <3300000>;
- 				regulator-max-microvolt = <3300000>;
- 
-@@ -441,11 +440,6 @@
- 	status = "okay";
- };
- 
--&i2s1_8ch {
--	rockchip,trcm-sync-tx-only;
--	status = "okay";
--};
--
- &pcie30phy {
- 	data-lanes = <1 2>;
- 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch
deleted file mode 100644
index 0465d80cba..0000000000
--- a/target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch
+++ /dev/null
@@ -1,152 +0,0 @@
-From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:43 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
-
-FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
-
-Specification:
-- Rockchip RK3568
-- 1/4GB LPDDR4X RAM
-- 8/32GB eMMC
-- SD card slot
-- M.2 Connector
-- 2x USB 3.0 Port
-- 2x 2500 Base-T (PCIe, r8125)
-- HDMI 2.0
-- MIPI DSI/CSI
-- USB Type C 5V
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5c.dts   | 112 ++++++++++++++++++
- 2 files changed, 113 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -0,0 +1,112 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3568-nanopi-r5s.dtsi"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R5C";
-+	compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
-+
-+	gpio-keys {
-+		compatible = "gpio-keys";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&reset_button_pin>;
-+
-+		button-reset {
-+			debounce-interval = <50>;
-+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
-+			label = "reset";
-+			linux,code = <KEY_RESTART>;
-+		};
-+	};
-+
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
-+
-+		led-lan {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_LAN;
-+			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		power_led: led-power {
-+			color = <LED_COLOR_ID_RED>;
-+			function = LED_FUNCTION_POWER;
-+			linux,default-trigger = "heartbeat";
-+			gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-wan {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_WAN;
-+			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
-+		};
-+
-+		led-wlan {
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_WLAN;
-+			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
-+		};
-+	};
-+};
-+
-+&pcie2x1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie20_reset_pin>;
-+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
-+	status = "okay";
-+};
-+
-+&pcie3x1 {
-+	num-lanes = <1>;
-+	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pcie>;
-+	status = "okay";
-+};
-+
-+&pcie3x2 {
-+	num-lanes = <1>;
-+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pcie>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	gpio-leds {
-+		lan_led_pin: lan-led-pin {
-+			rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		power_led_pin: power-led-pin {
-+			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wan_led_pin: wan-led-pin {
-+			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wlan_led_pin: wlan-led-pin {
-+			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pcie {
-+		pcie20_reset_pin: pcie20-reset-pin {
-+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	rockchip-key {
-+		reset_button_pin: reset-button-pin {
-+			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch b/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch
deleted file mode 100644
index 0e59f0275b..0000000000
--- a/target/linux/rockchip/patches-6.1/014-v6.4-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r5c.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Thu, 11 May 2023 00:18:50 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c
-
-The reset pin was wrongly assigned due to a copy/paste error,
-fix it to match actual gpio pin.
-
-While at it, remove a blank line from nanopi r5s dts.
-
-Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -106,7 +106,7 @@
- 
- 	rockchip-key {
- 		reset_button_pin: reset-button-pin {
--			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
- 		};
- 	};
- };
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -134,4 +134,3 @@
- 		};
- 	};
- };
--
diff --git a/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch b/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch
deleted file mode 100644
index 01efaa3a9d..0000000000
--- a/target/linux/rockchip/patches-6.1/015-v6.8-arm64-dts-rockchip-configure-eth-pad-driver-strength-for-.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 16 Dec 2023 12:07:23 +0800
-Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength
- for orangepi r1 plus lts
-
-The default strength is not enough to provide stable connection
-under 3.3v LDO voltage.
-
-Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
-Cc: stable@vger.kernel.org # 6.6+
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -26,9 +26,11 @@
- 			compatible = "ethernet-phy-ieee802.3-c22";
- 			reg = <0>;
- 
-+			motorcomm,auto-sleep-disabled;
- 			motorcomm,clk-out-frequency-hz = <125000000>;
- 			motorcomm,keep-pll-enabled;
--			motorcomm,auto-sleep-disabled;
-+			motorcomm,rx-clk-drv-microamp = <5020>;
-+			motorcomm,rx-data-drv-microamp = <5020>;
- 
- 			pinctrl-0 = <&eth_phy_reset_pin>;
- 			pinctrl-names = "default";
diff --git a/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch b/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch
deleted file mode 100644
index b4a68d1558..0000000000
--- a/target/linux/rockchip/patches-6.1/016-v6.3-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-board.patch
+++ /dev/null
@@ -1,233 +0,0 @@
-From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:02 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board
-
-Radxa Compute Module 3(CM3) IO board is an application board from Radxa
-and is compatible with Raspberry Pi CM4 IO form factor.
-
-Specification:
-- 1x HDMI,
-- 2x MIPI DSI
-- 2x MIPI CSI2
-- 1x eDP
-- 1x PCIe card
-- 2x SATA
-- 2x USB 2.0 Host
-- 1x USB 3.0
-- 1x USB 2.0 OTG
-- Phone jack
-- microSD slot
-- 40-pin GPIO expansion header
-- 12V DC
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Add support for Radxa CM3 IO Board.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
- 2 files changed, 180 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -0,0 +1,179 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3566.dtsi"
-+#include "rk3566-radxa-cm3.dtsi"
-+
-+/ {
-+	model = "Radxa Compute Module 3(CM3) IO Board";
-+	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+	aliases {
-+		mmc1 = &sdmmc0;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	hdmi-con {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_con_in: endpoint {
-+				remote-endpoint = <&hdmi_out_con>;
-+			};
-+		};
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-1 {
-+			gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_ACTIVITY;
-+			linux,default-trigger = "heartbeat";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pi_nled_activity>;
-+		};
-+	};
-+
-+	vcc5v0_usb30: vcc5v0-usb30-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb30";
-+		enable-active-high;
-+		gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb30_en_h>;
-+		regulator-always-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc_sys>;
-+	};
-+
-+	vcca1v8_image: vcca1v8-image-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcca1v8_image";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc_1v8_p>;
-+	};
-+
-+	vdda0v9_image: vdda0v9-image-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcca0v9_image";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		vin-supply = <&vdda_0v9>;
-+	};
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	avdd-0v9-supply = <&vdda0v9_image>;
-+	avdd-1v8-supply = <&vcca1v8_image>;
-+	status = "okay";
-+};
-+
-+&hdmi_in {
-+	hdmi_in_vp0: endpoint {
-+		remote-endpoint = <&vp0_out_hdmi>;
-+	};
-+};
-+
-+&hdmi_out {
-+	hdmi_out_con: endpoint {
-+		remote-endpoint = <&hdmi_con_in>;
-+	};
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	leds {
-+		pi_nled_activity: pi-nled-activity {
-+			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdcard {
-+		sdmmc_pwren: sdmmc-pwren {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_usb30_en_h: vcc5v0-host-en-h {
-+			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	cap-mmc-highspeed;
-+	cap-sd-highspeed;
-+	disable-wp;
-+	vqmmc-supply = <&vccio_sd>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb2phy0_host {
-+	phy-supply = <&vcc5v0_usb30>;
-+	status = "okay";
-+};
-+
-+&usb2phy1_host {
-+	status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+	status = "okay";
-+};
-+
-+&vop {
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+	status = "okay";
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0 {
-+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+		remote-endpoint = <&hdmi_in_vp0>;
-+	};
-+};
diff --git a/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch b/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
deleted file mode 100644
index d0a0aa1b69..0000000000
--- a/target/linux/rockchip/patches-6.1/016-v6.5-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 13 May 2023 21:53:07 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
-
-The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
-eMMC flash (8G) included.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile              |  1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts   | 33 ++++++++++++++++++++++
- 2 files changed, 34 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-@@ -0,0 +1,33 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2c.dts"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2C Plus";
-+	compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
-+
-+	aliases {
-+		mmc1 = &emmc;
-+	};
-+};
-+
-+&emmc {
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	max-frequency = <150000000>;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+	vmmc-supply = <&vcc_io_33>;
-+	vqmmc-supply = <&vcc18_emmc>;
-+	status = "okay";
-+};
diff --git a/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch b/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
deleted file mode 100644
index 305b5702d5..0000000000
--- a/target/linux/rockchip/patches-6.1/017-v6.3-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
+++ /dev/null
@@ -1,131 +0,0 @@
-From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:22 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
-
-Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
- 1 file changed, 93 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -21,6 +21,13 @@
- 		stdout-path = "serial2:1500000n8";
- 	};
- 
-+	gmac1_clkin: external-gmac1-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac1_clkin";
-+		#clock-cells = <0>;
-+	};
-+
- 	hdmi-con {
- 		compatible = "hdmi-connector";
- 		type = "a";
-@@ -83,6 +90,29 @@
- 	status = "okay";
- };
- 
-+&gmac1 {
-+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+	assigned-clock-rates = <0>, <125000000>;
-+	clock_in_out = "input";
-+	phy-handle = <&rgmii_phy1>;
-+	phy-mode = "rgmii";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac1m0_miim
-+		     &gmac1m0_tx_bus2
-+		     &gmac1m0_rx_bus2
-+		     &gmac1m0_rgmii_clk
-+		     &gmac1m0_rgmii_bus
-+		     &gmac1m0_clkinout>;
-+	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 20ms, 100ms for rtl8211f */
-+	snps,reset-delays-us = <0 20000 100000>;
-+	tx_delay = <0x46>;
-+	rx_delay = <0x2e>;
-+	status = "okay";
-+};
-+
- &hdmi {
- 	avdd-0v9-supply = <&vdda0v9_image>;
- 	avdd-1v8-supply = <&vcca1v8_image>;
-@@ -105,7 +135,70 @@
- 	status = "okay";
- };
- 
-+&mdio1 {
-+	rgmii_phy1: ethernet-phy@0 {
-+		compatible="ethernet-phy-ieee802.3-c22";
-+		reg= <0x0>;
-+	};
-+};
-+
- &pinctrl {
-+	gmac1 {
-+		gmac1m0_miim: gmac1m0-miim {
-+			rockchip,pins =
-+				/* gmac1_mdcm0 */
-+				<3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_mdiom0 */
-+				<3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+
-+		gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
-+			rockchip,pins =
-+				/* gmac1_rxd0m0 */
-+				<3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_rxd1m0 */
-+				<3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_rxdvcrsm0 */
-+				<3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+
-+		gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
-+			rockchip,pins =
-+				/* gmac1_txd0m0 */
-+				<3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_txd1m0 */
-+				<3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_txenm0 */
-+				<3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+
-+		gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
-+			rockchip,pins =
-+				/* gmac1_rxclkm0 */
-+				<3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_txclkm0 */
-+				<3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+
-+		gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
-+			rockchip,pins =
-+				/* gmac1_rxd2m0 */
-+				<3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_rxd3m0 */
-+				<3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_txd2m0 */
-+				<3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
-+				/* gmac1_txd3m0 */
-+				<3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+
-+		gmac1m0_clkinout: gmac1m0-clkinout {
-+			rockchip,pins =
-+				/* gmac1_mclkinoutm0 */
-+				<3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
-+		};
-+	};
-+
- 	leds {
- 		pi_nled_activity: pi-nled-activity {
- 			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch b/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch
deleted file mode 100644
index e53f7fa7e0..0000000000
--- a/target/linux/rockchip/patches-6.1/018-v6.3-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Module-3.patch
+++ /dev/null
@@ -1,386 +0,0 @@
-From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:01 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Radxa Compute Module 3(CM3) is one of the modules from a series
-System On Module based on the Radxa ROCK 3 series and is compatible
-with Raspberry Pi CM4 pinout and form factor.
-
-Specification:
-- Rockchip RK3566
-- up to 8GB LPDDR4
-- up to 128GB high performance eMMC
-- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
-  BT 5.0, BLE with onboard and external antenna.
-- Gigabit Ethernet PHY
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
-possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
-
-Add support for Radxa CM3.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 345 ++++++++++++++++++
- 1 file changed, 345 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -0,0 +1,345 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+	aliases {
-+		mmc0 = &sdhci;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-0 {
-+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+			color = <LED_COLOR_ID_GREEN>;
-+			function = LED_FUNCTION_STATUS;
-+			linux,default-trigger = "timer";
-+			default-state = "on";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&user_led2>;
-+		};
-+	};
-+
-+	vcc_sys: vcc-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc_1v8: vcc-1v8-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_1v8";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc_1v8_p>;
-+	};
-+
-+	vcc_3v3: vcc-3v3-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_3v3";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	vcca_1v8: vcca-1v8-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcca_1v8";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc_1v8_p>;
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu_npu>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <712500>;
-+		regulator-max-microvolt = <1390000>;
-+		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk817: pmic@20 {
-+		compatible = "rockchip,rk817";
-+		reg = <0x20>;
-+		#clock-cells = <1>;
-+		clock-output-names = "rk817-clkout1", "rk817-clkout2";
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int_l>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc_sys>;
-+		vcc2-supply = <&vcc_sys>;
-+		vcc3-supply = <&vcc_sys>;
-+		vcc4-supply = <&vcc_sys>;
-+		vcc5-supply = <&vcc_sys>;
-+		vcc6-supply = <&vcc_sys>;
-+		vcc7-supply = <&vcc_sys>;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vdd_gpu_npu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu_npu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sys: DCDC_REG4 {
-+				regulator-name = "vcc3v3_sys";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG1 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc_1v8_p: LDO_REG7 {
-+				regulator-name = "vcc_1v8_p";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc1v8_dvp: LDO_REG8 {
-+				regulator-name = "vcc1v8_dvp";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc2v8_dvp: LDO_REG9 {
-+				regulator-name = "vcc2v8_dvp";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <2800000>;
-+				regulator-max-microvolt = <2800000>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+		};
-+	};
-+};
-+
-+&pinctrl {
-+	pmic {
-+		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	leds {
-+		user_led2: user-led2 {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc_3v3>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio2-supply = <&vcc_1v8>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_3v3>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+};
-+
-+&usb2phy0 {
-+	status = "okay";
-+};
-+
-+&usb2phy1 {
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
diff --git a/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch
deleted file mode 100644
index 9855b9e1a6..0000000000
--- a/target/linux/rockchip/patches-6.1/019-v6.3-arm64-dts-rockchip-Enable-WiFi-BT-support-for-Radxa-CM3.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:23 +0530
-Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for
- Radxa CM3
-
-Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
-
-Add nodes for enabling it.
-
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 80 +++++++++++++++++++
- 1 file changed, 80 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -66,6 +66,15 @@
- 		regulator-max-microvolt = <1800000>;
- 		vin-supply = <&vcc_1v8_p>;
- 	};
-+
-+	sdio_pwrseq: pwrseq-sdio {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk817 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_reg_on_h>;
-+		reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
-+	};
- };
- 
- &cpu0 {
-@@ -287,6 +296,20 @@
- };
- 
- &pinctrl {
-+	bluetooth {
-+		bt_host_wake_h: bt-host-wake-h {
-+			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_reg_on_h: bt-reg-on-h {
-+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_wake_host_h: bt-wake-host-h {
-+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	pmic {
- 		pmic_int_l: pmic-int-l {
- 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-@@ -298,6 +321,16 @@
- 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- 		};
- 	};
-+
-+	wifi {
-+		wifi_reg_on_h: wifi-reg-on-h {
-+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		wifi_host_wake_h: wifi-host-wake-h {
-+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
- };
- 
- &pmu_io_domains {
-@@ -318,6 +351,34 @@
- 	status = "okay";
- };
- 
-+&sdmmc1 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	bus-width = <4>;
-+	disable-wp;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+
-+	wifi@1 {
-+		compatible = "brcm,bcm43455-fmac";
-+		reg = <1>;
-+		interrupt-parent = <&gpio2>;
-+		interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "host-wake";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_host_wake_h>;
-+	};
-+};
-+
- &sdhci {
- 	bus-width = <8>;
- 	max-frequency = <200000000>;
-@@ -330,6 +391,25 @@
- 	status = "okay";
- };
- 
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm4345c5";
-+		clocks = <&rk817 1>;
-+		clock-names = "lpo";
-+		device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
-+		host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
-+		reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
-+		vbat-supply = <&vcc_3v3>;
-+		vddio-supply = <&vcc_1v8>;
-+	};
-+};
-+
- &usb2phy0 {
- 	status = "okay";
- };
diff --git a/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch
deleted file mode 100644
index bfd6dbe0db..0000000000
--- a/target/linux/rockchip/patches-6.1/020-v6.4-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-CM3.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Thu, 23 Feb 2023 19:29:29 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
-
-Enable USB OTG support for Radxa Compute Module 3 IO Board
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -254,6 +254,14 @@
- 	status = "okay";
- };
- 
-+&usb2phy0_otg {
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	status = "okay";
-+};
-+
- &vop {
- 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
deleted file mode 100644
index e7e3ea0100..0000000000
--- a/target/linux/rockchip/patches-6.1/021-v6.3-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:50 +0530
-Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3
-
-The compatible string "radxa,radxa-cm3" referring the product name
-as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
-
-Fix the compatible strings.
-
-Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
-Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
-Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
-Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -11,7 +11,7 @@
- 
- / {
- 	model = "Radxa Compute Module 3(CM3) IO Board";
--	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+	compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
- 
- 	aliases {
- 		mmc1 = &sdmmc0;
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -8,7 +8,7 @@
- #include <dt-bindings/leds/common.h>
- 
- / {
--	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+	compatible = "radxa,cm3", "rockchip,rk3566";
- 
- 	aliases {
- 		mmc0 = &sdhci;
diff --git a/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch b/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch
deleted file mode 100644
index 8342c14ea4..0000000000
--- a/target/linux/rockchip/patches-6.1/022-v6.5-arm64-dts-rockchip-minor-whitespace-cleanup-around.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sun, 2 Jul 2023 20:52:42 +0200
-Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '='
-
-The DTS code coding style expects exactly one space before and after '='
-sign.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts    |  4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -137,8 +137,8 @@
- 
- &mdio1 {
- 	rgmii_phy1: ethernet-phy@0 {
--		compatible="ethernet-phy-ieee802.3-c22";
--		reg= <0x0>;
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0x0>;
- 	};
- };
- 
diff --git a/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch b/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch
deleted file mode 100644
index 354c546d7e..0000000000
--- a/target/linux/rockchip/patches-6.1/024-v6.3-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch
+++ /dev/null
@@ -1,689 +0,0 @@
-From 2bf2f4d9f673013a58109626b87329310537a611 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 9 Dec 2022 18:25:24 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa CM3I E25
-
-Radxa E25 is a network application carrier board for the Radxa CM3
-Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
-
-It has the following features:
-
-- MicroSD card socket, on board eMMC flash
-- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
-- 1x USB Type-C port (Power and Serial console)
-- 1x USB 3.0 OTG port
-- mini PCIe socket (USB or PCIe)
-- ngff PCIe socket (USB or SATA)
-- 1x User LED and 16x RGB LEDs
-- 26-pin expansion header
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi  | 416 ++++++++++++++++++
- .../boot/dts/rockchip/rk3568-radxa-e25.dts    | 229 ++++++++++
- 3 files changed, 646 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -78,4 +78,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
-@@ -0,0 +1,416 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+	model = "Radxa CM3 Industrial Board";
-+	compatible = "radxa,cm3i", "rockchip,rk3568";
-+
-+	aliases {
-+		mmc0 = &sdhci;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial2:115200n8";
-+	};
-+
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+
-+		led_user: led-0 {
-+			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+			function = LED_FUNCTION_HEARTBEAT;
-+			color = <LED_COLOR_ID_GREEN>;
-+			linux,default-trigger = "heartbeat";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&led_user_en>;
-+		};
-+	};
-+
-+	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd0v9";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <900000>;
-+		regulator-max-microvolt = <900000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie30_avdd1v8";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		vin-supply = <&vcc3v3_sys>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v_input>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v_input>;
-+	};
-+
-+	/* labeled +5v_input in schematic */
-+	vcc5v_input: vcc5v-input-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v_input";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+};
-+
-+&combphy0 {
-+	status = "okay";
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&combphy2 {
-+	status = "okay";
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&display_subsystem {
-+	status = "disabled";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <800000>;
-+		regulator-max-microvolt = <1150000>;
-+		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc5v_input>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-always-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&pinctrl {
-+	leds {
-+		led_user_en: led_user_en {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio2-supply = <&vcc_1v8>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&usb2phy0 {
-+	status = "okay";
-+};
-+
-+&usb2phy1 {
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	extcon = <&usb2phy0>;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3568-radxa-cm3i.dtsi"
-+
-+/ {
-+	model = "Radxa E25";
-+	compatible = "radxa,e25", "rockchip,rk3568";
-+
-+	aliases {
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	pwm-leds {
-+		compatible = "pwm-leds-multicolor";
-+
-+		multi-led {
-+			color = <LED_COLOR_ID_RGB>;
-+			max-brightness = <255>;
-+
-+			led-red {
-+				color = <LED_COLOR_ID_RED>;
-+				pwms = <&pwm1 0 1000000 0>;
-+			};
-+
-+			led-green {
-+				color = <LED_COLOR_ID_GREEN>;
-+				pwms = <&pwm2 0 1000000 0>;
-+			};
-+
-+			led-blue {
-+				color = <LED_COLOR_ID_BLUE>;
-+				pwms = <&pwm12 0 1000000 0>;
-+			};
-+		};
-+	};
-+
-+	vbus_typec: vbus-typec-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vbus_typec_en>;
-+		regulator-name = "vbus_typec";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&minipcie_enable_h>;
-+		regulator-name = "vcc3v3_minipcie";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc3v3_ngff: vcc3v3-ngff-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&ngffpcie_enable_h>;
-+		regulator-name = "vcc3v3_ngff";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	/* actually fed by vcc5v0_sys, dependent
-+	 * on pi6c clock generator
-+	 */
-+	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pcie30x1_enable_h>;
-+		regulator-name = "vcc3v3_pcie30x1";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc3v3_pi6c_05>;
-+	};
-+
-+	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pcie_enable_h>;
-+		regulator-name = "vcc3v3_pcie";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+};
-+
-+&pcie2x1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie20_reset_h>;
-+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+	status = "okay";
-+};
-+
-+&pcie30phy {
-+	data-lanes = <1 2>;
-+	status = "okay";
-+};
-+
-+&pcie3x1 {
-+	num-lanes = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie30x1m0_pins>;
-+	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+	status = "okay";
-+};
-+
-+&pcie3x2 {
-+	num-lanes = <1>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie30x2_reset_h>;
-+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	pcie {
-+		pcie20_reset_h: pcie20-reset-h {
-+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		pcie30x1_enable_h: pcie30x1-enable-h {
-+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		pcie30x2_reset_h: pcie30x2-reset-h {
-+			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		pcie_enable_h: pcie-enable-h {
-+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		minipcie_enable_h: minipcie-enable-h {
-+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		ngffpcie_enable_h: ngffpcie-enable-h {
-+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		vbus_typec_en: vbus_typec_en {
-+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pwm1 {
-+	status = "okay";
-+};
-+
-+&pwm2 {
-+	status = "okay";
-+};
-+
-+&pwm12 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pwm12m1_pins>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+	/* Also used in pcie30x1_clkreqnm0 */
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+	phy-supply = <&vbus_typec>;
-+	status = "okay";
-+};
-+
-+&usb2phy1_host {
-+	phy-supply = <&vcc3v3_minipcie>;
-+	status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+	phy-supply = <&vcc3v3_ngff>;
-+	status = "okay";
-+};
diff --git a/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch b/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch
deleted file mode 100644
index e556e2eb42..0000000000
--- a/target/linux/rockchip/patches-6.1/025-v6.3-arm64-dts-rockchip-Update-eMMC-SD.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From c80992abd2877590059e9cb254213c16824e2106 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 18 Jan 2023 13:34:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SoM
- boards
-
-Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with
-onboarding eMMC flash, so the eMMC is the primary MMC device.
-
-On the other hand, Rockchip boot orders start from eMMC from an MMC
-device perspective.
-
-Mark, the eMMC has mmc0 to satisfy the above two conditions.
-
-Reported-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++--
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts     | 3 +--
- 2 files changed, 3 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-@@ -13,8 +13,8 @@
- 	compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
- 
- 	aliases {
--		mmc0 = &sdmmc;
--		mmc1 = &sdhci;
-+		mmc0 = &sdhci;
-+		mmc1 = &sdmmc;
- 	};
- 
- 	vcc3v3_pcie: vcc-pcie-regulator {
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -8,8 +8,7 @@
- 	compatible = "radxa,e25", "rockchip,rk3568";
- 
- 	aliases {
--		mmc0 = &sdmmc0;
--		mmc1 = &sdhci;
-+		mmc1 = &sdmmc0;
- 	};
- 
- 	pwm-leds {
diff --git a/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch b/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch
deleted file mode 100644
index c1f1a09219..0000000000
--- a/target/linux/rockchip/patches-6.1/026-v6.3-arm64-dts-rockchip-Add-missing-CM3i.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From c4d2b02d63ee38b381fbc886c02eecfec4f981cc Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:51 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add missing CM3i fallback compatible
- for Radxa E25
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In order to function the Radxa E25 Carrier board, it is mandatory to
-mount the Radxa CM3i module. 
-
-Add Radxa CM3i compatible as fallback compatible to string to satisfy
-the Module and Carrier board topology.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -5,7 +5,7 @@
- 
- / {
- 	model = "Radxa E25";
--	compatible = "radxa,e25", "rockchip,rk3568";
-+	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
- 
- 	aliases {
- 		mmc1 = &sdmmc0;
diff --git a/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch
deleted file mode 100644
index 84e87bae05..0000000000
--- a/target/linux/rockchip/patches-6.1/027-v6.3-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-E25.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From ef9134d9bbce071c9e4ebdcbb6f8fb1a5dd0a67e Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Correct the model name for Radxa E25
-
-Radxa E25 is a Carrier board, so update the model name for Radxa E25
-as suggested by the Radxa website.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -4,7 +4,7 @@
- #include "rk3568-radxa-cm3i.dtsi"
- 
- / {
--	model = "Radxa E25";
-+	model = "Radxa E25 Carrier Board";
- 	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
- 
- 	aliases {
diff --git a/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch
deleted file mode 100644
index da02c4c001..0000000000
--- a/target/linux/rockchip/patches-6.1/028-v6.6-arm64-dts-rockchip-Fix-PCIe-regulators-on-Radxa-E25.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From a87852e37f782257ebc57cc44a0d3fbf806471f6 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Fix PCIe regulators on Radxa E25
-
-Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with
-pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as
-seen on page 8 of the schematic [1].
-
-pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the
-vcc3v3_minipcie regulator is instead related to pcie30x1.
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Use correct regulator vcc3v3_minipcie for pcie30x1.
-
-[1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -47,6 +47,9 @@
- 		vin-supply = <&vcc5v0_sys>;
- 	};
- 
-+	/* actually fed by vcc5v0_sys, dependent
-+	 * on pi6c clock generator
-+	 */
- 	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -54,9 +57,9 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&minipcie_enable_h>;
- 		regulator-name = "vcc3v3_minipcie";
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&vcc5v0_sys>;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc3v3_pi6c_05>;
- 	};
- 
- 	vcc3v3_ngff: vcc3v3-ngff-regulator {
-@@ -71,9 +74,6 @@
- 		vin-supply = <&vcc5v0_sys>;
- 	};
- 
--	/* actually fed by vcc5v0_sys, dependent
--	 * on pi6c clock generator
--	 */
- 	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
- 		compatible = "regulator-fixed";
- 		enable-active-high;
-@@ -83,7 +83,7 @@
- 		regulator-name = "vcc3v3_pcie30x1";
- 		regulator-min-microvolt = <3300000>;
- 		regulator-max-microvolt = <3300000>;
--		vin-supply = <&vcc3v3_pi6c_05>;
-+		vin-supply = <&vcc5v0_sys>;
- 	};
- 
- 	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-@@ -117,7 +117,7 @@
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie30x1m0_pins>;
- 	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
--	vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+	vpcie3v3-supply = <&vcc3v3_minipcie>;
- 	status = "okay";
- };
- 
diff --git a/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch b/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch
deleted file mode 100644
index c0abdeb267..0000000000
--- a/target/linux/rockchip/patches-6.1/029-v6.6-arm64-dts-rockchip-Enable-SATA-on-Radxa-E25.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 2bdfe84fbd57a4ed9fd65a67210442559ce078f0 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Enable SATA on Radxa E25
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Enable sata1 node to fix use of SATA drives on the M.2 slot.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -99,6 +99,10 @@
- 	};
- };
- 
-+&combphy1 {
-+	phy-supply = <&vcc3v3_pcie30x1>;
-+};
-+
- &pcie2x1 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie20_reset_h>;
-@@ -178,6 +182,10 @@
- 	status = "okay";
- };
- 
-+&sata1 {
-+	status = "okay";
-+};
-+
- &sdmmc0 {
- 	bus-width = <4>;
- 	cap-sd-highspeed;
diff --git a/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch
index fb5015cf6e..fb5015cf6e 100644
--- a/target/linux/rockchip/patches-6.1/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch
+++ b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch
diff --git a/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch
new file mode 100644
index 0000000000..9be609f661
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch
@@ -0,0 +1,27 @@
+From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001
+From: Tim Lunn <tim@feathertop.org>
+Date: Wed, 14 Feb 2024 15:07:30 +1100
+Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
+
+Adjust compatible string to match the board vendor of Sinovoip
+
+Signed-off-by: Tim Lunn <tim@feathertop.org>
+Reviewed-by: Dragan Simic <dsimic@manjaro.org>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -13,7 +13,7 @@
+ 
+ / {
+ 	model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
+-	compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
++	compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
+ 
+ 	aliases {
+ 		ethernet0 = &gmac0;
diff --git a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch
index 683e5347f7..683e5347f7 100644
--- a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
+++ b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch
diff --git a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
index eeef0df014..eeef0df014 100644
--- a/target/linux/rockchip/patches-6.1/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
+++ b/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
diff --git a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch
index b3c941821a..b3c941821a 100644
--- a/target/linux/rockchip/patches-6.1/105-nanopi-r4s-sd-signalling.patch
+++ b/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch
diff --git a/target/linux/rockchip/patches-6.1/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch
index d7579d61e9..d7579d61e9 100644
--- a/target/linux/rockchip/patches-6.1/106-r4s-openwrt-leds.patch
+++ b/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch
diff --git a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
index 3aff37d096..3aff37d096 100644
--- a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
+++ b/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch
diff --git a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
index af8f8b16ba..af8f8b16ba 100644
--- a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
+++ b/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch
diff --git a/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch
index 1a80dadd48..1a80dadd48 100644
--- a/target/linux/rockchip/patches-6.1/109-nanopc-t4-add-led-aliases.patch
+++ b/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch
diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
index c22fdd52b8..c22fdd52b8 100644
--- a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
+++ b/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch
diff --git a/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch
index c8183a2b8a..c8183a2b8a 100644
--- a/target/linux/rockchip/patches-6.1/111-radxa-cm3-io-add-led-aliases.patch
+++ b/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch
diff --git a/target/linux/rockchip/patches-6.1/112-radxa-e25-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases.patch
index 75038c7f39..75038c7f39 100644
--- a/target/linux/rockchip/patches-6.1/112-radxa-e25-add-led-aliases.patch
+++ b/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases.patch
diff --git a/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch
new file mode 100644
index 0000000000..0be9a7300b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch
@@ -0,0 +1,340 @@
+From patchwork Sat Nov 12 14:10:58 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
+X-Patchwork-Id: 13041222
+Return-Path: 
+ <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
+X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
+	aws-us-west-2-korg-lkml-1.web.codeaurora.org
+From: Aurelien Jarno <aurelien@aurel32.net>
+To: Olivia Mackall <olivia@selenic.com>,
+	Herbert Xu <herbert@gondor.apana.org.au>,
+	Rob Herring <robh+dt@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Heiko Stuebner <heiko@sntech.de>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	Lin Jinhan <troy.lin@rock-chips.com>
+Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
+ CORE),
+	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
+ BINDINGS),
+	linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
+ support),
+	linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
+	linux-kernel@vger.kernel.org (open list),
+	Aurelien Jarno <aurelien@aurel32.net>
+Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver
+Date: Sat, 12 Nov 2022 15:10:58 +0100
+Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net>
+In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
+References: <20221112141059.3802506-1-aurelien@aurel32.net>
+MIME-Version: 1.0
+List-Id: <linux-arm-kernel.lists.infradead.org>
+
+Rockchip SoCs used to have a random number generator as part of their
+crypto device, and support for it has to be added to the corresponding
+driver. However newer Rockchip SoCs like the RK356x have an independent
+True Random Number Generator device. This patch adds a driver for it,
+greatly inspired from the downstream driver.
+
+The TRNG device does not seem to have a signal conditionner and the FIPS
+140-2 test returns a lot of failures. They can be reduced by increasing
+RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
+has been adjusted to get ~90% of successes and the quality value has
+been set accordingly.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+---
+ drivers/char/hw_random/Kconfig        |  14 ++
+ drivers/char/hw_random/Makefile       |   1 +
+ drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++
+ 3 files changed, 266 insertions(+)
+ create mode 100644 drivers/char/hw_random/rockchip-rng.c
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
+ 	  To compile this driver as a module, choose M here.
+ 	  The module will be called jh7110-trng.
+ 
++config HW_RANDOM_ROCKCHIP
++        tristate "Rockchip True Random Number Generator"
++        depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
++        depends on HAS_IOMEM
++        default HW_RANDOM
++        help
++          This driver provides kernel-side support for the True Random Number
++          Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
++
++          To compile this driver as a module, choose M here: the
++          module will be called rockchip-rng.
++
++          If unsure, say Y.
++
+ endif # HW_RANDOM
+ 
+ config UML_RANDOM
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
+ obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
+ obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
+ obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
+--- /dev/null
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,251 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022, Aurelien Jarno
++ * Authors:
++ *  Lin Jinhan <troy.lin@rock-chips.com>
++ *  Aurelien Jarno <aurelien@aurel32.net>
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#define RK_RNG_AUTOSUSPEND_DELAY	100
++#define RK_RNG_MAX_BYTE			32
++#define RK_RNG_POLL_PERIOD_US		100
++#define RK_RNG_POLL_TIMEOUT_US		10000
++
++/*
++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
++ * a tradeoff between speed and quality and has been adjusted to get a quality
++ * of ~900 (~90% of FIPS 140-2 successes).
++ */
++#define RK_RNG_SAMPLE_CNT		1000
++
++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
++#define TRNG_RST_CTL			0x0004
++#define TRNG_RNG_CTL			0x0400
++#define TRNG_RNG_CTL_LEN_64_BIT		(0x00 << 4)
++#define TRNG_RNG_CTL_LEN_128_BIT	(0x01 << 4)
++#define TRNG_RNG_CTL_LEN_192_BIT	(0x02 << 4)
++#define TRNG_RNG_CTL_LEN_256_BIT	(0x03 << 4)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_0	(0x00 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_1	(0x01 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_2	(0x02 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_3	(0x03 << 2)
++#define TRNG_RNG_CTL_ENABLE		BIT(1)
++#define TRNG_RNG_CTL_START		BIT(0)
++#define TRNG_RNG_SAMPLE_CNT		0x0404
++#define TRNG_RNG_DOUT_0			0x0410
++#define TRNG_RNG_DOUT_1			0x0414
++#define TRNG_RNG_DOUT_2			0x0418
++#define TRNG_RNG_DOUT_3			0x041c
++#define TRNG_RNG_DOUT_4			0x0420
++#define TRNG_RNG_DOUT_5			0x0424
++#define TRNG_RNG_DOUT_6			0x0428
++#define TRNG_RNG_DOUT_7			0x042c
++
++struct rk_rng {
++	struct hwrng rng;
++	void __iomem *base;
++	struct reset_control *rst;
++	int clk_num;
++	struct clk_bulk_data *clk_bulks;
++};
++
++/* The mask determine the bits that are updated */
++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
++{
++	writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++	int ret;
++
++	/* start clocks */
++	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++	if (ret < 0) {
++		dev_err((struct device *) rk_rng->rng.priv,
++			"Failed to enable clks %d\n", ret);
++		return ret;
++	}
++
++	/* set the sample period */
++	writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
++
++	/* set osc ring speed and enable it */
++	reg = TRNG_RNG_CTL_LEN_256_BIT |
++		   TRNG_RNG_CTL_OSC_RING_SPEED_0 |
++		   TRNG_RNG_CTL_ENABLE;
++	rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++	return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++
++	/* stop TRNG */
++	reg = 0;
++	rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++	/* stop clocks */
++	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++	int ret = 0;
++	int i;
++
++	pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
++
++	/* Start collecting random data */
++	reg = TRNG_RNG_CTL_START;
++	rk_rng_write_ctl(rk_rng, reg, reg);
++
++	ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
++				 !(reg & TRNG_RNG_CTL_START),
++				 RK_RNG_POLL_PERIOD_US,
++				 RK_RNG_POLL_TIMEOUT_US);
++	if (ret < 0)
++		goto out;
++
++	/* Read random data stored in big endian in the registers */
++	ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
++	for (i = 0; i < ret; i += 4) {
++		reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
++		*(u32 *)(buf + i) = be32_to_cpu(reg);
++	}
++
++out:
++	pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
++	pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
++
++	return ret;
++}
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rk_rng *rk_rng;
++	int ret;
++
++	rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
++	if (!rk_rng)
++		return -ENOMEM;
++
++	rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(rk_rng->base))
++		return PTR_ERR(rk_rng->base);
++
++	rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
++	if (rk_rng->clk_num < 0)
++		return dev_err_probe(dev, rk_rng->clk_num,
++				     "Failed to get clks property\n");
++
++	rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
++	if (IS_ERR(rk_rng->rst))
++		return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
++				     "Failed to get reset property\n");
++
++	reset_control_assert(rk_rng->rst);
++	udelay(2);
++	reset_control_deassert(rk_rng->rst);
++
++	platform_set_drvdata(pdev, rk_rng);
++
++	rk_rng->rng.name = dev_driver_string(dev);
++#ifndef CONFIG_PM
++	rk_rng->rng.init = rk_rng_init;
++	rk_rng->rng.cleanup = rk_rng_cleanup;
++#endif
++	rk_rng->rng.read = rk_rng_read;
++	rk_rng->rng.priv = (unsigned long) dev;
++	rk_rng->rng.quality = 900;
++
++	pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
++	pm_runtime_use_autosuspend(dev);
++	pm_runtime_enable(dev);
++
++	ret = devm_hwrng_register(dev, &rk_rng->rng);
++	if (ret)
++		return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
++
++	dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
++
++	return 0;
++}
++
++static int rk_rng_remove(struct platform_device *pdev)
++{
++	pm_runtime_disable(&pdev->dev);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int rk_rng_runtime_suspend(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	rk_rng_cleanup(&rk_rng->rng);
++
++	return 0;
++}
++
++static int rk_rng_runtime_resume(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	return rk_rng_init(&rk_rng->rng);
++}
++#endif
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++				rk_rng_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++	{
++		.compatible = "rockchip,rk3568-rng",
++	},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static struct platform_driver rk_rng_driver = {
++	.driver	= {
++		.name	= "rockchip-rng",
++		.pm	= &rk_rng_pm_ops,
++		.of_match_table = rk_rng_dt_match,
++	},
++	.probe	= rk_rng_probe,
++	.remove = rk_rng_remove,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
++MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch
new file mode 100644
index 0000000000..577aa6c9d2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch
@@ -0,0 +1,56 @@
+From patchwork Sat Nov 12 14:10:59 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
+X-Patchwork-Id: 13041221
+From: Aurelien Jarno <aurelien@aurel32.net>
+To: Olivia Mackall <olivia@selenic.com>,
+	Herbert Xu <herbert@gondor.apana.org.au>,
+	Rob Herring <robh+dt@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Heiko Stuebner <heiko@sntech.de>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	Lin Jinhan <troy.lin@rock-chips.com>
+Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
+ CORE),
+	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
+ BINDINGS),
+	linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
+ support),
+	linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
+	linux-kernel@vger.kernel.org (open list),
+	Aurelien Jarno <aurelien@aurel32.net>
+Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x
+Date: Sat, 12 Nov 2022 15:10:59 +0100
+Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net>
+In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
+References: <20221112141059.3802506-1-aurelien@aurel32.net>
+MIME-Version: 1.0
+List-Id: <linux-arm-kernel.lists.infradead.org>
+
+Enable the just added Rockchip RNG driver for RK356x SoCs.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1807,6 +1807,15 @@
+ 		};
+ 	};
+ 
++	rng: rng@fe388000 {
++		compatible = "rockchip,rk3568-rng";
++		reg = <0x0 0xfe388000 0x0 0x4000>;
++		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++		clock-names = "trng_clk", "trng_hclk";
++		resets = <&cru SRST_TRNG_NS>;
++		reset-names = "reset";
++	};
++
+ 	pinctrl: pinctrl {
+ 		compatible = "rockchip,rk3568-pinctrl";
+ 		rockchip,grf = <&grf>;
diff --git a/target/linux/sifiveu/Makefile b/target/linux/sifiveu/Makefile
index 3a003a35fc..2e2ea96b4b 100644
--- a/target/linux/sifiveu/Makefile
+++ b/target/linux/sifiveu/Makefile
@@ -11,8 +11,7 @@ FEATURES:=ext4
 KERNELNAME:=Image dtbs
 SUBTARGETS:=generic
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/sifiveu/config-6.1 b/target/linux/sifiveu/config-6.1
deleted file mode 100644
index 98283f4e0d..0000000000
--- a/target/linux/sifiveu/config-6.1
+++ /dev/null
@@ -1,392 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ATA=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CAVIUM_PTP=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
-CONFIG_CLK_SIFIVE=y
-CONFIG_CLK_SIFIVE_PRCI=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMODEL_MEDANY=y
-# CONFIG_CMODEL_MEDLOW is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_LEGACY_SYSFS=y
-CONFIG_EDAC_SIFIVE=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_ELF_CORE=y
-CONFIG_ERRATA_SIFIVE=y
-CONFIG_ERRATA_SIFIVE_CIP_1200=y
-CONFIG_ERRATA_SIFIVE_CIP_453=y
-# CONFIG_ERRATA_THEAD is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FAT_FS=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_INJECTION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_SIFIVE=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OCORES=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYS=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICROSEMI_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SPI=y
-CONFIG_MMIOWB=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MODULE_SECTIONS=y
-CONFIG_MPILIB=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NONPORTABLE is not set
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DMA_DEFAULT_COHERENT=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xff60000000000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEAER_INJECT=m
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIE_FU740=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_SW_SWITCHTEC=y
-CONFIG_PGTABLE_LEVELS=5
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PORTABLE=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SIFIVE=y
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_GZIP=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RISCV=y
-CONFIG_RISCV_ALTERNATIVE=y
-# CONFIG_RISCV_BOOT_SPINWAIT is not set
-CONFIG_RISCV_DMA_NONCOHERENT=y
-CONFIG_RISCV_INTC=y
-CONFIG_RISCV_ISA_C=y
-CONFIG_RISCV_ISA_SVPBMT=y
-CONFIG_RISCV_ISA_ZICBOM=y
-CONFIG_RISCV_SBI=y
-CONFIG_RISCV_SBI_V01=y
-CONFIG_RISCV_TIMER=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_EFI is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_SERIAL_SIFIVE_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SIFIVE_CCACHE=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
-CONFIG_SOC_SIFIVE=y
-# CONFIG_SOC_STARFIVE is not set
-# CONFIG_SOC_VIRT is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SIFIVE=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOOLCHAIN_HAS_ZICBOM=y
-CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
-CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TUNE_GENERIC=y
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VFAT_FS=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
deleted file mode 100644
index 9a1c968139..0000000000
--- a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Wed, 17 Feb 2021 06:06:14 -0800
-Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
- sifive,u74-mc
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-@@ -39,7 +39,7 @@
- 			};
- 		};
- 		cpu1: cpu@1 {
--			compatible = "sifive,bullet0", "riscv";
-+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- 			d-cache-block-size = <64>;
- 			d-cache-sets = <64>;
- 			d-cache-size = <32768>;
-@@ -63,7 +63,7 @@
- 			};
- 		};
- 		cpu2: cpu@2 {
--			compatible = "sifive,bullet0", "riscv";
-+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- 			d-cache-block-size = <64>;
- 			d-cache-sets = <64>;
- 			d-cache-size = <32768>;
-@@ -87,7 +87,7 @@
- 			};
- 		};
- 		cpu3: cpu@3 {
--			compatible = "sifive,bullet0", "riscv";
-+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- 			d-cache-block-size = <64>;
- 			d-cache-sets = <64>;
- 			d-cache-size = <32768>;
-@@ -111,7 +111,7 @@
- 			};
- 		};
- 		cpu4: cpu@4 {
--			compatible = "sifive,bullet0", "riscv";
-+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- 			d-cache-block-size = <64>;
- 			d-cache-sets = <64>;
- 			d-cache-size = <32768>;
diff --git a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch
deleted file mode 100644
index 07170d7c76..0000000000
--- a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Mon, 13 Sep 2021 02:18:30 -0700
-Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
-
-Add gpio-poweroff node to allow powering off the system.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-@@ -86,6 +86,11 @@
- 			};
- 		};
- 	};
-+
-+	gpio-poweroff {
-+		compatible = "gpio-poweroff";
-+		gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
-+	};
- };
- 
- &uart0 {
diff --git a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
deleted file mode 100644
index c4242c6f07..0000000000
--- a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 14 May 2021 05:27:51 -0700
-Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
-
-Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/Kconfig                                 |  8 +++++
- arch/riscv/boot/dts/sifive/fu540-c000.dtsi         |  5 ++++
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
- 3 files changed, 47 insertions(+)
-
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -711,6 +711,14 @@ config PORTABLE
- 	select OF
- 	select MMU
- 
-+menu "CPU Power Management"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+source "drivers/cpufreq/Kconfig"
-+
-+endmenu
-+
- menu "Power management options"
- 
- source "kernel/power/Kconfig"
---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-@@ -30,6 +30,7 @@
- 			i-cache-size = <16384>;
- 			reg = <0>;
- 			riscv,isa = "rv64imac";
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			status = "disabled";
- 			cpu0_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -54,6 +55,7 @@
- 			reg = <1>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu1_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -78,6 +80,7 @@
- 			reg = <2>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu2_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -102,6 +105,7 @@
- 			reg = <3>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu3_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
-@@ -126,6 +130,7 @@
- 			reg = <4>;
- 			riscv,isa = "rv64imafdc";
- 			tlb-split;
-+			clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- 			next-level-cache = <&l2cache>;
- 			cpu4_intc: interrupt-controller {
- 				#interrupt-cells = <1>;
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -80,6 +80,40 @@
- 			label = "d4";
- 		};
- 	};
-+
-+	fu540_c000_opp_table: opp-table {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp-350000000 {
-+			opp-hz = /bits/ 64 <350000000>;
-+		};
-+		opp-700000000 {
-+			opp-hz = /bits/ 64 <700000000>;
-+		};
-+		opp-999999999 {
-+			opp-hz = /bits/ 64 <999999999>;
-+		};
-+		opp-1400000000 {
-+			opp-hz = /bits/ 64 <1400000000>;
-+		};
-+	};
-+};
-+
-+&cpu0 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu1 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu2 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu3 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu4 {
-+	operating-points-v2 = <&fu540_c000_opp_table>;
- };
- 
- &uart0 {
diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile
index 511c02772e..d91e5c5a3e 100644
--- a/target/linux/sunxi/Makefile
+++ b/target/linux/sunxi/Makefile
@@ -10,7 +10,7 @@ BOARDNAME:=Allwinner ARM SoCs
 FEATURES:=usb ext4 display rootfs-part rtc squashfs
 SUBTARGETS:=cortexa8 cortexa7 cortexa53
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 KERNELNAME:=zImage dtbs
 
diff --git a/target/linux/sunxi/config-6.1 b/target/linux/sunxi/config-6.1
deleted file mode 100644
index a76834c13a..0000000000
--- a/target/linux/sunxi/config-6.1
+++ /dev/null
@@ -1,524 +0,0 @@
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=416
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUNXI_MC_SMP=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CCI=y
-CONFIG_ARM_CCI400_COMMON=y
-CONFIG_ARM_CCI400_PORT_CTRL=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AXP20X_POWER=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CAN=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
-# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
-# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
-# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SUN4I=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DVB_CORE=y
-CONFIG_DWMAC_GENERIC=y
-# CONFIG_DWMAC_SUN8I is not set
-CONFIG_DWMAC_SUNXI=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_LITTLE_ENDIAN=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_SUN6I_P2WI=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_AXP20X_PEK=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KSM=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_SUN4I=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_AXP20X_I2C=y
-CONFIG_MFD_AXP20X_RSB=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SUNXI_SID=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_SUN4I_USB=y
-# CONFIG_PHY_SUN50I_USB3 is not set
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-CONFIG_PHY_SUN9I_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AXP209=y
-# CONFIG_PINCTRL_SUN20I_D1 is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-# CONFIG_PINCTRL_SUN50I_A100 is not set
-# CONFIG_PINCTRL_SUN50I_A100_R is not set
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H616 is not set
-# CONFIG_PINCTRL_SUN50I_H616_R is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-CONFIG_PINCTRL_SUN5I=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN8I_A33=y
-CONFIG_PINCTRL_SUN8I_A83T=y
-CONFIG_PINCTRL_SUN8I_A83T_R=y
-CONFIG_PINCTRL_SUN8I_H3=y
-CONFIG_PINCTRL_SUN8I_H3_R=y
-CONFIG_PINCTRL_SUN8I_V3S=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUN9I_A80_R=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SUN4I=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_SY8106A=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SDIO_UART=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SND=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN4I_SPDIF is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SUN4I=y
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SUN4I_A10_CCU=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_CCU=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUN6I_A31_CCU=y
-# CONFIG_SUN6I_RTC_CCU is not set
-CONFIG_SUN8I_A23_CCU=y
-CONFIG_SUN8I_A33_CCU=y
-CONFIG_SUN8I_A83T_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_R40_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_SUN8I_THERMAL=y
-CONFIG_SUN8I_V3S_CCU=y
-CONFIG_SUN9I_A80_CCU=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUNXI_MBUS=y
-CONFIG_SUNXI_RSB=y
-CONFIG_SUNXI_SRAM=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USERIO=y
-CONFIG_USE_OF=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VHOST=y
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_NET=y
-# CONFIG_VIDEO_SUN4I_CSI is not set
-# CONFIG_VIDEO_SUN6I_CSI is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
diff --git a/target/linux/sunxi/config-6.6 b/target/linux/sunxi/config-6.6
new file mode 100644
index 0000000000..3e73f44c90
--- /dev/null
+++ b/target/linux/sunxi/config-6.6
@@ -0,0 +1,526 @@
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=416
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_MC_SMP=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PORT_CTRL=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_AXP20X_POWER=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CAN=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_SUN4I_SS=y
+# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
+CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
+# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
+# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SUN4I=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DVB_CORE=y
+CONFIG_DWMAC_GENERIC=y
+# CONFIG_DWMAC_SUN8I is not set
+CONFIG_DWMAC_SUNXI=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ELF_CORE=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_LITTLE_ENDIAN=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_SUN6I_P2WI=y
+CONFIG_IIO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_KSM=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_MACH_SUN4I=y
+CONFIG_MACH_SUN5I=y
+CONFIG_MACH_SUN6I=y
+CONFIG_MACH_SUN7I=y
+CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN9I=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_SUN4I=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PCS_XPCS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+# CONFIG_PHY_SUN50I_USB3 is not set
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+CONFIG_PHY_SUN9I_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AXP209=y
+# CONFIG_PINCTRL_SUN20I_D1 is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+CONFIG_PINCTRL_SUN5I=y
+CONFIG_PINCTRL_SUN6I_A31=y
+CONFIG_PINCTRL_SUN6I_A31_R=y
+CONFIG_PINCTRL_SUN8I_A23=y
+CONFIG_PINCTRL_SUN8I_A23_R=y
+CONFIG_PINCTRL_SUN8I_A33=y
+CONFIG_PINCTRL_SUN8I_A83T=y
+CONFIG_PINCTRL_SUN8I_A83T_R=y
+CONFIG_PINCTRL_SUN8I_H3=y
+CONFIG_PINCTRL_SUN8I_H3_R=y
+CONFIG_PINCTRL_SUN8I_V3S=y
+CONFIG_PINCTRL_SUN9I_A80=y
+CONFIG_PINCTRL_SUN9I_A80_R=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SUN4I=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_SY8106A=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SDIO_UART=y
+CONFIG_SECURITYFS=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SND=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN4I_SPDIF is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+# CONFIG_SND_SUN8I_CODEC is not set
+# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_SUN20I_GPADC is not set
+# CONFIG_SUN20I_PPU is not set
+CONFIG_SUN4I_A10_CCU=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN5I_CCU=y
+CONFIG_SUN5I_HSTIMER=y
+CONFIG_SUN6I_A31_CCU=y
+# CONFIG_SUN6I_RTC_CCU is not set
+CONFIG_SUN8I_A23_CCU=y
+CONFIG_SUN8I_A33_CCU=y
+CONFIG_SUN8I_A83T_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_SUN8I_H3_CCU=y
+CONFIG_SUN8I_R40_CCU=y
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUN8I_V3S_CCU=y
+CONFIG_SUN9I_A80_CCU=y
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_MBUS=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TOUCHSCREEN_SUN4I=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USERIO=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VHOST=y
+CONFIG_VHOST_IOTLB=y
+CONFIG_VHOST_NET=y
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
diff --git a/target/linux/sunxi/cortexa53/config-6.1 b/target/linux/sunxi/cortexa53/config-6.6
index 55bcd4e8e5..55bcd4e8e5 100644
--- a/target/linux/sunxi/cortexa53/config-6.1
+++ b/target/linux/sunxi/cortexa53/config-6.6
diff --git a/target/linux/sunxi/cortexa7/config-6.1 b/target/linux/sunxi/cortexa7/config-6.1
deleted file mode 100644
index eaa6b037be..0000000000
--- a/target/linux/sunxi/cortexa7/config-6.1
+++ /dev/null
@@ -1,26 +0,0 @@
-CONFIG_B53=y
-CONFIG_B53_MDIO_DRIVER=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-# CONFIG_MACH_SUN4I is not set
-# CONFIG_MACH_SUN5I is not set
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MICREL_PHY=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_PHY=y
diff --git a/target/linux/sunxi/cortexa7/config-6.6 b/target/linux/sunxi/cortexa7/config-6.6
new file mode 100644
index 0000000000..105c090890
--- /dev/null
+++ b/target/linux/sunxi/cortexa7/config-6.6
@@ -0,0 +1,28 @@
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+# CONFIG_MACH_SUN4I is not set
+# CONFIG_MACH_SUN5I is not set
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_PHY=y
diff --git a/target/linux/sunxi/cortexa8/config-6.1 b/target/linux/sunxi/cortexa8/config-6.6
index b893b3142e..b893b3142e 100644
--- a/target/linux/sunxi/cortexa8/config-6.1
+++ b/target/linux/sunxi/cortexa8/config-6.6
diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile
index cc1c1ba42d..ee36df598a 100644
--- a/target/linux/sunxi/image/Makefile
+++ b/target/linux/sunxi/image/Makefile
@@ -34,7 +34,7 @@ define Device/Default
   KERNEL := kernel-bin | uImage none
   IMAGES := sdcard.img.gz
   IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip
-  SUNXI_DTS_DIR :=
+  SUNXI_DTS_DIR :=allwinner/
   SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1)))
 endef
 
diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk
index a85b20531d..e2d83fa94f 100644
--- a/target/linux/sunxi/image/cortexa7.mk
+++ b/target/linux/sunxi/image/cortexa7.mk
@@ -112,6 +112,14 @@ define Device/lemaker_bananapro
 endef
 TARGET_DEVICES += lemaker_bananapro
 
+define Device/licheepi_licheepi-zero-dock
+  DEVICE_VENDOR := LicheePi
+  DEVICE_MODEL := Zero with Dock (V3s)
+  DEVICE_PACKAGES:=kmod-rtc-sunxi
+  SOC := sun8i-v3s
+endef
+TARGET_DEVICES += licheepi_licheepi-zero-dock
+
 define Device/linksprite_pcduino3
   DEVICE_VENDOR := LinkSprite
   DEVICE_MODEL := pcDuino3
diff --git a/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch
deleted file mode 100644
index c24d479534..0000000000
--- a/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 28a1a6474c5053bae01bd29946b4d5ede539176b Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:52 +0000
-Subject: [PATCH] dt-bindings: usb: Add H616 compatible string
-
-The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
-controllers, so just add their compatible strings to the list of
-generic OHCI/EHCI controllers.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20221031111358.3387297-2-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
-+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
-@@ -30,6 +30,7 @@ properties:
-               - allwinner,sun4i-a10-ehci
-               - allwinner,sun50i-a64-ehci
-               - allwinner,sun50i-h6-ehci
-+              - allwinner,sun50i-h616-ehci
-               - allwinner,sun5i-a13-ehci
-               - allwinner,sun6i-a31-ehci
-               - allwinner,sun7i-a20-ehci
---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
-+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
-@@ -20,6 +20,7 @@ properties:
-               - allwinner,sun4i-a10-ohci
-               - allwinner,sun50i-a64-ohci
-               - allwinner,sun50i-h6-ohci
-+              - allwinner,sun50i-h616-ohci
-               - allwinner,sun5i-a13-ohci
-               - allwinner,sun6i-a31-ohci
-               - allwinner,sun7i-a20-ohci
diff --git a/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch b/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
deleted file mode 100644
index 5739172ceb..0000000000
--- a/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:53 +0000
-Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY
-
-The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
-some resources from port 2's PHY and HCI IP. In particular the PMU clock
-for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
-register of port 2. To allow each USB port to be controlled
-independently of port 2, we need a handle to that particular PMU clock
-in the *PHY* node, as the HCI and PHY part might be handled by separate
-drivers.
-
-Add that clock to the requirements of the H616 PHY binding, so that a
-PHY driver can apply the quirk in isolation, without requiring help from
-port 2's HCI driver.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- .../phy/allwinner,sun8i-h3-usb-phy.yaml       | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-@@ -36,18 +36,22 @@ properties:
-       - const: pmu3
- 
-   clocks:
-+    minItems: 4
-     items:
-       - description: USB OTG PHY bus clock
-       - description: USB Host 0 PHY bus clock
-       - description: USB Host 1 PHY bus clock
-       - description: USB Host 2 PHY bus clock
-+      - description: PMU clock for host port 2
- 
-   clock-names:
-+    minItems: 4
-     items:
-       - const: usb0_phy
-       - const: usb1_phy
-       - const: usb2_phy
-       - const: usb3_phy
-+      - const: pmu2_clk
- 
-   resets:
-     items:
-@@ -96,6 +100,28 @@ required:
-   - resets
-   - reset-names
- 
-+allOf:
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            enum:
-+              - allwinner,sun50i-h616-usb-phy
-+    then:
-+      properties:
-+        clocks:
-+          minItems: 5
-+
-+        clock-names:
-+          minItems: 5
-+    else:
-+      properties:
-+        clocks:
-+          maxItems: 4
-+
-+        clock-names:
-+          maxItems: 4
-+
- additionalProperties: false
- 
- examples:
diff --git a/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch
deleted file mode 100644
index 6dc1cf2f36..0000000000
--- a/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch
+++ /dev/null
@@ -1,188 +0,0 @@
-From f40cf244c3feb4e1a442f8029b691add2c65b3ab Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:56 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: Add USB nodes
-
-Add the nodes for the MUSB and the four USB host controllers to the SoC
-.dtsi, along with the PHY node needed to bind all of them together.
-
-EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
-some quirks (handled in the driver).
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20221031111358.3387297-6-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -504,6 +504,166 @@
- 			};
- 		};
- 
-+		usbotg: usb@5100000 {
-+			compatible = "allwinner,sun50i-h616-musb",
-+				     "allwinner,sun8i-h3-musb";
-+			reg = <0x05100000 0x0400>;
-+			clocks = <&ccu CLK_BUS_OTG>;
-+			resets = <&ccu RST_BUS_OTG>;
-+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "mc";
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			extcon = <&usbphy 0>;
-+			status = "disabled";
-+		};
-+
-+		usbphy: phy@5100400 {
-+			compatible = "allwinner,sun50i-h616-usb-phy";
-+			reg = <0x05100400 0x24>,
-+			      <0x05101800 0x14>,
-+			      <0x05200800 0x14>,
-+			      <0x05310800 0x14>,
-+			      <0x05311800 0x14>;
-+			reg-names = "phy_ctrl",
-+				    "pmu0",
-+				    "pmu1",
-+				    "pmu2",
-+				    "pmu3";
-+			clocks = <&ccu CLK_USB_PHY0>,
-+				 <&ccu CLK_USB_PHY1>,
-+				 <&ccu CLK_USB_PHY2>,
-+				 <&ccu CLK_USB_PHY3>,
-+				 <&ccu CLK_BUS_EHCI2>;
-+			clock-names = "usb0_phy",
-+				      "usb1_phy",
-+				      "usb2_phy",
-+				      "usb3_phy",
-+				      "pmu2_clk";
-+			resets = <&ccu RST_USB_PHY0>,
-+				 <&ccu RST_USB_PHY1>,
-+				 <&ccu RST_USB_PHY2>,
-+				 <&ccu RST_USB_PHY3>;
-+			reset-names = "usb0_reset",
-+				      "usb1_reset",
-+				      "usb2_reset",
-+				      "usb3_reset";
-+			status = "disabled";
-+			#phy-cells = <1>;
-+		};
-+
-+		ehci0: usb@5101000 {
-+			compatible = "allwinner,sun50i-h616-ehci",
-+				     "generic-ehci";
-+			reg = <0x05101000 0x100>;
-+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI0>,
-+				 <&ccu CLK_BUS_EHCI0>,
-+				 <&ccu CLK_USB_OHCI0>;
-+			resets = <&ccu RST_BUS_OHCI0>,
-+				 <&ccu RST_BUS_EHCI0>;
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci0: usb@5101400 {
-+			compatible = "allwinner,sun50i-h616-ohci",
-+				     "generic-ohci";
-+			reg = <0x05101400 0x100>;
-+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI0>,
-+				 <&ccu CLK_USB_OHCI0>;
-+			resets = <&ccu RST_BUS_OHCI0>;
-+			phys = <&usbphy 0>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ehci1: usb@5200000 {
-+			compatible = "allwinner,sun50i-h616-ehci",
-+				     "generic-ehci";
-+			reg = <0x05200000 0x100>;
-+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI1>,
-+				 <&ccu CLK_BUS_EHCI1>,
-+				 <&ccu CLK_USB_OHCI1>;
-+			resets = <&ccu RST_BUS_OHCI1>,
-+				 <&ccu RST_BUS_EHCI1>;
-+			phys = <&usbphy 1>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci1: usb@5200400 {
-+			compatible = "allwinner,sun50i-h616-ohci",
-+				     "generic-ohci";
-+			reg = <0x05200400 0x100>;
-+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI1>,
-+				 <&ccu CLK_USB_OHCI1>;
-+			resets = <&ccu RST_BUS_OHCI1>;
-+			phys = <&usbphy 1>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ehci2: usb@5310000 {
-+			compatible = "allwinner,sun50i-h616-ehci",
-+				     "generic-ehci";
-+			reg = <0x05310000 0x100>;
-+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI2>,
-+				 <&ccu CLK_BUS_EHCI2>,
-+				 <&ccu CLK_USB_OHCI2>;
-+			resets = <&ccu RST_BUS_OHCI2>,
-+				 <&ccu RST_BUS_EHCI2>;
-+			phys = <&usbphy 2>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci2: usb@5310400 {
-+			compatible = "allwinner,sun50i-h616-ohci",
-+				     "generic-ohci";
-+			reg = <0x05310400 0x100>;
-+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI2>,
-+				 <&ccu CLK_USB_OHCI2>;
-+			resets = <&ccu RST_BUS_OHCI2>;
-+			phys = <&usbphy 2>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ehci3: usb@5311000 {
-+			compatible = "allwinner,sun50i-h616-ehci",
-+				     "generic-ehci";
-+			reg = <0x05311000 0x100>;
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI3>,
-+				 <&ccu CLK_BUS_EHCI3>,
-+				 <&ccu CLK_USB_OHCI3>;
-+			resets = <&ccu RST_BUS_OHCI3>,
-+				 <&ccu RST_BUS_EHCI3>;
-+			phys = <&usbphy 3>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
-+		ohci3: usb@5311400 {
-+			compatible = "allwinner,sun50i-h616-ohci",
-+				     "generic-ohci";
-+			reg = <0x05311400 0x100>;
-+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_OHCI3>,
-+				 <&ccu CLK_USB_OHCI3>;
-+			resets = <&ccu RST_BUS_OHCI3>;
-+			phys = <&usbphy 3>;
-+			phy-names = "usb";
-+			status = "disabled";
-+		};
-+
- 		rtc: rtc@7000000 {
- 			compatible = "allwinner,sun50i-h616-rtc";
- 			reg = <0x07000000 0x400>;
diff --git a/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch
deleted file mode 100644
index a544e482f3..0000000000
--- a/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From db5f028309ede13767e2ba356c1975ac37a4fd6c Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:57 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
-
-The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
-a GPIO controlled regulator.
-The USB-C port is meant to power the board, but is also connected to
-the USB 0 port, which we configure as an MUSB peripheral.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20221031111358.3387297-7-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../allwinner/sun50i-h616-orangepi-zero2.dts  | 41 +++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -49,8 +49,24 @@
- 		regulator-max-microvolt = <5000000>;
- 		regulator-always-on;
- 	};
-+
-+	reg_usb1_vbus: regulator-usb1-vbus {
-+		compatible = "regulator-fixed";
-+		regulator-name = "usb1-vbus";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&reg_vcc5v>;
-+		enable-active-high;
-+		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
-+	};
-+};
-+
-+&ehci1 {
-+	status = "okay";
- };
- 
-+/* USB 2 & 3 are on headers only. */
-+
- &emac0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&ext_rgmii_pins>;
-@@ -76,6 +92,10 @@
- 	status = "okay";
- };
- 
-+&ohci1 {
-+	status = "okay";
-+};
-+
- &r_rsb {
- 	status = "okay";
- 
-@@ -211,3 +231,24 @@
- 	pinctrl-0 = <&uart0_ph_pins>;
- 	status = "okay";
- };
-+
-+&usbotg {
-+	/*
-+	 * PHY0 pins are connected to a USB-C socket, but a role switch
-+	 * is not implemented: both CC pins are pulled to GND.
-+	 * The VBUS pins power the device, so a fixed peripheral mode
-+	 * is the best choice.
-+	 * The board can be powered via GPIOs, in this case port0 *can*
-+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
-+	 * then provided by the GPIOs. Any user of this setup would
-+	 * need to adjust the DT accordingly: dr_mode set to "host",
-+	 * enabling OHCI0 and EHCI0.
-+	 */
-+	dr_mode = "peripheral";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb1_vbus-supply = <&reg_usb1_vbus>;
-+	status = "okay";
-+};
diff --git a/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch b/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch
deleted file mode 100644
index 0747e6a8e0..0000000000
--- a/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch
+++ /dev/null
@@ -1,305 +0,0 @@
-From 322bf103204b8f786547acbeed85569254e7088f Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Fri, 4 Aug 2023 18:08:54 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT
-
-The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some
-DT nodes with the Zero 2, but comes with a different PMIC.
-
-Move the common parts (except the PMIC) into a new shared file, and
-include that from the existing board .dts file.
-
-No functional change, the generated DTB is the same, except for some
-phandle numbering differences.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230804170856.1237202-2-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../allwinner/sun50i-h616-orangepi-zero.dtsi  | 134 ++++++++++++++++++
- .../allwinner/sun50i-h616-orangepi-zero2.dts  | 119 +---------------
- 2 files changed, 135 insertions(+), 118 deletions(-)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-@@ -0,0 +1,134 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+/*
-+ * Copyright (C) 2020 Arm Ltd.
-+ *
-+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
-+ * Excludes PMIC nodes and properties, since they are different between the two.
-+ */
-+
-+#include "sun50i-h616.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+	aliases {
-+		ethernet0 = &emac0;
-+		serial0 = &uart0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-0 {
-+			function = LED_FUNCTION_POWER;
-+			color = <LED_COLOR_ID_RED>;
-+			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
-+			default-state = "on";
-+		};
-+
-+		led-1 {
-+			function = LED_FUNCTION_STATUS;
-+			color = <LED_COLOR_ID_GREEN>;
-+			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
-+		};
-+	};
-+
-+	reg_vcc5v: vcc5v {
-+		/* board wide 5V supply directly from the USB-C socket */
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc-5v";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-always-on;
-+	};
-+
-+	reg_usb1_vbus: regulator-usb1-vbus {
-+		compatible = "regulator-fixed";
-+		regulator-name = "usb1-vbus";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&reg_vcc5v>;
-+		enable-active-high;
-+		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
-+	};
-+};
-+
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+/* USB 2 & 3 are on headers only. */
-+
-+&emac0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&ext_rgmii_pins>;
-+	phy-mode = "rgmii";
-+	phy-handle = <&ext_rgmii_phy>;
-+	allwinner,rx-delay-ps = <3100>;
-+	allwinner,tx-delay-ps = <700>;
-+	status = "okay";
-+};
-+
-+&mdio0 {
-+	ext_rgmii_phy: ethernet-phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <1>;
-+	};
-+};
-+
-+&mmc0 {
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
-+	bus-width = <4>;
-+	status = "okay";
-+};
-+
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&spi0  {
-+	status = "okay";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
-+
-+	flash@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <40000000>;
-+	};
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_ph_pins>;
-+	status = "okay";
-+};
-+
-+&usbotg {
-+	/*
-+	 * PHY0 pins are connected to a USB-C socket, but a role switch
-+	 * is not implemented: both CC pins are pulled to GND.
-+	 * The VBUS pins power the device, so a fixed peripheral mode
-+	 * is the best choice.
-+	 * The board can be powered via GPIOs, in this case port0 *can*
-+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
-+	 * then provided by the GPIOs. Any user of this setup would
-+	 * need to adjust the DT accordingly: dr_mode set to "host",
-+	 * enabling OHCI0 and EHCI0.
-+	 */
-+	dr_mode = "peripheral";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb1_vbus-supply = <&reg_usb1_vbus>;
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -5,95 +5,19 @@
- 
- /dts-v1/;
- 
--#include "sun50i-h616.dtsi"
--
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/interrupt-controller/arm-gic.h>
--#include <dt-bindings/leds/common.h>
-+#include "sun50i-h616-orangepi-zero.dtsi"
- 
- / {
- 	model = "OrangePi Zero2";
- 	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
--
--	aliases {
--		ethernet0 = &emac0;
--		serial0 = &uart0;
--	};
--
--	chosen {
--		stdout-path = "serial0:115200n8";
--	};
--
--	leds {
--		compatible = "gpio-leds";
--
--		led-0 {
--			function = LED_FUNCTION_POWER;
--			color = <LED_COLOR_ID_RED>;
--			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
--			default-state = "on";
--		};
--
--		led-1 {
--			function = LED_FUNCTION_STATUS;
--			color = <LED_COLOR_ID_GREEN>;
--			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
--		};
--	};
--
--	reg_vcc5v: vcc5v {
--		/* board wide 5V supply directly from the USB-C socket */
--		compatible = "regulator-fixed";
--		regulator-name = "vcc-5v";
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		regulator-always-on;
--	};
--
--	reg_usb1_vbus: regulator-usb1-vbus {
--		compatible = "regulator-fixed";
--		regulator-name = "usb1-vbus";
--		regulator-min-microvolt = <5000000>;
--		regulator-max-microvolt = <5000000>;
--		vin-supply = <&reg_vcc5v>;
--		enable-active-high;
--		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
--	};
--};
--
--&ehci1 {
--	status = "okay";
- };
- 
--/* USB 2 & 3 are on headers only. */
--
- &emac0 {
--	pinctrl-names = "default";
--	pinctrl-0 = <&ext_rgmii_pins>;
--	phy-mode = "rgmii";
--	phy-handle = <&ext_rgmii_phy>;
- 	phy-supply = <&reg_dcdce>;
--	allwinner,rx-delay-ps = <3100>;
--	allwinner,tx-delay-ps = <700>;
--	status = "okay";
--};
--
--&mdio0 {
--	ext_rgmii_phy: ethernet-phy@1 {
--		compatible = "ethernet-phy-ieee802.3-c22";
--		reg = <1>;
--	};
- };
- 
- &mmc0 {
- 	vmmc-supply = <&reg_dcdce>;
--	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
--	bus-width = <4>;
--	status = "okay";
--};
--
--&ohci1 {
--	status = "okay";
- };
- 
- &r_rsb {
-@@ -211,44 +135,3 @@
- 	vcc-ph-supply = <&reg_aldo1>;
- 	vcc-pi-supply = <&reg_aldo1>;
- };
--
--&spi0  {
--	status = "okay";
--	pinctrl-names = "default";
--	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
--
--	flash@0 {
--		#address-cells = <1>;
--		#size-cells = <1>;
--		compatible = "jedec,spi-nor";
--		reg = <0>;
--		spi-max-frequency = <40000000>;
--	};
--};
--
--&uart0 {
--	pinctrl-names = "default";
--	pinctrl-0 = <&uart0_ph_pins>;
--	status = "okay";
--};
--
--&usbotg {
--	/*
--	 * PHY0 pins are connected to a USB-C socket, but a role switch
--	 * is not implemented: both CC pins are pulled to GND.
--	 * The VBUS pins power the device, so a fixed peripheral mode
--	 * is the best choice.
--	 * The board can be powered via GPIOs, in this case port0 *can*
--	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
--	 * then provided by the GPIOs. Any user of this setup would
--	 * need to adjust the DT accordingly: dr_mode set to "host",
--	 * enabling OHCI0 and EHCI0.
--	 */
--	dr_mode = "peripheral";
--	status = "okay";
--};
--
--&usbphy {
--	usb1_vbus-supply = <&reg_usb1_vbus>;
--	status = "okay";
--};
diff --git a/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch b/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch
deleted file mode 100644
index 4081a82d52..0000000000
--- a/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From f1b3ddb3ecc2eec1f912383e01156c226daacfab Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Fri, 4 Aug 2023 18:08:56 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board
- support
-
-The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC,
-which seems to be just an H616 with more L2 cache. The board itself is a
-slightly updated version of the Orange Pi Zero 2. It features:
-- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
-- 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2)
-- AXP313a PMIC (more capable AXP305 on the Zero2)
-- Raspberry-Pi-1 compatible GPIO header
-- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
-- 1 USB 2.0 host port
-- 1 USB 2.0 type C port (power supply + OTG)
-- MicroSD slot
-- on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2)
-- 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2)
-- micro-HDMI port
-- (yet) unsupported Allwinner WiFi/BT chip
-
-Add the devicetree file describing the currently supported features,
-namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at
-the moment, though the basic functionality works.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230804170856.1237202-4-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/Makefile        |  1 +
- .../allwinner/sun50i-h618-orangepi-zero3.dts  | 94 +++++++++++++++++++
- 2 files changed, 95 insertions(+)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-
---- a/arch/arm64/boot/dts/allwinner/Makefile
-+++ b/arch/arm64/boot/dts/allwinner/Makefile
-@@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-ta
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-@@ -0,0 +1,94 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+/*
-+ * Copyright (C) 2023 Arm Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "sun50i-h616-orangepi-zero.dtsi"
-+
-+/ {
-+	model = "OrangePi Zero3";
-+	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
-+};
-+
-+&emac0 {
-+	phy-supply = <&reg_dldo1>;
-+};
-+
-+&ext_rgmii_phy {
-+	motorcomm,clk-out-frequency-hz = <125000000>;
-+};
-+
-+&mmc0 {
-+	/*
-+	 * The schematic shows the card detect pin wired up to PF6, via an
-+	 * inverter, but it just doesn't work.
-+	 */
-+	broken-cd;
-+	vmmc-supply = <&reg_dldo1>;
-+};
-+
-+&r_i2c {
-+	status = "okay";
-+
-+	axp313: pmic@36 {
-+		compatible = "x-powers,axp313a";
-+		reg = <0x36>;
-+		#interrupt-cells = <1>;
-+		interrupt-controller;
-+		interrupt-parent = <&pio>;
-+		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
-+
-+		vin1-supply = <&reg_vcc5v>;
-+		vin2-supply = <&reg_vcc5v>;
-+		vin3-supply = <&reg_vcc5v>;
-+
-+		regulators {
-+			/* Supplies VCC-PLL, so needs to be always on. */
-+			reg_aldo1: aldo1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-name = "vcc1v8";
-+			};
-+
-+			/* Supplies VCC-IO, so needs to be always on. */
-+			reg_dldo1: dldo1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+				regulator-name = "vcc3v3";
-+			};
-+
-+			reg_dcdc1: dcdc1 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <810000>;
-+				regulator-max-microvolt = <990000>;
-+				regulator-name = "vdd-gpu-sys";
-+			};
-+
-+			reg_dcdc2: dcdc2 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <810000>;
-+				regulator-max-microvolt = <1100000>;
-+				regulator-name = "vdd-cpu";
-+			};
-+
-+			reg_dcdc3: dcdc3 {
-+				regulator-always-on;
-+				regulator-min-microvolt = <1100000>;
-+				regulator-max-microvolt = <1100000>;
-+				regulator-name = "vdd-dram";
-+			};
-+		};
-+	};
-+};
-+
-+&pio {
-+	vcc-pc-supply = <&reg_dldo1>;
-+	vcc-pf-supply = <&reg_dldo1>;
-+	vcc-pg-supply = <&reg_aldo1>;
-+	vcc-ph-supply = <&reg_dldo1>;
-+	vcc-pi-supply = <&reg_dldo1>;
-+};
diff --git a/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch b/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch
deleted file mode 100644
index a492eed551..0000000000
--- a/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From b9622937d95809ef89904583191571a9fa326402 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 29 Oct 2023 15:40:09 +0800
-Subject: [PATCH] arm64: dts: allwinner: h616: update emac for Orange Pi Zero 3
-
-The current emac setting is not suitable for Orange Pi Zero 3,
-move it back to Orange Pi Zero 2 DT. Also update phy mode and
-delay values for emac on Orange Pi Zero 3.
-With these changes, Ethernet now looks stable.
-
-Fixes: 322bf103204b ("arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT")
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20231029074009.7820-2-amadeus@jmu.edu.cn
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 3 ---
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 3 +++
- arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 2 ++
- 3 files changed, 5 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-@@ -68,10 +68,7 @@
- &emac0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&ext_rgmii_pins>;
--	phy-mode = "rgmii";
- 	phy-handle = <&ext_rgmii_phy>;
--	allwinner,rx-delay-ps = <3100>;
--	allwinner,tx-delay-ps = <700>;
- 	status = "okay";
- };
- 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -13,6 +13,9 @@
- };
- 
- &emac0 {
-+	allwinner,rx-delay-ps = <3100>;
-+	allwinner,tx-delay-ps = <700>;
-+	phy-mode = "rgmii";
- 	phy-supply = <&reg_dcdce>;
- };
- 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-@@ -13,6 +13,8 @@
- };
- 
- &emac0 {
-+	allwinner,tx-delay-ps = <700>;
-+	phy-mode = "rgmii-rxid";
- 	phy-supply = <&reg_dldo1>;
- };
- 
diff --git a/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch b/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
deleted file mode 100644
index 3453e2aa53..0000000000
--- a/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:33 +0000
-Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
-
-The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
-in the SRAM control block. If bit 16 is set (the reset value), the
-temperature readings of the THS are way off, leading to reports about
-200C, at normal ambient temperatures. Clearing this bits brings the
-reported values down to the expected values.
-The BSP code clears this bit in firmware (U-Boot), and has an explicit
-comment about this, but offers no real explanation.
-
-Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
-visibility: all tested bit settings still allow full read and write
-access by the CPU to the whole of SRAM C. Only bit 24 of the register at
-offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
-the THS switch functionality as an SRAM region would not reflect reality.
-
-Since we should not rely on firmware settings, allow other code (the THS
-driver) to access this register, by exporting it through the already
-existing regmap. This mimics what we already do for the LDO control and
-the EMAC register.
-
-To avoid concurrent accesses to the same register at the same time, by
-the SRAM switch code and the regmap code, use the same lock to protect
-the access. The regmap subsystem allows to use an existing lock, so we
-just need to hook in there.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
----
- drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/soc/sunxi/sunxi_sram.c
-+++ b/drivers/soc/sunxi/sunxi_sram.c
-@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
- struct sunxi_sramc_variant {
- 	int num_emac_clocks;
- 	bool has_ldo_ctrl;
-+	bool has_ths_offset;
- };
- 
- static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
-@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant
- 
- static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
- 	.num_emac_clocks = 2,
-+	.has_ths_offset = true,
- };
- 
-+#define SUNXI_SRAM_THS_OFFSET_REG	0x0
- #define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
- #define SUNXI_SYS_LDO_CTRL_REG		0x150
- 
-@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible
- {
- 	const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
- 
-+	if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
-+		return true;
- 	if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
- 	    reg <  SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
- 		return true;
-@@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible
- 	return false;
- }
- 
-+static void sunxi_sram_lock(void *_lock)
-+{
-+	spinlock_t *lock = _lock;
-+
-+	spin_lock(lock);
-+}
-+
-+static void sunxi_sram_unlock(void *_lock)
-+{
-+	spinlock_t *lock = _lock;
-+
-+	spin_unlock(lock);
-+}
-+
- static struct regmap_config sunxi_sram_regmap_config = {
- 	.reg_bits       = 32,
- 	.val_bits       = 32,
-@@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r
- 	/* other devices have no business accessing other registers */
- 	.readable_reg	= sunxi_sram_regmap_accessible_reg,
- 	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
-+	.lock		= sunxi_sram_lock,
-+	.unlock		= sunxi_sram_unlock,
-+	.lock_arg	= &sram_lock,
- };
- 
- static int __init sunxi_sram_probe(struct platform_device *pdev)
diff --git a/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
deleted file mode 100644
index 8b19989118..0000000000
--- a/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
-From: Maxim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 18 Dec 2023 00:06:23 +0300
-Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
-
-This patch adds a thermal sensor controller support for the D1/T113s,
-which is similar to the one on H6, but with only one sensor and
-different scale and offset values.
-
-Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
----
- drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -610,6 +610,18 @@ static const struct ths_thermal_chip sun
- 	.calc_temp = sun8i_ths_calc_temp,
- };
- 
-+static const struct ths_thermal_chip sun20i_d1_ths = {
-+	.sensor_num = 1,
-+	.has_bus_clk_reset = true,
-+	.offset = 188552,
-+	.scale = 673,
-+	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+	.calibrate = sun50i_h6_ths_calibrate,
-+	.init = sun50i_h6_thermal_init,
-+	.irq_ack = sun50i_h6_irq_ack,
-+	.calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -618,6 +630,7 @@ static const struct of_device_id of_ths_
- 	{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
- 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
-+	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
- 	{ /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
diff --git a/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch b/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
deleted file mode 100644
index 3d01a507fa..0000000000
--- a/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
-From: Maksim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 19 Feb 2024 15:36:36 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
- sensors
-
-The H616 SoC resembles the H6 thermal sensor controller, with a few
-changes like four sensors.
-
-Extend sun50i_h6_ths_calibrate() function to support calibration of
-these sensors.
-
-Co-developed-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
- 1 file changed, 20 insertions(+), 8 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -224,16 +224,21 @@ static int sun50i_h6_ths_calibrate(struc
- 	struct device *dev = tmdev->dev;
- 	int i, ft_temp;
- 
--	if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
-+	if (!caldata[0])
- 		return -EINVAL;
- 
- 	/*
- 	 * efuse layout:
- 	 *
--	 *	0   11  16	 32
--	 *	+-------+-------+-------+
--	 *	|temp|  |sensor0|sensor1|
--	 *	+-------+-------+-------+
-+	 * 0      11  16     27   32     43   48    57
-+	 * +----------+-----------+-----------+-----------+
-+	 * |  temp |  |sensor0|   |sensor1|   |sensor2|   |
-+	 * +----------+-----------+-----------+-----------+
-+	 *                      ^           ^           ^
-+	 *                      |           |           |
-+	 *                      |           |           sensor3[11:8]
-+	 *                      |           sensor3[7:4]
-+	 *                      sensor3[3:0]
- 	 *
- 	 * The calibration data on the H6 is the ambient temperature and
- 	 * sensor values that are filled during the factory test stage.
-@@ -246,9 +251,16 @@ static int sun50i_h6_ths_calibrate(struc
- 	ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
- 
- 	for (i = 0; i < tmdev->chip->sensor_num; i++) {
--		int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
--		int cdata, offset;
--		int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
-+		int sensor_reg, sensor_temp, cdata, offset;
-+
-+		if (i == 3)
-+			sensor_reg = (caldata[1] >> 12)
-+				     | ((caldata[2] >> 12) << 4)
-+				     | ((caldata[3] >> 12) << 8);
-+		else
-+			sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
-+
-+		sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
- 
- 		/*
- 		 * Calibration data is CALIBRATE_DEFAULT - (calculated
diff --git a/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch b/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
deleted file mode 100644
index 6db1e32cfb..0000000000
--- a/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:37 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
-
-The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
-controller, to report reasonable temperature values. On reset, bit 16 in
-register 0x3000000 is set, which leads to the driver reporting
-temperatures around 200C. Clearing this bit brings the values down to the
-expected range. The BSP code does a one-time write in U-Boot, with a
-comment just mentioning the effect on the THS, but offering no further
-explanation.
-
-To not rely on firmware to set things up for us, add code that queries
-the SRAM controller device via a DT phandle link, then clear just this
-single bit.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_device.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
- #include <linux/reset.h>
-@@ -68,6 +69,7 @@ struct tsensor {
- struct ths_thermal_chip {
- 	bool            has_mod_clk;
- 	bool            has_bus_clk_reset;
-+	bool		needs_sram;
- 	int		sensor_num;
- 	int		offset;
- 	int		scale;
-@@ -85,12 +87,16 @@ struct ths_device {
- 	const struct ths_thermal_chip		*chip;
- 	struct device				*dev;
- 	struct regmap				*regmap;
-+	struct regmap_field			*sram_regmap_field;
- 	struct reset_control			*reset;
- 	struct clk				*bus_clk;
- 	struct clk                              *mod_clk;
- 	struct tsensor				sensor[MAX_SENSOR_NUM];
- };
- 
-+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
-+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
-+
- /* Temp Unit: millidegree Celsius */
- static int sun8i_ths_calc_temp(struct ths_device *tmdev,
- 			       int id, int reg)
-@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
- 	reset_control_assert(data);
- }
- 
-+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
-+{
-+	struct device_node *sram_node;
-+	struct platform_device *sram_pdev;
-+	struct regmap *regmap = NULL;
-+
-+	sram_node = of_parse_phandle(node, "allwinner,sram", 0);
-+	if (!sram_node)
-+		return ERR_PTR(-ENODEV);
-+
-+	sram_pdev = of_find_device_by_node(sram_node);
-+	if (!sram_pdev) {
-+		/* platform device might not be probed yet */
-+		regmap = ERR_PTR(-EPROBE_DEFER);
-+		goto out_put_node;
-+	}
-+
-+	/* If no regmap is found then the other device driver is at fault */
-+	regmap = dev_get_regmap(&sram_pdev->dev, NULL);
-+	if (!regmap)
-+		regmap = ERR_PTR(-EINVAL);
-+
-+	platform_device_put(sram_pdev);
-+out_put_node:
-+	of_node_put(sram_node);
-+	return regmap;
-+}
-+
- static int sun8i_ths_resource_init(struct ths_device *tmdev)
- {
- 	struct device *dev = tmdev->dev;
-@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
- 	if (ret)
- 		return ret;
- 
-+	if (tmdev->chip->needs_sram) {
-+		struct regmap *regmap;
-+
-+		regmap = sun8i_ths_get_sram_regmap(dev->of_node);
-+		if (IS_ERR(regmap))
-+			return PTR_ERR(regmap);
-+		tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
-+						      regmap,
-+						      sun8i_ths_sram_reg_field);
-+		if (IS_ERR(tmdev->sram_regmap_field))
-+			return PTR_ERR(tmdev->sram_regmap_field);
-+	}
-+
- 	ret = sun8i_ths_calibrate(tmdev);
- 	if (ret)
- 		return ret;
-@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
- {
- 	int val;
- 
-+	/* The H616 needs to have a bit in the SRAM control register cleared. */
-+	if (tmdev->sram_regmap_field)
-+		regmap_field_write(tmdev->sram_regmap_field, 0);
-+
- 	/*
- 	 * The manual recommends an overall sample frequency of 50 KHz (20us,
- 	 * 480 cycles at 24 MHz), which provides plenty of time for both the
diff --git a/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch b/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
deleted file mode 100644
index e743d344c6..0000000000
--- a/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Mon, 19 Feb 2024 15:36:38 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
-
-Add support for the thermal sensor found in H616 SoCs, is the same as
-the H6 thermal sensor controller, but with four sensors.
-Also the registers readings are wrong, unless a bit in the first SYS_CFG
-register cleared, so set exercise the SRAM regmap to take care of that.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -688,6 +688,20 @@ static const struct ths_thermal_chip sun
- 	.calc_temp = sun8i_ths_calc_temp,
- };
- 
-+static const struct ths_thermal_chip sun50i_h616_ths = {
-+	.sensor_num = 4,
-+	.has_bus_clk_reset = true,
-+	.needs_sram = true,
-+	.ft_deviation = 8000,
-+	.offset = 263655,
-+	.scale = 810,
-+	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+	.calibrate = sun50i_h6_ths_calibrate,
-+	.init = sun50i_h6_thermal_init,
-+	.irq_ack = sun50i_h6_irq_ack,
-+	.calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -697,6 +711,7 @@ static const struct of_device_id of_ths_
- 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
- 	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
-+	{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
- 	{ /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
diff --git a/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch b/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
deleted file mode 100644
index 384bf55084..0000000000
--- a/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
-From: Mark Brown <broonie@kernel.org>
-Date: Tue, 23 Jan 2024 23:33:07 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
- registration failure
-
-Currently the sun8i thermal driver will fail to probe if any of the
-thermal zones it is registering fails to register with the thermal core.
-Since we currently do not define any trip points for the GPU thermal
-zones on at least A64 or H5 this means that we have no thermal support
-on these platforms:
-
-[    1.698703] thermal_sys: Failed to find 'trips' node
-[    1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
-
-even though the main CPU thermal zone on both SoCs is fully configured.
-This does not seem ideal, while we may not be able to use all the zones
-it seems better to have those zones which are usable be operational.
-Instead just carry on registering zones if we get any non-deferral
-error, allowing use of those zones which are usable.
-
-This means that we also need to update the interrupt handler to not
-attempt to notify the core for events on zones which we have not
-registered, I didn't see an ability to mask individual interrupts and
-I would expect that interrupts would still be indicated in the ISR even
-if they were masked.
-
-Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
----
- drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -197,6 +197,9 @@ static irqreturn_t sun8i_irq_thread(int
- 	int i;
- 
- 	for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
-+		/* We allow some zones to not register. */
-+		if (IS_ERR(tmdev->sensor[i].tzd))
-+			continue;
- 		thermal_zone_device_update(tmdev->sensor[i].tzd,
- 					   THERMAL_EVENT_UNSPECIFIED);
- 	}
-@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
- 						      i,
- 						      &tmdev->sensor[i],
- 						      &ths_ops);
--		if (IS_ERR(tmdev->sensor[i].tzd))
--			return PTR_ERR(tmdev->sensor[i].tzd);
-+
-+		/*
-+		 * If an individual zone fails to register for reasons
-+		 * other than probe deferral (eg, a bad DT) then carry
-+		 * on, other zones might register successfully.
-+		 */
-+		if (IS_ERR(tmdev->sensor[i].tzd)) {
-+			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
-+				return PTR_ERR(tmdev->sensor[i].tzd);
-+			continue;
-+		}
- 
- 		if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
- 			dev_warn(tmdev->dev,
diff --git a/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch
deleted file mode 100644
index 2c5ccd7d96..0000000000
--- a/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-@@ -59,7 +59,7 @@
- 
- 		key-sw4 {
- 			label = "sw4";
--			linux,code = <BTN_0>;
-+			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
- 			wakeup-source;
- 		};
-@@ -220,7 +220,7 @@
- };
- 
- &usb_otg {
--	dr_mode = "otg";
-+	dr_mode = "host";
- 	status = "okay";
- };
- 
diff --git a/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch
deleted file mode 100644
index 5b8dd170c5..0000000000
--- a/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch
+++ /dev/null
@@ -1,292 +0,0 @@
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -1352,6 +1352,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
- 	sun8i-a83t-cubietruck-plus.dtb \
- 	sun8i-a83t-tbs-a711.dtb \
- 	sun8i-h2-plus-bananapi-m2-zero.dtb \
-+	sun8i-h2-plus-bananapi-p2-zero.dtb \
- 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
- 	sun8i-h2-plus-orangepi-r1.dtb \
- 	sun8i-h2-plus-orangepi-zero.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-p2-zero.dts
-@@ -0,0 +1,279 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
-+ *
-+ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
-+ *   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
-+ */
-+
-+/dts-v1/;
-+#include "sun8i-h3.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+	model = "Banana Pi BPI-P2-Zero";
-+	compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
-+
-+	aliases {
-+		serial0 = &uart0;
-+		serial1 = &uart1;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	connector {
-+		compatible = "hdmi-connector";
-+		type = "c";
-+
-+		port {
-+			hdmi_con_in: endpoint {
-+				remote-endpoint = <&hdmi_out_con>;
-+			};
-+		};
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		pwr_led {
-+			label = "bananapi-p2-zero:red:pwr";
-+			gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
-+			default-state = "on";
-+		};
-+	};
-+
-+	gpio_keys {
-+		compatible = "gpio-keys";
-+
-+		sw4 {
-+			label = "power";
-+			linux,code = <BTN_0>;
-+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	reg_vdd_cpux: vdd-cpux-regulator {
-+		compatible = "regulator-gpio";
-+		regulator-name = "vdd-cpux";
-+		regulator-type = "voltage";
-+		regulator-boot-on;
-+		regulator-always-on;
-+		regulator-min-microvolt = <1100000>;
-+		regulator-max-microvolt = <1300000>;
-+		regulator-ramp-delay = <50>; /* 4ms */
-+
-+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
-+		enable-active-high;
-+		gpios-states = <0x1>;
-+		states = <1100000 0>, <1300000 1>;
-+	};
-+
-+	reg_vcc_dram: vcc-dram {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc-dram";
-+		regulator-min-microvolt = <1500000>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		enable-active-high;
-+		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
-+		vin-supply = <&reg_vcc5v0>;
-+	};
-+
-+	reg_vcc1v2: vcc1v2 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc1v2";
-+		regulator-min-microvolt = <1200000>;
-+		regulator-max-microvolt = <1200000>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		enable-active-high;
-+		gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
-+		vin-supply = <&reg_vcc5v0>;
-+	};
-+
-+	poweroff {
-+		compatible = "regulator-poweroff";
-+		cpu-supply = <&reg_vcc1v2>;
-+	};
-+
-+	wifi_pwrseq: wifi_pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-+		clocks = <&rtc 1>;
-+		clock-names = "ext_clock";
-+	};
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&reg_vdd_cpux>;
-+};
-+
-+&de {
-+	status = "okay";
-+};
-+
-+&ehci0 {
-+	status = "okay";
-+};
-+
-+&emac {
-+	phy-handle = <&int_mii_phy>;
-+	phy-mode = "mii";
-+	allwinner,leds-active-low;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	status = "okay";
-+};
-+
-+&hdmi_out {
-+	hdmi_out_con: endpoint {
-+		remote-endpoint = <&hdmi_con_in>;
-+	};
-+};
-+
-+&mmc0 {
-+	vmmc-supply = <&reg_vcc3v3>;
-+	bus-width = <4>;
-+	/*
-+	 * On the production batch of this board the card detect GPIO is
-+	 * high active (card inserted), although on the early samples it's
-+	 * low active.
-+	 */
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+	status = "okay";
-+};
-+
-+&mmc1 {
-+	vmmc-supply = <&reg_vcc3v3>;
-+	vqmmc-supply = <&reg_vcc3v3>;
-+	mmc-pwrseq = <&wifi_pwrseq>;
-+	bus-width = <4>;
-+	non-removable;
-+	status = "okay";
-+
-+	brcmf: wifi@1 {
-+		reg = <1>;
-+		compatible = "brcm,bcm4329-fmac";
-+		interrupt-parent = <&pio>;
-+		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
-+		interrupt-names = "host-wake";
-+	};
-+};
-+
-+&ohci0 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pa_pins>;
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+	uart-has-rtscts;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		max-speed = <1500000>;
-+		clocks = <&rtc 1>;
-+		clock-names = "lpo";
-+		vbat-supply = <&reg_vcc3v3>;
-+		vddio-supply = <&reg_vcc3v3>;
-+		device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
-+		host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
-+		shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-+	};
-+
-+};
-+
-+&pio {
-+	gpio-line-names =
-+		/* PA */
-+		"CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
-+			"CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
-+		"CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
-+			"CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
-+		"CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
-+			"CON2-P40", "CON2-P38", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PB */
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PC */
-+		"CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
-+			"CON2-P18", "", "", "CON2-P26",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PD */
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "CSI-PWR-EN", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PE */
-+		"CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
-+			"CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
-+		"CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
-+			"CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PF */
-+		"SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
-+			"SDC0-D2", "SDC0-DET", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+
-+		/* PG */
-+		"WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
-+			"WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
-+		"BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
-+			"BT-RST-N", "AP-WAKE-BT", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "";
-+};
-+
-+&r_pio {
-+	gpio-line-names =
-+		/* PL */
-+		"", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
-+			"VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
-+		"PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
-+		"", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "";
-+};
-+
-+&usb_otg {
-+	dr_mode = "otg";
-+	status = "okay";
-+};
-+
-+&usbphy {
-+	usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-+	/*
-+	 * There're two micro-USB connectors, one is power-only and another is
-+	 * OTG. The Vbus of these two connectors are connected together, so
-+	 * the external USB device will be powered just by the power input
-+	 * from the power-only USB port.
-+	 */
-+	status = "okay";
-+};
diff --git a/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch b/target/linux/sunxi/patches-6.6/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch
index ce8add18ab..ce8add18ab 100644
--- a/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch
+++ b/target/linux/sunxi/patches-6.6/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch
diff --git a/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch b/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
new file mode 100644
index 0000000000..5f9cb0273a
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
@@ -0,0 +1,98 @@
+From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:33 +0000
+Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
+
+The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
+in the SRAM control block. If bit 16 is set (the reset value), the
+temperature readings of the THS are way off, leading to reports about
+200C, at normal ambient temperatures. Clearing this bits brings the
+reported values down to the expected values.
+The BSP code clears this bit in firmware (U-Boot), and has an explicit
+comment about this, but offers no real explanation.
+
+Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
+visibility: all tested bit settings still allow full read and write
+access by the CPU to the whole of SRAM C. Only bit 24 of the register at
+offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
+the THS switch functionality as an SRAM region would not reflect reality.
+
+Since we should not rely on firmware settings, allow other code (the THS
+driver) to access this register, by exporting it through the already
+existing regmap. This mimics what we already do for the LDO control and
+the EMAC register.
+
+To avoid concurrent accesses to the same register at the same time, by
+the SRAM switch code and the regmap code, use the same lock to protect
+the access. The regmap subsystem allows to use an existing lock, so we
+just need to hook in there.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
+---
+ drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
+ struct sunxi_sramc_variant {
+ 	int num_emac_clocks;
+ 	bool has_ldo_ctrl;
++	bool has_ths_offset;
+ };
+ 
+ static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
+@@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant
+ 
+ static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ 	.num_emac_clocks = 2,
++	.has_ths_offset = true,
+ };
+ 
++#define SUNXI_SRAM_THS_OFFSET_REG	0x0
+ #define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
+ #define SUNXI_SYS_LDO_CTRL_REG		0x150
+ 
+@@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible
+ {
+ 	const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
+ 
++	if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
++		return true;
+ 	if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
+ 	    reg <  SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ 		return true;
+@@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible
+ 	return false;
+ }
+ 
++static void sunxi_sram_lock(void *_lock)
++{
++	spinlock_t *lock = _lock;
++
++	spin_lock(lock);
++}
++
++static void sunxi_sram_unlock(void *_lock)
++{
++	spinlock_t *lock = _lock;
++
++	spin_unlock(lock);
++}
++
+ static struct regmap_config sunxi_sram_regmap_config = {
+ 	.reg_bits       = 32,
+ 	.val_bits       = 32,
+@@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_r
+ 	/* other devices have no business accessing other registers */
+ 	.readable_reg	= sunxi_sram_regmap_accessible_reg,
+ 	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
++	.lock		= sunxi_sram_lock,
++	.unlock		= sunxi_sram_unlock,
++	.lock_arg	= &sram_lock,
+ };
+ 
+ static int __init sunxi_sram_probe(struct platform_device *pdev)
diff --git a/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
new file mode 100644
index 0000000000..66f576eb38
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
@@ -0,0 +1,47 @@
+From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:23 +0300
+Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
+
+This patch adds a thermal sensor controller support for the D1/T113s,
+which is similar to the one on H6, but with only one sensor and
+different scale and offset values.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
+---
+ drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
+ 	.calc_temp = sun8i_ths_calc_temp,
+ };
+ 
++static const struct ths_thermal_chip sun20i_d1_ths = {
++	.sensor_num = 1,
++	.has_bus_clk_reset = true,
++	.offset = 188552,
++	.scale = 673,
++	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++	.calibrate = sun50i_h6_ths_calibrate,
++	.init = sun50i_h6_thermal_init,
++	.irq_ack = sun50i_h6_irq_ack,
++	.calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
+ 	{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
diff --git a/target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch b/target/linux/sunxi/patches-6.6/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch
index b8138a3870..b8138a3870 100644
--- a/target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch
+++ b/target/linux/sunxi/patches-6.6/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch
diff --git a/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch b/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
new file mode 100644
index 0000000000..a0dbad48c9
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
@@ -0,0 +1,74 @@
+From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 19 Feb 2024 15:36:36 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
+ sensors
+
+The H616 SoC resembles the H6 thermal sensor controller, with a few
+changes like four sensors.
+
+Extend sun50i_h6_ths_calibrate() function to support calibration of
+these sensors.
+
+Co-developed-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
+ 1 file changed, 20 insertions(+), 8 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -222,16 +222,21 @@ static int sun50i_h6_ths_calibrate(struc
+ 	struct device *dev = tmdev->dev;
+ 	int i, ft_temp;
+ 
+-	if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
++	if (!caldata[0])
+ 		return -EINVAL;
+ 
+ 	/*
+ 	 * efuse layout:
+ 	 *
+-	 *	0   11  16	 32
+-	 *	+-------+-------+-------+
+-	 *	|temp|  |sensor0|sensor1|
+-	 *	+-------+-------+-------+
++	 * 0      11  16     27   32     43   48    57
++	 * +----------+-----------+-----------+-----------+
++	 * |  temp |  |sensor0|   |sensor1|   |sensor2|   |
++	 * +----------+-----------+-----------+-----------+
++	 *                      ^           ^           ^
++	 *                      |           |           |
++	 *                      |           |           sensor3[11:8]
++	 *                      |           sensor3[7:4]
++	 *                      sensor3[3:0]
+ 	 *
+ 	 * The calibration data on the H6 is the ambient temperature and
+ 	 * sensor values that are filled during the factory test stage.
+@@ -244,9 +249,16 @@ static int sun50i_h6_ths_calibrate(struc
+ 	ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
+ 
+ 	for (i = 0; i < tmdev->chip->sensor_num; i++) {
+-		int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
+-		int cdata, offset;
+-		int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
++		int sensor_reg, sensor_temp, cdata, offset;
++
++		if (i == 3)
++			sensor_reg = (caldata[1] >> 12)
++				     | ((caldata[2] >> 12) << 4)
++				     | ((caldata[3] >> 12) << 8);
++		else
++			sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
++
++		sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
+ 
+ 		/*
+ 		 * Calibration data is CALIBRATE_DEFAULT - (calculated
diff --git a/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch b/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
new file mode 100644
index 0000000000..9b5e9d374f
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
@@ -0,0 +1,126 @@
+From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:37 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
+
+The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
+controller, to report reasonable temperature values. On reset, bit 16 in
+register 0x3000000 is set, which leads to the driver reporting
+temperatures around 200C. Clearing this bit brings the values down to the
+expected range. The BSP code does a one-time write in U-Boot, with a
+comment just mentioning the effect on the THS, but offering no further
+explanation.
+
+To not rely on firmware to set things up for us, add code that queries
+the SRAM controller device via a DT phandle link, then clear just this
+single bit.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -15,6 +15,7 @@
+ #include <linux/module.h>
+ #include <linux/nvmem-consumer.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -66,6 +67,7 @@ struct tsensor {
+ struct ths_thermal_chip {
+ 	bool            has_mod_clk;
+ 	bool            has_bus_clk_reset;
++	bool		needs_sram;
+ 	int		sensor_num;
+ 	int		offset;
+ 	int		scale;
+@@ -83,12 +85,16 @@ struct ths_device {
+ 	const struct ths_thermal_chip		*chip;
+ 	struct device				*dev;
+ 	struct regmap				*regmap;
++	struct regmap_field			*sram_regmap_field;
+ 	struct reset_control			*reset;
+ 	struct clk				*bus_clk;
+ 	struct clk                              *mod_clk;
+ 	struct tsensor				sensor[MAX_SENSOR_NUM];
+ };
+ 
++/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
++static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
++
+ /* Temp Unit: millidegree Celsius */
+ static int sun8i_ths_calc_temp(struct ths_device *tmdev,
+ 			       int id, int reg)
+@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
+ 	reset_control_assert(data);
+ }
+ 
++static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
++{
++	struct device_node *sram_node;
++	struct platform_device *sram_pdev;
++	struct regmap *regmap = NULL;
++
++	sram_node = of_parse_phandle(node, "allwinner,sram", 0);
++	if (!sram_node)
++		return ERR_PTR(-ENODEV);
++
++	sram_pdev = of_find_device_by_node(sram_node);
++	if (!sram_pdev) {
++		/* platform device might not be probed yet */
++		regmap = ERR_PTR(-EPROBE_DEFER);
++		goto out_put_node;
++	}
++
++	/* If no regmap is found then the other device driver is at fault */
++	regmap = dev_get_regmap(&sram_pdev->dev, NULL);
++	if (!regmap)
++		regmap = ERR_PTR(-EINVAL);
++
++	platform_device_put(sram_pdev);
++out_put_node:
++	of_node_put(sram_node);
++	return regmap;
++}
++
+ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ {
+ 	struct device *dev = tmdev->dev;
+@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
+ 	if (ret)
+ 		return ret;
+ 
++	if (tmdev->chip->needs_sram) {
++		struct regmap *regmap;
++
++		regmap = sun8i_ths_get_sram_regmap(dev->of_node);
++		if (IS_ERR(regmap))
++			return PTR_ERR(regmap);
++		tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
++						      regmap,
++						      sun8i_ths_sram_reg_field);
++		if (IS_ERR(tmdev->sram_regmap_field))
++			return PTR_ERR(tmdev->sram_regmap_field);
++	}
++
+ 	ret = sun8i_ths_calibrate(tmdev);
+ 	if (ret)
+ 		return ret;
+@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
+ {
+ 	int val;
+ 
++	/* The H616 needs to have a bit in the SRAM control register cleared. */
++	if (tmdev->sram_regmap_field)
++		regmap_field_write(tmdev->sram_regmap_field, 0);
++
+ 	/*
+ 	 * The manual recommends an overall sample frequency of 50 KHz (20us,
+ 	 * 480 cycles at 24 MHz), which provides plenty of time for both the
diff --git a/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch b/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
new file mode 100644
index 0000000000..187bc0dd7b
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
@@ -0,0 +1,50 @@
+From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Mon, 19 Feb 2024 15:36:38 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
+
+Add support for the thermal sensor found in H616 SoCs, is the same as
+the H6 thermal sensor controller, but with four sensors.
+Also the registers readings are wrong, unless a bit in the first SYS_CFG
+register cleared, so set exercise the SRAM regmap to take care of that.
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -684,6 +684,20 @@ static const struct ths_thermal_chip sun
+ 	.calc_temp = sun8i_ths_calc_temp,
+ };
+ 
++static const struct ths_thermal_chip sun50i_h616_ths = {
++	.sensor_num = 4,
++	.has_bus_clk_reset = true,
++	.needs_sram = true,
++	.ft_deviation = 8000,
++	.offset = 263655,
++	.scale = 810,
++	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++	.calibrate = sun50i_h6_ths_calibrate,
++	.init = sun50i_h6_thermal_init,
++	.irq_ack = sun50i_h6_irq_ack,
++	.calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -693,6 +707,7 @@ static const struct of_device_id of_ths_
+ 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
+ 	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
++	{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
+ 	{ /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
diff --git a/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch b/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
new file mode 100644
index 0000000000..dd18cd953c
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
@@ -0,0 +1,68 @@
+From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
+From: Mark Brown <broonie@kernel.org>
+Date: Tue, 23 Jan 2024 23:33:07 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
+ registration failure
+
+Currently the sun8i thermal driver will fail to probe if any of the
+thermal zones it is registering fails to register with the thermal core.
+Since we currently do not define any trip points for the GPU thermal
+zones on at least A64 or H5 this means that we have no thermal support
+on these platforms:
+
+[    1.698703] thermal_sys: Failed to find 'trips' node
+[    1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
+
+even though the main CPU thermal zone on both SoCs is fully configured.
+This does not seem ideal, while we may not be able to use all the zones
+it seems better to have those zones which are usable be operational.
+Instead just carry on registering zones if we get any non-deferral
+error, allowing use of those zones which are usable.
+
+This means that we also need to update the interrupt handler to not
+attempt to notify the core for events on zones which we have not
+registered, I didn't see an ability to mask individual interrupts and
+I would expect that interrupts would still be indicated in the ISR even
+if they were masked.
+
+Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
+---
+ drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -195,6 +195,9 @@ static irqreturn_t sun8i_irq_thread(int
+ 	int i;
+ 
+ 	for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
++		/* We allow some zones to not register. */
++		if (IS_ERR(tmdev->sensor[i].tzd))
++			continue;
+ 		thermal_zone_device_update(tmdev->sensor[i].tzd,
+ 					   THERMAL_EVENT_UNSPECIFIED);
+ 	}
+@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
+ 						      i,
+ 						      &tmdev->sensor[i],
+ 						      &ths_ops);
+-		if (IS_ERR(tmdev->sensor[i].tzd))
+-			return PTR_ERR(tmdev->sensor[i].tzd);
++
++		/*
++		 * If an individual zone fails to register for reasons
++		 * other than probe deferral (eg, a bad DT) then carry
++		 * on, other zones might register successfully.
++		 */
++		if (IS_ERR(tmdev->sensor[i].tzd)) {
++			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
++				return PTR_ERR(tmdev->sensor[i].tzd);
++			continue;
++		}
+ 
+ 		devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd);
+ 	}
diff --git a/target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch b/target/linux/sunxi/patches-6.6/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch
index cd6542bf14..cd6542bf14 100644
--- a/target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch
+++ b/target/linux/sunxi/patches-6.6/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch
diff --git a/target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-6.6/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch
index 30c98aa737..30c98aa737 100644
--- a/target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch
+++ b/target/linux/sunxi/patches-6.6/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch
diff --git a/target/linux/sunxi/patches-6.6/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.6/301-orangepi_pc2_usb_otg_to_host_key_power.patch
new file mode 100644
index 0000000000..eea47737fa
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/301-orangepi_pc2_usb_otg_to_host_key_power.patch
@@ -0,0 +1,20 @@
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 			wakeup-source;
+ 		};
+@@ -221,7 +221,7 @@
+ };
+ 
+ &usb_otg {
+-	dr_mode = "otg";
++	dr_mode = "host";
+ 	status = "okay";
+ };
+ 
diff --git a/target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-6.6/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch
index a8dfcd9dbc..a8dfcd9dbc 100644
--- a/target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch
+++ b/target/linux/sunxi/patches-6.6/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch
diff --git a/target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch
new file mode 100644
index 0000000000..01044fef49
--- /dev/null
+++ b/target/linux/sunxi/patches-6.6/410-sunxi-add-bananapi-p2-zero.patch
@@ -0,0 +1,292 @@
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -280,6 +280,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-a83t-cubietruck-plus.dtb \
+ 	sun8i-a83t-tbs-a711.dtb \
+ 	sun8i-h2-plus-bananapi-m2-zero.dtb \
++	sun8i-h2-plus-bananapi-p2-zero.dtb \
+ 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
+ 	sun8i-h2-plus-orangepi-r1.dtb \
+ 	sun8i-h2-plus-orangepi-zero.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-p2-zero.dts
+@@ -0,0 +1,279 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
++ *
++ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
++ *   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Banana Pi BPI-P2-Zero";
++	compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
++
++	aliases {
++		serial0 = &uart0;
++		serial1 = &uart1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "c";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr_led {
++			label = "bananapi-p2-zero:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++			default-state = "on";
++		};
++	};
++
++	gpio_keys {
++		compatible = "gpio-keys";
++
++		sw4 {
++			label = "power";
++			linux,code = <BTN_0>;
++			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	reg_vdd_cpux: vdd-cpux-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++
++		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0>, <1300000 1>;
++	};
++
++	reg_vcc_dram: vcc-dram {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-dram";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		regulator-always-on;
++		regulator-boot-on;
++		enable-active-high;
++		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++		vin-supply = <&reg_vcc5v0>;
++	};
++
++	reg_vcc1v2: vcc1v2 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v2";
++		regulator-min-microvolt = <1200000>;
++		regulator-max-microvolt = <1200000>;
++		regulator-always-on;
++		regulator-boot-on;
++		enable-active-high;
++		gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		vin-supply = <&reg_vcc5v0>;
++	};
++
++	poweroff {
++		compatible = "regulator-poweroff";
++		cpu-supply = <&reg_vcc1v2>;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	/*
++	 * On the production batch of this board the card detect GPIO is
++	 * high active (card inserted), although on the early samples it's
++	 * low active.
++	 */
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		max-speed = <1500000>;
++		clocks = <&rtc 1>;
++		clock-names = "lpo";
++		vbat-supply = <&reg_vcc3v3>;
++		vddio-supply = <&reg_vcc3v3>;
++		device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
++		shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	};
++
++};
++
++&pio {
++	gpio-line-names =
++		/* PA */
++		"CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
++			"CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
++		"CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
++			"CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
++		"CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
++			"CON2-P40", "CON2-P38", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PB */
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PC */
++		"CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
++			"CON2-P18", "", "", "CON2-P26",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PD */
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "CSI-PWR-EN", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PE */
++		"CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
++			"CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
++		"CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
++			"CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PF */
++		"SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
++			"SDC0-D2", "SDC0-DET", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PG */
++		"WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
++			"WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
++		"BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
++			"BT-RST-N", "AP-WAKE-BT", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "";
++};
++
++&r_pio {
++	gpio-line-names =
++		/* PL */
++		"", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
++			"VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
++		"PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++	/*
++	 * There're two micro-USB connectors, one is power-only and another is
++	 * OTG. The Vbus of these two connectors are connected together, so
++	 * the external USB device will be powered just by the power input
++	 * from the power-only USB port.
++	 */
++	status = "okay";
++};
diff --git a/target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-6.6/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch
index 68ec333e37..68ec333e37 100644
--- a/target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch
+++ b/target/linux/sunxi/patches-6.6/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch
diff --git a/target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-6.6/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch
index 8670d06109..8670d06109 100644
--- a/target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch
+++ b/target/linux/sunxi/patches-6.6/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch
diff --git a/target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-6.6/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
index 76a73ee1f0..76a73ee1f0 100644
--- a/target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
+++ b/target/linux/sunxi/patches-6.6/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
diff --git a/target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.6/450-arm64-dts-enable-wifi-on-pine64-boards.patch
index 3876852c2b..3876852c2b 100644
--- a/target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch
+++ b/target/linux/sunxi/patches-6.6/450-arm64-dts-enable-wifi-on-pine64-boards.patch
diff --git a/target/linux/tegra/Makefile b/target/linux/tegra/Makefile
index 43ca154e8a..3513e2751e 100644
--- a/target/linux/tegra/Makefile
+++ b/target/linux/tegra/Makefile
@@ -13,6 +13,7 @@ CPU_SUBTYPE := vfpv3-d16
 SUBTARGETS := generic
 
 KERNEL_PATCHVER := 5.15
+KERNEL_TESTING_PATCHVER := 6.6
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/tegra/config-5.15 b/target/linux/tegra/config-5.15
index 257ffda252..c143c3f5a9 100644
--- a/target/linux/tegra/config-5.15
+++ b/target/linux/tegra/config-5.15
@@ -157,6 +157,7 @@ CONFIG_DMA_SHARED_BUFFER=y
 CONFIG_DNOTIFY=y
 CONFIG_DRM=y
 CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DP_AUX_BUS=y
 CONFIG_DRM_FBDEV_EMULATION=y
 CONFIG_DRM_FBDEV_OVERALLOC=100
 CONFIG_DRM_KMS_HELPER=y
@@ -186,6 +187,7 @@ CONFIG_FB_SYS_IMAGEBLIT=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FS_IOMAP=y
 CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ARCH_TOPOLOGY=y
@@ -297,6 +299,7 @@ CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NLS=y
 CONFIG_NR_CPUS=4
 CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
@@ -386,7 +389,6 @@ CONFIG_SMP_ON_UP=y
 CONFIG_SND=y
 # CONFIG_SND_COMPRESS_OFFLOAD is not set
 CONFIG_SND_DMAENGINE_PCM=y
-# CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_HDA_TEGRA is not set
 CONFIG_SND_JACK=y
 CONFIG_SND_JACK_INPUT_DEV=y
diff --git a/target/linux/tegra/config-6.6 b/target/linux/tegra/config-6.6
new file mode 100644
index 0000000000..c86a51a572
--- /dev/null
+++ b/target/linux/tegra/config-6.6
@@ -0,0 +1,579 @@
+CONFIG_AC97_BUS=y
+# CONFIG_AHCI_TEGRA is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_TEGRA=y
+# CONFIG_ARCH_TEGRA_114_SOC is not set
+# CONFIG_ARCH_TEGRA_124_SOC is not set
+CONFIG_ARCH_TEGRA_2x_SOC=y
+# CONFIG_ARCH_TEGRA_3x_SOC is not set
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_TEGRA124_CPUFREQ is not set
+CONFIG_ARM_TEGRA20_CPUFREQ=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASN1=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_STAT is not set
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_LZ4HC=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DDR=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+CONFIG_DEVFREQ_THERMAL=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DP_AUX_BUS=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_TEGRA=y
+# CONFIG_DRM_TEGRA_DEBUG is not set
+# CONFIG_DRM_TEGRA_STAGING is not set
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_TEGRA=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_TEGRA=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INTERCONNECT=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_IOVA=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KCMP=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZ4HC_COMPRESS=y
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_ACER_A500_EC is not set
+# CONFIG_MFD_NVEC is not set
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPILIB=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+# CONFIG_NEON is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_TEGRA=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_TEGRA=y
+CONFIG_PINCTRL_TEGRA20=y
+CONFIG_PINCTRL_TEGRA_XUSB=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL353_SMC=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_TEGRA=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SND=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+# CONFIG_SND_HDA_TEGRA is not set
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_PCI is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+# CONFIG_SND_PROC_FS is not set
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_TEGRA=y
+# CONFIG_SND_SOC_TEGRA186_ASRC is not set
+# CONFIG_SND_SOC_TEGRA186_DSPK is not set
+CONFIG_SND_SOC_TEGRA20_AC97=y
+CONFIG_SND_SOC_TEGRA20_DAS=y
+CONFIG_SND_SOC_TEGRA20_I2S=y
+CONFIG_SND_SOC_TEGRA20_SPDIF=y
+# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set
+# CONFIG_SND_SOC_TEGRA210_ADX is not set
+# CONFIG_SND_SOC_TEGRA210_AHUB is not set
+# CONFIG_SND_SOC_TEGRA210_AMX is not set
+# CONFIG_SND_SOC_TEGRA210_DMIC is not set
+# CONFIG_SND_SOC_TEGRA210_I2S is not set
+# CONFIG_SND_SOC_TEGRA210_MIXER is not set
+# CONFIG_SND_SOC_TEGRA210_MVC is not set
+# CONFIG_SND_SOC_TEGRA210_OPE is not set
+# CONFIG_SND_SOC_TEGRA210_SFC is not set
+# CONFIG_SND_SOC_TEGRA30_AHUB is not set
+# CONFIG_SND_SOC_TEGRA30_I2S is not set
+# CONFIG_SND_SOC_TEGRA_ALC5632 is not set
+# CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD is not set
+CONFIG_SND_SOC_TEGRA_MACHINE_DRV=y
+# CONFIG_SND_SOC_TEGRA_MAX98088 is not set
+# CONFIG_SND_SOC_TEGRA_MAX98090 is not set
+# CONFIG_SND_SOC_TEGRA_RT5631 is not set
+# CONFIG_SND_SOC_TEGRA_RT5640 is not set
+# CONFIG_SND_SOC_TEGRA_RT5677 is not set
+# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set
+CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+# CONFIG_SND_SOC_TEGRA_WM8753 is not set
+# CONFIG_SND_SOC_TEGRA_WM8903 is not set
+# CONFIG_SND_SOC_TEGRA_WM9712 is not set
+CONFIG_SND_SOC_TLV320AIC23=y
+CONFIG_SND_SOC_TLV320AIC23_I2C=y
+# CONFIG_SND_USB is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y
+CONFIG_SOC_TEGRA_FLOWCTRL=y
+CONFIG_SOC_TEGRA_FUSE=y
+CONFIG_SOC_TEGRA_PMC=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_TEGRA114 is not set
+CONFIG_SPI_TEGRA20_SFLASH=y
+CONFIG_SPI_TEGRA20_SLINK=y
+# CONFIG_SPI_TEGRA210_QUAD is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEGRA186_TIMER is not set
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_TEGRA20_EMC=y
+# CONFIG_TEGRA210_ADMA is not set
+# CONFIG_TEGRA_ACONNECT is not set
+CONFIG_TEGRA_AHB=y
+CONFIG_TEGRA_GMI=y
+CONFIG_TEGRA_HOST1X=y
+CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y
+CONFIG_TEGRA_HOST1X_FIREWALL=y
+CONFIG_TEGRA_IOMMU_GART=y
+# CONFIG_TEGRA_IOMMU_SMMU is not set
+# CONFIG_TEGRA_IVC is not set
+CONFIG_TEGRA_MC=y
+CONFIG_TEGRA_SOCTHERM=y
+CONFIG_TEGRA_TIMER=y
+CONFIG_TEGRA_WATCHDOG=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_TEGRA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_TEGRA_PHY=y
+# CONFIG_USB_TEGRA_XUDC is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# CONFIG_USB_XHCI_TEGRA is not set
+CONFIG_USE_OF=y
+CONFIG_V4L2_H264=y
+CONFIG_V4L2_MEM2MEM_DEV=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_DMA_SG=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_V4L2=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_TEGRA_VDE=y
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/tegra/image/Makefile b/target/linux/tegra/image/Makefile
index 82394f4ab6..7103b6d36e 100644
--- a/target/linux/tegra/image/Makefile
+++ b/target/linux/tegra/image/Makefile
@@ -10,18 +10,19 @@ define Build/tegra-sdcard
 	mkdir -p $@.boot
 	$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot
 	$(if $(DEVICE_DTS),\
-		$(foreach dtb,$(DEVICE_DTS),$(CP) $(DTS_DIR)/$(dtb).dtb $@.boot), \
-		$(CP) $(DTS_DIR)/*.dtb $@.boot)
+		$(foreach dtb,$(DEVICE_DTS),$(CP) $(DEVICE_DTS_DIR)/$(dtb).dtb $@.boot), \
+		$(CP) $(DEVICE_DTS_DIR)/*.dtb $@.boot)
 	mkimage -A arm -O linux -T script -C none -a 0 -e 0 \
 		-n '$(DEVICE_TITLE) OpenWrt bootscript' \
 		-d $(BOOT_SCRIPT) \
 		$@.boot/boot.scr
+	$(CP) $@ $@.rootfs
 
 	SIGNATURE="$(IMG_PART_SIGNATURE)" \
 	$(SCRIPT_DIR)/gen_image_generic.sh \
 		$@ \
 		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
-		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $@.rootfs \
 		2048
 
 	$(if $(UBOOT),dd if=$(STAGING_DIR_IMAGE)/$(UBOOT).img of=$@ bs=512 skip=1 seek=1 conv=notrunc)
@@ -31,8 +32,13 @@ DEVICE_VARS += BOOT_SCRIPT UBOOT
 
 define Device/Default
   BOOT_SCRIPT := generic-bootscript
+ifeq ($(KERNEL),6.6)
+  DEVICE_DTS_DIR := $$(DTS_DIR)/nvidia
+else
+  DEVICE_DTS_DIR := $$(DTS_DIR)
+endif
   IMAGES := sdcard.img.gz
-  IMAGE/sdcard.img.gz := tegra-sdcard | gzip | append-metadata
+  IMAGE/sdcard.img.gz := append-rootfs | pad-extra 128k | tegra-sdcard | gzip | append-metadata
   KERNEL_NAME := zImage
   KERNEL := kernel-bin
   PROFILES := Default
@@ -42,8 +48,8 @@ define Device/compulab_trimslice
   DEVICE_VENDOR := CompuLab
   DEVICE_MODEL := TrimSlice
   DEVICE_DTS := tegra20-trimslice
-  DEVICE_PACKAGES := kmod-r8169 kmod-rt2800-usb kmod-rtc-em3027 \
-	kmod-usb-storage wpad-basic-mbedtls
+  DEVICE_PACKAGES := kmod-leds-gpio kmod-r8169 kmod-rt2800-usb \
+	kmod-rtc-em3027 kmod-usb-hid kmod-usb-storage wpad-basic-mbedtls
   UBOOT := trimslice-mmc
 endef
 TARGET_DEVICES += compulab_trimslice
diff --git a/target/linux/tegra/image/generic-bootscript b/target/linux/tegra/image/generic-bootscript
index 0e7816490d..5d4620c4d2 100644
--- a/target/linux/tegra/image/generic-bootscript
+++ b/target/linux/tegra/image/generic-bootscript
@@ -1,6 +1,6 @@
 part uuid ${devtype} ${devnum}:2 ptuuid
 
-setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait console=ttyS0,115200 console=tty0"
+setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait"
 
 load ${devtype} ${devnum}:${bootpart} ${kernel_addr_r} zImage
 load ${devtype} ${devnum}:${bootpart} ${fdt_addr_r} ${soc}-${board}.dtb
diff --git a/target/linux/tegra/patches-6.6/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch b/target/linux/tegra/patches-6.6/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch
new file mode 100644
index 0000000000..9ec7f8b839
--- /dev/null
+++ b/target/linux/tegra/patches-6.6/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch
@@ -0,0 +1,46 @@
+--- a/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts
++++ b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts
+@@ -201,16 +201,17 @@
+ 			conf_ata {
+ 				nvidia,pins = "ata", "atc", "atd", "ate",
+ 					"crtp", "dap2", "dap3", "dap4", "dta",
+-					"dtb", "dtc", "dtd", "dte", "gmb",
+-					"gme", "i2cp", "pta", "slxc", "slxd",
+-					"spdi", "spdo", "uda";
++					"dtb", "dtc", "dtd", "gmb", "gme",
++					"i2cp", "pta", "slxc", "slxd", "spdi",
++					"spdo", "uda";
+ 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ 			};
+ 			conf_atb {
+ 				nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
+-					"gma", "gmc", "gmd", "gpu", "gpu7",
+-					"gpv", "sdio1", "slxa", "slxk", "uac";
++					"dte", "gma", "gmc", "gmd", "gpu",
++					"gpu7", "gpv", "sdio1", "slxa", "slxk",
++					"uac";
+ 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ 			};
+@@ -408,6 +409,20 @@
+ 		};
+ 	};
+ 
++	gpio-leds {
++		compatible = "gpio-leds";
++
++		ds2 {
++			label = "trimslice:green:right";
++			gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>;
++		};
++
++		ds3 {
++			label = "trimslice:green:left";
++			gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;
++		};
++	};
++
+ 	poweroff {
+ 		compatible = "gpio-poweroff";
+ 		gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
diff --git a/target/linux/x86/64/config-6.1 b/target/linux/x86/64/config-6.1
deleted file mode 100644
index 3767fd4b9b..0000000000
--- a/target/linux/x86/64/config-6.1
+++ /dev/null
@@ -1,607 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPPC_LIB=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_FPDT is not set
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ACPI_LPIT=y
-CONFIG_ACPI_PCC=y
-# CONFIG_ACPI_PCI_SLOT is not set
-# CONFIG_ACPI_PFRUT is not set
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_TAD is not set
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ACRN_GUEST is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_AMD64 is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_HSMP is not set
-CONFIG_AMD_IOMMU=y
-CONFIG_AMD_IOMMU_V2=y
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-# CONFIG_AMD_PTDMA is not set
-# CONFIG_AMD_SFH_HID is not set
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ARCH_MMAP_RND_BITS=28
-CONFIG_ARCH_MMAP_RND_BITS_MAX=32
-CONFIG_ARCH_MMAP_RND_BITS_MIN=28
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ASUS_WMI is not set
-CONFIG_AUDIT_ARCH=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
-CONFIG_BTT=y
-CONFIG_CDROM=y
-CONFIG_CONNECTOR=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_IBPB_ENTRY=y
-CONFIG_CPU_IBRS_ENTRY=y
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SRSO=y
-CONFIG_CPU_UNRET_ENTRY=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_AES_NI_INTEL=y
-# CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 is not set
-CONFIG_CRYPTO_BLAKE2S_X86=y
-# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
-# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
-CONFIG_CRYPTO_CRCT10DIF=y
-# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
-CONFIG_CRYPTO_LRW=y
-# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
-# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
-# CONFIG_CRYPTO_POLYVAL_CLMUL_NI is not set
-# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
-# CONFIG_CRYPTO_SHA1_SSSE3 is not set
-# CONFIG_CRYPTO_SHA256_SSSE3 is not set
-# CONFIG_CRYPTO_SHA512_SSSE3 is not set
-CONFIG_CRYPTO_SIMD=y
-# CONFIG_CRYPTO_SM3_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set
-CONFIG_CRYPTO_XTS=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_HYPERV is not set
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_GVT=y
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-# CONFIG_EFI_MIXED is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_EFI_RCI2_TABLE is not set
-CONFIG_EFI_RUNTIME_MAP=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-# CONFIG_EFI_SECRET is not set
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_VARS is not set
-CONFIG_FAILOVER=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_EFI=y
-CONFIG_FB_HYPERV=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FB_TILEBLITTING=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FUSION_SAS=y
-CONFIG_FW_CACHE=y
-CONFIG_GART_IOMMU=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CPU=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_PENDING_IRQ=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_ICH=y
-CONFIG_GPIO_SCH=y
-CONFIG_HALTPOLL_CPUIDLE=y
-CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
-CONFIG_HDMI=y
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_HYPERV_MOUSE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HOTPLUG_SMT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_HYPERV=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_HYPERV_BALLOON=y
-CONFIG_HYPERV_IOMMU=y
-CONFIG_HYPERV_KEYBOARD=y
-CONFIG_HYPERV_NET=y
-CONFIG_HYPERV_STORAGE=y
-# CONFIG_HYPERV_TESTING is not set
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=y
-# CONFIG_HYPERV_VSOCKETS is not set
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_IA32_EMULATION is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IDXD is not set
-# CONFIG_INTEL_IDXD_COMPAT is not set
-CONFIG_INTEL_IOMMU=y
-# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
-CONFIG_INTEL_IOMMU_FLOPPY_WA=y
-CONFIG_INTEL_IOMMU_PERF_EVENTS=y
-# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
-# CONFIG_INTEL_IOMMU_SVM is not set
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-CONFIG_INTEL_PCH_THERMAL=y
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
-CONFIG_INTEL_SOC_DTS_THERMAL=y
-# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set
-CONFIG_INTEL_TDX_GUEST=y
-# CONFIG_INTEL_TURBO_MAX_3 is not set
-# CONFIG_INTEL_TXT is not set
-# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUG is not set
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_REMAP=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
-CONFIG_KCMP=y
-CONFIG_KVM_GUEST=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
-CONFIG_LEGACY_VSYSCALL_NONE=y
-# CONFIG_LEGACY_VSYSCALL_XONLY is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_LIBNVDIMM=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LPC_ICH=y
-CONFIG_LPC_SCH=y
-CONFIG_MAILBOX=y
-# CONFIG_MAXSMP is not set
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMREGION=y
-# CONFIG_MERAKI_MX100 is not set
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_INTEL_LPSS_ACPI is not set
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=y
-# CONFIG_MMC_SDHCI_PLTFM is not set
-# CONFIG_MMC_WBSD is not set
-CONFIG_MMU_NOTIFIER=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPSC is not set
-# CONFIG_MSI_WMI is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MXM_WMI is not set
-CONFIG_ND_BLK=y
-CONFIG_ND_BTT=y
-CONFIG_ND_CLAIM=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-# CONFIG_NITRO_ENCLAVES is not set
-CONFIG_NR_CPUS=512
-CONFIG_NR_CPUS_DEFAULT=64
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=512
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_NVME_CORE=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_MULTIPATH=y
-CONFIG_OUTPUT_FORMAT="elf64-x86-64"
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_PARAVIRT=y
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_PARAVIRT_DEBUG is not set
-CONFIG_PARAVIRT_SPINLOCKS=y
-CONFIG_PARAVIRT_XXL=y
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-CONFIG_PCC=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_HYPERV=y
-CONFIG_PCI_HYPERV_INTERFACE=y
-# CONFIG_PCI_MMCONFIG is not set
-CONFIG_PCI_XEN=y
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ALDERLAKE=y
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_BROXTON=y
-CONFIG_PINCTRL_CANNONLAKE=y
-CONFIG_PINCTRL_CHERRYVIEW=y
-CONFIG_PINCTRL_DENVERTON=y
-CONFIG_PINCTRL_ELKHARTLAKE=y
-CONFIG_PINCTRL_EMMITSBURG=y
-CONFIG_PINCTRL_GEMINILAKE=y
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_JASPERLAKE=y
-CONFIG_PINCTRL_LAKEFIELD=y
-CONFIG_PINCTRL_LEWISBURG=y
-CONFIG_PINCTRL_LYNXPOINT=y
-CONFIG_PINCTRL_METEORLAKE=y
-CONFIG_PINCTRL_SUNRISEPOINT=y
-CONFIG_PINCTRL_TIGERLAKE=y
-CONFIG_PM=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_PPS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_KVM=y
-CONFIG_PTP_1588_CLOCK_VMW=y
-CONFIG_PVH=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_VIRTIO=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_CORETEMP=y
-CONFIG_SENSORS_FAM15H_POWER=y
-CONFIG_SENSORS_I5500=y
-CONFIG_SENSORS_K8TEMP=y
-CONFIG_SENSORS_K10TEMP=y
-CONFIG_SENSORS_VIA_CPUTEMP=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-CONFIG_SLS=y
-CONFIG_SMP=y
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-# CONFIG_SPARSEMEM_VMEMMAP is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_STACK_VALIDATION=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWIOTLB_XEN=y
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UCS2_STRING=y
-# CONFIG_UNWINDER_ORC is not set
-CONFIG_USB_STORAGE=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-CONFIG_VIRTIO_IOMMU=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-# CONFIG_VIRTIO_PMEM is not set
-# CONFIG_VIRTIO_VSOCKETS is not set
-CONFIG_VIRTIO_VSOCKETS_COMMON=y
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMAP_PFN=y
-CONFIG_VMAP_STACK=y
-# CONFIG_VMD is not set
-CONFIG_VMGENID=y
-CONFIG_VMWARE_BALLOON=y
-CONFIG_VMWARE_PVSCSI=y
-CONFIG_VMWARE_VMCI=y
-CONFIG_VMWARE_VMCI_VSOCKETS=y
-CONFIG_VMXNET3=y
-CONFIG_VSOCKETS=y
-CONFIG_VSOCKETS_LOOPBACK=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-# CONFIG_X86_5LEVEL is not set
-CONFIG_X86_64=y
-CONFIG_X86_64_SMP=y
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_AMD_FREQ_SENSITIVITY=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_X86_AMD_PSTATE=y
-# CONFIG_X86_AMD_PSTATE_UT is not set
-CONFIG_X86_CPUID=y
-CONFIG_X86_DIRECT_GBPAGES=y
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-CONFIG_X86_INTEL_LPSS=y
-# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
-CONFIG_X86_INTEL_PSTATE=y
-# CONFIG_X86_KERNEL_IBT is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=64
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PKG_TEMP_THERMAL=y
-# CONFIG_X86_PMEM_LEGACY is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-# CONFIG_X86_VSYSCALL_EMULATION is not set
-CONFIG_X86_X2APIC=y
-# CONFIG_X86_X32 is not set
-# CONFIG_X86_X32_ABI is not set
-CONFIG_XEN=y
-CONFIG_XENFS=y
-CONFIG_XEN_512GB=y
-CONFIG_XEN_ACPI=y
-CONFIG_XEN_ACPI_PROCESSOR=y
-CONFIG_XEN_AUTO_XLATE=y
-# CONFIG_XEN_BACKEND is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_BLKDEV_FRONTEND=y
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_DEBUG_FS=y
-CONFIG_XEN_DEV_EVTCHN=y
-CONFIG_XEN_DOM0=y
-CONFIG_XEN_EFI=y
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_XEN_GNTDEV=y
-CONFIG_XEN_GRANT_DEV_ALLOC=y
-CONFIG_XEN_HAVE_PVMMU=y
-CONFIG_XEN_HAVE_VPMU=y
-# CONFIG_XEN_MCE_LOG is not set
-CONFIG_XEN_NETDEV_FRONTEND=y
-CONFIG_XEN_PCIDEV_FRONTEND=y
-CONFIG_XEN_PRIVCMD=y
-CONFIG_XEN_PV=y
-CONFIG_XEN_PVH=y
-CONFIG_XEN_PVHVM=y
-CONFIG_XEN_PVHVM_GUEST=y
-CONFIG_XEN_PVHVM_SMP=y
-CONFIG_XEN_PV_DOM0=y
-CONFIG_XEN_PV_MSR_SAFE=y
-CONFIG_XEN_PV_SMP=y
-CONFIG_XEN_SAVE_RESTORE=y
-CONFIG_XEN_SCSI_FRONTEND=y
-CONFIG_XEN_SYMS=y
-CONFIG_XEN_SYS_HYPERVISOR=y
-CONFIG_XEN_VIRTIO=y
-# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
-CONFIG_XEN_WDT=y
-CONFIG_XEN_XENBUS_FRONTEND=y
-# CONFIG_XIAOMI_WMI is not set
-CONFIG_XPS=y
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZONE_DMA32=y
diff --git a/target/linux/x86/64/config-6.6 b/target/linux/x86/64/config-6.6
index ce4eb644db..8533d57532 100644
--- a/target/linux/x86/64/config-6.6
+++ b/target/linux/x86/64/config-6.6
@@ -214,6 +214,7 @@ CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 CONFIG_FB_CORE=y
 CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
 CONFIG_FB_EFI=y
 CONFIG_FB_HYPERV=y
 CONFIG_FB_IOMEM_HELPERS=y
diff --git a/target/linux/x86/Makefile b/target/linux/x86/Makefile
index b4ac2a5ec8..f5f39d8421 100644
--- a/target/linux/x86/Makefile
+++ b/target/linux/x86/Makefile
@@ -10,8 +10,7 @@ BOARDNAME:=x86
 FEATURES:=squashfs ext4 vdi vmdk vhdx pcmcia targz fpu boot-part rootfs-part
 SUBTARGETS:=generic legacy geode 64
 
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
 
 KERNELNAME:=bzImage
 
diff --git a/target/linux/x86/config-6.1 b/target/linux/x86/config-6.1
deleted file mode 100644
index 20feecafd0..0000000000
--- a/target/linux/x86/config-6.1
+++ /dev/null
@@ -1,466 +0,0 @@
-# CONFIG_60XX_WDT is not set
-# CONFIG_64BIT is not set
-# CONFIG_ACPI is not set
-# CONFIG_ACQUIRE_WDT is not set
-# CONFIG_ADVANTECH_WDT is not set
-# CONFIG_ALIM1535_WDT is not set
-# CONFIG_ALIX is not set
-CONFIG_AMD_NB=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_NR_GPIO=512
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPLIT_ARG64=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ATA=y
-CONFIG_ATA_GENERIC=y
-CONFIG_ATA_PIIX=y
-# CONFIG_BARCO_P50_GPIO is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32=y
-CONFIG_COMPAT_32BIT_TIME=y
-# CONFIG_COMPAT_VDSO is not set
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPU5_WDT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_CYRIX_32=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_TRANSMETA_32=y
-CONFIG_CPU_SUP_UMC_32=y
-CONFIG_CPU_SUP_VORTEX_32=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32_PCLMUL is not set
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
-# CONFIG_CX_ECAT is not set
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_DEBUG_ENTRY is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_MISC=y
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_DMI_SYSFS=y
-# CONFIG_DM_AUDIT is not set
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DYNAMIC_SIGFRAME=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_DBGP is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EDD is not set
-CONFIG_EFI_HANDOVER_PROTOCOL=y
-# CONFIG_EISA is not set
-# CONFIG_EUROTECH_WDT is not set
-# CONFIG_EXAR_WDT is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-# CONFIG_F71808E_WDT is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FUSION=y
-# CONFIG_FUSION_CTL is not set
-# CONFIG_FUSION_LOGGING is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_SPI=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-# CONFIG_GDS_FORCE_MITIGATION is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-# CONFIG_GEOS is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHMEM4G=y
-# CONFIG_HIGHMEM64G is not set
-CONFIG_HIGHPTE=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_HPET_TIMER=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_GEODE=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HYPERVISOR_GUEST is not set
-CONFIG_HZ_PERIODIC=y
-CONFIG_I8253_LOCK=y
-CONFIG_IA32_FEAT_CTL=y
-# CONFIG_IB700_WDT is not set
-# CONFIG_IBMASR is not set
-# CONFIG_IBM_RTL is not set
-# CONFIG_IE6XX_WDT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_VIVALDIFMAP=y
-CONFIG_INSTRUCTION_DECODER=y
-# CONFIG_INTEL_HFI_THERMAL is not set
-# CONFIG_INTEL_LDMA is not set
-# CONFIG_INTEL_PCH_THERMAL is not set
-# CONFIG_INTEL_POWERCLAMP is not set
-# CONFIG_INTEL_SCU_PCI is not set
-# CONFIG_INTEL_TCC_COOLING is not set
-# CONFIG_INTEL_VSEC is not set
-# CONFIG_IOSF_MBI is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISA is not set
-CONFIG_ISA_DMA_API=y
-# CONFIG_IT8712F_WDT is not set
-# CONFIG_IT87_WDT is not set
-# CONFIG_ITCO_WDT is not set
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-# CONFIG_M486 is not set
-# CONFIG_M486SX is not set
-# CONFIG_M586 is not set
-# CONFIG_M586MMX is not set
-# CONFIG_M586TSC is not set
-CONFIG_M686=y
-# CONFIG_MACHZ_WDT is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MELAN is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_INTEL_LPSS_PCI is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_AMD=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_LATE_LOADING=y
-CONFIG_MIGRATION=y
-CONFIG_MITIGATION_RFDS=y
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-CONFIG_MMU_GATHER_MERGE_VMAS=y
-# CONFIG_MODIFY_LDT_SYSCALL is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MTD is not set
-CONFIG_MTRR=y
-# CONFIG_MTRR_SANITIZER is not set
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MWINCHIPC6 is not set
-CONFIG_NAMESPACES=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET5501 is not set
-# CONFIG_NET_NS is not set
-CONFIG_NLS=y
-# CONFIG_NOHIGHMEM is not set
-CONFIG_NR_CPUS=1
-CONFIG_NR_CPUS_DEFAULT=1
-CONFIG_NR_CPUS_RANGE_BEGIN=1
-CONFIG_NR_CPUS_RANGE_END=1
-# CONFIG_NSC_GPIO is not set
-CONFIG_NVRAM=y
-# CONFIG_OF is not set
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-# CONFIG_OLPC is not set
-CONFIG_OUTPUT_FORMAT="elf32-i386"
-# CONFIG_P2SB is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PC104=y
-# CONFIG_PC8736x_GPIO is not set
-# CONFIG_PC87413_WDT is not set
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCI=y
-CONFIG_PCI_ATS=y
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GOANY=y
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GODIRECT is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-CONFIG_PCI_IOV=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_EVENTS=y
-# CONFIG_PERF_EVENTS_AMD_BRS is not set
-# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
-CONFIG_PERF_EVENTS_INTEL_CSTATE=y
-CONFIG_PERF_EVENTS_INTEL_RAPL=y
-CONFIG_PERF_EVENTS_INTEL_UNCORE=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYSICAL_ALIGN=0x100000
-CONFIG_PHYSICAL_START=0x1000000
-# CONFIG_PHY_INTEL_LGM_EMMC is not set
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-# CONFIG_PROCESSOR_SELECT is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RETHUNK=y
-CONFIG_RETPOLINE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SATA_HOST=y
-# CONFIG_SBC7240_WDT is not set
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC_EPX_C3_WATCHDOG is not set
-# CONFIG_SC1200_WDT is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCx200=y
-CONFIG_SCx200HR_TIMER=y
-# CONFIG_SCx200_GPIO is not set
-# CONFIG_SCx200_WDT is not set
-CONFIG_SERIAL_8250_PCI=y
-# CONFIG_SERIAL_LANTIQ is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-# CONFIG_SIEMENS_SIMATIC_IPC is not set
-# CONFIG_SMSC37B787_WDT is not set
-# CONFIG_SMSC_SCH311X_WDT is not set
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SPECTRE_BHI_AUTO is not set
-# CONFIG_SPECTRE_BHI_OFF is not set
-CONFIG_SPECTRE_BHI_ON=y
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_SRCU=y
-# CONFIG_STATIC_CALL_SELFTEST is not set
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-# CONFIG_TELCLOCK is not set
-# CONFIG_TEST_FPU is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-# CONFIG_TOSHIBA is not set
-# CONFIG_TQMX86_WDT is not set
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_UNWINDER_FRAME_POINTER=y
-# CONFIG_UNWINDER_GUESS is not set
-CONFIG_UP_LATE_INIT=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_PCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-# CONFIG_USER_NS is not set
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VIA_WDT is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WAFER_WDT is not set
-# CONFIG_WINMATE_FM07_KEYS is not set
-CONFIG_X86=y
-CONFIG_X86_32=y
-# CONFIG_X86_32_IRIS is not set
-# CONFIG_X86_ANCIENT_MCE is not set
-# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
-CONFIG_X86_CMOV=y
-CONFIG_X86_CMPXCHG64=y
-# CONFIG_X86_CPA_STATISTICS is not set
-# CONFIG_X86_CPUFREQ_NFORCE2 is not set
-# CONFIG_X86_CPUID is not set
-# CONFIG_X86_CPU_RESCTRL is not set
-CONFIG_X86_DEBUGCTLMSR=y
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_X86_DECODER_SELFTEST is not set
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_GENERIC=y
-# CONFIG_X86_GX_SUSPMOD is not set
-# CONFIG_X86_INTEL_PSTATE is not set
-# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
-CONFIG_X86_INTEL_TSX_MODE_OFF=y
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_IOPL_IOPERM=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_L1_CACHE_SHIFT=6
-# CONFIG_X86_LEGACY_VM86 is not set
-CONFIG_X86_LOCAL_APIC=y
-# CONFIG_X86_LONGRUN is not set
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-CONFIG_X86_MCE_AMD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_THRESHOLD=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=6
-CONFIG_X86_MPPARSE=y
-CONFIG_X86_MSR=y
-# CONFIG_X86_P4_CLOCKMOD is not set
-CONFIG_X86_PAT=y
-CONFIG_X86_PLATFORM_DEVICES=y
-# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
-# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
-# CONFIG_X86_POWERNOW_K6 is not set
-# CONFIG_X86_POWERNOW_K7 is not set
-# CONFIG_X86_REBOOTFIXUPS is not set
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_SPEEDSTEP_ICH is not set
-# CONFIG_X86_SPEEDSTEP_SMI is not set
-CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_X86_THERMAL_VECTOR=y
-CONFIG_X86_TSC=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_UP_APIC=y
-CONFIG_X86_UP_IOAPIC=y
-CONFIG_X86_USE_PPRO_CHECKSUM=y
-CONFIG_X86_VERBOSE_BOOTUP=y
-CONFIG_X86_VMX_FEATURE_NAMES=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/x86/config-6.6 b/target/linux/x86/config-6.6
index 7f00ffdb78..d71e95f676 100644
--- a/target/linux/x86/config-6.6
+++ b/target/linux/x86/config-6.6
@@ -61,6 +61,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_IDLE=y
 CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_MITIGATIONS=y
 CONFIG_CPU_SUP_AMD=y
 CONFIG_CPU_SUP_CENTAUR=y
 CONFIG_CPU_SUP_CYRIX_32=y
@@ -361,7 +362,6 @@ CONFIG_SG_POOL=y
 CONFIG_SOFTIRQ_ON_OWN_STACK=y
 CONFIG_SPARSEMEM_STATIC=y
 CONFIG_SPARSE_IRQ=y
-CONFIG_SPECULATION_MITIGATIONS=y
 CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 # CONFIG_STATIC_CALL_SELFTEST is not set
 # CONFIG_STRICT_SIGALTSTACK_SIZE is not set
diff --git a/target/linux/x86/generic/config-6.1 b/target/linux/x86/generic/config-6.1
deleted file mode 100644
index b7c79de273..0000000000
--- a/target/linux/x86/generic/config-6.1
+++ /dev/null
@@ -1,509 +0,0 @@
-# CONFIG_3C515 is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-# CONFIG_ACPI_FAN is not set
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_TAD=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_AMD is not set
-# CONFIG_AGP_AMD64 is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_NVIDIA is not set
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_SWORKS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-# CONFIG_APM is not set
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ASUS_WMI is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
-CONFIG_BTT=y
-CONFIG_CDROM=y
-CONFIG_CONNECTOR=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-# CONFIG_CS89x0_ISA is not set
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_HYPERV is not set
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_EFI_RCI2_TABLE is not set
-CONFIG_EFI_RUNTIME_MAP=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_VARS is not set
-# CONFIG_EL3 is not set
-CONFIG_FAILOVER=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_EFI=y
-CONFIG_FB_HYPERV=y
-# CONFIG_FB_I810 is not set
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FW_CACHE=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GUP_GET_PTE_LOW_HIGH=y
-CONFIG_HALTPOLL_CPUIDLE=y
-CONFIG_HDMI=y
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_HYPERV_MOUSE=y
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HIGHMEM64G=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_COMPAQ is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_IBM is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HOTPLUG_SMT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_HYPERV=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_HYPERV_BALLOON=y
-CONFIG_HYPERV_KEYBOARD=y
-CONFIG_HYPERV_NET=y
-CONFIG_HYPERV_STORAGE=y
-# CONFIG_HYPERV_TESTING is not set
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-CONFIG_INTEL_PCH_THERMAL=y
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
-CONFIG_INTEL_SOC_DTS_THERMAL=y
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_ISA=y
-CONFIG_ISAPNP=y
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
-CONFIG_KCMP=y
-CONFIG_KVM=y
-CONFIG_KVM_AMD=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_GUEST=y
-CONFIG_KVM_INTEL=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_VFIO=y
-# CONFIG_KVM_XEN is not set
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-# CONFIG_LANCE is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_LIBNVDIMM=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMREGION=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_INTEL_LPSS=y
-CONFIG_MFD_INTEL_LPSS_ACPI=y
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-# CONFIG_MIXCOMWD is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=y
-# CONFIG_MMC_SDHCI_PLTFM is not set
-# CONFIG_MMC_WBSD is not set
-CONFIG_MMU_NOTIFIER=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-# CONFIG_MOUSE_PS2_BYD is not set
-# CONFIG_MOUSE_PS2_CYPRESS is not set
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-CONFIG_MPENTIUM4=y
-# CONFIG_MSI_WMI is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MXM_WMI is not set
-CONFIG_ND_BLK=y
-CONFIG_ND_BTT=y
-CONFIG_ND_CLAIM=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NO_HZ=y
-CONFIG_NR_CPUS=4
-CONFIG_NR_CPUS_DEFAULT=8
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=8
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_PARAVIRT=y
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_PARAVIRT_DEBUG is not set
-CONFIG_PARAVIRT_SPINLOCKS=y
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_SC1200=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_MMCONFIG=y
-CONFIG_PCI_XEN=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ALDERLAKE=y
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_BROXTON=y
-CONFIG_PINCTRL_CANNONLAKE=y
-CONFIG_PINCTRL_CHERRYVIEW=y
-CONFIG_PINCTRL_DENVERTON=y
-CONFIG_PINCTRL_ELKHARTLAKE=y
-CONFIG_PINCTRL_EMMITSBURG=y
-CONFIG_PINCTRL_GEMINILAKE=y
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_JASPERLAKE=y
-CONFIG_PINCTRL_LAKEFIELD=y
-CONFIG_PINCTRL_LEWISBURG=y
-CONFIG_PINCTRL_LYNXPOINT=y
-CONFIG_PINCTRL_METEORLAKE=y
-CONFIG_PINCTRL_SUNRISEPOINT=y
-CONFIG_PINCTRL_TIGERLAKE=y
-CONFIG_PM=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_KVM=y
-CONFIG_PTP_1588_CLOCK_VMW=y
-CONFIG_PVH=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_VIA=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-CONFIG_SCSI_VIRTIO=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_CORETEMP=y
-CONFIG_SENSORS_FAM15H_POWER=y
-CONFIG_SENSORS_I5500=y
-CONFIG_SENSORS_K8TEMP=y
-CONFIG_SENSORS_K10TEMP=y
-CONFIG_SENSORS_VIA_CPUTEMP=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-CONFIG_SMP=y
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UCS2_STRING=y
-CONFIG_USB_STORAGE=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_VHOST=y
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_NET=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-# CONFIG_VIRTIO_PMEM is not set
-CONFIG_VIRTUALIZATION=y
-CONFIG_VMAP_PFN=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-CONFIG_X86_32_SMP=y
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_AMD_FREQ_SENSITIVITY=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_X86_AMD_PSTATE=y
-# CONFIG_X86_AMD_PSTATE_UT is not set
-# CONFIG_X86_BIGSMP is not set
-CONFIG_X86_CPUID=y
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-CONFIG_X86_INTEL_LPSS=y
-CONFIG_X86_INTEL_PSTATE=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=7
-CONFIG_X86_L1_CACHE_SHIFT=7
-# CONFIG_X86_LONGHAUL is not set
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_X86_PAE=y
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PKG_TEMP_THERMAL=y
-# CONFIG_X86_PMEM_LEGACY is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-CONFIG_XEN=y
-CONFIG_XENFS=y
-CONFIG_XEN_ACPI=y
-CONFIG_XEN_AUTO_XLATE=y
-# CONFIG_XEN_BACKEND is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_BLKDEV_FRONTEND=y
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_DEBUG_FS=y
-CONFIG_XEN_DEV_EVTCHN=y
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_XEN_GNTDEV=y
-CONFIG_XEN_GRANT_DEV_ALLOC=y
-CONFIG_XEN_NETDEV_FRONTEND=y
-CONFIG_XEN_PRIVCMD=y
-CONFIG_XEN_PVH=y
-CONFIG_XEN_PVHVM=y
-CONFIG_XEN_PVHVM_GUEST=y
-CONFIG_XEN_PVHVM_SMP=y
-CONFIG_XEN_SAVE_RESTORE=y
-CONFIG_XEN_SCSI_FRONTEND=y
-CONFIG_XEN_SYS_HYPERVISOR=y
-CONFIG_XEN_VIRTIO=y
-# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
-CONFIG_XEN_WDT=y
-CONFIG_XEN_XENBUS_FRONTEND=y
-# CONFIG_XIAOMI_WMI is not set
-CONFIG_XPS=y
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
diff --git a/target/linux/x86/generic/config-6.6 b/target/linux/x86/generic/config-6.6
index 698f3bbe4d..c02ec35100 100644
--- a/target/linux/x86/generic/config-6.6
+++ b/target/linux/x86/generic/config-6.6
@@ -148,6 +148,7 @@ CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 CONFIG_FB_CORE=y
 CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
 CONFIG_FB_EFI=y
 CONFIG_FB_HYPERV=y
 # CONFIG_FB_I810 is not set
diff --git a/target/linux/x86/geode/config-6.1 b/target/linux/x86/geode/config-6.1
deleted file mode 100644
index cf02d2b9b0..0000000000
--- a/target/linux/x86/geode/config-6.1
+++ /dev/null
@@ -1,176 +0,0 @@
-# CONFIG_3C515 is not set
-CONFIG_8139CP=y
-CONFIG_8139TOO=y
-CONFIG_8139TOO_8129=y
-CONFIG_8139TOO_PIO=y
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-# CONFIG_8139_OLD_RX_RESET is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-# CONFIG_ACPI_BATTERY is not set
-# CONFIG_ACPI_CMPC is not set
-# CONFIG_ACPI_CONTAINER is not set
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TINY_POWER_BUTTON is not set
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_ALIX=y
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ATA_PIIX is not set
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CS5535_CLOCK_EVENT_SRC=y
-CONFIG_CS5535_MFGPT=y
-CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
-# CONFIG_CS89x0_ISA is not set
-CONFIG_DMA_ACPI=y
-# CONFIG_EL3 is not set
-CONFIG_GEODE_WDT=y
-CONFIG_GEOS=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CS5535=y
-# CONFIG_HPET is not set
-# CONFIG_HP_ACCEL is not set
-CONFIG_HWMON=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MENLOW is not set
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-# CONFIG_INTEL_SOC_DTS_THERMAL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_ISA=y
-# CONFIG_ISAPNP is not set
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-# CONFIG_LANCE is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_CS5535=y
-# CONFIG_MFD_INTEL_LPSS_ACPI is not set
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-CONFIG_MGEODEGX1=y
-# CONFIG_MIXCOMWD is not set
-# CONFIG_MSI_WMI is not set
-# CONFIG_MXM_WMI is not set
-CONFIG_NATSEMI=y
-CONFIG_NET5501=y
-CONFIG_NSC_GPIO=y
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PATA_CS5520=y
-CONFIG_PATA_CS5530=y
-CONFIG_PATA_CS5535=y
-CONFIG_PATA_CS5536=y
-CONFIG_PATA_SC1200=y
-CONFIG_PC8736x_GPIO=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_ALDERLAKE is not set
-# CONFIG_PINCTRL_BAYTRAIL is not set
-# CONFIG_PINCTRL_BROXTON is not set
-# CONFIG_PINCTRL_CANNONLAKE is not set
-# CONFIG_PINCTRL_CHERRYVIEW is not set
-# CONFIG_PINCTRL_DENVERTON is not set
-# CONFIG_PINCTRL_ELKHARTLAKE is not set
-# CONFIG_PINCTRL_EMMITSBURG is not set
-# CONFIG_PINCTRL_GEMINILAKE is not set
-# CONFIG_PINCTRL_JASPERLAKE is not set
-# CONFIG_PINCTRL_LAKEFIELD is not set
-# CONFIG_PINCTRL_LEWISBURG is not set
-# CONFIG_PINCTRL_LYNXPOINT is not set
-# CONFIG_PINCTRL_METEORLAKE is not set
-# CONFIG_PINCTRL_SUNRISEPOINT is not set
-# CONFIG_PINCTRL_TIGERLAKE is not set
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SC1200_WDT=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-CONFIG_SCx200_ACB=y
-CONFIG_SCx200_WDT=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_LM90=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-# CONFIG_SURFACE_PLATFORMS is not set
-# CONFIG_SYSTEM76_ACPI is not set
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_VIA_RHINE=y
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-# CONFIG_X86_ACPI_CPUFREQ is not set
-CONFIG_X86_ALIGNMENT_16=y
-# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
-# CONFIG_X86_AMD_PSTATE is not set
-# CONFIG_X86_AMD_PSTATE_UT is not set
-CONFIG_X86_CPUID=y
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_INTEL_LPSS=y
-# CONFIG_X86_LONGHAUL is not set
-# CONFIG_X86_MCE is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=5
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PM_TIMER=y
-CONFIG_X86_REBOOTFIXUPS=y
-# CONFIG_XIAOMI_WMI is not set
-# CONFIG_YOGABOOK_WMI is not set
diff --git a/target/linux/x86/legacy/config-6.1 b/target/linux/x86/legacy/config-6.1
deleted file mode 100644
index efa1eabe82..0000000000
--- a/target/linux/x86/legacy/config-6.1
+++ /dev/null
@@ -1,262 +0,0 @@
-# CONFIG_3C515 is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-# CONFIG_ACPI_CONTAINER is not set
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-# CONFIG_ACPI_FAN is not set
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_AMD is not set
-# CONFIG_AGP_AMD64 is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_NVIDIA is not set
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_SWORKS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CDROM=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-# CONFIG_CS89x0_ISA is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_AMDGPU=y
-# CONFIG_DRM_AMD_DC is not set
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_RADEON=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VRAM_HELPER=y
-# CONFIG_EL3 is not set
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_I810 is not set
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_HDMI=y
-CONFIG_HID_BATTERY_STRENGTH=y
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HWMON=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-# CONFIG_INTEL_SOC_DTS_THERMAL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_ISA=y
-CONFIG_ISAPNP=y
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
-CONFIG_KCMP=y
-# CONFIG_LANCE is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_M586MMX=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_INTEL_LPSS=y
-CONFIG_MFD_INTEL_LPSS_ACPI=y
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-# CONFIG_MIXCOMWD is not set
-CONFIG_MMU_NOTIFIER=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-# CONFIG_MOUSE_PS2_BYD is not set
-# CONFIG_MOUSE_PS2_CYPRESS is not set
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MSI_WMI is not set
-# CONFIG_MXM_WMI is not set
-CONFIG_NOHIGHMEM=y
-CONFIG_NO_HZ=y
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_LEGACY=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_SC1200=y
-CONFIG_PATA_SIS=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_USB_STORAGE=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VMAP_PFN=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_ALIGNMENT_16=y
-# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
-# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
-# CONFIG_X86_AMD_PSTATE is not set
-# CONFIG_X86_AMD_PSTATE_UT is not set
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_F00F_BUG=y
-# CONFIG_X86_INTEL_LPSS is not set
-# CONFIG_X86_LONGHAUL is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=5
-# CONFIG_X86_PAE is not set
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-# CONFIG_XIAOMI_WMI is not set
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
diff --git a/target/linux/x86/legacy/config-6.6 b/target/linux/x86/legacy/config-6.6
index 402ad89472..f71747e433 100644
--- a/target/linux/x86/legacy/config-6.6
+++ b/target/linux/x86/legacy/config-6.6
@@ -109,6 +109,7 @@ CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 CONFIG_FB_CORE=y
 CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
 # CONFIG_FB_I810 is not set
 CONFIG_FB_IOMEM_HELPERS=y
 CONFIG_FB_SYSMEM_HELPERS=y
diff --git a/target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch b/target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch
deleted file mode 100644
index d4de2027ba..0000000000
--- a/target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/drivers/clocksource/timer-cs5535.c
-+++ b/drivers/clocksource/timer-cs5535.c
-@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v
- 		cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
- 				MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
- 
--	cs5535_clockevent.event_handler(&cs5535_clockevent);
-+	if (cs5535_clockevent.event_handler)
-+		cs5535_clockevent.event_handler(&cs5535_clockevent);
-+
- 	return IRQ_HANDLED;
- }
- 
diff --git a/target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch b/target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch
deleted file mode 100644
index 654bd88b7f..0000000000
--- a/target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch
+++ /dev/null
@@ -1,280 +0,0 @@
-From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001
-From: Philip Prindeville <philipp@redfish-solutions.com>
-Date: Sun, 1 Jan 2023 15:25:04 -0700
-Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver
-To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org
-Cc: Ed Wildgoose <lists@wildgooses.com>, Andres Salomon <dilinger@queued.net>, Andreas Eberlein <foodeas@aeberlein.de>, Paul Spooren <paul@spooren.de>
-
-PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA.
-It also has support for 3x LTE modems with 6x SIM slots (pairs with a
-SIM switch device). Each mpcie slot for modems has a reset GPIO
-
-To ensure that the naming is sane between APU2-6 the GPIOS are
-renamed to be modem1-reset, modem2-reset, etc. This is significant
-because the slots that can be reset change between APU2 and APU3/4
-
-GPIO for simswap is moved to the end of the list as it could be dropped
-for APU2 boards (but causes no harm to leave it in, hardware could be
-added to a future rev of the board).
-
-Structure of the GPIOs for APU5 is extremely similar to APU2-4, but
-many lines are moved around and there are simply more
-modems/resets/sim-swap lines to breakout.
-
-Also added APU6, which is essentially APU4 with a different ethernet
-interface and SFP cage on eth0.
-
-Revision history:
-
-v1: originally titled, "apu6: add apu6 variation to apu2 driver family"
-this dealt only with detecting the APUv6, which is otherwise identical
-to the v4 excepting the SFP cage on eth0.
-
-v2: at Ed's request, merged with his previous pull-request titled
-"x86: Support APU5 in PCEngines platform driver", and some cleanup
-to that changeset (including dropping the table "apu5_driver_data"
-which did not have a defined type "struct apu_driver_data"), but got
-mistitled when the Subject of that commit got accidentally dropped.
-
-v3: retitled to match Ed's previous pull-request.
-
-Cc: platform-driver-x86@vger.kernel.org
-Cc: linux-x86_64@vger.kernel.org
-Reviewed-by: Andreas Eberlein <foodeas@aeberlein.de>
-Reviewed-by: Paul Spooren <paul@spooren.de>
-Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
-Sighed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
----
- drivers/leds/leds-apu.c                |   2 +-
- drivers/platform/x86/Kconfig           |   4 +-
- drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++---
- 3 files changed, 107 insertions(+), 17 deletions(-)
-
---- a/drivers/leds/leds-apu.c
-+++ b/drivers/leds/leds-apu.c
-@@ -183,7 +183,7 @@ static int __init apu_led_init(void)
- 
- 	if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") &&
- 	      (dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) {
--		pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n");
-+		pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n");
- 		return -ENODEV;
- 	}
- 
---- a/drivers/platform/x86/Kconfig
-+++ b/drivers/platform/x86/Kconfig
-@@ -698,7 +698,7 @@ config XO1_RFKILL
- 	  laptop.
- 
- config PCENGINES_APU2
--	tristate "PC Engines APUv2/3 front button and LEDs driver"
-+	tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver"
- 	depends on INPUT && INPUT_KEYBOARD && GPIOLIB
- 	depends on LEDS_CLASS
- 	select GPIO_AMD_FCH
-@@ -706,7 +706,7 @@ config PCENGINES_APU2
- 	select LEDS_GPIO
- 	help
- 	  This driver provides support for the front button and LEDs on
--	  PC Engines APUv2/APUv3 board.
-+	  PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board.
- 
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called pcengines-apuv2.
---- a/drivers/platform/x86/pcengines-apuv2.c
-+++ b/drivers/platform/x86/pcengines-apuv2.c
-@@ -1,10 +1,12 @@
- // SPDX-License-Identifier: GPL-2.0+
- 
- /*
-- * PC-Engines APUv2/APUv3 board platform driver
-+ * PC-Engines APUv2-6 board platform driver
-  * for GPIO buttons and LEDs
-  *
-  * Copyright (C) 2018 metux IT consult
-+ * Copyright (C) 2022 Ed Wildgoose <lists@wildgooses.com>
-+ * Copyright (C) 2022 Philip Prindeville <philipp@redfish-solutions.com>
-  * Author: Enrico Weigelt <info@metux.net>
-  */
- 
-@@ -22,38 +24,70 @@
- #include <linux/platform_data/gpio/gpio-amd-fch.h>
- 
- /*
-- * NOTE: this driver only supports APUv2/3 - not APUv1, as this one
-+ * NOTE: this driver only supports APUv2-6 - not APUv1, as this one
-  * has completely different register layouts.
-  */
- 
-+/*
-+ * There are a number of APU variants, with differing features
-+ * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2
-+ * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed
-+ * However, most APU3/4 have a SIM switch which we default on to reverse
-+ * the order and keep physical SIM order matching physical modem order
-+ * APU6 is approximately the same as APU4 with different ethernet layout
-+ *
-+ * APU5 has 3x SIM sockets, all with a SIM switch
-+ * several GPIOs are shuffled (see schematic), including MODESW
-+ */
-+
- /* Register mappings */
- #define APU2_GPIO_REG_LED1		AMD_FCH_GPIO_REG_GPIO57
- #define APU2_GPIO_REG_LED2		AMD_FCH_GPIO_REG_GPIO58
- #define APU2_GPIO_REG_LED3		AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
- #define APU2_GPIO_REG_MODESW		AMD_FCH_GPIO_REG_GPIO32_GE1
- #define APU2_GPIO_REG_SIMSWAP		AMD_FCH_GPIO_REG_GPIO33_GE2
--#define APU2_GPIO_REG_MPCIE2		AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
--#define APU2_GPIO_REG_MPCIE3		AMD_FCH_GPIO_REG_GPIO51
-+#define APU2_GPIO_REG_RESETM1		AMD_FCH_GPIO_REG_GPIO51
-+#define APU2_GPIO_REG_RESETM2		AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
-+
-+#define APU5_GPIO_REG_MODESW		AMT_FCH_GPIO_REG_GEVT22
-+#define APU5_GPIO_REG_SIMSWAP1		AMD_FCH_GPIO_REG_GPIO68
-+#define APU5_GPIO_REG_SIMSWAP2		AMD_FCH_GPIO_REG_GPIO32_GE1
-+#define APU5_GPIO_REG_SIMSWAP3		AMD_FCH_GPIO_REG_GPIO33_GE2
-+#define APU5_GPIO_REG_RESETM1		AMD_FCH_GPIO_REG_GPIO51
-+#define APU5_GPIO_REG_RESETM2		AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
-+#define APU5_GPIO_REG_RESETM3		AMD_FCH_GPIO_REG_GPIO64
- 
- /* Order in which the GPIO lines are defined in the register list */
- #define APU2_GPIO_LINE_LED1		0
- #define APU2_GPIO_LINE_LED2		1
- #define APU2_GPIO_LINE_LED3		2
- #define APU2_GPIO_LINE_MODESW		3
--#define APU2_GPIO_LINE_SIMSWAP		4
--#define APU2_GPIO_LINE_MPCIE2		5
--#define APU2_GPIO_LINE_MPCIE3		6
-+#define APU2_GPIO_LINE_RESETM1		4
-+#define APU2_GPIO_LINE_RESETM2		5
-+#define APU2_GPIO_LINE_SIMSWAP		6
-+
-+#define APU5_GPIO_LINE_LED1		0
-+#define APU5_GPIO_LINE_LED2		1
-+#define APU5_GPIO_LINE_LED3		2
-+#define APU5_GPIO_LINE_MODESW		3
-+#define APU5_GPIO_LINE_RESETM1		4
-+#define APU5_GPIO_LINE_RESETM2		5
-+#define APU5_GPIO_LINE_RESETM3		6
-+#define APU5_GPIO_LINE_SIMSWAP1		7
-+#define APU5_GPIO_LINE_SIMSWAP2		8
-+#define APU5_GPIO_LINE_SIMSWAP3		9
-+
- 
--/* GPIO device */
-+/* GPIO device - APU2/3/4/6 */
- 
- static int apu2_gpio_regs[] = {
- 	[APU2_GPIO_LINE_LED1]		= APU2_GPIO_REG_LED1,
- 	[APU2_GPIO_LINE_LED2]		= APU2_GPIO_REG_LED2,
- 	[APU2_GPIO_LINE_LED3]		= APU2_GPIO_REG_LED3,
- 	[APU2_GPIO_LINE_MODESW]		= APU2_GPIO_REG_MODESW,
-+	[APU2_GPIO_LINE_RESETM1]	= APU2_GPIO_REG_RESETM1,
-+	[APU2_GPIO_LINE_RESETM2]	= APU2_GPIO_REG_RESETM2,
- 	[APU2_GPIO_LINE_SIMSWAP]	= APU2_GPIO_REG_SIMSWAP,
--	[APU2_GPIO_LINE_MPCIE2]		= APU2_GPIO_REG_MPCIE2,
--	[APU2_GPIO_LINE_MPCIE3]		= APU2_GPIO_REG_MPCIE3,
- };
- 
- static const char * const apu2_gpio_names[] = {
-@@ -61,9 +95,9 @@ static const char * const apu2_gpio_name
- 	[APU2_GPIO_LINE_LED2]		= "front-led2",
- 	[APU2_GPIO_LINE_LED3]		= "front-led3",
- 	[APU2_GPIO_LINE_MODESW]		= "front-button",
-+	[APU2_GPIO_LINE_RESETM1]	= "modem1-reset",
-+	[APU2_GPIO_LINE_RESETM2]	= "modem2-reset",
- 	[APU2_GPIO_LINE_SIMSWAP]	= "simswap",
--	[APU2_GPIO_LINE_MPCIE2]		= "mpcie2_reset",
--	[APU2_GPIO_LINE_MPCIE3]		= "mpcie3_reset",
- };
- 
- static const struct amd_fch_gpio_pdata board_apu2 = {
-@@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b
- 	.gpio_names	= apu2_gpio_names,
- };
- 
-+/* GPIO device - APU5 */
-+
-+static int apu5_gpio_regs[] = {
-+	[APU5_GPIO_LINE_LED1]		= APU2_GPIO_REG_LED1,
-+	[APU5_GPIO_LINE_LED2]		= APU2_GPIO_REG_LED2,
-+	[APU5_GPIO_LINE_LED3]		= APU2_GPIO_REG_LED3,
-+	[APU5_GPIO_LINE_MODESW]		= APU5_GPIO_REG_MODESW,
-+	[APU5_GPIO_LINE_RESETM1]	= APU5_GPIO_REG_RESETM1,
-+	[APU5_GPIO_LINE_RESETM2]	= APU5_GPIO_REG_RESETM2,
-+	[APU5_GPIO_LINE_RESETM3]	= APU5_GPIO_REG_RESETM3,
-+	[APU5_GPIO_LINE_SIMSWAP1]	= APU5_GPIO_REG_SIMSWAP1,
-+	[APU5_GPIO_LINE_SIMSWAP2]	= APU5_GPIO_REG_SIMSWAP2,
-+	[APU5_GPIO_LINE_SIMSWAP3]	= APU5_GPIO_REG_SIMSWAP3,
-+};
-+
-+static const char * const apu5_gpio_names[] = {
-+	[APU5_GPIO_LINE_LED1]		= "front-led1",
-+	[APU5_GPIO_LINE_LED2]		= "front-led2",
-+	[APU5_GPIO_LINE_LED3]		= "front-led3",
-+	[APU5_GPIO_LINE_MODESW]		= "front-button",
-+	[APU5_GPIO_LINE_RESETM1]	= "modem1-reset",
-+	[APU5_GPIO_LINE_RESETM2]	= "modem2-reset",
-+	[APU5_GPIO_LINE_RESETM3]	= "modem3-reset",
-+	[APU5_GPIO_LINE_SIMSWAP1]	= "simswap1",
-+	[APU5_GPIO_LINE_SIMSWAP2]	= "simswap2",
-+	[APU5_GPIO_LINE_SIMSWAP3]	= "simswap3",
-+};
-+
-+static const struct amd_fch_gpio_pdata board_apu5 = {
-+	.gpio_num	= ARRAY_SIZE(apu5_gpio_regs),
-+	.gpio_reg	= apu5_gpio_regs,
-+	.gpio_names	= apu5_gpio_names,
-+};
-+
- /* GPIO LEDs device */
- 
- static const struct gpio_led apu2_leds[] = {
-@@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp
- 		},
- 		.driver_data = (void *)&board_apu2,
- 	},
-+	/* APU5 w/ mainline BIOS */
-+	{
-+		.ident		= "apu5",
-+		.matches	= {
-+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
-+			DMI_MATCH(DMI_BOARD_NAME, "apu5")
-+		},
-+		.driver_data	= (void *)&board_apu5,
-+	},
-+	/* APU6 w/ mainline BIOS */
-+	{
-+		.ident		= "apu6",
-+		.matches	= {
-+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
-+			DMI_MATCH(DMI_BOARD_NAME, "apu6")
-+		},
-+		.driver_data	= (void *)&board_apu2,
-+	},
- 	{}
- };
- 
-@@ -249,7 +335,7 @@ static int __init apu_board_init(void)
- 
- 	id = dmi_first_match(apu_gpio_dmi_table);
- 	if (!id) {
--		pr_err("failed to detect APU board via DMI\n");
-+		pr_err("No APU board detected via DMI\n");
- 		return -ENODEV;
- 	}
- 
-@@ -288,8 +374,12 @@ module_init(apu_board_init);
- module_exit(apu_board_exit);
- 
- MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
--MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver");
-+MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver");
- MODULE_LICENSE("GPL");
- MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table);
- MODULE_ALIAS("platform:pcengines-apuv2");
-+MODULE_ALIAS("platform:pcengines-apuv3");
-+MODULE_ALIAS("platform:pcengines-apuv4");
-+MODULE_ALIAS("platform:pcengines-apuv5");
-+MODULE_ALIAS("platform:pcengines-apuv6");
- MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled");
diff --git a/target/linux/zynq/Makefile b/target/linux/zynq/Makefile
index f48b58e598..90e49df878 100644
--- a/target/linux/zynq/Makefile
+++ b/target/linux/zynq/Makefile
@@ -18,7 +18,7 @@ define Target/Description
 	Build firmware image for Zynq 7000 SoC devices.
 endef
 
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
 
 include $(INCLUDE_DIR)/target.mk
 
diff --git a/target/linux/zynq/config-5.15 b/target/linux/zynq/config-5.15
deleted file mode 100644
index d1d7392440..0000000000
--- a/target/linux/zynq/config-5.15
+++ /dev/null
@@ -1,552 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ALTERA_FREEZE_BRIDGE is not set
-# CONFIG_ALTERA_PR_IP_CORE is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
-# CONFIG_ARCH_VEXPRESS_SPC is not set
-CONFIG_ARCH_ZYNQ=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_PL172_MPMC is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ARM_ZYNQ_CPUIDLE=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_AXI_DMAC is not set
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CADENCE_TTC_TIMER=y
-CONFIG_CADENCE_WATCHDOG=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_VERSATILE=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_SI570=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_E1000E=y
-CONFIG_EDAC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_LEGACY_SYSFS=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EDAC_SYNOPSYS is not set
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_XILINX is not set
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FPGA=y
-CONFIG_FPGA_BRIDGE=y
-# CONFIG_FPGA_DFL is not set
-# CONFIG_FPGA_MGR_ALTERA_CVP is not set
-# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
-# CONFIG_FPGA_MGR_ICE40_SPI is not set
-# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
-# CONFIG_FPGA_MGR_XILINX_SPI is not set
-CONFIG_FPGA_MGR_ZYNQ_FPGA=y
-CONFIG_FPGA_REGION=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_ZYNQ=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CADENCE=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_ICST=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_SPARSEKMAP=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_CAMERA=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_TRANSIENT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_GPIO is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_VEXPRESS_SYSREG=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODULE_STRIPPED is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_FOCALTECH=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-CONFIG_NLS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-# CONFIG_OF_FPGA_REGION is not set
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PCI=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_ZYNQ=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PL330_DMA=y
-# CONFIG_PL353_SMC is not set
-CONFIG_PLAT_VERSATILE=y
-CONFIG_PM=y
-CONFIG_PMBUS=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_R8169=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VEXPRESS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_ZYNQ=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_SENSORS_PMBUS=y
-CONFIG_SENSORS_UCD9000=y
-CONFIG_SENSORS_UCD9200=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CADENCE=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_XILINX=y
-CONFIG_SPI_ZYNQ_QSPI=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UIO=y
-# CONFIG_UIO_AEC is not set
-# CONFIG_UIO_CIF is not set
-# CONFIG_UIO_DMEM_GENIRQ is not set
-# CONFIG_UIO_MF624 is not set
-# CONFIG_UIO_NETX is not set
-# CONFIG_UIO_PCI_GENERIC is not set
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_UIO_PRUSS is not set
-# CONFIG_UIO_SERCOS3 is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_XILINX=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OTG=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USE_OF=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VITESSE_PHY=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XILINX_EMACLITE=y
-# CONFIG_XILINX_INTC is not set
-# CONFIG_XILINX_PR_DECOUPLER is not set
-CONFIG_XILINX_WATCHDOG=y
-CONFIG_XILINX_XADC=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/zynq/config-6.1 b/target/linux/zynq/config-6.1
new file mode 100644
index 0000000000..b6318a776c
--- /dev/null
+++ b/target/linux/zynq/config-6.1
@@ -0,0 +1,566 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALTERA_FREEZE_BRIDGE is not set
+# CONFIG_ALTERA_PR_IP_CORE is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
+# CONFIG_ARCH_VEXPRESS_SPC is not set
+CONFIG_ARCH_ZYNQ=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ARM_ZYNQ_CPUIDLE=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXI_DMAC is not set
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CADENCE_TTC_TIMER=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_ICST=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_SI570=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000E=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC_SYNOPSYS is not set
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CMDLINE=y
+# CONFIG_FB_XILINX is not set
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FPGA=y
+CONFIG_FPGA_BRIDGE=y
+# CONFIG_FPGA_DFL is not set
+# CONFIG_FPGA_MGR_ALTERA_CVP is not set
+# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
+# CONFIG_FPGA_MGR_ICE40_SPI is not set
+# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
+# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set
+# CONFIG_FPGA_MGR_XILINX_SPI is not set
+CONFIG_FPGA_MGR_ZYNQ_FPGA=y
+CONFIG_FPGA_REGION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CADENCE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_STRIPPED is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+CONFIG_NLS=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+# CONFIG_OF_FPGA_REGION is not set
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PCI=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_ZYNQ=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL330_DMA=y
+# CONFIG_PL353_SMC is not set
+CONFIG_PLAT_VERSATILE=y
+CONFIG_PM=y
+CONFIG_PMBUS=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_R8169=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_ZYNQ=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_SENSORS_PMBUS=y
+CONFIG_SENSORS_UCD9000=y
+CONFIG_SENSORS_UCD9200=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPI_ZYNQ_QSPI=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UIO=y
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_XILINX=y
+CONFIG_USB_HID=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USE_OF=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XILINX_EMACLITE=y
+# CONFIG_XILINX_PR_DECOUPLER is not set
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XILINX_XADC=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y