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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-04-07 10:18:43 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-09 06:27:00 +0000 |
| commit | edc6da2de9cc491a03cfa335879829efb0446b74 (patch) | |
| tree | e18d303975b57581b1dc578fe979bb75ecee353c | |
| parent | 09446778e899fa923895f5690481a509479c6641 (diff) | |
| download | coreboot-edc6da2de9cc491a03cfa335879829efb0446b74.tar.gz coreboot-edc6da2de9cc491a03cfa335879829efb0446b74.tar.bz2 coreboot-edc6da2de9cc491a03cfa335879829efb0446b74.zip | |
mb/intel/adlrvp: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.
BUG=None
TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0)
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cade987313d5..57d78de9ce94 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -12,6 +12,9 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # Enable HECI1 interface + register "HeciEnabled" = "1" + # FSP configuration # Enable CNVi BT |