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| author | Iru Cai <mytbk920423@gmail.com> | 2020-07-30 22:57:09 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:16:19 +0000 |
| commit | 9c20ad6da2cb5322afc389373bc27185c38fed98 (patch) | |
| tree | b675d108a5798ba3f51cb45fb626c65639fd6865 /src/cpu/intel/common/fsb.c | |
| parent | 2aedc9776a3c2ef99c8ca4f1ed836c3f7f6821d6 (diff) | |
| download | coreboot-9c20ad6da2cb5322afc389373bc27185c38fed98.tar.gz coreboot-9c20ad6da2cb5322afc389373bc27185c38fed98.tar.bz2 coreboot-9c20ad6da2cb5322afc389373bc27185c38fed98.zip | |
cpu/intel/common/fsb.c: add Crystal Well support
Without this change, there will be no console output when using a
Crystal Well CPU.
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS.
Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel/common/fsb.c')
| -rw-r--r-- | src/cpu/intel/common/fsb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 7772171f0dc3..3d46bbc4b94a 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -45,6 +45,7 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; |