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| author | Tony Huang <tony-huang@quanta.corp-partner.google.com> | 2022-07-07 17:57:55 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-12 00:48:52 +0000 |
| commit | 6cfe2624a24eb07279cda6356b0195539e1d67d3 (patch) | |
| tree | 351c49c2de02abb7d5b3a8297300251bef694dc2 /src/mainboard/google/brya/variants/agah/overridetree.cb | |
| parent | e3ed9cacaa2b372a3efce95308d15aea3806fbf9 (diff) | |
| download | coreboot-6cfe2624a24eb07279cda6356b0195539e1d67d3.tar.gz coreboot-6cfe2624a24eb07279cda6356b0195539e1d67d3.tar.bz2 coreboot-6cfe2624a24eb07279cda6356b0195539e1d67d3.zip | |
mb/google/brya/var/agah: Disable thunderbolt interface
Agah doesn't support TBT interface so disable it in devicetree, for
fitimage configuration is at chrome-internal:4846869.
BUG=b:224423318
TEST=Build and check DUT boots.
Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/agah/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/overridetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 007b188ff090..550dab60fbd8 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -59,6 +59,12 @@ chip soc/intel/alderlake }" device domain 0 on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref pcie4_0 on # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ |