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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-03-17 10:02:54 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-21 11:19:21 +0000 |
| commit | fb4fdac64cfe05c9642cd93129dbbf23dde4ac51 (patch) | |
| tree | 790c11309cf66c926171b8bd03627c84bf0335ab /src/mainboard/siemens | |
| parent | fd4f8911c12cb28467054eb06896bae1e0337df0 (diff) | |
| download | coreboot-fb4fdac64cfe05c9642cd93129dbbf23dde4ac51.tar.gz coreboot-fb4fdac64cfe05c9642cd93129dbbf23dde4ac51.tar.bz2 coreboot-fb4fdac64cfe05c9642cd93129dbbf23dde4ac51.zip | |
mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1
Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3)
and #5 (00:1c.4), the speed must be limit to Gen 1.
BUG=none
TEST=RX signal measured with oscilloscope
Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/mainboard/siemens')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 1bf99fd8377e..52da98e2e276 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -74,6 +74,10 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[3]" = "true" register "PcieRpLtrDisable[4]" = "true" + # Determines PCIe root port speed + register "PcieRpPcieSpeed[3]" = "1" + register "PcieRpPcieSpeed[4]" = "1" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" |